usb: dwc3-msm: Simplify OTG_STATE_UNDEFINED handling
In commit 48924e2fe107 ("dwc3: Reset USB controller/PHY after psy
connect indication at bootup") the controller initialization path
was removed from dwc3_msm_probe() and is deferred to when actually
needed, which is when beginning peripheral or host mode. This was
to optimize for the HVDCP charger already-connected case in which
case we want to avoid performing controller initialization which
can disrupt D+/D- linestate.
As part of that change, the OTG_STATE_UNDEFINED state was made
to be the entry point for starting controller initialization.
However, apart from that, the handling is identical to B_IDLE_STATE,
and therefore could be consolidated. And now that charger driver
only notifies us when SDP or CDP types, but not when DCP/HVDCP are
connected, the code can be simplified by removing the duplicate code
between dwc3_initialize() and dwc3_msm_resume().
Change-Id: Ife749c864284864098bcbcbdbda096d05397c60e
Signed-off-by: Jack Pham <jackp@codeaurora.org>
This commit is contained in:
Jack Pham
David Keitel
parent
40a697724b
commit
b885707413
1 changed files with 41 additions and 116 deletions
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@ -1717,6 +1717,13 @@ static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc)
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clk_disable_unprepare(mdwc->cfg_ahb_clk);
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}
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if (!mdwc->init) {
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dbg_event(0xFF, "dwc3 init",
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atomic_read(&mdwc->dev->power.usage_count));
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dwc3_core_pre_init(dwc);
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mdwc->init = true;
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}
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dwc3_core_init(dwc);
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/* Re-configure event buffers */
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dwc3_event_buffers_setup(dwc);
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@ -1985,11 +1992,16 @@ static int dwc3_msm_resume(struct dwc3_msm *mdwc)
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/* Recover from controller power collapse */
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if (mdwc->lpm_flags & MDWC3_POWER_COLLAPSE) {
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u32 tmp;
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dev_dbg(mdwc->dev, "%s: exit power collapse\n", __func__);
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dwc3_msm_power_collapse_por(mdwc);
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/* Re-enable IN_P3 event */
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/* Get initial P3 status and enable IN_P3 event */
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tmp = dwc3_msm_read_reg_field(mdwc->base,
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DWC3_GDBGLTSSM, DWC3_GDBGLTSSM_LINKSTATE_MASK);
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atomic_set(&mdwc->in_p3, tmp == DWC3_LINK_STATE_U3);
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dwc3_msm_write_reg_field(mdwc->base, PWR_EVNT_IRQ_MASK_REG,
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PWR_EVNT_POWERDOWN_IN_P3_MASK, 1);
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@ -2069,15 +2081,6 @@ static void dwc3_ext_event_notify(struct dwc3_msm *mdwc)
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clear_bit(B_SUSPEND, &mdwc->inputs);
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}
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if (!mdwc->init) {
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mdwc->init = true;
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pm_runtime_set_autosuspend_delay(mdwc->dev, 1000);
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pm_runtime_use_autosuspend(mdwc->dev);
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if (!work_busy(&mdwc->sm_work.work))
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schedule_delayed_work(&mdwc->sm_work, 0);
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return;
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}
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schedule_delayed_work(&mdwc->sm_work, 0);
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}
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@ -2497,20 +2500,14 @@ static int dwc3_msm_probe(struct platform_device *pdev)
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}
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}
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/*
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* Some platforms have a special interrupt line for indicating resume
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* while in low power mode, when clocks are disabled.
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*/
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mdwc->pwr_event_irq = platform_get_irq_byname(pdev, "pwr_event_irq");
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if (mdwc->pwr_event_irq < 0) {
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dev_err(&pdev->dev, "pget_irq for pwr_event_irq failed\n");
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ret = -EINVAL;
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goto err;
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} else {
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/*
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* enable pwr event irq early during PM resume to meet bus
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* resume timeline from usb device
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*/
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/* will be enabled in dwc3_msm_resume() */
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irq_set_status_flags(mdwc->pwr_event_irq, IRQ_NOAUTOEN);
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ret = devm_request_threaded_irq(&pdev->dev, mdwc->pwr_event_irq,
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msm_dwc3_pwr_irq,
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msm_dwc3_pwr_irq_thread,
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@ -2701,8 +2698,18 @@ static int dwc3_msm_probe(struct platform_device *pdev)
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if (cpu_to_affin)
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register_cpu_notifier(&mdwc->dwc3_cpu_notifier);
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/*
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* Clocks and regulators will not be turned on until the first time
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* runtime PM resume is called. This is to allow for booting up with
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* charger already connected so as not to disturb PHY line states.
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*/
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mdwc->lpm_flags = MDWC3_POWER_COLLAPSE | MDWC3_SS_PHY_SUSPEND;
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atomic_set(&dwc->in_lpm, 1);
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pm_runtime_set_suspended(mdwc->dev);
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pm_runtime_set_autosuspend_delay(mdwc->dev, 1000);
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pm_runtime_use_autosuspend(mdwc->dev);
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pm_runtime_enable(mdwc->dev);
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device_init_wakeup(mdwc->dev, 1);
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pm_stay_awake(mdwc->dev);
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if (of_property_read_bool(node, "qcom,disable-dev-mode-pm"))
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pm_runtime_get_noresume(mdwc->dev);
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@ -3053,52 +3060,6 @@ psy_error:
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}
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static void dwc3_initialize(struct dwc3_msm *mdwc)
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{
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u32 tmp;
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int ret;
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struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3);
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dbg_event(0xFF, "Initialized Start",
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atomic_read(&mdwc->dev->power.usage_count));
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if (mdwc->bus_perf_client) {
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mdwc->bus_vote = 1;
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schedule_work(&mdwc->bus_vote_w);
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}
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/* enable USB GDSC */
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dwc3_msm_config_gdsc(mdwc, 1);
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/* enable all clocks */
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ret = clk_prepare_enable(mdwc->xo_clk);
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clk_prepare_enable(mdwc->iface_clk);
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clk_prepare_enable(mdwc->core_clk);
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clk_prepare_enable(mdwc->sleep_clk);
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clk_prepare_enable(mdwc->utmi_clk);
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if (mdwc->bus_aggr_clk)
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clk_prepare_enable(mdwc->bus_aggr_clk);
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/* Perform controller GCC reset */
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dwc3_msm_link_clk_reset(mdwc, 1);
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msleep(20);
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dwc3_msm_link_clk_reset(mdwc, 0);
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/*
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* Get core configuration and initialized
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* Set Event buffers
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* Reset both USB PHYs and initialized
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*/
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dwc3_core_pre_init(dwc);
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/* Get initial P3 status and enable IN_P3 event */
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tmp = dwc3_msm_read_reg_field(mdwc->base,
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DWC3_GDBGLTSSM, DWC3_GDBGLTSSM_LINKSTATE_MASK);
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atomic_set(&mdwc->in_p3, tmp == DWC3_LINK_STATE_U3);
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dwc3_msm_write_reg_field(mdwc->base, PWR_EVNT_IRQ_MASK_REG,
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PWR_EVNT_POWERDOWN_IN_P3_MASK, 1);
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}
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/**
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* dwc3_otg_sm_work - workqueue function.
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*
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@ -3130,57 +3091,21 @@ static void dwc3_otg_sm_work(struct work_struct *w)
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/* Check OTG state */
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switch (mdwc->otg_state) {
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case OTG_STATE_UNDEFINED:
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if (!test_bit(ID, &mdwc->inputs)) {
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dbg_event(0xFF, "undef_host", 0);
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atomic_set(&dwc->in_lpm, 0);
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pm_runtime_set_active(mdwc->dev);
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pm_runtime_enable(mdwc->dev);
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pm_runtime_get_noresume(mdwc->dev);
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dwc3_initialize(mdwc);
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mdwc->otg_state = OTG_STATE_A_HOST;
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ret = dwc3_otg_start_host(mdwc, 1);
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pm_runtime_put_noidle(mdwc->dev);
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if (ret != -EPROBE_DEFER)
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return;
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/*
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* regulator_get for VBUS may fail with -EPROBE_DEFER.
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* Set the state as A_IDLE which will re-schedule
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* sm_work after 1sec and call start_host again.
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*/
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mdwc->otg_state = OTG_STATE_A_IDLE;
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work = 1;
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/* Do nothing if no cable connected */
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if (test_bit(ID, &mdwc->inputs) &&
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!test_bit(B_SESS_VLD, &mdwc->inputs))
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break;
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}
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if (test_bit(B_SESS_VLD, &mdwc->inputs)) {
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dev_dbg(mdwc->dev, "b_sess_vld\n");
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dbg_event(0xFF, "undef_b_sess_vld", 0);
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atomic_set(&dwc->in_lpm, 0);
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pm_runtime_set_active(mdwc->dev);
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pm_runtime_enable(mdwc->dev);
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pm_runtime_get_noresume(mdwc->dev);
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dwc3_initialize(mdwc);
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dwc3_otg_start_peripheral(mdwc, 1);
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mdwc->otg_state = OTG_STATE_B_PERIPHERAL;
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dbg_event(0xFF, "Undef SDP",
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atomic_read(&mdwc->dev->power.usage_count));
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break;
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}
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if (!test_bit(B_SESS_VLD, &mdwc->inputs)) {
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dbg_event(0xFF, "undef_!b_sess_vld", 0);
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atomic_set(&dwc->in_lpm, 0);
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pm_runtime_set_active(mdwc->dev);
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pm_runtime_enable(mdwc->dev);
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pm_runtime_get_noresume(mdwc->dev);
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dwc3_initialize(mdwc);
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pm_runtime_put_sync(mdwc->dev);
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dbg_event(0xFF, "Undef NoUSB",
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atomic_read(&mdwc->dev->power.usage_count));
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mdwc->otg_state = OTG_STATE_B_IDLE;
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}
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break;
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dbg_event(0xFF, "Exit UNDEF", 0);
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/*
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* The first call to msm_resume will enable this IRQ which
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* needs to first be disabled else it will be unbalanced.
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*/
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if (dwc->irq)
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disable_irq(dwc->irq);
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mdwc->otg_state = OTG_STATE_B_IDLE;
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/* fall-through */
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case OTG_STATE_B_IDLE:
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if (!test_bit(ID, &mdwc->inputs)) {
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dev_dbg(mdwc->dev, "!id\n");
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@ -3202,7 +3127,7 @@ static void dwc3_otg_sm_work(struct work_struct *w)
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break;
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} else {
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dwc3_msm_gadget_vbus_draw(mdwc, 0);
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dev_dbg(mdwc->dev, "No device, allowing suspend\n");
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dev_dbg(mdwc->dev, "Cable disconnected\n");
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}
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break;
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@ -3218,7 +3143,7 @@ static void dwc3_otg_sm_work(struct work_struct *w)
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* OTG_STATE_B_IDLE state
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*/
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pm_runtime_put_sync(mdwc->dev);
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dbg_event(0xFF, "BPER psync",
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dbg_event(0xFF, "!BSV psync",
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atomic_read(&mdwc->dev->power.usage_count));
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work = 1;
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} else if (test_bit(B_SUSPEND, &mdwc->inputs) &&
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@ -3254,7 +3179,7 @@ static void dwc3_otg_sm_work(struct work_struct *w)
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* OTG_STATE_B_PERIPHERAL state.
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*/
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pm_runtime_get_sync(mdwc->dev);
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dbg_event(0xFF, "SUSP gsync",
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dbg_event(0xFF, "!SUSP gsync",
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atomic_read(&mdwc->dev->power.usage_count));
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}
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break;
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