ARM: shmobile: r8a7790: Add VIN clock support
This adds VIN[0-3] clock support to R8A7790 SoC. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> [horms+renesas@verge.net.au: manually applied] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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1 changed files with 9 additions and 0 deletions
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@ -197,6 +197,7 @@ enum {
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MSTP931, MSTP930, MSTP929, MSTP928,
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MSTP917,
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MSTP813,
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MSTP811, MSTP810, MSTP809, MSTP808,
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MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
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MSTP717, MSTP716,
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MSTP704,
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@ -226,6 +227,10 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
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[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
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[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
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[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
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[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
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[MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
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[MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 8, MSTPSR8, 0), /* VIN3 */
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[MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
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[MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
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[MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
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@ -312,6 +317,10 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
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CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
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CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
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CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
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CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
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CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
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CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
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CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
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CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
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CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
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