msm: camera: isp: Ignore bus error from RDI write master

Bus error can be generated on RDI write master even if there
is no data sent on it. This is not actually an error hence
ignore it.

CRs-Fixed: 1098568
Change-Id: I8dc24f3c4926f008d114778c890ad2c2902f84b9
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
This commit is contained in:
Shubhraprakash Das 2016-12-02 17:53:31 -08:00
parent f230f0f67b
commit b9a96eb2e5
9 changed files with 59 additions and 6 deletions

View file

@ -243,6 +243,10 @@ struct msm_vfe_core_ops {
int (*start_fetch_eng_multi_pass)(struct vfe_device *vfe_dev,
void *arg);
void (*set_halt_restart_mask)(struct vfe_device *vfe_dev);
void (*set_bus_err_ign_mask)(struct vfe_device *vfe_dev,
int wm, int enable);
void (*get_bus_err_mask)(struct vfe_device *vfe_dev,
uint32_t *bus_err, uint32_t *irq_status1);
};
struct msm_vfe_stats_ops {
@ -786,6 +790,8 @@ struct vfe_device {
/* irq info */
uint32_t irq0_mask;
uint32_t irq1_mask;
uint32_t bus_err_ign_mask;
};
struct vfe_parent_device {

View file

@ -1474,6 +1474,8 @@ struct msm_vfe_hardware_info vfe32_hw_info = {
.is_module_cfg_lock_needed =
msm_vfe32_is_module_cfg_lock_needed,
.ahb_clk_cfg = NULL,
.set_bus_err_ign_mask = NULL,
.get_bus_err_mask = NULL,
},
.stats_ops = {
.get_stats_idx = msm_vfe32_get_stats_idx,

View file

@ -2263,6 +2263,8 @@ struct msm_vfe_hardware_info vfe40_hw_info = {
msm_vfe40_start_fetch_engine_multi_pass,
.set_halt_restart_mask =
msm_vfe40_set_halt_restart_mask,
.set_bus_err_ign_mask = NULL,
.get_bus_err_mask = NULL,
},
.stats_ops = {
.get_stats_idx = msm_vfe40_get_stats_idx,

View file

@ -1869,6 +1869,8 @@ struct msm_vfe_hardware_info vfe44_hw_info = {
.ahb_clk_cfg = NULL,
.set_halt_restart_mask =
msm_vfe44_set_halt_restart_mask,
.set_bus_err_ign_mask = NULL,
.get_bus_err_mask = NULL,
},
.stats_ops = {
.get_stats_idx = msm_vfe44_get_stats_idx,

View file

@ -1945,6 +1945,8 @@ struct msm_vfe_hardware_info vfe46_hw_info = {
.ahb_clk_cfg = NULL,
.set_halt_restart_mask =
msm_vfe46_set_halt_restart_mask,
.set_bus_err_ign_mask = NULL,
.get_bus_err_mask = NULL,
},
.stats_ops = {
.get_stats_idx = msm_vfe46_get_stats_idx,

View file

@ -2858,6 +2858,8 @@ struct msm_vfe_hardware_info vfe47_hw_info = {
msm_vfe47_start_fetch_engine_multi_pass,
.set_halt_restart_mask =
msm_vfe47_set_halt_restart_mask,
.set_bus_err_ign_mask = NULL,
.get_bus_err_mask = NULL,
},
.stats_ops = {
.get_stats_idx = msm_vfe47_get_stats_idx,

View file

@ -241,6 +241,25 @@ static void msm_vfe48_put_regulators(struct vfe_device *vfe_dev)
vfe_dev->vfe_num_regulators = 0;
}
static void msm_vfe48_get_bus_err_mask(struct vfe_device *vfe_dev,
uint32_t *bus_err, uint32_t *irq_status1)
{
*bus_err = msm_camera_io_r(vfe_dev->vfe_base + 0xC94);
*bus_err &= ~vfe_dev->bus_err_ign_mask;
if (*bus_err == 0)
*irq_status1 &= ~(1 << 4);
}
static void msm_vfe48_set_bus_err_ign_mask(struct vfe_device *vfe_dev,
int wm, int enable)
{
if (enable)
vfe_dev->bus_err_ign_mask |= (1 << wm);
else
vfe_dev->bus_err_ign_mask &= ~(1 << wm);
}
struct msm_vfe_hardware_info vfe48_hw_info = {
.num_iommu_ctx = 1,
.num_iommu_secure_ctx = 0,
@ -315,6 +334,8 @@ struct msm_vfe_hardware_info vfe48_hw_info = {
msm_vfe47_start_fetch_engine_multi_pass,
.set_halt_restart_mask =
msm_vfe47_set_halt_restart_mask,
.set_bus_err_ign_mask = msm_vfe48_set_bus_err_ign_mask,
.get_bus_err_mask = msm_vfe48_get_bus_err_mask,
},
.stats_ops = {
.get_stats_idx = msm_vfe47_get_stats_idx,

View file

@ -430,6 +430,13 @@ static void msm_isp_axi_reserve_wm(struct vfe_device *vfe_dev,
vfe_dev->pdev->id,
stream_info->stream_handle[vfe_idx], j);
stream_info->wm[vfe_idx][i] = j;
/* setup var to ignore bus error from RDI wm */
if (stream_info->stream_src >= RDI_INTF_0) {
if (vfe_dev->hw_info->vfe_ops.core_ops.
set_bus_err_ign_mask)
vfe_dev->hw_info->vfe_ops.core_ops.
set_bus_err_ign_mask(vfe_dev, j, 1);
}
}
}
@ -443,6 +450,13 @@ void msm_isp_axi_free_wm(struct vfe_device *vfe_dev,
for (i = 0; i < stream_info->num_planes; i++) {
axi_data->free_wm[stream_info->wm[vfe_idx][i]] = 0;
axi_data->num_used_wm--;
if (stream_info->stream_src >= RDI_INTF_0) {
if (vfe_dev->hw_info->vfe_ops.core_ops.
set_bus_err_ign_mask)
vfe_dev->hw_info->vfe_ops.core_ops.
set_bus_err_ign_mask(vfe_dev,
stream_info->wm[vfe_idx][i], 0);
}
}
if (stream_info->stream_src <= IDEAL_RAW)
axi_data->num_pix_stream++;

View file

@ -1791,12 +1791,17 @@ static int msm_isp_process_overflow_irq(
uint32_t *irq_status0, uint32_t *irq_status1)
{
uint32_t overflow_mask;
uint32_t bus_err = 0;
/* if there are no active streams - do not start recovery */
if (!vfe_dev->axi_data.num_active_stream)
return 0;
/*Mask out all other irqs if recovery is started*/
if (vfe_dev->hw_info->vfe_ops.core_ops.
get_bus_err_mask)
vfe_dev->hw_info->vfe_ops.core_ops.get_bus_err_mask(
vfe_dev, &bus_err, irq_status1);
/* Mask out all other irqs if recovery is started */
if (atomic_read(&vfe_dev->error_info.overflow_state) != NO_OVERFLOW) {
uint32_t halt_restart_mask0, halt_restart_mask1;
vfe_dev->hw_info->vfe_ops.core_ops.
@ -1808,14 +1813,13 @@ static int msm_isp_process_overflow_irq(
return 0;
}
/*Check if any overflow bit is set*/
/* Check if any overflow bit is set */
vfe_dev->hw_info->vfe_ops.core_ops.
get_overflow_mask(&overflow_mask);
overflow_mask &= *irq_status1;
if (overflow_mask) {
struct msm_isp_event_data error_event;
uint32_t val = 0;
int i;
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
@ -1830,10 +1834,8 @@ static int msm_isp_process_overflow_irq(
*irq_status1 &= ~overflow_mask;
return 0;
}
if (msm_vfe_is_vfe48(vfe_dev))
val = msm_camera_io_r(vfe_dev->vfe_base + 0xC94);
pr_err("%s: vfe %d overflow mask %x, bus_error %x\n",
__func__, vfe_dev->pdev->id, overflow_mask, val);
__func__, vfe_dev->pdev->id, overflow_mask, bus_err);
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
if (!axi_data->free_wm[i])
continue;