From ba1ad633396bafc23cabfea286f14f4930a07d02 Mon Sep 17 00:00:00 2001 From: Sharat Masetty Date: Thu, 6 Apr 2017 15:43:14 +0530 Subject: [PATCH] drm/msm: Re-trigger preemption upon command completion Trigger preemption from the interrupt handler. This allows us to aggressively change ringbuffers especially to lower priority ones and finish working on pending commands. Change-Id: Ic05213f3d02b1bb7400461edd0d19e38d5b01ec2 Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 5b2c7e77771c..32b2c7fab839 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1039,8 +1039,10 @@ static irqreturn_t a5xx_irq(struct msm_gpu *gpu) if (status & A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP) a5xx_gpmu_err_irq(gpu); - if (status & A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) + if (status & A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) { + a5xx_preempt_trigger(gpu); msm_gpu_retire(gpu); + } if (status & A5XX_RBBM_INT_0_MASK_CP_SW) a5xx_preempt_irq(gpu);