drivers: net: xgene: Add 10GbE support with ring manager v2
Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
ed9b7da019
commit
bc1b7c132a
5 changed files with 152 additions and 25 deletions
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@ -102,6 +102,7 @@ enum xgene_enet_rm {
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#define BLOCK_ETH_CSR_OFFSET 0x2000
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#define BLOCK_ETH_CSR_OFFSET 0x2000
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#define BLOCK_ETH_RING_IF_OFFSET 0x9000
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#define BLOCK_ETH_RING_IF_OFFSET 0x9000
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#define BLOCK_ETH_CLKRST_CSR_OFFSET 0xc000
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#define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000
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#define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000
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#define BLOCK_ETH_MAC_OFFSET 0x0000
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#define BLOCK_ETH_MAC_OFFSET 0x0000
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@ -28,6 +28,8 @@
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#define RES_RING_CSR 1
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#define RES_RING_CSR 1
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#define RES_RING_CMD 2
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#define RES_RING_CMD 2
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static const struct of_device_id xgene_enet_of_match[];
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static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
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static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
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{
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{
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struct xgene_enet_raw_desc16 *raw_desc;
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struct xgene_enet_raw_desc16 *raw_desc;
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@ -632,6 +634,25 @@ static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata)
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}
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}
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}
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}
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static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata,
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struct xgene_enet_desc_ring *ring)
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{
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if ((pdata->enet_id == XGENE_ENET2) &&
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(xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) {
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return true;
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}
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return false;
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}
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static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata,
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struct xgene_enet_desc_ring *ring)
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{
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u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift;
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return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift);
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}
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static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring(
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static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring(
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struct net_device *ndev, u32 ring_num,
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struct net_device *ndev, u32 ring_num,
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enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id)
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enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id)
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@ -663,7 +684,18 @@ static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring(
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}
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}
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ring->size = size;
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ring->size = size;
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ring->cmd_base = pdata->ring_cmd_addr + (ring->num << 6);
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if (is_irq_mbox_required(pdata, ring)) {
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ring->irq_mbox_addr = dma_zalloc_coherent(dev, INTR_MBOX_SIZE,
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&ring->irq_mbox_dma, GFP_KERNEL);
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if (!ring->irq_mbox_addr) {
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dma_free_coherent(dev, size, ring->desc_addr,
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ring->dma);
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devm_kfree(dev, ring);
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return NULL;
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}
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}
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ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring);
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ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR;
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ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR;
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ring = pdata->ring_ops->setup(ring);
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ring = pdata->ring_ops->setup(ring);
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netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n",
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netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n",
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@ -677,12 +709,34 @@ static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum)
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return (owner << 6) | (bufnum & GENMASK(5, 0));
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return (owner << 6) | (bufnum & GENMASK(5, 0));
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}
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}
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static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p)
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{
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enum xgene_ring_owner owner;
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if (p->enet_id == XGENE_ENET1) {
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switch (p->phy_mode) {
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case PHY_INTERFACE_MODE_SGMII:
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owner = RING_OWNER_ETH0;
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break;
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default:
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owner = (!p->port_id) ? RING_OWNER_ETH0 :
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RING_OWNER_ETH1;
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break;
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}
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} else {
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owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1;
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}
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return owner;
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}
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static int xgene_enet_create_desc_rings(struct net_device *ndev)
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static int xgene_enet_create_desc_rings(struct net_device *ndev)
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{
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{
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struct xgene_enet_pdata *pdata = netdev_priv(ndev);
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struct xgene_enet_pdata *pdata = netdev_priv(ndev);
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struct device *dev = ndev_to_dev(ndev);
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struct device *dev = ndev_to_dev(ndev);
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struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring;
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struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring;
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struct xgene_enet_desc_ring *buf_pool = NULL;
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struct xgene_enet_desc_ring *buf_pool = NULL;
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enum xgene_ring_owner owner;
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u8 cpu_bufnum = pdata->cpu_bufnum;
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u8 cpu_bufnum = pdata->cpu_bufnum;
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u8 eth_bufnum = pdata->eth_bufnum;
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u8 eth_bufnum = pdata->eth_bufnum;
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u8 bp_bufnum = pdata->bp_bufnum;
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u8 bp_bufnum = pdata->bp_bufnum;
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@ -691,6 +745,7 @@ static int xgene_enet_create_desc_rings(struct net_device *ndev)
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int ret;
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int ret;
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/* allocate rx descriptor ring */
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/* allocate rx descriptor ring */
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owner = xgene_derive_ring_owner(pdata);
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ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++);
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ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++);
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rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
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rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
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RING_CFGSIZE_16KB, ring_id);
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RING_CFGSIZE_16KB, ring_id);
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@ -700,7 +755,8 @@ static int xgene_enet_create_desc_rings(struct net_device *ndev)
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}
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}
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/* allocate buffer pool for receiving packets */
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/* allocate buffer pool for receiving packets */
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ring_id = xgene_enet_get_ring_id(RING_OWNER_ETH0, bp_bufnum++);
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owner = xgene_derive_ring_owner(pdata);
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ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
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buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
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buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
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RING_CFGSIZE_2KB, ring_id);
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RING_CFGSIZE_2KB, ring_id);
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if (!buf_pool) {
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if (!buf_pool) {
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@ -729,7 +785,8 @@ static int xgene_enet_create_desc_rings(struct net_device *ndev)
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pdata->rx_ring = rx_ring;
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pdata->rx_ring = rx_ring;
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/* allocate tx descriptor ring */
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/* allocate tx descriptor ring */
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ring_id = xgene_enet_get_ring_id(RING_OWNER_ETH0, eth_bufnum++);
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owner = xgene_derive_ring_owner(pdata);
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ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++);
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tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
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tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
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RING_CFGSIZE_16KB, ring_id);
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RING_CFGSIZE_16KB, ring_id);
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if (!tx_ring) {
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if (!tx_ring) {
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@ -957,7 +1014,10 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
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pdata->clk = NULL;
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pdata->clk = NULL;
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}
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}
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if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII)
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base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET);
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base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET);
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else
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base_addr = pdata->base_addr;
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pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
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pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
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pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
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pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
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pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
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pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
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@ -1029,6 +1089,7 @@ static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
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break;
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break;
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}
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}
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if (pdata->enet_id == XGENE_ENET1) {
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switch (pdata->port_id) {
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switch (pdata->port_id) {
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case 0:
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case 0:
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pdata->cpu_bufnum = START_CPU_BUFNUM_0;
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pdata->cpu_bufnum = START_CPU_BUFNUM_0;
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@ -1045,8 +1106,27 @@ static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
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default:
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default:
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break;
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break;
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}
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}
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pdata->ring_ops = &xgene_ring1_ops;
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pdata->ring_ops = &xgene_ring1_ops;
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} else {
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switch (pdata->port_id) {
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case 0:
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pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
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pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
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pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
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pdata->ring_num = X2_START_RING_NUM_0;
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break;
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case 1:
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pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1;
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pdata->eth_bufnum = X2_START_ETH_BUFNUM_1;
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pdata->bp_bufnum = X2_START_BP_BUFNUM_1;
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pdata->ring_num = X2_START_RING_NUM_1;
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break;
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default:
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break;
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}
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pdata->rm = RM0;
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pdata->ring_ops = &xgene_ring2_ops;
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}
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}
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}
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static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata)
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static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata)
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@ -1082,6 +1162,7 @@ static int xgene_enet_probe(struct platform_device *pdev)
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struct xgene_enet_pdata *pdata;
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struct xgene_enet_pdata *pdata;
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struct device *dev = &pdev->dev;
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struct device *dev = &pdev->dev;
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struct xgene_mac_ops *mac_ops;
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struct xgene_mac_ops *mac_ops;
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const struct of_device_id *of_id;
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int ret;
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int ret;
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ndev = alloc_etherdev(sizeof(struct xgene_enet_pdata));
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ndev = alloc_etherdev(sizeof(struct xgene_enet_pdata));
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@ -1100,6 +1181,17 @@ static int xgene_enet_probe(struct platform_device *pdev)
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NETIF_F_GSO |
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NETIF_F_GSO |
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NETIF_F_GRO;
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NETIF_F_GRO;
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#ifdef CONFIG_OF
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of_id = of_match_device(xgene_enet_of_match, &pdev->dev);
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if (of_id) {
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pdata->enet_id = (enum xgene_enet_id)of_id->data;
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if (!pdata->enet_id) {
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free_netdev(ndev);
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return -ENODEV;
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}
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}
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#endif
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ret = xgene_enet_get_resources(pdata);
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ret = xgene_enet_get_resources(pdata);
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if (ret)
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if (ret)
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goto err;
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goto err;
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@ -1171,9 +1263,10 @@ MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match);
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#ifdef CONFIG_OF
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#ifdef CONFIG_OF
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static const struct of_device_id xgene_enet_of_match[] = {
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static const struct of_device_id xgene_enet_of_match[] = {
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{.compatible = "apm,xgene-enet",},
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{.compatible = "apm,xgene-enet", .data = (void *)XGENE_ENET1},
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{.compatible = "apm,xgene1-sgenet",},
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{.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1},
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{.compatible = "apm,xgene1-xgenet",},
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{.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1},
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{.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2},
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{},
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{},
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};
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};
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@ -35,6 +35,7 @@
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#include <linux/if_vlan.h>
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#include <linux/if_vlan.h>
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#include <linux/phy.h>
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#include <linux/phy.h>
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#include "xgene_enet_hw.h"
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#include "xgene_enet_hw.h"
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#include "xgene_enet_ring2.h"
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#define XGENE_DRV_VERSION "v1.0"
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#define XGENE_DRV_VERSION "v1.0"
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#define XGENE_ENET_MAX_MTU 1536
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#define XGENE_ENET_MAX_MTU 1536
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#define START_BP_BUFNUM_1 0x2A
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#define START_BP_BUFNUM_1 0x2A
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#define START_RING_NUM_1 264
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#define START_RING_NUM_1 264
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#define X2_START_CPU_BUFNUM_0 0
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#define X2_START_ETH_BUFNUM_0 0
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#define X2_START_BP_BUFNUM_0 0x20
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#define X2_START_RING_NUM_0 0
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#define X2_START_CPU_BUFNUM_1 0xc
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#define X2_START_ETH_BUFNUM_1 0
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#define X2_START_BP_BUFNUM_1 0x20
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#define X2_START_RING_NUM_1 256
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#define IRQ_ID_SIZE 16
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#define IRQ_ID_SIZE 16
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#define XGENE_MAX_TXC_RINGS 1
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#define XGENE_MAX_TXC_RINGS 1
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#define PHY_POLL_LINK_ON (10 * HZ)
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#define PHY_POLL_LINK_ON (10 * HZ)
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#define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
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#define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
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enum xgene_enet_id {
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XGENE_ENET1 = 1,
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XGENE_ENET2
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};
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/* software context of a descriptor ring */
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/* software context of a descriptor ring */
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struct xgene_enet_desc_ring {
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struct xgene_enet_desc_ring {
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struct net_device *ndev;
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struct net_device *ndev;
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@ -124,6 +140,7 @@ struct xgene_enet_pdata {
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int phy_speed;
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int phy_speed;
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struct clk *clk;
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struct clk *clk;
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struct platform_device *pdev;
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struct platform_device *pdev;
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enum xgene_enet_id enet_id;
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struct xgene_enet_desc_ring *tx_ring;
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struct xgene_enet_desc_ring *tx_ring;
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struct xgene_enet_desc_ring *rx_ring;
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struct xgene_enet_desc_ring *rx_ring;
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char *dev_name;
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char *dev_name;
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@ -122,7 +122,6 @@ static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd,
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return true;
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return true;
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}
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}
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static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata,
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static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata,
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u32 rd_addr, u32 *rd_data)
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u32 rd_addr, u32 *rd_data)
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{
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{
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@ -24,6 +24,23 @@
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#define BLOCK_AXG_MAC_OFFSET 0x0800
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#define BLOCK_AXG_MAC_OFFSET 0x0800
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#define BLOCK_AXG_MAC_CSR_OFFSET 0x2000
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#define BLOCK_AXG_MAC_CSR_OFFSET 0x2000
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#define XGENET_SRST_ADDR 0x0000
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#define XGENET_CLKEN_ADDR 0x0008
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#define CSR_CLK BIT(0)
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#define XGENET_CLK BIT(1)
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#define PCS_CLK BIT(3)
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#define AN_REF_CLK BIT(4)
|
||||||
|
#define AN_CLK BIT(5)
|
||||||
|
#define AD_CLK BIT(6)
|
||||||
|
|
||||||
|
#define CSR_RST BIT(0)
|
||||||
|
#define XGENET_RST BIT(1)
|
||||||
|
#define PCS_RST BIT(3)
|
||||||
|
#define AN_REF_RST BIT(4)
|
||||||
|
#define AN_RST BIT(5)
|
||||||
|
#define AD_RST BIT(6)
|
||||||
|
|
||||||
#define AXGMAC_CONFIG_0 0x0000
|
#define AXGMAC_CONFIG_0 0x0000
|
||||||
#define AXGMAC_CONFIG_1 0x0004
|
#define AXGMAC_CONFIG_1 0x0004
|
||||||
#define HSTMACRST BIT(31)
|
#define HSTMACRST BIT(31)
|
||||||
|
|
Loading…
Add table
Reference in a new issue