From 4fce87dd36970f3c87e44b7b6957de3b36cfb170 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Thu, 1 Dec 2016 11:40:03 +0530 Subject: [PATCH] ARM: dts: msm: Add aggre2_snoc_axi_clk handle in msmfalcon USB3 node Add aggre2_snoc_axi_clk handle in USB3 node which is required to be voted from USB driver before enabling USB core clock for msmfalcon. Change-Id: I190233c1fc483f3d519e09784ed19e6c09ccb2bd Signed-off-by: Vijayavardhan Vennapusa --- arch/arm/boot/dts/qcom/msmfalcon-common.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi index b3be67bd8c32..b2bad31d12d4 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi @@ -39,13 +39,15 @@ clocks = <&clock_gcc GCC_USB30_MASTER_CLK>, <&clock_gcc GCC_CFG_NOC_USB3_AXI_CLK>, <&clock_gcc GCC_AGGRE2_USB3_AXI_CLK>, + <&clock_rpmcc RPM_AGGR2_NOC_CLK>, <&clock_gcc GCC_USB30_MOCK_UTMI_CLK>, <&clock_gcc GCC_USB30_SLEEP_CLK>, <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, <&clock_rpmcc CXO_DWC3_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", - "utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo"; + "noc_aggr_clk", "utmi_clk", "sleep_clk", + "cfg_ahb_clk", "xo"; resets = <&clock_gcc GCC_USB_30_BCR>; reset-names = "core_reset";