evie/android_kernel_oneplus_msm8998
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mmc: sdhci-msm-ice: Factor out update config from sdhci_msm_ice_cfg

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Factor out the logic of updating the SDHC ICE config registers
from sdhci_msm_ice_cfg().

For ICE3.0, different set of SDHC ICE registers are need to be updated.
So having this logic in separate functions, we can have logical
separation for ICE2.0 and ICE3.0.

Change-Id: Ib3d3f9701875000985dc9382bdcdf5fb0e872a43
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
This commit is contained in:
Veerabhadrarao Badiganti 2017-01-31 07:33:29 +05:30
parent af883d4db0
commit bd4fadcb01
1 changed files with 35 additions and 27 deletions
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62
drivers/mmc/host/sdhci-msm-ice.c
View file

@ -211,6 +211,39 @@ void sdhci_msm_ice_cfg_reset(struct sdhci_host *host, u32 slot)
host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_3_n + 16 * slot); host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_3_n + 16 * slot);
} }
static
void sdhci_msm_ice_update_cfg(struct sdhci_host *host, u64 lba,
u32 slot, unsigned int bypass, short key_index)
{
unsigned int ctrl_info_val = 0;
/* Configure ICE index */
ctrl_info_val =
(key_index &
MASK_SDHCI_MSM_ICE_CTRL_INFO_KEY_INDEX)
<< OFFSET_SDHCI_MSM_ICE_CTRL_INFO_KEY_INDEX;
/* Configure data unit size of transfer request */
ctrl_info_val |=
(SDHCI_MSM_ICE_TR_DATA_UNIT_512_B &
MASK_SDHCI_MSM_ICE_CTRL_INFO_CDU)
<< OFFSET_SDHCI_MSM_ICE_CTRL_INFO_CDU;
/* Configure ICE bypass mode */
ctrl_info_val |=
(bypass & MASK_SDHCI_MSM_ICE_CTRL_INFO_BYPASS)
<< OFFSET_SDHCI_MSM_ICE_CTRL_INFO_BYPASS;
writel_relaxed((lba & 0xFFFFFFFF),
host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_1_n + 16 * slot);
writel_relaxed(((lba >> 32) & 0xFFFFFFFF),
host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_2_n + 16 * slot);
writel_relaxed(ctrl_info_val,
host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_3_n + 16 * slot);
/* Ensure ICE registers are configured before issuing SDHCI request */
mb();
}
int sdhci_msm_ice_cfg(struct sdhci_host *host, struct mmc_request *mrq, int sdhci_msm_ice_cfg(struct sdhci_host *host, struct mmc_request *mrq,
u32 slot) u32 slot)
{ {
@ -219,7 +252,6 @@ int sdhci_msm_ice_cfg(struct sdhci_host *host, struct mmc_request *mrq,
int err = 0; int err = 0;
struct ice_data_setting ice_set; struct ice_data_setting ice_set;
sector_t lba = 0; sector_t lba = 0;
unsigned int ctrl_info_val = 0;
unsigned int bypass = SDHCI_MSM_ICE_ENABLE_BYPASS; unsigned int bypass = SDHCI_MSM_ICE_ENABLE_BYPASS;
struct request *req; struct request *req;
@ -262,32 +294,8 @@ int sdhci_msm_ice_cfg(struct sdhci_host *host, struct mmc_request *mrq,
ice_set.crypto_data.key_index); ice_set.crypto_data.key_index);
} }
/* Configure ICE index */ sdhci_msm_ice_update_cfg(host, lba, slot, bypass,
ctrl_info_val = ice_set.crypto_data.key_index);
(ice_set.crypto_data.key_index &
MASK_SDHCI_MSM_ICE_CTRL_INFO_KEY_INDEX)
<< OFFSET_SDHCI_MSM_ICE_CTRL_INFO_KEY_INDEX;
/* Configure data unit size of transfer request */
ctrl_info_val |=
(SDHCI_MSM_ICE_TR_DATA_UNIT_512_B &
MASK_SDHCI_MSM_ICE_CTRL_INFO_CDU)
<< OFFSET_SDHCI_MSM_ICE_CTRL_INFO_CDU;
/* Configure ICE bypass mode */
ctrl_info_val |=
(bypass & MASK_SDHCI_MSM_ICE_CTRL_INFO_BYPASS)
<< OFFSET_SDHCI_MSM_ICE_CTRL_INFO_BYPASS;
writel_relaxed((lba & 0xFFFFFFFF),
host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_1_n + 16 * slot);
writel_relaxed(((lba >> 32) & 0xFFFFFFFF),
host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_2_n + 16 * slot);
writel_relaxed(ctrl_info_val,
host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_3_n + 16 * slot);
/* Ensure ICE registers are configured before issuing SDHCI request */
mb();
return 0; return 0;
} }