clk: msm: mdss: add DT support for SSC frequency and PPM values

The SSC frequency and PPM values are currently hardcoded in the
DSI PLL driver. Add DT properties to specify the SSC frequency
and SSC PPM values for DSI SSC feature.

Change-Id: I0faed9f48694f7407c6855b067ffa4510d7e3fdd
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>

Documentation/devicetree/bindings/fb/mdss-pll.txt

@@ -32,6 +32,10 @@ Optional properties:
 - qcom,dsi-pll-ssc-en:	Boolean property to indicate that ssc is enabled.
 - qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread"
 			or "center-spread". Default is "down-spread" if it is not specified.
+- qcom,ssc-frequency-hz:	Integer property to specify the spread frequency
+			to be programmed for the SSC.
+- qcom,ssc-ppm:		Integer property to specify the Parts per Million
+			value of SSC.
 
 - qcom,platform-supply-entries:	A node that lists the elements of the supply. There
 				can be more than one instance of this binding,
@@ -70,8 +74,10 @@ Example:
 		clock-rate = <0>, <0>, <0>;
 
 		qcom,dsi-pll-slave;
-		qcom,dsi-pll-ssc-en:
+		qcom,dsi-pll-ssc-en;
 		qcom,dsi-pll-ssc-mode = "down-spread";
+		qcom,ssc-frequency-hz = <30000>;
+		qcom,ssc-ppm = <5000>;
 
 		qcom,platform-supply-entries {
 			#address-cells = <1>;

drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c

@@ -382,8 +382,8 @@ static void mdss_dsi_pll_8996_input_init(struct mdss_pll_resources *pll,
 	pdb->in.plllock_rng = 0;	/* 0, reg: 0x0488, bit 3 - 4 */
 	pdb->in.ssc_center = pll->ssc_center;/* 0, reg: 0x0494, bit 1 */
 	pdb->in.ssc_adj_period = 37;	/* 37, reg: 0x498, bit 0 - 9 */
-	pdb->in.ssc_spread = 5;		/* 0.005, 5kppm */
-	pdb->in.ssc_freq = 31500;	/* 31.5 khz */
+	pdb->in.ssc_spread = pll->ssc_ppm / 1000;
+	pdb->in.ssc_freq = pll->ssc_freq;
 
 	pdb->in.pll_ie_trim = 4;	/* 4, reg: 0x0400 */
 	pdb->in.pll_ip_trim = 4;	/* 4, reg: 0x0404 */

drivers/clk/msm/mdss/mdss-dsi-pll-8996.c

@@ -465,6 +465,8 @@ int dsi_pll_clock_register_8996(struct platform_device *pdev,
 				struct mdss_pll_resources *pll_res)
 {
 	int rc, ndx;
+	int const ssc_freq_default = 31500; /* default h/w recommended value */
+	int const ssc_ppm_default = 5000; /* default h/w recommended value */
 	struct dsi_pll_db *pdb;
 
 	if (!pdev || !pdev->dev.of_node) {
@@ -511,6 +513,13 @@ int dsi_pll_clock_register_8996(struct platform_device *pdev,
 	clk_ops_gen_mux_dsi.round_rate = parent_round_rate;
 	clk_ops_gen_mux_dsi.set_rate = parent_set_rate;
 
+	if (pll_res->ssc_en) {
+		if (!pll_res->ssc_freq)
+			pll_res->ssc_freq = ssc_freq_default;
+		if (!pll_res->ssc_ppm)
+			pll_res->ssc_ppm = ssc_ppm_default;
+	}
+
 	/* Set client data to mux, div and vco clocks.  */
 	if (pll_res->index == DSI_PLL_1) {
 		dsi1pll_byte_clk_src.priv = pll_res;

drivers/clk/msm/mdss/mdss-pll.c

@@ -236,12 +236,23 @@ static int mdss_pll_probe(struct platform_device *pdev)
 	pll_res->ssc_en = of_property_read_bool(pdev->dev.of_node,
 						"qcom,dsi-pll-ssc-en");
 
-	pll_res->ssc_center = false;
+	if (pll_res->ssc_en) {
+		pr_info("%s: label=%s PLL SSC enabled\n", __func__, label);
 
-	label = of_get_property(pdev->dev.of_node,
-				"qcom,dsi-pll-ssc-mode", NULL);
-	if (label && !strcmp(label, "center-spread"))
-		pll_res->ssc_center = true;
+		rc = of_property_read_u32(pdev->dev.of_node,
+			"qcom,ssc-frequency-hz", &pll_res->ssc_freq);
+
+		rc = of_property_read_u32(pdev->dev.of_node,
+			"qcom,ssc-ppm", &pll_res->ssc_ppm);
+
+		pll_res->ssc_center = false;
+
+		label = of_get_property(pdev->dev.of_node,
+			"qcom,dsi-pll-ssc-mode", NULL);
+
+		if (label && !strcmp(label, "center-spread"))
+			pll_res->ssc_center = true;
+	}
 
 	pll_base_reg = platform_get_resource_byname(pdev,
 						IORESOURCE_MEM, "pll_base");

drivers/clk/msm/mdss/mdss-pll.h

@@ -155,6 +155,8 @@ struct mdss_pll_resources {
 
 	bool ssc_en;	/* share pll with master */
 	bool ssc_center;	/* default is down spread */
+	u32 ssc_freq;
+	u32 ssc_ppm;
 
 	struct mdss_pll_resources *slave;