From 4534a2af58087d33a7fcc4497da72bd7b69fe8d0 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 3 Dec 2014 16:43:16 +1000
Subject: [PATCH 01/86] drm/nouveau/fb: remove some (now) unnecessary hacks
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/subdev/fb/base.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/base.c b/drivers/gpu/drm/nouveau/core/subdev/fb/base.c
index c866148c440f..31869ff30740 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/base.c
@@ -135,8 +135,6 @@ nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
}
- atomic_dec(&ram->parent->refcount);
- atomic_dec(&ram->engine->refcount);
pfb->ram = (void *)ram;
if (!nouveau_mm_initialised(&pfb->vram)) {
From 2f4a58e852d103488fc435f0c1ecbb9a86761579 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 3 Dec 2014 17:07:22 +1000
Subject: [PATCH 02/86] drm/nouveau/subdev: always upcast through
nouveau_subdev()/nouveau_engine()
Has additional safeties for one. For two, needed for an upcoming
commit that removes abuse of nouveau_object.engine.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/include/engine/disp.h | 2 +-
drivers/gpu/drm/nouveau/core/include/engine/fifo.h | 2 +-
drivers/gpu/drm/nouveau/core/include/engine/graph.h | 2 +-
drivers/gpu/drm/nouveau/core/include/engine/perfmon.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/bar.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/bios.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/bus.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/clock.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/devinit.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/fb.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/fuse.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/gpio.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/i2c.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/ibus.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/instmem.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/ltc.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/mc.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/mxm.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/pwr.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/therm.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/timer.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/vm.h | 2 +-
drivers/gpu/drm/nouveau/core/include/subdev/volt.h | 2 +-
23 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/disp.h b/drivers/gpu/drm/nouveau/core/include/engine/disp.h
index fc307f1317ff..626508d8da40 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/disp.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/disp.h
@@ -18,7 +18,7 @@ struct nouveau_disp {
static inline struct nouveau_disp *
nouveau_disp(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_DISP];
+ return (void *)nouveau_engine(obj, NVDEV_ENGINE_DISP);
}
extern struct nouveau_oclass *nv04_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
index 2007453f6fce..c52b939f52f0 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
@@ -85,7 +85,7 @@ struct nouveau_fifo {
static inline struct nouveau_fifo *
nouveau_fifo(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_FIFO];
+ return (void *)nouveau_engine(obj, NVDEV_ENGINE_FIFO);
}
#define nouveau_fifo_create(o,e,c,fc,lc,d) \
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/graph.h b/drivers/gpu/drm/nouveau/core/include/engine/graph.h
index d5055570d01b..d61dcb7d6d5f 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/graph.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/graph.h
@@ -35,7 +35,7 @@ struct nouveau_graph {
static inline struct nouveau_graph *
nouveau_graph(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_GR];
+ return (void *)nouveau_engine(obj, NVDEV_ENGINE_GR);
}
#define nouveau_graph_create(p,e,c,y,d) \
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h b/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h
index 88cc812baaa3..251c8545ca58 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h
@@ -24,7 +24,7 @@ struct nouveau_perfmon {
static inline struct nouveau_perfmon *
nouveau_perfmon(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_PERFMON];
+ return (void *)nouveau_engine(obj, NVDEV_ENGINE_PERFMON);
}
extern struct nouveau_oclass *nv40_perfmon_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h b/drivers/gpu/drm/nouveau/core/include/subdev/bar.h
index 257ddf6d36d4..960e33a30819 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bar.h
@@ -27,7 +27,7 @@ struct nouveau_bar {
static inline struct nouveau_bar *
nouveau_bar(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BAR];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_BAR);
}
extern struct nouveau_oclass nv50_bar_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios.h
index 5bd1ca8cd20d..39528a9f3c20 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios.h
@@ -24,7 +24,7 @@ struct nouveau_bios {
static inline struct nouveau_bios *
nouveau_bios(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_VBIOS];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_VBIOS);
}
u8 nvbios_checksum(const u8 *data, int size);
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bus.h b/drivers/gpu/drm/nouveau/core/include/subdev/bus.h
index 697f7ce70aab..2d40f0c2fdfc 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bus.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bus.h
@@ -18,7 +18,7 @@ struct nouveau_bus {
static inline struct nouveau_bus *
nouveau_bus(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BUS];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_BUS);
}
#define nouveau_bus_create(p, e, o, d) \
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
index 36ed035d4d42..0fd5e4a3a7a2 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
@@ -104,7 +104,7 @@ struct nouveau_clock {
static inline struct nouveau_clock *
nouveau_clock(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_CLOCK];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_CLOCK);
}
struct nouveau_clocks {
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h b/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
index e007a9d44683..b627d5329543 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
@@ -15,7 +15,7 @@ struct nouveau_devinit {
static inline struct nouveau_devinit *
nouveau_devinit(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_DEVINIT];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_DEVINIT);
}
extern struct nouveau_oclass *nv04_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
index 8d0032f15205..889603fbb0cf 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
@@ -80,7 +80,7 @@ nouveau_fb(void *obj)
nv_subidx(obj) == NVDEV_SUBDEV_FB)
return obj;
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_FB];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_FB);
}
extern struct nouveau_oclass *nv04_fb_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h b/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h
index 2b1ddb2a9a7d..cc6b02fec682 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h
@@ -11,7 +11,7 @@ struct nouveau_fuse {
static inline struct nouveau_fuse *
nouveau_fuse(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_FUSE];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_FUSE);
}
#define nouveau_fuse_create(p, e, o, d) \
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h b/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h
index f855140dbcb7..8b60c5de6cb9 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h
@@ -35,7 +35,7 @@ struct nouveau_gpio {
static inline struct nouveau_gpio *
nouveau_gpio(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_GPIO];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_GPIO);
}
extern struct nouveau_oclass *nv10_gpio_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h b/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h
index d94ccacb40bf..a400e67f2d43 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h
@@ -81,7 +81,7 @@ struct nouveau_i2c {
static inline struct nouveau_i2c *
nouveau_i2c(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_I2C];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_I2C);
}
extern struct nouveau_oclass *nv04_i2c_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h b/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h
index 31df634c0fdc..b6387d27ea0c 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h
@@ -11,7 +11,7 @@ struct nouveau_ibus {
static inline struct nouveau_ibus *
nouveau_ibus(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_IBUS];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_IBUS);
}
#define nouveau_ibus_create(p,e,o,d) \
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h b/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h
index c1df26f3230c..4953e6c6c86b 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h
@@ -42,7 +42,7 @@ nouveau_instmem(void *obj)
nv_subidx(obj) == NVDEV_SUBDEV_INSTMEM)
return obj;
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_INSTMEM];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_INSTMEM);
}
extern struct nouveau_oclass *nv04_instmem_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h b/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h
index b909a7363f6b..432717a421d3 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h
@@ -25,7 +25,7 @@ struct nouveau_ltc {
static inline struct nouveau_ltc *
nouveau_ltc(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_LTC];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_LTC);
}
extern struct nouveau_oclass *gf100_ltc_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/mc.h b/drivers/gpu/drm/nouveau/core/include/subdev/mc.h
index 568e4dfc5e9e..af7926f3a93d 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/mc.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/mc.h
@@ -14,7 +14,7 @@ struct nouveau_mc {
static inline struct nouveau_mc *
nouveau_mc(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_MC];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MC);
}
extern struct nouveau_oclass *nv04_mc_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h b/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h
index b93b152cb566..94b8af23c33e 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h
@@ -15,7 +15,7 @@ struct nouveau_mxm {
static inline struct nouveau_mxm *
nouveau_mxm(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_MXM];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MXM);
}
#define nouveau_mxm_create(p,e,o,d) \
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
index f2427bf5aeed..ef57c85405ff 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
@@ -30,7 +30,7 @@ struct nouveau_pwr {
static inline struct nouveau_pwr *
nouveau_pwr(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_PWR];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_PWR);
}
extern struct nouveau_oclass *nva3_pwr_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/therm.h b/drivers/gpu/drm/nouveau/core/include/subdev/therm.h
index a437597dcafc..42f9574a06c9 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/therm.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/therm.h
@@ -47,7 +47,7 @@ struct nouveau_therm {
static inline struct nouveau_therm *
nouveau_therm(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_THERM];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_THERM);
}
#define nouveau_therm_create(p,e,o,d) \
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/timer.h b/drivers/gpu/drm/nouveau/core/include/subdev/timer.h
index db9be803a874..36b5184e35ec 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/timer.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/timer.h
@@ -42,7 +42,7 @@ struct nouveau_timer {
static inline struct nouveau_timer *
nouveau_timer(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_TIMER];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_TIMER);
}
#define nouveau_timer_create(p,e,o,d) \
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h b/drivers/gpu/drm/nouveau/core/include/subdev/vm.h
index c9509039f94b..d56585f1cd8c 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/vm.h
@@ -91,7 +91,7 @@ struct nouveau_vmmgr {
static inline struct nouveau_vmmgr *
nouveau_vmmgr(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_VM];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_VM);
}
#define nouveau_vmmgr_create(p,e,o,i,f,d) \
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/volt.h b/drivers/gpu/drm/nouveau/core/include/subdev/volt.h
index 67db5e58880d..13e9a83ceccc 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/volt.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/volt.h
@@ -29,7 +29,7 @@ struct nouveau_volt {
static inline struct nouveau_volt *
nouveau_volt(void *obj)
{
- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_VOLT];
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_VOLT);
}
#define nouveau_volt_create(p, e, o, d) \
From 587f7a5b7c829bcbb1ce122d8635067ef99021d4 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 3 Dec 2014 12:56:41 +1000
Subject: [PATCH 03/86] drm/nouveau/core: rename subclass.base to
subclass.superclass
Makes things a bit more readable. This is specially important now as
upcoming commits are going to be gradually removing the use of macros
for down-casts, in favour of compile-time checking.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/core/client.c | 2 +-
drivers/gpu/drm/nouveau/core/core/engctx.c | 10 +++++-----
drivers/gpu/drm/nouveau/core/core/gpuobj.c | 4 ++--
drivers/gpu/drm/nouveau/core/core/parent.c | 2 +-
drivers/gpu/drm/nouveau/core/core/subdev.c | 8 ++++----
drivers/gpu/drm/nouveau/core/engine/device/base.c | 2 +-
drivers/gpu/drm/nouveau/core/engine/fifo/base.c | 2 +-
drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c | 2 +-
drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c | 2 +-
drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c | 2 +-
drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c | 4 ++--
drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c | 4 ++--
drivers/gpu/drm/nouveau/core/include/core/client.h | 2 +-
drivers/gpu/drm/nouveau/core/include/core/device.h | 2 +-
drivers/gpu/drm/nouveau/core/include/core/engctx.h | 2 +-
drivers/gpu/drm/nouveau/core/include/core/engine.h | 8 ++++----
drivers/gpu/drm/nouveau/core/include/core/gpuobj.h | 8 ++++----
drivers/gpu/drm/nouveau/core/include/core/namedb.h | 8 ++++----
drivers/gpu/drm/nouveau/core/include/core/parent.h | 6 +++---
drivers/gpu/drm/nouveau/core/include/core/ramht.h | 4 ++--
drivers/gpu/drm/nouveau/core/include/core/subdev.h | 2 +-
drivers/gpu/drm/nouveau/core/include/engine/fifo.h | 14 +++++++-------
drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c | 3 +--
23 files changed, 51 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/core/client.c b/drivers/gpu/drm/nouveau/core/core/client.c
index e962433294c3..acff10387846 100644
--- a/drivers/gpu/drm/nouveau/core/core/client.c
+++ b/drivers/gpu/drm/nouveau/core/core/client.c
@@ -190,7 +190,7 @@ nouveau_client_dtor(struct nouveau_object *object)
nvkm_client_notify_del(client, i);
nouveau_object_ref(NULL, &client->device);
nouveau_handle_destroy(client->root);
- nouveau_namedb_destroy(&client->base);
+ nouveau_namedb_destroy(&client->namedb);
}
static struct nouveau_oclass
diff --git a/drivers/gpu/drm/nouveau/core/core/engctx.c b/drivers/gpu/drm/nouveau/core/core/engctx.c
index 84c71fad2b6c..6b9c728053d0 100644
--- a/drivers/gpu/drm/nouveau/core/core/engctx.c
+++ b/drivers/gpu/drm/nouveau/core/core/engctx.c
@@ -125,10 +125,10 @@ nouveau_engctx_destroy(struct nouveau_engctx *engctx)
if (client->vm)
atomic_dec(&client->vm->engref[nv_engidx(engobj)]);
- if (engctx->base.size)
- nouveau_gpuobj_destroy(&engctx->base);
+ if (engctx->gpuobj.size)
+ nouveau_gpuobj_destroy(&engctx->gpuobj);
else
- nouveau_object_destroy(&engctx->base.base);
+ nouveau_object_destroy(&engctx->gpuobj.object);
}
int
@@ -140,7 +140,7 @@ nouveau_engctx_init(struct nouveau_engctx *engctx)
struct nouveau_subdev *pardev;
int ret;
- ret = nouveau_gpuobj_init(&engctx->base);
+ ret = nouveau_gpuobj_init(&engctx->gpuobj);
if (ret)
return ret;
@@ -186,7 +186,7 @@ nouveau_engctx_fini(struct nouveau_engctx *engctx, bool suspend)
}
nv_debug(parent, "detached %s context\n", subdev->name);
- return nouveau_gpuobj_fini(&engctx->base, suspend);
+ return nouveau_gpuobj_fini(&engctx->gpuobj, suspend);
}
int
diff --git a/drivers/gpu/drm/nouveau/core/core/gpuobj.c b/drivers/gpu/drm/nouveau/core/core/gpuobj.c
index daee87702502..0a9ea1fa9b55 100644
--- a/drivers/gpu/drm/nouveau/core/core/gpuobj.c
+++ b/drivers/gpu/drm/nouveau/core/core/gpuobj.c
@@ -47,7 +47,7 @@ nouveau_gpuobj_destroy(struct nouveau_gpuobj *gpuobj)
if (gpuobj->heap.block_size)
nouveau_mm_fini(&gpuobj->heap);
- nouveau_object_destroy(&gpuobj->base);
+ nouveau_object_destroy(&gpuobj->object);
}
int
@@ -290,7 +290,7 @@ nouveau_gpudup_dtor(struct nouveau_object *object)
{
struct nouveau_gpuobj *gpuobj = (void *)object;
nouveau_object_ref(NULL, &gpuobj->parent);
- nouveau_object_destroy(&gpuobj->base);
+ nouveau_object_destroy(&gpuobj->object);
}
static struct nouveau_oclass
diff --git a/drivers/gpu/drm/nouveau/core/core/parent.c b/drivers/gpu/drm/nouveau/core/core/parent.c
index 30a2911878f8..07a2006a1d78 100644
--- a/drivers/gpu/drm/nouveau/core/core/parent.c
+++ b/drivers/gpu/drm/nouveau/core/core/parent.c
@@ -150,7 +150,7 @@ nouveau_parent_destroy(struct nouveau_parent *parent)
kfree(sclass);
}
- nouveau_object_destroy(&parent->base);
+ nouveau_object_destroy(&parent->object);
}
diff --git a/drivers/gpu/drm/nouveau/core/core/subdev.c b/drivers/gpu/drm/nouveau/core/core/subdev.c
index 2ea5568b6cf5..28157bf57da1 100644
--- a/drivers/gpu/drm/nouveau/core/core/subdev.c
+++ b/drivers/gpu/drm/nouveau/core/core/subdev.c
@@ -38,11 +38,11 @@ nouveau_subdev_reset(struct nouveau_object *subdev)
int
nouveau_subdev_init(struct nouveau_subdev *subdev)
{
- int ret = nouveau_object_init(&subdev->base);
+ int ret = nouveau_object_init(&subdev->object);
if (ret)
return ret;
- nouveau_subdev_reset(&subdev->base);
+ nouveau_subdev_reset(&subdev->object);
return 0;
}
@@ -60,7 +60,7 @@ nouveau_subdev_fini(struct nouveau_subdev *subdev, bool suspend)
nv_mask(subdev, 0x000200, subdev->unit, subdev->unit);
}
- return nouveau_object_fini(&subdev->base, suspend);
+ return nouveau_object_fini(&subdev->object, suspend);
}
int
@@ -74,7 +74,7 @@ nouveau_subdev_destroy(struct nouveau_subdev *subdev)
{
int subidx = nv_hclass(subdev) & 0xff;
nv_device(subdev)->subdev[subidx] = NULL;
- nouveau_object_destroy(&subdev->base);
+ nouveau_object_destroy(&subdev->object);
}
void
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c
index 137e0b0faeae..714a93eb1fd3 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c
@@ -616,7 +616,7 @@ nouveau_device_dtor(struct nouveau_object *object)
if (nv_subdev(device)->mmio)
iounmap(nv_subdev(device)->mmio);
- nouveau_engine_destroy(&device->base);
+ nouveau_engine_destroy(&device->engine);
}
resource_size_t
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c b/drivers/gpu/drm/nouveau/core/engine/fifo/base.c
index ac8375cf4eef..836c6d32e82e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/base.c
@@ -127,7 +127,7 @@ nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *chan)
nouveau_gpuobj_ref(NULL, &chan->pushgpu);
nouveau_object_ref(NULL, (struct nouveau_object **)&chan->pushdma);
- nouveau_namedb_destroy(&chan->base);
+ nouveau_namedb_destroy(&chan->namedb);
}
void
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
index 1931057f9962..6f51ae0daecf 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
@@ -629,7 +629,7 @@ nv04_fifo_init(struct nouveau_object *object)
nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
((priv->ramht->bits - 9) << 16) |
- (priv->ramht->base.addr >> 8));
+ (priv->ramht->gpuobj.addr >> 8));
nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8);
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
index 12d76c8adb23..01fbb11af00d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
@@ -193,7 +193,7 @@ nv17_fifo_init(struct nouveau_object *object)
nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
((priv->ramht->bits - 9) << 16) |
- (priv->ramht->base.addr >> 8));
+ (priv->ramht->gpuobj.addr >> 8));
nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 | 0x00010000);
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
index 9f49c3a24dc6..604cb5286632 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
@@ -314,7 +314,7 @@ nv40_fifo_init(struct nouveau_object *object)
nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
((priv->ramht->bits - 9) << 16) |
- (priv->ramht->base.addr >> 8));
+ (priv->ramht->gpuobj.addr >> 8));
nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
switch (nv_device(priv)->chipset) {
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
index 5d1e86bc244c..403fafc05072 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
@@ -246,7 +246,7 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent,
nv_wo32(base->ramfc, 0x7c, 0x30000001);
nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
(4 << 24) /* SEARCH_FULL */ |
- (chan->ramht->base.node->offset >> 4));
+ (chan->ramht->gpuobj.node->offset >> 4));
bar->flush(bar);
return 0;
}
@@ -310,7 +310,7 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
nv_wo32(base->ramfc, 0x7c, 0x30000001);
nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
(4 << 24) /* SEARCH_FULL */ |
- (chan->ramht->base.node->offset >> 4));
+ (chan->ramht->gpuobj.node->offset >> 4));
bar->flush(bar);
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
index 1f42996b354a..b18386b8a842 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
@@ -219,7 +219,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
nv_wo32(base->ramfc, 0x7c, 0x30000001);
nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
(4 << 24) /* SEARCH_FULL */ |
- (chan->ramht->base.node->offset >> 4));
+ (chan->ramht->gpuobj.node->offset >> 4));
nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
bar->flush(bar);
@@ -292,7 +292,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
nv_wo32(base->ramfc, 0x7c, 0x30000001);
nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
(4 << 24) /* SEARCH_FULL */ |
- (chan->ramht->base.node->offset >> 4));
+ (chan->ramht->gpuobj.node->offset >> 4));
nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
bar->flush(bar);
diff --git a/drivers/gpu/drm/nouveau/core/include/core/client.h b/drivers/gpu/drm/nouveau/core/include/core/client.h
index b0ce9f6680b5..827c4e972ed3 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/client.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/client.h
@@ -4,7 +4,7 @@
#include <core/namedb.h>
struct nouveau_client {
- struct nouveau_namedb base;
+ struct nouveau_namedb namedb;
struct nouveau_handle *root;
struct nouveau_object *device;
char name[32];
diff --git a/drivers/gpu/drm/nouveau/core/include/core/device.h b/drivers/gpu/drm/nouveau/core/include/core/device.h
index 2ec2e50d3676..33b35c487cba 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/device.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/device.h
@@ -64,7 +64,7 @@ enum nv_subdev_type {
};
struct nouveau_device {
- struct nouveau_engine base;
+ struct nouveau_engine engine;
struct list_head head;
struct pci_dev *pdev;
diff --git a/drivers/gpu/drm/nouveau/core/include/core/engctx.h b/drivers/gpu/drm/nouveau/core/include/core/engctx.h
index 2fd48b564c7d..dbc6a3e6dd44 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/engctx.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/engctx.h
@@ -10,7 +10,7 @@
#define NV_ENGCTX(name,var) NV_ENGCTX_(NVDEV_ENGINE_##name, (var))
struct nouveau_engctx {
- struct nouveau_gpuobj base;
+ struct nouveau_gpuobj gpuobj;
struct nouveau_vma vma;
struct list_head head;
unsigned long save;
diff --git a/drivers/gpu/drm/nouveau/core/include/core/engine.h b/drivers/gpu/drm/nouveau/core/include/core/engine.h
index 666d06de77ec..8945755eeec0 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/engine.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/engine.h
@@ -8,7 +8,7 @@
#define NV_ENGINE(name,var) NV_ENGINE_(NVDEV_ENGINE_##name, (var))
struct nouveau_engine {
- struct nouveau_subdev base;
+ struct nouveau_subdev subdev;
struct nouveau_oclass *cclass;
struct nouveau_oclass *sclass;
@@ -40,11 +40,11 @@ nv_engidx(struct nouveau_object *object)
sizeof(**r),(void **)r)
#define nouveau_engine_destroy(p) \
- nouveau_subdev_destroy(&(p)->base)
+ nouveau_subdev_destroy(&(p)->subdev)
#define nouveau_engine_init(p) \
- nouveau_subdev_init(&(p)->base)
+ nouveau_subdev_init(&(p)->subdev)
#define nouveau_engine_fini(p,s) \
- nouveau_subdev_fini(&(p)->base, (s))
+ nouveau_subdev_fini(&(p)->subdev, (s))
int nouveau_engine_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, bool, const char *,
diff --git a/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h b/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h
index b3b9ce4e9d38..c262c2505164 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h
@@ -14,7 +14,7 @@ struct nouveau_vm;
#define NVOBJ_FLAG_HEAP 0x00000004
struct nouveau_gpuobj {
- struct nouveau_object base;
+ struct nouveau_object object;
struct nouveau_object *parent;
struct nouveau_mm_node *node;
struct nouveau_mm heap;
@@ -37,8 +37,8 @@ nv_gpuobj(void *obj)
#define nouveau_gpuobj_create(p,e,c,v,g,s,a,f,d) \
nouveau_gpuobj_create_((p), (e), (c), (v), (g), (s), (a), (f), \
sizeof(**d), (void **)d)
-#define nouveau_gpuobj_init(p) nouveau_object_init(&(p)->base)
-#define nouveau_gpuobj_fini(p,s) nouveau_object_fini(&(p)->base, (s))
+#define nouveau_gpuobj_init(p) nouveau_object_init(&(p)->object)
+#define nouveau_gpuobj_fini(p,s) nouveau_object_fini(&(p)->object, (s))
int nouveau_gpuobj_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, u32 pclass,
struct nouveau_object *, u32 size, u32 align,
@@ -59,7 +59,7 @@ void nouveau_gpuobj_unmap(struct nouveau_vma *);
static inline void
nouveau_gpuobj_ref(struct nouveau_gpuobj *obj, struct nouveau_gpuobj **ref)
{
- nouveau_object_ref(&obj->base, (struct nouveau_object **)ref);
+ nouveau_object_ref(&obj->object, (struct nouveau_object **)ref);
}
void _nouveau_gpuobj_dtor(struct nouveau_object *);
diff --git a/drivers/gpu/drm/nouveau/core/include/core/namedb.h b/drivers/gpu/drm/nouveau/core/include/core/namedb.h
index f5b5fd8e1fc9..98e666b1e375 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/namedb.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/namedb.h
@@ -6,7 +6,7 @@
struct nouveau_handle;
struct nouveau_namedb {
- struct nouveau_parent base;
+ struct nouveau_parent parent;
rwlock_t lock;
struct list_head list;
};
@@ -25,11 +25,11 @@ nv_namedb(void *obj)
nouveau_namedb_create_((p), (e), (c), (v), (s), (m), \
sizeof(**d), (void **)d)
#define nouveau_namedb_init(p) \
- nouveau_parent_init(&(p)->base)
+ nouveau_parent_init(&(p)->parent)
#define nouveau_namedb_fini(p,s) \
- nouveau_parent_fini(&(p)->base, (s))
+ nouveau_parent_fini(&(p)->parent, (s))
#define nouveau_namedb_destroy(p) \
- nouveau_parent_destroy(&(p)->base)
+ nouveau_parent_destroy(&(p)->parent)
int nouveau_namedb_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, u32 pclass,
diff --git a/drivers/gpu/drm/nouveau/core/include/core/parent.h b/drivers/gpu/drm/nouveau/core/include/core/parent.h
index 12da418ec70a..4e2345a5cfdb 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/parent.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/parent.h
@@ -11,7 +11,7 @@ struct nouveau_sclass {
};
struct nouveau_parent {
- struct nouveau_object base;
+ struct nouveau_object object;
struct nouveau_sclass *sclass;
u64 engine;
@@ -40,9 +40,9 @@ nv_parent(void *obj)
nouveau_parent_create_((p), (e), (c), (v), (s), (m), \
sizeof(**d), (void **)d)
#define nouveau_parent_init(p) \
- nouveau_object_init(&(p)->base)
+ nouveau_object_init(&(p)->object)
#define nouveau_parent_fini(p,s) \
- nouveau_object_fini(&(p)->base, (s))
+ nouveau_object_fini(&(p)->object, (s))
int nouveau_parent_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, u32 pclass,
diff --git a/drivers/gpu/drm/nouveau/core/include/core/ramht.h b/drivers/gpu/drm/nouveau/core/include/core/ramht.h
index 47e4cacbca37..e51014337ebe 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/ramht.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/ramht.h
@@ -4,7 +4,7 @@
#include <core/gpuobj.h>
struct nouveau_ramht {
- struct nouveau_gpuobj base;
+ struct nouveau_gpuobj gpuobj;
int bits;
};
@@ -17,7 +17,7 @@ int nouveau_ramht_new(struct nouveau_object *, struct nouveau_object *,
static inline void
nouveau_ramht_ref(struct nouveau_ramht *obj, struct nouveau_ramht **ref)
{
- nouveau_gpuobj_ref(&obj->base, (struct nouveau_gpuobj **)ref);
+ nouveau_gpuobj_ref(&obj->gpuobj, (struct nouveau_gpuobj **)ref);
}
#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/subdev.h b/drivers/gpu/drm/nouveau/core/include/core/subdev.h
index e9632e931616..c24d64ba9a6b 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/subdev.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/subdev.h
@@ -7,7 +7,7 @@
#define NV_SUBDEV(name,var) NV_SUBDEV_(NVDEV_SUBDEV_##name, (var))
struct nouveau_subdev {
- struct nouveau_object base;
+ struct nouveau_object object;
struct mutex mutex;
const char *name;
void __iomem *mmio;
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
index c52b939f52f0..27f05de8fd0a 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
@@ -7,7 +7,7 @@
#include <core/event.h>
struct nouveau_fifo_chan {
- struct nouveau_namedb base;
+ struct nouveau_namedb namedb;
struct nouveau_dmaobj *pushdma;
struct nouveau_gpuobj *pushgpu;
void __iomem *user;
@@ -27,9 +27,9 @@ nouveau_fifo_chan(void *obj)
nouveau_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \
(m), sizeof(**d), (void **)d)
#define nouveau_fifo_channel_init(p) \
- nouveau_namedb_init(&(p)->base)
+ nouveau_namedb_init(&(p)->namedb)
#define nouveau_fifo_channel_fini(p,s) \
- nouveau_namedb_fini(&(p)->base, (s))
+ nouveau_namedb_fini(&(p)->namedb, (s))
int nouveau_fifo_channel_create_(struct nouveau_object *,
struct nouveau_object *,
@@ -48,17 +48,17 @@ void _nouveau_fifo_channel_wr32(struct nouveau_object *, u64, u32);
int _nouveau_fifo_channel_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
struct nouveau_fifo_base {
- struct nouveau_gpuobj base;
+ struct nouveau_gpuobj gpuobj;
};
#define nouveau_fifo_context_create(p,e,c,g,s,a,f,d) \
nouveau_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d))
#define nouveau_fifo_context_destroy(p) \
- nouveau_gpuobj_destroy(&(p)->base)
+ nouveau_gpuobj_destroy(&(p)->gpuobj)
#define nouveau_fifo_context_init(p) \
- nouveau_gpuobj_init(&(p)->base)
+ nouveau_gpuobj_init(&(p)->gpuobj)
#define nouveau_fifo_context_fini(p,s) \
- nouveau_gpuobj_fini(&(p)->base, (s))
+ nouveau_gpuobj_fini(&(p)->gpuobj, (s))
#define _nouveau_fifo_context_dtor _nouveau_gpuobj_dtor
#define _nouveau_fifo_context_init _nouveau_gpuobj_init
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
index 2d0988755530..c0a3389204fa 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
@@ -116,8 +116,7 @@ nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
pte <<= 3;
if (mem->tag) {
- struct nouveau_ltc *ltc =
- nouveau_ltc(vma->vm->vmm->base.base.parent);
+ struct nouveau_ltc *ltc = nouveau_ltc(vma->vm->vmm);
u32 tag = mem->tag->offset + (delta >> 17);
phys |= (u64)tag << (32 + 12);
next |= (u64)1 << (32 + 12);
From 6f5cee5b57b09b260fd61ef116859f0240cff067 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 3 Dec 2014 13:00:30 +1000
Subject: [PATCH 04/86] drm/nouveau/core: rename parent to handle, use parent
for nouveau_parent
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/core/ioctl.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/core/ioctl.c b/drivers/gpu/drm/nouveau/core/core/ioctl.c
index 692aa92dd850..bdfabb4a8dc9 100644
--- a/drivers/gpu/drm/nouveau/core/core/ioctl.c
+++ b/drivers/gpu/drm/nouveau/core/core/ioctl.c
@@ -85,17 +85,17 @@ nvkm_ioctl_sclass(struct nouveau_handle *handle, void *data, u32 size)
}
static int
-nvkm_ioctl_new(struct nouveau_handle *parent, void *data, u32 size)
+nvkm_ioctl_new(struct nouveau_handle *handle, void *data, u32 size)
{
union {
struct nvif_ioctl_new_v0 v0;
} *args = data;
- struct nouveau_client *client = nouveau_client(parent->object);
+ struct nouveau_client *client = nouveau_client(handle->object);
struct nouveau_object *engctx = NULL;
struct nouveau_object *object = NULL;
+ struct nouveau_parent *parent;
struct nouveau_object *engine;
struct nouveau_oclass *oclass;
- struct nouveau_handle *handle;
u32 _handle, _oclass;
int ret;
@@ -111,16 +111,18 @@ nvkm_ioctl_new(struct nouveau_handle *parent, void *data, u32 size)
args->v0.version, _handle, _oclass,
args->v0.route, args->v0.token);
- if (!nv_iclass(parent->object, NV_PARENT_CLASS)) {
- nv_debug(parent->object, "cannot have children (ctor)\n");
+ if (!nv_iclass(handle->object, NV_PARENT_CLASS)) {
+ nv_debug(handle->object, "cannot have children (ctor)\n");
ret = -ENODEV;
goto fail_class;
}
+ parent = nv_parent(handle->object);
+
/* check that parent supports the requested subclass */
- ret = nouveau_parent_sclass(parent->object, _oclass, &engine, &oclass);
+ ret = nouveau_parent_sclass(&parent->object, _oclass, &engine, &oclass);
if (ret) {
- nv_debug(parent->object, "illegal class 0x%04x\n", _oclass);
+ nv_debug(parent, "illegal class 0x%04x\n", _oclass);
goto fail_class;
}
@@ -138,13 +140,13 @@ nvkm_ioctl_new(struct nouveau_handle *parent, void *data, u32 size)
* between the parent and its children (eg. PGRAPH context)
*/
if (engine && nv_engine(engine)->cclass) {
- ret = nouveau_object_ctor(parent->object, engine,
+ ret = nouveau_object_ctor(&parent->object, engine,
nv_engine(engine)->cclass,
data, size, &engctx);
if (ret)
goto fail_engctx;
} else {
- nouveau_object_ref(parent->object, &engctx);
+ nouveau_object_ref(&parent->object, &engctx);
}
/* finally, create new object and bind it to its handle */
@@ -157,7 +159,7 @@ nvkm_ioctl_new(struct nouveau_handle *parent, void *data, u32 size)
if (ret)
goto fail_init;
- ret = nouveau_handle_create(parent->object, parent->name,
+ ret = nouveau_handle_create(&parent->object, handle->name,
_handle, object, &handle);
if (ret)
goto fail_handle;
From 8d90d1ef88ddad5353888e9ecf1d30c75a5effff Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 3 Dec 2014 18:19:58 +1000
Subject: [PATCH 05/86] drm/gf100-/bar: don't fill in bar->alloc until after
all vm setup done
gpuobj has a condition of (bar && bar->alloc) around usage to avoid
some nasty ordering issues (which, i've now been reminded to add a
todo about fixing...) between bar and vm.
The bar->alloc part of the condition isn't currently necessary (it
used to be, another change made bar always NULL where it matters),
so we got lucky. That won't be the case for much longer.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
index 05a278bab247..8320ee0509c3 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
@@ -153,8 +153,6 @@ nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
ret = nvc0_bar_init_vm(priv, &priv->bar[0], 3);
if (ret)
return ret;
- priv->base.alloc = nouveau_bar_alloc;
- priv->base.kmap = nvc0_bar_kmap;
}
/* BAR1 */
@@ -162,6 +160,10 @@ nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret)
return ret;
+ if (has_bar3) {
+ priv->base.alloc = nouveau_bar_alloc;
+ priv->base.kmap = nvc0_bar_kmap;
+ }
priv->base.umap = nvc0_bar_umap;
priv->base.unmap = nvc0_bar_unmap;
priv->base.flush = nv84_bar_flush;
From 95fb6dd72850cb8dd6262aeae3d12fc867dc0b7b Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 3 Dec 2014 18:47:09 +1000
Subject: [PATCH 06/86] drm/nouveau/i2c: fix some blatant abuse
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/subdev/i2c/base.c | 4 ++--
drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
index 0dc605db7ec8..e5f1ffaa6ef0 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
@@ -494,8 +494,8 @@ nouveau_i2c_create_port(struct nouveau_i2c *i2c, int index, u8 type,
oclass = impl->pad_x;
}
- ret = nouveau_object_ctor(NULL, nv_object(i2c), oclass, NULL, pad,
- &parent);
+ ret = nouveau_object_ctor(nv_object(i2c), nv_object(i2c), oclass,
+ NULL, pad, &parent);
if (ret < 0)
return;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h b/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h
index 452ac10c3004..89aea46a7da1 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h
@@ -14,7 +14,7 @@ static inline struct nvkm_i2c_pad *
nvkm_i2c_pad(struct nouveau_i2c_port *port)
{
struct nouveau_object *pad = nv_object(port);
- while (pad->parent)
+ while (!nv_iclass(pad->parent, NV_SUBDEV_CLASS))
pad = pad->parent;
return (void *)pad;
}
From e138c7d8fcb4b40a31346b8ffb955f8f25adba3f Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Fri, 5 Dec 2014 10:55:50 +1000
Subject: [PATCH 07/86] drm/nouveau/core: drop the pointer value in debug
printk output
Makes the output slightly less useful, in that objects with the same
class handle can't be distinguished from each other now.
Upcoming commits will name objects with user-readable strings to fix
this problem.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/core/printk.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/core/printk.c b/drivers/gpu/drm/nouveau/core/core/printk.c
index 03e0060b13da..d6c4d9072a36 100644
--- a/drivers/gpu/drm/nouveau/core/core/printk.c
+++ b/drivers/gpu/drm/nouveau/core/core/printk.c
@@ -65,8 +65,8 @@ nv_printk_(struct nouveau_object *object, int level, const char *fmt, ...)
char obuf[64], *ofmt = "";
if (object->engine) {
- snprintf(obuf, sizeof(obuf), "[0x%08x][%p]",
- nv_hclass(object), object);
+ snprintf(obuf, sizeof(obuf), "[0x%08x]",
+ nv_hclass(object));
ofmt = obuf;
subdev = object->engine;
device = object->engine;
From 0527a04fe837d66f2d1f8606d625a59d4a1c52cd Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Fri, 5 Dec 2014 11:03:18 +1000
Subject: [PATCH 08/86] drm/nouveau/core: prepare printk for NULL engine
pointer on device object tree
The [ SUBDEV] specified in log output will be a bit different for
children of a subdev now. Previously this reports whatever subdev
is specified by object.engine, now it reports the subdev that owns
the object (so, up object.parent somewhere).
Later patches will append object and class identifiers to messages,
which will help clarify where it's coming from.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/core/printk.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/core/printk.c b/drivers/gpu/drm/nouveau/core/core/printk.c
index d6c4d9072a36..1060e3a173fe 100644
--- a/drivers/gpu/drm/nouveau/core/core/printk.c
+++ b/drivers/gpu/drm/nouveau/core/core/printk.c
@@ -60,21 +60,26 @@ nv_printk_(struct nouveau_object *object, int level, const char *fmt, ...)
}
if (object && !nv_iclass(object, NV_CLIENT_CLASS)) {
- struct nouveau_object *device = object;
- struct nouveau_object *subdev = object;
+ struct nouveau_object *device;
+ struct nouveau_object *subdev;
char obuf[64], *ofmt = "";
- if (object->engine) {
+ subdev = object;
+ while (subdev && !nv_iclass(subdev, NV_SUBDEV_CLASS))
+ subdev = subdev->parent;
+ if (!subdev)
+ subdev = object->engine;
+
+ device = subdev;
+ if (device->parent)
+ device = device->parent;
+
+ if (object != subdev) {
snprintf(obuf, sizeof(obuf), "[0x%08x]",
nv_hclass(object));
ofmt = obuf;
- subdev = object->engine;
- device = object->engine;
}
- if (subdev->parent)
- device = subdev->parent;
-
if (level > nv_subdev(subdev)->debug)
return;
From a38f37a7e06b7ea1bca966805e7a0d03191731f4 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Fri, 5 Dec 2014 11:20:19 +1000
Subject: [PATCH 09/86] drm/nouveau/core: uninline subdev/engine/device lookup
functions
These are a tad more complex than a direct cast with paranoia safeties.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/core/engine.c | 9 +++++
drivers/gpu/drm/nouveau/core/core/subdev.c | 8 ++++
.../gpu/drm/nouveau/core/engine/device/base.c | 22 +++++++++++
.../drm/nouveau/core/include/core/device.h | 39 +------------------
.../drm/nouveau/core/include/core/engine.h | 2 +
.../drm/nouveau/core/include/core/subdev.h | 2 +
6 files changed, 44 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/core/engine.c b/drivers/gpu/drm/nouveau/core/core/engine.c
index 1f6954ae9dd3..4835056b0689 100644
--- a/drivers/gpu/drm/nouveau/core/core/engine.c
+++ b/drivers/gpu/drm/nouveau/core/core/engine.c
@@ -26,6 +26,15 @@
#include <core/engine.h>
#include <core/option.h>
+struct nouveau_engine *
+nouveau_engine(void *obj, int sub)
+{
+ struct nouveau_subdev *subdev = nouveau_subdev(obj, sub);
+ if (subdev && nv_iclass(subdev, NV_ENGINE_CLASS))
+ return nv_engine(subdev);
+ return NULL;
+}
+
int
nouveau_engine_create_(struct nouveau_object *parent,
struct nouveau_object *engobj,
diff --git a/drivers/gpu/drm/nouveau/core/core/subdev.c b/drivers/gpu/drm/nouveau/core/core/subdev.c
index 28157bf57da1..edae535406e5 100644
--- a/drivers/gpu/drm/nouveau/core/core/subdev.c
+++ b/drivers/gpu/drm/nouveau/core/core/subdev.c
@@ -27,6 +27,14 @@
#include <core/device.h>
#include <core/option.h>
+struct nouveau_subdev *
+nouveau_subdev(void *obj, int sub)
+{
+ if (nv_device(obj)->subdev[sub])
+ return nv_subdev(nv_device(obj)->subdev[sub]);
+ return NULL;
+}
+
void
nouveau_subdev_reset(struct nouveau_object *subdev)
{
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c
index 714a93eb1fd3..e2da1d4029cd 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c
@@ -508,6 +508,28 @@ nouveau_devobj_ofuncs = {
* nouveau_device: engine functions
*****************************************************************************/
+struct nouveau_device *
+nv_device(void *obj)
+{
+ struct nouveau_object *object = nv_object(obj);
+ struct nouveau_object *device = object;
+
+ if (device->engine)
+ device = device->engine;
+ if (device->parent)
+ device = device->parent;
+
+#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
+ if (unlikely(!nv_iclass(device, NV_SUBDEV_CLASS) ||
+ (nv_hclass(device) & 0xff) != NVDEV_ENGINE_DEVICE)) {
+ nv_assert("BAD CAST -> NvDevice, 0x%08x 0x%08x",
+ nv_hclass(object), nv_hclass(device));
+ }
+#endif
+
+ return (void *)device;
+}
+
static struct nouveau_oclass
nouveau_device_sclass[] = {
{ 0x0080, &nouveau_devobj_ofuncs },
diff --git a/drivers/gpu/drm/nouveau/core/include/core/device.h b/drivers/gpu/drm/nouveau/core/include/core/device.h
index 33b35c487cba..21a055aca513 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/device.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/device.h
@@ -105,44 +105,7 @@ struct nouveau_device {
int nouveau_device_list(u64 *name, int size);
-static inline struct nouveau_device *
-nv_device(void *obj)
-{
- struct nouveau_object *object = nv_object(obj);
- struct nouveau_object *device = object;
-
- if (device->engine)
- device = device->engine;
- if (device->parent)
- device = device->parent;
-
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
- if (unlikely(!nv_iclass(device, NV_SUBDEV_CLASS) ||
- (nv_hclass(device) & 0xff) != NVDEV_ENGINE_DEVICE)) {
- nv_assert("BAD CAST -> NvDevice, 0x%08x 0x%08x",
- nv_hclass(object), nv_hclass(device));
- }
-#endif
-
- return (void *)device;
-}
-
-static inline struct nouveau_subdev *
-nouveau_subdev(void *obj, int sub)
-{
- if (nv_device(obj)->subdev[sub])
- return nv_subdev(nv_device(obj)->subdev[sub]);
- return NULL;
-}
-
-static inline struct nouveau_engine *
-nouveau_engine(void *obj, int sub)
-{
- struct nouveau_subdev *subdev = nouveau_subdev(obj, sub);
- if (subdev && nv_iclass(subdev, NV_ENGINE_CLASS))
- return nv_engine(subdev);
- return NULL;
-}
+struct nouveau_device *nv_device(void *obj);
static inline bool
nv_device_match(struct nouveau_object *object, u16 dev, u16 ven, u16 sub)
diff --git a/drivers/gpu/drm/nouveau/core/include/core/engine.h b/drivers/gpu/drm/nouveau/core/include/core/engine.h
index 8945755eeec0..be04250a1c00 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/engine.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/engine.h
@@ -35,6 +35,8 @@ nv_engidx(struct nouveau_object *object)
return nv_subidx(object);
}
+struct nouveau_engine *nouveau_engine(void *obj, int idx);
+
#define nouveau_engine_create(p,e,c,d,i,f,r) \
nouveau_engine_create_((p), (e), (c), (d), (i), (f), \
sizeof(**r),(void **)r)
diff --git a/drivers/gpu/drm/nouveau/core/include/core/subdev.h b/drivers/gpu/drm/nouveau/core/include/core/subdev.h
index c24d64ba9a6b..d9739aed0150 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/subdev.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/subdev.h
@@ -33,6 +33,8 @@ nv_subidx(struct nouveau_object *object)
return nv_hclass(nv_subdev(object)) & 0xff;
}
+struct nouveau_subdev *nouveau_subdev(void *obj, int idx);
+
#define nouveau_subdev_create(p,e,o,v,s,f,d) \
nouveau_subdev_create_((p), (e), (o), (v), (s), (f), \
sizeof(**d),(void **)d)
From 490d595f321d16f34040836c494d7875eb8f66a4 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Fri, 5 Dec 2014 11:26:23 +1000
Subject: [PATCH 10/86] drm/nouveau/core: fix subdev/engine/device lookup to
not require engine pointer
It's about to not be valid for objects that aren't in the client
object tree.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/core/engine.c | 8 +++----
drivers/gpu/drm/nouveau/core/core/subdev.c | 11 ++++++----
.../gpu/drm/nouveau/core/engine/device/base.c | 22 ++++++++-----------
3 files changed, 20 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/core/engine.c b/drivers/gpu/drm/nouveau/core/core/engine.c
index 4835056b0689..85bf4b3d1fe4 100644
--- a/drivers/gpu/drm/nouveau/core/core/engine.c
+++ b/drivers/gpu/drm/nouveau/core/core/engine.c
@@ -27,11 +27,11 @@
#include <core/option.h>
struct nouveau_engine *
-nouveau_engine(void *obj, int sub)
+nouveau_engine(void *obj, int idx)
{
- struct nouveau_subdev *subdev = nouveau_subdev(obj, sub);
- if (subdev && nv_iclass(subdev, NV_ENGINE_CLASS))
- return nv_engine(subdev);
+ obj = nouveau_subdev(obj, idx);
+ if (obj && nv_iclass(obj, NV_ENGINE_CLASS))
+ return nv_engine(obj);
return NULL;
}
diff --git a/drivers/gpu/drm/nouveau/core/core/subdev.c b/drivers/gpu/drm/nouveau/core/core/subdev.c
index edae535406e5..69ba1482c3f5 100644
--- a/drivers/gpu/drm/nouveau/core/core/subdev.c
+++ b/drivers/gpu/drm/nouveau/core/core/subdev.c
@@ -28,11 +28,14 @@
#include <core/option.h>
struct nouveau_subdev *
-nouveau_subdev(void *obj, int sub)
+nouveau_subdev(void *obj, int idx)
{
- if (nv_device(obj)->subdev[sub])
- return nv_subdev(nv_device(obj)->subdev[sub]);
- return NULL;
+ struct nouveau_object *object = nv_object(obj);
+ while (object && !nv_iclass(object, NV_SUBDEV_CLASS))
+ object = object->parent;
+ if (object == NULL || nv_subidx(object) != idx)
+ object = nv_device(obj)->subdev[idx];
+ return object ? nv_subdev(object) : NULL;
}
void
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c
index e2da1d4029cd..7c0cbcde7b2f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c
@@ -511,22 +511,18 @@ nouveau_devobj_ofuncs = {
struct nouveau_device *
nv_device(void *obj)
{
- struct nouveau_object *object = nv_object(obj);
- struct nouveau_object *device = object;
-
- if (device->engine)
- device = device->engine;
- if (device->parent)
+ struct nouveau_object *device = nv_object(obj);
+ while (device && device->parent)
device = device->parent;
-
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
- if (unlikely(!nv_iclass(device, NV_SUBDEV_CLASS) ||
- (nv_hclass(device) & 0xff) != NVDEV_ENGINE_DEVICE)) {
- nv_assert("BAD CAST -> NvDevice, 0x%08x 0x%08x",
- nv_hclass(object), nv_hclass(device));
+ if (!nv_iclass(device, NV_ENGINE_CLASS)) {
+ device = nv_object(obj)->engine;
+ if (device && device->parent)
+ device = device->parent;
}
+#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
+ if (unlikely(!device))
+ nv_assert("BAD CAST -> NvDevice, 0x%08x\n", nv_hclass(obj));
#endif
-
return (void *)device;
}
From 3532c37017f4666b74acf85b887bc11359b4765c Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Fri, 5 Dec 2014 11:54:50 +1000
Subject: [PATCH 11/86] drm/nouveau/instmem: instobjs may not have an engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/subdev/instmem/base.c | 9 ++++-----
drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c | 10 ++++++----
drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c | 4 ++--
3 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c
index 14706d9842ca..b2dac4a088a1 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c
@@ -31,7 +31,7 @@
void
_nouveau_instobj_dtor(struct nouveau_object *object)
{
- struct nouveau_instmem *imem = (void *)object->engine;
+ struct nouveau_instmem *imem = nouveau_instmem(object);
struct nouveau_instobj *iobj = (void *)object;
mutex_lock(&nv_subdev(imem)->mutex);
@@ -47,7 +47,7 @@ nouveau_instobj_create_(struct nouveau_object *parent,
struct nouveau_oclass *oclass,
int length, void **pobject)
{
- struct nouveau_instmem *imem = (void *)engine;
+ struct nouveau_instmem *imem = nouveau_instmem(parent);
struct nouveau_instobj *iobj;
int ret;
@@ -72,10 +72,9 @@ nouveau_instmem_alloc(struct nouveau_instmem *imem,
struct nouveau_object *parent, u32 size, u32 align,
struct nouveau_object **pobject)
{
- struct nouveau_object *engine = nv_object(imem);
- struct nouveau_instmem_impl *impl = (void *)engine->oclass;
+ struct nouveau_instmem_impl *impl = (void *)imem->base.object.oclass;
struct nouveau_instobj_args args = { .size = size, .align = align };
- return nouveau_object_ctor(parent, engine, impl->instobj, &args,
+ return nouveau_object_ctor(parent, parent->engine, impl->instobj, &args,
sizeof(args), pobject);
}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c
index e8b1401c59c0..9ffd2d8d73c4 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c
@@ -31,21 +31,23 @@
static u32
nv04_instobj_rd32(struct nouveau_object *object, u64 addr)
{
+ struct nv04_instmem_priv *priv = (void *)nouveau_instmem(object);
struct nv04_instobj_priv *node = (void *)object;
- return nv_ro32(object->engine, node->mem->offset + addr);
+ return nv_ro32(priv, node->mem->offset + addr);
}
static void
nv04_instobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
{
+ struct nv04_instmem_priv *priv = (void *)nouveau_instmem(object);
struct nv04_instobj_priv *node = (void *)object;
- nv_wo32(object->engine, node->mem->offset + addr, data);
+ nv_wo32(priv, node->mem->offset + addr, data);
}
static void
nv04_instobj_dtor(struct nouveau_object *object)
{
- struct nv04_instmem_priv *priv = (void *)object->engine;
+ struct nv04_instmem_priv *priv = (void *)nouveau_instmem(object);
struct nv04_instobj_priv *node = (void *)object;
nouveau_mm_free(&priv->heap, &node->mem);
nouveau_instobj_destroy(&node->base);
@@ -56,7 +58,7 @@ nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv04_instmem_priv *priv = (void *)engine;
+ struct nv04_instmem_priv *priv = (void *)nouveau_instmem(parent);
struct nv04_instobj_priv *node;
struct nouveau_instobj_args *args = data;
int ret;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c
index 7cb3b098a08d..64ee680232e2 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c
@@ -45,7 +45,7 @@ struct nv50_instobj_priv {
static u32
nv50_instobj_rd32(struct nouveau_object *object, u64 offset)
{
- struct nv50_instmem_priv *priv = (void *)object->engine;
+ struct nv50_instmem_priv *priv = (void *)nouveau_instmem(object);
struct nv50_instobj_priv *node = (void *)object;
unsigned long flags;
u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
@@ -65,7 +65,7 @@ nv50_instobj_rd32(struct nouveau_object *object, u64 offset)
static void
nv50_instobj_wr32(struct nouveau_object *object, u64 offset, u32 data)
{
- struct nv50_instmem_priv *priv = (void *)object->engine;
+ struct nv50_instmem_priv *priv = (void *)nouveau_instmem(object);
struct nv50_instobj_priv *node = (void *)object;
unsigned long flags;
u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
From 8c237fdf114db89156ecae9e7e8cd97cf79a99e0 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Fri, 5 Dec 2014 12:03:55 +1000
Subject: [PATCH 12/86] drm/nouveau/i2c: pad/ports do not have an engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/subdev/i2c/base.c | 10 +++++-----
drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c | 8 ++++----
drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c | 8 ++++----
drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c | 10 +++++-----
drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c | 4 ++--
drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c | 2 +-
drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h | 2 +-
drivers/gpu/drm/nouveau/core/subdev/i2c/padgm204.c | 4 ++--
drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c | 4 ++--
drivers/gpu/drm/nouveau/core/subdev/i2c/port.h | 2 +-
10 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
index e5f1ffaa6ef0..d1f06e9aaca2 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
@@ -117,8 +117,8 @@ nouveau_i2c_port_create_(struct nouveau_object *parent,
const struct nouveau_i2c_func *func,
int size, void **pobject)
{
- struct nouveau_device *device = nv_device(engine);
- struct nouveau_i2c *i2c = (void *)engine;
+ struct nouveau_device *device = nv_device(parent);
+ struct nouveau_i2c *i2c = nouveau_i2c(parent);
struct nouveau_i2c_port *port;
int ret;
@@ -494,7 +494,7 @@ nouveau_i2c_create_port(struct nouveau_i2c *i2c, int index, u8 type,
oclass = impl->pad_x;
}
- ret = nouveau_object_ctor(nv_object(i2c), nv_object(i2c), oclass,
+ ret = nouveau_object_ctor(nv_object(i2c), NULL, oclass,
NULL, pad, &parent);
if (ret < 0)
return;
@@ -503,7 +503,7 @@ nouveau_i2c_create_port(struct nouveau_i2c *i2c, int index, u8 type,
do {
ret = -EINVAL;
if (oclass->handle == type) {
- ret = nouveau_object_ctor(parent, nv_object(i2c),
+ ret = nouveau_object_ctor(parent, NULL,
oclass, info, index,
&object);
}
@@ -603,7 +603,7 @@ nouveau_i2c_create_(struct nouveau_object *parent,
do {
if (oclass->handle != info.type)
continue;
- ret = nouveau_object_ctor(parent, *pobject,
+ ret = nouveau_object_ctor(parent, NULL,
oclass, NULL,
index++, &object);
} while (ret && (++oclass)->handle);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c
index b1725bdea967..0db5de6a27fd 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c
@@ -39,7 +39,7 @@ struct nv04_i2c_port {
static void
nv04_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
{
- struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv04_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv04_i2c_port *port = (void *)base;
u8 val = nv_rdvgac(priv, 0, port->drive);
if (state) val |= 0x20;
@@ -50,7 +50,7 @@ nv04_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
static void
nv04_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
{
- struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv04_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv04_i2c_port *port = (void *)base;
u8 val = nv_rdvgac(priv, 0, port->drive);
if (state) val |= 0x10;
@@ -61,7 +61,7 @@ nv04_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
static int
nv04_i2c_sense_scl(struct nouveau_i2c_port *base)
{
- struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv04_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv04_i2c_port *port = (void *)base;
return !!(nv_rdvgac(priv, 0, port->sense) & 0x04);
}
@@ -69,7 +69,7 @@ nv04_i2c_sense_scl(struct nouveau_i2c_port *base)
static int
nv04_i2c_sense_sda(struct nouveau_i2c_port *base)
{
- struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv04_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv04_i2c_port *port = (void *)base;
return !!(nv_rdvgac(priv, 0, port->sense) & 0x08);
}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c
index f16c87ce5ba1..0d783890f267 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c
@@ -38,7 +38,7 @@ struct nv4e_i2c_port {
static void
nv4e_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
{
- struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv4e_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv4e_i2c_port *port = (void *)base;
nv_mask(priv, port->addr, 0x2f, state ? 0x21 : 0x01);
}
@@ -46,7 +46,7 @@ nv4e_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
static void
nv4e_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
{
- struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv4e_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv4e_i2c_port *port = (void *)base;
nv_mask(priv, port->addr, 0x1f, state ? 0x11 : 0x01);
}
@@ -54,7 +54,7 @@ nv4e_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
static int
nv4e_i2c_sense_scl(struct nouveau_i2c_port *base)
{
- struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv4e_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv4e_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00040000);
}
@@ -62,7 +62,7 @@ nv4e_i2c_sense_scl(struct nouveau_i2c_port *base)
static int
nv4e_i2c_sense_sda(struct nouveau_i2c_port *base)
{
- struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv4e_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv4e_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00080000);
}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c
index 7b8756d4df08..33dd89f5cfc4 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c
@@ -27,7 +27,7 @@
void
nv50_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
{
- struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv50_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv50_i2c_port *port = (void *)base;
if (state) port->state |= 0x01;
else port->state &= 0xfe;
@@ -37,7 +37,7 @@ nv50_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
void
nv50_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
{
- struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv50_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv50_i2c_port *port = (void *)base;
if (state) port->state |= 0x02;
else port->state &= 0xfd;
@@ -47,7 +47,7 @@ nv50_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
int
nv50_i2c_sense_scl(struct nouveau_i2c_port *base)
{
- struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv50_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv50_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00000001);
}
@@ -55,7 +55,7 @@ nv50_i2c_sense_scl(struct nouveau_i2c_port *base)
int
nv50_i2c_sense_sda(struct nouveau_i2c_port *base)
{
- struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv50_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv50_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00000002);
}
@@ -102,7 +102,7 @@ nv50_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
int
nv50_i2c_port_init(struct nouveau_object *object)
{
- struct nv50_i2c_priv *priv = (void *)object->engine;
+ struct nv50_i2c_priv *priv = (void *)nouveau_i2c(object);
struct nv50_i2c_port *port = (void *)object;
nv_wr32(priv, port->addr, port->state);
return nouveau_i2c_port_init(&port->base);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c
index fd99380502ec..62dde9b09007 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c
@@ -27,7 +27,7 @@
static int
nvd0_i2c_sense_scl(struct nouveau_i2c_port *base)
{
- struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv50_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv50_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00000010);
}
@@ -35,7 +35,7 @@ nvd0_i2c_sense_scl(struct nouveau_i2c_port *base)
static int
nvd0_i2c_sense_sda(struct nouveau_i2c_port *base)
{
- struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine;
+ struct nv50_i2c_priv *priv = (void *)nouveau_i2c(base);
struct nv50_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00000020);
}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c
index e9e412477c12..a3d0d82ff6f5 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c
@@ -48,7 +48,7 @@ nvkm_i2c_pad_create_(struct nouveau_object *parent,
struct nouveau_oclass *oclass, int index,
int size, void **pobject)
{
- struct nouveau_i2c *i2c = (void *)engine;
+ struct nouveau_i2c *i2c = nouveau_i2c(parent);
struct nouveau_i2c_port *port;
struct nvkm_i2c_pad *pad;
int ret;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h b/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h
index 89aea46a7da1..f03138b2e42c 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h
@@ -47,7 +47,7 @@ int _nvkm_i2c_pad_fini(struct nouveau_object *, bool);
#ifndef MSG
#define MSG(l,f,a...) do { \
struct nvkm_i2c_pad *_pad = (void *)pad; \
- nv_##l(nv_object(_pad)->engine, "PAD:%c:%02x: "f, \
+ nv_##l(_pad, "PAD:%c:%02x: "f, \
_pad->index >= 0x100 ? 'X' : 'S', \
_pad->index >= 0x100 ? _pad->index - 0x100 : _pad->index, ##a); \
} while(0)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/padgm204.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/padgm204.c
index f0e6fbbaa8cd..1630a934bece 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/padgm204.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/padgm204.c
@@ -32,7 +32,7 @@ struct gm204_i2c_pad {
static int
gm204_i2c_pad_fini(struct nouveau_object *object, bool suspend)
{
- struct nouveau_i2c *i2c = (void *)object->engine;
+ struct nouveau_i2c *i2c = (void *)nouveau_i2c(object);
struct gm204_i2c_pad *pad = (void *)object;
nv_mask(i2c, 0x00d97c + pad->addr, 0x00000001, 0x00000001);
return nvkm_i2c_pad_fini(&pad->base, suspend);
@@ -41,7 +41,7 @@ gm204_i2c_pad_fini(struct nouveau_object *object, bool suspend)
static int
gm204_i2c_pad_init(struct nouveau_object *object)
{
- struct nouveau_i2c *i2c = (void *)object->engine;
+ struct nouveau_i2c *i2c = (void *)nouveau_i2c(object);
struct gm204_i2c_pad *pad = (void *)object;
switch (nv_oclass(pad->base.next)->handle) {
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c
index 0dc6753014f0..afe79892f3be 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c
@@ -32,7 +32,7 @@ struct nv94_i2c_pad {
static int
nv94_i2c_pad_fini(struct nouveau_object *object, bool suspend)
{
- struct nouveau_i2c *i2c = (void *)object->engine;
+ struct nouveau_i2c *i2c = (void *)nouveau_i2c(object);
struct nv94_i2c_pad *pad = (void *)object;
nv_mask(i2c, 0x00e50c + pad->addr, 0x00000001, 0x00000001);
return nvkm_i2c_pad_fini(&pad->base, suspend);
@@ -41,7 +41,7 @@ nv94_i2c_pad_fini(struct nouveau_object *object, bool suspend)
static int
nv94_i2c_pad_init(struct nouveau_object *object)
{
- struct nouveau_i2c *i2c = (void *)object->engine;
+ struct nouveau_i2c *i2c = (void *)nouveau_i2c(object);
struct nv94_i2c_pad *pad = (void *)object;
switch (nv_oclass(pad->base.next)->handle) {
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/port.h b/drivers/gpu/drm/nouveau/core/subdev/i2c/port.h
index a8ff6e077af5..b9acf788e960 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/port.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/i2c/port.h
@@ -6,7 +6,7 @@
#ifndef MSG
#define MSG(l,f,a...) do { \
struct nouveau_i2c_port *_port = (void *)port; \
- nv_##l(nv_object(_port)->engine, "PORT:%02x: "f, _port->index, ##a); \
+ nv_##l(_port, "PORT:%02x: "f, _port->index, ##a); \
} while(0)
#define DBG(f,a...) MSG(debug, f, ##a)
#define ERR(f,a...) MSG(error, f, ##a)
From 9d18cdbb09a49b4565b84406a9eb0d0b67311da7 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Fri, 5 Dec 2014 12:04:56 +1000
Subject: [PATCH 13/86] drm/nouveau/fb: ram impl does not have an engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/subdev/fb/base.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/base.c b/drivers/gpu/drm/nouveau/core/subdev/fb/base.c
index 31869ff30740..090a7f2ac9b3 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/base.c
@@ -128,7 +128,7 @@ nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine,
pfb->memtype_valid = impl->memtype;
- ret = nouveau_object_ctor(nv_object(pfb), nv_object(pfb),
+ ret = nouveau_object_ctor(nv_object(pfb), NULL,
impl->ram, NULL, 0, &ram);
if (ret) {
nv_fatal(pfb, "error detecting memory configuration!!\n");
From c272d86e70db2b59a458c4c4e0460bf41ae42948 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Fri, 5 Dec 2014 12:08:20 +1000
Subject: [PATCH 14/86] drm/nouveau/bar: barobjs may not have an engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/subdev/bar/base.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
index b1adc69efd88..24fb89fd580f 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
@@ -42,7 +42,7 @@ nouveau_barobj_ctor(struct nouveau_object *parent,
struct nouveau_object **pobject)
{
struct nouveau_device *device = nv_device(parent);
- struct nouveau_bar *bar = (void *)engine;
+ struct nouveau_bar *bar = nouveau_bar(device);
struct nouveau_mem *mem = data;
struct nouveau_barobj *barobj;
int ret;
@@ -69,7 +69,7 @@ nouveau_barobj_ctor(struct nouveau_object *parent,
static void
nouveau_barobj_dtor(struct nouveau_object *object)
{
- struct nouveau_bar *bar = (void *)object->engine;
+ struct nouveau_bar *bar = nouveau_bar(object);
struct nouveau_barobj *barobj = (void *)object;
if (barobj->vma.node) {
if (barobj->iomem)
@@ -109,9 +109,9 @@ int
nouveau_bar_alloc(struct nouveau_bar *bar, struct nouveau_object *parent,
struct nouveau_mem *mem, struct nouveau_object **pobject)
{
- struct nouveau_object *engine = nv_object(bar);
struct nouveau_object *gpuobj;
- int ret = nouveau_object_ctor(parent, engine, &nouveau_barobj_oclass,
+ int ret = nouveau_object_ctor(parent, parent->engine,
+ &nouveau_barobj_oclass,
mem, 0, &gpuobj);
if (ret == 0)
*pobject = gpuobj;
From bdda4703f145ef5a098d100a071e272a65abd01d Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Fri, 5 Dec 2014 12:12:23 +1000
Subject: [PATCH 15/86] drm/nouveau/disp: outp/conns do not have an engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/engine/disp/base.c | 3 +--
drivers/gpu/drm/nouveau/core/engine/disp/conn.c | 2 +-
drivers/gpu/drm/nouveau/core/engine/disp/conn.h | 2 +-
drivers/gpu/drm/nouveau/core/engine/disp/outp.c | 6 +++---
drivers/gpu/drm/nouveau/core/engine/disp/outp.h | 2 +-
5 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/base.c b/drivers/gpu/drm/nouveau/core/engine/disp/base.c
index 64b84667f3a5..c8a5f810e537 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/base.c
@@ -225,8 +225,7 @@ nouveau_disp_create_(struct nouveau_object *parent,
sclass++;
}
- nouveau_object_ctor(*pobject, *pobject, oclass,
- &dcbE, i, &object);
+ nouveau_object_ctor(*pobject, NULL, oclass, &dcbE, i, &object);
hpd = max(hpd, (u8)(dcbE.connector + 1));
}
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/conn.c b/drivers/gpu/drm/nouveau/core/engine/disp/conn.c
index 1496b567dd4a..498ab4b8a9af 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/conn.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/conn.c
@@ -86,8 +86,8 @@ nvkm_connector_create_(struct nouveau_object *parent,
int length, void **pobject)
{
static const u8 hpd[] = { 0x07, 0x08, 0x51, 0x52, 0x5e, 0x5f, 0x60 };
+ struct nouveau_disp *disp = nouveau_disp(parent);
struct nouveau_gpio *gpio = nouveau_gpio(parent);
- struct nouveau_disp *disp = (void *)engine;
struct nvkm_connector *conn;
struct nvkm_output *outp;
struct dcb_gpio_func func;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/conn.h b/drivers/gpu/drm/nouveau/core/engine/disp/conn.h
index 55e5f5c82c14..a1bf359e53bd 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/conn.h
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/conn.h
@@ -46,7 +46,7 @@ struct nvkm_connector_impl {
#ifndef MSG
#define MSG(l,f,a...) do { \
struct nvkm_connector *_conn = (void *)conn; \
- nv_##l(nv_object(conn)->engine, "%02x:%02x%02x: "f, _conn->index, \
+ nv_##l(_conn, "%02x:%02x%02x: "f, _conn->index, \
_conn->info.location, _conn->info.type, ##a); \
} while(0)
#define DBG(f,a...) MSG(debug, f, ##a)
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outp.c b/drivers/gpu/drm/nouveau/core/engine/disp/outp.c
index bbd9b6fdc90f..c5589c26e07d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/outp.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/outp.c
@@ -62,9 +62,9 @@ nvkm_output_create_(struct nouveau_object *parent,
struct dcb_output *dcbE, int index,
int length, void **pobject)
{
- struct nouveau_bios *bios = nouveau_bios(engine);
+ struct nouveau_disp *disp = nouveau_disp(parent);
+ struct nouveau_bios *bios = nouveau_bios(parent);
struct nouveau_i2c *i2c = nouveau_i2c(parent);
- struct nouveau_disp *disp = (void *)engine;
struct nvbios_connE connE;
struct nvkm_output *outp;
u8 ver, hdr;
@@ -98,7 +98,7 @@ nvkm_output_create_(struct nouveau_object *parent,
connE.type = DCB_CONNECTOR_NONE;
}
- ret = nouveau_object_ctor(parent, engine, nvkm_connector_oclass,
+ ret = nouveau_object_ctor(parent, NULL, nvkm_connector_oclass,
&connE, outp->info.connector,
(struct nouveau_object **)&outp->conn);
if (ret < 0) {
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outp.h b/drivers/gpu/drm/nouveau/core/engine/disp/outp.h
index 187f435ad0e2..5305aa0f73b6 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/outp.h
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/outp.h
@@ -50,7 +50,7 @@ struct nvkm_output_impl {
#ifndef MSG
#define MSG(l,f,a...) do { \
struct nvkm_output *_outp = (void *)outp; \
- nv_##l(nv_object(outp)->engine, "%02x:%04x:%04x: "f, _outp->index, \
+ nv_##l(_outp, "%02x:%04x:%04x: "f, _outp->index, \
_outp->info.hasht, _outp->info.hashm, ##a); \
} while(0)
#define DBG(f,a...) MSG(debug, f, ##a)
From 8000fb219179e0be23cef03588dcd6c00a2035f3 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Fri, 5 Dec 2014 12:21:34 +1000
Subject: [PATCH 16/86] drm/nouveau/core: can now assume client/device object
tree based on object.engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/core/printk.c | 10 ++++++----
drivers/gpu/drm/nouveau/core/engine/device/base.c | 7 ++++---
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/core/printk.c b/drivers/gpu/drm/nouveau/core/core/printk.c
index 1060e3a173fe..81f559692624 100644
--- a/drivers/gpu/drm/nouveau/core/core/printk.c
+++ b/drivers/gpu/drm/nouveau/core/core/printk.c
@@ -64,11 +64,13 @@ nv_printk_(struct nouveau_object *object, int level, const char *fmt, ...)
struct nouveau_object *subdev;
char obuf[64], *ofmt = "";
- subdev = object;
- while (subdev && !nv_iclass(subdev, NV_SUBDEV_CLASS))
- subdev = subdev->parent;
- if (!subdev)
+ if (object->engine == NULL) {
+ subdev = object;
+ while (subdev && !nv_iclass(subdev, NV_SUBDEV_CLASS))
+ subdev = subdev->parent;
+ } else {
subdev = object->engine;
+ }
device = subdev;
if (device->parent)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c
index 7c0cbcde7b2f..0a6abc23f85d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c
@@ -512,9 +512,10 @@ struct nouveau_device *
nv_device(void *obj)
{
struct nouveau_object *device = nv_object(obj);
- while (device && device->parent)
- device = device->parent;
- if (!nv_iclass(device, NV_ENGINE_CLASS)) {
+ if (device->engine == NULL) {
+ while (device && device->parent)
+ device = device->parent;
+ } else {
device = nv_object(obj)->engine;
if (device && device->parent)
device = device->parent;
From ec0e55420de97aae9338cba081de03c7804375ce Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Fri, 5 Dec 2014 12:37:19 +1000
Subject: [PATCH 17/86] drm/nouveau/core: object.engine is always a
nouveau_engine now
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/core/engctx.c | 7 +++----
drivers/gpu/drm/nouveau/core/core/engine.c | 2 +-
drivers/gpu/drm/nouveau/core/core/gpuobj.c | 4 ++--
drivers/gpu/drm/nouveau/core/core/object.c | 14 +++++++-------
drivers/gpu/drm/nouveau/core/core/parent.c | 2 +-
drivers/gpu/drm/nouveau/core/core/printk.c | 2 +-
drivers/gpu/drm/nouveau/core/core/ramht.c | 2 +-
drivers/gpu/drm/nouveau/core/core/subdev.c | 2 +-
drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c | 2 +-
drivers/gpu/drm/nouveau/core/engine/copy/nve0.c | 2 +-
drivers/gpu/drm/nouveau/core/engine/device/base.c | 2 +-
drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c | 3 +--
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 3 +--
drivers/gpu/drm/nouveau/core/include/core/engine.h | 4 ++--
drivers/gpu/drm/nouveau/core/include/core/object.h | 2 +-
drivers/gpu/drm/nouveau/core/include/core/subdev.h | 4 ++--
drivers/gpu/drm/nouveau/core/subdev/bar/base.c | 2 +-
drivers/gpu/drm/nouveau/core/subdev/instmem/base.c | 4 ++--
18 files changed, 30 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/core/engctx.c b/drivers/gpu/drm/nouveau/core/core/engctx.c
index 6b9c728053d0..16f09b1280dc 100644
--- a/drivers/gpu/drm/nouveau/core/core/engctx.c
+++ b/drivers/gpu/drm/nouveau/core/core/engctx.c
@@ -102,7 +102,7 @@ nouveau_engctx_create_(struct nouveau_object *parent,
}
if (client->vm)
- atomic_inc(&client->vm->engref[nv_engidx(engobj)]);
+ atomic_inc(&client->vm->engref[nv_engidx(engine)]);
list_add(&nv_engctx(engctx)->head, &engine->contexts);
nv_engctx(engctx)->addr = ~0ULL;
spin_unlock_irqrestore(&engine->lock, save);
@@ -112,8 +112,7 @@ nouveau_engctx_create_(struct nouveau_object *parent,
void
nouveau_engctx_destroy(struct nouveau_engctx *engctx)
{
- struct nouveau_object *engobj = nv_object(engctx)->engine;
- struct nouveau_engine *engine = nv_engine(engobj);
+ struct nouveau_engine *engine = engctx->gpuobj.object.engine;
struct nouveau_client *client = nouveau_client(engctx);
unsigned long save;
@@ -123,7 +122,7 @@ nouveau_engctx_destroy(struct nouveau_engctx *engctx)
spin_unlock_irqrestore(&engine->lock, save);
if (client->vm)
- atomic_dec(&client->vm->engref[nv_engidx(engobj)]);
+ atomic_dec(&client->vm->engref[nv_engidx(engine)]);
if (engctx->gpuobj.size)
nouveau_gpuobj_destroy(&engctx->gpuobj);
diff --git a/drivers/gpu/drm/nouveau/core/core/engine.c b/drivers/gpu/drm/nouveau/core/core/engine.c
index 85bf4b3d1fe4..c9414b1532ff 100644
--- a/drivers/gpu/drm/nouveau/core/core/engine.c
+++ b/drivers/gpu/drm/nouveau/core/core/engine.c
@@ -53,7 +53,7 @@ nouveau_engine_create_(struct nouveau_object *parent,
if (parent) {
struct nouveau_device *device = nv_device(parent);
- int engidx = nv_engidx(nv_object(engine));
+ int engidx = nv_engidx(engine);
if (device->disable_mask & (1ULL << engidx)) {
if (!nouveau_boolopt(device->cfgopt, iname, false)) {
diff --git a/drivers/gpu/drm/nouveau/core/core/gpuobj.c b/drivers/gpu/drm/nouveau/core/core/gpuobj.c
index 0a9ea1fa9b55..0fa64576b8d6 100644
--- a/drivers/gpu/drm/nouveau/core/core/gpuobj.c
+++ b/drivers/gpu/drm/nouveau/core/core/gpuobj.c
@@ -229,7 +229,7 @@ nouveau_gpuobj_new(struct nouveau_object *parent, struct nouveau_object *pargpu,
};
if (!nv_iclass(engine, NV_SUBDEV_CLASS))
- engine = engine->engine;
+ engine = &engine->engine->subdev.object;
BUG_ON(engine == NULL);
return nouveau_object_ctor(parent, engine, &_nouveau_gpuobj_oclass,
@@ -310,7 +310,7 @@ nouveau_gpuobj_dup(struct nouveau_object *parent, struct nouveau_gpuobj *base,
struct nouveau_gpuobj *gpuobj;
int ret;
- ret = nouveau_object_create(parent, parent->engine,
+ ret = nouveau_object_create(parent, &parent->engine->subdev.object,
&nouveau_gpudup_oclass, 0, &gpuobj);
*pgpuobj = gpuobj;
if (ret)
diff --git a/drivers/gpu/drm/nouveau/core/core/object.c b/drivers/gpu/drm/nouveau/core/core/object.c
index b08630577c82..b160860edf54 100644
--- a/drivers/gpu/drm/nouveau/core/core/object.c
+++ b/drivers/gpu/drm/nouveau/core/core/object.c
@@ -43,7 +43,7 @@ nouveau_object_create_(struct nouveau_object *parent,
return -ENOMEM;
nouveau_object_ref(parent, &object->parent);
- nouveau_object_ref(engine, &object->engine);
+ nouveau_object_ref(engine, (struct nouveau_object **)&object->engine);
object->oclass = oclass;
object->oclass->handle |= pclass;
atomic_set(&object->refcount, 1);
@@ -77,7 +77,7 @@ nouveau_object_destroy(struct nouveau_object *object)
list_del(&object->list);
spin_unlock(&_objlist_lock);
#endif
- nouveau_object_ref(NULL, &object->engine);
+ nouveau_object_ref(NULL, (struct nouveau_object **)&object->engine);
nouveau_object_ref(NULL, &object->parent);
kfree(object);
}
@@ -182,7 +182,7 @@ nouveau_object_inc(struct nouveau_object *object)
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
- ret = nouveau_object_inc(object->engine);
+ ret = nouveau_object_inc(&object->engine->subdev.object);
mutex_unlock(&nv_subdev(object->engine)->mutex);
if (ret) {
nv_error(object, "engine failed, %d\n", ret);
@@ -203,7 +203,7 @@ nouveau_object_inc(struct nouveau_object *object)
fail_self:
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
- nouveau_object_dec(object->engine, false);
+ nouveau_object_dec(&object->engine->subdev.object, false);
mutex_unlock(&nv_subdev(object->engine)->mutex);
}
fail_engine:
@@ -228,7 +228,7 @@ nouveau_object_decf(struct nouveau_object *object)
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
- nouveau_object_dec(object->engine, false);
+ nouveau_object_dec(&object->engine->subdev.object, false);
mutex_unlock(&nv_subdev(object->engine)->mutex);
}
@@ -255,7 +255,7 @@ nouveau_object_decs(struct nouveau_object *object)
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
- ret = nouveau_object_dec(object->engine, true);
+ ret = nouveau_object_dec(&object->engine->subdev.object, true);
mutex_unlock(&nv_subdev(object->engine)->mutex);
if (ret) {
nv_warn(object, "engine failed suspend, %d\n", ret);
@@ -277,7 +277,7 @@ nouveau_object_decs(struct nouveau_object *object)
fail_parent:
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
- rret = nouveau_object_inc(object->engine);
+ rret = nouveau_object_inc(&object->engine->subdev.object);
mutex_unlock(&nv_subdev(object->engine)->mutex);
if (rret)
nv_fatal(object, "engine failed to reinit, %d\n", rret);
diff --git a/drivers/gpu/drm/nouveau/core/core/parent.c b/drivers/gpu/drm/nouveau/core/core/parent.c
index 07a2006a1d78..1f28fa12e98f 100644
--- a/drivers/gpu/drm/nouveau/core/core/parent.c
+++ b/drivers/gpu/drm/nouveau/core/core/parent.c
@@ -39,7 +39,7 @@ nouveau_parent_sclass(struct nouveau_object *parent, u16 handle,
sclass = nv_parent(parent)->sclass;
while (sclass) {
if ((sclass->oclass->handle & 0xffff) == handle) {
- *pengine = parent->engine;
+ *pengine = &parent->engine->subdev.object;
*poclass = sclass->oclass;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/core/core/printk.c b/drivers/gpu/drm/nouveau/core/core/printk.c
index 81f559692624..ed424f99f383 100644
--- a/drivers/gpu/drm/nouveau/core/core/printk.c
+++ b/drivers/gpu/drm/nouveau/core/core/printk.c
@@ -69,7 +69,7 @@ nv_printk_(struct nouveau_object *object, int level, const char *fmt, ...)
while (subdev && !nv_iclass(subdev, NV_SUBDEV_CLASS))
subdev = subdev->parent;
} else {
- subdev = object->engine;
+ subdev = &object->engine->subdev.object;
}
device = subdev;
diff --git a/drivers/gpu/drm/nouveau/core/core/ramht.c b/drivers/gpu/drm/nouveau/core/core/ramht.c
index f3b9bddc3875..25cd6f29072b 100644
--- a/drivers/gpu/drm/nouveau/core/core/ramht.c
+++ b/drivers/gpu/drm/nouveau/core/core/ramht.c
@@ -96,7 +96,7 @@ nouveau_ramht_new(struct nouveau_object *parent, struct nouveau_object *pargpu,
int ret;
ret = nouveau_gpuobj_create(parent, parent->engine ?
- parent->engine : parent, /* <nv50 ramht */
+ &parent->engine->subdev.object : parent, /* <nv50 ramht */
&nouveau_ramht_oclass, 0, pargpu, size,
align, NVOBJ_FLAG_ZERO_ALLOC, &ramht);
*pramht = ramht;
diff --git a/drivers/gpu/drm/nouveau/core/core/subdev.c b/drivers/gpu/drm/nouveau/core/core/subdev.c
index 69ba1482c3f5..cb1c49c2e9d6 100644
--- a/drivers/gpu/drm/nouveau/core/core/subdev.c
+++ b/drivers/gpu/drm/nouveau/core/core/subdev.c
@@ -33,7 +33,7 @@ nouveau_subdev(void *obj, int idx)
struct nouveau_object *object = nv_object(obj);
while (object && !nv_iclass(object, NV_SUBDEV_CLASS))
object = object->parent;
- if (object == NULL || nv_subidx(object) != idx)
+ if (object == NULL || nv_subidx(nv_subdev(object)) != idx)
object = nv_device(obj)->subdev[idx];
return object ? nv_subdev(object) : NULL;
}
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
index 9261694d0d35..20a8cd7f7730 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
@@ -91,7 +91,7 @@ nvc0_copy_init(struct nouveau_object *object)
if (ret)
return ret;
- nv_wo32(priv, 0x084, nv_engidx(object) - NVDEV_ENGINE_COPY0);
+ nv_wo32(priv, 0x084, nv_engidx(&priv->base.base) - NVDEV_ENGINE_COPY0);
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
index c7194b354605..b140a01dd323 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
@@ -69,7 +69,7 @@ nve0_copy_cclass = {
static void
nve0_copy_intr(struct nouveau_subdev *subdev)
{
- const int ce = nv_subidx(nv_object(subdev)) - NVDEV_ENGINE_COPY0;
+ const int ce = nv_subidx(subdev) - NVDEV_ENGINE_COPY0;
struct nve0_copy_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000));
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c
index 0a6abc23f85d..f74f9cbbf3d8 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c
@@ -516,7 +516,7 @@ nv_device(void *obj)
while (device && device->parent)
device = device->parent;
} else {
- device = nv_object(obj)->engine;
+ device = &nv_object(obj)->engine->subdev.object;
if (device && device->parent)
device = device->parent;
}
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
index 074d434c3077..e8ef8cb058cd 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
@@ -445,7 +445,6 @@ static void
nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine,
struct nvc0_fifo_chan *chan)
{
- struct nouveau_object *engobj = nv_object(engine);
u32 chid = chan->base.chid;
unsigned long flags;
@@ -456,7 +455,7 @@ nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine,
chan->state = KILLED;
spin_lock_irqsave(&priv->base.lock, flags);
- priv->mask |= 1ULL << nv_engidx(engobj);
+ priv->mask |= 1ULL << nv_engidx(engine);
spin_unlock_irqrestore(&priv->base.lock, flags);
schedule_work(&priv->fault);
}
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
index 6a8db7c80bd1..c9c168035b4d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
@@ -471,7 +471,6 @@ static void
nve0_fifo_recover(struct nve0_fifo_priv *priv, struct nouveau_engine *engine,
struct nve0_fifo_chan *chan)
{
- struct nouveau_object *engobj = nv_object(engine);
u32 chid = chan->base.chid;
unsigned long flags;
@@ -482,7 +481,7 @@ nve0_fifo_recover(struct nve0_fifo_priv *priv, struct nouveau_engine *engine,
chan->state = KILLED;
spin_lock_irqsave(&priv->base.lock, flags);
- priv->mask |= 1ULL << nv_engidx(engobj);
+ priv->mask |= 1ULL << nv_engidx(engine);
spin_unlock_irqrestore(&priv->base.lock, flags);
schedule_work(&priv->fault);
}
diff --git a/drivers/gpu/drm/nouveau/core/include/core/engine.h b/drivers/gpu/drm/nouveau/core/include/core/engine.h
index be04250a1c00..d7ebd35ef1ad 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/engine.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/engine.h
@@ -30,9 +30,9 @@ nv_engine(void *obj)
}
static inline int
-nv_engidx(struct nouveau_object *object)
+nv_engidx(struct nouveau_engine *engine)
{
- return nv_subidx(object);
+ return nv_subidx(&engine->subdev);
}
struct nouveau_engine *nouveau_engine(void *obj, int idx);
diff --git a/drivers/gpu/drm/nouveau/core/include/core/object.h b/drivers/gpu/drm/nouveau/core/include/core/object.h
index 2e2afa502c99..64c0038f1971 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/object.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/object.h
@@ -17,7 +17,7 @@
struct nouveau_object {
struct nouveau_oclass *oclass;
struct nouveau_object *parent;
- struct nouveau_object *engine;
+ struct nouveau_engine *engine;
atomic_t refcount;
atomic_t usecount;
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
diff --git a/drivers/gpu/drm/nouveau/core/include/core/subdev.h b/drivers/gpu/drm/nouveau/core/include/core/subdev.h
index d9739aed0150..68f1c419d156 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/subdev.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/subdev.h
@@ -28,9 +28,9 @@ nv_subdev(void *obj)
}
static inline int
-nv_subidx(struct nouveau_object *object)
+nv_subidx(struct nouveau_subdev *subdev)
{
- return nv_hclass(nv_subdev(object)) & 0xff;
+ return nv_hclass(subdev) & 0xff;
}
struct nouveau_subdev *nouveau_subdev(void *obj, int idx);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
index 24fb89fd580f..188c638411b2 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
@@ -110,7 +110,7 @@ nouveau_bar_alloc(struct nouveau_bar *bar, struct nouveau_object *parent,
struct nouveau_mem *mem, struct nouveau_object **pobject)
{
struct nouveau_object *gpuobj;
- int ret = nouveau_object_ctor(parent, parent->engine,
+ int ret = nouveau_object_ctor(parent, &parent->engine->subdev.object,
&nouveau_barobj_oclass,
mem, 0, &gpuobj);
if (ret == 0)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c
index b2dac4a088a1..767fcf70f98f 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c
@@ -74,8 +74,8 @@ nouveau_instmem_alloc(struct nouveau_instmem *imem,
{
struct nouveau_instmem_impl *impl = (void *)imem->base.object.oclass;
struct nouveau_instobj_args args = { .size = size, .align = align };
- return nouveau_object_ctor(parent, parent->engine, impl->instobj, &args,
- sizeof(args), pobject);
+ return nouveau_object_ctor(parent, &parent->engine->subdev.object,
+ impl->instobj, &args, sizeof(args), pobject);
}
int
From 2474ae294260e9a3172c99a3c2b41d84e95644fc Mon Sep 17 00:00:00 2001
From: Alexandre Courbot <acourbot@nvidia.com>
Date: Thu, 11 Dec 2014 03:43:05 +0900
Subject: [PATCH 18/86] drm/nouveau: sgdma: remove unused nouveau_sgdma_be::dev
nouveau_sgdma_be::dev is only set once during init and never used
anywhere, so remove it.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/nouveau_sgdma.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index 01707e7deaf5..ec76c0b4e452 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -9,7 +9,6 @@ struct nouveau_sgdma_be {
* nouve_bo.c works properly, otherwise have to move them here
*/
struct ttm_dma_tt ttm;
- struct drm_device *dev;
struct nouveau_mem *node;
};
@@ -101,7 +100,6 @@ nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
if (!nvbe)
return NULL;
- nvbe->dev = drm->dev;
if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA)
nvbe->ttm.ttm.func = &nv04_sgdma_backend;
else
From 495b21761a4bf50c0453766ed8fdcfed075d43ff Mon Sep 17 00:00:00 2001
From: Alexandre Courbot <acourbot@nvidia.com>
Date: Thu, 11 Dec 2014 04:07:20 +0900
Subject: [PATCH 19/86] drm/nouveau: sgdma: add comment around suspiscious
error handler
Common programming sense dictates that resources allocated by a function
are freed by this function should it fails, but this is not the case for
the allocated structure of nouveau_sgdma_create_ttm(). It seems that
n00b contributors attempt to fix this one like bugs flying towards a bug
zapper, so add a comment to hopefully prevent this from happening
anymore.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/nouveau_sgdma.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index ec76c0b4e452..23c377a6c761 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -106,6 +106,11 @@ nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
nvbe->ttm.ttm.func = &nv50_sgdma_backend;
if (ttm_dma_tt_init(&nvbe->ttm, bdev, size, page_flags, dummy_read_page))
+ /*
+ * A failing ttm_dma_tt_init() will call ttm_tt_destroy()
+ * and thus our nouveau_sgdma_destroy() hook, so we don't need
+ * to free nvbe here.
+ */
return NULL;
return &nvbe->ttm.ttm;
}
From a91d322120a65ec5ada5518d948fda84aa87796f Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Mon, 22 Dec 2014 16:30:13 +1000
Subject: [PATCH 20/86] drm/nv50-/kms: move identical scaler mode fixup code
into a function
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/nv50_display.c | 78 ++++++++------------------
1 file changed, 24 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 490b90866baf..4f544f3683db 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -1465,6 +1465,26 @@ out:
return ret;
}
+/******************************************************************************
+ * Encoder helpers
+ *****************************************************************************/
+static bool
+nv50_encoder_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+ struct nouveau_connector *nv_connector;
+
+ nv_connector = nouveau_encoder_connector_get(nv_encoder);
+ if (nv_connector && nv_connector->native_mode) {
+ if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE)
+ drm_mode_copy(adjusted_mode, nv_connector->native_mode);
+ }
+
+ return true;
+}
+
/******************************************************************************
* DAC
*****************************************************************************/
@@ -1492,26 +1512,6 @@ nv50_dac_dpms(struct drm_encoder *encoder, int mode)
nvif_mthd(disp->disp, 0, &args, sizeof(args));
}
-static bool
-nv50_dac_mode_fixup(struct drm_encoder *encoder,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
- struct nouveau_connector *nv_connector;
-
- nv_connector = nouveau_encoder_connector_get(nv_encoder);
- if (nv_connector && nv_connector->native_mode) {
- if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
- int id = adjusted_mode->base.id;
- *adjusted_mode = *nv_connector->native_mode;
- adjusted_mode->base.id = id;
- }
- }
-
- return true;
-}
-
static void
nv50_dac_commit(struct drm_encoder *encoder)
{
@@ -1629,7 +1629,7 @@ nv50_dac_destroy(struct drm_encoder *encoder)
static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
.dpms = nv50_dac_dpms,
- .mode_fixup = nv50_dac_mode_fixup,
+ .mode_fixup = nv50_encoder_mode_fixup,
.prepare = nv50_dac_disconnect,
.commit = nv50_dac_commit,
.mode_set = nv50_dac_mode_set,
@@ -1834,26 +1834,6 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
}
}
-static bool
-nv50_sor_mode_fixup(struct drm_encoder *encoder,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
- struct nouveau_connector *nv_connector;
-
- nv_connector = nouveau_encoder_connector_get(nv_encoder);
- if (nv_connector && nv_connector->native_mode) {
- if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
- int id = adjusted_mode->base.id;
- *adjusted_mode = *nv_connector->native_mode;
- adjusted_mode->base.id = id;
- }
- }
-
- return true;
-}
-
static void
nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
{
@@ -2035,7 +2015,7 @@ nv50_sor_destroy(struct drm_encoder *encoder)
static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
.dpms = nv50_sor_dpms,
- .mode_fixup = nv50_sor_mode_fixup,
+ .mode_fixup = nv50_encoder_mode_fixup,
.prepare = nv50_sor_disconnect,
.commit = nv50_sor_commit,
.mode_set = nv50_sor_mode_set,
@@ -2112,18 +2092,8 @@ nv50_pior_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
- struct nouveau_connector *nv_connector;
-
- nv_connector = nouveau_encoder_connector_get(nv_encoder);
- if (nv_connector && nv_connector->native_mode) {
- if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
- int id = adjusted_mode->base.id;
- *adjusted_mode = *nv_connector->native_mode;
- adjusted_mode->base.id = id;
- }
- }
-
+ if (!nv50_encoder_mode_fixup(encoder, mode, adjusted_mode))
+ return false;
adjusted_mode->clock *= 2;
return true;
}
From 576f79116ee8ed6f41f0f9f1fc295eaad5d5aeee Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Mon, 22 Dec 2014 17:19:26 +1000
Subject: [PATCH 21/86] drm/nv50-/kms: allow disabling of gpu scaling on fixed
panels
The hilarious part is that, under X, this won't work anyway because the
server decides to construct its own modes for some reason.
Tested with modetest, which isn't quite as insane. I'd hope that
wayland is more sensible.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/nouveau_connector.c | 29 ++++++++++++++++-----
drivers/gpu/drm/nouveau/nouveau_connector.h | 1 +
drivers/gpu/drm/nouveau/nv50_display.c | 24 ++++++++++++++---
3 files changed, 44 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index c8ac9482cf2e..d13f50db765d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -458,6 +458,28 @@ nouveau_connector_set_property(struct drm_connector *connector,
switch (value) {
case DRM_MODE_SCALE_NONE:
+ /* We allow 'None' for EDID modes, even on a fixed
+ * panel (some exist with support for lower refresh
+ * rates, which people might want to use for power
+ * saving purposes).
+ *
+ * Non-EDID modes will force the use of GPU scaling
+ * to the native mode regardless of this setting.
+ */
+ switch (nv_connector->type) {
+ case DCB_CONNECTOR_LVDS:
+ case DCB_CONNECTOR_LVDS_SPWG:
+ case DCB_CONNECTOR_eDP:
+ /* ... except prior to G80, where the code
+ * doesn't support such things.
+ */
+ if (disp->disp.oclass < NV50_DISP)
+ return -EINVAL;
+ break;
+ default:
+ break;
+ }
+ break;
case DRM_MODE_SCALE_FULLSCREEN:
case DRM_MODE_SCALE_CENTER:
case DRM_MODE_SCALE_ASPECT:
@@ -466,11 +488,6 @@ nouveau_connector_set_property(struct drm_connector *connector,
return -EINVAL;
}
- /* LVDS always needs gpu scaling */
- if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS &&
- value == DRM_MODE_SCALE_NONE)
- return -EINVAL;
-
/* Changing between GPU and panel scaling requires a full
* modeset
*/
@@ -662,8 +679,6 @@ nouveau_connector_scaler_modes_add(struct drm_connector *connector)
if (!m)
continue;
- m->type |= DRM_MODE_TYPE_DRIVER;
-
drm_mode_probed_add(connector, m);
modes++;
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h
index 629a380c7085..a2d099142d96 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.h
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.h
@@ -72,6 +72,7 @@ struct nouveau_connector {
int dithering_mode;
int dithering_depth;
int scaling_mode;
+ bool scaling_full;
enum nouveau_underscan_type underscan;
u32 underscan_hborder;
u32 underscan_vborder;
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 4f544f3683db..85cc667cfb0f 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -729,8 +729,11 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
* effectively handles NONE/FULL scaling
*/
nv_connector = nouveau_crtc_connector_get(nv_crtc);
- if (nv_connector && nv_connector->native_mode)
+ if (nv_connector && nv_connector->native_mode) {
mode = nv_connector->scaling_mode;
+ if (nv_connector->scaling_full) /* non-EDID LVDS/eDP mode */
+ mode = DRM_MODE_SCALE_FULLSCREEN;
+ }
if (mode != DRM_MODE_SCALE_NONE)
omode = nv_connector->native_mode;
@@ -1478,8 +1481,23 @@ nv50_encoder_mode_fixup(struct drm_encoder *encoder,
nv_connector = nouveau_encoder_connector_get(nv_encoder);
if (nv_connector && nv_connector->native_mode) {
- if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE)
- drm_mode_copy(adjusted_mode, nv_connector->native_mode);
+ nv_connector->scaling_full = false;
+ if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE) {
+ switch (nv_connector->type) {
+ case DCB_CONNECTOR_LVDS:
+ case DCB_CONNECTOR_LVDS_SPWG:
+ case DCB_CONNECTOR_eDP:
+ /* force use of scaler for non-edid modes */
+ if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
+ return true;
+ nv_connector->scaling_full = true;
+ break;
+ default:
+ return true;
+ }
+ }
+
+ drm_mode_copy(adjusted_mode, nv_connector->native_mode);
}
return true;
From f0d15402a38654a987e5ebb844d06db4a8f98435 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Mon, 22 Dec 2014 17:28:35 +1000
Subject: [PATCH 22/86] drm/nouveau/kms: avoid adding scaler-only modes the
same as the panel's native mode
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/nouveau_connector.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index d13f50db765d..660d0e77ef34 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -672,7 +672,9 @@ nouveau_connector_scaler_modes_add(struct drm_connector *connector)
while (mode->hdisplay) {
if (mode->hdisplay <= native->hdisplay &&
- mode->vdisplay <= native->vdisplay) {
+ mode->vdisplay <= native->vdisplay &&
+ (mode->hdisplay != native->hdisplay ||
+ mode->vdisplay != native->vdisplay)) {
m = drm_cvt_mode(dev, mode->hdisplay, mode->vdisplay,
drm_mode_vrefresh(native), false,
false, false);
From 7d95216e1ca4be5964ce3f1949c07fb87bef0565 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Mon, 22 Dec 2014 18:15:55 +1000
Subject: [PATCH 23/86] drm/nouveau/kms: untangle connector property logic a
little
Should be the same defaults as before, just easier to follow.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/nouveau_connector.c | 53 ++++++++++++++-------
1 file changed, 37 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 660d0e77ef34..938de24da7dd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -1197,36 +1197,57 @@ nouveau_connector_create(struct drm_device *dev, int index)
disp->color_vibrance_property,
150);
+ /* default scaling mode */
switch (nv_connector->type) {
- case DCB_CONNECTOR_VGA:
- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
- drm_object_attach_property(&connector->base,
- dev->mode_config.scaling_mode_property,
- nv_connector->scaling_mode);
- }
- /* fall-through */
case DCB_CONNECTOR_TV_0:
case DCB_CONNECTOR_TV_1:
case DCB_CONNECTOR_TV_3:
+ case DCB_CONNECTOR_VGA:
nv_connector->scaling_mode = DRM_MODE_SCALE_NONE;
break;
default:
nv_connector->scaling_mode = DRM_MODE_SCALE_FULLSCREEN;
+ break;
+ }
- drm_object_attach_property(&connector->base,
- dev->mode_config.scaling_mode_property,
- nv_connector->scaling_mode);
+ /* scaling mode property */
+ switch (nv_connector->type) {
+ case DCB_CONNECTOR_TV_0:
+ case DCB_CONNECTOR_TV_1:
+ case DCB_CONNECTOR_TV_3:
+ break;
+ case DCB_CONNECTOR_VGA:
+ if (disp->disp.oclass < NV50_DISP)
+ break; /* can only scale on DFPs */
+ /* fall-through */
+ default:
+ drm_object_attach_property(&connector->base, dev->mode_config.
+ scaling_mode_property,
+ nv_connector->scaling_mode);
+ break;
+ }
+
+ /* dithering properties */
+ switch (nv_connector->type) {
+ case DCB_CONNECTOR_TV_0:
+ case DCB_CONNECTOR_TV_1:
+ case DCB_CONNECTOR_TV_3:
+ case DCB_CONNECTOR_VGA:
+ break;
+ default:
if (disp->dithering_mode) {
- nv_connector->dithering_mode = DITHERING_MODE_AUTO;
drm_object_attach_property(&connector->base,
- disp->dithering_mode,
- nv_connector->dithering_mode);
+ disp->dithering_mode,
+ nv_connector->
+ dithering_mode);
+ nv_connector->dithering_mode = DITHERING_MODE_AUTO;
}
if (disp->dithering_depth) {
- nv_connector->dithering_depth = DITHERING_DEPTH_AUTO;
drm_object_attach_property(&connector->base,
- disp->dithering_depth,
- nv_connector->dithering_depth);
+ disp->dithering_depth,
+ nv_connector->
+ dithering_depth);
+ nv_connector->dithering_depth = DITHERING_DEPTH_AUTO;
}
break;
}
From 0ea5fe8a83c2d1d59bcf1a59ba685a6452c41205 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Mon, 22 Dec 2014 18:19:45 +1000
Subject: [PATCH 24/86] drm/nouveau/kms: default to panel scaling, except for
fixed panels prior to nv50
On NV50 and up, we'll allow fixed panels to use EDID-provided modes
without the GPU scaler, and force scaling (even for NONE) otherwise.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/nouveau_connector.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 938de24da7dd..9c871f93cc1e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -1199,14 +1199,18 @@ nouveau_connector_create(struct drm_device *dev, int index)
/* default scaling mode */
switch (nv_connector->type) {
- case DCB_CONNECTOR_TV_0:
- case DCB_CONNECTOR_TV_1:
- case DCB_CONNECTOR_TV_3:
- case DCB_CONNECTOR_VGA:
+ case DCB_CONNECTOR_LVDS:
+ case DCB_CONNECTOR_LVDS_SPWG:
+ case DCB_CONNECTOR_eDP:
+ /* see note in nouveau_connector_set_property() */
+ if (disp->disp.oclass < NV50_DISP) {
+ nv_connector->scaling_mode = DRM_MODE_SCALE_FULLSCREEN;
+ break;
+ }
nv_connector->scaling_mode = DRM_MODE_SCALE_NONE;
break;
default:
- nv_connector->scaling_mode = DRM_MODE_SCALE_FULLSCREEN;
+ nv_connector->scaling_mode = DRM_MODE_SCALE_NONE;
break;
}
From 9ba8310647fc39d95c2a1ebb974fc189e74b11d4 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Mon, 22 Dec 2014 19:50:23 +1000
Subject: [PATCH 25/86] drm/nv50-/kms: reject attempts at flipping to
incompatible framebuffer
Looks like a userspace bug can trigger this somehow during a mode
switch, causing: EVO complaint -> semaphores get out of sync ->
entire display stalled.
We likely want to be even stricter than this (or at least deal
better if EVO rejects our request), but I'll save that for the
drm_plane/atomic conversion and just fix the bug that I already
know can be triggered.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/nv50_display.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 85cc667cfb0f..fcbbf3884781 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -550,6 +550,10 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
u32 *push;
int ret;
+ if (crtc->primary->fb->width != fb->width ||
+ crtc->primary->fb->height != fb->height)
+ return -EINVAL;
+
swap_interval <<= 4;
if (swap_interval == 0)
swap_interval |= 0x100;
From 9509ff759fb550194003507d143110388e3c8857 Mon Sep 17 00:00:00 2001
From: Vince Hsu <vinceh@nvidia.com>
Date: Tue, 30 Dec 2014 14:59:42 +0800
Subject: [PATCH 26/86] drm/nouveau/mc: add missing braces
Several braces were misplaced unintentionally. That caused the msi handling
became part of the default case of the first switch statement. So add the
missing ones.
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/subdev/mc/base.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c
index ca7cee3a314a..25e3b9644a3f 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c
@@ -124,7 +124,7 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
pmc->unk260 = nouveau_mc_unk260;
- if (nv_device_is_pci(device))
+ if (nv_device_is_pci(device)) {
switch (device->pdev->device & 0x0ff0) {
case 0x00f0:
case 0x02e0:
@@ -138,6 +138,7 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
default:
pmc->use_msi = true;
break;
+ }
}
pmc->use_msi = nouveau_boolopt(device->cfgopt, "NvMSI",
From f8a8546194d7794c309d2d8114f457f4f921afad Mon Sep 17 00:00:00 2001
From: Vince Hsu <vinceh@nvidia.com>
Date: Mon, 22 Dec 2014 17:11:37 +0800
Subject: [PATCH 27/86] drm/nouveau/clk: allow non-blocking for
nouveau_clock_astate()
There might be some callers of nouveau_clock_astate(), and they are from
inetrrupt context. So we must ensure that this function can be atomic in
that condition. This patch adds one parameter which is subsequently passed
to nouveau_pstate_calc(). Therefore we can choose whether we want to wait
for the pstate work's completion or not.
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/include/subdev/clock.h | 2 +-
drivers/gpu/drm/nouveau/core/subdev/clock/base.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
index 0fd5e4a3a7a2..39ad2d2cee2a 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
@@ -159,7 +159,7 @@ int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
int clk, struct nouveau_pll_vals *);
int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr);
-int nouveau_clock_astate(struct nouveau_clock *, int req, int rel);
+int nouveau_clock_astate(struct nouveau_clock *, int req, int rel, bool wait);
int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel);
int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
index e51b72d47129..b1bbe764fa35 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
@@ -430,13 +430,13 @@ nouveau_clock_ustate(struct nouveau_clock *clk, int req, int pwr)
}
int
-nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel)
+nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel, bool wait)
{
if (!rel) clk->astate = req;
if ( rel) clk->astate += rel;
clk->astate = min(clk->astate, clk->state_nr - 1);
clk->astate = max(clk->astate, 0);
- return nouveau_pstate_calc(clk, true);
+ return nouveau_pstate_calc(clk, wait);
}
int
From 47e7df39d9fb74fa11bd4b4453fc34d231b2169c Mon Sep 17 00:00:00 2001
From: Vince Hsu <vinceh@nvidia.com>
Date: Mon, 22 Dec 2014 17:11:38 +0800
Subject: [PATCH 28/86] drm/nouveau/pwr: make nouveau_pwr_pgob() non-static
The platform device does not use the common nouveau_pwr_init() to initialize
the PWR, but it does need the .pgob() be assigned to avoid NULL pointer
dereference in graph/nve4.c.
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/subdev/pwr/base.c | 2 +-
drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
index 0ab55f27ec45..1ea433a5e118 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
@@ -26,7 +26,7 @@
#include "priv.h"
-static void
+void
nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable)
{
const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h
index 3814a341db32..86149d9a440c 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h
@@ -26,6 +26,7 @@ int _nouveau_pwr_ctor(struct nouveau_object *, struct nouveau_object *,
#define _nouveau_pwr_dtor _nouveau_subdev_dtor
int _nouveau_pwr_init(struct nouveau_object *);
int _nouveau_pwr_fini(struct nouveau_object *, bool);
+void nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable);
struct nvkm_pwr_impl {
struct nouveau_oclass base;
From 9f7fd620af29d4501ed063333824562656d46da5 Mon Sep 17 00:00:00 2001
From: Vince Hsu <vinceh@nvidia.com>
Date: Mon, 22 Dec 2014 17:11:39 +0800
Subject: [PATCH 29/86] drm/nouveau/pwr: add support for GK20A
This patch adds PWR support for GK20A. But instead of adding the PWR
features like firmware loading and communication with PMU firmware, we
add the DVFS (Dynamic Voltage and Frequency Scaling), which is one of
the PMU firmware's jobs on dGPUs, in this patch. This refers to the
idle signals provided by the NVIDIA hardware and tries to adjust the
performance level based on the calculated target. The reclocking policy
can be fine-tuned later when we have more real use cases.
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/Makefile | 1 +
.../gpu/drm/nouveau/core/engine/device/nve0.c | 1 +
.../gpu/drm/nouveau/core/include/subdev/pwr.h | 1 +
.../gpu/drm/nouveau/core/subdev/pwr/gk20a.c | 232 ++++++++++++++++++
4 files changed, 235 insertions(+)
create mode 100644 drivers/gpu/drm/nouveau/core/subdev/pwr/gk20a.c
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 6461e3565afe..ba6b660d3316 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -201,6 +201,7 @@ nouveau-y += core/subdev/pwr/nvc0.o
nouveau-y += core/subdev/pwr/nvd0.o
nouveau-y += core/subdev/pwr/gk104.o
nouveau-y += core/subdev/pwr/nv108.o
+nouveau-y += core/subdev/pwr/gk20a.o
nouveau-y += core/subdev/therm/base.o
nouveau-y += core/subdev/therm/fan.o
nouveau-y += core/subdev/therm/fannil.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index 732922690653..d308aee028f0 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -180,6 +180,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
+ device->oclass[NVDEV_SUBDEV_PWR ] = gk20a_pwr_oclass;
break;
case 0xf0:
device->cname = "GK110";
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
index ef57c85405ff..83f85ac153ef 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
@@ -38,6 +38,7 @@ extern struct nouveau_oclass *nvc0_pwr_oclass;
extern struct nouveau_oclass *nvd0_pwr_oclass;
extern struct nouveau_oclass *gk104_pwr_oclass;
extern struct nouveau_oclass *nv108_pwr_oclass;
+extern struct nouveau_oclass *gk20a_pwr_oclass;
/* interface to MEMX process running on PPWR */
struct nouveau_memx;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/gk20a.c
new file mode 100644
index 000000000000..f6b7df1b1686
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/gk20a.c
@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include "priv.h"
+
+#include <subdev/clock.h>
+#include <subdev/timer.h>
+#include <subdev/volt.h>
+
+#define BUSY_SLOT 0
+#define CLK_SLOT 7
+
+struct gk20a_pwr_dvfs_data {
+ int p_load_target;
+ int p_load_max;
+ int p_smooth;
+ unsigned int avg_load;
+};
+
+struct gk20a_pwr_priv {
+ struct nouveau_pwr base;
+ struct nouveau_alarm alarm;
+ struct gk20a_pwr_dvfs_data *data;
+};
+
+struct gk20a_pwr_dvfs_dev_status {
+ unsigned long total;
+ unsigned long busy;
+ int cur_state;
+};
+
+static int
+gk20a_pwr_dvfs_target(struct gk20a_pwr_priv *priv, int *state)
+{
+ struct nouveau_clock *clk = nouveau_clock(priv);
+
+ return nouveau_clock_astate(clk, *state, 0, false);
+}
+
+static int
+gk20a_pwr_dvfs_get_cur_state(struct gk20a_pwr_priv *priv, int *state)
+{
+ struct nouveau_clock *clk = nouveau_clock(priv);
+
+ *state = clk->pstate;
+ return 0;
+}
+
+static int
+gk20a_pwr_dvfs_get_target_state(struct gk20a_pwr_priv *priv,
+ int *state, int load)
+{
+ struct gk20a_pwr_dvfs_data *data = priv->data;
+ struct nouveau_clock *clk = nouveau_clock(priv);
+ int cur_level, level;
+
+ /* For GK20A, the performance level is directly mapped to pstate */
+ level = cur_level = clk->pstate;
+
+ if (load > data->p_load_max) {
+ level = min(clk->state_nr - 1, level + (clk->state_nr / 3));
+ } else {
+ level += ((load - data->p_load_target) * 10 /
+ data->p_load_target) / 2;
+ level = max(0, level);
+ level = min(clk->state_nr - 1, level);
+ }
+
+ nv_trace(priv, "cur level = %d, new level = %d\n", cur_level, level);
+
+ *state = level;
+
+ if (level == cur_level)
+ return 0;
+ else
+ return 1;
+}
+
+static int
+gk20a_pwr_dvfs_get_dev_status(struct gk20a_pwr_priv *priv,
+ struct gk20a_pwr_dvfs_dev_status *status)
+{
+ status->busy = nv_rd32(priv, 0x10a508 + (BUSY_SLOT * 0x10));
+ status->total= nv_rd32(priv, 0x10a508 + (CLK_SLOT * 0x10));
+ return 0;
+}
+
+static void
+gk20a_pwr_dvfs_reset_dev_status(struct gk20a_pwr_priv *priv)
+{
+ nv_wr32(priv, 0x10a508 + (BUSY_SLOT * 0x10), 0x80000000);
+ nv_wr32(priv, 0x10a508 + (CLK_SLOT * 0x10), 0x80000000);
+}
+
+static void
+gk20a_pwr_dvfs_work(struct nouveau_alarm *alarm)
+{
+ struct gk20a_pwr_priv *priv = container_of(alarm,
+ struct gk20a_pwr_priv, alarm);
+ struct gk20a_pwr_dvfs_data *data = priv->data;
+ struct gk20a_pwr_dvfs_dev_status status;
+ struct nouveau_clock *clk = nouveau_clock(priv);
+ struct nouveau_volt *volt = nouveau_volt(priv);
+ u32 utilization = 0;
+ int state, ret;
+
+ /*
+ * The PWR is initialized before CLK and VOLT, so we have to make sure the
+ * CLK and VOLT are ready here.
+ */
+ if (!clk || !volt)
+ goto resched;
+
+ ret = gk20a_pwr_dvfs_get_dev_status(priv, &status);
+ if (ret) {
+ nv_warn(priv, "failed to get device status\n");
+ goto resched;
+ }
+
+ if (status.total)
+ utilization = div_u64((u64)status.busy * 100, status.total);
+
+ data->avg_load = (data->p_smooth * data->avg_load) + utilization;
+ data->avg_load /= data->p_smooth + 1;
+ nv_trace(priv, "utilization = %d %%, avg_load = %d %%\n",
+ utilization, data->avg_load);
+
+ ret = gk20a_pwr_dvfs_get_cur_state(priv, &state);
+ if (ret) {
+ nv_warn(priv, "failed to get current state\n");
+ goto resched;
+ }
+
+ if (gk20a_pwr_dvfs_get_target_state(priv, &state, data->avg_load)) {
+ nv_trace(priv, "set new state to %d\n", state);
+ gk20a_pwr_dvfs_target(priv, &state);
+ }
+
+resched:
+ gk20a_pwr_dvfs_reset_dev_status(priv);
+ nouveau_timer_alarm(priv, 100000000, alarm);
+}
+
+int
+gk20a_pwr_fini(struct nouveau_object *object, bool suspend)
+{
+ struct nouveau_pwr *ppwr = (void *)object;
+ struct gk20a_pwr_priv *priv = (void *)ppwr;
+
+ nouveau_timer_alarm_cancel(priv, &priv->alarm);
+
+ return nouveau_subdev_fini(&ppwr->base, suspend);
+}
+
+int
+gk20a_pwr_init(struct nouveau_object *object)
+{
+ struct nouveau_pwr *ppwr = (void *)object;
+ struct gk20a_pwr_priv *priv = (void *)ppwr;
+ int ret;
+
+ ret = nouveau_subdev_init(&ppwr->base);
+ if (ret)
+ return ret;
+
+ ppwr->pgob = nouveau_pwr_pgob;
+
+ /* init pwr perf counter */
+ nv_wr32(ppwr, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001);
+ nv_wr32(ppwr, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002);
+ nv_wr32(ppwr, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
+
+ nouveau_timer_alarm(ppwr, 2000000000, &priv->alarm);
+
+ return ret;
+}
+
+struct gk20a_pwr_dvfs_data gk20a_dvfs_data= {
+ .p_load_target = 70,
+ .p_load_max = 90,
+ .p_smooth = 1,
+};
+
+static int
+gk20a_pwr_ctor(struct nouveau_object *parent,
+ struct nouveau_object *engine,
+ struct nouveau_oclass *oclass, void *data, u32 size,
+ struct nouveau_object **pobject)
+{
+ struct gk20a_pwr_priv *priv;
+ int ret;
+
+ ret = nouveau_pwr_create(parent, engine, oclass, &priv);
+ *pobject = nv_object(priv);
+ if (ret)
+ return ret;
+
+ priv->data = &gk20a_dvfs_data;
+
+ nouveau_alarm_init(&priv->alarm, gk20a_pwr_dvfs_work);
+
+ return 0;
+}
+
+struct nouveau_oclass *
+gk20a_pwr_oclass = &(struct nvkm_pwr_impl) {
+ .base.handle = NV_SUBDEV(PWR, 0xea),
+ .base.ofuncs = &(struct nouveau_ofuncs) {
+ .ctor = gk20a_pwr_ctor,
+ .dtor = _nouveau_pwr_dtor,
+ .init = gk20a_pwr_init,
+ .fini = gk20a_pwr_fini,
+ },
+}.base;
From 9f79b5ce127dfa1241c2e23e40f900b998806a2c Mon Sep 17 00:00:00 2001
From: Vince Hsu <vinceh@nvidia.com>
Date: Mon, 22 Dec 2014 17:11:40 +0800
Subject: [PATCH 30/86] drm/nouveau/clk: allow users to enable auto mode when
loading driver
This patch adds one option for the boot config strings "NvClkMode*", so
that we can enable the "auto" mode when loading module.
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/core/subdev/clock/base.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
index b1bbe764fa35..bc095b470121 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
@@ -401,6 +401,9 @@ nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen)
{
int ret = 1;
+ if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen))
+ return -2;
+
if (strncasecmpz(mode, "disabled", arglen)) {
char save = mode[arglen];
long v;
From 26b40d81d7e3fb9e5022e0abccf1566554484c07 Mon Sep 17 00:00:00 2001
From: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Date: Sun, 11 Jan 2015 23:31:35 +0100
Subject: [PATCH 31/86] drm/nouveau/bo: Remove unused function
Remove the function nouveau_bo_rd16() that is not used anywhere.
This was partially found by using a static code analysis program
called cppcheck.
Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 14 --------------
drivers/gpu/drm/nouveau/nouveau_bo.h | 1 -
2 files changed, 15 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index bba2960d3dfb..d96fe3524dbd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -533,20 +533,6 @@ _nouveau_bo_mem_index(struct nouveau_bo *nvbo, unsigned index, void *mem, u8 sz)
}
#define nouveau_bo_mem_index(o, i, m) _nouveau_bo_mem_index(o, i, m, sizeof(*m))
-u16
-nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
-{
- bool is_iomem;
- u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
-
- mem = nouveau_bo_mem_index(nvbo, index, mem);
-
- if (is_iomem)
- return ioread16_native((void __force __iomem *)mem);
- else
- return *mem;
-}
-
void
nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
{
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h
index 072222efeeb7..302aa63b81a4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.h
@@ -78,7 +78,6 @@ int nouveau_bo_unpin(struct nouveau_bo *);
int nouveau_bo_map(struct nouveau_bo *);
void nouveau_bo_unmap(struct nouveau_bo *);
void nouveau_bo_placement_set(struct nouveau_bo *, u32 type, u32 busy);
-u16 nouveau_bo_rd16(struct nouveau_bo *, unsigned index);
void nouveau_bo_wr16(struct nouveau_bo *, unsigned index, u16 val);
u32 nouveau_bo_rd32(struct nouveau_bo *, unsigned index);
void nouveau_bo_wr32(struct nouveau_bo *, unsigned index, u32 val);
From 1119eef0fd4c440a7eae2f1ff174e809d9f129e6 Mon Sep 17 00:00:00 2001
From: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Date: Sun, 11 Jan 2015 14:58:05 +0100
Subject: [PATCH 32/86] drm/nouveau/gem: Remove unused function
Remove the function domain_to_ttm() that is not used anywhere.
This was partially found by using a static code analysis program
called cppcheck.
Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/nouveau_gem.c | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index bf0f9e21d714..9eb8af4daeeb 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -850,19 +850,6 @@ out_next:
return nouveau_abi16_put(abi16, ret);
}
-static inline uint32_t
-domain_to_ttm(struct nouveau_bo *nvbo, uint32_t domain)
-{
- uint32_t flags = 0;
-
- if (domain & NOUVEAU_GEM_DOMAIN_VRAM)
- flags |= TTM_PL_FLAG_VRAM;
- if (domain & NOUVEAU_GEM_DOMAIN_GART)
- flags |= TTM_PL_FLAG_TT;
-
- return flags;
-}
-
int
nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data,
struct drm_file *file_priv)
From 4d8bb03bced49526304592728002ebea54c7f224 Mon Sep 17 00:00:00 2001
From: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Date: Sun, 11 Jan 2015 23:36:47 +0100
Subject: [PATCH 33/86] drm/nouveau/dispnv04: Remove some unused functions
Removes some functions that are not used anywhere:
nv04_display_late_takedown() nv04_display_early_init()
This was partially found by using a static code analysis program
called cppcheck.
Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/dispnv04/disp.c | 18 ------------------
drivers/gpu/drm/nouveau/dispnv04/disp.h | 2 --
2 files changed, 20 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c
index 3d0afa1c6cff..bdf7cf49afcd 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c
@@ -31,24 +31,6 @@
#include "nouveau_encoder.h"
#include "nouveau_connector.h"
-int
-nv04_display_early_init(struct drm_device *dev)
-{
- /* ensure vblank interrupts are off, they can't be enabled until
- * drm_vblank has been initialised
- */
- NVWriteCRTC(dev, 0, NV_PCRTC_INTR_EN_0, 0);
- if (nv_two_heads(dev))
- NVWriteCRTC(dev, 1, NV_PCRTC_INTR_EN_0, 0);
-
- return 0;
-}
-
-void
-nv04_display_late_takedown(struct drm_device *dev)
-{
-}
-
int
nv04_display_create(struct drm_device *dev)
{
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h b/drivers/gpu/drm/nouveau/dispnv04/disp.h
index 17b899d9aba3..3ad3ee818c1a 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/disp.h
+++ b/drivers/gpu/drm/nouveau/dispnv04/disp.h
@@ -90,8 +90,6 @@ nv04_display(struct drm_device *dev)
}
/* nv04_display.c */
-int nv04_display_early_init(struct drm_device *);
-void nv04_display_late_takedown(struct drm_device *);
int nv04_display_create(struct drm_device *);
void nv04_display_destroy(struct drm_device *);
int nv04_display_init(struct drm_device *);
From 4dc63933ea518501fe9cfe6a8f8797d21095e76f Mon Sep 17 00:00:00 2001
From: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Date: Tue, 13 Jan 2015 09:18:49 +0100
Subject: [PATCH 34/86] drm/nouveau: dont switch vt on suspend
Restore the nv50 cursor bo on resume, and load the lut in
nv50_display_display_init so it gets set on resume too.
Tested on a fermi and a curie.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@ubuntu.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/nouveau_display.c | 9 +++--
drivers/gpu/drm/nouveau/nouveau_fbcon.c | 23 +++---------
drivers/gpu/drm/nouveau/nouveau_fbcon.h | 1 -
drivers/gpu/drm/nouveau/nv50_display.c | 43 ++++++++++++++---------
4 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index f8042433752b..f972e9c1a23a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -570,7 +570,8 @@ nouveau_display_suspend(struct drm_device *dev, bool runtime)
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
if (nv_crtc->cursor.nvbo) {
- nouveau_bo_unmap(nv_crtc->cursor.nvbo);
+ if (nv_crtc->cursor.set_offset)
+ nouveau_bo_unmap(nv_crtc->cursor.nvbo);
nouveau_bo_unpin(nv_crtc->cursor.nvbo);
}
}
@@ -604,7 +605,7 @@ nouveau_display_resume(struct drm_device *dev, bool runtime)
continue;
ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, true);
- if (!ret)
+ if (!ret && nv_crtc->cursor.set_offset)
ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
if (ret)
NV_ERROR(drm, "Could not pin/map cursor.\n");
@@ -637,7 +638,9 @@ nouveau_display_resume(struct drm_device *dev, bool runtime)
if (!nv_crtc->cursor.nvbo)
continue;
- nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset);
+
+ if (nv_crtc->cursor.set_offset)
+ nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset);
nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
nv_crtc->cursor_saved_y);
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 3ed12a8cfc91..d6e6958bc5f8 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -370,6 +370,7 @@ nouveau_fbcon_create(struct drm_fb_helper *helper,
ret = -ENOMEM;
goto out_unlock;
}
+ info->skip_vt_switch = 1;
ret = fb_alloc_cmap(&info->cmap, 256, 0);
if (ret) {
@@ -487,30 +488,17 @@ static const struct drm_fb_helper_funcs nouveau_fbcon_helper_funcs = {
.fb_probe = nouveau_fbcon_create,
};
-static void
-nouveau_fbcon_set_suspend_work(struct work_struct *work)
-{
- struct nouveau_fbdev *fbcon = container_of(work, typeof(*fbcon), work);
- console_lock();
- nouveau_fbcon_accel_restore(fbcon->dev);
- nouveau_fbcon_zfill(fbcon->dev, fbcon);
- fb_set_suspend(fbcon->helper.fbdev, FBINFO_STATE_RUNNING);
- console_unlock();
-}
-
void
nouveau_fbcon_set_suspend(struct drm_device *dev, int state)
{
struct nouveau_drm *drm = nouveau_drm(dev);
if (drm->fbcon) {
- if (state == FBINFO_STATE_RUNNING) {
- schedule_work(&drm->fbcon->work);
- return;
- }
- flush_work(&drm->fbcon->work);
console_lock();
+ if (state == FBINFO_STATE_RUNNING)
+ nouveau_fbcon_accel_restore(dev);
fb_set_suspend(drm->fbcon->helper.fbdev, state);
- nouveau_fbcon_accel_save_disable(dev);
+ if (state != FBINFO_STATE_RUNNING)
+ nouveau_fbcon_accel_save_disable(dev);
console_unlock();
}
}
@@ -531,7 +519,6 @@ nouveau_fbcon_init(struct drm_device *dev)
if (!fbcon)
return -ENOMEM;
- INIT_WORK(&fbcon->work, nouveau_fbcon_set_suspend_work);
fbcon->dev = dev;
drm->fbcon = fbcon;
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
index 6208e70e4a1c..1e2e9e27a03b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
@@ -36,7 +36,6 @@ struct nouveau_fbdev {
struct nouveau_framebuffer nouveau_fb;
struct list_head fbdev_list;
struct drm_device *dev;
- struct work_struct work;
unsigned int saved_flags;
struct nvif_object surf2d;
struct nvif_object clip;
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index fcbbf3884781..113e8cdb0b2b 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -125,7 +125,6 @@ nv50_pioc_create(struct nvif_object *disp, const u32 *oclass, u8 head,
struct nv50_curs {
struct nv50_pioc base;
- struct nouveau_bo *image;
};
static int
@@ -924,29 +923,29 @@ static void
nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
{
struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
- struct nv50_curs *curs = nv50_curs(&nv_crtc->base);
u32 *push = evo_wait(mast, 16);
if (push) {
if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
evo_data(push, 0x85000000);
- evo_data(push, curs->image->bo.offset >> 8);
+ evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
} else
if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
evo_data(push, 0x85000000);
- evo_data(push, curs->image->bo.offset >> 8);
+ evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
evo_data(push, mast->base.vram.handle);
} else {
evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
evo_data(push, 0x85000000);
- evo_data(push, curs->image->bo.offset >> 8);
+ evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
evo_data(push, mast->base.vram.handle);
}
evo_kick(push, mast);
}
+ nv_crtc->cursor.visible = true;
}
static void
@@ -972,15 +971,15 @@ nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
}
evo_kick(push, mast);
}
+ nv_crtc->cursor.visible = false;
}
static void
nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
{
struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
- struct nv50_curs *curs = nv50_curs(&nv_crtc->base);
- if (show && curs->image)
+ if (show && nv_crtc->cursor.nvbo)
nv50_crtc_cursor_show(nv_crtc);
else
nv50_crtc_cursor_hide(nv_crtc);
@@ -1280,7 +1279,6 @@ nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
uint32_t handle, uint32_t width, uint32_t height)
{
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
- struct nv50_curs *curs = nv50_curs(crtc);
struct drm_device *dev = crtc->dev;
struct drm_gem_object *gem = NULL;
struct nouveau_bo *nvbo = NULL;
@@ -1299,9 +1297,9 @@ nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
}
if (ret == 0) {
- if (curs->image)
- nouveau_bo_unpin(curs->image);
- nouveau_bo_ref(nvbo, &curs->image);
+ if (nv_crtc->cursor.nvbo)
+ nouveau_bo_unpin(nv_crtc->cursor.nvbo);
+ nouveau_bo_ref(nvbo, &nv_crtc->cursor.nvbo);
}
drm_gem_object_unreference_unlocked(gem);
@@ -1312,10 +1310,14 @@ nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
static int
nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
{
+ struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct nv50_curs *curs = nv50_curs(crtc);
struct nv50_chan *chan = nv50_chan(curs);
nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
nvif_wr32(&chan->user, 0x0080, 0x00000000);
+
+ nv_crtc->cursor_saved_x = x;
+ nv_crtc->cursor_saved_y = y;
return 0;
}
@@ -1336,6 +1338,14 @@ nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
nv50_crtc_lut_load(crtc);
}
+static void
+nv50_crtc_cursor_restore(struct nouveau_crtc *nv_crtc, int x, int y)
+{
+ nv50_crtc_cursor_move(&nv_crtc->base, x, y);
+
+ nv50_crtc_cursor_show_hide(nv_crtc, true, true);
+}
+
static void
nv50_crtc_destroy(struct drm_crtc *crtc)
{
@@ -1361,9 +1371,9 @@ nv50_crtc_destroy(struct drm_crtc *crtc)
nouveau_bo_ref(NULL, &head->image);
/*XXX: ditto */
- if (head->curs.image)
- nouveau_bo_unpin(head->curs.image);
- nouveau_bo_ref(NULL, &head->curs.image);
+ if (nv_crtc->cursor.nvbo)
+ nouveau_bo_unpin(nv_crtc->cursor.nvbo);
+ nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
nouveau_bo_unmap(nv_crtc->lut.nvbo);
if (nv_crtc->lut.nvbo)
@@ -1413,6 +1423,7 @@ nv50_crtc_create(struct drm_device *dev, int index)
head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
head->base.color_vibrance = 50;
head->base.vibrant_hue = 0;
+ head->base.cursor.set_pos = nv50_crtc_cursor_restore;
for (i = 0; i < 256; i++) {
head->base.lut.r[i] = i << 8;
head->base.lut.g[i] = i << 8;
@@ -1440,8 +1451,6 @@ nv50_crtc_create(struct drm_device *dev, int index)
if (ret)
goto out;
- nv50_crtc_lut_load(crtc);
-
/* allocate cursor resources */
ret = nv50_curs_create(disp->disp, index, &head->curs);
if (ret)
@@ -2419,6 +2428,8 @@ nv50_display_init(struct drm_device *dev)
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
struct nv50_sync *sync = nv50_sync(crtc);
+
+ nv50_crtc_lut_load(crtc);
nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
}
From 055a65d5987a7f246c3fc2297158286882dbdbcf Mon Sep 17 00:00:00 2001
From: Alexandre Courbot <acourbot@nvidia.com>
Date: Thu, 15 Jan 2015 15:29:56 +0900
Subject: [PATCH 35/86] drm/nouveau: merge nouveau_platform.ko into nouveau.ko
Having the two modules separated causes various unneeded complications,
including having to export symbols accessed between the modules. Make
things simpler by compiling platform device support into nouveau.ko.
Platform device support remains optional and is only compiled on Tegra.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Vince Hsu <vinceh@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/Kconfig | 2 +-
drivers/gpu/drm/nouveau/Makefile | 3 +--
drivers/gpu/drm/nouveau/nouveau_drm.c | 11 +++++++++--
drivers/gpu/drm/nouveau/nouveau_platform.c | 6 ------
drivers/gpu/drm/nouveau/nouveau_platform.h | 3 +++
5 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig
index 40afc69a3778..5ab13e7939db 100644
--- a/drivers/gpu/drm/nouveau/Kconfig
+++ b/drivers/gpu/drm/nouveau/Kconfig
@@ -26,7 +26,7 @@ config DRM_NOUVEAU
Choose this option for open-source NVIDIA support.
config NOUVEAU_PLATFORM_DRIVER
- tristate "Nouveau (NVIDIA) SoC GPUs"
+ bool "Nouveau (NVIDIA) SoC GPUs"
depends on DRM_NOUVEAU && ARCH_TEGRA
default y
help
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index ba6b660d3316..1febf6ec0b69 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -394,8 +394,7 @@ nouveau-$(CONFIG_ACPI) += nouveau_acpi.o
endif
nouveau-$(CONFIG_DRM_NOUVEAU_BACKLIGHT) += nouveau_backlight.o
nouveau-$(CONFIG_DEBUG_FS) += nouveau_debugfs.o
+nouveau-$(CONFIG_NOUVEAU_PLATFORM_DRIVER) += nouveau_platform.o
obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o
-# platform driver
-obj-$(CONFIG_NOUVEAU_PLATFORM_DRIVER) += nouveau_platform.o
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 65910e3aed0c..1118efa56817 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -52,6 +52,7 @@
#include "nouveau_debugfs.h"
#include "nouveau_usif.h"
#include "nouveau_connector.h"
+#include "nouveau_platform.h"
MODULE_PARM_DESC(config, "option string to pass to driver core");
static char *nouveau_config;
@@ -533,7 +534,6 @@ nouveau_drm_device_remove(struct drm_device *dev)
nouveau_object_ref(NULL, &device);
nouveau_object_debug();
}
-EXPORT_SYMBOL(nouveau_drm_device_remove);
static void
nouveau_drm_remove(struct pci_dev *pdev)
@@ -1083,7 +1083,6 @@ err_free:
return ERR_PTR(err);
}
-EXPORT_SYMBOL(nouveau_platform_device_create_);
static int __init
nouveau_drm_init(void)
@@ -1105,6 +1104,10 @@ nouveau_drm_init(void)
if (!nouveau_modeset)
return 0;
+#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
+ platform_driver_register(&nouveau_platform_driver);
+#endif
+
nouveau_register_dsm_handler();
return drm_pci_init(&driver_pci, &nouveau_drm_pci_driver);
}
@@ -1117,6 +1120,10 @@ nouveau_drm_exit(void)
drm_pci_exit(&driver_pci, &nouveau_drm_pci_driver);
nouveau_unregister_dsm_handler();
+
+#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
+ platform_driver_unregister(&nouveau_platform_driver);
+#endif
}
module_init(nouveau_drm_init);
diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.c b/drivers/gpu/drm/nouveau/nouveau_platform.c
index b307bbedd4c4..34d78b288f97 100644
--- a/drivers/gpu/drm/nouveau/nouveau_platform.c
+++ b/drivers/gpu/drm/nouveau/nouveau_platform.c
@@ -177,9 +177,3 @@ struct platform_driver nouveau_platform_driver = {
.probe = nouveau_platform_probe,
.remove = nouveau_platform_remove,
};
-
-module_platform_driver(nouveau_platform_driver);
-
-MODULE_AUTHOR(DRIVER_AUTHOR);
-MODULE_DESCRIPTION(DRIVER_DESC);
-MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.h b/drivers/gpu/drm/nouveau/nouveau_platform.h
index 58c28b5653d5..ca22c525329a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_platform.h
+++ b/drivers/gpu/drm/nouveau/nouveau_platform.h
@@ -28,6 +28,7 @@
struct reset_control;
struct clk;
struct regulator;
+struct platform_driver;
struct nouveau_platform_gpu {
struct reset_control *rst;
@@ -48,4 +49,6 @@ struct nouveau_platform_device {
#define nv_device_to_platform(d) \
container_of(d, struct nouveau_platform_device, device)
+extern struct platform_driver nouveau_platform_driver;
+
#endif
From c39f472e9f14e49a9bc091977ced0ec45fc00c57 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Tue, 13 Jan 2015 22:13:14 +1000
Subject: [PATCH 36/86] drm/nouveau: remove symlinks, move core/ to nvkm/ (no
code changes)
The symlinks were annoying some people, and they're not used anywhere
else in the kernel tree. The include directory structure has been
changed so that symlinks aren't needed anymore.
NVKM has been moved from core/ to nvkm/ to make it more obvious as to
what the directory is for, and as some minor prep for when NVKM gets
split out into its own module (virt) at a later date.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/Kbuild | 66 +++
drivers/gpu/drm/nouveau/Makefile | 400 ------------------
.../gpu/drm/nouveau/core/include/nvif/class.h | 1 -
.../gpu/drm/nouveau/core/include/nvif/event.h | 1 -
.../gpu/drm/nouveau/core/include/nvif/ioctl.h | 1 -
.../drm/nouveau/core/include/nvif/unpack.h | 1 -
.../drm/nouveau/dispnv04/{Makefile => Kbuild} | 0
.../drm/nouveau/{ => include}/nvif/class.h | 0
.../drm/nouveau/{ => include}/nvif/client.h | 2 +-
.../drm/nouveau/{ => include}/nvif/device.h | 4 +-
.../drm/nouveau/{ => include}/nvif/driver.h | 0
.../drm/nouveau/{ => include}/nvif/event.h | 0
.../drm/nouveau/{ => include}/nvif/ioctl.h | 0
.../gpu/drm/nouveau/{ => include}/nvif/list.h | 0
.../drm/nouveau/{ => include}/nvif/notify.h | 0
.../drm/nouveau/{ => include}/nvif/object.h | 0
.../drm/nouveau/{core => include/nvif}/os.h | 0
.../drm/nouveau/{ => include}/nvif/unpack.h | 0
.../include => include/nvkm}/core/client.h | 0
.../include => include/nvkm}/core/debug.h | 0
.../include => include/nvkm}/core/device.h | 0
.../include => include/nvkm}/core/engctx.h | 0
.../include => include/nvkm}/core/engine.h | 0
.../include => include/nvkm}/core/enum.h | 0
.../include => include/nvkm}/core/event.h | 0
.../include => include/nvkm}/core/gpuobj.h | 0
.../include => include/nvkm}/core/handle.h | 0
.../include => include/nvkm}/core/ioctl.h | 0
.../{core/include => include/nvkm}/core/mm.h | 0
.../include => include/nvkm}/core/namedb.h | 0
.../include => include/nvkm}/core/notify.h | 0
.../include => include/nvkm}/core/object.h | 0
.../include => include/nvkm}/core/option.h | 0
.../gpu/drm/nouveau/include/nvkm/core/os.h | 4 +
.../include => include/nvkm}/core/parent.h | 0
.../include => include/nvkm}/core/printk.h | 0
.../include => include/nvkm}/core/ramht.h | 0
.../include => include/nvkm}/core/subdev.h | 0
.../include => include/nvkm}/engine/bsp.h | 0
.../include => include/nvkm}/engine/copy.h | 0
.../include => include/nvkm}/engine/crypt.h | 0
.../include => include/nvkm}/engine/device.h | 0
.../include => include/nvkm}/engine/disp.h | 0
.../include => include/nvkm}/engine/dmaobj.h | 0
.../include => include/nvkm}/engine/falcon.h | 0
.../include => include/nvkm}/engine/fifo.h | 0
.../include => include/nvkm}/engine/graph.h | 0
.../include => include/nvkm}/engine/mpeg.h | 0
.../include => include/nvkm}/engine/perfmon.h | 0
.../include => include/nvkm}/engine/ppp.h | 0
.../nvkm}/engine/software.h | 0
.../include => include/nvkm}/engine/vp.h | 0
.../include => include/nvkm}/engine/xtensa.h | 0
.../include => include/nvkm}/subdev/bar.h | 0
.../include => include/nvkm}/subdev/bios.h | 0
.../nvkm}/subdev/bios/M0203.h | 0
.../nvkm}/subdev/bios/M0205.h | 0
.../nvkm}/subdev/bios/M0209.h | 0
.../nvkm}/subdev/bios/P0260.h | 0
.../nvkm}/subdev/bios/bit.h | 0
.../nvkm}/subdev/bios/bmp.h | 0
.../nvkm}/subdev/bios/boost.h | 0
.../nvkm}/subdev/bios/conn.h | 0
.../nvkm}/subdev/bios/cstep.h | 0
.../nvkm}/subdev/bios/dcb.h | 0
.../nvkm}/subdev/bios/disp.h | 0
.../include => include/nvkm}/subdev/bios/dp.h | 0
.../nvkm}/subdev/bios/extdev.h | 0
.../nvkm}/subdev/bios/fan.h | 0
.../nvkm}/subdev/bios/gpio.h | 0
.../nvkm}/subdev/bios/i2c.h | 0
.../nvkm}/subdev/bios/image.h | 0
.../nvkm}/subdev/bios/init.h | 0
.../nvkm}/subdev/bios/mxm.h | 0
.../nvkm}/subdev/bios/npde.h | 0
.../nvkm}/subdev/bios/pcir.h | 0
.../nvkm}/subdev/bios/perf.h | 0
.../nvkm}/subdev/bios/pll.h | 0
.../nvkm}/subdev/bios/pmu.h | 0
.../nvkm}/subdev/bios/ramcfg.h | 0
.../nvkm}/subdev/bios/rammap.h | 0
.../nvkm}/subdev/bios/therm.h | 0
.../nvkm}/subdev/bios/timing.h | 0
.../nvkm}/subdev/bios/vmap.h | 0
.../nvkm}/subdev/bios/volt.h | 0
.../nvkm}/subdev/bios/xpio.h | 0
.../include => include/nvkm}/subdev/bus.h | 0
.../include => include/nvkm}/subdev/clock.h | 0
.../include => include/nvkm}/subdev/devinit.h | 0
.../include => include/nvkm}/subdev/fb.h | 0
.../include => include/nvkm}/subdev/fuse.h | 0
.../include => include/nvkm}/subdev/gpio.h | 0
.../include => include/nvkm}/subdev/i2c.h | 0
.../include => include/nvkm}/subdev/ibus.h | 0
.../include => include/nvkm}/subdev/instmem.h | 0
.../include => include/nvkm}/subdev/ltc.h | 0
.../include => include/nvkm}/subdev/mc.h | 0
.../include => include/nvkm}/subdev/mxm.h | 0
.../include => include/nvkm}/subdev/pwr.h | 0
.../include => include/nvkm}/subdev/therm.h | 0
.../include => include/nvkm}/subdev/timer.h | 0
.../include => include/nvkm}/subdev/vga.h | 0
.../include => include/nvkm}/subdev/vm.h | 0
.../include => include/nvkm}/subdev/volt.h | 0
drivers/gpu/drm/nouveau/nouveau_ttm.c | 2 +-
drivers/gpu/drm/nouveau/nvif/Kbuild | 4 +
drivers/gpu/drm/nouveau/nvif/client.c | 6 +-
drivers/gpu/drm/nouveau/nvif/device.c | 2 +-
drivers/gpu/drm/nouveau/nvif/object.c | 8 +-
drivers/gpu/drm/nouveau/nvif/os.h | 1 -
drivers/gpu/drm/nouveau/nvkm/Kbuild | 3 +
drivers/gpu/drm/nouveau/nvkm/core/Kbuild | 17 +
.../drm/nouveau/{core => nvkm}/core/client.c | 0
.../drm/nouveau/{core => nvkm}/core/engctx.c | 0
.../drm/nouveau/{core => nvkm}/core/engine.c | 0
.../drm/nouveau/{core => nvkm}/core/enum.c | 0
.../drm/nouveau/{core => nvkm}/core/event.c | 0
.../drm/nouveau/{core => nvkm}/core/gpuobj.c | 0
.../drm/nouveau/{core => nvkm}/core/handle.c | 0
.../drm/nouveau/{core => nvkm}/core/ioctl.c | 0
.../gpu/drm/nouveau/{core => nvkm}/core/mm.c | 0
.../drm/nouveau/{core => nvkm}/core/namedb.c | 0
.../drm/nouveau/{core => nvkm}/core/notify.c | 0
.../drm/nouveau/{core => nvkm}/core/object.c | 0
.../drm/nouveau/{core => nvkm}/core/option.c | 0
.../drm/nouveau/{core => nvkm}/core/parent.c | 0
.../drm/nouveau/{core => nvkm}/core/printk.c | 0
.../drm/nouveau/{core => nvkm}/core/ramht.c | 0
.../drm/nouveau/{core => nvkm}/core/subdev.c | 0
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 16 +
.../gpu/drm/nouveau/nvkm/engine/bsp/Kbuild | 4 +
.../nouveau/{core => nvkm}/engine/bsp/nv84.c | 0
.../nouveau/{core => nvkm}/engine/bsp/nv98.c | 0
.../nouveau/{core => nvkm}/engine/bsp/nvc0.c | 0
.../nouveau/{core => nvkm}/engine/bsp/nve0.c | 0
.../gpu/drm/nouveau/nvkm/engine/copy/Kbuild | 3 +
.../nva3.fuc => nvkm/engine/copy/fuc/com.fuc} | 41 +-
.../nouveau/nvkm/engine/copy/fuc/nva3.fuc3 | 2 +
.../engine/copy/fuc/nva3.fuc3.h} | 0
.../nouveau/nvkm/engine/copy/fuc/nvc0.fuc3 | 2 +
.../engine/copy/fuc/nvc0.fuc3.h} | 0
.../nouveau/{core => nvkm}/engine/copy/nva3.c | 2 +-
.../nouveau/{core => nvkm}/engine/copy/nvc0.c | 2 +-
.../nouveau/{core => nvkm}/engine/copy/nve0.c | 0
.../gpu/drm/nouveau/nvkm/engine/crypt/Kbuild | 2 +
.../engine/crypt/fuc/nv98.fuc0s} | 0
.../engine/crypt/fuc/nv98.fuc0s.h} | 0
.../{core => nvkm}/engine/crypt/nv84.c | 0
.../{core => nvkm}/engine/crypt/nv98.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/device/Kbuild | 12 +
.../{core => nvkm}/engine/device/acpi.c | 0
.../{core => nvkm}/engine/device/acpi.h | 0
.../{core => nvkm}/engine/device/base.c | 0
.../{core => nvkm}/engine/device/ctrl.c | 0
.../{core => nvkm}/engine/device/gm100.c | 0
.../{core => nvkm}/engine/device/nv04.c | 0
.../{core => nvkm}/engine/device/nv10.c | 0
.../{core => nvkm}/engine/device/nv20.c | 0
.../{core => nvkm}/engine/device/nv30.c | 0
.../{core => nvkm}/engine/device/nv40.c | 0
.../{core => nvkm}/engine/device/nv50.c | 0
.../{core => nvkm}/engine/device/nvc0.c | 0
.../{core => nvkm}/engine/device/nve0.c | 0
.../{core => nvkm}/engine/device/priv.h | 0
.../gpu/drm/nouveau/nvkm/engine/disp/Kbuild | 29 ++
.../nouveau/{core => nvkm}/engine/disp/base.c | 0
.../nouveau/{core => nvkm}/engine/disp/conn.c | 0
.../nouveau/{core => nvkm}/engine/disp/conn.h | 0
.../{core => nvkm}/engine/disp/dacnv50.c | 0
.../{core => nvkm}/engine/disp/dport.c | 0
.../{core => nvkm}/engine/disp/dport.h | 0
.../{core => nvkm}/engine/disp/gm107.c | 0
.../{core => nvkm}/engine/disp/gm204.c | 0
.../{core => nvkm}/engine/disp/hdanva3.c | 0
.../{core => nvkm}/engine/disp/hdanvd0.c | 0
.../{core => nvkm}/engine/disp/hdminv84.c | 0
.../{core => nvkm}/engine/disp/hdminva3.c | 0
.../{core => nvkm}/engine/disp/hdminvd0.c | 0
.../{core => nvkm}/engine/disp/hdminve0.c | 0
.../nouveau/{core => nvkm}/engine/disp/nv04.c | 0
.../nouveau/{core => nvkm}/engine/disp/nv50.c | 0
.../nouveau/{core => nvkm}/engine/disp/nv50.h | 0
.../nouveau/{core => nvkm}/engine/disp/nv84.c | 0
.../nouveau/{core => nvkm}/engine/disp/nv94.c | 0
.../nouveau/{core => nvkm}/engine/disp/nva0.c | 0
.../nouveau/{core => nvkm}/engine/disp/nva3.c | 0
.../nouveau/{core => nvkm}/engine/disp/nvd0.c | 0
.../nouveau/{core => nvkm}/engine/disp/nve0.c | 0
.../nouveau/{core => nvkm}/engine/disp/nvf0.c | 0
.../nouveau/{core => nvkm}/engine/disp/outp.c | 0
.../nouveau/{core => nvkm}/engine/disp/outp.h | 0
.../{core => nvkm}/engine/disp/outpdp.c | 0
.../{core => nvkm}/engine/disp/outpdp.h | 0
.../{core => nvkm}/engine/disp/piornv50.c | 0
.../nouveau/{core => nvkm}/engine/disp/priv.h | 0
.../{core => nvkm}/engine/disp/sorgm204.c | 0
.../{core => nvkm}/engine/disp/sornv50.c | 0
.../{core => nvkm}/engine/disp/sornv94.c | 0
.../{core => nvkm}/engine/disp/sornvd0.c | 0
.../nouveau/{core => nvkm}/engine/disp/vga.c | 0
.../gpu/drm/nouveau/nvkm/engine/dmaobj/Kbuild | 5 +
.../{core => nvkm}/engine/dmaobj/base.c | 0
.../{core => nvkm}/engine/dmaobj/nv04.c | 0
.../{core => nvkm}/engine/dmaobj/nv50.c | 0
.../{core => nvkm}/engine/dmaobj/nvc0.c | 0
.../{core => nvkm}/engine/dmaobj/nvd0.c | 0
.../{core => nvkm}/engine/dmaobj/priv.h | 0
.../nouveau/{core => nvkm}/engine/falcon.c | 0
.../gpu/drm/nouveau/nvkm/engine/fifo/Kbuild | 11 +
.../nouveau/{core => nvkm}/engine/fifo/base.c | 0
.../{core => nvkm}/engine/fifo/gk20a.c | 0
.../nouveau/{core => nvkm}/engine/fifo/nv04.c | 0
.../nouveau/{core => nvkm}/engine/fifo/nv04.h | 0
.../nouveau/{core => nvkm}/engine/fifo/nv10.c | 0
.../{core => nvkm}/engine/fifo/nv108.c | 0
.../nouveau/{core => nvkm}/engine/fifo/nv17.c | 0
.../nouveau/{core => nvkm}/engine/fifo/nv40.c | 0
.../nouveau/{core => nvkm}/engine/fifo/nv50.c | 0
.../nouveau/{core => nvkm}/engine/fifo/nv50.h | 0
.../nouveau/{core => nvkm}/engine/fifo/nv84.c | 0
.../nouveau/{core => nvkm}/engine/fifo/nvc0.c | 0
.../nouveau/{core => nvkm}/engine/fifo/nve0.c | 0
.../nouveau/{core => nvkm}/engine/fifo/nve0.h | 0
.../gpu/drm/nouveau/nvkm/engine/graph/Kbuild | 36 ++
.../nouveau/{core => nvkm}/engine/graph/ctx.h | 0
.../{core => nvkm}/engine/graph/ctxgk110b.c | 0
.../{core => nvkm}/engine/graph/ctxgk20a.c | 0
.../{core => nvkm}/engine/graph/ctxgm107.c | 0
.../{core => nvkm}/engine/graph/ctxnv108.c | 0
.../{core => nvkm}/engine/graph/ctxnv40.c | 0
.../{core => nvkm}/engine/graph/ctxnv50.c | 0
.../{core => nvkm}/engine/graph/ctxnvc0.c | 0
.../{core => nvkm}/engine/graph/ctxnvc0.h | 0
.../{core => nvkm}/engine/graph/ctxnvc1.c | 0
.../{core => nvkm}/engine/graph/ctxnvc4.c | 0
.../{core => nvkm}/engine/graph/ctxnvc8.c | 0
.../{core => nvkm}/engine/graph/ctxnvd7.c | 0
.../{core => nvkm}/engine/graph/ctxnvd9.c | 0
.../{core => nvkm}/engine/graph/ctxnve4.c | 0
.../{core => nvkm}/engine/graph/ctxnvf0.c | 0
.../{core => nvkm}/engine/graph/fuc/com.fuc | 0
.../{core => nvkm}/engine/graph/fuc/gpc.fuc | 0
.../engine/graph/fuc/gpcgm107.fuc5 | 0
.../engine/graph/fuc/gpcgm107.fuc5.h | 0
.../engine/graph/fuc/gpcnv108.fuc5 | 0
.../engine/graph/fuc/gpcnv108.fuc5.h | 0
.../engine/graph/fuc/gpcnvc0.fuc3} | 0
.../engine/graph/fuc/gpcnvc0.fuc3.h} | 0
.../engine/graph/fuc/gpcnvd7.fuc3} | 0
.../engine/graph/fuc/gpcnvd7.fuc3.h} | 0
.../engine/graph/fuc/gpcnve0.fuc3} | 0
.../engine/graph/fuc/gpcnve0.fuc3.h} | 0
.../engine/graph/fuc/gpcnvf0.fuc3} | 0
.../engine/graph/fuc/gpcnvf0.fuc3.h} | 0
.../{core => nvkm}/engine/graph/fuc/hub.fuc | 0
.../engine/graph/fuc/hubgm107.fuc5 | 0
.../engine/graph/fuc/hubgm107.fuc5.h | 0
.../engine/graph/fuc/hubnv108.fuc5 | 0
.../engine/graph/fuc/hubnv108.fuc5.h | 0
.../engine/graph/fuc/hubnvc0.fuc3} | 0
.../engine/graph/fuc/hubnvc0.fuc3.h} | 0
.../engine/graph/fuc/hubnvd7.fuc3} | 0
.../engine/graph/fuc/hubnvd7.fuc3.h} | 0
.../engine/graph/fuc/hubnve0.fuc3} | 0
.../engine/graph/fuc/hubnve0.fuc3.h} | 0
.../engine/graph/fuc/hubnvf0.fuc3} | 0
.../engine/graph/fuc/hubnvf0.fuc3.h} | 0
.../engine/graph/fuc/macros.fuc | 0
.../{core => nvkm}/engine/graph/fuc/os.h | 0
.../{core => nvkm}/engine/graph/gk110b.c | 0
.../{core => nvkm}/engine/graph/gk20a.c | 0
.../{core => nvkm}/engine/graph/gm107.c | 0
.../{core => nvkm}/engine/graph/nv04.c | 0
.../{core => nvkm}/engine/graph/nv10.c | 0
.../{core => nvkm}/engine/graph/nv108.c | 0
.../{core => nvkm}/engine/graph/nv20.c | 0
.../{core => nvkm}/engine/graph/nv20.h | 0
.../{core => nvkm}/engine/graph/nv25.c | 0
.../{core => nvkm}/engine/graph/nv2a.c | 0
.../{core => nvkm}/engine/graph/nv30.c | 0
.../{core => nvkm}/engine/graph/nv34.c | 0
.../{core => nvkm}/engine/graph/nv35.c | 0
.../{core => nvkm}/engine/graph/nv40.c | 0
.../{core => nvkm}/engine/graph/nv40.h | 0
.../{core => nvkm}/engine/graph/nv50.c | 0
.../{core => nvkm}/engine/graph/nv50.h | 0
.../{core => nvkm}/engine/graph/nvc0.c | 4 +-
.../{core => nvkm}/engine/graph/nvc0.h | 0
.../{core => nvkm}/engine/graph/nvc1.c | 0
.../{core => nvkm}/engine/graph/nvc4.c | 0
.../{core => nvkm}/engine/graph/nvc8.c | 0
.../{core => nvkm}/engine/graph/nvd7.c | 4 +-
.../{core => nvkm}/engine/graph/nvd9.c | 0
.../{core => nvkm}/engine/graph/nve4.c | 4 +-
.../{core => nvkm}/engine/graph/nvf0.c | 4 +-
.../{core => nvkm}/engine/graph/regs.h | 0
.../gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild | 5 +
.../nouveau/{core => nvkm}/engine/mpeg/nv31.c | 0
.../nouveau/{core => nvkm}/engine/mpeg/nv31.h | 0
.../nouveau/{core => nvkm}/engine/mpeg/nv40.c | 0
.../nouveau/{core => nvkm}/engine/mpeg/nv44.c | 0
.../nouveau/{core => nvkm}/engine/mpeg/nv50.c | 0
.../nouveau/{core => nvkm}/engine/mpeg/nv84.c | 0
.../drm/nouveau/nvkm/engine/perfmon/Kbuild | 9 +
.../{core => nvkm}/engine/perfmon/base.c | 0
.../{core => nvkm}/engine/perfmon/daemon.c | 0
.../{core => nvkm}/engine/perfmon/nv40.c | 0
.../{core => nvkm}/engine/perfmon/nv40.h | 0
.../{core => nvkm}/engine/perfmon/nv50.c | 0
.../{core => nvkm}/engine/perfmon/nv84.c | 0
.../{core => nvkm}/engine/perfmon/nva3.c | 0
.../{core => nvkm}/engine/perfmon/nvc0.c | 0
.../{core => nvkm}/engine/perfmon/nvc0.h | 0
.../{core => nvkm}/engine/perfmon/nve0.c | 0
.../{core => nvkm}/engine/perfmon/nvf0.c | 0
.../{core => nvkm}/engine/perfmon/priv.h | 0
.../gpu/drm/nouveau/nvkm/engine/ppp/Kbuild | 2 +
.../nouveau/{core => nvkm}/engine/ppp/nv98.c | 0
.../nouveau/{core => nvkm}/engine/ppp/nvc0.c | 0
.../drm/nouveau/nvkm/engine/software/Kbuild | 4 +
.../{core => nvkm}/engine/software/nv04.c | 0
.../{core => nvkm}/engine/software/nv10.c | 0
.../{core => nvkm}/engine/software/nv50.c | 0
.../{core => nvkm}/engine/software/nv50.h | 0
.../{core => nvkm}/engine/software/nvc0.c | 0
drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild | 4 +
.../nouveau/{core => nvkm}/engine/vp/nv84.c | 0
.../nouveau/{core => nvkm}/engine/vp/nv98.c | 0
.../nouveau/{core => nvkm}/engine/vp/nvc0.c | 0
.../nouveau/{core => nvkm}/engine/vp/nve0.c | 0
.../nouveau/{core => nvkm}/engine/xtensa.c | 0
drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild | 19 +
.../gpu/drm/nouveau/nvkm/subdev/bar/Kbuild | 4 +
.../nouveau/{core => nvkm}/subdev/bar/base.c | 0
.../nouveau/{core => nvkm}/subdev/bar/gk20a.c | 0
.../nouveau/{core => nvkm}/subdev/bar/nv50.c | 0
.../nouveau/{core => nvkm}/subdev/bar/nvc0.c | 0
.../nouveau/{core => nvkm}/subdev/bar/priv.h | 0
.../gpu/drm/nouveau/nvkm/subdev/bios/Kbuild | 37 ++
.../{core => nvkm}/subdev/bios/M0203.c | 0
.../{core => nvkm}/subdev/bios/M0205.c | 0
.../{core => nvkm}/subdev/bios/M0209.c | 0
.../{core => nvkm}/subdev/bios/P0260.c | 0
.../nouveau/{core => nvkm}/subdev/bios/base.c | 0
.../nouveau/{core => nvkm}/subdev/bios/bit.c | 0
.../{core => nvkm}/subdev/bios/boost.c | 0
.../nouveau/{core => nvkm}/subdev/bios/conn.c | 0
.../{core => nvkm}/subdev/bios/cstep.c | 0
.../nouveau/{core => nvkm}/subdev/bios/dcb.c | 0
.../nouveau/{core => nvkm}/subdev/bios/disp.c | 0
.../nouveau/{core => nvkm}/subdev/bios/dp.c | 0
.../{core => nvkm}/subdev/bios/extdev.c | 0
.../nouveau/{core => nvkm}/subdev/bios/fan.c | 0
.../nouveau/{core => nvkm}/subdev/bios/gpio.c | 0
.../nouveau/{core => nvkm}/subdev/bios/i2c.c | 0
.../{core => nvkm}/subdev/bios/image.c | 0
.../nouveau/{core => nvkm}/subdev/bios/init.c | 0
.../nouveau/{core => nvkm}/subdev/bios/mxm.c | 0
.../nouveau/{core => nvkm}/subdev/bios/npde.c | 0
.../nouveau/{core => nvkm}/subdev/bios/pcir.c | 0
.../nouveau/{core => nvkm}/subdev/bios/perf.c | 0
.../nouveau/{core => nvkm}/subdev/bios/pll.c | 0
.../nouveau/{core => nvkm}/subdev/bios/pmu.c | 0
.../nouveau/{core => nvkm}/subdev/bios/priv.h | 0
.../{core => nvkm}/subdev/bios/ramcfg.c | 0
.../{core => nvkm}/subdev/bios/rammap.c | 0
.../{core => nvkm}/subdev/bios/shadow.c | 0
.../{core => nvkm}/subdev/bios/shadowacpi.c | 0
.../{core => nvkm}/subdev/bios/shadowof.c | 0
.../{core => nvkm}/subdev/bios/shadowpci.c | 0
.../{core => nvkm}/subdev/bios/shadowramin.c | 0
.../{core => nvkm}/subdev/bios/shadowrom.c | 0
.../{core => nvkm}/subdev/bios/therm.c | 0
.../{core => nvkm}/subdev/bios/timing.c | 0
.../nouveau/{core => nvkm}/subdev/bios/vmap.c | 0
.../nouveau/{core => nvkm}/subdev/bios/volt.c | 0
.../nouveau/{core => nvkm}/subdev/bios/xpio.c | 0
.../gpu/drm/nouveau/nvkm/subdev/bus/Kbuild | 6 +
.../nouveau/{core => nvkm}/subdev/bus/hwsq.c | 0
.../nouveau/{core => nvkm}/subdev/bus/hwsq.h | 0
.../nouveau/{core => nvkm}/subdev/bus/nv04.c | 0
.../nouveau/{core => nvkm}/subdev/bus/nv04.h | 0
.../nouveau/{core => nvkm}/subdev/bus/nv31.c | 0
.../nouveau/{core => nvkm}/subdev/bus/nv50.c | 0
.../nouveau/{core => nvkm}/subdev/bus/nv94.c | 0
.../nouveau/{core => nvkm}/subdev/bus/nvc0.c | 0
.../gpu/drm/nouveau/nvkm/subdev/clock/Kbuild | 12 +
.../{core => nvkm}/subdev/clock/base.c | 0
.../{core => nvkm}/subdev/clock/gk20a.c | 0
.../{core => nvkm}/subdev/clock/nv04.c | 0
.../{core => nvkm}/subdev/clock/nv40.c | 0
.../{core => nvkm}/subdev/clock/nv50.c | 0
.../{core => nvkm}/subdev/clock/nv50.h | 0
.../{core => nvkm}/subdev/clock/nv84.c | 0
.../{core => nvkm}/subdev/clock/nva3.c | 0
.../{core => nvkm}/subdev/clock/nva3.h | 0
.../{core => nvkm}/subdev/clock/nvaa.c | 0
.../{core => nvkm}/subdev/clock/nvc0.c | 0
.../{core => nvkm}/subdev/clock/nve0.c | 0
.../nouveau/{core => nvkm}/subdev/clock/pll.h | 0
.../{core => nvkm}/subdev/clock/pllnv04.c | 0
.../{core => nvkm}/subdev/clock/pllnva3.c | 0
.../nouveau/{core => nvkm}/subdev/clock/seq.h | 0
.../drm/nouveau/nvkm/subdev/devinit/Kbuild | 14 +
.../{core => nvkm}/subdev/devinit/base.c | 0
.../{core => nvkm}/subdev/devinit/fbmem.h | 0
.../{core => nvkm}/subdev/devinit/gm107.c | 0
.../{core => nvkm}/subdev/devinit/gm204.c | 0
.../{core => nvkm}/subdev/devinit/nv04.c | 0
.../{core => nvkm}/subdev/devinit/nv04.h | 0
.../{core => nvkm}/subdev/devinit/nv05.c | 0
.../{core => nvkm}/subdev/devinit/nv10.c | 0
.../{core => nvkm}/subdev/devinit/nv1a.c | 0
.../{core => nvkm}/subdev/devinit/nv20.c | 0
.../{core => nvkm}/subdev/devinit/nv50.c | 0
.../{core => nvkm}/subdev/devinit/nv50.h | 0
.../{core => nvkm}/subdev/devinit/nv84.c | 0
.../{core => nvkm}/subdev/devinit/nv98.c | 0
.../{core => nvkm}/subdev/devinit/nva3.c | 0
.../{core => nvkm}/subdev/devinit/nvaf.c | 0
.../{core => nvkm}/subdev/devinit/nvc0.c | 0
.../{core => nvkm}/subdev/devinit/priv.h | 0
drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild | 45 ++
.../nouveau/{core => nvkm}/subdev/fb/base.c | 0
.../nouveau/{core => nvkm}/subdev/fb/gddr3.c | 0
.../nouveau/{core => nvkm}/subdev/fb/gddr5.c | 0
.../nouveau/{core => nvkm}/subdev/fb/gk20a.c | 0
.../nouveau/{core => nvkm}/subdev/fb/gm107.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv04.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv04.h | 0
.../nouveau/{core => nvkm}/subdev/fb/nv10.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv1a.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv20.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv25.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv30.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv35.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv36.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv40.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv40.h | 0
.../nouveau/{core => nvkm}/subdev/fb/nv41.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv44.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv46.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv47.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv49.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv4e.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv50.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nv50.h | 0
.../nouveau/{core => nvkm}/subdev/fb/nv84.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nva3.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nvaa.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nvaf.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nvc0.c | 0
.../nouveau/{core => nvkm}/subdev/fb/nvc0.h | 0
.../nouveau/{core => nvkm}/subdev/fb/nve0.c | 0
.../nouveau/{core => nvkm}/subdev/fb/priv.h | 0
.../nouveau/{core => nvkm}/subdev/fb/ramfuc.h | 0
.../{core => nvkm}/subdev/fb/ramgk20a.c | 0
.../{core => nvkm}/subdev/fb/ramgm107.c | 0
.../{core => nvkm}/subdev/fb/ramnv04.c | 0
.../{core => nvkm}/subdev/fb/ramnv10.c | 0
.../{core => nvkm}/subdev/fb/ramnv1a.c | 0
.../{core => nvkm}/subdev/fb/ramnv20.c | 0
.../{core => nvkm}/subdev/fb/ramnv40.c | 0
.../{core => nvkm}/subdev/fb/ramnv41.c | 0
.../{core => nvkm}/subdev/fb/ramnv44.c | 0
.../{core => nvkm}/subdev/fb/ramnv49.c | 0
.../{core => nvkm}/subdev/fb/ramnv4e.c | 0
.../{core => nvkm}/subdev/fb/ramnv50.c | 0
.../{core => nvkm}/subdev/fb/ramnva3.c | 0
.../{core => nvkm}/subdev/fb/ramnvaa.c | 0
.../{core => nvkm}/subdev/fb/ramnvc0.c | 0
.../{core => nvkm}/subdev/fb/ramnve0.c | 0
.../nouveau/{core => nvkm}/subdev/fb/ramseq.h | 0
.../include => nvkm}/subdev/fb/regsnv04.h | 0
.../nouveau/{core => nvkm}/subdev/fb/sddr2.c | 0
.../nouveau/{core => nvkm}/subdev/fb/sddr3.c | 0
.../gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild | 4 +
.../nouveau/{core => nvkm}/subdev/fuse/base.c | 0
.../nouveau/{core => nvkm}/subdev/fuse/g80.c | 0
.../{core => nvkm}/subdev/fuse/gf100.c | 0
.../{core => nvkm}/subdev/fuse/gm107.c | 0
.../nouveau/{core => nvkm}/subdev/fuse/priv.h | 0
.../gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild | 6 +
.../nouveau/{core => nvkm}/subdev/gpio/base.c | 0
.../nouveau/{core => nvkm}/subdev/gpio/nv10.c | 0
.../nouveau/{core => nvkm}/subdev/gpio/nv50.c | 0
.../nouveau/{core => nvkm}/subdev/gpio/nv94.c | 0
.../nouveau/{core => nvkm}/subdev/gpio/nvd0.c | 0
.../nouveau/{core => nvkm}/subdev/gpio/nve0.c | 0
.../nouveau/{core => nvkm}/subdev/gpio/priv.h | 0
.../gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild | 16 +
.../{core => nvkm}/subdev/i2c/anx9805.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/aux.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/base.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/bit.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/gf117.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/gm204.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/nv04.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/nv4e.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/nv50.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/nv50.h | 0
.../nouveau/{core => nvkm}/subdev/i2c/nv94.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/nvd0.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/nve0.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/pad.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/pad.h | 0
.../{core => nvkm}/subdev/i2c/padgm204.c | 0
.../{core => nvkm}/subdev/i2c/padnv04.c | 0
.../{core => nvkm}/subdev/i2c/padnv94.c | 0
.../nouveau/{core => nvkm}/subdev/i2c/port.h | 0
.../nouveau/{core => nvkm}/subdev/i2c/priv.h | 0
.../gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild | 3 +
.../{core => nvkm}/subdev/ibus/gk20a.c | 0
.../nouveau/{core => nvkm}/subdev/ibus/nvc0.c | 0
.../nouveau/{core => nvkm}/subdev/ibus/nve0.c | 0
.../drm/nouveau/nvkm/subdev/instmem/Kbuild | 4 +
.../{core => nvkm}/subdev/instmem/base.c | 0
.../{core => nvkm}/subdev/instmem/nv04.c | 0
.../{core => nvkm}/subdev/instmem/nv04.h | 0
.../{core => nvkm}/subdev/instmem/nv40.c | 0
.../{core => nvkm}/subdev/instmem/nv50.c | 0
.../{core => nvkm}/subdev/instmem/priv.h | 0
.../gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild | 4 +
.../nouveau/{core => nvkm}/subdev/ltc/base.c | 0
.../nouveau/{core => nvkm}/subdev/ltc/gf100.c | 0
.../nouveau/{core => nvkm}/subdev/ltc/gk104.c | 0
.../nouveau/{core => nvkm}/subdev/ltc/gm107.c | 0
.../nouveau/{core => nvkm}/subdev/ltc/priv.h | 0
drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild | 11 +
.../nouveau/{core => nvkm}/subdev/mc/base.c | 0
.../nouveau/{core => nvkm}/subdev/mc/gk20a.c | 0
.../nouveau/{core => nvkm}/subdev/mc/nv04.c | 0
.../nouveau/{core => nvkm}/subdev/mc/nv04.h | 0
.../nouveau/{core => nvkm}/subdev/mc/nv40.c | 0
.../nouveau/{core => nvkm}/subdev/mc/nv44.c | 0
.../nouveau/{core => nvkm}/subdev/mc/nv4c.c | 0
.../nouveau/{core => nvkm}/subdev/mc/nv50.c | 0
.../nouveau/{core => nvkm}/subdev/mc/nv94.c | 0
.../nouveau/{core => nvkm}/subdev/mc/nv98.c | 0
.../nouveau/{core => nvkm}/subdev/mc/nvc0.c | 0
.../nouveau/{core => nvkm}/subdev/mc/nvc3.c | 0
.../nouveau/{core => nvkm}/subdev/mc/priv.h | 0
.../gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild | 3 +
.../nouveau/{core => nvkm}/subdev/mxm/base.c | 0
.../nouveau/{core => nvkm}/subdev/mxm/mxms.c | 0
.../nouveau/{core => nvkm}/subdev/mxm/mxms.h | 0
.../nouveau/{core => nvkm}/subdev/mxm/nv50.c | 0
.../gpu/drm/nouveau/nvkm/subdev/pwr/Kbuild | 8 +
.../nouveau/{core => nvkm}/subdev/pwr/base.c | 0
.../{core => nvkm}/subdev/pwr/fuc/arith.fuc | 0
.../{core => nvkm}/subdev/pwr/fuc/host.fuc | 0
.../{core => nvkm}/subdev/pwr/fuc/i2c_.fuc | 0
.../{core => nvkm}/subdev/pwr/fuc/idle.fuc | 0
.../{core => nvkm}/subdev/pwr/fuc/kernel.fuc | 0
.../{core => nvkm}/subdev/pwr/fuc/macros.fuc | 0
.../{core => nvkm}/subdev/pwr/fuc/memx.fuc | 0
.../subdev/pwr/fuc/nv108.fuc5} | 0
.../subdev/pwr/fuc/nv108.fuc5.h} | 0
.../subdev/pwr/fuc/nva3.fuc3} | 0
.../subdev/pwr/fuc/nva3.fuc3.h} | 0
.../subdev/pwr/fuc/nvc0.fuc3} | 0
.../subdev/pwr/fuc/nvc0.fuc3.h} | 0
.../subdev/pwr/fuc/nvd0.fuc4} | 0
.../subdev/pwr/fuc/nvd0.fuc4.h} | 0
.../{core => nvkm}/subdev/pwr/fuc/os.h | 0
.../{core => nvkm}/subdev/pwr/fuc/perf.fuc | 0
.../{core => nvkm}/subdev/pwr/fuc/test.fuc | 0
.../nouveau/{core => nvkm}/subdev/pwr/gk104.c | 2 +-
.../nouveau/{core => nvkm}/subdev/pwr/gk20a.c | 0
.../nouveau/{core => nvkm}/subdev/pwr/memx.c | 0
.../nouveau/{core => nvkm}/subdev/pwr/nv108.c | 2 +-
.../nouveau/{core => nvkm}/subdev/pwr/nva3.c | 2 +-
.../nouveau/{core => nvkm}/subdev/pwr/nvc0.c | 2 +-
.../nouveau/{core => nvkm}/subdev/pwr/nvd0.c | 2 +-
.../nouveau/{core => nvkm}/subdev/pwr/priv.h | 0
.../gpu/drm/nouveau/nvkm/subdev/therm/Kbuild | 13 +
.../{core => nvkm}/subdev/therm/base.c | 0
.../nouveau/{core => nvkm}/subdev/therm/fan.c | 0
.../{core => nvkm}/subdev/therm/fannil.c | 0
.../{core => nvkm}/subdev/therm/fanpwm.c | 0
.../{core => nvkm}/subdev/therm/fantog.c | 0
.../{core => nvkm}/subdev/therm/gm107.c | 0
.../nouveau/{core => nvkm}/subdev/therm/ic.c | 0
.../{core => nvkm}/subdev/therm/nv40.c | 0
.../{core => nvkm}/subdev/therm/nv50.c | 0
.../{core => nvkm}/subdev/therm/nv84.c | 0
.../{core => nvkm}/subdev/therm/nva3.c | 0
.../{core => nvkm}/subdev/therm/nvd0.c | 0
.../{core => nvkm}/subdev/therm/priv.h | 0
.../{core => nvkm}/subdev/therm/temp.c | 0
.../gpu/drm/nouveau/nvkm/subdev/timer/Kbuild | 3 +
.../{core => nvkm}/subdev/timer/base.c | 0
.../{core => nvkm}/subdev/timer/gk20a.c | 0
.../{core => nvkm}/subdev/timer/nv04.c | 0
.../{core => nvkm}/subdev/timer/nv04.h | 0
.../{core => nvkm}/subdev/timer/priv.h | 0
drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild | 6 +
.../nouveau/{core => nvkm}/subdev/vm/base.c | 0
.../nouveau/{core => nvkm}/subdev/vm/nv04.c | 0
.../nouveau/{core => nvkm}/subdev/vm/nv04.h | 0
.../nouveau/{core => nvkm}/subdev/vm/nv41.c | 0
.../nouveau/{core => nvkm}/subdev/vm/nv44.c | 0
.../nouveau/{core => nvkm}/subdev/vm/nv50.c | 0
.../nouveau/{core => nvkm}/subdev/vm/nvc0.c | 0
.../gpu/drm/nouveau/nvkm/subdev/volt/Kbuild | 4 +
.../nouveau/{core => nvkm}/subdev/volt/base.c | 0
.../{core => nvkm}/subdev/volt/gk20a.c | 0
.../nouveau/{core => nvkm}/subdev/volt/gpio.c | 0
.../nouveau/{core => nvkm}/subdev/volt/nv40.c | 0
609 files changed, 510 insertions(+), 454 deletions(-)
create mode 100644 drivers/gpu/drm/nouveau/Kbuild
delete mode 100644 drivers/gpu/drm/nouveau/Makefile
delete mode 120000 drivers/gpu/drm/nouveau/core/include/nvif/class.h
delete mode 120000 drivers/gpu/drm/nouveau/core/include/nvif/event.h
delete mode 120000 drivers/gpu/drm/nouveau/core/include/nvif/ioctl.h
delete mode 120000 drivers/gpu/drm/nouveau/core/include/nvif/unpack.h
rename drivers/gpu/drm/nouveau/dispnv04/{Makefile => Kbuild} (100%)
rename drivers/gpu/drm/nouveau/{ => include}/nvif/class.h (100%)
rename drivers/gpu/drm/nouveau/{ => include}/nvif/client.h (97%)
rename drivers/gpu/drm/nouveau/{ => include}/nvif/device.h (97%)
rename drivers/gpu/drm/nouveau/{ => include}/nvif/driver.h (100%)
rename drivers/gpu/drm/nouveau/{ => include}/nvif/event.h (100%)
rename drivers/gpu/drm/nouveau/{ => include}/nvif/ioctl.h (100%)
rename drivers/gpu/drm/nouveau/{ => include}/nvif/list.h (100%)
rename drivers/gpu/drm/nouveau/{ => include}/nvif/notify.h (100%)
rename drivers/gpu/drm/nouveau/{ => include}/nvif/object.h (100%)
rename drivers/gpu/drm/nouveau/{core => include/nvif}/os.h (100%)
rename drivers/gpu/drm/nouveau/{ => include}/nvif/unpack.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/client.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/debug.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/device.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/engctx.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/engine.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/enum.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/event.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/gpuobj.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/handle.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/ioctl.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/mm.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/namedb.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/notify.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/object.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/option.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/core/os.h
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/parent.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/printk.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/ramht.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/core/subdev.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/bsp.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/copy.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/crypt.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/device.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/disp.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/dmaobj.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/falcon.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/fifo.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/graph.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/mpeg.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/perfmon.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/ppp.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/software.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/vp.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/engine/xtensa.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bar.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/M0203.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/M0205.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/M0209.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/P0260.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/bit.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/bmp.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/boost.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/conn.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/cstep.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/dcb.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/disp.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/dp.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/extdev.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/fan.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/gpio.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/i2c.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/image.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/init.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/mxm.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/npde.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/pcir.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/perf.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/pll.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/pmu.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/ramcfg.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/rammap.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/therm.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/timing.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/vmap.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/volt.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bios/xpio.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/bus.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/clock.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/devinit.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/fb.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/fuse.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/gpio.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/i2c.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/ibus.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/instmem.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/ltc.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/mc.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/mxm.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/pwr.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/therm.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/timer.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/vga.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/vm.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => include/nvkm}/subdev/volt.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvif/Kbuild
delete mode 120000 drivers/gpu/drm/nouveau/nvif/os.h
create mode 100644 drivers/gpu/drm/nouveau/nvkm/Kbuild
create mode 100644 drivers/gpu/drm/nouveau/nvkm/core/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/client.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/engctx.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/engine.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/enum.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/event.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/gpuobj.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/handle.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/ioctl.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/mm.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/namedb.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/notify.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/object.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/option.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/parent.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/printk.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/ramht.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/core/subdev.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/bsp/nv84.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/bsp/nv98.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/bsp/nvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/bsp/nve0.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/copy/Kbuild
rename drivers/gpu/drm/nouveau/{core/engine/copy/fuc/nva3.fuc => nvkm/engine/copy/fuc/com.fuc} (99%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3
rename drivers/gpu/drm/nouveau/{core/engine/copy/fuc/nva3.fuc.h => nvkm/engine/copy/fuc/nva3.fuc3.h} (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3
rename drivers/gpu/drm/nouveau/{core/engine/copy/fuc/nvc0.fuc.h => nvkm/engine/copy/fuc/nvc0.fuc3.h} (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/copy/nva3.c (99%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/copy/nvc0.c (99%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/copy/nve0.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild
rename drivers/gpu/drm/nouveau/{core/engine/crypt/fuc/nv98.fuc => nvkm/engine/crypt/fuc/nv98.fuc0s} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/crypt/fuc/nv98.fuc.h => nvkm/engine/crypt/fuc/nv98.fuc0s.h} (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/crypt/nv84.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/crypt/nv98.c (99%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/acpi.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/acpi.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/ctrl.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/gm100.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/nv10.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/nv20.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/nv30.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/nv40.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/nvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/nve0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/device/priv.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/conn.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/conn.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/dacnv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/dport.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/dport.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/gm107.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/gm204.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/hdanva3.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/hdanvd0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/hdminv84.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/hdminva3.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/hdminvd0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/hdminve0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/nv50.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/nv84.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/nv94.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/nva0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/nva3.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/nvd0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/nve0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/nvf0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/outp.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/outp.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/outpdp.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/outpdp.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/piornv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/priv.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/sorgm204.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/sornv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/sornv94.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/sornvd0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/disp/vga.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/dmaobj/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/dmaobj/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/dmaobj/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/dmaobj/nvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/dmaobj/nvd0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/dmaobj/priv.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/falcon.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/gk20a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/nv04.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/nv10.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/nv108.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/nv17.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/nv40.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/nv50.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/nv84.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/nvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/nve0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/fifo/nve0.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctx.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxgk110b.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxgk20a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxgm107.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxnv108.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxnv40.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxnv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxnvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxnvc0.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxnvc1.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxnvc4.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxnvc8.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxnvd7.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxnvd9.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxnve4.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/ctxnvf0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/fuc/com.fuc (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/fuc/gpc.fuc (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/fuc/gpcgm107.fuc5 (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/fuc/gpcgm107.fuc5.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/fuc/gpcnv108.fuc5 (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/fuc/gpcnv108.fuc5.h (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/gpcnvc0.fuc => nvkm/engine/graph/fuc/gpcnvc0.fuc3} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/gpcnvc0.fuc.h => nvkm/engine/graph/fuc/gpcnvc0.fuc3.h} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/gpcnvd7.fuc => nvkm/engine/graph/fuc/gpcnvd7.fuc3} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/gpcnvd7.fuc.h => nvkm/engine/graph/fuc/gpcnvd7.fuc3.h} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/gpcnve0.fuc => nvkm/engine/graph/fuc/gpcnve0.fuc3} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/gpcnve0.fuc.h => nvkm/engine/graph/fuc/gpcnve0.fuc3.h} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/gpcnvf0.fuc => nvkm/engine/graph/fuc/gpcnvf0.fuc3} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/gpcnvf0.fuc.h => nvkm/engine/graph/fuc/gpcnvf0.fuc3.h} (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/fuc/hub.fuc (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/fuc/hubgm107.fuc5 (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/fuc/hubgm107.fuc5.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/fuc/hubnv108.fuc5 (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/fuc/hubnv108.fuc5.h (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/hubnvc0.fuc => nvkm/engine/graph/fuc/hubnvc0.fuc3} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/hubnvc0.fuc.h => nvkm/engine/graph/fuc/hubnvc0.fuc3.h} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/hubnvd7.fuc => nvkm/engine/graph/fuc/hubnvd7.fuc3} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/hubnvd7.fuc.h => nvkm/engine/graph/fuc/hubnvd7.fuc3.h} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/hubnve0.fuc => nvkm/engine/graph/fuc/hubnve0.fuc3} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/hubnve0.fuc.h => nvkm/engine/graph/fuc/hubnve0.fuc3.h} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/hubnvf0.fuc => nvkm/engine/graph/fuc/hubnvf0.fuc3} (100%)
rename drivers/gpu/drm/nouveau/{core/engine/graph/fuc/hubnvf0.fuc.h => nvkm/engine/graph/fuc/hubnvf0.fuc3.h} (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/fuc/macros.fuc (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/fuc/os.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/gk110b.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/gk20a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/gm107.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv10.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv108.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv20.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv20.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv25.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv2a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv30.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv34.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv35.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv40.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv40.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nv50.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nvc0.c (99%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nvc0.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nvc1.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nvc4.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nvc8.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nvd7.c (98%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nvd9.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nve4.c (99%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/nvf0.c (99%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/graph/regs.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/mpeg/nv31.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/mpeg/nv31.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/mpeg/nv40.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/mpeg/nv44.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/mpeg/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/mpeg/nv84.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/perfmon/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/perfmon/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/perfmon/daemon.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/perfmon/nv40.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/perfmon/nv40.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/perfmon/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/perfmon/nv84.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/perfmon/nva3.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/perfmon/nvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/perfmon/nvc0.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/perfmon/nve0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/perfmon/nvf0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/perfmon/priv.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/ppp/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/ppp/nv98.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/ppp/nvc0.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/software/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/software/nv10.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/software/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/software/nv50.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/software/nvc0.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/vp/nv84.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/vp/nv98.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/vp/nvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/vp/nve0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/engine/xtensa.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bar/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bar/gk20a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bar/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bar/nvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bar/priv.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/M0203.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/M0205.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/M0209.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/P0260.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/bit.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/boost.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/conn.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/cstep.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/dcb.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/disp.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/dp.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/extdev.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/fan.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/gpio.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/i2c.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/image.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/init.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/mxm.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/npde.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/pcir.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/perf.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/pll.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/pmu.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/priv.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/ramcfg.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/rammap.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/shadow.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/shadowacpi.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/shadowof.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/shadowpci.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/shadowramin.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/shadowrom.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/therm.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/timing.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/vmap.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/volt.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bios/xpio.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bus/hwsq.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bus/hwsq.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bus/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bus/nv04.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bus/nv31.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bus/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bus/nv94.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/bus/nvc0.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/gk20a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/nv40.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/nv50.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/nv84.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/nva3.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/nva3.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/nvaa.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/nvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/nve0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/pll.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/pllnv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/pllnva3.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/clock/seq.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/fbmem.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/gm107.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/gm204.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/nv04.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/nv05.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/nv10.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/nv1a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/nv20.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/nv50.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/nv84.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/nv98.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/nva3.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/nvaf.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/nvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/devinit/priv.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/gddr3.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/gddr5.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/gk20a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/gm107.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv04.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv10.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv1a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv20.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv25.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv30.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv35.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv36.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv40.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv40.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv41.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv44.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv46.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv47.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv49.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv4e.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv50.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nv84.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nva3.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nvaa.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nvaf.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nvc0.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/nve0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/priv.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramfuc.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramgk20a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramgm107.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnv10.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnv1a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnv20.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnv40.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnv41.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnv44.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnv49.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnv4e.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnva3.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnvaa.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramnve0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/ramseq.h (100%)
rename drivers/gpu/drm/nouveau/{core/include => nvkm}/subdev/fb/regsnv04.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/sddr2.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fb/sddr3.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fuse/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fuse/g80.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fuse/gf100.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fuse/gm107.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/fuse/priv.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/gpio/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/gpio/nv10.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/gpio/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/gpio/nv94.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/gpio/nvd0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/gpio/nve0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/gpio/priv.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/anx9805.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/aux.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/bit.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/gf117.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/gm204.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/nv4e.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/nv50.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/nv94.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/nvd0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/nve0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/pad.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/pad.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/padgm204.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/padnv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/padnv94.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/port.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/i2c/priv.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/ibus/gk20a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/ibus/nvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/ibus/nve0.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/instmem/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/instmem/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/instmem/nv04.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/instmem/nv40.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/instmem/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/instmem/priv.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/ltc/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/ltc/gf100.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/ltc/gk104.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/ltc/gm107.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/ltc/priv.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mc/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mc/gk20a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mc/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mc/nv04.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mc/nv40.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mc/nv44.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mc/nv4c.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mc/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mc/nv94.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mc/nv98.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mc/nvc0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mc/nvc3.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mc/priv.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mxm/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mxm/mxms.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mxm/mxms.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/mxm/nv50.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pwr/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/fuc/arith.fuc (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/fuc/host.fuc (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/fuc/i2c_.fuc (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/fuc/idle.fuc (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/fuc/kernel.fuc (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/fuc/macros.fuc (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/fuc/memx.fuc (100%)
rename drivers/gpu/drm/nouveau/{core/subdev/pwr/fuc/nv108.fuc => nvkm/subdev/pwr/fuc/nv108.fuc5} (100%)
rename drivers/gpu/drm/nouveau/{core/subdev/pwr/fuc/nv108.fuc.h => nvkm/subdev/pwr/fuc/nv108.fuc5.h} (100%)
rename drivers/gpu/drm/nouveau/{core/subdev/pwr/fuc/nva3.fuc => nvkm/subdev/pwr/fuc/nva3.fuc3} (100%)
rename drivers/gpu/drm/nouveau/{core/subdev/pwr/fuc/nva3.fuc.h => nvkm/subdev/pwr/fuc/nva3.fuc3.h} (100%)
rename drivers/gpu/drm/nouveau/{core/subdev/pwr/fuc/nvc0.fuc => nvkm/subdev/pwr/fuc/nvc0.fuc3} (100%)
rename drivers/gpu/drm/nouveau/{core/subdev/pwr/fuc/nvc0.fuc.h => nvkm/subdev/pwr/fuc/nvc0.fuc3.h} (100%)
rename drivers/gpu/drm/nouveau/{core/subdev/pwr/fuc/nvd0.fuc => nvkm/subdev/pwr/fuc/nvd0.fuc4} (100%)
rename drivers/gpu/drm/nouveau/{core/subdev/pwr/fuc/nvd0.fuc.h => nvkm/subdev/pwr/fuc/nvd0.fuc4.h} (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/fuc/os.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/fuc/perf.fuc (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/fuc/test.fuc (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/gk104.c (98%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/gk20a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/memx.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/nv108.c (98%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/nva3.c (98%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/nvc0.c (98%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/nvd0.c (98%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/pwr/priv.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/fan.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/fannil.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/fanpwm.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/fantog.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/gm107.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/ic.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/nv40.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/nv84.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/nva3.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/nvd0.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/priv.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/therm/temp.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/timer/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/timer/gk20a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/timer/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/timer/nv04.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/timer/priv.h (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/vm/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/vm/nv04.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/vm/nv04.h (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/vm/nv41.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/vm/nv44.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/vm/nv50.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/vm/nvc0.c (100%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/volt/base.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/volt/gk20a.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/volt/gpio.c (100%)
rename drivers/gpu/drm/nouveau/{core => nvkm}/subdev/volt/nv40.c (100%)
diff --git a/drivers/gpu/drm/nouveau/Kbuild b/drivers/gpu/drm/nouveau/Kbuild
new file mode 100644
index 000000000000..2b765663c1a3
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/Kbuild
@@ -0,0 +1,66 @@
+ccflags-y := -Iinclude/drm
+ccflags-y += -I$(src)/include
+ccflags-y += -I$(src)/include/nvkm
+ccflags-y += -I$(src)/nvkm
+ccflags-y += -I$(src)
+
+# NVKM - HW resource manager
+#- code also used by various userspace tools/tests
+include $(src)/nvif/Kbuild
+nouveau-y := $(nvif-y)
+
+# NVIF - NVKM interface library (NVKM user interface also defined here)
+#- code also used by various userspace tools/tests
+include $(src)/nvkm/Kbuild
+nouveau-y += $(nvkm-y)
+
+# DRM - general
+ifdef CONFIG_X86
+nouveau-$(CONFIG_ACPI) += nouveau_acpi.o
+endif
+nouveau-y += nouveau_agp.o
+nouveau-$(CONFIG_DEBUG_FS) += nouveau_debugfs.o
+nouveau-y += nouveau_drm.o
+nouveau-y += nouveau_hwmon.o
+nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
+nouveau-y += nouveau_nvif.o
+nouveau-$(CONFIG_NOUVEAU_PLATFORM_DRIVER) += nouveau_platform.o
+nouveau-y += nouveau_sysfs.o
+nouveau-y += nouveau_usif.o # userspace <-> nvif
+nouveau-y += nouveau_vga.o
+
+# DRM - memory management
+nouveau-y += nouveau_bo.o
+nouveau-y += nouveau_gem.o
+nouveau-y += nouveau_prime.o
+nouveau-y += nouveau_sgdma.o
+nouveau-y += nouveau_ttm.o
+
+# DRM - modesetting
+nouveau-$(CONFIG_DRM_NOUVEAU_BACKLIGHT) += nouveau_backlight.o
+nouveau-y += nouveau_connector.o
+nouveau-y += nouveau_display.o
+nouveau-y += nv50_display.o
+nouveau-y += nouveau_dp.o
+nouveau-y += nouveau_fbcon.o
+nouveau-y += nv04_fbcon.o
+nouveau-y += nv50_fbcon.o
+nouveau-y += nvc0_fbcon.o
+
+# DRM - command submission
+nouveau-y += nouveau_abi16.o
+nouveau-y += nouveau_chan.o
+nouveau-y += nouveau_dma.o
+nouveau-y += nouveau_fence.o
+nouveau-y += nv04_fence.o
+nouveau-y += nv10_fence.o
+nouveau-y += nv17_fence.o
+nouveau-y += nv50_fence.o
+nouveau-y += nv84_fence.o
+nouveau-y += nvc0_fence.o
+
+# DRM - prehistoric modesetting (NV04-G7x)
+nouveau-y += nouveau_bios.o
+include $(src)/dispnv04/Kbuild
+
+obj-$(CONFIG_DRM_NOUVEAU) += nouveau.o
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
deleted file mode 100644
index 1febf6ec0b69..000000000000
--- a/drivers/gpu/drm/nouveau/Makefile
+++ /dev/null
@@ -1,400 +0,0 @@
-#
-# Makefile for the drm device driver. This driver provides support for the
-# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-
-ccflags-y := -Iinclude/drm
-ccflags-y += -I$(src)/core/include
-ccflags-y += -I$(src)/core
-ccflags-y += -I$(src)
-
-nouveau-y := core/core/client.o
-nouveau-y += core/core/engctx.o
-nouveau-y += core/core/engine.o
-nouveau-y += core/core/enum.o
-nouveau-y += core/core/event.o
-nouveau-y += core/core/gpuobj.o
-nouveau-y += core/core/handle.o
-nouveau-y += core/core/ioctl.o
-nouveau-y += core/core/mm.o
-nouveau-y += core/core/namedb.o
-nouveau-y += core/core/notify.o
-nouveau-y += core/core/object.o
-nouveau-y += core/core/option.o
-nouveau-y += core/core/parent.o
-nouveau-y += core/core/printk.o
-nouveau-y += core/core/ramht.o
-nouveau-y += core/core/subdev.o
-
-nouveau-y += core/subdev/bar/base.o
-nouveau-y += core/subdev/bar/nv50.o
-nouveau-y += core/subdev/bar/nvc0.o
-nouveau-y += core/subdev/bar/gk20a.o
-nouveau-y += core/subdev/bios/base.o
-nouveau-y += core/subdev/bios/bit.o
-nouveau-y += core/subdev/bios/boost.o
-nouveau-y += core/subdev/bios/conn.o
-nouveau-y += core/subdev/bios/cstep.o
-nouveau-y += core/subdev/bios/dcb.o
-nouveau-y += core/subdev/bios/disp.o
-nouveau-y += core/subdev/bios/dp.o
-nouveau-y += core/subdev/bios/extdev.o
-nouveau-y += core/subdev/bios/fan.o
-nouveau-y += core/subdev/bios/gpio.o
-nouveau-y += core/subdev/bios/i2c.o
-nouveau-y += core/subdev/bios/image.o
-nouveau-y += core/subdev/bios/init.o
-nouveau-y += core/subdev/bios/mxm.o
-nouveau-y += core/subdev/bios/npde.o
-nouveau-y += core/subdev/bios/pcir.o
-nouveau-y += core/subdev/bios/perf.o
-nouveau-y += core/subdev/bios/pll.o
-nouveau-y += core/subdev/bios/pmu.o
-nouveau-y += core/subdev/bios/ramcfg.o
-nouveau-y += core/subdev/bios/rammap.o
-nouveau-y += core/subdev/bios/shadow.o
-nouveau-y += core/subdev/bios/shadowacpi.o
-nouveau-y += core/subdev/bios/shadowof.o
-nouveau-y += core/subdev/bios/shadowpci.o
-nouveau-y += core/subdev/bios/shadowramin.o
-nouveau-y += core/subdev/bios/shadowrom.o
-nouveau-y += core/subdev/bios/timing.o
-nouveau-y += core/subdev/bios/therm.o
-nouveau-y += core/subdev/bios/vmap.o
-nouveau-y += core/subdev/bios/volt.o
-nouveau-y += core/subdev/bios/xpio.o
-nouveau-y += core/subdev/bios/M0203.o
-nouveau-y += core/subdev/bios/M0205.o
-nouveau-y += core/subdev/bios/M0209.o
-nouveau-y += core/subdev/bios/P0260.o
-nouveau-y += core/subdev/bus/hwsq.o
-nouveau-y += core/subdev/bus/nv04.o
-nouveau-y += core/subdev/bus/nv31.o
-nouveau-y += core/subdev/bus/nv50.o
-nouveau-y += core/subdev/bus/nv94.o
-nouveau-y += core/subdev/bus/nvc0.o
-nouveau-y += core/subdev/clock/base.o
-nouveau-y += core/subdev/clock/nv04.o
-nouveau-y += core/subdev/clock/nv40.o
-nouveau-y += core/subdev/clock/nv50.o
-nouveau-y += core/subdev/clock/nv84.o
-nouveau-y += core/subdev/clock/nva3.o
-nouveau-y += core/subdev/clock/nvaa.o
-nouveau-y += core/subdev/clock/nvc0.o
-nouveau-y += core/subdev/clock/nve0.o
-nouveau-y += core/subdev/clock/gk20a.o
-nouveau-y += core/subdev/clock/pllnv04.o
-nouveau-y += core/subdev/clock/pllnva3.o
-nouveau-y += core/subdev/devinit/base.o
-nouveau-y += core/subdev/devinit/nv04.o
-nouveau-y += core/subdev/devinit/nv05.o
-nouveau-y += core/subdev/devinit/nv10.o
-nouveau-y += core/subdev/devinit/nv1a.o
-nouveau-y += core/subdev/devinit/nv20.o
-nouveau-y += core/subdev/devinit/nv50.o
-nouveau-y += core/subdev/devinit/nv84.o
-nouveau-y += core/subdev/devinit/nv98.o
-nouveau-y += core/subdev/devinit/nva3.o
-nouveau-y += core/subdev/devinit/nvaf.o
-nouveau-y += core/subdev/devinit/nvc0.o
-nouveau-y += core/subdev/devinit/gm107.o
-nouveau-y += core/subdev/devinit/gm204.o
-nouveau-y += core/subdev/fb/base.o
-nouveau-y += core/subdev/fb/nv04.o
-nouveau-y += core/subdev/fb/nv10.o
-nouveau-y += core/subdev/fb/nv1a.o
-nouveau-y += core/subdev/fb/nv20.o
-nouveau-y += core/subdev/fb/nv25.o
-nouveau-y += core/subdev/fb/nv30.o
-nouveau-y += core/subdev/fb/nv35.o
-nouveau-y += core/subdev/fb/nv36.o
-nouveau-y += core/subdev/fb/nv40.o
-nouveau-y += core/subdev/fb/nv41.o
-nouveau-y += core/subdev/fb/nv44.o
-nouveau-y += core/subdev/fb/nv46.o
-nouveau-y += core/subdev/fb/nv47.o
-nouveau-y += core/subdev/fb/nv49.o
-nouveau-y += core/subdev/fb/nv4e.o
-nouveau-y += core/subdev/fb/nv50.o
-nouveau-y += core/subdev/fb/nv84.o
-nouveau-y += core/subdev/fb/nva3.o
-nouveau-y += core/subdev/fb/nvaa.o
-nouveau-y += core/subdev/fb/nvaf.o
-nouveau-y += core/subdev/fb/nvc0.o
-nouveau-y += core/subdev/fb/nve0.o
-nouveau-y += core/subdev/fb/gk20a.o
-nouveau-y += core/subdev/fb/gm107.o
-nouveau-y += core/subdev/fb/ramnv04.o
-nouveau-y += core/subdev/fb/ramnv10.o
-nouveau-y += core/subdev/fb/ramnv1a.o
-nouveau-y += core/subdev/fb/ramnv20.o
-nouveau-y += core/subdev/fb/ramnv40.o
-nouveau-y += core/subdev/fb/ramnv41.o
-nouveau-y += core/subdev/fb/ramnv44.o
-nouveau-y += core/subdev/fb/ramnv49.o
-nouveau-y += core/subdev/fb/ramnv4e.o
-nouveau-y += core/subdev/fb/ramnv50.o
-nouveau-y += core/subdev/fb/ramnva3.o
-nouveau-y += core/subdev/fb/ramnvaa.o
-nouveau-y += core/subdev/fb/ramnvc0.o
-nouveau-y += core/subdev/fb/ramnve0.o
-nouveau-y += core/subdev/fb/ramgk20a.o
-nouveau-y += core/subdev/fb/ramgm107.o
-nouveau-y += core/subdev/fb/sddr2.o
-nouveau-y += core/subdev/fb/sddr3.o
-nouveau-y += core/subdev/fb/gddr3.o
-nouveau-y += core/subdev/fb/gddr5.o
-nouveau-y += core/subdev/fuse/base.o
-nouveau-y += core/subdev/fuse/g80.o
-nouveau-y += core/subdev/fuse/gf100.o
-nouveau-y += core/subdev/fuse/gm107.o
-nouveau-y += core/subdev/gpio/base.o
-nouveau-y += core/subdev/gpio/nv10.o
-nouveau-y += core/subdev/gpio/nv50.o
-nouveau-y += core/subdev/gpio/nv94.o
-nouveau-y += core/subdev/gpio/nvd0.o
-nouveau-y += core/subdev/gpio/nve0.o
-nouveau-y += core/subdev/i2c/base.o
-nouveau-y += core/subdev/i2c/anx9805.o
-nouveau-y += core/subdev/i2c/aux.o
-nouveau-y += core/subdev/i2c/bit.o
-nouveau-y += core/subdev/i2c/pad.o
-nouveau-y += core/subdev/i2c/padnv04.o
-nouveau-y += core/subdev/i2c/padnv94.o
-nouveau-y += core/subdev/i2c/padgm204.o
-nouveau-y += core/subdev/i2c/nv04.o
-nouveau-y += core/subdev/i2c/nv4e.o
-nouveau-y += core/subdev/i2c/nv50.o
-nouveau-y += core/subdev/i2c/nv94.o
-nouveau-y += core/subdev/i2c/nvd0.o
-nouveau-y += core/subdev/i2c/gf117.o
-nouveau-y += core/subdev/i2c/nve0.o
-nouveau-y += core/subdev/i2c/gm204.o
-nouveau-y += core/subdev/ibus/nvc0.o
-nouveau-y += core/subdev/ibus/nve0.o
-nouveau-y += core/subdev/ibus/gk20a.o
-nouveau-y += core/subdev/instmem/base.o
-nouveau-y += core/subdev/instmem/nv04.o
-nouveau-y += core/subdev/instmem/nv40.o
-nouveau-y += core/subdev/instmem/nv50.o
-nouveau-y += core/subdev/ltc/base.o
-nouveau-y += core/subdev/ltc/gf100.o
-nouveau-y += core/subdev/ltc/gk104.o
-nouveau-y += core/subdev/ltc/gm107.o
-nouveau-y += core/subdev/mc/base.o
-nouveau-y += core/subdev/mc/nv04.o
-nouveau-y += core/subdev/mc/nv40.o
-nouveau-y += core/subdev/mc/nv44.o
-nouveau-y += core/subdev/mc/nv4c.o
-nouveau-y += core/subdev/mc/nv50.o
-nouveau-y += core/subdev/mc/nv94.o
-nouveau-y += core/subdev/mc/nv98.o
-nouveau-y += core/subdev/mc/nvc0.o
-nouveau-y += core/subdev/mc/nvc3.o
-nouveau-y += core/subdev/mc/gk20a.o
-nouveau-y += core/subdev/mxm/base.o
-nouveau-y += core/subdev/mxm/mxms.o
-nouveau-y += core/subdev/mxm/nv50.o
-nouveau-y += core/subdev/pwr/base.o
-nouveau-y += core/subdev/pwr/memx.o
-nouveau-y += core/subdev/pwr/nva3.o
-nouveau-y += core/subdev/pwr/nvc0.o
-nouveau-y += core/subdev/pwr/nvd0.o
-nouveau-y += core/subdev/pwr/gk104.o
-nouveau-y += core/subdev/pwr/nv108.o
-nouveau-y += core/subdev/pwr/gk20a.o
-nouveau-y += core/subdev/therm/base.o
-nouveau-y += core/subdev/therm/fan.o
-nouveau-y += core/subdev/therm/fannil.o
-nouveau-y += core/subdev/therm/fanpwm.o
-nouveau-y += core/subdev/therm/fantog.o
-nouveau-y += core/subdev/therm/ic.o
-nouveau-y += core/subdev/therm/temp.o
-nouveau-y += core/subdev/therm/nv40.o
-nouveau-y += core/subdev/therm/nv50.o
-nouveau-y += core/subdev/therm/nv84.o
-nouveau-y += core/subdev/therm/nva3.o
-nouveau-y += core/subdev/therm/nvd0.o
-nouveau-y += core/subdev/therm/gm107.o
-nouveau-y += core/subdev/timer/base.o
-nouveau-y += core/subdev/timer/nv04.o
-nouveau-y += core/subdev/timer/gk20a.o
-nouveau-y += core/subdev/vm/base.o
-nouveau-y += core/subdev/vm/nv04.o
-nouveau-y += core/subdev/vm/nv41.o
-nouveau-y += core/subdev/vm/nv44.o
-nouveau-y += core/subdev/vm/nv50.o
-nouveau-y += core/subdev/vm/nvc0.o
-nouveau-y += core/subdev/volt/base.o
-nouveau-y += core/subdev/volt/gpio.o
-nouveau-y += core/subdev/volt/nv40.o
-nouveau-y += core/subdev/volt/gk20a.o
-
-nouveau-y += core/engine/falcon.o
-nouveau-y += core/engine/xtensa.o
-nouveau-y += core/engine/dmaobj/base.o
-nouveau-y += core/engine/dmaobj/nv04.o
-nouveau-y += core/engine/dmaobj/nv50.o
-nouveau-y += core/engine/dmaobj/nvc0.o
-nouveau-y += core/engine/dmaobj/nvd0.o
-nouveau-y += core/engine/bsp/nv84.o
-nouveau-y += core/engine/bsp/nv98.o
-nouveau-y += core/engine/bsp/nvc0.o
-nouveau-y += core/engine/bsp/nve0.o
-nouveau-y += core/engine/copy/nva3.o
-nouveau-y += core/engine/copy/nvc0.o
-nouveau-y += core/engine/copy/nve0.o
-nouveau-y += core/engine/crypt/nv84.o
-nouveau-y += core/engine/crypt/nv98.o
-nouveau-y += core/engine/device/acpi.o
-nouveau-y += core/engine/device/base.o
-nouveau-y += core/engine/device/ctrl.o
-nouveau-y += core/engine/device/nv04.o
-nouveau-y += core/engine/device/nv10.o
-nouveau-y += core/engine/device/nv20.o
-nouveau-y += core/engine/device/nv30.o
-nouveau-y += core/engine/device/nv40.o
-nouveau-y += core/engine/device/nv50.o
-nouveau-y += core/engine/device/nvc0.o
-nouveau-y += core/engine/device/nve0.o
-nouveau-y += core/engine/device/gm100.o
-nouveau-y += core/engine/disp/base.o
-nouveau-y += core/engine/disp/conn.o
-nouveau-y += core/engine/disp/outp.o
-nouveau-y += core/engine/disp/outpdp.o
-nouveau-y += core/engine/disp/nv04.o
-nouveau-y += core/engine/disp/nv50.o
-nouveau-y += core/engine/disp/nv84.o
-nouveau-y += core/engine/disp/nv94.o
-nouveau-y += core/engine/disp/nva0.o
-nouveau-y += core/engine/disp/nva3.o
-nouveau-y += core/engine/disp/nvd0.o
-nouveau-y += core/engine/disp/nve0.o
-nouveau-y += core/engine/disp/nvf0.o
-nouveau-y += core/engine/disp/gm107.o
-nouveau-y += core/engine/disp/gm204.o
-nouveau-y += core/engine/disp/dacnv50.o
-nouveau-y += core/engine/disp/dport.o
-nouveau-y += core/engine/disp/hdanva3.o
-nouveau-y += core/engine/disp/hdanvd0.o
-nouveau-y += core/engine/disp/hdminv84.o
-nouveau-y += core/engine/disp/hdminva3.o
-nouveau-y += core/engine/disp/hdminvd0.o
-nouveau-y += core/engine/disp/hdminve0.o
-nouveau-y += core/engine/disp/piornv50.o
-nouveau-y += core/engine/disp/sornv50.o
-nouveau-y += core/engine/disp/sornv94.o
-nouveau-y += core/engine/disp/sornvd0.o
-nouveau-y += core/engine/disp/sorgm204.o
-nouveau-y += core/engine/disp/vga.o
-nouveau-y += core/engine/fifo/base.o
-nouveau-y += core/engine/fifo/nv04.o
-nouveau-y += core/engine/fifo/nv10.o
-nouveau-y += core/engine/fifo/nv17.o
-nouveau-y += core/engine/fifo/nv40.o
-nouveau-y += core/engine/fifo/nv50.o
-nouveau-y += core/engine/fifo/nv84.o
-nouveau-y += core/engine/fifo/nvc0.o
-nouveau-y += core/engine/fifo/nve0.o
-nouveau-y += core/engine/fifo/gk20a.o
-nouveau-y += core/engine/fifo/nv108.o
-nouveau-y += core/engine/graph/ctxnv40.o
-nouveau-y += core/engine/graph/ctxnv50.o
-nouveau-y += core/engine/graph/ctxnvc0.o
-nouveau-y += core/engine/graph/ctxnvc1.o
-nouveau-y += core/engine/graph/ctxnvc4.o
-nouveau-y += core/engine/graph/ctxnvc8.o
-nouveau-y += core/engine/graph/ctxnvd7.o
-nouveau-y += core/engine/graph/ctxnvd9.o
-nouveau-y += core/engine/graph/ctxnve4.o
-nouveau-y += core/engine/graph/ctxgk20a.o
-nouveau-y += core/engine/graph/ctxnvf0.o
-nouveau-y += core/engine/graph/ctxgk110b.o
-nouveau-y += core/engine/graph/ctxnv108.o
-nouveau-y += core/engine/graph/ctxgm107.o
-nouveau-y += core/engine/graph/nv04.o
-nouveau-y += core/engine/graph/nv10.o
-nouveau-y += core/engine/graph/nv20.o
-nouveau-y += core/engine/graph/nv25.o
-nouveau-y += core/engine/graph/nv2a.o
-nouveau-y += core/engine/graph/nv30.o
-nouveau-y += core/engine/graph/nv34.o
-nouveau-y += core/engine/graph/nv35.o
-nouveau-y += core/engine/graph/nv40.o
-nouveau-y += core/engine/graph/nv50.o
-nouveau-y += core/engine/graph/nvc0.o
-nouveau-y += core/engine/graph/nvc1.o
-nouveau-y += core/engine/graph/nvc4.o
-nouveau-y += core/engine/graph/nvc8.o
-nouveau-y += core/engine/graph/nvd7.o
-nouveau-y += core/engine/graph/nvd9.o
-nouveau-y += core/engine/graph/nve4.o
-nouveau-y += core/engine/graph/gk20a.o
-nouveau-y += core/engine/graph/nvf0.o
-nouveau-y += core/engine/graph/gk110b.o
-nouveau-y += core/engine/graph/nv108.o
-nouveau-y += core/engine/graph/gm107.o
-nouveau-y += core/engine/mpeg/nv31.o
-nouveau-y += core/engine/mpeg/nv40.o
-nouveau-y += core/engine/mpeg/nv44.o
-nouveau-y += core/engine/mpeg/nv50.o
-nouveau-y += core/engine/mpeg/nv84.o
-nouveau-y += core/engine/perfmon/base.o
-nouveau-y += core/engine/perfmon/daemon.o
-nouveau-y += core/engine/perfmon/nv40.o
-nouveau-y += core/engine/perfmon/nv50.o
-nouveau-y += core/engine/perfmon/nv84.o
-nouveau-y += core/engine/perfmon/nva3.o
-nouveau-y += core/engine/perfmon/nvc0.o
-nouveau-y += core/engine/perfmon/nve0.o
-nouveau-y += core/engine/perfmon/nvf0.o
-nouveau-y += core/engine/ppp/nv98.o
-nouveau-y += core/engine/ppp/nvc0.o
-nouveau-y += core/engine/software/nv04.o
-nouveau-y += core/engine/software/nv10.o
-nouveau-y += core/engine/software/nv50.o
-nouveau-y += core/engine/software/nvc0.o
-nouveau-y += core/engine/vp/nv84.o
-nouveau-y += core/engine/vp/nv98.o
-nouveau-y += core/engine/vp/nvc0.o
-nouveau-y += core/engine/vp/nve0.o
-
-# nvif
-nouveau-y += nvif/object.o
-nouveau-y += nvif/client.o
-nouveau-y += nvif/device.o
-nouveau-y += nvif/notify.o
-
-# drm/core
-nouveau-y += nouveau_drm.o nouveau_chan.o nouveau_dma.o nouveau_fence.o
-nouveau-y += nouveau_vga.o nouveau_agp.o
-nouveau-y += nouveau_ttm.o nouveau_sgdma.o nouveau_bo.o nouveau_gem.o
-nouveau-y += nouveau_prime.o nouveau_abi16.o
-nouveau-y += nouveau_nvif.o nouveau_usif.o
-nouveau-y += nv04_fence.o nv10_fence.o nv17_fence.o
-nouveau-y += nv50_fence.o nv84_fence.o nvc0_fence.o
-
-# drm/kms
-nouveau-y += nouveau_bios.o nouveau_fbcon.o nouveau_display.o
-nouveau-y += nouveau_connector.o nouveau_dp.o
-nouveau-y += nv04_fbcon.o nv50_fbcon.o nvc0_fbcon.o
-
-# drm/kms/nv04:nv50
-include $(src)/dispnv04/Makefile
-
-# drm/kms/nv50-
-nouveau-y += nv50_display.o
-
-# drm/pm
-nouveau-y += nouveau_hwmon.o nouveau_sysfs.o
-
-# other random bits
-nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
-ifdef CONFIG_X86
-nouveau-$(CONFIG_ACPI) += nouveau_acpi.o
-endif
-nouveau-$(CONFIG_DRM_NOUVEAU_BACKLIGHT) += nouveau_backlight.o
-nouveau-$(CONFIG_DEBUG_FS) += nouveau_debugfs.o
-nouveau-$(CONFIG_NOUVEAU_PLATFORM_DRIVER) += nouveau_platform.o
-
-obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o
-
diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/class.h b/drivers/gpu/drm/nouveau/core/include/nvif/class.h
deleted file mode 120000
index f1ac4859edd4..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/nvif/class.h
+++ /dev/null
@@ -1 +0,0 @@
-../../../nvif/class.h
\ No newline at end of file
diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/event.h b/drivers/gpu/drm/nouveau/core/include/nvif/event.h
deleted file mode 120000
index 1b798538a725..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/nvif/event.h
+++ /dev/null
@@ -1 +0,0 @@
-../../../nvif/event.h
\ No newline at end of file
diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/ioctl.h b/drivers/gpu/drm/nouveau/core/include/nvif/ioctl.h
deleted file mode 120000
index 8569c86907c5..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/nvif/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
-../../../nvif/ioctl.h
\ No newline at end of file
diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/unpack.h b/drivers/gpu/drm/nouveau/core/include/nvif/unpack.h
deleted file mode 120000
index 69d99292bca4..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/nvif/unpack.h
+++ /dev/null
@@ -1 +0,0 @@
-../../../nvif/unpack.h
\ No newline at end of file
diff --git a/drivers/gpu/drm/nouveau/dispnv04/Makefile b/drivers/gpu/drm/nouveau/dispnv04/Kbuild
similarity index 100%
rename from drivers/gpu/drm/nouveau/dispnv04/Makefile
rename to drivers/gpu/drm/nouveau/dispnv04/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvif/class.h
rename to drivers/gpu/drm/nouveau/include/nvif/class.h
diff --git a/drivers/gpu/drm/nouveau/nvif/client.h b/drivers/gpu/drm/nouveau/include/nvif/client.h
similarity index 97%
rename from drivers/gpu/drm/nouveau/nvif/client.h
rename to drivers/gpu/drm/nouveau/include/nvif/client.h
index 28352f0882ec..8b0048426ee5 100644
--- a/drivers/gpu/drm/nouveau/nvif/client.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/client.h
@@ -1,7 +1,7 @@
#ifndef __NVIF_CLIENT_H__
#define __NVIF_CLIENT_H__
-#include "object.h"
+#include <nvif/object.h>
struct nvif_client {
struct nvif_object base;
diff --git a/drivers/gpu/drm/nouveau/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h
similarity index 97%
rename from drivers/gpu/drm/nouveau/nvif/device.h
rename to drivers/gpu/drm/nouveau/include/nvif/device.h
index 43180f9fe630..4aa1b93a8cd4 100644
--- a/drivers/gpu/drm/nouveau/nvif/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/device.h
@@ -1,8 +1,8 @@
#ifndef __NVIF_DEVICE_H__
#define __NVIF_DEVICE_H__
-#include "object.h"
-#include "class.h"
+#include <nvif/object.h>
+#include <nvif/class.h>
struct nvif_device {
struct nvif_object base;
diff --git a/drivers/gpu/drm/nouveau/nvif/driver.h b/drivers/gpu/drm/nouveau/include/nvif/driver.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvif/driver.h
rename to drivers/gpu/drm/nouveau/include/nvif/driver.h
diff --git a/drivers/gpu/drm/nouveau/nvif/event.h b/drivers/gpu/drm/nouveau/include/nvif/event.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvif/event.h
rename to drivers/gpu/drm/nouveau/include/nvif/event.h
diff --git a/drivers/gpu/drm/nouveau/nvif/ioctl.h b/drivers/gpu/drm/nouveau/include/nvif/ioctl.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvif/ioctl.h
rename to drivers/gpu/drm/nouveau/include/nvif/ioctl.h
diff --git a/drivers/gpu/drm/nouveau/nvif/list.h b/drivers/gpu/drm/nouveau/include/nvif/list.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvif/list.h
rename to drivers/gpu/drm/nouveau/include/nvif/list.h
diff --git a/drivers/gpu/drm/nouveau/nvif/notify.h b/drivers/gpu/drm/nouveau/include/nvif/notify.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvif/notify.h
rename to drivers/gpu/drm/nouveau/include/nvif/notify.h
diff --git a/drivers/gpu/drm/nouveau/nvif/object.h b/drivers/gpu/drm/nouveau/include/nvif/object.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvif/object.h
rename to drivers/gpu/drm/nouveau/include/nvif/object.h
diff --git a/drivers/gpu/drm/nouveau/core/os.h b/drivers/gpu/drm/nouveau/include/nvif/os.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/os.h
rename to drivers/gpu/drm/nouveau/include/nvif/os.h
diff --git a/drivers/gpu/drm/nouveau/nvif/unpack.h b/drivers/gpu/drm/nouveau/include/nvif/unpack.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvif/unpack.h
rename to drivers/gpu/drm/nouveau/include/nvif/unpack.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/client.h b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/client.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/client.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/debug.h b/drivers/gpu/drm/nouveau/include/nvkm/core/debug.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/debug.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/debug.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/device.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/device.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/engctx.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/engctx.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/engine.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/engine.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/enum.h b/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/enum.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/enum.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/event.h b/drivers/gpu/drm/nouveau/include/nvkm/core/event.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/event.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/event.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/gpuobj.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/handle.h b/drivers/gpu/drm/nouveau/include/nvkm/core/handle.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/handle.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/handle.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/ioctl.h b/drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/ioctl.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/mm.h b/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/mm.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/mm.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/namedb.h b/drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/namedb.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/notify.h b/drivers/gpu/drm/nouveau/include/nvkm/core/notify.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/notify.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/notify.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/object.h b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/object.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/object.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/option.h b/drivers/gpu/drm/nouveau/include/nvkm/core/option.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/option.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/option.h
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
new file mode 100644
index 000000000000..cd57e238ddd3
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -0,0 +1,4 @@
+#ifndef __NVKM_OS_H__
+#define __NVKM_OS_H__
+#include <nvif/os.h>
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/parent.h b/drivers/gpu/drm/nouveau/include/nvkm/core/parent.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/parent.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/parent.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/printk.h b/drivers/gpu/drm/nouveau/include/nvkm/core/printk.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/printk.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/printk.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/ramht.h b/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/ramht.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h
diff --git a/drivers/gpu/drm/nouveau/core/include/core/subdev.h b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/core/subdev.h
rename to drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/bsp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/bsp.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/copy.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/copy.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/copy.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/copy.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/crypt.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/crypt.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/crypt.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/crypt.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/device.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/device.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/device.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/device.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/disp.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/dmaobj.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/dmaobj.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/falcon.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/falcon.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/fifo.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/graph.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/graph.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/graph.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/graph.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/mpeg.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/perfmon.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/perfmon.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/perfmon.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/ppp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ppp.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/ppp.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/ppp.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/software.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/software.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/software.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/software.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/vp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/vp.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/engine/xtensa.h
rename to drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bar.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0203.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/M0203.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/P0260.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/P0260.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bit.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/bit.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bmp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/bmp.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/boost.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/boost.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/cstep.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/cstep.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/disp.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/extdev.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/extdev.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/fan.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/fan.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/i2c.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/i2c.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/image.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/image.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/mxm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/mxm.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/npde.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/npde.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pcir.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/pcir.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/perf.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/perf.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/pmu.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/vmap.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/vmap.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/volt.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/xpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bios/xpio.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/bus.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/clock.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/fb.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/fuse.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/gpio.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/i2c.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/ibus.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/instmem.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/ltc.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/mc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/mc.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/mxm.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pwr.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/pwr.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/therm.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/timer.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/vga.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/vga.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/vm.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/volt.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index 3d1cfcb96b6b..2e0d1d998ca6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -203,7 +203,7 @@ const struct ttm_mem_type_manager_func nouveau_gart_manager = {
};
/*XXX*/
-#include <core/subdev/vm/nv04.h>
+#include <subdev/vm/nv04.h>
static int
nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
diff --git a/drivers/gpu/drm/nouveau/nvif/Kbuild b/drivers/gpu/drm/nouveau/nvif/Kbuild
new file mode 100644
index 000000000000..ff8ed3a04d06
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvif/Kbuild
@@ -0,0 +1,4 @@
+nvif-y := nvif/object.o
+nvif-y += nvif/client.o
+nvif-y += nvif/device.o
+nvif-y += nvif/notify.o
diff --git a/drivers/gpu/drm/nouveau/nvif/client.c b/drivers/gpu/drm/nouveau/nvif/client.c
index 3f7ac5bc8e03..80b96844221e 100644
--- a/drivers/gpu/drm/nouveau/nvif/client.c
+++ b/drivers/gpu/drm/nouveau/nvif/client.c
@@ -22,9 +22,9 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-#include "client.h"
-#include "driver.h"
-#include "ioctl.h"
+#include <nvif/client.h>
+#include <nvif/driver.h>
+#include <nvif/ioctl.h>
int
nvif_client_ioctl(struct nvif_client *client, void *data, u32 size)
diff --git a/drivers/gpu/drm/nouveau/nvif/device.c b/drivers/gpu/drm/nouveau/nvif/device.c
index f477579725e3..6f72244c52cd 100644
--- a/drivers/gpu/drm/nouveau/nvif/device.c
+++ b/drivers/gpu/drm/nouveau/nvif/device.c
@@ -22,7 +22,7 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-#include "device.h"
+#include <nvif/device.h>
void
nvif_device_fini(struct nvif_device *device)
diff --git a/drivers/gpu/drm/nouveau/nvif/object.c b/drivers/gpu/drm/nouveau/nvif/object.c
index dd85b56f6aa5..3ab4e2f8cc12 100644
--- a/drivers/gpu/drm/nouveau/nvif/object.c
+++ b/drivers/gpu/drm/nouveau/nvif/object.c
@@ -22,10 +22,10 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-#include "object.h"
-#include "client.h"
-#include "driver.h"
-#include "ioctl.h"
+#include <nvif/object.h>
+#include <nvif/client.h>
+#include <nvif/driver.h>
+#include <nvif/ioctl.h>
int
nvif_object_ioctl(struct nvif_object *object, void *data, u32 size, void **hack)
diff --git a/drivers/gpu/drm/nouveau/nvif/os.h b/drivers/gpu/drm/nouveau/nvif/os.h
deleted file mode 120000
index bd744b2cf5cf..000000000000
--- a/drivers/gpu/drm/nouveau/nvif/os.h
+++ /dev/null
@@ -1 +0,0 @@
-../core/os.h
\ No newline at end of file
diff --git a/drivers/gpu/drm/nouveau/nvkm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/Kbuild
new file mode 100644
index 000000000000..2832147b676c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/Kbuild
@@ -0,0 +1,3 @@
+include $(src)/nvkm/core/Kbuild
+include $(src)/nvkm/subdev/Kbuild
+include $(src)/nvkm/engine/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/Kbuild b/drivers/gpu/drm/nouveau/nvkm/core/Kbuild
new file mode 100644
index 000000000000..a2bdb2069113
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/core/Kbuild
@@ -0,0 +1,17 @@
+nvkm-y := nvkm/core/client.o
+nvkm-y += nvkm/core/engctx.o
+nvkm-y += nvkm/core/engine.o
+nvkm-y += nvkm/core/enum.o
+nvkm-y += nvkm/core/event.o
+nvkm-y += nvkm/core/gpuobj.o
+nvkm-y += nvkm/core/handle.o
+nvkm-y += nvkm/core/ioctl.o
+nvkm-y += nvkm/core/mm.o
+nvkm-y += nvkm/core/namedb.o
+nvkm-y += nvkm/core/notify.o
+nvkm-y += nvkm/core/object.o
+nvkm-y += nvkm/core/option.o
+nvkm-y += nvkm/core/parent.o
+nvkm-y += nvkm/core/printk.o
+nvkm-y += nvkm/core/ramht.o
+nvkm-y += nvkm/core/subdev.o
diff --git a/drivers/gpu/drm/nouveau/core/core/client.c b/drivers/gpu/drm/nouveau/nvkm/core/client.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/client.c
rename to drivers/gpu/drm/nouveau/nvkm/core/client.c
diff --git a/drivers/gpu/drm/nouveau/core/core/engctx.c b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/engctx.c
rename to drivers/gpu/drm/nouveau/nvkm/core/engctx.c
diff --git a/drivers/gpu/drm/nouveau/core/core/engine.c b/drivers/gpu/drm/nouveau/nvkm/core/engine.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/engine.c
rename to drivers/gpu/drm/nouveau/nvkm/core/engine.c
diff --git a/drivers/gpu/drm/nouveau/core/core/enum.c b/drivers/gpu/drm/nouveau/nvkm/core/enum.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/enum.c
rename to drivers/gpu/drm/nouveau/nvkm/core/enum.c
diff --git a/drivers/gpu/drm/nouveau/core/core/event.c b/drivers/gpu/drm/nouveau/nvkm/core/event.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/event.c
rename to drivers/gpu/drm/nouveau/nvkm/core/event.c
diff --git a/drivers/gpu/drm/nouveau/core/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/gpuobj.c
rename to drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
diff --git a/drivers/gpu/drm/nouveau/core/core/handle.c b/drivers/gpu/drm/nouveau/nvkm/core/handle.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/handle.c
rename to drivers/gpu/drm/nouveau/nvkm/core/handle.c
diff --git a/drivers/gpu/drm/nouveau/core/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/ioctl.c
rename to drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
diff --git a/drivers/gpu/drm/nouveau/core/core/mm.c b/drivers/gpu/drm/nouveau/nvkm/core/mm.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/mm.c
rename to drivers/gpu/drm/nouveau/nvkm/core/mm.c
diff --git a/drivers/gpu/drm/nouveau/core/core/namedb.c b/drivers/gpu/drm/nouveau/nvkm/core/namedb.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/namedb.c
rename to drivers/gpu/drm/nouveau/nvkm/core/namedb.c
diff --git a/drivers/gpu/drm/nouveau/core/core/notify.c b/drivers/gpu/drm/nouveau/nvkm/core/notify.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/notify.c
rename to drivers/gpu/drm/nouveau/nvkm/core/notify.c
diff --git a/drivers/gpu/drm/nouveau/core/core/object.c b/drivers/gpu/drm/nouveau/nvkm/core/object.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/object.c
rename to drivers/gpu/drm/nouveau/nvkm/core/object.c
diff --git a/drivers/gpu/drm/nouveau/core/core/option.c b/drivers/gpu/drm/nouveau/nvkm/core/option.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/option.c
rename to drivers/gpu/drm/nouveau/nvkm/core/option.c
diff --git a/drivers/gpu/drm/nouveau/core/core/parent.c b/drivers/gpu/drm/nouveau/nvkm/core/parent.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/parent.c
rename to drivers/gpu/drm/nouveau/nvkm/core/parent.c
diff --git a/drivers/gpu/drm/nouveau/core/core/printk.c b/drivers/gpu/drm/nouveau/nvkm/core/printk.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/printk.c
rename to drivers/gpu/drm/nouveau/nvkm/core/printk.c
diff --git a/drivers/gpu/drm/nouveau/core/core/ramht.c b/drivers/gpu/drm/nouveau/nvkm/core/ramht.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/ramht.c
rename to drivers/gpu/drm/nouveau/nvkm/core/ramht.c
diff --git a/drivers/gpu/drm/nouveau/core/core/subdev.c b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/core/subdev.c
rename to drivers/gpu/drm/nouveau/nvkm/core/subdev.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
new file mode 100644
index 000000000000..ebd30be3a62d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
@@ -0,0 +1,16 @@
+nvkm-y += nvkm/engine/falcon.o
+nvkm-y += nvkm/engine/xtensa.o
+
+include $(src)/nvkm/engine/bsp/Kbuild
+include $(src)/nvkm/engine/copy/Kbuild
+include $(src)/nvkm/engine/crypt/Kbuild
+include $(src)/nvkm/engine/device/Kbuild
+include $(src)/nvkm/engine/disp/Kbuild
+include $(src)/nvkm/engine/dmaobj/Kbuild
+include $(src)/nvkm/engine/fifo/Kbuild
+include $(src)/nvkm/engine/graph/Kbuild
+include $(src)/nvkm/engine/mpeg/Kbuild
+include $(src)/nvkm/engine/perfmon/Kbuild
+include $(src)/nvkm/engine/ppp/Kbuild
+include $(src)/nvkm/engine/software/Kbuild
+include $(src)/nvkm/engine/vp/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild
new file mode 100644
index 000000000000..da54c5610a67
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild
@@ -0,0 +1,4 @@
+nvkm-y += nvkm/engine/bsp/nv84.o
+nvkm-y += nvkm/engine/bsp/nv98.o
+nvkm-y += nvkm/engine/bsp/nvc0.o
+nvkm-y += nvkm/engine/bsp/nve0.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv84.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv84.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv98.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv98.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/bsp/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/bsp/nve0.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/copy/Kbuild
new file mode 100644
index 000000000000..d8aa5edba726
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/copy/Kbuild
@@ -0,0 +1,3 @@
+nvkm-y += nvkm/engine/copy/nva3.o
+nvkm-y += nvkm/engine/copy/nvc0.o
+nvkm-y += nvkm/engine/copy/nve0.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/com.fuc
similarity index 99%
rename from drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/com.fuc
index 219850d53286..33b67dc711ac 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/com.fuc
@@ -30,19 +30,19 @@
* m4 -DNVC0 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_copy.fuc.h
*/
-ifdef(`NVA3',
+#ifdef NVA3
.section #nva3_pcopy_data
-,
+#else
.section #nvc0_pcopy_data
-)
+#endif
ctx_object: .b32 0
-ifdef(`NVA3',
+#ifdef NVA3
ctx_dma:
ctx_dma_query: .b32 0
ctx_dma_src: .b32 0
ctx_dma_dst: .b32 0
-,)
+#endif
.equ #ctx_dma_count 3
ctx_query_address_high: .b32 0
ctx_query_address_low: .b32 0
@@ -86,14 +86,14 @@ dispatch_table:
// mthd 0x0140, PM_TRIGGER
.b16 0x050 1
.b32 0x00010000 + #cmd_pm_trigger ~0xffffffff
-ifdef(`NVA3', `
+#ifdef NVA3
// mthd 0x0180-0x018c, DMA_
.b16 0x060 #ctx_dma_count
dispatch_dma:
.b32 0x00010000 + #cmd_dma ~0xffffffff
.b32 0x00010000 + #cmd_dma ~0xffffffff
.b32 0x00010000 + #cmd_dma ~0xffffffff
-',)
+#endif
// mthd 0x0200-0x0218, SRC_TILE
.b16 0x80 7
.b32 #ctx_src_tile_mode ~0x00000fff
@@ -134,11 +134,11 @@ dispatch_dma:
.b32 #ctx_query_counter ~0xffffffff
.b16 0x800 0
-ifdef(`NVA3',
+#ifdef NVA3
.section #nva3_pcopy_code
-,
+#else
.section #nvc0_pcopy_code
-)
+#endif
main:
clear b32 $r0
@@ -190,10 +190,10 @@ ih:
swctx:
mov $r4 0x7700
mov $xtargets $r4
-ifdef(`NVA3', `
+#ifdef NVA3
// target 7 hardcoded to ctx dma object
mov $xdbase $r0
-', ` // NVC0
+#else
// read SCRATCH3 to decide if we are PCOPY0 or PCOPY1
mov $r4 0x2100
iord $r4 I[$r4 + 0]
@@ -231,7 +231,7 @@ ifdef(`NVA3', `
shl b32 $r6 24
or $r4 $r6
mov $xdbase $r4
-')
+#endif
// 256-byte context, at start of data segment
mov b32 $r4 $r0
sethi $r4 0x60000
@@ -271,7 +271,7 @@ chsw:
bra e #chsw_finish_load
bset $flags $p1
call #swctx
-ifdef(`NVA3',
+#ifdef NVA3
// load dma objects back into TARGET regs
mov $r5 #ctx_dma
mov $r6 #ctx_dma_count
@@ -282,8 +282,7 @@ ifdef(`NVA3',
iowr I[$r8] $r7
sub b32 $r6 1
bra nc #chsw_load_ctx_dma
-,)
-
+#endif
chsw_finish_load:
mov $r3 2
iowr I[$r2 + 0x200] $r3
@@ -397,7 +396,7 @@ cmd_pm_trigger:
iowr I[$r2] $r3
ret
-ifdef(`NVA3',
+#ifdef NVA3
// SET_DMA_* method handler
//
// Inputs:
@@ -419,7 +418,7 @@ cmd_dma:
shl b32 $r4 6
iowr I[$r4] $r3
ret
-,)
+#endif
// Calculates the hw swizzle mask and adjusts the surface's xcnt to match
//
@@ -548,11 +547,11 @@ cmd_exec_set_surface_tiled:
ld b32 $r7 D[$r5 + #ctx_src_tile_mode]
extr $r9 $r7 8:11
extr $r8 $r7 4:7
-ifdef(`NVA3',
+#ifdef NVA3
add b32 $r8 2
-,
+#else
add b32 $r8 3
-)
+#endif
extr $r7 $r7 0:3
cmp b32 $r7 0xe
bra ne #xtile64
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3
new file mode 100644
index 000000000000..e670620227e7
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3
@@ -0,0 +1,2 @@
+#define NVA3
+#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3
new file mode 100644
index 000000000000..df6866c34e16
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3
@@ -0,0 +1,2 @@
+#define NVC0
+#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c
similarity index 99%
rename from drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c
index abb410ef09ea..13c05e09ff87 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c
@@ -33,7 +33,7 @@
#include <core/enum.h>
-#include "fuc/nva3.fuc.h"
+#include "fuc/nva3.fuc3.h"
struct nva3_copy_priv {
struct nouveau_falcon base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nvc0.c
similarity index 99%
rename from drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/copy/nvc0.c
index 20a8cd7f7730..abe324993eaf 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nvc0.c
@@ -29,7 +29,7 @@
#include <core/enum.h>
#include <core/enum.h>
-#include "fuc/nvc0.fuc.h"
+#include "fuc/nvc0.fuc3.h"
struct nvc0_copy_priv {
struct nouveau_falcon base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/copy/nve0.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild
new file mode 100644
index 000000000000..eaeafdf3bc81
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild
@@ -0,0 +1,2 @@
+nvkm-y += nvkm/engine/crypt/nv84.o
+nvkm-y += nvkm/engine/crypt/nv98.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv84.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv84.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv98.c
similarity index 99%
rename from drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv98.c
index 5571c09534cb..e0838c46ec17 100644
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv98.c
@@ -34,7 +34,7 @@
#include <engine/fifo.h>
#include <engine/crypt.h>
-#include "fuc/nv98.fuc.h"
+#include "fuc/nv98.fuc0s.h"
struct nv98_crypt_priv {
struct nouveau_falcon base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild
new file mode 100644
index 000000000000..77d06d46eff4
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild
@@ -0,0 +1,12 @@
+nvkm-y += nvkm/engine/device/acpi.o
+nvkm-y += nvkm/engine/device/base.o
+nvkm-y += nvkm/engine/device/ctrl.o
+nvkm-y += nvkm/engine/device/nv04.o
+nvkm-y += nvkm/engine/device/nv10.o
+nvkm-y += nvkm/engine/device/nv20.o
+nvkm-y += nvkm/engine/device/nv30.o
+nvkm-y += nvkm/engine/device/nv40.o
+nvkm-y += nvkm/engine/device/nv50.o
+nvkm-y += nvkm/engine/device/nvc0.o
+nvkm-y += nvkm/engine/device/nve0.o
+nvkm-y += nvkm/engine/device/gm100.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/acpi.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/acpi.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/acpi.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/acpi.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/base.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/ctrl.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/gm100.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/nv10.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/nv20.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/nv30.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/device/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
new file mode 100644
index 000000000000..50bd1e2bb8fa
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
@@ -0,0 +1,29 @@
+nvkm-y += nvkm/engine/disp/base.o
+nvkm-y += nvkm/engine/disp/conn.o
+nvkm-y += nvkm/engine/disp/outp.o
+nvkm-y += nvkm/engine/disp/outpdp.o
+nvkm-y += nvkm/engine/disp/nv04.o
+nvkm-y += nvkm/engine/disp/nv50.o
+nvkm-y += nvkm/engine/disp/nv84.o
+nvkm-y += nvkm/engine/disp/nv94.o
+nvkm-y += nvkm/engine/disp/nva0.o
+nvkm-y += nvkm/engine/disp/nva3.o
+nvkm-y += nvkm/engine/disp/nvd0.o
+nvkm-y += nvkm/engine/disp/nve0.o
+nvkm-y += nvkm/engine/disp/nvf0.o
+nvkm-y += nvkm/engine/disp/gm107.o
+nvkm-y += nvkm/engine/disp/gm204.o
+nvkm-y += nvkm/engine/disp/dacnv50.o
+nvkm-y += nvkm/engine/disp/dport.o
+nvkm-y += nvkm/engine/disp/hdanva3.o
+nvkm-y += nvkm/engine/disp/hdanvd0.o
+nvkm-y += nvkm/engine/disp/hdminv84.o
+nvkm-y += nvkm/engine/disp/hdminva3.o
+nvkm-y += nvkm/engine/disp/hdminvd0.o
+nvkm-y += nvkm/engine/disp/hdminve0.o
+nvkm-y += nvkm/engine/disp/piornv50.o
+nvkm-y += nvkm/engine/disp/sornv50.o
+nvkm-y += nvkm/engine/disp/sornv94.o
+nvkm-y += nvkm/engine/disp/sornvd0.o
+nvkm-y += nvkm/engine/disp/sorgm204.o
+nvkm-y += nvkm/engine/disp/vga.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/base.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/conn.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/conn.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/conn.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/conn.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/dport.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/dport.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/gm204.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdanva3.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/hdanva3.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdanvd0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/hdanvd0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminv84.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminv84.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminva3.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminva3.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminvd0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminvd0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminve0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvd0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/nvd0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/outp.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/outp.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sorgm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/sorgm204.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv94.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv94.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornvd0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/sornvd0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/vga.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/disp/vga.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/Kbuild
new file mode 100644
index 000000000000..4f9286a038ef
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/Kbuild
@@ -0,0 +1,5 @@
+nvkm-y += nvkm/engine/dmaobj/base.o
+nvkm-y += nvkm/engine/dmaobj/nv04.o
+nvkm-y += nvkm/engine/dmaobj/nv50.o
+nvkm-y += nvkm/engine/dmaobj/nvc0.o
+nvkm-y += nvkm/engine/dmaobj/nvd0.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nvd0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nvd0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/dmaobj/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/falcon.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
new file mode 100644
index 000000000000..f38820faf44f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
@@ -0,0 +1,11 @@
+nvkm-y += nvkm/engine/fifo/base.o
+nvkm-y += nvkm/engine/fifo/nv04.o
+nvkm-y += nvkm/engine/fifo/nv10.o
+nvkm-y += nvkm/engine/fifo/nv17.o
+nvkm-y += nvkm/engine/fifo/nv40.o
+nvkm-y += nvkm/engine/fifo/nv50.o
+nvkm-y += nvkm/engine/fifo/nv84.o
+nvkm-y += nvkm/engine/fifo/nvc0.o
+nvkm-y += nvkm/engine/fifo/nve0.o
+nvkm-y += nvkm/engine/fifo/gk20a.o
+nvkm-y += nvkm/engine/fifo/nv108.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/base.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/nv04.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv108.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv108.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/nv50.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild
new file mode 100644
index 000000000000..fd56e979344b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild
@@ -0,0 +1,36 @@
+nvkm-y += nvkm/engine/graph/ctxnv40.o
+nvkm-y += nvkm/engine/graph/ctxnv50.o
+nvkm-y += nvkm/engine/graph/ctxnvc0.o
+nvkm-y += nvkm/engine/graph/ctxnvc1.o
+nvkm-y += nvkm/engine/graph/ctxnvc4.o
+nvkm-y += nvkm/engine/graph/ctxnvc8.o
+nvkm-y += nvkm/engine/graph/ctxnvd7.o
+nvkm-y += nvkm/engine/graph/ctxnvd9.o
+nvkm-y += nvkm/engine/graph/ctxnve4.o
+nvkm-y += nvkm/engine/graph/ctxgk20a.o
+nvkm-y += nvkm/engine/graph/ctxnvf0.o
+nvkm-y += nvkm/engine/graph/ctxgk110b.o
+nvkm-y += nvkm/engine/graph/ctxnv108.o
+nvkm-y += nvkm/engine/graph/ctxgm107.o
+nvkm-y += nvkm/engine/graph/nv04.o
+nvkm-y += nvkm/engine/graph/nv10.o
+nvkm-y += nvkm/engine/graph/nv20.o
+nvkm-y += nvkm/engine/graph/nv25.o
+nvkm-y += nvkm/engine/graph/nv2a.o
+nvkm-y += nvkm/engine/graph/nv30.o
+nvkm-y += nvkm/engine/graph/nv34.o
+nvkm-y += nvkm/engine/graph/nv35.o
+nvkm-y += nvkm/engine/graph/nv40.o
+nvkm-y += nvkm/engine/graph/nv50.o
+nvkm-y += nvkm/engine/graph/nvc0.o
+nvkm-y += nvkm/engine/graph/nvc1.o
+nvkm-y += nvkm/engine/graph/nvc4.o
+nvkm-y += nvkm/engine/graph/nvc8.o
+nvkm-y += nvkm/engine/graph/nvd7.o
+nvkm-y += nvkm/engine/graph/nvd9.o
+nvkm-y += nvkm/engine/graph/nve4.o
+nvkm-y += nvkm/engine/graph/gk20a.o
+nvkm-y += nvkm/engine/graph/nvf0.o
+nvkm-y += nvkm/engine/graph/gk110b.o
+nvkm-y += nvkm/engine/graph/nv108.o
+nvkm-y += nvkm/engine/graph/gm107.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctx.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctx.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctx.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctx.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk110b.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk110b.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk20a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk20a.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgm107.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgm107.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv108.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv108.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv40.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv40.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv50.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc1.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc1.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc4.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc4.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc8.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc8.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd7.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd7.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd9.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd9.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnve4.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnve4.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvf0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvf0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/com.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/com.fuc
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpc.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpc.fuc
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hub.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hub.fuc
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/macros.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/macros.fuc
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/os.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/os.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/gk110b.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/gk110b.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/gk20a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/gk20a.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/gm107.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/gm107.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/gm107.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv10.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv10.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv108.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv108.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv108.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv20.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv25.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv25.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv25.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv2a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv2a.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv30.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv30.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv30.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv34.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv34.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv34.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv35.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv35.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv35.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv40.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nv50.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.c
similarity index 99%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.c
index 17251e4b9e86..3e90e437dbbe 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.c
@@ -1630,7 +1630,7 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-#include "fuc/hubnvc0.fuc.h"
+#include "fuc/hubnvc0.fuc3.h"
struct nvc0_graph_ucode
nvc0_graph_fecs_ucode = {
@@ -1640,7 +1640,7 @@ nvc0_graph_fecs_ucode = {
.data.size = sizeof(nvc0_grhub_data),
};
-#include "fuc/gpcnvc0.fuc.h"
+#include "fuc/gpcnvc0.fuc3.h"
struct nvc0_graph_ucode
nvc0_graph_gpccs_ucode = {
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc1.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc1.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc4.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc4.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc8.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc8.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd7.c
similarity index 98%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd7.c
index 41e8445c7eea..6f9f5ede5588 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd7.c
@@ -99,7 +99,7 @@ nvd7_graph_pack_mmio[] = {
* PGRAPH engine/subdev functions
******************************************************************************/
-#include "fuc/hubnvd7.fuc.h"
+#include "fuc/hubnvd7.fuc3.h"
struct nvc0_graph_ucode
nvd7_graph_fecs_ucode = {
@@ -109,7 +109,7 @@ nvd7_graph_fecs_ucode = {
.data.size = sizeof(nvd7_grhub_data),
};
-#include "fuc/gpcnvd7.fuc.h"
+#include "fuc/gpcnvd7.fuc3.h"
struct nvc0_graph_ucode
nvd7_graph_gpccs_ucode = {
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd9.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd9.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c
similarity index 99%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c
index 0c71f5c67ae0..83a966fc5301 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c
@@ -309,7 +309,7 @@ nve4_graph_init(struct nouveau_object *object)
return nvc0_graph_init_ctxctl(priv);
}
-#include "fuc/hubnve0.fuc.h"
+#include "fuc/hubnve0.fuc3.h"
static struct nvc0_graph_ucode
nve4_graph_fecs_ucode = {
@@ -319,7 +319,7 @@ nve4_graph_fecs_ucode = {
.data.size = sizeof(nve0_grhub_data),
};
-#include "fuc/gpcnve0.fuc.h"
+#include "fuc/gpcnve0.fuc3.h"
static struct nvc0_graph_ucode
nve4_graph_gpccs_ucode = {
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvf0.c
similarity index 99%
rename from drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/nvf0.c
index c306c0f2fc84..73f77fa04a62 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvf0.c
@@ -207,7 +207,7 @@ nvf0_graph_fini(struct nouveau_object *object, bool suspend)
return nouveau_graph_fini(&priv->base, suspend);
}
-#include "fuc/hubnvf0.fuc.h"
+#include "fuc/hubnvf0.fuc3.h"
struct nvc0_graph_ucode
nvf0_graph_fecs_ucode = {
@@ -217,7 +217,7 @@ nvf0_graph_fecs_ucode = {
.data.size = sizeof(nvf0_grhub_data),
};
-#include "fuc/gpcnvf0.fuc.h"
+#include "fuc/gpcnvf0.fuc3.h"
struct nvc0_graph_ucode
nvf0_graph_gpccs_ucode = {
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/regs.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/regs.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/graph/regs.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/graph/regs.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild
new file mode 100644
index 000000000000..39a045bcaf6e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild
@@ -0,0 +1,5 @@
+nvkm-y += nvkm/engine/mpeg/nv31.o
+nvkm-y += nvkm/engine/mpeg/nv40.o
+nvkm-y += nvkm/engine/mpeg/nv44.o
+nvkm-y += nvkm/engine/mpeg/nv50.o
+nvkm-y += nvkm/engine/mpeg/nv84.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.h b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/Kbuild
new file mode 100644
index 000000000000..d5f574c4e7b2
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/Kbuild
@@ -0,0 +1,9 @@
+nvkm-y += nvkm/engine/perfmon/base.o
+nvkm-y += nvkm/engine/perfmon/daemon.o
+nvkm-y += nvkm/engine/perfmon/nv40.o
+nvkm-y += nvkm/engine/perfmon/nv50.o
+nvkm-y += nvkm/engine/perfmon/nv84.o
+nvkm-y += nvkm/engine/perfmon/nva3.o
+nvkm-y += nvkm/engine/perfmon/nvc0.o
+nvkm-y += nvkm/engine/perfmon/nve0.o
+nvkm-y += nvkm/engine/perfmon/nvf0.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/perfmon/base.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/daemon.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/daemon.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/perfmon/daemon.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/perfmon/daemon.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/perfmon/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv84.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/perfmon/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv84.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nva3.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/perfmon/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nva3.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/perfmon/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nve0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvf0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/perfmon/nvf0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvf0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/perfmon/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/perfmon/priv.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ppp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/ppp/Kbuild
new file mode 100644
index 000000000000..0c1de976f45d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ppp/Kbuild
@@ -0,0 +1,2 @@
+nvkm-y += nvkm/engine/ppp/nv98.o
+nvkm-y += nvkm/engine/ppp/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/ppp/nv98.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/ppp/nv98.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/ppp/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/ppp/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild
new file mode 100644
index 000000000000..e1332a15dc1b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild
@@ -0,0 +1,4 @@
+nvkm-y += nvkm/engine/software/nv04.o
+nvkm-y += nvkm/engine/software/nv10.o
+nvkm-y += nvkm/engine/software/nv50.o
+nvkm-y += nvkm/engine/software/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/software/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/software/nv10.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/software/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/software/nv50.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
new file mode 100644
index 000000000000..6c1d9d1ede94
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
@@ -0,0 +1,4 @@
+nvkm-y += nvkm/engine/vp/nv84.o
+nvkm-y += nvkm/engine/vp/nv98.o
+nvkm-y += nvkm/engine/vp/nvc0.o
+nvkm-y += nvkm/engine/vp/nve0.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/vp/nv84.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/vp/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/vp/nv84.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/vp/nv98.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/vp/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/vp/nv98.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/vp/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/vp/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/vp/nve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/vp/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/vp/nve0.c
diff --git a/drivers/gpu/drm/nouveau/core/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/engine/xtensa.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
new file mode 100644
index 000000000000..10ef07cf3f91
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
@@ -0,0 +1,19 @@
+include $(src)/nvkm/subdev/bar/Kbuild
+include $(src)/nvkm/subdev/bios/Kbuild
+include $(src)/nvkm/subdev/bus/Kbuild
+include $(src)/nvkm/subdev/clock/Kbuild
+include $(src)/nvkm/subdev/devinit/Kbuild
+include $(src)/nvkm/subdev/fb/Kbuild
+include $(src)/nvkm/subdev/fuse/Kbuild
+include $(src)/nvkm/subdev/gpio/Kbuild
+include $(src)/nvkm/subdev/i2c/Kbuild
+include $(src)/nvkm/subdev/ibus/Kbuild
+include $(src)/nvkm/subdev/instmem/Kbuild
+include $(src)/nvkm/subdev/ltc/Kbuild
+include $(src)/nvkm/subdev/mc/Kbuild
+include $(src)/nvkm/subdev/mxm/Kbuild
+include $(src)/nvkm/subdev/pwr/Kbuild
+include $(src)/nvkm/subdev/therm/Kbuild
+include $(src)/nvkm/subdev/timer/Kbuild
+include $(src)/nvkm/subdev/vm/Kbuild
+include $(src)/nvkm/subdev/volt/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild
new file mode 100644
index 000000000000..922454f97de2
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild
@@ -0,0 +1,4 @@
+nvkm-y += nvkm/subdev/bar/base.o
+nvkm-y += nvkm/subdev/bar/nv50.o
+nvkm-y += nvkm/subdev/bar/nvc0.o
+nvkm-y += nvkm/subdev/bar/gk20a.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bar/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bar/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bar/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild
new file mode 100644
index 000000000000..64730d5e9351
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild
@@ -0,0 +1,37 @@
+nvkm-y += nvkm/subdev/bios/base.o
+nvkm-y += nvkm/subdev/bios/bit.o
+nvkm-y += nvkm/subdev/bios/boost.o
+nvkm-y += nvkm/subdev/bios/conn.o
+nvkm-y += nvkm/subdev/bios/cstep.o
+nvkm-y += nvkm/subdev/bios/dcb.o
+nvkm-y += nvkm/subdev/bios/disp.o
+nvkm-y += nvkm/subdev/bios/dp.o
+nvkm-y += nvkm/subdev/bios/extdev.o
+nvkm-y += nvkm/subdev/bios/fan.o
+nvkm-y += nvkm/subdev/bios/gpio.o
+nvkm-y += nvkm/subdev/bios/i2c.o
+nvkm-y += nvkm/subdev/bios/image.o
+nvkm-y += nvkm/subdev/bios/init.o
+nvkm-y += nvkm/subdev/bios/mxm.o
+nvkm-y += nvkm/subdev/bios/npde.o
+nvkm-y += nvkm/subdev/bios/pcir.o
+nvkm-y += nvkm/subdev/bios/perf.o
+nvkm-y += nvkm/subdev/bios/pll.o
+nvkm-y += nvkm/subdev/bios/pmu.o
+nvkm-y += nvkm/subdev/bios/ramcfg.o
+nvkm-y += nvkm/subdev/bios/rammap.o
+nvkm-y += nvkm/subdev/bios/shadow.o
+nvkm-y += nvkm/subdev/bios/shadowacpi.o
+nvkm-y += nvkm/subdev/bios/shadowof.o
+nvkm-y += nvkm/subdev/bios/shadowpci.o
+nvkm-y += nvkm/subdev/bios/shadowramin.o
+nvkm-y += nvkm/subdev/bios/shadowrom.o
+nvkm-y += nvkm/subdev/bios/timing.o
+nvkm-y += nvkm/subdev/bios/therm.o
+nvkm-y += nvkm/subdev/bios/vmap.o
+nvkm-y += nvkm/subdev/bios/volt.o
+nvkm-y += nvkm/subdev/bios/xpio.o
+nvkm-y += nvkm/subdev/bios/M0203.o
+nvkm-y += nvkm/subdev/bios/M0205.o
+nvkm-y += nvkm/subdev/bios/M0209.o
+nvkm-y += nvkm/subdev/bios/P0260.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0203.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/M0203.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/P0260.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/P0260.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/bit.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/bit.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/boost.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/boost.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/conn.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/conn.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/cstep.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/cstep.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/disp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/disp.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/dp.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/extdev.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/extdev.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/fan.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/i2c.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/i2c.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/image.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/image.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/init.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/mxm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/mxm.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/npde.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/npde.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/pcir.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/pcir.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/perf.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/pll.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/pll.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/pmu.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/pmu.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadow.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/shadow.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowacpi.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/shadowacpi.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowof.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/shadowof.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowpci.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/shadowpci.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowramin.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/shadowramin.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/shadowrom.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/shadowrom.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/therm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/therm.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/vmap.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/vmap.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/volt.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/volt.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/xpio.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bios/xpio.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild
new file mode 100644
index 000000000000..633e9b4b6a3a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild
@@ -0,0 +1,6 @@
+nvkm-y += nvkm/subdev/bus/hwsq.o
+nvkm-y += nvkm/subdev/bus/nv04.o
+nvkm-y += nvkm/subdev/bus/nv31.o
+nvkm-y += nvkm/subdev/bus/nv50.o
+nvkm-y += nvkm/subdev/bus/nv94.o
+nvkm-y += nvkm/subdev/bus/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv94.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bus/nv94.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv94.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bus/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild
new file mode 100644
index 000000000000..f0a86021fbb1
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild
@@ -0,0 +1,12 @@
+nvkm-y += nvkm/subdev/clock/base.o
+nvkm-y += nvkm/subdev/clock/nv04.o
+nvkm-y += nvkm/subdev/clock/nv40.o
+nvkm-y += nvkm/subdev/clock/nv50.o
+nvkm-y += nvkm/subdev/clock/nv84.o
+nvkm-y += nvkm/subdev/clock/nva3.o
+nvkm-y += nvkm/subdev/clock/nvaa.o
+nvkm-y += nvkm/subdev/clock/nvc0.o
+nvkm-y += nvkm/subdev/clock/nve0.o
+nvkm-y += nvkm/subdev/clock/gk20a.o
+nvkm-y += nvkm/subdev/clock/pllnv04.o
+nvkm-y += nvkm/subdev/clock/pllnva3.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/nv50.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/pll.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/seq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/clock/seq.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild
new file mode 100644
index 000000000000..4321e285c51c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild
@@ -0,0 +1,14 @@
+nvkm-y += nvkm/subdev/devinit/base.o
+nvkm-y += nvkm/subdev/devinit/nv04.o
+nvkm-y += nvkm/subdev/devinit/nv05.o
+nvkm-y += nvkm/subdev/devinit/nv10.o
+nvkm-y += nvkm/subdev/devinit/nv1a.o
+nvkm-y += nvkm/subdev/devinit/nv20.o
+nvkm-y += nvkm/subdev/devinit/nv50.o
+nvkm-y += nvkm/subdev/devinit/nv84.o
+nvkm-y += nvkm/subdev/devinit/nv98.o
+nvkm-y += nvkm/subdev/devinit/nva3.o
+nvkm-y += nvkm/subdev/devinit/nvaf.o
+nvkm-y += nvkm/subdev/devinit/nvc0.o
+nvkm-y += nvkm/subdev/devinit/gm107.o
+nvkm-y += nvkm/subdev/devinit/gm204.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/gm107.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/gm204.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/gm204.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild
new file mode 100644
index 000000000000..bfd0166d3e1b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild
@@ -0,0 +1,45 @@
+nvkm-y += nvkm/subdev/fb/base.o
+nvkm-y += nvkm/subdev/fb/nv04.o
+nvkm-y += nvkm/subdev/fb/nv10.o
+nvkm-y += nvkm/subdev/fb/nv1a.o
+nvkm-y += nvkm/subdev/fb/nv20.o
+nvkm-y += nvkm/subdev/fb/nv25.o
+nvkm-y += nvkm/subdev/fb/nv30.o
+nvkm-y += nvkm/subdev/fb/nv35.o
+nvkm-y += nvkm/subdev/fb/nv36.o
+nvkm-y += nvkm/subdev/fb/nv40.o
+nvkm-y += nvkm/subdev/fb/nv41.o
+nvkm-y += nvkm/subdev/fb/nv44.o
+nvkm-y += nvkm/subdev/fb/nv46.o
+nvkm-y += nvkm/subdev/fb/nv47.o
+nvkm-y += nvkm/subdev/fb/nv49.o
+nvkm-y += nvkm/subdev/fb/nv4e.o
+nvkm-y += nvkm/subdev/fb/nv50.o
+nvkm-y += nvkm/subdev/fb/nv84.o
+nvkm-y += nvkm/subdev/fb/nva3.o
+nvkm-y += nvkm/subdev/fb/nvaa.o
+nvkm-y += nvkm/subdev/fb/nvaf.o
+nvkm-y += nvkm/subdev/fb/nvc0.o
+nvkm-y += nvkm/subdev/fb/nve0.o
+nvkm-y += nvkm/subdev/fb/gk20a.o
+nvkm-y += nvkm/subdev/fb/gm107.o
+nvkm-y += nvkm/subdev/fb/ramnv04.o
+nvkm-y += nvkm/subdev/fb/ramnv10.o
+nvkm-y += nvkm/subdev/fb/ramnv1a.o
+nvkm-y += nvkm/subdev/fb/ramnv20.o
+nvkm-y += nvkm/subdev/fb/ramnv40.o
+nvkm-y += nvkm/subdev/fb/ramnv41.o
+nvkm-y += nvkm/subdev/fb/ramnv44.o
+nvkm-y += nvkm/subdev/fb/ramnv49.o
+nvkm-y += nvkm/subdev/fb/ramnv4e.o
+nvkm-y += nvkm/subdev/fb/ramnv50.o
+nvkm-y += nvkm/subdev/fb/ramnva3.o
+nvkm-y += nvkm/subdev/fb/ramnvaa.o
+nvkm-y += nvkm/subdev/fb/ramnvc0.o
+nvkm-y += nvkm/subdev/fb/ramnve0.o
+nvkm-y += nvkm/subdev/fb/ramgk20a.o
+nvkm-y += nvkm/subdev/fb/ramgm107.o
+nvkm-y += nvkm/subdev/fb/sddr2.o
+nvkm-y += nvkm/subdev/fb/sddr3.o
+nvkm-y += nvkm/subdev/fb/gddr3.o
+nvkm-y += nvkm/subdev/fb/gddr5.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/gddr3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/gm107.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv04.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv40.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv84.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv84.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nva3.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nva3.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaa.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaa.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaf.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaf.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/nve0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramgm107.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnv10.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnv1a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnv20.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnv40.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnv41.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnv44.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvaa.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvaa.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramseq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/ramseq.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb/regsnv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/include/subdev/fb/regsnv04.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild
new file mode 100644
index 000000000000..0458bce2ceeb
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild
@@ -0,0 +1,4 @@
+nvkm-y += nvkm/subdev/fuse/base.o
+nvkm-y += nvkm/subdev/fuse/g80.o
+nvkm-y += nvkm/subdev/fuse/gf100.o
+nvkm-y += nvkm/subdev/fuse/gm107.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fuse/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/g80.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fuse/g80.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild
new file mode 100644
index 000000000000..77bc88672af6
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild
@@ -0,0 +1,6 @@
+nvkm-y += nvkm/subdev/gpio/base.o
+nvkm-y += nvkm/subdev/gpio/nv10.o
+nvkm-y += nvkm/subdev/gpio/nv50.o
+nvkm-y += nvkm/subdev/gpio/nv94.o
+nvkm-y += nvkm/subdev/gpio/nvd0.o
+nvkm-y += nvkm/subdev/gpio/nve0.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/gpio/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv94.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv94.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nvd0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nvd0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/gpio/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nve0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild
new file mode 100644
index 000000000000..cc8bd8368358
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild
@@ -0,0 +1,16 @@
+nvkm-y += nvkm/subdev/i2c/base.o
+nvkm-y += nvkm/subdev/i2c/anx9805.o
+nvkm-y += nvkm/subdev/i2c/aux.o
+nvkm-y += nvkm/subdev/i2c/bit.o
+nvkm-y += nvkm/subdev/i2c/pad.o
+nvkm-y += nvkm/subdev/i2c/padnv04.o
+nvkm-y += nvkm/subdev/i2c/padnv94.o
+nvkm-y += nvkm/subdev/i2c/padgm204.o
+nvkm-y += nvkm/subdev/i2c/nv04.o
+nvkm-y += nvkm/subdev/i2c/nv4e.o
+nvkm-y += nvkm/subdev/i2c/nv50.o
+nvkm-y += nvkm/subdev/i2c/nv94.o
+nvkm-y += nvkm/subdev/i2c/nvd0.o
+nvkm-y += nvkm/subdev/i2c/gf117.o
+nvkm-y += nvkm/subdev/i2c/nve0.o
+nvkm-y += nvkm/subdev/i2c/gm204.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/anx9805.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/anx9805.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/aux.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/aux.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/bit.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/bit.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/gm204.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm204.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/gm204.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm204.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv94.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/nv94.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv94.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nvd0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nvd0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nve0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/padgm204.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm204.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/padgm204.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm204.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/padnv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv94.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv94.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/port.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/port.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/port.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/port.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/i2c/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild
new file mode 100644
index 000000000000..a006e535e450
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild
@@ -0,0 +1,3 @@
+nvkm-y += nvkm/subdev/ibus/nvc0.o
+nvkm-y += nvkm/subdev/ibus/nve0.o
+nvkm-y += nvkm/subdev/ibus/gk20a.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/ibus/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/ibus/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/ibus/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/nve0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/ibus/nve0.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild
new file mode 100644
index 000000000000..e6f35abe7879
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild
@@ -0,0 +1,4 @@
+nvkm-y += nvkm/subdev/instmem/base.o
+nvkm-y += nvkm/subdev/instmem/nv04.o
+nvkm-y += nvkm/subdev/instmem/nv40.o
+nvkm-y += nvkm/subdev/instmem/nv50.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/instmem/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
new file mode 100644
index 000000000000..e5df3d865f0c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
@@ -0,0 +1,4 @@
+nvkm-y += nvkm/subdev/ltc/base.o
+nvkm-y += nvkm/subdev/ltc/gf100.o
+nvkm-y += nvkm/subdev/ltc/gk104.o
+nvkm-y += nvkm/subdev/ltc/gm107.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/ltc/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild
new file mode 100644
index 000000000000..24b589b5001a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild
@@ -0,0 +1,11 @@
+nvkm-y += nvkm/subdev/mc/base.o
+nvkm-y += nvkm/subdev/mc/nv04.o
+nvkm-y += nvkm/subdev/mc/nv40.o
+nvkm-y += nvkm/subdev/mc/nv44.o
+nvkm-y += nvkm/subdev/mc/nv4c.o
+nvkm-y += nvkm/subdev/mc/nv50.o
+nvkm-y += nvkm/subdev/mc/nv94.o
+nvkm-y += nvkm/subdev/mc/nv98.o
+nvkm-y += nvkm/subdev/mc/nvc0.o
+nvkm-y += nvkm/subdev/mc/nvc3.o
+nvkm-y += nvkm/subdev/mc/gk20a.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mc/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mc/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv94.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mc/nv94.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv94.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc3.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc3.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mc/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild
new file mode 100644
index 000000000000..1a479e050b54
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild
@@ -0,0 +1,3 @@
+nvkm-y += nvkm/subdev/mxm/base.o
+nvkm-y += nvkm/subdev/mxm/mxms.o
+nvkm-y += nvkm/subdev/mxm/nv50.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mxm/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/mxm/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/Kbuild
new file mode 100644
index 000000000000..a664886040f4
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/Kbuild
@@ -0,0 +1,8 @@
+nvkm-y += nvkm/subdev/pwr/base.o
+nvkm-y += nvkm/subdev/pwr/memx.o
+nvkm-y += nvkm/subdev/pwr/nva3.o
+nvkm-y += nvkm/subdev/pwr/nvc0.o
+nvkm-y += nvkm/subdev/pwr/nvd0.o
+nvkm-y += nvkm/subdev/pwr/gk104.o
+nvkm-y += nvkm/subdev/pwr/nv108.o
+nvkm-y += nvkm/subdev/pwr/gk20a.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/arith.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/arith.fuc
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/host.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/host.fuc
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/i2c_.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/i2c_.fuc
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/idle.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/idle.fuc
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/kernel.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/kernel.fuc
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/macros.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/macros.fuc
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/memx.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/memx.fuc
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nv108.fuc5
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nv108.fuc5
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nv108.fuc5.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nv108.fuc5.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nva3.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nva3.fuc3
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nva3.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nva3.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvc0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvc0.fuc3
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvc0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvc0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvd0.fuc4
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvd0.fuc4
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvd0.fuc4.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvd0.fuc4.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/os.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/os.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/perf.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/perf.fuc
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/test.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/test.fuc
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk104.c
similarity index 98%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk104.c
index d76612999b9f..9bb419c90451 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk104.c
@@ -26,7 +26,7 @@
#define nvd0_pwr_code gk104_pwr_code
#define nvd0_pwr_data gk104_pwr_data
-#include "fuc/nvd0.fuc.h"
+#include "fuc/nvd0.fuc4.h"
static void
gk104_pwr_pgob(struct nouveau_pwr *ppwr, bool enable)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/memx.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/memx.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nv108.c
similarity index 98%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nv108.c
index 04ff7c3c34e9..dacee084a6b2 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nv108.c
@@ -23,7 +23,7 @@
*/
#include "priv.h"
-#include "fuc/nv108.fuc.h"
+#include "fuc/nv108.fuc5.h"
struct nouveau_oclass *
nv108_pwr_oclass = &(struct nvkm_pwr_impl) {
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nva3.c
similarity index 98%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nva3.c
index 998d53076b8b..f8325a697cd8 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nva3.c
@@ -23,7 +23,7 @@
*/
#include "priv.h"
-#include "fuc/nva3.fuc.h"
+#include "fuc/nva3.fuc3.h"
static int
nva3_pwr_init(struct nouveau_object *object)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nvc0.c
similarity index 98%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nvc0.c
index 9a773e66efa4..669417c23f9c 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nvc0.c
@@ -23,7 +23,7 @@
*/
#include "priv.h"
-#include "fuc/nvc0.fuc.h"
+#include "fuc/nvc0.fuc3.h"
struct nouveau_oclass *
nvc0_pwr_oclass = &(struct nvkm_pwr_impl) {
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nvd0.c
similarity index 98%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nvd0.c
index 2b29be5d08ac..d6e33d0a0544 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nvd0.c
@@ -23,7 +23,7 @@
*/
#include "priv.h"
-#include "fuc/nvd0.fuc.h"
+#include "fuc/nvd0.fuc4.h"
struct nouveau_oclass *
nvd0_pwr_oclass = &(struct nvkm_pwr_impl) {
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pwr/priv.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild
new file mode 100644
index 000000000000..9ac82070944a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild
@@ -0,0 +1,13 @@
+nvkm-y += nvkm/subdev/therm/base.o
+nvkm-y += nvkm/subdev/therm/fan.o
+nvkm-y += nvkm/subdev/therm/fannil.o
+nvkm-y += nvkm/subdev/therm/fanpwm.o
+nvkm-y += nvkm/subdev/therm/fantog.o
+nvkm-y += nvkm/subdev/therm/ic.o
+nvkm-y += nvkm/subdev/therm/temp.o
+nvkm-y += nvkm/subdev/therm/nv40.o
+nvkm-y += nvkm/subdev/therm/nv50.o
+nvkm-y += nvkm/subdev/therm/nv84.o
+nvkm-y += nvkm/subdev/therm/nva3.o
+nvkm-y += nvkm/subdev/therm/nvd0.o
+nvkm-y += nvkm/subdev/therm/gm107.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/fan.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fannil.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/fannil.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fantog.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/fantog.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/ic.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/ic.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv84.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv84.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nva3.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/nva3.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nvd0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/nvd0.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/temp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/therm/temp.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild
new file mode 100644
index 000000000000..d1d38b4ba30a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild
@@ -0,0 +1,3 @@
+nvkm-y += nvkm/subdev/timer/base.o
+nvkm-y += nvkm/subdev/timer/nv04.o
+nvkm-y += nvkm/subdev/timer/gk20a.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/timer/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/timer/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/timer/nv04.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/timer/priv.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild
new file mode 100644
index 000000000000..b0290c056630
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild
@@ -0,0 +1,6 @@
+nvkm-y += nvkm/subdev/vm/base.o
+nvkm-y += nvkm/subdev/vm/nv04.o
+nvkm-y += nvkm/subdev/vm/nv41.o
+nvkm-y += nvkm/subdev/vm/nv44.o
+nvkm-y += nvkm/subdev/vm/nv50.o
+nvkm-y += nvkm/subdev/vm/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/vm/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild
new file mode 100644
index 000000000000..6b46ff4213a3
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild
@@ -0,0 +1,4 @@
+nvkm-y += nvkm/subdev/volt/base.o
+nvkm-y += nvkm/subdev/volt/gpio.o
+nvkm-y += nvkm/subdev/volt/nv40.o
+nvkm-y += nvkm/subdev/volt/gk20a.o
diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/volt/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/volt/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/gpio.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/volt/gpio.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.c
diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/core/subdev/volt/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c
From f3867f439fd610db0cbcf1bb739001e95b7b25c6 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Tue, 13 Jan 2015 23:37:38 +1000
Subject: [PATCH 37/86] drm/nouveau/clk: rename from clock (no binary change)
Rename to match the Linux subsystem responsible for the same kind of
things. Will be investigating how feasible it will be to expose the
GPU clock trees with it at some point.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4 +-
drivers/gpu/drm/nouveau/dispnv04/hw.c | 4 +-
drivers/gpu/drm/nouveau/include/nvif/device.h | 4 +-
.../drm/nouveau/include/nvkm/core/device.h | 2 +-
.../gpu/drm/nouveau/include/nvkm/subdev/clk.h | 166 ++++++++++++++++++
.../drm/nouveau/include/nvkm/subdev/clock.h | 166 ------------------
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/device/ctrl.c | 16 +-
.../drm/nouveau/nvkm/engine/device/gm100.c | 6 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv04.c | 6 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv10.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv20.c | 10 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv30.c | 12 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv40.c | 34 ++--
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 30 ++--
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 20 +--
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 18 +-
.../drm/nouveau/nvkm/engine/perfmon/base.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/clk/Kbuild | 12 ++
.../nouveau/nvkm/subdev/{clock => clk}/base.c | 78 ++++----
.../nvkm/subdev/{clock => clk}/gk20a.c | 80 ++++-----
.../nouveau/nvkm/subdev/{clock => clk}/nv04.c | 34 ++--
.../nouveau/nvkm/subdev/{clock => clk}/nv40.c | 64 +++----
.../nouveau/nvkm/subdev/{clock => clk}/nv50.c | 64 +++----
.../nouveau/nvkm/subdev/{clock => clk}/nv50.h | 16 +-
.../nouveau/nvkm/subdev/{clock => clk}/nv84.c | 14 +-
.../nouveau/nvkm/subdev/{clock => clk}/nva3.c | 106 +++++------
.../gpu/drm/nouveau/nvkm/subdev/clk/nva3.h | 20 +++
.../nouveau/nvkm/subdev/{clock => clk}/nvaa.c | 60 +++----
.../nouveau/nvkm/subdev/{clock => clk}/nvc0.c | 108 ++++++------
.../nouveau/nvkm/subdev/{clock => clk}/nve0.c | 118 ++++++-------
.../nouveau/nvkm/subdev/{clock => clk}/pll.h | 0
.../nvkm/subdev/{clock => clk}/pllnv04.c | 0
.../nvkm/subdev/{clock => clk}/pllnva3.c | 2 +-
.../nouveau/nvkm/subdev/{clock => clk}/seq.h | 0
.../gpu/drm/nouveau/nvkm/subdev/clock/Kbuild | 12 --
.../gpu/drm/nouveau/nvkm/subdev/clock/nva3.h | 20 ---
.../drm/nouveau/nvkm/subdev/devinit/priv.h | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c | 4 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c | 18 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c | 6 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c | 6 +-
.../gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c | 12 +-
45 files changed, 690 insertions(+), 690 deletions(-)
create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/base.c (85%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/gk20a.c (89%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/nv04.c (76%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/nv40.c (77%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/nv50.c (90%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/nv50.h (59%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/nv84.c (86%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/nva3.c (80%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/nvaa.c (88%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/nvc0.c (78%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/nve0.c (77%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/pll.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/pllnv04.c (100%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/pllnva3.c (98%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{clock => clk}/seq.h (100%)
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
index 38402ade6835..f8ddae26dfbf 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
@@ -41,7 +41,7 @@
#include "disp.h"
#include <subdev/bios/pll.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
static int
nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
@@ -113,7 +113,7 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod
struct drm_device *dev = crtc->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_bios *bios = nvkm_bios(&drm->device);
- struct nouveau_clock *clk = nvkm_clock(&drm->device);
+ struct nouveau_clk *clk = nvkm_clk(&drm->device);
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
index 3d4c19300768..f9491f926c14 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -253,7 +253,7 @@ nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
- struct nouveau_clock *clk = nvkm_clock(device);
+ struct nouveau_clk *clk = nvkm_clk(device);
struct nouveau_bios *bios = nvkm_bios(device);
struct nvbios_pll pll_lim;
struct nouveau_pll_vals pv;
@@ -463,7 +463,7 @@ nv_load_state_ramdac(struct drm_device *dev, int head,
struct nv04_mode_state *state)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_clock *clk = nvkm_clock(&drm->device);
+ struct nouveau_clk *clk = nvkm_clk(&drm->device);
struct nv04_crtc_reg *regp = &state->crtc_reg[head];
uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
int i;
diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h
index 4aa1b93a8cd4..e73a16dd97fa 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/device.h
@@ -32,7 +32,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
#include <subdev/vm.h>
#include <subdev/bar.h>
#include <subdev/gpio.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/i2c.h>
#include <subdev/timer.h>
#include <subdev/therm.h>
@@ -43,7 +43,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
#define nvkm_vmmgr(a) nouveau_vmmgr(nvkm_device(a))
#define nvkm_bar(a) nouveau_bar(nvkm_device(a))
#define nvkm_gpio(a) nouveau_gpio(nvkm_device(a))
-#define nvkm_clock(a) nouveau_clock(nvkm_device(a))
+#define nvkm_clk(a) nouveau_clk(nvkm_device(a))
#define nvkm_i2c(a) nouveau_i2c(nvkm_device(a))
#define nvkm_timer(a) nouveau_timer(nvkm_device(a))
#define nvkm_wait(a,b,c,d) nv_wait(nvkm_timer(a), (b), (c), (d))
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 21a055aca513..87ecf6d23d9e 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -38,7 +38,7 @@ enum nv_subdev_type {
NVDEV_SUBDEV_PWR,
NVDEV_SUBDEV_VOLT,
NVDEV_SUBDEV_THERM,
- NVDEV_SUBDEV_CLOCK,
+ NVDEV_SUBDEV_CLK,
NVDEV_ENGINE_FIRST,
NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
new file mode 100644
index 000000000000..4524d4eea2f1
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
@@ -0,0 +1,166 @@
+#ifndef __NOUVEAU_CLK_H__
+#define __NOUVEAU_CLK_H__
+
+#include <core/device.h>
+#include <core/subdev.h>
+
+struct nouveau_pll_vals;
+struct nvbios_pll;
+
+enum nv_clk_src {
+ nv_clk_src_crystal,
+ nv_clk_src_href,
+
+ nv_clk_src_hclk,
+ nv_clk_src_hclkm3,
+ nv_clk_src_hclkm3d2,
+ nv_clk_src_hclkm2d3, /* NVAA */
+ nv_clk_src_hclkm4, /* NVAA */
+ nv_clk_src_cclk, /* NVAA */
+
+ nv_clk_src_host,
+
+ nv_clk_src_sppll0,
+ nv_clk_src_sppll1,
+
+ nv_clk_src_mpllsrcref,
+ nv_clk_src_mpllsrc,
+ nv_clk_src_mpll,
+ nv_clk_src_mdiv,
+
+ nv_clk_src_core,
+ nv_clk_src_core_intm,
+ nv_clk_src_shader,
+
+ nv_clk_src_mem,
+
+ nv_clk_src_gpc,
+ nv_clk_src_rop,
+ nv_clk_src_hubk01,
+ nv_clk_src_hubk06,
+ nv_clk_src_hubk07,
+ nv_clk_src_copy,
+ nv_clk_src_daemon,
+ nv_clk_src_disp,
+ nv_clk_src_vdec,
+
+ nv_clk_src_dom6,
+
+ nv_clk_src_max,
+};
+
+struct nouveau_cstate {
+ struct list_head head;
+ u8 voltage;
+ u32 domain[nv_clk_src_max];
+};
+
+struct nouveau_pstate {
+ struct list_head head;
+ struct list_head list; /* c-states */
+ struct nouveau_cstate base;
+ u8 pstate;
+ u8 fanspeed;
+};
+
+struct nouveau_clk {
+ struct nouveau_subdev base;
+
+ struct nouveau_domain *domains;
+ struct nouveau_pstate bstate;
+
+ struct list_head states;
+ int state_nr;
+
+ struct work_struct work;
+ wait_queue_head_t wait;
+ atomic_t waiting;
+
+ struct nvkm_notify pwrsrc_ntfy;
+ int pwrsrc;
+ int pstate; /* current */
+ int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */
+ int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */
+ int astate; /* perfmon adjustment (base) */
+ int tstate; /* thermal adjustment (max-) */
+ int dstate; /* display adjustment (min+) */
+
+ bool allow_reclock;
+
+ int (*read)(struct nouveau_clk *, enum nv_clk_src);
+ int (*calc)(struct nouveau_clk *, struct nouveau_cstate *);
+ int (*prog)(struct nouveau_clk *);
+ void (*tidy)(struct nouveau_clk *);
+
+ /*XXX: die, these are here *only* to support the completely
+ * bat-shit insane what-was-nouveau_hw.c code
+ */
+ int (*pll_calc)(struct nouveau_clk *, struct nvbios_pll *,
+ int clk, struct nouveau_pll_vals *pv);
+ int (*pll_prog)(struct nouveau_clk *, u32 reg1,
+ struct nouveau_pll_vals *pv);
+};
+
+static inline struct nouveau_clk *
+nouveau_clk(void *obj)
+{
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_CLK);
+}
+
+struct nouveau_domain {
+ enum nv_clk_src name;
+ u8 bios; /* 0xff for none */
+#define NVKM_CLK_DOM_FLAG_CORE 0x01
+ u8 flags;
+ const char *mname;
+ int mdiv;
+};
+
+#define nouveau_clk_create(p,e,o,i,r,s,n,d) \
+ nouveau_clk_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \
+ (void **)d)
+#define nouveau_clk_destroy(p) ({ \
+ struct nouveau_clk *clk = (p); \
+ _nouveau_clk_dtor(nv_object(clk)); \
+})
+#define nouveau_clk_init(p) ({ \
+ struct nouveau_clk *clk = (p); \
+ _nouveau_clk_init(nv_object(clk)); \
+})
+#define nouveau_clk_fini(p,s) ({ \
+ struct nouveau_clk *clk = (p); \
+ _nouveau_clk_fini(nv_object(clk), (s)); \
+})
+
+int nouveau_clk_create_(struct nouveau_object *, struct nouveau_object *,
+ struct nouveau_oclass *,
+ struct nouveau_domain *, struct nouveau_pstate *,
+ int, bool, int, void **);
+void _nouveau_clk_dtor(struct nouveau_object *);
+int _nouveau_clk_init(struct nouveau_object *);
+int _nouveau_clk_fini(struct nouveau_object *, bool);
+
+extern struct nouveau_oclass nv04_clk_oclass;
+extern struct nouveau_oclass nv40_clk_oclass;
+extern struct nouveau_oclass *nv50_clk_oclass;
+extern struct nouveau_oclass *nv84_clk_oclass;
+extern struct nouveau_oclass *nvaa_clk_oclass;
+extern struct nouveau_oclass nva3_clk_oclass;
+extern struct nouveau_oclass nvc0_clk_oclass;
+extern struct nouveau_oclass nve0_clk_oclass;
+extern struct nouveau_oclass gk20a_clk_oclass;
+
+int nv04_clk_pll_set(struct nouveau_clk *, u32 type, u32 freq);
+int nv04_clk_pll_calc(struct nouveau_clk *, struct nvbios_pll *,
+ int clk, struct nouveau_pll_vals *);
+int nv04_clk_pll_prog(struct nouveau_clk *, u32 reg1,
+ struct nouveau_pll_vals *);
+int nva3_clk_pll_calc(struct nouveau_clk *, struct nvbios_pll *,
+ int clk, struct nouveau_pll_vals *);
+
+int nouveau_clk_ustate(struct nouveau_clk *, int req, int pwr);
+int nouveau_clk_astate(struct nouveau_clk *, int req, int rel, bool wait);
+int nouveau_clk_dstate(struct nouveau_clk *, int req, int rel);
+int nouveau_clk_tstate(struct nouveau_clk *, int req, int rel);
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h
deleted file mode 100644
index 39ad2d2cee2a..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h
+++ /dev/null
@@ -1,166 +0,0 @@
-#ifndef __NOUVEAU_CLOCK_H__
-#define __NOUVEAU_CLOCK_H__
-
-#include <core/device.h>
-#include <core/subdev.h>
-
-struct nouveau_pll_vals;
-struct nvbios_pll;
-
-enum nv_clk_src {
- nv_clk_src_crystal,
- nv_clk_src_href,
-
- nv_clk_src_hclk,
- nv_clk_src_hclkm3,
- nv_clk_src_hclkm3d2,
- nv_clk_src_hclkm2d3, /* NVAA */
- nv_clk_src_hclkm4, /* NVAA */
- nv_clk_src_cclk, /* NVAA */
-
- nv_clk_src_host,
-
- nv_clk_src_sppll0,
- nv_clk_src_sppll1,
-
- nv_clk_src_mpllsrcref,
- nv_clk_src_mpllsrc,
- nv_clk_src_mpll,
- nv_clk_src_mdiv,
-
- nv_clk_src_core,
- nv_clk_src_core_intm,
- nv_clk_src_shader,
-
- nv_clk_src_mem,
-
- nv_clk_src_gpc,
- nv_clk_src_rop,
- nv_clk_src_hubk01,
- nv_clk_src_hubk06,
- nv_clk_src_hubk07,
- nv_clk_src_copy,
- nv_clk_src_daemon,
- nv_clk_src_disp,
- nv_clk_src_vdec,
-
- nv_clk_src_dom6,
-
- nv_clk_src_max,
-};
-
-struct nouveau_cstate {
- struct list_head head;
- u8 voltage;
- u32 domain[nv_clk_src_max];
-};
-
-struct nouveau_pstate {
- struct list_head head;
- struct list_head list; /* c-states */
- struct nouveau_cstate base;
- u8 pstate;
- u8 fanspeed;
-};
-
-struct nouveau_clock {
- struct nouveau_subdev base;
-
- struct nouveau_clocks *domains;
- struct nouveau_pstate bstate;
-
- struct list_head states;
- int state_nr;
-
- struct work_struct work;
- wait_queue_head_t wait;
- atomic_t waiting;
-
- struct nvkm_notify pwrsrc_ntfy;
- int pwrsrc;
- int pstate; /* current */
- int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */
- int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */
- int astate; /* perfmon adjustment (base) */
- int tstate; /* thermal adjustment (max-) */
- int dstate; /* display adjustment (min+) */
-
- bool allow_reclock;
-
- int (*read)(struct nouveau_clock *, enum nv_clk_src);
- int (*calc)(struct nouveau_clock *, struct nouveau_cstate *);
- int (*prog)(struct nouveau_clock *);
- void (*tidy)(struct nouveau_clock *);
-
- /*XXX: die, these are here *only* to support the completely
- * bat-shit insane what-was-nouveau_hw.c code
- */
- int (*pll_calc)(struct nouveau_clock *, struct nvbios_pll *,
- int clk, struct nouveau_pll_vals *pv);
- int (*pll_prog)(struct nouveau_clock *, u32 reg1,
- struct nouveau_pll_vals *pv);
-};
-
-static inline struct nouveau_clock *
-nouveau_clock(void *obj)
-{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_CLOCK);
-}
-
-struct nouveau_clocks {
- enum nv_clk_src name;
- u8 bios; /* 0xff for none */
-#define NVKM_CLK_DOM_FLAG_CORE 0x01
- u8 flags;
- const char *mname;
- int mdiv;
-};
-
-#define nouveau_clock_create(p,e,o,i,r,s,n,d) \
- nouveau_clock_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \
- (void **)d)
-#define nouveau_clock_destroy(p) ({ \
- struct nouveau_clock *clk = (p); \
- _nouveau_clock_dtor(nv_object(clk)); \
-})
-#define nouveau_clock_init(p) ({ \
- struct nouveau_clock *clk = (p); \
- _nouveau_clock_init(nv_object(clk)); \
-})
-#define nouveau_clock_fini(p,s) ({ \
- struct nouveau_clock *clk = (p); \
- _nouveau_clock_fini(nv_object(clk), (s)); \
-})
-
-int nouveau_clock_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *,
- struct nouveau_clocks *, struct nouveau_pstate *,
- int, bool, int, void **);
-void _nouveau_clock_dtor(struct nouveau_object *);
-int _nouveau_clock_init(struct nouveau_object *);
-int _nouveau_clock_fini(struct nouveau_object *, bool);
-
-extern struct nouveau_oclass nv04_clock_oclass;
-extern struct nouveau_oclass nv40_clock_oclass;
-extern struct nouveau_oclass *nv50_clock_oclass;
-extern struct nouveau_oclass *nv84_clock_oclass;
-extern struct nouveau_oclass *nvaa_clock_oclass;
-extern struct nouveau_oclass nva3_clock_oclass;
-extern struct nouveau_oclass nvc0_clock_oclass;
-extern struct nouveau_oclass nve0_clock_oclass;
-extern struct nouveau_oclass gk20a_clock_oclass;
-
-int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq);
-int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
- int clk, struct nouveau_pll_vals *);
-int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1,
- struct nouveau_pll_vals *);
-int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
- int clk, struct nouveau_pll_vals *);
-
-int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr);
-int nouveau_clock_astate(struct nouveau_clock *, int req, int rel, bool wait);
-int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel);
-int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index f74f9cbbf3d8..f9589e8935d9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -209,7 +209,7 @@ static const u64 disable_map[] = {
[NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_GPIO] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_I2C] = NV_DEVICE_V0_DISABLE_CORE,
- [NVDEV_SUBDEV_CLOCK] = NV_DEVICE_V0_DISABLE_CORE,
+ [NVDEV_SUBDEV_CLK ] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_MXM] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_MC] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_BUS] = NV_DEVICE_V0_DISABLE_CORE,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
index e34101a3490e..7a7632e65c77 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
@@ -28,7 +28,7 @@
#include <nvif/class.h>
#include <nvif/ioctl.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include "priv.h"
@@ -39,7 +39,7 @@ nouveau_control_mthd_pstate_info(struct nouveau_object *object,
union {
struct nvif_control_pstate_info_v0 v0;
} *args = data;
- struct nouveau_clock *clk = nouveau_clock(object);
+ struct nouveau_clk *clk = nouveau_clk(object);
int ret;
nv_ioctl(object, "control pstate info size %d\n", size);
@@ -73,8 +73,8 @@ nouveau_control_mthd_pstate_attr(struct nouveau_object *object,
union {
struct nvif_control_pstate_attr_v0 v0;
} *args = data;
- struct nouveau_clock *clk = nouveau_clock(object);
- struct nouveau_clocks *domain;
+ struct nouveau_clk *clk = nouveau_clk(object);
+ struct nouveau_domain *domain;
struct nouveau_pstate *pstate;
struct nouveau_cstate *cstate;
int i = 0, j = -1;
@@ -147,7 +147,7 @@ nouveau_control_mthd_pstate_user(struct nouveau_object *object,
union {
struct nvif_control_pstate_user_v0 v0;
} *args = data;
- struct nouveau_clock *clk = nouveau_clock(object);
+ struct nouveau_clk *clk = nouveau_clk(object);
int ret;
nv_ioctl(object, "control pstate user size %d\n", size);
@@ -161,10 +161,10 @@ nouveau_control_mthd_pstate_user(struct nouveau_object *object,
return ret;
if (args->v0.pwrsrc >= 0) {
- ret |= nouveau_clock_ustate(clk, args->v0.ustate, args->v0.pwrsrc);
+ ret |= nouveau_clk_ustate(clk, args->v0.ustate, args->v0.pwrsrc);
} else {
- ret |= nouveau_clock_ustate(clk, args->v0.ustate, 0);
- ret |= nouveau_clock_ustate(clk, args->v0.ustate, 1);
+ ret |= nouveau_clk_ustate(clk, args->v0.ustate, 0);
+ ret |= nouveau_clk_ustate(clk, args->v0.ustate, 1);
}
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 4e74a3376de8..e453a52135d7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -27,7 +27,7 @@
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/fuse.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
@@ -64,7 +64,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
@@ -106,7 +106,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
#if 0
/* looks to be some non-trivial changes */
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
/* priv ring says no to 0x10eb14 writes */
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index 573b55f5c2f9..dff51984ea94 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -25,7 +25,7 @@
#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/i2c.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
@@ -48,7 +48,7 @@ nv04_identify(struct nouveau_device *device)
device->cname = "NV04";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -66,7 +66,7 @@ nv04_identify(struct nouveau_device *device)
device->cname = "NV05";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index 183a85a6204e..af63f5b95f01 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -26,7 +26,7 @@
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
@@ -50,7 +50,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -67,7 +67,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -86,7 +86,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -105,7 +105,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -124,7 +124,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -143,7 +143,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -162,7 +162,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -181,7 +181,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index aa564c68a920..eddeb126c7ec 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -26,7 +26,7 @@
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
@@ -51,7 +51,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -70,7 +70,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -89,7 +89,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -108,7 +108,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index 11bd31da82ab..6fe2d130a2ce 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -26,7 +26,7 @@
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
@@ -51,7 +51,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -70,7 +70,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -89,7 +89,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
@@ -109,7 +109,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
@@ -129,7 +129,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index e96c223cb797..d85edd87cec8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -27,7 +27,7 @@
#include <subdev/vm.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
@@ -55,7 +55,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -78,7 +78,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -101,7 +101,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -124,7 +124,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -147,7 +147,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -170,7 +170,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -193,7 +193,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -216,7 +216,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -239,7 +239,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
@@ -262,7 +262,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
@@ -285,7 +285,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
@@ -308,7 +308,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
@@ -331,7 +331,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
@@ -354,7 +354,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
@@ -377,7 +377,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
@@ -400,7 +400,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 96f568d1321b..ccf82ab16881 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -27,7 +27,7 @@
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/fuse.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
@@ -64,7 +64,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv50_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
@@ -90,7 +90,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -119,7 +119,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -148,7 +148,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -177,7 +177,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -206,7 +206,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -235,7 +235,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
@@ -264,7 +264,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -293,7 +293,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
@@ -322,7 +322,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
@@ -351,7 +351,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
@@ -382,7 +382,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
@@ -412,7 +412,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
@@ -442,7 +442,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 72a40f95d048..ff5b2ab674bd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -27,7 +27,7 @@
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/fuse.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
@@ -64,7 +64,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -97,7 +97,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -130,7 +130,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -162,7 +162,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -195,7 +195,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -227,7 +227,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -259,7 +259,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -292,7 +292,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -324,7 +324,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index d308aee028f0..7c02ff5b13ed 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -27,7 +27,7 @@
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/fuse.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
@@ -64,7 +64,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -98,7 +98,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -132,7 +132,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -162,7 +162,7 @@ nve0_identify(struct nouveau_device *device)
break;
case 0xea:
device->cname = "GK20A";
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &gk20a_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -188,7 +188,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -222,7 +222,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -256,7 +256,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -289,7 +289,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c
index 63013812f7c9..3a9359e29179 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c
@@ -28,7 +28,7 @@
#include <nvif/class.h>
#include <nvif/ioctl.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include "priv.h"
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
index 10ef07cf3f91..39f800a6f1e4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
@@ -1,7 +1,7 @@
include $(src)/nvkm/subdev/bar/Kbuild
include $(src)/nvkm/subdev/bios/Kbuild
include $(src)/nvkm/subdev/bus/Kbuild
-include $(src)/nvkm/subdev/clock/Kbuild
+include $(src)/nvkm/subdev/clk/Kbuild
include $(src)/nvkm/subdev/devinit/Kbuild
include $(src)/nvkm/subdev/fb/Kbuild
include $(src)/nvkm/subdev/fuse/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
new file mode 100644
index 000000000000..94d10a9e637a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
@@ -0,0 +1,12 @@
+nvkm-y += nvkm/subdev/clk/base.o
+nvkm-y += nvkm/subdev/clk/nv04.o
+nvkm-y += nvkm/subdev/clk/nv40.o
+nvkm-y += nvkm/subdev/clk/nv50.o
+nvkm-y += nvkm/subdev/clk/nv84.o
+nvkm-y += nvkm/subdev/clk/nva3.o
+nvkm-y += nvkm/subdev/clk/nvaa.o
+nvkm-y += nvkm/subdev/clk/nvc0.o
+nvkm-y += nvkm/subdev/clk/nve0.o
+nvkm-y += nvkm/subdev/clk/gk20a.o
+nvkm-y += nvkm/subdev/clk/pllnv04.o
+nvkm-y += nvkm/subdev/clk/pllnva3.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
similarity index 85%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
index bc095b470121..a0c21ec3f61d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
@@ -24,7 +24,7 @@
#include <core/option.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/volt.h>
#include <subdev/fb.h>
@@ -38,7 +38,7 @@
* misc
*****************************************************************************/
static u32
-nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust,
+nouveau_clk_adjust(struct nouveau_clk *clk, bool adjust,
u8 pstate, u8 domain, u32 input)
{
struct nouveau_bios *bios = nouveau_bios(clk);
@@ -76,7 +76,7 @@ nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust,
* C-States
*****************************************************************************/
static int
-nouveau_cstate_prog(struct nouveau_clock *clk,
+nouveau_cstate_prog(struct nouveau_clk *clk,
struct nouveau_pstate *pstate, int cstatei)
{
struct nouveau_therm *ptherm = nouveau_therm(clk);
@@ -135,11 +135,11 @@ nouveau_cstate_del(struct nouveau_cstate *cstate)
}
static int
-nouveau_cstate_new(struct nouveau_clock *clk, int idx,
+nouveau_cstate_new(struct nouveau_clk *clk, int idx,
struct nouveau_pstate *pstate)
{
struct nouveau_bios *bios = nouveau_bios(clk);
- struct nouveau_clocks *domain = clk->domains;
+ struct nouveau_domain *domain = clk->domains;
struct nouveau_cstate *cstate = NULL;
struct nvbios_cstepX cstepX;
u8 ver, hdr;
@@ -158,7 +158,7 @@ nouveau_cstate_new(struct nouveau_clock *clk, int idx,
while (domain && domain->name != nv_clk_src_max) {
if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
- u32 freq = nouveau_clock_adjust(clk, true,
+ u32 freq = nouveau_clk_adjust(clk, true,
pstate->pstate,
domain->bios,
cstepX.freq);
@@ -175,7 +175,7 @@ nouveau_cstate_new(struct nouveau_clock *clk, int idx,
* P-States
*****************************************************************************/
static int
-nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei)
+nouveau_pstate_prog(struct nouveau_clk *clk, int pstatei)
{
struct nouveau_fb *pfb = nouveau_fb(clk);
struct nouveau_pstate *pstate;
@@ -205,7 +205,7 @@ nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei)
static void
nouveau_pstate_work(struct work_struct *work)
{
- struct nouveau_clock *clk = container_of(work, typeof(*clk), work);
+ struct nouveau_clk *clk = container_of(work, typeof(*clk), work);
int pstate;
if (!atomic_xchg(&clk->waiting, 0))
@@ -239,7 +239,7 @@ nouveau_pstate_work(struct work_struct *work)
}
static int
-nouveau_pstate_calc(struct nouveau_clock *clk, bool wait)
+nouveau_pstate_calc(struct nouveau_clk *clk, bool wait)
{
atomic_set(&clk->waiting, 1);
schedule_work(&clk->work);
@@ -249,9 +249,9 @@ nouveau_pstate_calc(struct nouveau_clock *clk, bool wait)
}
static void
-nouveau_pstate_info(struct nouveau_clock *clk, struct nouveau_pstate *pstate)
+nouveau_pstate_info(struct nouveau_clk *clk, struct nouveau_pstate *pstate)
{
- struct nouveau_clocks *clock = clk->domains - 1;
+ struct nouveau_domain *clock = clk->domains - 1;
struct nouveau_cstate *cstate;
char info[3][32] = { "", "", "" };
char name[4] = "--";
@@ -304,10 +304,10 @@ nouveau_pstate_del(struct nouveau_pstate *pstate)
}
static int
-nouveau_pstate_new(struct nouveau_clock *clk, int idx)
+nouveau_pstate_new(struct nouveau_clk *clk, int idx)
{
struct nouveau_bios *bios = nouveau_bios(clk);
- struct nouveau_clocks *domain = clk->domains - 1;
+ struct nouveau_domain *domain = clk->domains - 1;
struct nouveau_pstate *pstate;
struct nouveau_cstate *cstate;
struct nvbios_cstepE cstepE;
@@ -346,7 +346,7 @@ nouveau_pstate_new(struct nouveau_clock *clk, int idx)
continue;
if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
- perfS.v40.freq = nouveau_clock_adjust(clk, false,
+ perfS.v40.freq = nouveau_clk_adjust(clk, false,
pstate->pstate,
domain->bios,
perfS.v40.freq);
@@ -373,7 +373,7 @@ nouveau_pstate_new(struct nouveau_clock *clk, int idx)
* Adjustment triggers
*****************************************************************************/
static int
-nouveau_clock_ustate_update(struct nouveau_clock *clk, int req)
+nouveau_clk_ustate_update(struct nouveau_clk *clk, int req)
{
struct nouveau_pstate *pstate;
int i = 0;
@@ -397,7 +397,7 @@ nouveau_clock_ustate_update(struct nouveau_clock *clk, int req)
}
static int
-nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen)
+nouveau_clk_nstate(struct nouveau_clk *clk, const char *mode, int arglen)
{
int ret = 1;
@@ -410,7 +410,7 @@ nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen)
((char *)mode)[arglen] = '\0';
if (!kstrtol(mode, 0, &v)) {
- ret = nouveau_clock_ustate_update(clk, v);
+ ret = nouveau_clk_ustate_update(clk, v);
if (ret < 0)
ret = 1;
}
@@ -421,9 +421,9 @@ nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen)
}
int
-nouveau_clock_ustate(struct nouveau_clock *clk, int req, int pwr)
+nouveau_clk_ustate(struct nouveau_clk *clk, int req, int pwr)
{
- int ret = nouveau_clock_ustate_update(clk, req);
+ int ret = nouveau_clk_ustate_update(clk, req);
if (ret >= 0) {
if (ret -= 2, pwr) clk->ustate_ac = ret;
else clk->ustate_dc = ret;
@@ -433,7 +433,7 @@ nouveau_clock_ustate(struct nouveau_clock *clk, int req, int pwr)
}
int
-nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel, bool wait)
+nouveau_clk_astate(struct nouveau_clk *clk, int req, int rel, bool wait)
{
if (!rel) clk->astate = req;
if ( rel) clk->astate += rel;
@@ -443,7 +443,7 @@ nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel, bool wait)
}
int
-nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel)
+nouveau_clk_tstate(struct nouveau_clk *clk, int req, int rel)
{
if (!rel) clk->tstate = req;
if ( rel) clk->tstate += rel;
@@ -453,7 +453,7 @@ nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel)
}
int
-nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel)
+nouveau_clk_dstate(struct nouveau_clk *clk, int req, int rel)
{
if (!rel) clk->dstate = req;
if ( rel) clk->dstate += rel;
@@ -463,9 +463,9 @@ nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel)
}
static int
-nouveau_clock_pwrsrc(struct nvkm_notify *notify)
+nouveau_clk_pwrsrc(struct nvkm_notify *notify)
{
- struct nouveau_clock *clk =
+ struct nouveau_clk *clk =
container_of(notify, typeof(*clk), pwrsrc_ntfy);
nouveau_pstate_calc(clk, false);
return NVKM_NOTIFY_DROP;
@@ -476,18 +476,18 @@ nouveau_clock_pwrsrc(struct nvkm_notify *notify)
*****************************************************************************/
int
-_nouveau_clock_fini(struct nouveau_object *object, bool suspend)
+_nouveau_clk_fini(struct nouveau_object *object, bool suspend)
{
- struct nouveau_clock *clk = (void *)object;
+ struct nouveau_clk *clk = (void *)object;
nvkm_notify_put(&clk->pwrsrc_ntfy);
return nouveau_subdev_fini(&clk->base, suspend);
}
int
-_nouveau_clock_init(struct nouveau_object *object)
+_nouveau_clk_init(struct nouveau_object *object)
{
- struct nouveau_clock *clk = (void *)object;
- struct nouveau_clocks *clock = clk->domains;
+ struct nouveau_clk *clk = (void *)object;
+ struct nouveau_domain *clock = clk->domains;
int ret;
ret = nouveau_subdev_init(&clk->base);
@@ -519,9 +519,9 @@ _nouveau_clock_init(struct nouveau_object *object)
}
void
-_nouveau_clock_dtor(struct nouveau_object *object)
+_nouveau_clk_dtor(struct nouveau_object *object)
{
- struct nouveau_clock *clk = (void *)object;
+ struct nouveau_clk *clk = (void *)object;
struct nouveau_pstate *pstate, *temp;
nvkm_notify_fini(&clk->pwrsrc_ntfy);
@@ -534,16 +534,16 @@ _nouveau_clock_dtor(struct nouveau_object *object)
}
int
-nouveau_clock_create_(struct nouveau_object *parent,
+nouveau_clk_create_(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass,
- struct nouveau_clocks *clocks,
+ struct nouveau_domain *clocks,
struct nouveau_pstate *pstates, int nb_pstates,
bool allow_reclock,
int length, void **object)
{
struct nouveau_device *device = nv_device(parent);
- struct nouveau_clock *clk;
+ struct nouveau_clk *clk;
int ret, idx, arglen;
const char *mode;
@@ -576,24 +576,24 @@ nouveau_clock_create_(struct nouveau_object *parent,
clk->allow_reclock = allow_reclock;
- ret = nvkm_notify_init(NULL, &device->event, nouveau_clock_pwrsrc, true,
+ ret = nvkm_notify_init(NULL, &device->event, nouveau_clk_pwrsrc, true,
NULL, 0, 0, &clk->pwrsrc_ntfy);
if (ret)
return ret;
mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen);
if (mode) {
- clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen);
- clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen);
+ clk->ustate_ac = nouveau_clk_nstate(clk, mode, arglen);
+ clk->ustate_dc = nouveau_clk_nstate(clk, mode, arglen);
}
mode = nouveau_stropt(device->cfgopt, "NvClkModeAC", &arglen);
if (mode)
- clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen);
+ clk->ustate_ac = nouveau_clk_nstate(clk, mode, arglen);
mode = nouveau_stropt(device->cfgopt, "NvClkModeDC", &arglen);
if (mode)
- clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen);
+ clk->ustate_dc = nouveau_clk_nstate(clk, mode, arglen);
return 0;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
similarity index 89%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
index fb4fad374bdd..4529ba20af5e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
@@ -87,7 +87,7 @@
#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \
(0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT)
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/timer.h>
#ifdef __KERNEL__
@@ -116,16 +116,16 @@ static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
.min_pl = 1, .max_pl = 32,
};
-struct gk20a_clock_priv {
- struct nouveau_clock base;
+struct gk20a_clk_priv {
+ struct nouveau_clk base;
const struct gk20a_clk_pllg_params *params;
u32 m, n, pl;
u32 parent_rate;
};
-#define to_gk20a_clock(base) container_of(base, struct gk20a_clock_priv, base)
+#define to_gk20a_clk(base) container_of(base, struct gk20a_clk_priv, base)
static void
-gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv)
+gk20a_pllg_read_mnp(struct gk20a_clk_priv *priv)
{
u32 val;
@@ -136,7 +136,7 @@ gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv)
}
static u32
-gk20a_pllg_calc_rate(struct gk20a_clock_priv *priv)
+gk20a_pllg_calc_rate(struct gk20a_clk_priv *priv)
{
u32 rate;
u32 divider;
@@ -149,7 +149,7 @@ gk20a_pllg_calc_rate(struct gk20a_clock_priv *priv)
}
static int
-gk20a_pllg_calc_mnp(struct gk20a_clock_priv *priv, unsigned long rate)
+gk20a_pllg_calc_mnp(struct gk20a_clk_priv *priv, unsigned long rate)
{
u32 target_clk_f, ref_clk_f, target_freq;
u32 min_vco_f, max_vco_f;
@@ -265,7 +265,7 @@ found_match:
}
static int
-gk20a_pllg_slide(struct gk20a_clock_priv *priv, u32 n)
+gk20a_pllg_slide(struct gk20a_clk_priv *priv, u32 n)
{
u32 val;
int ramp_timeout;
@@ -322,21 +322,21 @@ gk20a_pllg_slide(struct gk20a_clock_priv *priv, u32 n)
}
static void
-_gk20a_pllg_enable(struct gk20a_clock_priv *priv)
+_gk20a_pllg_enable(struct gk20a_clk_priv *priv)
{
nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
nv_rd32(priv, GPCPLL_CFG);
}
static void
-_gk20a_pllg_disable(struct gk20a_clock_priv *priv)
+_gk20a_pllg_disable(struct gk20a_clk_priv *priv)
{
nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
nv_rd32(priv, GPCPLL_CFG);
}
static int
-_gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide)
+_gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv, bool allow_slide)
{
u32 val, cfg;
u32 m_old, pl_old, n_lo;
@@ -422,7 +422,7 @@ _gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide)
}
static int
-gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv)
+gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv)
{
int err;
@@ -434,7 +434,7 @@ gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv)
}
static void
-gk20a_pllg_disable(struct gk20a_clock_priv *priv)
+gk20a_pllg_disable(struct gk20a_clk_priv *priv)
{
u32 val;
@@ -458,7 +458,7 @@ gk20a_pllg_disable(struct gk20a_clock_priv *priv)
#define GK20A_CLK_GPC_MDIV 1000
-static struct nouveau_clocks
+static struct nouveau_domain
gk20a_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
@@ -560,9 +560,9 @@ gk20a_pstates[] = {
};
static int
-gk20a_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+gk20a_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
- struct gk20a_clock_priv *priv = (void *)clk;
+ struct gk20a_clk_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
@@ -577,34 +577,34 @@ gk20a_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
}
static int
-gk20a_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+gk20a_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct gk20a_clock_priv *priv = (void *)clk;
+ struct gk20a_clk_priv *priv = (void *)clk;
return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] *
GK20A_CLK_GPC_MDIV);
}
static int
-gk20a_clock_prog(struct nouveau_clock *clk)
+gk20a_clk_prog(struct nouveau_clk *clk)
{
- struct gk20a_clock_priv *priv = (void *)clk;
+ struct gk20a_clk_priv *priv = (void *)clk;
return gk20a_pllg_program_mnp(priv);
}
static void
-gk20a_clock_tidy(struct nouveau_clock *clk)
+gk20a_clk_tidy(struct nouveau_clk *clk)
{
}
static int
-gk20a_clock_fini(struct nouveau_object *object, bool suspend)
+gk20a_clk_fini(struct nouveau_object *object, bool suspend)
{
- struct gk20a_clock_priv *priv = (void *)object;
+ struct gk20a_clk_priv *priv = (void *)object;
int ret;
- ret = nouveau_clock_fini(&priv->base, false);
+ ret = nouveau_clk_fini(&priv->base, false);
gk20a_pllg_disable(priv);
@@ -612,18 +612,18 @@ gk20a_clock_fini(struct nouveau_object *object, bool suspend)
}
static int
-gk20a_clock_init(struct nouveau_object *object)
+gk20a_clk_init(struct nouveau_object *object)
{
- struct gk20a_clock_priv *priv = (void *)object;
+ struct gk20a_clk_priv *priv = (void *)object;
int ret;
nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL);
- ret = nouveau_clock_init(&priv->base);
+ ret = nouveau_clk_init(&priv->base);
if (ret)
return ret;
- ret = gk20a_clock_prog(&priv->base);
+ ret = gk20a_clk_prog(&priv->base);
if (ret) {
nv_error(priv, "cannot initialize clock\n");
return ret;
@@ -633,11 +633,11 @@ gk20a_clock_init(struct nouveau_object *object)
}
static int
-gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+gk20a_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct gk20a_clock_priv *priv;
+ struct gk20a_clk_priv *priv;
struct nouveau_platform_device *plat;
int ret;
int i;
@@ -648,7 +648,7 @@ gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
gk20a_pstates[i].pstate = i + 1;
}
- ret = nouveau_clock_create(parent, engine, oclass, gk20a_domains,
+ ret = nouveau_clk_create(parent, engine, oclass, gk20a_domains,
gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv);
*pobject = nv_object(priv);
if (ret)
@@ -660,21 +660,21 @@ gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->parent_rate = clk_get_rate(plat->gpu->clk);
nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ);
- priv->base.read = gk20a_clock_read;
- priv->base.calc = gk20a_clock_calc;
- priv->base.prog = gk20a_clock_prog;
- priv->base.tidy = gk20a_clock_tidy;
+ priv->base.read = gk20a_clk_read;
+ priv->base.calc = gk20a_clk_calc;
+ priv->base.prog = gk20a_clk_prog;
+ priv->base.tidy = gk20a_clk_tidy;
return 0;
}
struct nouveau_oclass
-gk20a_clock_oclass = {
- .handle = NV_SUBDEV(CLOCK, 0xea),
+gk20a_clk_oclass = {
+ .handle = NV_SUBDEV(CLK, 0xea),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = gk20a_clock_ctor,
+ .ctor = gk20a_clk_ctor,
.dtor = _nouveau_subdev_dtor,
- .init = gk20a_clock_init,
- .fini = gk20a_clock_fini,
+ .init = gk20a_clk_init,
+ .fini = gk20a_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
similarity index 76%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
index 4c48232686be..de68f2f53204 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
@@ -24,17 +24,17 @@
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/devinit/nv04.h>
#include "pll.h"
-struct nv04_clock_priv {
- struct nouveau_clock base;
+struct nv04_clk_priv {
+ struct nouveau_clk base;
};
int
-nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
+nv04_clk_pll_calc(struct nouveau_clk *clock, struct nvbios_pll *info,
int clk, struct nouveau_pll_vals *pv)
{
int N1, M1, N2, M2, P;
@@ -51,7 +51,7 @@ nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
}
int
-nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
+nv04_clk_pll_prog(struct nouveau_clk *clk, u32 reg1,
struct nouveau_pll_vals *pv)
{
struct nouveau_devinit *devinit = nouveau_devinit(clk);
@@ -69,37 +69,37 @@ nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
return 0;
}
-static struct nouveau_clocks
+static struct nouveau_domain
nv04_domain[] = {
{ nv_clk_src_max }
};
static int
-nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv04_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv04_clock_priv *priv;
+ struct nv04_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, NULL, 0,
+ ret = nouveau_clk_create(parent, engine, oclass, nv04_domain, NULL, 0,
false, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.pll_calc = nv04_clock_pll_calc;
- priv->base.pll_prog = nv04_clock_pll_prog;
+ priv->base.pll_calc = nv04_clk_pll_calc;
+ priv->base.pll_prog = nv04_clk_pll_prog;
return 0;
}
struct nouveau_oclass
-nv04_clock_oclass = {
- .handle = NV_SUBDEV(CLOCK, 0x04),
+nv04_clk_oclass = {
+ .handle = NV_SUBDEV(CLK, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv04_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nv04_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
similarity index 77%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
index 08368fe97029..460ca4ab603b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
@@ -22,21 +22,21 @@
* Authors: Ben Skeggs
*/
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "pll.h"
-struct nv40_clock_priv {
- struct nouveau_clock base;
+struct nv40_clk_priv {
+ struct nouveau_clk base;
u32 ctrl;
u32 npll_ctrl;
u32 npll_coef;
u32 spll;
};
-static struct nouveau_clocks
+static struct nouveau_domain
nv40_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -47,7 +47,7 @@ nv40_domain[] = {
};
static u32
-read_pll_1(struct nv40_clock_priv *priv, u32 reg)
+read_pll_1(struct nv40_clk_priv *priv, u32 reg)
{
u32 ctrl = nv_rd32(priv, reg + 0x00);
int P = (ctrl & 0x00070000) >> 16;
@@ -62,7 +62,7 @@ read_pll_1(struct nv40_clock_priv *priv, u32 reg)
}
static u32
-read_pll_2(struct nv40_clock_priv *priv, u32 reg)
+read_pll_2(struct nv40_clk_priv *priv, u32 reg)
{
u32 ctrl = nv_rd32(priv, reg + 0x00);
u32 coef = nv_rd32(priv, reg + 0x04);
@@ -87,7 +87,7 @@ read_pll_2(struct nv40_clock_priv *priv, u32 reg)
}
static u32
-read_clk(struct nv40_clock_priv *priv, u32 src)
+read_clk(struct nv40_clk_priv *priv, u32 src)
{
switch (src) {
case 3:
@@ -102,9 +102,9 @@ read_clk(struct nv40_clock_priv *priv, u32 src)
}
static int
-nv40_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+nv40_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
- struct nv40_clock_priv *priv = (void *)clk;
+ struct nv40_clk_priv *priv = (void *)clk;
u32 mast = nv_rd32(priv, 0x00c040);
switch (src) {
@@ -127,7 +127,7 @@ nv40_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
}
static int
-nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk,
+nv40_clk_calc_pll(struct nv40_clk_priv *priv, u32 reg, u32 clk,
int *N1, int *M1, int *N2, int *M2, int *log2P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
@@ -148,16 +148,16 @@ nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk,
}
static int
-nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+nv40_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct nv40_clock_priv *priv = (void *)clk;
+ struct nv40_clk_priv *priv = (void *)clk;
int gclk = cstate->domain[nv_clk_src_core];
int sclk = cstate->domain[nv_clk_src_shader];
int N1, M1, N2, M2, log2P;
int ret;
/* core/geometric clock */
- ret = nv40_clock_calc_pll(priv, 0x004000, gclk,
+ ret = nv40_clk_calc_pll(priv, 0x004000, gclk,
&N1, &M1, &N2, &M2, &log2P);
if (ret < 0)
return ret;
@@ -172,7 +172,7 @@ nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
/* use the second pll for shader/rop clock, if it differs from core */
if (sclk && sclk != gclk) {
- ret = nv40_clock_calc_pll(priv, 0x004008, sclk,
+ ret = nv40_clk_calc_pll(priv, 0x004008, sclk,
&N1, &M1, NULL, NULL, &log2P);
if (ret < 0)
return ret;
@@ -188,9 +188,9 @@ nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
}
static int
-nv40_clock_prog(struct nouveau_clock *clk)
+nv40_clk_prog(struct nouveau_clk *clk)
{
- struct nv40_clock_priv *priv = (void *)clk;
+ struct nv40_clk_priv *priv = (void *)clk;
nv_mask(priv, 0x00c040, 0x00000333, 0x00000000);
nv_wr32(priv, 0x004004, priv->npll_coef);
nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl);
@@ -201,40 +201,40 @@ nv40_clock_prog(struct nouveau_clock *clk)
}
static void
-nv40_clock_tidy(struct nouveau_clock *clk)
+nv40_clk_tidy(struct nouveau_clk *clk)
{
}
static int
-nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv40_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv40_clock_priv *priv;
+ struct nv40_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, nv40_domain, NULL, 0,
+ ret = nouveau_clk_create(parent, engine, oclass, nv40_domain, NULL, 0,
true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.pll_calc = nv04_clock_pll_calc;
- priv->base.pll_prog = nv04_clock_pll_prog;
- priv->base.read = nv40_clock_read;
- priv->base.calc = nv40_clock_calc;
- priv->base.prog = nv40_clock_prog;
- priv->base.tidy = nv40_clock_tidy;
+ priv->base.pll_calc = nv04_clk_pll_calc;
+ priv->base.pll_prog = nv04_clk_pll_prog;
+ priv->base.read = nv40_clk_read;
+ priv->base.calc = nv40_clk_calc;
+ priv->base.prog = nv40_clk_prog;
+ priv->base.tidy = nv40_clk_tidy;
return 0;
}
struct nouveau_oclass
-nv40_clock_oclass = {
- .handle = NV_SUBDEV(CLOCK, 0x40),
+nv40_clk_oclass = {
+ .handle = NV_SUBDEV(CLK, 0x40),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv40_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nv40_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
similarity index 90%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
index 5070ebc260f8..3c462a24922c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
@@ -30,7 +30,7 @@
#include "seq.h"
static u32
-read_div(struct nv50_clock_priv *priv)
+read_div(struct nv50_clk_priv *priv)
{
switch (nv_device(priv)->chipset) {
case 0x50: /* it exists, but only has bit 31, not the dividers.. */
@@ -49,9 +49,9 @@ read_div(struct nv50_clock_priv *priv)
}
static u32
-read_pll_src(struct nv50_clock_priv *priv, u32 base)
+read_pll_src(struct nv50_clk_priv *priv, u32 base)
{
- struct nouveau_clock *clk = &priv->base;
+ struct nouveau_clk *clk = &priv->base;
u32 coef, ref = clk->read(clk, nv_clk_src_crystal);
u32 rsel = nv_rd32(priv, 0x00e18c);
int P, N, M, id;
@@ -120,9 +120,9 @@ read_pll_src(struct nv50_clock_priv *priv, u32 base)
}
static u32
-read_pll_ref(struct nv50_clock_priv *priv, u32 base)
+read_pll_ref(struct nv50_clk_priv *priv, u32 base)
{
- struct nouveau_clock *clk = &priv->base;
+ struct nouveau_clk *clk = &priv->base;
u32 src, mast = nv_rd32(priv, 0x00c040);
switch (base) {
@@ -151,9 +151,9 @@ read_pll_ref(struct nv50_clock_priv *priv, u32 base)
}
static u32
-read_pll(struct nv50_clock_priv *priv, u32 base)
+read_pll(struct nv50_clk_priv *priv, u32 base)
{
- struct nouveau_clock *clk = &priv->base;
+ struct nouveau_clk *clk = &priv->base;
u32 mast = nv_rd32(priv, 0x00c040);
u32 ctrl = nv_rd32(priv, base + 0);
u32 coef = nv_rd32(priv, base + 4);
@@ -185,9 +185,9 @@ read_pll(struct nv50_clock_priv *priv, u32 base)
}
static int
-nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+nv50_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
- struct nv50_clock_priv *priv = (void *)clk;
+ struct nv50_clk_priv *priv = (void *)clk;
u32 mast = nv_rd32(priv, 0x00c040);
u32 P = 0;
@@ -316,7 +316,7 @@ nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
}
static u32
-calc_pll(struct nv50_clock_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P)
+calc_pll(struct nv50_clk_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll pll;
@@ -359,10 +359,10 @@ clk_same(u32 a, u32 b)
}
static int
-nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+nv50_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct nv50_clock_priv *priv = (void *)clk;
- struct nv50_clock_hwsq *hwsq = &priv->hwsq;
+ struct nv50_clk_priv *priv = (void *)clk;
+ struct nv50_clk_hwsq *hwsq = &priv->hwsq;
const int shader = cstate->domain[nv_clk_src_shader];
const int core = cstate->domain[nv_clk_src_core];
const int vdec = cstate->domain[nv_clk_src_vdec];
@@ -484,29 +484,29 @@ nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
}
static int
-nv50_clock_prog(struct nouveau_clock *clk)
+nv50_clk_prog(struct nouveau_clk *clk)
{
- struct nv50_clock_priv *priv = (void *)clk;
+ struct nv50_clk_priv *priv = (void *)clk;
return clk_exec(&priv->hwsq, true);
}
static void
-nv50_clock_tidy(struct nouveau_clock *clk)
+nv50_clk_tidy(struct nouveau_clk *clk)
{
- struct nv50_clock_priv *priv = (void *)clk;
+ struct nv50_clk_priv *priv = (void *)clk;
clk_exec(&priv->hwsq, false);
}
int
-nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv50_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv50_clock_oclass *pclass = (void *)oclass;
- struct nv50_clock_priv *priv;
+ struct nv50_clk_oclass *pclass = (void *)oclass;
+ struct nv50_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, pclass->domains,
+ ret = nouveau_clk_create(parent, engine, oclass, pclass->domains,
NULL, 0, false, &priv);
*pobject = nv_object(priv);
if (ret)
@@ -529,14 +529,14 @@ nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
priv->hwsq.r_mast = hwsq_reg(0x00c040);
- priv->base.read = nv50_clock_read;
- priv->base.calc = nv50_clock_calc;
- priv->base.prog = nv50_clock_prog;
- priv->base.tidy = nv50_clock_tidy;
+ priv->base.read = nv50_clk_read;
+ priv->base.calc = nv50_clk_calc;
+ priv->base.prog = nv50_clk_prog;
+ priv->base.tidy = nv50_clk_tidy;
return 0;
}
-static struct nouveau_clocks
+static struct nouveau_domain
nv50_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -547,13 +547,13 @@ nv50_domains[] = {
};
struct nouveau_oclass *
-nv50_clock_oclass = &(struct nv50_clock_oclass) {
- .base.handle = NV_SUBDEV(CLOCK, 0x50),
+nv50_clk_oclass = &(struct nv50_clk_oclass) {
+ .base.handle = NV_SUBDEV(CLK, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv50_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nv50_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
.domains = nv50_domains,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
similarity index 59%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
index f10917d789e8..ae6421fd28f4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
@@ -3,9 +3,9 @@
#include <subdev/bus.h>
#include <subdev/bus/hwsq.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
-struct nv50_clock_hwsq {
+struct nv50_clk_hwsq {
struct hwsq base;
struct hwsq_reg r_fifo;
struct hwsq_reg r_spll[2];
@@ -14,18 +14,18 @@ struct nv50_clock_hwsq {
struct hwsq_reg r_mast;
};
-struct nv50_clock_priv {
- struct nouveau_clock base;
- struct nv50_clock_hwsq hwsq;
+struct nv50_clk_priv {
+ struct nouveau_clk base;
+ struct nv50_clk_hwsq hwsq;
};
-int nv50_clock_ctor(struct nouveau_object *, struct nouveau_object *,
+int nv50_clk_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
-struct nv50_clock_oclass {
+struct nv50_clk_oclass {
struct nouveau_oclass base;
- struct nouveau_clocks *domains;
+ struct nouveau_domain *domains;
};
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c
similarity index 86%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c
index b0b7c1437f10..b5b00b3df6c4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c
@@ -24,7 +24,7 @@
#include "nv50.h"
-static struct nouveau_clocks
+static struct nouveau_domain
nv84_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -36,13 +36,13 @@ nv84_domains[] = {
};
struct nouveau_oclass *
-nv84_clock_oclass = &(struct nv50_clock_oclass) {
- .base.handle = NV_SUBDEV(CLOCK, 0x84),
+nv84_clk_oclass = &(struct nv50_clk_oclass) {
+ .base.handle = NV_SUBDEV(CLK, 0x84),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv50_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nv50_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
.domains = nv84_domains,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c
similarity index 80%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c
index 07ad01247675..3002c60a3993 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c
@@ -32,16 +32,16 @@
#include "nva3.h"
-struct nva3_clock_priv {
- struct nouveau_clock base;
- struct nva3_clock_info eng[nv_clk_src_max];
+struct nva3_clk_priv {
+ struct nouveau_clk base;
+ struct nva3_clk_info eng[nv_clk_src_max];
};
-static u32 read_clk(struct nva3_clock_priv *, int, bool);
-static u32 read_pll(struct nva3_clock_priv *, int, u32);
+static u32 read_clk(struct nva3_clk_priv *, int, bool);
+static u32 read_pll(struct nva3_clk_priv *, int, u32);
static u32
-read_vco(struct nva3_clock_priv *priv, int clk)
+read_vco(struct nva3_clk_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
@@ -58,7 +58,7 @@ read_vco(struct nva3_clock_priv *priv, int clk)
}
static u32
-read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
+read_clk(struct nva3_clk_priv *priv, int clk, bool ignore_en)
{
u32 sctl, sdiv, sclk;
@@ -104,7 +104,7 @@ read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
}
static u32
-read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
+read_pll(struct nva3_clk_priv *priv, int clk, u32 pll)
{
u32 ctrl = nv_rd32(priv, pll + 0);
u32 sclk = 0, P = 1, N = 1, M = 1;
@@ -134,9 +134,9 @@ read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
}
static int
-nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+nva3_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
- struct nva3_clock_priv *priv = (void *)clk;
+ struct nva3_clk_priv *priv = (void *)clk;
u32 hsrc;
switch (src) {
@@ -176,10 +176,10 @@ nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
}
int
-nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz,
- struct nva3_clock_info *info)
+nva3_clk_info(struct nouveau_clk *clock, int clk, u32 khz,
+ struct nva3_clk_info *info)
{
- struct nva3_clock_priv *priv = (void *)clock;
+ struct nva3_clk_priv *priv = (void *)clock;
u32 oclk, sclk, sdiv, diff;
info->clk = 0;
@@ -223,11 +223,11 @@ nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz,
}
int
-nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
- struct nva3_clock_info *info)
+nva3_pll_info(struct nouveau_clk *clock, int clk, u32 pll, u32 khz,
+ struct nva3_clk_info *info)
{
struct nouveau_bios *bios = nouveau_bios(clock);
- struct nva3_clock_priv *priv = (void *)clock;
+ struct nva3_clk_priv *priv = (void *)clock;
struct nvbios_pll limits;
int P, N, M, diff;
int ret;
@@ -263,7 +263,7 @@ out:
}
static int
-calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
+calc_clk(struct nva3_clk_priv *priv, struct nouveau_cstate *cstate,
int clk, u32 pll, int idx)
{
int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx],
@@ -274,11 +274,11 @@ calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
}
static int
-calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate)
+calc_host(struct nva3_clk_priv *priv, struct nouveau_cstate *cstate)
{
int ret = 0;
u32 kHz = cstate->domain[nv_clk_src_host];
- struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
+ struct nva3_clk_info *info = &priv->eng[nv_clk_src_host];
if (kHz == 277000) {
info->clk = 0;
@@ -295,7 +295,7 @@ calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate)
}
int
-nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags)
+nva3_clk_pre(struct nouveau_clk *clk, unsigned long *flags)
{
struct nouveau_fifo *pfifo = nouveau_fifo(clk);
@@ -318,7 +318,7 @@ nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags)
}
void
-nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags)
+nva3_clk_post(struct nouveau_clk *clk, unsigned long *flags)
{
struct nouveau_fifo *pfifo = nouveau_fifo(clk);
@@ -330,16 +330,16 @@ nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags)
}
static void
-disable_clk_src(struct nva3_clock_priv *priv, u32 src)
+disable_clk_src(struct nva3_clk_priv *priv, u32 src)
{
nv_mask(priv, src, 0x00000100, 0x00000000);
nv_mask(priv, src, 0x00000001, 0x00000000);
}
static void
-prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
+prog_pll(struct nva3_clk_priv *priv, int clk, u32 pll, int idx)
{
- struct nva3_clock_info *info = &priv->eng[idx];
+ struct nva3_clk_info *info = &priv->eng[idx];
const u32 src0 = 0x004120 + (clk * 4);
const u32 src1 = 0x004160 + (clk * 4);
const u32 ctrl = pll + 0;
@@ -377,16 +377,16 @@ prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
}
static void
-prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
+prog_clk(struct nva3_clk_priv *priv, int clk, int idx)
{
- struct nva3_clock_info *info = &priv->eng[idx];
+ struct nva3_clk_info *info = &priv->eng[idx];
nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
}
static void
-prog_host(struct nva3_clock_priv *priv)
+prog_host(struct nva3_clk_priv *priv)
{
- struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
+ struct nva3_clk_info *info = &priv->eng[nv_clk_src_host];
u32 hsrc = (nv_rd32(priv, 0xc040));
switch (info->host_out) {
@@ -411,9 +411,9 @@ prog_host(struct nva3_clock_priv *priv)
}
static void
-prog_core(struct nva3_clock_priv *priv, int idx)
+prog_core(struct nva3_clk_priv *priv, int idx)
{
- struct nva3_clock_info *info = &priv->eng[idx];
+ struct nva3_clk_info *info = &priv->eng[idx];
u32 fb_delay = nv_rd32(priv, 0x10002c);
if (fb_delay < info->fb_delay)
@@ -426,10 +426,10 @@ prog_core(struct nva3_clock_priv *priv, int idx)
}
static int
-nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+nva3_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct nva3_clock_priv *priv = (void *)clk;
- struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
+ struct nva3_clk_priv *priv = (void *)clk;
+ struct nva3_clk_info *core = &priv->eng[nv_clk_src_core];
int ret;
if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
@@ -453,15 +453,15 @@ nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
}
static int
-nva3_clock_prog(struct nouveau_clock *clk)
+nva3_clk_prog(struct nouveau_clk *clk)
{
- struct nva3_clock_priv *priv = (void *)clk;
- struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
+ struct nva3_clk_priv *priv = (void *)clk;
+ struct nva3_clk_info *core = &priv->eng[nv_clk_src_core];
int ret = 0;
unsigned long flags;
unsigned long *f = &flags;
- ret = nva3_clock_pre(clk, f);
+ ret = nva3_clk_pre(clk, f);
if (ret)
goto out;
@@ -478,17 +478,17 @@ out:
if (ret == -EBUSY)
f = NULL;
- nva3_clock_post(clk, f);
+ nva3_clk_post(clk, f);
return ret;
}
static void
-nva3_clock_tidy(struct nouveau_clock *clk)
+nva3_clk_tidy(struct nouveau_clk *clk)
{
}
-static struct nouveau_clocks
+static struct nouveau_domain
nva3_domain[] = {
{ nv_clk_src_crystal , 0xff },
{ nv_clk_src_core , 0x00, 0, "core", 1000 },
@@ -502,33 +502,33 @@ nva3_domain[] = {
};
static int
-nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nva3_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nva3_clock_priv *priv;
+ struct nva3_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0,
+ ret = nouveau_clk_create(parent, engine, oclass, nva3_domain, NULL, 0,
true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.read = nva3_clock_read;
- priv->base.calc = nva3_clock_calc;
- priv->base.prog = nva3_clock_prog;
- priv->base.tidy = nva3_clock_tidy;
+ priv->base.read = nva3_clk_read;
+ priv->base.calc = nva3_clk_calc;
+ priv->base.prog = nva3_clk_prog;
+ priv->base.tidy = nva3_clk_tidy;
return 0;
}
struct nouveau_oclass
-nva3_clock_oclass = {
- .handle = NV_SUBDEV(CLOCK, 0xa3),
+nva3_clk_oclass = {
+ .handle = NV_SUBDEV(CLK, 0xa3),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nva3_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nva3_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h
new file mode 100644
index 000000000000..ce0fc83345e3
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h
@@ -0,0 +1,20 @@
+#ifndef __NVKM_CLK_NVA3_H__
+#define __NVKM_CLK_NVA3_H__
+
+#include <subdev/clk.h>
+
+struct nva3_clk_info {
+ u32 clk;
+ u32 pll;
+ enum {
+ NVA3_HOST_277,
+ NVA3_HOST_CLK,
+ } host_out;
+ u32 fb_delay;
+};
+
+int nva3_pll_info(struct nouveau_clk *, int, u32, u32,
+ struct nva3_clk_info *);
+int nva3_clk_pre(struct nouveau_clk *clk, unsigned long *flags);
+void nva3_clk_post(struct nouveau_clk *clk, unsigned long *flags);
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c
similarity index 88%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c
index 54aeab8005a0..d6d2bd190144 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c
@@ -26,13 +26,13 @@
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include "nva3.h"
#include "pll.h"
-struct nvaa_clock_priv {
- struct nouveau_clock base;
+struct nvaa_clk_priv {
+ struct nouveau_clk base;
enum nv_clk_src csrc, ssrc, vsrc;
u32 cctrl, sctrl;
u32 ccoef, scoef;
@@ -41,13 +41,13 @@ struct nvaa_clock_priv {
};
static u32
-read_div(struct nouveau_clock *clk)
+read_div(struct nouveau_clk *clk)
{
return nv_rd32(clk, 0x004600);
}
static u32
-read_pll(struct nouveau_clock *clk, u32 base)
+read_pll(struct nouveau_clk *clk, u32 base)
{
u32 ctrl = nv_rd32(clk, base + 0);
u32 coef = nv_rd32(clk, base + 4);
@@ -78,9 +78,9 @@ read_pll(struct nouveau_clock *clk, u32 base)
}
static int
-nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+nvaa_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
- struct nvaa_clock_priv *priv = (void *)clk;
+ struct nvaa_clk_priv *priv = (void *)clk;
u32 mast = nv_rd32(clk, 0x00c054);
u32 P = 0;
@@ -160,12 +160,12 @@ nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
}
static u32
-calc_pll(struct nvaa_clock_priv *priv, u32 reg,
+calc_pll(struct nvaa_clk_priv *priv, u32 reg,
u32 clock, int *N, int *M, int *P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll pll;
- struct nouveau_clock *clk = &priv->base;
+ struct nouveau_clk *clk = &priv->base;
int ret;
ret = nvbios_pll_parse(bios, reg, &pll);
@@ -199,9 +199,9 @@ calc_P(u32 src, u32 target, int *div)
}
static int
-nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct nvaa_clock_priv *priv = (void *)clk;
+ struct nvaa_clk_priv *priv = (void *)clk;
const int shader = cstate->domain[nv_clk_src_shader];
const int core = cstate->domain[nv_clk_src_core];
const int vdec = cstate->domain[nv_clk_src_vdec];
@@ -297,15 +297,15 @@ nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
}
static int
-nvaa_clock_prog(struct nouveau_clock *clk)
+nvaa_clk_prog(struct nouveau_clk *clk)
{
- struct nvaa_clock_priv *priv = (void *)clk;
+ struct nvaa_clk_priv *priv = (void *)clk;
u32 pllmask = 0, mast;
unsigned long flags;
unsigned long *f = &flags;
int ret = 0;
- ret = nva3_clock_pre(clk, f);
+ ret = nva3_clk_pre(clk, f);
if (ret)
goto out;
@@ -382,17 +382,17 @@ out:
if (ret == -EBUSY)
f = NULL;
- nva3_clock_post(clk, f);
+ nva3_clk_post(clk, f);
return ret;
}
static void
-nvaa_clock_tidy(struct nouveau_clock *clk)
+nvaa_clk_tidy(struct nouveau_clk *clk)
{
}
-static struct nouveau_clocks
+static struct nouveau_domain
nvaa_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -403,33 +403,33 @@ nvaa_domains[] = {
};
static int
-nvaa_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvaa_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvaa_clock_priv *priv;
+ struct nvaa_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, NULL,
+ ret = nouveau_clk_create(parent, engine, oclass, nvaa_domains, NULL,
0, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.read = nvaa_clock_read;
- priv->base.calc = nvaa_clock_calc;
- priv->base.prog = nvaa_clock_prog;
- priv->base.tidy = nvaa_clock_tidy;
+ priv->base.read = nvaa_clk_read;
+ priv->base.calc = nvaa_clk_calc;
+ priv->base.prog = nvaa_clk_prog;
+ priv->base.tidy = nvaa_clk_tidy;
return 0;
}
struct nouveau_oclass *
-nvaa_clock_oclass = &(struct nouveau_oclass) {
- .handle = NV_SUBDEV(CLOCK, 0xaa),
+nvaa_clk_oclass = &(struct nouveau_oclass) {
+ .handle = NV_SUBDEV(CLK, 0xaa),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvaa_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nvaa_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c
similarity index 78%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c
index 1234abaab2db..791a9f5198eb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c
@@ -22,14 +22,14 @@
* Authors: Ben Skeggs
*/
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
#include "pll.h"
-struct nvc0_clock_info {
+struct nvc0_clk_info {
u32 freq;
u32 ssel;
u32 mdiv;
@@ -38,17 +38,17 @@ struct nvc0_clock_info {
u32 coef;
};
-struct nvc0_clock_priv {
- struct nouveau_clock base;
- struct nvc0_clock_info eng[16];
+struct nvc0_clk_priv {
+ struct nouveau_clk base;
+ struct nvc0_clk_info eng[16];
};
-static u32 read_div(struct nvc0_clock_priv *, int, u32, u32);
+static u32 read_div(struct nvc0_clk_priv *, int, u32, u32);
static u32
-read_vco(struct nvc0_clock_priv *priv, u32 dsrc)
+read_vco(struct nvc0_clk_priv *priv, u32 dsrc)
{
- struct nouveau_clock *clk = &priv->base;
+ struct nouveau_clk *clk = &priv->base;
u32 ssrc = nv_rd32(priv, dsrc);
if (!(ssrc & 0x00000100))
return clk->read(clk, nv_clk_src_sppll0);
@@ -56,9 +56,9 @@ read_vco(struct nvc0_clock_priv *priv, u32 dsrc)
}
static u32
-read_pll(struct nvc0_clock_priv *priv, u32 pll)
+read_pll(struct nvc0_clk_priv *priv, u32 pll)
{
- struct nouveau_clock *clk = &priv->base;
+ struct nouveau_clk *clk = &priv->base;
u32 ctrl = nv_rd32(priv, pll + 0x00);
u32 coef = nv_rd32(priv, pll + 0x04);
u32 P = (coef & 0x003f0000) >> 16;
@@ -95,7 +95,7 @@ read_pll(struct nvc0_clock_priv *priv, u32 pll)
}
static u32
-read_div(struct nvc0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
+read_div(struct nvc0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
{
u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
u32 sctl = nv_rd32(priv, dctl + (doff * 4));
@@ -121,7 +121,7 @@ read_div(struct nvc0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
}
static u32
-read_clk(struct nvc0_clock_priv *priv, int clk)
+read_clk(struct nvc0_clk_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
u32 ssel = nv_rd32(priv, 0x137100);
@@ -145,10 +145,10 @@ read_clk(struct nvc0_clock_priv *priv, int clk)
}
static int
-nvc0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+nvc0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
struct nouveau_device *device = nv_device(clk);
- struct nvc0_clock_priv *priv = (void *)clk;
+ struct nvc0_clk_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
@@ -196,7 +196,7 @@ nvc0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
}
static u32
-calc_div(struct nvc0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
+calc_div(struct nvc0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
{
u32 div = min((ref * 2) / freq, (u32)65);
if (div < 2)
@@ -207,7 +207,7 @@ calc_div(struct nvc0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
}
static u32
-calc_src(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
+calc_src(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
{
u32 sclk;
@@ -236,7 +236,7 @@ calc_src(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
}
static u32
-calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef)
+calc_pll(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *coef)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll limits;
@@ -259,10 +259,10 @@ calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef)
}
static int
-calc_clk(struct nvc0_clock_priv *priv,
+calc_clk(struct nvc0_clk_priv *priv,
struct nouveau_cstate *cstate, int clk, int dom)
{
- struct nvc0_clock_info *info = &priv->eng[clk];
+ struct nvc0_clk_info *info = &priv->eng[clk];
u32 freq = cstate->domain[dom];
u32 src0, div0, div1D, div1P = 0;
u32 clk0, clk1 = 0;
@@ -311,9 +311,9 @@ calc_clk(struct nvc0_clock_priv *priv,
}
static int
-nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+nvc0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct nvc0_clock_priv *priv = (void *)clk;
+ struct nvc0_clk_priv *priv = (void *)clk;
int ret;
if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
@@ -330,9 +330,9 @@ nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
}
static void
-nvc0_clock_prog_0(struct nvc0_clock_priv *priv, int clk)
+nvc0_clk_prog_0(struct nvc0_clk_priv *priv, int clk)
{
- struct nvc0_clock_info *info = &priv->eng[clk];
+ struct nvc0_clk_info *info = &priv->eng[clk];
if (clk < 7 && !info->ssel) {
nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
@@ -340,16 +340,16 @@ nvc0_clock_prog_0(struct nvc0_clock_priv *priv, int clk)
}
static void
-nvc0_clock_prog_1(struct nvc0_clock_priv *priv, int clk)
+nvc0_clk_prog_1(struct nvc0_clk_priv *priv, int clk)
{
nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
}
static void
-nvc0_clock_prog_2(struct nvc0_clock_priv *priv, int clk)
+nvc0_clk_prog_2(struct nvc0_clk_priv *priv, int clk)
{
- struct nvc0_clock_info *info = &priv->eng[clk];
+ struct nvc0_clk_info *info = &priv->eng[clk];
const u32 addr = 0x137000 + (clk * 0x20);
if (clk <= 7) {
nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
@@ -364,9 +364,9 @@ nvc0_clock_prog_2(struct nvc0_clock_priv *priv, int clk)
}
static void
-nvc0_clock_prog_3(struct nvc0_clock_priv *priv, int clk)
+nvc0_clk_prog_3(struct nvc0_clk_priv *priv, int clk)
{
- struct nvc0_clock_info *info = &priv->eng[clk];
+ struct nvc0_clk_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137100, (1 << clk), info->ssel);
nv_wait(priv, 0x137100, (1 << clk), info->ssel);
@@ -374,24 +374,24 @@ nvc0_clock_prog_3(struct nvc0_clock_priv *priv, int clk)
}
static void
-nvc0_clock_prog_4(struct nvc0_clock_priv *priv, int clk)
+nvc0_clk_prog_4(struct nvc0_clk_priv *priv, int clk)
{
- struct nvc0_clock_info *info = &priv->eng[clk];
+ struct nvc0_clk_info *info = &priv->eng[clk];
nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
}
static int
-nvc0_clock_prog(struct nouveau_clock *clk)
+nvc0_clk_prog(struct nouveau_clk *clk)
{
- struct nvc0_clock_priv *priv = (void *)clk;
+ struct nvc0_clk_priv *priv = (void *)clk;
struct {
- void (*exec)(struct nvc0_clock_priv *, int);
+ void (*exec)(struct nvc0_clk_priv *, int);
} stage[] = {
- { nvc0_clock_prog_0 }, /* div programming */
- { nvc0_clock_prog_1 }, /* select div mode */
- { nvc0_clock_prog_2 }, /* (maybe) program pll */
- { nvc0_clock_prog_3 }, /* (maybe) select pll mode */
- { nvc0_clock_prog_4 }, /* final divider */
+ { nvc0_clk_prog_0 }, /* div programming */
+ { nvc0_clk_prog_1 }, /* select div mode */
+ { nvc0_clk_prog_2 }, /* (maybe) program pll */
+ { nvc0_clk_prog_3 }, /* (maybe) select pll mode */
+ { nvc0_clk_prog_4 }, /* final divider */
};
int i, j;
@@ -407,13 +407,13 @@ nvc0_clock_prog(struct nouveau_clock *clk)
}
static void
-nvc0_clock_tidy(struct nouveau_clock *clk)
+nvc0_clk_tidy(struct nouveau_clk *clk)
{
- struct nvc0_clock_priv *priv = (void *)clk;
+ struct nvc0_clk_priv *priv = (void *)clk;
memset(priv->eng, 0x00, sizeof(priv->eng));
}
-static struct nouveau_clocks
+static struct nouveau_domain
nvc0_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -430,33 +430,33 @@ nvc0_domain[] = {
};
static int
-nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvc0_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvc0_clock_priv *priv;
+ struct nvc0_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, nvc0_domain, NULL, 0,
+ ret = nouveau_clk_create(parent, engine, oclass, nvc0_domain, NULL, 0,
false, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.read = nvc0_clock_read;
- priv->base.calc = nvc0_clock_calc;
- priv->base.prog = nvc0_clock_prog;
- priv->base.tidy = nvc0_clock_tidy;
+ priv->base.read = nvc0_clk_read;
+ priv->base.calc = nvc0_clk_calc;
+ priv->base.prog = nvc0_clk_prog;
+ priv->base.tidy = nvc0_clk_tidy;
return 0;
}
struct nouveau_oclass
-nvc0_clock_oclass = {
- .handle = NV_SUBDEV(CLOCK, 0xc0),
+nvc0_clk_oclass = {
+ .handle = NV_SUBDEV(CLK, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nvc0_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c
similarity index 77%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c
index 7eccad57512e..ffd2139e0a49 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c
@@ -22,14 +22,14 @@
* Authors: Ben Skeggs
*/
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/timer.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "pll.h"
-struct nve0_clock_info {
+struct nve0_clk_info {
u32 freq;
u32 ssel;
u32 mdiv;
@@ -38,16 +38,16 @@ struct nve0_clock_info {
u32 coef;
};
-struct nve0_clock_priv {
- struct nouveau_clock base;
- struct nve0_clock_info eng[16];
+struct nve0_clk_priv {
+ struct nouveau_clk base;
+ struct nve0_clk_info eng[16];
};
-static u32 read_div(struct nve0_clock_priv *, int, u32, u32);
-static u32 read_pll(struct nve0_clock_priv *, u32);
+static u32 read_div(struct nve0_clk_priv *, int, u32, u32);
+static u32 read_pll(struct nve0_clk_priv *, u32);
static u32
-read_vco(struct nve0_clock_priv *priv, u32 dsrc)
+read_vco(struct nve0_clk_priv *priv, u32 dsrc)
{
u32 ssrc = nv_rd32(priv, dsrc);
if (!(ssrc & 0x00000100))
@@ -56,7 +56,7 @@ read_vco(struct nve0_clock_priv *priv, u32 dsrc)
}
static u32
-read_pll(struct nve0_clock_priv *priv, u32 pll)
+read_pll(struct nve0_clk_priv *priv, u32 pll)
{
u32 ctrl = nv_rd32(priv, pll + 0x00);
u32 coef = nv_rd32(priv, pll + 0x04);
@@ -101,7 +101,7 @@ read_pll(struct nve0_clock_priv *priv, u32 pll)
}
static u32
-read_div(struct nve0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
+read_div(struct nve0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
{
u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
u32 sctl = nv_rd32(priv, dctl + (doff * 4));
@@ -127,7 +127,7 @@ read_div(struct nve0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
}
static u32
-read_mem(struct nve0_clock_priv *priv)
+read_mem(struct nve0_clk_priv *priv)
{
switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) {
case 1: return read_pll(priv, 0x132020);
@@ -138,7 +138,7 @@ read_mem(struct nve0_clock_priv *priv)
}
static u32
-read_clk(struct nve0_clock_priv *priv, int clk)
+read_clk(struct nve0_clk_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
u32 sclk, sdiv;
@@ -181,10 +181,10 @@ read_clk(struct nve0_clock_priv *priv, int clk)
}
static int
-nve0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+nve0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
struct nouveau_device *device = nv_device(clk);
- struct nve0_clock_priv *priv = (void *)clk;
+ struct nve0_clk_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
@@ -214,7 +214,7 @@ nve0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
}
static u32
-calc_div(struct nve0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
+calc_div(struct nve0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
{
u32 div = min((ref * 2) / freq, (u32)65);
if (div < 2)
@@ -225,7 +225,7 @@ calc_div(struct nve0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
}
static u32
-calc_src(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
+calc_src(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
{
u32 sclk;
@@ -254,7 +254,7 @@ calc_src(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
}
static u32
-calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef)
+calc_pll(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *coef)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll limits;
@@ -277,10 +277,10 @@ calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef)
}
static int
-calc_clk(struct nve0_clock_priv *priv,
+calc_clk(struct nve0_clk_priv *priv,
struct nouveau_cstate *cstate, int clk, int dom)
{
- struct nve0_clock_info *info = &priv->eng[clk];
+ struct nve0_clk_info *info = &priv->eng[clk];
u32 freq = cstate->domain[dom];
u32 src0, div0, div1D, div1P = 0;
u32 clk0, clk1 = 0;
@@ -329,9 +329,9 @@ calc_clk(struct nve0_clock_priv *priv,
}
static int
-nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+nve0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct nve0_clock_priv *priv = (void *)clk;
+ struct nve0_clk_priv *priv = (void *)clk;
int ret;
if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
@@ -347,9 +347,9 @@ nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
}
static void
-nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_0(struct nve0_clk_priv *priv, int clk)
{
- struct nve0_clock_info *info = &priv->eng[clk];
+ struct nve0_clk_info *info = &priv->eng[clk];
if (!info->ssel) {
nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv);
nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
@@ -357,22 +357,22 @@ nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk)
}
static void
-nve0_clock_prog_1_0(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_1_0(struct nve0_clk_priv *priv, int clk)
{
nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
}
static void
-nve0_clock_prog_1_1(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_1_1(struct nve0_clk_priv *priv, int clk)
{
nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000);
}
static void
-nve0_clock_prog_2(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_2(struct nve0_clk_priv *priv, int clk)
{
- struct nve0_clock_info *info = &priv->eng[clk];
+ struct nve0_clk_info *info = &priv->eng[clk];
const u32 addr = 0x137000 + (clk * 0x20);
nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
@@ -385,9 +385,9 @@ nve0_clock_prog_2(struct nve0_clock_priv *priv, int clk)
}
static void
-nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_3(struct nve0_clk_priv *priv, int clk)
{
- struct nve0_clock_info *info = &priv->eng[clk];
+ struct nve0_clk_info *info = &priv->eng[clk];
if (info->ssel)
nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv);
else
@@ -395,9 +395,9 @@ nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk)
}
static void
-nve0_clock_prog_4_0(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_4_0(struct nve0_clk_priv *priv, int clk)
{
- struct nve0_clock_info *info = &priv->eng[clk];
+ struct nve0_clk_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137100, (1 << clk), info->ssel);
nv_wait(priv, 0x137100, (1 << clk), info->ssel);
@@ -405,9 +405,9 @@ nve0_clock_prog_4_0(struct nve0_clock_priv *priv, int clk)
}
static void
-nve0_clock_prog_4_1(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_4_1(struct nve0_clk_priv *priv, int clk)
{
- struct nve0_clock_info *info = &priv->eng[clk];
+ struct nve0_clk_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000);
nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100);
@@ -415,20 +415,20 @@ nve0_clock_prog_4_1(struct nve0_clock_priv *priv, int clk)
}
static int
-nve0_clock_prog(struct nouveau_clock *clk)
+nve0_clk_prog(struct nouveau_clk *clk)
{
- struct nve0_clock_priv *priv = (void *)clk;
+ struct nve0_clk_priv *priv = (void *)clk;
struct {
u32 mask;
- void (*exec)(struct nve0_clock_priv *, int);
+ void (*exec)(struct nve0_clk_priv *, int);
} stage[] = {
- { 0x007f, nve0_clock_prog_0 }, /* div programming */
- { 0x007f, nve0_clock_prog_1_0 }, /* select div mode */
- { 0xff80, nve0_clock_prog_1_1 },
- { 0x00ff, nve0_clock_prog_2 }, /* (maybe) program pll */
- { 0xff80, nve0_clock_prog_3 }, /* final divider */
- { 0x007f, nve0_clock_prog_4_0 }, /* (maybe) select pll mode */
- { 0xff80, nve0_clock_prog_4_1 },
+ { 0x007f, nve0_clk_prog_0 }, /* div programming */
+ { 0x007f, nve0_clk_prog_1_0 }, /* select div mode */
+ { 0xff80, nve0_clk_prog_1_1 },
+ { 0x00ff, nve0_clk_prog_2 }, /* (maybe) program pll */
+ { 0xff80, nve0_clk_prog_3 }, /* final divider */
+ { 0x007f, nve0_clk_prog_4_0 }, /* (maybe) select pll mode */
+ { 0xff80, nve0_clk_prog_4_1 },
};
int i, j;
@@ -446,13 +446,13 @@ nve0_clock_prog(struct nouveau_clock *clk)
}
static void
-nve0_clock_tidy(struct nouveau_clock *clk)
+nve0_clk_tidy(struct nouveau_clk *clk)
{
- struct nve0_clock_priv *priv = (void *)clk;
+ struct nve0_clk_priv *priv = (void *)clk;
memset(priv->eng, 0x00, sizeof(priv->eng));
}
-static struct nouveau_clocks
+static struct nouveau_domain
nve0_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -468,33 +468,33 @@ nve0_domain[] = {
};
static int
-nve0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nve0_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nve0_clock_priv *priv;
+ struct nve0_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, nve0_domain, NULL, 0,
+ ret = nouveau_clk_create(parent, engine, oclass, nve0_domain, NULL, 0,
true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.read = nve0_clock_read;
- priv->base.calc = nve0_clock_calc;
- priv->base.prog = nve0_clock_prog;
- priv->base.tidy = nve0_clock_tidy;
+ priv->base.read = nve0_clk_read;
+ priv->base.calc = nve0_clk_calc;
+ priv->base.prog = nve0_clk_prog;
+ priv->base.tidy = nve0_clk_tidy;
return 0;
}
struct nouveau_oclass
-nve0_clock_oclass = {
- .handle = NV_SUBDEV(CLOCK, 0xe0),
+nve0_clk_oclass = {
+ .handle = NV_SUBDEV(CLK, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nve0_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c
similarity index 98%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c
index 8eca457c2814..bc17fcc83bfe 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c
@@ -22,7 +22,7 @@
* Authors: Ben Skeggs
*/
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild
deleted file mode 100644
index f0a86021fbb1..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild
+++ /dev/null
@@ -1,12 +0,0 @@
-nvkm-y += nvkm/subdev/clock/base.o
-nvkm-y += nvkm/subdev/clock/nv04.o
-nvkm-y += nvkm/subdev/clock/nv40.o
-nvkm-y += nvkm/subdev/clock/nv50.o
-nvkm-y += nvkm/subdev/clock/nv84.o
-nvkm-y += nvkm/subdev/clock/nva3.o
-nvkm-y += nvkm/subdev/clock/nvaa.o
-nvkm-y += nvkm/subdev/clock/nvc0.o
-nvkm-y += nvkm/subdev/clock/nve0.o
-nvkm-y += nvkm/subdev/clock/gk20a.o
-nvkm-y += nvkm/subdev/clock/pllnv04.o
-nvkm-y += nvkm/subdev/clock/pllnva3.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h
deleted file mode 100644
index a45a1038b12f..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __NVKM_CLK_NVA3_H__
-#define __NVKM_CLK_NVA3_H__
-
-#include <subdev/clock.h>
-
-struct nva3_clock_info {
- u32 clk;
- u32 pll;
- enum {
- NVA3_HOST_277,
- NVA3_HOST_CLK,
- } host_out;
- u32 fb_delay;
-};
-
-int nva3_pll_info(struct nouveau_clock *, int, u32, u32,
- struct nva3_clock_info *);
-int nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags);
-void nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags);
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
index cbcd51852472..7a768afba813 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
@@ -4,7 +4,7 @@
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/bios/init.h>
-#include <subdev/clock/pll.h>
+#include <subdev/clk/pll.h>
#include <subdev/devinit.h>
struct nouveau_devinit_impl {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
index 7648beb11199..50cbc3804eaf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
@@ -26,8 +26,8 @@
#include <subdev/bios/bit.h>
#include <subdev/bios/pll.h>
#include <subdev/bios/init.h>
-#include <subdev/clock.h>
-#include <subdev/clock/pll.h>
+#include <subdev/clk.h>
+#include <subdev/clk/pll.h>
#include <subdev/timer.h>
#include <engine/fifo.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
index 64a983c96625..8d2970c27715 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
@@ -27,7 +27,7 @@
#include <subdev/bios/pll.h>
#include <subdev/bios/perf.h>
#include <subdev/bios/timing.h>
-#include <subdev/clock/pll.h>
+#include <subdev/clk/pll.h>
#include <subdev/fb.h>
#include <core/option.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
index 3b38a538845d..50e8dee513cc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
@@ -30,8 +30,8 @@
#include <subdev/bios/M0205.h>
#include <subdev/bios/timing.h>
-#include <subdev/clock/nva3.h>
-#include <subdev/clock/pll.h>
+#include <subdev/clk/nva3.h>
+#include <subdev/clk/pll.h>
#include <subdev/gpio.h>
@@ -168,7 +168,7 @@ nva3_link_train(struct nouveau_fb *pfb)
{
struct nouveau_bios *bios = nouveau_bios(pfb);
struct nva3_ram *ram = (void *)pfb->ram;
- struct nouveau_clock *clk = nouveau_clock(pfb);
+ struct nouveau_clk *clk = nouveau_clk(pfb);
struct nva3_ltrain *train = &ram->ltrain;
struct nouveau_device *device = nv_device(pfb);
struct nva3_ramfuc *fuc = &ram->fuc;
@@ -197,7 +197,7 @@ nva3_link_train(struct nouveau_fb *pfb)
clk_current = clk->read(clk, nv_clk_src_mem);
- ret = nva3_clock_pre(clk, f);
+ ret = nva3_clk_pre(clk, f);
if (ret)
goto out;
@@ -252,7 +252,7 @@ nva3_link_train(struct nouveau_fb *pfb)
nv_mask(pfb, 0x616308, 0x10, 0x10);
nv_mask(pfb, 0x616b08, 0x10, 0x10);
- nva3_clock_post(clk, f);
+ nva3_clk_post(clk, f);
ram_train_result(pfb, result, 64);
for (i = 0; i < 64; i++)
@@ -274,7 +274,7 @@ out:
train->state = NVA3_TRAIN_UNSUPPORTED;
- nva3_clock_post(clk, f);
+ nva3_clk_post(clk, f);
return ret;
}
@@ -465,7 +465,7 @@ nouveau_gddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr)
}
static void
-nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clock_info *mclk)
+nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clk_info *mclk)
{
ram_wr32(fuc, 0x004004, mclk->pll);
ram_mask(fuc, 0x004000, 0x00000001, 0x00000001);
@@ -504,7 +504,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
struct nva3_ram *ram = (void *)pfb->ram;
struct nva3_ramfuc *fuc = &ram->fuc;
struct nva3_ltrain *train = &ram->ltrain;
- struct nva3_clock_info mclk;
+ struct nva3_clk_info mclk;
struct nouveau_ram_data *next;
u8 ver, hdr, cnt, len, strap;
u32 data;
@@ -555,7 +555,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
}
}
- ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
+ ret = nva3_pll_info(nouveau_clk(pfb), 0x12, 0x4000, freq, &mclk);
if (ret < 0) {
nv_error(pfb, "failed mclk calculation\n");
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c
index 735cb9580abe..d08eacd580d4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c
@@ -28,8 +28,8 @@
#include <subdev/bios/timing.h>
#include <subdev/ltc.h>
-#include <subdev/clock.h>
-#include <subdev/clock/pll.h>
+#include <subdev/clk.h>
+#include <subdev/clk/pll.h>
#include <core/option.h>
@@ -129,7 +129,7 @@ nvc0_ram_train(struct nvc0_ramfuc *fuc, u32 magic)
static int
nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
{
- struct nouveau_clock *clk = nouveau_clock(pfb);
+ struct nouveau_clk *clk = nouveau_clk(pfb);
struct nouveau_bios *bios = nouveau_bios(pfb);
struct nvc0_ram *ram = (void *)pfb->ram;
struct nvc0_ramfuc *fuc = &ram->fuc;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c
index 6bae474abb44..60050aab84b8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c
@@ -32,8 +32,8 @@
#include <subdev/bios/M0205.h>
#include <subdev/bios/M0209.h>
-#include <subdev/clock.h>
-#include <subdev/clock/pll.h>
+#include <subdev/clk.h>
+#include <subdev/clk/pll.h>
#include <subdev/timer.h>
@@ -1033,7 +1033,7 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next)
static int
nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
{
- struct nouveau_clock *clk = nouveau_clock(pfb);
+ struct nouveau_clk *clk = nouveau_clk(pfb);
struct nve0_ram *ram = (void *)pfb->ram;
struct nouveau_ram_data *xits = &ram->base.xition;
struct nouveau_ram_data *copy;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c
index f6b7df1b1686..a4e3a9b57306 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c
@@ -21,7 +21,7 @@
*/
#include "priv.h"
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/timer.h>
#include <subdev/volt.h>
@@ -50,15 +50,15 @@ struct gk20a_pwr_dvfs_dev_status {
static int
gk20a_pwr_dvfs_target(struct gk20a_pwr_priv *priv, int *state)
{
- struct nouveau_clock *clk = nouveau_clock(priv);
+ struct nouveau_clk *clk = nouveau_clk(priv);
- return nouveau_clock_astate(clk, *state, 0, false);
+ return nouveau_clk_astate(clk, *state, 0, false);
}
static int
gk20a_pwr_dvfs_get_cur_state(struct gk20a_pwr_priv *priv, int *state)
{
- struct nouveau_clock *clk = nouveau_clock(priv);
+ struct nouveau_clk *clk = nouveau_clk(priv);
*state = clk->pstate;
return 0;
@@ -69,7 +69,7 @@ gk20a_pwr_dvfs_get_target_state(struct gk20a_pwr_priv *priv,
int *state, int load)
{
struct gk20a_pwr_dvfs_data *data = priv->data;
- struct nouveau_clock *clk = nouveau_clock(priv);
+ struct nouveau_clk *clk = nouveau_clk(priv);
int cur_level, level;
/* For GK20A, the performance level is directly mapped to pstate */
@@ -117,7 +117,7 @@ gk20a_pwr_dvfs_work(struct nouveau_alarm *alarm)
struct gk20a_pwr_priv, alarm);
struct gk20a_pwr_dvfs_data *data = priv->data;
struct gk20a_pwr_dvfs_dev_status status;
- struct nouveau_clock *clk = nouveau_clock(priv);
+ struct nouveau_clk *clk = nouveau_clk(priv);
struct nouveau_volt *volt = nouveau_volt(priv);
u32 utilization = 0;
int state, ret;
From ebb58dc2ef8c62d1affa28160f57faa7b0e1dc02 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 00:04:21 +1000
Subject: [PATCH 38/86] drm/nouveau/pmu: rename from pwr (no binary change)
Switch to NVIDIA's name for the device.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/core/device.h | 2 +-
.../include/nvkm/subdev/{pwr.h => pmu.h} | 34 +--
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +-
.../drm/nouveau/nvkm/engine/device/gm100.c | 6 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 10 +-
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/graph/nve4.c | 8 +-
drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h | 10 +-
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild | 8 +
.../gpu/drm/nouveau/nvkm/subdev/pmu/base.c | 272 ++++++++++++++++++
.../nvkm/subdev/{pwr => pmu}/fuc/arith.fuc | 0
.../nvkm/subdev/{pwr => pmu}/fuc/host.fuc | 0
.../nvkm/subdev/{pwr => pmu}/fuc/i2c_.fuc | 0
.../nvkm/subdev/{pwr => pmu}/fuc/idle.fuc | 0
.../nvkm/subdev/{pwr => pmu}/fuc/kernel.fuc | 0
.../nvkm/subdev/{pwr => pmu}/fuc/macros.fuc | 0
.../nvkm/subdev/{pwr => pmu}/fuc/memx.fuc | 0
.../nvkm/subdev/{pwr => pmu}/fuc/nv108.fuc5 | 4 +-
.../nvkm/subdev/{pwr => pmu}/fuc/nv108.fuc5.h | 4 +-
.../nvkm/subdev/{pwr => pmu}/fuc/nva3.fuc3 | 4 +-
.../nvkm/subdev/{pwr => pmu}/fuc/nva3.fuc3.h | 4 +-
.../nvkm/subdev/{pwr => pmu}/fuc/nvc0.fuc3 | 4 +-
.../nvkm/subdev/{pwr => pmu}/fuc/nvc0.fuc3.h | 4 +-
.../nvkm/subdev/{pwr => pmu}/fuc/nvd0.fuc4 | 4 +-
.../nvkm/subdev/{pwr => pmu}/fuc/nvd0.fuc4.h | 4 +-
.../nouveau/nvkm/subdev/{pwr => pmu}/fuc/os.h | 0
.../nvkm/subdev/{pwr => pmu}/fuc/perf.fuc | 0
.../nvkm/subdev/{pwr => pmu}/fuc/test.fuc | 0
.../nouveau/nvkm/subdev/{pwr => pmu}/gk104.c | 54 ++--
.../nouveau/nvkm/subdev/{pwr => pmu}/gk20a.c | 94 +++---
.../nouveau/nvkm/subdev/{pwr => pmu}/memx.c | 66 ++---
.../nouveau/nvkm/subdev/{pwr => pmu}/nv108.c | 20 +-
.../nouveau/nvkm/subdev/{pwr => pmu}/nva3.c | 30 +-
.../nouveau/nvkm/subdev/{pwr => pmu}/nvc0.c | 20 +-
.../nouveau/nvkm/subdev/{pwr => pmu}/nvd0.c | 20 +-
.../gpu/drm/nouveau/nvkm/subdev/pmu/priv.h | 45 +++
.../gpu/drm/nouveau/nvkm/subdev/pwr/Kbuild | 8 -
.../gpu/drm/nouveau/nvkm/subdev/pwr/base.c | 272 ------------------
.../gpu/drm/nouveau/nvkm/subdev/pwr/priv.h | 45 ---
.../gpu/drm/nouveau/nvkm/subdev/therm/base.c | 2 +-
44 files changed, 551 insertions(+), 551 deletions(-)
rename drivers/gpu/drm/nouveau/include/nvkm/subdev/{pwr.h => pmu.h} (51%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/arith.fuc (100%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/host.fuc (100%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/i2c_.fuc (100%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/idle.fuc (100%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/kernel.fuc (100%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/macros.fuc (100%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/memx.fuc (100%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/nv108.fuc5 (97%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/nv108.fuc5.h (99%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/nva3.fuc3 (97%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/nva3.fuc3.h (99%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/nvc0.fuc3 (97%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/nvc0.fuc3.h (99%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/nvd0.fuc4 (97%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/nvd0.fuc4.h (99%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/os.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/perf.fuc (100%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/fuc/test.fuc (100%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/gk104.c (54%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/gk20a.c (64%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/memx.c (64%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/nv108.c (79%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/nva3.c (70%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/nvc0.c (79%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{pwr => pmu}/nvd0.c (79%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pwr/Kbuild
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pwr/base.c
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pwr/priv.h
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 87ecf6d23d9e..a2828ac6a65e 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -35,7 +35,7 @@ enum nv_subdev_type {
NVDEV_SUBDEV_INSTMEM,
NVDEV_SUBDEV_VM,
NVDEV_SUBDEV_BAR,
- NVDEV_SUBDEV_PWR,
+ NVDEV_SUBDEV_PMU,
NVDEV_SUBDEV_VOLT,
NVDEV_SUBDEV_THERM,
NVDEV_SUBDEV_CLK,
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pwr.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
similarity index 51%
rename from drivers/gpu/drm/nouveau/include/nvkm/subdev/pwr.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
index 83f85ac153ef..c890a4fb3cbb 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pwr.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
@@ -1,10 +1,10 @@
-#ifndef __NOUVEAU_PWR_H__
-#define __NOUVEAU_PWR_H__
+#ifndef __NOUVEAU_PMU_H__
+#define __NOUVEAU_PMU_H__
#include <core/subdev.h>
#include <core/device.h>
-struct nouveau_pwr {
+struct nouveau_pmu {
struct nouveau_subdev base;
struct {
@@ -23,26 +23,26 @@ struct nouveau_pwr {
u32 data[2];
} recv;
- int (*message)(struct nouveau_pwr *, u32[2], u32, u32, u32, u32);
- void (*pgob)(struct nouveau_pwr *, bool);
+ int (*message)(struct nouveau_pmu *, u32[2], u32, u32, u32, u32);
+ void (*pgob)(struct nouveau_pmu *, bool);
};
-static inline struct nouveau_pwr *
-nouveau_pwr(void *obj)
+static inline struct nouveau_pmu *
+nouveau_pmu(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_PWR);
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_PMU);
}
-extern struct nouveau_oclass *nva3_pwr_oclass;
-extern struct nouveau_oclass *nvc0_pwr_oclass;
-extern struct nouveau_oclass *nvd0_pwr_oclass;
-extern struct nouveau_oclass *gk104_pwr_oclass;
-extern struct nouveau_oclass *nv108_pwr_oclass;
-extern struct nouveau_oclass *gk20a_pwr_oclass;
+extern struct nouveau_oclass *nva3_pmu_oclass;
+extern struct nouveau_oclass *nvc0_pmu_oclass;
+extern struct nouveau_oclass *nvd0_pmu_oclass;
+extern struct nouveau_oclass *gk104_pmu_oclass;
+extern struct nouveau_oclass *nv108_pmu_oclass;
+extern struct nouveau_oclass *gk20a_pmu_oclass;
-/* interface to MEMX process running on PPWR */
+/* interface to MEMX process running on PMU */
struct nouveau_memx;
-int nouveau_memx_init(struct nouveau_pwr *, struct nouveau_memx **);
+int nouveau_memx_init(struct nouveau_pmu *, struct nouveau_memx **);
int nouveau_memx_fini(struct nouveau_memx **, bool exec);
void nouveau_memx_wr32(struct nouveau_memx *, u32 addr, u32 data);
void nouveau_memx_wait(struct nouveau_memx *,
@@ -50,7 +50,7 @@ void nouveau_memx_wait(struct nouveau_memx *,
void nouveau_memx_nsec(struct nouveau_memx *, u32 nsec);
void nouveau_memx_wait_vblank(struct nouveau_memx *);
void nouveau_memx_train(struct nouveau_memx *);
-int nouveau_memx_train_result(struct nouveau_pwr *, u32 *, int);
+int nouveau_memx_train_result(struct nouveau_pmu *, u32 *, int);
void nouveau_memx_block(struct nouveau_memx *);
void nouveau_memx_unblock(struct nouveau_memx *);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index f9589e8935d9..e141dff31553 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -222,7 +222,7 @@ static const u64 disable_map[] = {
[NVDEV_SUBDEV_BAR] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_VOLT] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_THERM] = NV_DEVICE_V0_DISABLE_CORE,
- [NVDEV_SUBDEV_PWR] = NV_DEVICE_V0_DISABLE_CORE,
+ [NVDEV_SUBDEV_PMU] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_FUSE] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_ENGINE_PERFMON] = NV_DEVICE_V0_DISABLE_CORE,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index e453a52135d7..763572fcb7d4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -39,7 +39,7 @@
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>
-#include <subdev/pwr.h>
+#include <subdev/pmu.h>
#include <subdev/volt.h>
#include <engine/device.h>
@@ -77,7 +77,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -121,7 +121,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index ccf82ab16881..867b79a0679a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -37,7 +37,7 @@
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>
-#include <subdev/pwr.h>
+#include <subdev/pmu.h>
#include <subdev/volt.h>
#include <engine/device.h>
@@ -362,7 +362,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
@@ -393,7 +393,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
@@ -423,7 +423,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
@@ -453,7 +453,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index ff5b2ab674bd..d54d6ac4cea5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -39,7 +39,7 @@
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>
-#include <subdev/pwr.h>
+#include <subdev/pmu.h>
#include <subdev/volt.h>
#include <engine/device.h>
@@ -77,7 +77,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -110,7 +110,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -143,7 +143,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -175,7 +175,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -208,7 +208,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -240,7 +240,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -272,7 +272,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -305,7 +305,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 7c02ff5b13ed..39b3fe32b9fb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -39,7 +39,7 @@
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>
-#include <subdev/pwr.h>
+#include <subdev/pmu.h>
#include <subdev/volt.h>
#include <engine/device.h>
@@ -77,7 +77,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = gk104_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
@@ -111,7 +111,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
@@ -145,7 +145,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = gk104_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
@@ -180,7 +180,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = gk20a_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass;
break;
case 0xf0:
device->cname = "GK110";
@@ -201,7 +201,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
@@ -235,7 +235,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
@@ -269,7 +269,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
@@ -302,7 +302,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c
index 83a966fc5301..8e6b62c4706c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c
@@ -22,7 +22,7 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-#include <subdev/pwr.h>
+#include <subdev/pmu.h>
#include "nvc0.h"
#include "ctxnvc0.h"
@@ -196,15 +196,15 @@ nve4_graph_init(struct nouveau_object *object)
{
struct nvc0_graph_oclass *oclass = (void *)object->oclass;
struct nvc0_graph_priv *priv = (void *)object;
- struct nouveau_pwr *ppwr = nouveau_pwr(priv);
+ struct nouveau_pmu *pmu = nouveau_pmu(priv);
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, rop;
int ret, i;
- if (ppwr)
- ppwr->pgob(ppwr, false);
+ if (pmu)
+ pmu->pgob(pmu, false);
ret = nouveau_graph_init(&priv->base);
if (ret)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
index 39f800a6f1e4..55090f73bab4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
@@ -12,7 +12,7 @@ include $(src)/nvkm/subdev/instmem/Kbuild
include $(src)/nvkm/subdev/ltc/Kbuild
include $(src)/nvkm/subdev/mc/Kbuild
include $(src)/nvkm/subdev/mxm/Kbuild
-include $(src)/nvkm/subdev/pwr/Kbuild
+include $(src)/nvkm/subdev/pmu/Kbuild
include $(src)/nvkm/subdev/therm/Kbuild
include $(src)/nvkm/subdev/timer/Kbuild
include $(src)/nvkm/subdev/vm/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h
index 0ac7256443bb..f641f3abd4f3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h
@@ -1,7 +1,7 @@
#ifndef __NVKM_FBRAM_FUC_H__
#define __NVKM_FBRAM_FUC_H__
-#include <subdev/pwr.h>
+#include <subdev/pmu.h>
struct ramfuc {
struct nouveau_memx *memx;
@@ -57,10 +57,10 @@ ramfuc_reg(u32 addr)
static inline int
ramfuc_init(struct ramfuc *ram, struct nouveau_fb *pfb)
{
- struct nouveau_pwr *ppwr = nouveau_pwr(pfb);
+ struct nouveau_pmu *pmu = nouveau_pmu(pfb);
int ret;
- ret = nouveau_memx_init(ppwr, &ram->memx);
+ ret = nouveau_memx_init(pmu, &ram->memx);
if (ret)
return ret;
@@ -149,9 +149,9 @@ ramfuc_train(struct ramfuc *ram)
static inline int
ramfuc_train_result(struct nouveau_fb *pfb, u32 *result, u32 rsize)
{
- struct nouveau_pwr *ppwr = nouveau_pwr(pfb);
+ struct nouveau_pmu *pmu = nouveau_pmu(pfb);
- return nouveau_memx_train_result(ppwr, result, rsize);
+ return nouveau_memx_train_result(pmu, result, rsize);
}
static inline void
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
index 3c76d9038f38..aa1c690fe0e1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
@@ -33,7 +33,7 @@ nv98_mc_intr[] = {
{ 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84:NVA3 */
{ 0x00008000, NVDEV_ENGINE_BSP },
{ 0x00020000, NVDEV_ENGINE_VP },
- { 0x00040000, NVDEV_SUBDEV_PWR }, /* NVA3:NVC0 */
+ { 0x00040000, NVDEV_SUBDEV_PMU }, /* NVA3:NVC0 */
{ 0x00080000, NVDEV_SUBDEV_THERM }, /* NVA3:NVC0 */
{ 0x00100000, NVDEV_SUBDEV_TIMER },
{ 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
index 15d41dc176ff..7053ae3db08e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
@@ -40,7 +40,7 @@ nvc0_mc_intr[] = {
{ 0x00100000, NVDEV_SUBDEV_TIMER },
{ 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */
{ 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */
- { 0x01000000, NVDEV_SUBDEV_PWR },
+ { 0x01000000, NVDEV_SUBDEV_PMU },
{ 0x02000000, NVDEV_SUBDEV_LTC },
{ 0x08000000, NVDEV_SUBDEV_FB },
{ 0x10000000, NVDEV_SUBDEV_BUS },
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild
new file mode 100644
index 000000000000..85c8392c8ace
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild
@@ -0,0 +1,8 @@
+nvkm-y += nvkm/subdev/pmu/base.o
+nvkm-y += nvkm/subdev/pmu/memx.o
+nvkm-y += nvkm/subdev/pmu/nva3.o
+nvkm-y += nvkm/subdev/pmu/nvc0.o
+nvkm-y += nvkm/subdev/pmu/nvd0.o
+nvkm-y += nvkm/subdev/pmu/gk104.o
+nvkm-y += nvkm/subdev/pmu/nv108.o
+nvkm-y += nvkm/subdev/pmu/gk20a.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c
new file mode 100644
index 000000000000..562ea6e16819
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <subdev/timer.h>
+
+#include "priv.h"
+
+void
+nouveau_pmu_pgob(struct nouveau_pmu *pmu, bool enable)
+{
+ const struct nvkm_pmu_impl *impl = (void *)nv_oclass(pmu);
+ if (impl->pgob)
+ impl->pgob(pmu, enable);
+}
+
+static int
+nouveau_pmu_send(struct nouveau_pmu *pmu, u32 reply[2],
+ u32 process, u32 message, u32 data0, u32 data1)
+{
+ struct nouveau_subdev *subdev = nv_subdev(pmu);
+ u32 addr;
+
+ /* wait for a free slot in the fifo */
+ addr = nv_rd32(pmu, 0x10a4a0);
+ if (!nv_wait_ne(pmu, 0x10a4b0, 0xffffffff, addr ^ 8))
+ return -EBUSY;
+
+ /* we currently only support a single process at a time waiting
+ * on a synchronous reply, take the PMU mutex and tell the
+ * receive handler what we're waiting for
+ */
+ if (reply) {
+ mutex_lock(&subdev->mutex);
+ pmu->recv.message = message;
+ pmu->recv.process = process;
+ }
+
+ /* acquire data segment access */
+ do {
+ nv_wr32(pmu, 0x10a580, 0x00000001);
+ } while (nv_rd32(pmu, 0x10a580) != 0x00000001);
+
+ /* write the packet */
+ nv_wr32(pmu, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) +
+ pmu->send.base));
+ nv_wr32(pmu, 0x10a1c4, process);
+ nv_wr32(pmu, 0x10a1c4, message);
+ nv_wr32(pmu, 0x10a1c4, data0);
+ nv_wr32(pmu, 0x10a1c4, data1);
+ nv_wr32(pmu, 0x10a4a0, (addr + 1) & 0x0f);
+
+ /* release data segment access */
+ nv_wr32(pmu, 0x10a580, 0x00000000);
+
+ /* wait for reply, if requested */
+ if (reply) {
+ wait_event(pmu->recv.wait, (pmu->recv.process == 0));
+ reply[0] = pmu->recv.data[0];
+ reply[1] = pmu->recv.data[1];
+ mutex_unlock(&subdev->mutex);
+ }
+
+ return 0;
+}
+
+static void
+nouveau_pmu_recv(struct work_struct *work)
+{
+ struct nouveau_pmu *pmu =
+ container_of(work, struct nouveau_pmu, recv.work);
+ u32 process, message, data0, data1;
+
+ /* nothing to do if GET == PUT */
+ u32 addr = nv_rd32(pmu, 0x10a4cc);
+ if (addr == nv_rd32(pmu, 0x10a4c8))
+ return;
+
+ /* acquire data segment access */
+ do {
+ nv_wr32(pmu, 0x10a580, 0x00000002);
+ } while (nv_rd32(pmu, 0x10a580) != 0x00000002);
+
+ /* read the packet */
+ nv_wr32(pmu, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) +
+ pmu->recv.base));
+ process = nv_rd32(pmu, 0x10a1c4);
+ message = nv_rd32(pmu, 0x10a1c4);
+ data0 = nv_rd32(pmu, 0x10a1c4);
+ data1 = nv_rd32(pmu, 0x10a1c4);
+ nv_wr32(pmu, 0x10a4cc, (addr + 1) & 0x0f);
+
+ /* release data segment access */
+ nv_wr32(pmu, 0x10a580, 0x00000000);
+
+ /* wake process if it's waiting on a synchronous reply */
+ if (pmu->recv.process) {
+ if (process == pmu->recv.process &&
+ message == pmu->recv.message) {
+ pmu->recv.data[0] = data0;
+ pmu->recv.data[1] = data1;
+ pmu->recv.process = 0;
+ wake_up(&pmu->recv.wait);
+ return;
+ }
+ }
+
+ /* right now there's no other expected responses from the engine,
+ * so assume that any unexpected message is an error.
+ */
+ nv_warn(pmu, "%c%c%c%c 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ (char)((process & 0x000000ff) >> 0),
+ (char)((process & 0x0000ff00) >> 8),
+ (char)((process & 0x00ff0000) >> 16),
+ (char)((process & 0xff000000) >> 24),
+ process, message, data0, data1);
+}
+
+static void
+nouveau_pmu_intr(struct nouveau_subdev *subdev)
+{
+ struct nouveau_pmu *pmu = (void *)subdev;
+ u32 disp = nv_rd32(pmu, 0x10a01c);
+ u32 intr = nv_rd32(pmu, 0x10a008) & disp & ~(disp >> 16);
+
+ if (intr & 0x00000020) {
+ u32 stat = nv_rd32(pmu, 0x10a16c);
+ if (stat & 0x80000000) {
+ nv_error(pmu, "UAS fault at 0x%06x addr 0x%08x\n",
+ stat & 0x00ffffff, nv_rd32(pmu, 0x10a168));
+ nv_wr32(pmu, 0x10a16c, 0x00000000);
+ intr &= ~0x00000020;
+ }
+ }
+
+ if (intr & 0x00000040) {
+ schedule_work(&pmu->recv.work);
+ nv_wr32(pmu, 0x10a004, 0x00000040);
+ intr &= ~0x00000040;
+ }
+
+ if (intr & 0x00000080) {
+ nv_info(pmu, "wr32 0x%06x 0x%08x\n", nv_rd32(pmu, 0x10a7a0),
+ nv_rd32(pmu, 0x10a7a4));
+ nv_wr32(pmu, 0x10a004, 0x00000080);
+ intr &= ~0x00000080;
+ }
+
+ if (intr) {
+ nv_error(pmu, "intr 0x%08x\n", intr);
+ nv_wr32(pmu, 0x10a004, intr);
+ }
+}
+
+int
+_nouveau_pmu_fini(struct nouveau_object *object, bool suspend)
+{
+ struct nouveau_pmu *pmu = (void *)object;
+
+ nv_wr32(pmu, 0x10a014, 0x00000060);
+ flush_work(&pmu->recv.work);
+
+ return nouveau_subdev_fini(&pmu->base, suspend);
+}
+
+int
+_nouveau_pmu_init(struct nouveau_object *object)
+{
+ const struct nvkm_pmu_impl *impl = (void *)object->oclass;
+ struct nouveau_pmu *pmu = (void *)object;
+ int ret, i;
+
+ ret = nouveau_subdev_init(&pmu->base);
+ if (ret)
+ return ret;
+
+ nv_subdev(pmu)->intr = nouveau_pmu_intr;
+ pmu->message = nouveau_pmu_send;
+ pmu->pgob = nouveau_pmu_pgob;
+
+ /* prevent previous ucode from running, wait for idle, reset */
+ nv_wr32(pmu, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */
+ nv_wait(pmu, 0x10a04c, 0xffffffff, 0x00000000);
+ nv_mask(pmu, 0x000200, 0x00002000, 0x00000000);
+ nv_mask(pmu, 0x000200, 0x00002000, 0x00002000);
+ nv_rd32(pmu, 0x000200);
+ nv_wait(pmu, 0x10a10c, 0x00000006, 0x00000000);
+
+ /* upload data segment */
+ nv_wr32(pmu, 0x10a1c0, 0x01000000);
+ for (i = 0; i < impl->data.size / 4; i++)
+ nv_wr32(pmu, 0x10a1c4, impl->data.data[i]);
+
+ /* upload code segment */
+ nv_wr32(pmu, 0x10a180, 0x01000000);
+ for (i = 0; i < impl->code.size / 4; i++) {
+ if ((i & 0x3f) == 0)
+ nv_wr32(pmu, 0x10a188, i >> 6);
+ nv_wr32(pmu, 0x10a184, impl->code.data[i]);
+ }
+
+ /* start it running */
+ nv_wr32(pmu, 0x10a10c, 0x00000000);
+ nv_wr32(pmu, 0x10a104, 0x00000000);
+ nv_wr32(pmu, 0x10a100, 0x00000002);
+
+ /* wait for valid host->pmu ring configuration */
+ if (!nv_wait_ne(pmu, 0x10a4d0, 0xffffffff, 0x00000000))
+ return -EBUSY;
+ pmu->send.base = nv_rd32(pmu, 0x10a4d0) & 0x0000ffff;
+ pmu->send.size = nv_rd32(pmu, 0x10a4d0) >> 16;
+
+ /* wait for valid pmu->host ring configuration */
+ if (!nv_wait_ne(pmu, 0x10a4dc, 0xffffffff, 0x00000000))
+ return -EBUSY;
+ pmu->recv.base = nv_rd32(pmu, 0x10a4dc) & 0x0000ffff;
+ pmu->recv.size = nv_rd32(pmu, 0x10a4dc) >> 16;
+
+ nv_wr32(pmu, 0x10a010, 0x000000e0);
+ return 0;
+}
+
+int
+nouveau_pmu_create_(struct nouveau_object *parent,
+ struct nouveau_object *engine,
+ struct nouveau_oclass *oclass, int length, void **pobject)
+{
+ struct nouveau_pmu *pmu;
+ int ret;
+
+ ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PMU",
+ "pmu", length, pobject);
+ pmu = *pobject;
+ if (ret)
+ return ret;
+
+ INIT_WORK(&pmu->recv.work, nouveau_pmu_recv);
+ init_waitqueue_head(&pmu->recv.wait);
+ return 0;
+}
+
+int
+_nouveau_pmu_ctor(struct nouveau_object *parent,
+ struct nouveau_object *engine,
+ struct nouveau_oclass *oclass, void *data, u32 size,
+ struct nouveau_object **pobject)
+{
+ struct nouveau_pmu *pmu;
+ int ret = nouveau_pmu_create(parent, engine, oclass, &pmu);
+ *pobject = nv_object(pmu);
+ return ret;
+}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/arith.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/arith.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/arith.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/arith.fuc
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/host.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/host.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/host.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/host.fuc
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/i2c_.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/i2c_.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/i2c_.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/i2c_.fuc
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/idle.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/idle.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/idle.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/idle.fuc
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/kernel.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/kernel.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/kernel.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/kernel.fuc
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/macros.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/macros.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/memx.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/memx.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nv108.fuc5
similarity index 97%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nv108.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nv108.fuc5
index b439519ec866..d2214ab68f09 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nv108.fuc5
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nv108.fuc5
@@ -32,7 +32,7 @@
#include "macros.fuc"
-.section #nv108_pwr_data
+.section #nv108_pmu_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "arith.fuc"
@@ -56,7 +56,7 @@
#undef INCLUDE_DATA
.align 256
-.section #nv108_pwr_code
+.section #nv108_pmu_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "arith.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nv108.fuc5.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nv108.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nv108.fuc5.h
index 713e11e2953d..c25ee1f88128 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nv108.fuc5.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nv108.fuc5.h
@@ -1,4 +1,4 @@
-uint32_t nv108_pwr_data[] = {
+uint32_t nv108_pmu_data[] = {
/* 0x0000: proc_kern */
0x52544e49,
0x00000000,
@@ -915,7 +915,7 @@ uint32_t nv108_pwr_data[] = {
0x00000000,
};
-uint32_t nv108_pwr_code[] = {
+uint32_t nv108_pmu_code[] = {
0x031c0ef5,
/* 0x0004: rd32 */
0xf607a040,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nva3.fuc3 b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nva3.fuc3
similarity index 97%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nva3.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nva3.fuc3
index daa06c1c655e..93d76177e935 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nva3.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nva3.fuc3
@@ -32,7 +32,7 @@
#include "macros.fuc"
-.section #nva3_pwr_data
+.section #nva3_pmu_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "arith.fuc"
@@ -56,7 +56,7 @@
#undef INCLUDE_DATA
.align 256
-.section #nva3_pwr_code
+.section #nva3_pmu_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "arith.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nva3.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nva3.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nva3.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nva3.fuc3.h
index d1f9b6cb66d7..e8274401338c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nva3.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nva3.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nva3_pwr_data[] = {
+uint32_t nva3_pmu_data[] = {
/* 0x0000: proc_kern */
0x52544e49,
0x00000000,
@@ -916,7 +916,7 @@ uint32_t nva3_pwr_data[] = {
0x00000000,
};
-uint32_t nva3_pwr_code[] = {
+uint32_t nva3_pmu_code[] = {
0x039e0ef5,
/* 0x0004: rd32 */
0x07a007f1,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvc0.fuc3
similarity index 97%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvc0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvc0.fuc3
index 21bf8cc7618f..6eee93d3c313 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvc0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvc0.fuc3
@@ -32,7 +32,7 @@
#include "macros.fuc"
-.section #nvc0_pwr_data
+.section #nvc0_pmu_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "arith.fuc"
@@ -56,7 +56,7 @@
#undef INCLUDE_DATA
.align 256
-.section #nvc0_pwr_code
+.section #nvc0_pmu_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "arith.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvc0.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvc0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvc0.fuc3.h
index 90221d973f84..124f5c13ac0a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvc0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvc0.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvc0_pwr_data[] = {
+uint32_t nvc0_pmu_data[] = {
/* 0x0000: proc_kern */
0x52544e49,
0x00000000,
@@ -916,7 +916,7 @@ uint32_t nvc0_pwr_data[] = {
0x00000000,
};
-uint32_t nvc0_pwr_code[] = {
+uint32_t nvc0_pmu_code[] = {
0x039e0ef5,
/* 0x0004: rd32 */
0x07a007f1,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvd0.fuc4 b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvd0.fuc4
similarity index 97%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvd0.fuc4
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvd0.fuc4
index b85443261569..e11f9934d977 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvd0.fuc4
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvd0.fuc4
@@ -32,7 +32,7 @@
#include "macros.fuc"
-.section #nvd0_pwr_data
+.section #nvd0_pmu_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "arith.fuc"
@@ -56,7 +56,7 @@
#undef INCLUDE_DATA
.align 256
-.section #nvd0_pwr_code
+.section #nvd0_pmu_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "arith.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvd0.fuc4.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvd0.fuc4.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvd0.fuc4.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvd0.fuc4.h
index 7e16aab44d85..6fc8c704f38b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/nvd0.fuc4.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvd0.fuc4.h
@@ -1,4 +1,4 @@
-uint32_t nvd0_pwr_data[] = {
+uint32_t nvd0_pmu_data[] = {
/* 0x0000: proc_kern */
0x52544e49,
0x00000000,
@@ -915,7 +915,7 @@ uint32_t nvd0_pwr_data[] = {
0x00000000,
};
-uint32_t nvd0_pwr_code[] = {
+uint32_t nvd0_pmu_code[] = {
0x034d0ef5,
/* 0x0004: rd32 */
0x07a007f1,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/os.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/os.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/os.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/os.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/perf.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/perf.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/perf.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/perf.fuc
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/test.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/test.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/fuc/test.fuc
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/test.fuc
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c
similarity index 54%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk104.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c
index 9bb419c90451..7776b4a0958e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c
@@ -24,46 +24,46 @@
#include "priv.h"
-#define nvd0_pwr_code gk104_pwr_code
-#define nvd0_pwr_data gk104_pwr_data
+#define nvd0_pmu_code gk104_pmu_code
+#define nvd0_pmu_data gk104_pmu_data
#include "fuc/nvd0.fuc4.h"
static void
-gk104_pwr_pgob(struct nouveau_pwr *ppwr, bool enable)
+gk104_pmu_pgob(struct nouveau_pmu *pmu, bool enable)
{
- nv_mask(ppwr, 0x000200, 0x00001000, 0x00000000);
- nv_rd32(ppwr, 0x000200);
- nv_mask(ppwr, 0x000200, 0x08000000, 0x08000000);
+ nv_mask(pmu, 0x000200, 0x00001000, 0x00000000);
+ nv_rd32(pmu, 0x000200);
+ nv_mask(pmu, 0x000200, 0x08000000, 0x08000000);
msleep(50);
- nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000002);
- nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001);
- nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000);
+ nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000002);
+ nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001);
+ nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000);
- nv_mask(ppwr, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000);
+ nv_mask(pmu, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000);
msleep(50);
- nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000000);
- nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001);
- nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000);
+ nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000000);
+ nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001);
+ nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000);
- nv_mask(ppwr, 0x000200, 0x08000000, 0x00000000);
- nv_mask(ppwr, 0x000200, 0x00001000, 0x00001000);
- nv_rd32(ppwr, 0x000200);
+ nv_mask(pmu, 0x000200, 0x08000000, 0x00000000);
+ nv_mask(pmu, 0x000200, 0x00001000, 0x00001000);
+ nv_rd32(pmu, 0x000200);
}
struct nouveau_oclass *
-gk104_pwr_oclass = &(struct nvkm_pwr_impl) {
- .base.handle = NV_SUBDEV(PWR, 0xe4),
+gk104_pmu_oclass = &(struct nvkm_pmu_impl) {
+ .base.handle = NV_SUBDEV(PMU, 0xe4),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pwr_ctor,
- .dtor = _nouveau_pwr_dtor,
- .init = _nouveau_pwr_init,
- .fini = _nouveau_pwr_fini,
+ .ctor = _nouveau_pmu_ctor,
+ .dtor = _nouveau_pmu_dtor,
+ .init = _nouveau_pmu_init,
+ .fini = _nouveau_pmu_fini,
},
- .code.data = gk104_pwr_code,
- .code.size = sizeof(gk104_pwr_code),
- .data.data = gk104_pwr_data,
- .data.size = sizeof(gk104_pwr_data),
- .pgob = gk104_pwr_pgob,
+ .code.data = gk104_pmu_code,
+ .code.size = sizeof(gk104_pmu_code),
+ .data.data = gk104_pmu_data,
+ .data.size = sizeof(gk104_pmu_data),
+ .pgob = gk104_pmu_pgob,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
similarity index 64%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
index a4e3a9b57306..28d858a875bf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
@@ -28,27 +28,27 @@
#define BUSY_SLOT 0
#define CLK_SLOT 7
-struct gk20a_pwr_dvfs_data {
+struct gk20a_pmu_dvfs_data {
int p_load_target;
int p_load_max;
int p_smooth;
unsigned int avg_load;
};
-struct gk20a_pwr_priv {
- struct nouveau_pwr base;
+struct gk20a_pmu_priv {
+ struct nouveau_pmu base;
struct nouveau_alarm alarm;
- struct gk20a_pwr_dvfs_data *data;
+ struct gk20a_pmu_dvfs_data *data;
};
-struct gk20a_pwr_dvfs_dev_status {
+struct gk20a_pmu_dvfs_dev_status {
unsigned long total;
unsigned long busy;
int cur_state;
};
static int
-gk20a_pwr_dvfs_target(struct gk20a_pwr_priv *priv, int *state)
+gk20a_pmu_dvfs_target(struct gk20a_pmu_priv *priv, int *state)
{
struct nouveau_clk *clk = nouveau_clk(priv);
@@ -56,7 +56,7 @@ gk20a_pwr_dvfs_target(struct gk20a_pwr_priv *priv, int *state)
}
static int
-gk20a_pwr_dvfs_get_cur_state(struct gk20a_pwr_priv *priv, int *state)
+gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu_priv *priv, int *state)
{
struct nouveau_clk *clk = nouveau_clk(priv);
@@ -65,10 +65,10 @@ gk20a_pwr_dvfs_get_cur_state(struct gk20a_pwr_priv *priv, int *state)
}
static int
-gk20a_pwr_dvfs_get_target_state(struct gk20a_pwr_priv *priv,
+gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu_priv *priv,
int *state, int load)
{
- struct gk20a_pwr_dvfs_data *data = priv->data;
+ struct gk20a_pmu_dvfs_data *data = priv->data;
struct nouveau_clk *clk = nouveau_clk(priv);
int cur_level, level;
@@ -95,8 +95,8 @@ gk20a_pwr_dvfs_get_target_state(struct gk20a_pwr_priv *priv,
}
static int
-gk20a_pwr_dvfs_get_dev_status(struct gk20a_pwr_priv *priv,
- struct gk20a_pwr_dvfs_dev_status *status)
+gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu_priv *priv,
+ struct gk20a_pmu_dvfs_dev_status *status)
{
status->busy = nv_rd32(priv, 0x10a508 + (BUSY_SLOT * 0x10));
status->total= nv_rd32(priv, 0x10a508 + (CLK_SLOT * 0x10));
@@ -104,32 +104,32 @@ gk20a_pwr_dvfs_get_dev_status(struct gk20a_pwr_priv *priv,
}
static void
-gk20a_pwr_dvfs_reset_dev_status(struct gk20a_pwr_priv *priv)
+gk20a_pmu_dvfs_reset_dev_status(struct gk20a_pmu_priv *priv)
{
nv_wr32(priv, 0x10a508 + (BUSY_SLOT * 0x10), 0x80000000);
nv_wr32(priv, 0x10a508 + (CLK_SLOT * 0x10), 0x80000000);
}
static void
-gk20a_pwr_dvfs_work(struct nouveau_alarm *alarm)
+gk20a_pmu_dvfs_work(struct nouveau_alarm *alarm)
{
- struct gk20a_pwr_priv *priv = container_of(alarm,
- struct gk20a_pwr_priv, alarm);
- struct gk20a_pwr_dvfs_data *data = priv->data;
- struct gk20a_pwr_dvfs_dev_status status;
+ struct gk20a_pmu_priv *priv = container_of(alarm,
+ struct gk20a_pmu_priv, alarm);
+ struct gk20a_pmu_dvfs_data *data = priv->data;
+ struct gk20a_pmu_dvfs_dev_status status;
struct nouveau_clk *clk = nouveau_clk(priv);
struct nouveau_volt *volt = nouveau_volt(priv);
u32 utilization = 0;
int state, ret;
/*
- * The PWR is initialized before CLK and VOLT, so we have to make sure the
+ * The PMU is initialized before CLK and VOLT, so we have to make sure the
* CLK and VOLT are ready here.
*/
if (!clk || !volt)
goto resched;
- ret = gk20a_pwr_dvfs_get_dev_status(priv, &status);
+ ret = gk20a_pmu_dvfs_get_dev_status(priv, &status);
if (ret) {
nv_warn(priv, "failed to get device status\n");
goto resched;
@@ -143,90 +143,90 @@ gk20a_pwr_dvfs_work(struct nouveau_alarm *alarm)
nv_trace(priv, "utilization = %d %%, avg_load = %d %%\n",
utilization, data->avg_load);
- ret = gk20a_pwr_dvfs_get_cur_state(priv, &state);
+ ret = gk20a_pmu_dvfs_get_cur_state(priv, &state);
if (ret) {
nv_warn(priv, "failed to get current state\n");
goto resched;
}
- if (gk20a_pwr_dvfs_get_target_state(priv, &state, data->avg_load)) {
+ if (gk20a_pmu_dvfs_get_target_state(priv, &state, data->avg_load)) {
nv_trace(priv, "set new state to %d\n", state);
- gk20a_pwr_dvfs_target(priv, &state);
+ gk20a_pmu_dvfs_target(priv, &state);
}
resched:
- gk20a_pwr_dvfs_reset_dev_status(priv);
+ gk20a_pmu_dvfs_reset_dev_status(priv);
nouveau_timer_alarm(priv, 100000000, alarm);
}
int
-gk20a_pwr_fini(struct nouveau_object *object, bool suspend)
+gk20a_pmu_fini(struct nouveau_object *object, bool suspend)
{
- struct nouveau_pwr *ppwr = (void *)object;
- struct gk20a_pwr_priv *priv = (void *)ppwr;
+ struct nouveau_pmu *pmu = (void *)object;
+ struct gk20a_pmu_priv *priv = (void *)pmu;
nouveau_timer_alarm_cancel(priv, &priv->alarm);
- return nouveau_subdev_fini(&ppwr->base, suspend);
+ return nouveau_subdev_fini(&pmu->base, suspend);
}
int
-gk20a_pwr_init(struct nouveau_object *object)
+gk20a_pmu_init(struct nouveau_object *object)
{
- struct nouveau_pwr *ppwr = (void *)object;
- struct gk20a_pwr_priv *priv = (void *)ppwr;
+ struct nouveau_pmu *pmu = (void *)object;
+ struct gk20a_pmu_priv *priv = (void *)pmu;
int ret;
- ret = nouveau_subdev_init(&ppwr->base);
+ ret = nouveau_subdev_init(&pmu->base);
if (ret)
return ret;
- ppwr->pgob = nouveau_pwr_pgob;
+ pmu->pgob = nouveau_pmu_pgob;
/* init pwr perf counter */
- nv_wr32(ppwr, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001);
- nv_wr32(ppwr, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002);
- nv_wr32(ppwr, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
+ nv_wr32(pmu, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001);
+ nv_wr32(pmu, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002);
+ nv_wr32(pmu, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
- nouveau_timer_alarm(ppwr, 2000000000, &priv->alarm);
+ nouveau_timer_alarm(pmu, 2000000000, &priv->alarm);
return ret;
}
-struct gk20a_pwr_dvfs_data gk20a_dvfs_data= {
+struct gk20a_pmu_dvfs_data gk20a_dvfs_data= {
.p_load_target = 70,
.p_load_max = 90,
.p_smooth = 1,
};
static int
-gk20a_pwr_ctor(struct nouveau_object *parent,
+gk20a_pmu_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct gk20a_pwr_priv *priv;
+ struct gk20a_pmu_priv *priv;
int ret;
- ret = nouveau_pwr_create(parent, engine, oclass, &priv);
+ ret = nouveau_pmu_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->data = &gk20a_dvfs_data;
- nouveau_alarm_init(&priv->alarm, gk20a_pwr_dvfs_work);
+ nouveau_alarm_init(&priv->alarm, gk20a_pmu_dvfs_work);
return 0;
}
struct nouveau_oclass *
-gk20a_pwr_oclass = &(struct nvkm_pwr_impl) {
- .base.handle = NV_SUBDEV(PWR, 0xea),
+gk20a_pmu_oclass = &(struct nvkm_pmu_impl) {
+ .base.handle = NV_SUBDEV(PMU, 0xea),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = gk20a_pwr_ctor,
- .dtor = _nouveau_pwr_dtor,
- .init = gk20a_pwr_init,
- .fini = gk20a_pwr_fini,
+ .ctor = gk20a_pmu_ctor,
+ .dtor = _nouveau_pmu_dtor,
+ .init = gk20a_pmu_init,
+ .fini = gk20a_pmu_fini,
},
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/memx.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
similarity index 64%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/memx.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
index 7a9299d7159f..671c7177d3af 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/memx.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
@@ -1,10 +1,10 @@
-#ifndef __NVKM_PWR_MEMX_H__
-#define __NVKM_PWR_MEMX_H__
+#ifndef __NVKM_PMU_MEMX_H__
+#define __NVKM_PMU_MEMX_H__
#include "priv.h"
struct nouveau_memx {
- struct nouveau_pwr *ppwr;
+ struct nouveau_pmu *pmu;
u32 base;
u32 size;
struct {
@@ -17,13 +17,13 @@ struct nouveau_memx {
static void
memx_out(struct nouveau_memx *memx)
{
- struct nouveau_pwr *ppwr = memx->ppwr;
+ struct nouveau_pmu *pmu = memx->pmu;
int i;
if (memx->c.mthd) {
- nv_wr32(ppwr, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd);
+ nv_wr32(pmu, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd);
for (i = 0; i < memx->c.size; i++)
- nv_wr32(ppwr, 0x10a1c4, memx->c.data[i]);
+ nv_wr32(pmu, 0x10a1c4, memx->c.data[i]);
memx->c.mthd = 0;
memx->c.size = 0;
}
@@ -41,13 +41,13 @@ memx_cmd(struct nouveau_memx *memx, u32 mthd, u32 size, u32 data[])
}
int
-nouveau_memx_init(struct nouveau_pwr *ppwr, struct nouveau_memx **pmemx)
+nouveau_memx_init(struct nouveau_pmu *pmu, struct nouveau_memx **pmemx)
{
struct nouveau_memx *memx;
u32 reply[2];
int ret;
- ret = ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_INFO,
+ ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
MEMX_INFO_DATA, 0);
if (ret)
return ret;
@@ -55,15 +55,15 @@ nouveau_memx_init(struct nouveau_pwr *ppwr, struct nouveau_memx **pmemx)
memx = *pmemx = kzalloc(sizeof(*memx), GFP_KERNEL);
if (!memx)
return -ENOMEM;
- memx->ppwr = ppwr;
+ memx->pmu = pmu;
memx->base = reply[0];
memx->size = reply[1];
/* acquire data segment access */
do {
- nv_wr32(ppwr, 0x10a580, 0x00000003);
- } while (nv_rd32(ppwr, 0x10a580) != 0x00000003);
- nv_wr32(ppwr, 0x10a1c0, 0x01000000 | memx->base);
+ nv_wr32(pmu, 0x10a580, 0x00000003);
+ } while (nv_rd32(pmu, 0x10a580) != 0x00000003);
+ nv_wr32(pmu, 0x10a1c0, 0x01000000 | memx->base);
return 0;
}
@@ -72,23 +72,23 @@ int
nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec)
{
struct nouveau_memx *memx = *pmemx;
- struct nouveau_pwr *ppwr = memx->ppwr;
+ struct nouveau_pmu *pmu = memx->pmu;
u32 finish, reply[2];
/* flush the cache... */
memx_out(memx);
/* release data segment access */
- finish = nv_rd32(ppwr, 0x10a1c0) & 0x00ffffff;
- nv_wr32(ppwr, 0x10a580, 0x00000000);
+ finish = nv_rd32(pmu, 0x10a1c0) & 0x00ffffff;
+ nv_wr32(pmu, 0x10a580, 0x00000000);
/* call MEMX process to execute the script, and wait for reply */
if (exec) {
- ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_EXEC,
+ pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_EXEC,
memx->base, finish);
}
- nv_debug(memx->ppwr, "Exec took %uns, PPWR_IN %08x\n",
+ nv_debug(memx->pmu, "Exec took %uns, PMU_IN %08x\n",
reply[0], reply[1]);
kfree(memx);
return 0;
@@ -97,7 +97,7 @@ nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec)
void
nouveau_memx_wr32(struct nouveau_memx *memx, u32 addr, u32 data)
{
- nv_debug(memx->ppwr, "R[%06x] = 0x%08x\n", addr, data);
+ nv_debug(memx->pmu, "R[%06x] = 0x%08x\n", addr, data);
memx_cmd(memx, MEMX_WR32, 2, (u32[]){ addr, data });
}
@@ -105,7 +105,7 @@ void
nouveau_memx_wait(struct nouveau_memx *memx,
u32 addr, u32 mask, u32 data, u32 nsec)
{
- nv_debug(memx->ppwr, "R[%06x] & 0x%08x == 0x%08x, %d us\n",
+ nv_debug(memx->pmu, "R[%06x] & 0x%08x == 0x%08x, %d us\n",
addr, mask, data, nsec);
memx_cmd(memx, MEMX_WAIT, 4, (u32[]){ addr, mask, data, nsec });
memx_out(memx); /* fuc can't handle multiple */
@@ -114,7 +114,7 @@ nouveau_memx_wait(struct nouveau_memx *memx,
void
nouveau_memx_nsec(struct nouveau_memx *memx, u32 nsec)
{
- nv_debug(memx->ppwr, " DELAY = %d ns\n", nsec);
+ nv_debug(memx->pmu, " DELAY = %d ns\n", nsec);
memx_cmd(memx, MEMX_DELAY, 1, (u32[]){ nsec });
memx_out(memx); /* fuc can't handle multiple */
}
@@ -122,16 +122,16 @@ nouveau_memx_nsec(struct nouveau_memx *memx, u32 nsec)
void
nouveau_memx_wait_vblank(struct nouveau_memx *memx)
{
- struct nouveau_pwr *ppwr = memx->ppwr;
+ struct nouveau_pmu *pmu = memx->pmu;
u32 heads, x, y, px = 0;
int i, head_sync;
- if (nv_device(ppwr)->chipset < 0xd0) {
- heads = nv_rd32(ppwr, 0x610050);
+ if (nv_device(pmu)->chipset < 0xd0) {
+ heads = nv_rd32(pmu, 0x610050);
for (i = 0; i < 2; i++) {
/* Heuristic: sync to head with biggest resolution */
if (heads & (2 << (i << 3))) {
- x = nv_rd32(ppwr, 0x610b40 + (0x540 * i));
+ x = nv_rd32(pmu, 0x610b40 + (0x540 * i));
y = (x & 0xffff0000) >> 16;
x &= 0x0000ffff;
if ((x * y) > px) {
@@ -143,11 +143,11 @@ nouveau_memx_wait_vblank(struct nouveau_memx *memx)
}
if (px == 0) {
- nv_debug(memx->ppwr, "WAIT VBLANK !NO ACTIVE HEAD\n");
+ nv_debug(memx->pmu, "WAIT VBLANK !NO ACTIVE HEAD\n");
return;
}
- nv_debug(memx->ppwr, "WAIT VBLANK HEAD%d\n", head_sync);
+ nv_debug(memx->pmu, "WAIT VBLANK HEAD%d\n", head_sync);
memx_cmd(memx, MEMX_VBLANK, 1, (u32[]){ head_sync });
memx_out(memx); /* fuc can't handle multiple */
}
@@ -155,17 +155,17 @@ nouveau_memx_wait_vblank(struct nouveau_memx *memx)
void
nouveau_memx_train(struct nouveau_memx *memx)
{
- nv_debug(memx->ppwr, " MEM TRAIN\n");
+ nv_debug(memx->pmu, " MEM TRAIN\n");
memx_cmd(memx, MEMX_TRAIN, 0, NULL);
}
int
-nouveau_memx_train_result(struct nouveau_pwr *ppwr, u32 *res, int rsize)
+nouveau_memx_train_result(struct nouveau_pmu *pmu, u32 *res, int rsize)
{
u32 reply[2], base, size, i;
int ret;
- ret = ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_INFO,
+ ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
MEMX_INFO_TRAIN, 0);
if (ret)
return ret;
@@ -176,10 +176,10 @@ nouveau_memx_train_result(struct nouveau_pwr *ppwr, u32 *res, int rsize)
return -ENOMEM;
/* read the packet */
- nv_wr32(ppwr, 0x10a1c0, 0x02000000 | base);
+ nv_wr32(pmu, 0x10a1c0, 0x02000000 | base);
for (i = 0; i < size; i++)
- res[i] = nv_rd32(ppwr, 0x10a1c4);
+ res[i] = nv_rd32(pmu, 0x10a1c4);
return 0;
}
@@ -187,14 +187,14 @@ nouveau_memx_train_result(struct nouveau_pwr *ppwr, u32 *res, int rsize)
void
nouveau_memx_block(struct nouveau_memx *memx)
{
- nv_debug(memx->ppwr, " HOST BLOCKED\n");
+ nv_debug(memx->pmu, " HOST BLOCKED\n");
memx_cmd(memx, MEMX_ENTER, 0, NULL);
}
void
nouveau_memx_unblock(struct nouveau_memx *memx)
{
- nv_debug(memx->ppwr, " HOST UNBLOCKED\n");
+ nv_debug(memx->pmu, " HOST UNBLOCKED\n");
memx_cmd(memx, MEMX_LEAVE, 0, NULL);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nv108.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nv108.c
similarity index 79%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nv108.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nv108.c
index dacee084a6b2..a7db0870ed88 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nv108.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nv108.c
@@ -26,16 +26,16 @@
#include "fuc/nv108.fuc5.h"
struct nouveau_oclass *
-nv108_pwr_oclass = &(struct nvkm_pwr_impl) {
- .base.handle = NV_SUBDEV(PWR, 0x00),
+nv108_pmu_oclass = &(struct nvkm_pmu_impl) {
+ .base.handle = NV_SUBDEV(PMU, 0x00),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pwr_ctor,
- .dtor = _nouveau_pwr_dtor,
- .init = _nouveau_pwr_init,
- .fini = _nouveau_pwr_fini,
+ .ctor = _nouveau_pmu_ctor,
+ .dtor = _nouveau_pmu_dtor,
+ .init = _nouveau_pmu_init,
+ .fini = _nouveau_pmu_fini,
},
- .code.data = nv108_pwr_code,
- .code.size = sizeof(nv108_pwr_code),
- .data.data = nv108_pwr_data,
- .data.size = sizeof(nv108_pwr_data),
+ .code.data = nv108_pmu_code,
+ .code.size = sizeof(nv108_pmu_code),
+ .data.data = nv108_pmu_data,
+ .data.size = sizeof(nv108_pmu_data),
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nva3.c
similarity index 70%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nva3.c
index f8325a697cd8..06f99283d1a9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nva3.c
@@ -26,25 +26,25 @@
#include "fuc/nva3.fuc3.h"
static int
-nva3_pwr_init(struct nouveau_object *object)
+nva3_pmu_init(struct nouveau_object *object)
{
- struct nouveau_pwr *ppwr = (void *)object;
- nv_mask(ppwr, 0x022210, 0x00000001, 0x00000000);
- nv_mask(ppwr, 0x022210, 0x00000001, 0x00000001);
- return nouveau_pwr_init(ppwr);
+ struct nouveau_pmu *pmu = (void *)object;
+ nv_mask(pmu, 0x022210, 0x00000001, 0x00000000);
+ nv_mask(pmu, 0x022210, 0x00000001, 0x00000001);
+ return nouveau_pmu_init(pmu);
}
struct nouveau_oclass *
-nva3_pwr_oclass = &(struct nvkm_pwr_impl) {
- .base.handle = NV_SUBDEV(PWR, 0xa3),
+nva3_pmu_oclass = &(struct nvkm_pmu_impl) {
+ .base.handle = NV_SUBDEV(PMU, 0xa3),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pwr_ctor,
- .dtor = _nouveau_pwr_dtor,
- .init = nva3_pwr_init,
- .fini = _nouveau_pwr_fini,
+ .ctor = _nouveau_pmu_ctor,
+ .dtor = _nouveau_pmu_dtor,
+ .init = nva3_pmu_init,
+ .fini = _nouveau_pmu_fini,
},
- .code.data = nva3_pwr_code,
- .code.size = sizeof(nva3_pwr_code),
- .data.data = nva3_pwr_data,
- .data.size = sizeof(nva3_pwr_data),
+ .code.data = nva3_pmu_code,
+ .code.size = sizeof(nva3_pmu_code),
+ .data.data = nva3_pmu_data,
+ .data.size = sizeof(nva3_pmu_data),
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nvc0.c
similarity index 79%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nvc0.c
index 669417c23f9c..a9fd1456f5b5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nvc0.c
@@ -26,16 +26,16 @@
#include "fuc/nvc0.fuc3.h"
struct nouveau_oclass *
-nvc0_pwr_oclass = &(struct nvkm_pwr_impl) {
- .base.handle = NV_SUBDEV(PWR, 0xc0),
+nvc0_pmu_oclass = &(struct nvkm_pmu_impl) {
+ .base.handle = NV_SUBDEV(PMU, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pwr_ctor,
- .dtor = _nouveau_pwr_dtor,
- .init = _nouveau_pwr_init,
- .fini = _nouveau_pwr_fini,
+ .ctor = _nouveau_pmu_ctor,
+ .dtor = _nouveau_pmu_dtor,
+ .init = _nouveau_pmu_init,
+ .fini = _nouveau_pmu_fini,
},
- .code.data = nvc0_pwr_code,
- .code.size = sizeof(nvc0_pwr_code),
- .data.data = nvc0_pwr_data,
- .data.size = sizeof(nvc0_pwr_data),
+ .code.data = nvc0_pmu_code,
+ .code.size = sizeof(nvc0_pmu_code),
+ .data.data = nvc0_pmu_data,
+ .data.size = sizeof(nvc0_pmu_data),
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nvd0.c
similarity index 79%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nvd0.c
index d6e33d0a0544..a9b1d7e027a3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/nvd0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nvd0.c
@@ -26,16 +26,16 @@
#include "fuc/nvd0.fuc4.h"
struct nouveau_oclass *
-nvd0_pwr_oclass = &(struct nvkm_pwr_impl) {
- .base.handle = NV_SUBDEV(PWR, 0xd0),
+nvd0_pmu_oclass = &(struct nvkm_pmu_impl) {
+ .base.handle = NV_SUBDEV(PMU, 0xd0),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pwr_ctor,
- .dtor = _nouveau_pwr_dtor,
- .init = _nouveau_pwr_init,
- .fini = _nouveau_pwr_fini,
+ .ctor = _nouveau_pmu_ctor,
+ .dtor = _nouveau_pmu_dtor,
+ .init = _nouveau_pmu_init,
+ .fini = _nouveau_pmu_fini,
},
- .code.data = nvd0_pwr_code,
- .code.size = sizeof(nvd0_pwr_code),
- .data.data = nvd0_pwr_data,
- .data.size = sizeof(nvd0_pwr_data),
+ .code.data = nvd0_pmu_code,
+ .code.size = sizeof(nvd0_pmu_code),
+ .data.data = nvd0_pmu_data,
+ .data.size = sizeof(nvd0_pmu_data),
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h
new file mode 100644
index 000000000000..eb5bd1cb3955
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h
@@ -0,0 +1,45 @@
+#ifndef __NVKM_PMU_PRIV_H__
+#define __NVKM_PMU_PRIV_H__
+
+#include <subdev/pmu.h>
+#include <subdev/pmu/fuc/os.h>
+
+#define nouveau_pmu_create(p, e, o, d) \
+ nouveau_pmu_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nouveau_pmu_destroy(p) \
+ nouveau_subdev_destroy(&(p)->base)
+#define nouveau_pmu_init(p) ({ \
+ struct nouveau_pmu *_pmu = (p); \
+ _nouveau_pmu_init(nv_object(_pmu)); \
+})
+#define nouveau_pmu_fini(p,s) ({ \
+ struct nouveau_pmu *_pmu = (p); \
+ _nouveau_pmu_fini(nv_object(_pmu), (s)); \
+})
+
+int nouveau_pmu_create_(struct nouveau_object *, struct nouveau_object *,
+ struct nouveau_oclass *, int, void **);
+
+int _nouveau_pmu_ctor(struct nouveau_object *, struct nouveau_object *,
+ struct nouveau_oclass *, void *, u32,
+ struct nouveau_object **);
+#define _nouveau_pmu_dtor _nouveau_subdev_dtor
+int _nouveau_pmu_init(struct nouveau_object *);
+int _nouveau_pmu_fini(struct nouveau_object *, bool);
+void nouveau_pmu_pgob(struct nouveau_pmu *pmu, bool enable);
+
+struct nvkm_pmu_impl {
+ struct nouveau_oclass base;
+ struct {
+ u32 *data;
+ u32 size;
+ } code;
+ struct {
+ u32 *data;
+ u32 size;
+ } data;
+
+ void (*pgob)(struct nouveau_pmu *, bool);
+};
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/Kbuild
deleted file mode 100644
index a664886040f4..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/Kbuild
+++ /dev/null
@@ -1,8 +0,0 @@
-nvkm-y += nvkm/subdev/pwr/base.o
-nvkm-y += nvkm/subdev/pwr/memx.o
-nvkm-y += nvkm/subdev/pwr/nva3.o
-nvkm-y += nvkm/subdev/pwr/nvc0.o
-nvkm-y += nvkm/subdev/pwr/nvd0.o
-nvkm-y += nvkm/subdev/pwr/gk104.o
-nvkm-y += nvkm/subdev/pwr/nv108.o
-nvkm-y += nvkm/subdev/pwr/gk20a.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/base.c
deleted file mode 100644
index 1ea433a5e118..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/base.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <subdev/timer.h>
-
-#include "priv.h"
-
-void
-nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable)
-{
- const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr);
- if (impl->pgob)
- impl->pgob(ppwr, enable);
-}
-
-static int
-nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2],
- u32 process, u32 message, u32 data0, u32 data1)
-{
- struct nouveau_subdev *subdev = nv_subdev(ppwr);
- u32 addr;
-
- /* wait for a free slot in the fifo */
- addr = nv_rd32(ppwr, 0x10a4a0);
- if (!nv_wait_ne(ppwr, 0x10a4b0, 0xffffffff, addr ^ 8))
- return -EBUSY;
-
- /* we currently only support a single process at a time waiting
- * on a synchronous reply, take the PPWR mutex and tell the
- * receive handler what we're waiting for
- */
- if (reply) {
- mutex_lock(&subdev->mutex);
- ppwr->recv.message = message;
- ppwr->recv.process = process;
- }
-
- /* acquire data segment access */
- do {
- nv_wr32(ppwr, 0x10a580, 0x00000001);
- } while (nv_rd32(ppwr, 0x10a580) != 0x00000001);
-
- /* write the packet */
- nv_wr32(ppwr, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) +
- ppwr->send.base));
- nv_wr32(ppwr, 0x10a1c4, process);
- nv_wr32(ppwr, 0x10a1c4, message);
- nv_wr32(ppwr, 0x10a1c4, data0);
- nv_wr32(ppwr, 0x10a1c4, data1);
- nv_wr32(ppwr, 0x10a4a0, (addr + 1) & 0x0f);
-
- /* release data segment access */
- nv_wr32(ppwr, 0x10a580, 0x00000000);
-
- /* wait for reply, if requested */
- if (reply) {
- wait_event(ppwr->recv.wait, (ppwr->recv.process == 0));
- reply[0] = ppwr->recv.data[0];
- reply[1] = ppwr->recv.data[1];
- mutex_unlock(&subdev->mutex);
- }
-
- return 0;
-}
-
-static void
-nouveau_pwr_recv(struct work_struct *work)
-{
- struct nouveau_pwr *ppwr =
- container_of(work, struct nouveau_pwr, recv.work);
- u32 process, message, data0, data1;
-
- /* nothing to do if GET == PUT */
- u32 addr = nv_rd32(ppwr, 0x10a4cc);
- if (addr == nv_rd32(ppwr, 0x10a4c8))
- return;
-
- /* acquire data segment access */
- do {
- nv_wr32(ppwr, 0x10a580, 0x00000002);
- } while (nv_rd32(ppwr, 0x10a580) != 0x00000002);
-
- /* read the packet */
- nv_wr32(ppwr, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) +
- ppwr->recv.base));
- process = nv_rd32(ppwr, 0x10a1c4);
- message = nv_rd32(ppwr, 0x10a1c4);
- data0 = nv_rd32(ppwr, 0x10a1c4);
- data1 = nv_rd32(ppwr, 0x10a1c4);
- nv_wr32(ppwr, 0x10a4cc, (addr + 1) & 0x0f);
-
- /* release data segment access */
- nv_wr32(ppwr, 0x10a580, 0x00000000);
-
- /* wake process if it's waiting on a synchronous reply */
- if (ppwr->recv.process) {
- if (process == ppwr->recv.process &&
- message == ppwr->recv.message) {
- ppwr->recv.data[0] = data0;
- ppwr->recv.data[1] = data1;
- ppwr->recv.process = 0;
- wake_up(&ppwr->recv.wait);
- return;
- }
- }
-
- /* right now there's no other expected responses from the engine,
- * so assume that any unexpected message is an error.
- */
- nv_warn(ppwr, "%c%c%c%c 0x%08x 0x%08x 0x%08x 0x%08x\n",
- (char)((process & 0x000000ff) >> 0),
- (char)((process & 0x0000ff00) >> 8),
- (char)((process & 0x00ff0000) >> 16),
- (char)((process & 0xff000000) >> 24),
- process, message, data0, data1);
-}
-
-static void
-nouveau_pwr_intr(struct nouveau_subdev *subdev)
-{
- struct nouveau_pwr *ppwr = (void *)subdev;
- u32 disp = nv_rd32(ppwr, 0x10a01c);
- u32 intr = nv_rd32(ppwr, 0x10a008) & disp & ~(disp >> 16);
-
- if (intr & 0x00000020) {
- u32 stat = nv_rd32(ppwr, 0x10a16c);
- if (stat & 0x80000000) {
- nv_error(ppwr, "UAS fault at 0x%06x addr 0x%08x\n",
- stat & 0x00ffffff, nv_rd32(ppwr, 0x10a168));
- nv_wr32(ppwr, 0x10a16c, 0x00000000);
- intr &= ~0x00000020;
- }
- }
-
- if (intr & 0x00000040) {
- schedule_work(&ppwr->recv.work);
- nv_wr32(ppwr, 0x10a004, 0x00000040);
- intr &= ~0x00000040;
- }
-
- if (intr & 0x00000080) {
- nv_info(ppwr, "wr32 0x%06x 0x%08x\n", nv_rd32(ppwr, 0x10a7a0),
- nv_rd32(ppwr, 0x10a7a4));
- nv_wr32(ppwr, 0x10a004, 0x00000080);
- intr &= ~0x00000080;
- }
-
- if (intr) {
- nv_error(ppwr, "intr 0x%08x\n", intr);
- nv_wr32(ppwr, 0x10a004, intr);
- }
-}
-
-int
-_nouveau_pwr_fini(struct nouveau_object *object, bool suspend)
-{
- struct nouveau_pwr *ppwr = (void *)object;
-
- nv_wr32(ppwr, 0x10a014, 0x00000060);
- flush_work(&ppwr->recv.work);
-
- return nouveau_subdev_fini(&ppwr->base, suspend);
-}
-
-int
-_nouveau_pwr_init(struct nouveau_object *object)
-{
- const struct nvkm_pwr_impl *impl = (void *)object->oclass;
- struct nouveau_pwr *ppwr = (void *)object;
- int ret, i;
-
- ret = nouveau_subdev_init(&ppwr->base);
- if (ret)
- return ret;
-
- nv_subdev(ppwr)->intr = nouveau_pwr_intr;
- ppwr->message = nouveau_pwr_send;
- ppwr->pgob = nouveau_pwr_pgob;
-
- /* prevent previous ucode from running, wait for idle, reset */
- nv_wr32(ppwr, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */
- nv_wait(ppwr, 0x10a04c, 0xffffffff, 0x00000000);
- nv_mask(ppwr, 0x000200, 0x00002000, 0x00000000);
- nv_mask(ppwr, 0x000200, 0x00002000, 0x00002000);
- nv_rd32(ppwr, 0x000200);
- nv_wait(ppwr, 0x10a10c, 0x00000006, 0x00000000);
-
- /* upload data segment */
- nv_wr32(ppwr, 0x10a1c0, 0x01000000);
- for (i = 0; i < impl->data.size / 4; i++)
- nv_wr32(ppwr, 0x10a1c4, impl->data.data[i]);
-
- /* upload code segment */
- nv_wr32(ppwr, 0x10a180, 0x01000000);
- for (i = 0; i < impl->code.size / 4; i++) {
- if ((i & 0x3f) == 0)
- nv_wr32(ppwr, 0x10a188, i >> 6);
- nv_wr32(ppwr, 0x10a184, impl->code.data[i]);
- }
-
- /* start it running */
- nv_wr32(ppwr, 0x10a10c, 0x00000000);
- nv_wr32(ppwr, 0x10a104, 0x00000000);
- nv_wr32(ppwr, 0x10a100, 0x00000002);
-
- /* wait for valid host->pwr ring configuration */
- if (!nv_wait_ne(ppwr, 0x10a4d0, 0xffffffff, 0x00000000))
- return -EBUSY;
- ppwr->send.base = nv_rd32(ppwr, 0x10a4d0) & 0x0000ffff;
- ppwr->send.size = nv_rd32(ppwr, 0x10a4d0) >> 16;
-
- /* wait for valid pwr->host ring configuration */
- if (!nv_wait_ne(ppwr, 0x10a4dc, 0xffffffff, 0x00000000))
- return -EBUSY;
- ppwr->recv.base = nv_rd32(ppwr, 0x10a4dc) & 0x0000ffff;
- ppwr->recv.size = nv_rd32(ppwr, 0x10a4dc) >> 16;
-
- nv_wr32(ppwr, 0x10a010, 0x000000e0);
- return 0;
-}
-
-int
-nouveau_pwr_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int length, void **pobject)
-{
- struct nouveau_pwr *ppwr;
- int ret;
-
- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PPWR",
- "pwr", length, pobject);
- ppwr = *pobject;
- if (ret)
- return ret;
-
- INIT_WORK(&ppwr->recv.work, nouveau_pwr_recv);
- init_waitqueue_head(&ppwr->recv.wait);
- return 0;
-}
-
-int
-_nouveau_pwr_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
-{
- struct nouveau_pwr *ppwr;
- int ret = nouveau_pwr_create(parent, engine, oclass, &ppwr);
- *pobject = nv_object(ppwr);
- return ret;
-}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/priv.h
deleted file mode 100644
index 86149d9a440c..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/priv.h
+++ /dev/null
@@ -1,45 +0,0 @@
-#ifndef __NVKM_PWR_PRIV_H__
-#define __NVKM_PWR_PRIV_H__
-
-#include <subdev/pwr.h>
-#include <subdev/pwr/fuc/os.h>
-
-#define nouveau_pwr_create(p, e, o, d) \
- nouveau_pwr_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_pwr_destroy(p) \
- nouveau_subdev_destroy(&(p)->base)
-#define nouveau_pwr_init(p) ({ \
- struct nouveau_pwr *_ppwr = (p); \
- _nouveau_pwr_init(nv_object(_ppwr)); \
-})
-#define nouveau_pwr_fini(p,s) ({ \
- struct nouveau_pwr *_ppwr = (p); \
- _nouveau_pwr_fini(nv_object(_ppwr), (s)); \
-})
-
-int nouveau_pwr_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-
-int _nouveau_pwr_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-#define _nouveau_pwr_dtor _nouveau_subdev_dtor
-int _nouveau_pwr_init(struct nouveau_object *);
-int _nouveau_pwr_fini(struct nouveau_object *, bool);
-void nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable);
-
-struct nvkm_pwr_impl {
- struct nouveau_oclass base;
- struct {
- u32 *data;
- u32 size;
- } code;
- struct {
- u32 *data;
- u32 size;
- } data;
-
- void (*pgob)(struct nouveau_pwr *, bool);
-};
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
index 9ad01da6eacb..7d4bfd8d5b93 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
@@ -176,7 +176,7 @@ nouveau_therm_fan_mode(struct nouveau_therm *therm, int mode)
/* The default PPWR ucode on fermi interferes with fan management */
if ((mode >= ARRAY_SIZE(name)) ||
(mode != NOUVEAU_THERM_CTRL_NONE && device->card_type >= NV_C0 &&
- !nouveau_subdev(device, NVDEV_SUBDEV_PWR)))
+ !nouveau_subdev(device, NVDEV_SUBDEV_PMU)))
return -EINVAL;
/* do not allow automatic fan management if the thermal sensor is
From 5ce3bf3c72436c49fbd9a5b71d7d278665f4bf55 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 09:57:36 +1000
Subject: [PATCH 39/86] drm/nouveau/mmu: rename from vmmgr (no binary change)
Switch to NVIDIA's name for the device.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/include/nvif/device.h | 4 +-
.../drm/nouveau/include/nvkm/core/device.h | 2 +-
.../drm/nouveau/include/nvkm/core/engctx.h | 2 +-
.../gpu/drm/nouveau/include/nvkm/subdev/fb.h | 2 +-
.../include/nvkm/subdev/{vm.h => mmu.h} | 46 +++---
drivers/gpu/drm/nouveau/nouveau_bo.c | 8 +-
drivers/gpu/drm/nouveau/nouveau_chan.c | 14 +-
drivers/gpu/drm/nouveau/nouveau_display.h | 2 +-
drivers/gpu/drm/nouveau/nouveau_ttm.c | 10 +-
drivers/gpu/drm/nouveau/nvkm/core/engctx.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/copy/nva3.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +-
.../drm/nouveau/nvkm/engine/device/gm100.c | 6 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv04.c | 6 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv10.c | 18 +--
.../gpu/drm/nouveau/nvkm/engine/device/nv20.c | 10 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv30.c | 12 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv40.c | 36 ++---
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 30 ++--
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 20 +--
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 18 +--
.../gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c | 10 +-
.../gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/fifo/nve0.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/graph/nv50.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/graph/nvc0.h | 2 +-
.../gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/bar/base.c | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/bar/nv50.c | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild | 6 +
.../nouveau/nvkm/subdev/{vm => mmu}/base.c | 140 +++++++++---------
.../nouveau/nvkm/subdev/{vm => mmu}/nv04.c | 28 ++--
.../gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h | 19 +++
.../nouveau/nvkm/subdev/{vm => mmu}/nv41.c | 32 ++--
.../nouveau/nvkm/subdev/{vm => mmu}/nv44.c | 36 ++---
.../nouveau/nvkm/subdev/{vm => mmu}/nv50.c | 36 ++---
.../nouveau/nvkm/subdev/{vm => mmu}/nvc0.c | 32 ++--
drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild | 6 -
drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h | 19 ---
43 files changed, 319 insertions(+), 319 deletions(-)
rename drivers/gpu/drm/nouveau/include/nvkm/subdev/{vm.h => mmu.h} (73%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
rename drivers/gpu/drm/nouveau/nvkm/subdev/{vm => mmu}/base.c (73%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{vm => mmu}/nv04.c (86%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h
rename drivers/gpu/drm/nouveau/nvkm/subdev/{vm => mmu}/nv41.c (86%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{vm => mmu}/nv44.c (89%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{vm => mmu}/nv50.c (88%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/{vm => mmu}/nvc0.c (91%)
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h
diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h
index e73a16dd97fa..93acd5153bee 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/device.h
@@ -29,7 +29,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
/*XXX*/
#include <subdev/bios.h>
#include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/gpio.h>
#include <subdev/clk.h>
@@ -40,7 +40,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
#define nvkm_device(a) nv_device(nvkm_object((a)))
#define nvkm_bios(a) nouveau_bios(nvkm_device(a))
#define nvkm_fb(a) nouveau_fb(nvkm_device(a))
-#define nvkm_vmmgr(a) nouveau_vmmgr(nvkm_device(a))
+#define nvkm_mmu(a) nouveau_mmu(nvkm_device(a))
#define nvkm_bar(a) nouveau_bar(nvkm_device(a))
#define nvkm_gpio(a) nouveau_gpio(nvkm_device(a))
#define nvkm_clk(a) nouveau_clk(nvkm_device(a))
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index a2828ac6a65e..82625c5d68d7 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -33,7 +33,7 @@ enum nv_subdev_type {
NVDEV_SUBDEV_FB,
NVDEV_SUBDEV_LTC,
NVDEV_SUBDEV_INSTMEM,
- NVDEV_SUBDEV_VM,
+ NVDEV_SUBDEV_MMU,
NVDEV_SUBDEV_BAR,
NVDEV_SUBDEV_PMU,
NVDEV_SUBDEV_VOLT,
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h
index dbc6a3e6dd44..9d696e4747e7 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h
@@ -4,7 +4,7 @@
#include <core/object.h>
#include <core/gpuobj.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#define NV_ENGCTX_(eng,var) (NV_ENGCTX_CLASS | ((var) << 8) | (eng))
#define NV_ENGCTX(name,var) NV_ENGCTX_(NVDEV_ENGINE_##name, (var))
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
index 889603fbb0cf..0277585c9067 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
@@ -5,7 +5,7 @@
#include <core/device.h>
#include <core/mm.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
/* memory type/access flags, do not match hardware values */
#define NV_MEM_ACCESS_RO 1
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
similarity index 73%
rename from drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h
rename to drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
index d56585f1cd8c..2c3b29967ea4 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/vm.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
@@ -22,8 +22,8 @@
* Authors: Ben Skeggs
*/
-#ifndef __NOUVEAU_VM_H__
-#define __NOUVEAU_VM_H__
+#ifndef __NOUVEAU_MMU_H__
+#define __NOUVEAU_MMU_H__
#include <core/object.h>
#include <core/subdev.h>
@@ -53,7 +53,7 @@ struct nouveau_vma {
};
struct nouveau_vm {
- struct nouveau_vmmgr *vmm;
+ struct nouveau_mmu *mmu;
struct nouveau_mm mm;
struct kref refcount;
@@ -65,7 +65,7 @@ struct nouveau_vm {
u32 lpde;
};
-struct nouveau_vmmgr {
+struct nouveau_mmu {
struct nouveau_subdev base;
u64 limit;
@@ -74,7 +74,7 @@ struct nouveau_vmmgr {
u8 spg_shift;
u8 lpg_shift;
- int (*create)(struct nouveau_vmmgr *, u64 offset, u64 length,
+ int (*create)(struct nouveau_mmu *, u64 offset, u64 length,
u64 mm_offset, struct nouveau_vm **);
void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde,
@@ -88,37 +88,37 @@ struct nouveau_vmmgr {
void (*flush)(struct nouveau_vm *);
};
-static inline struct nouveau_vmmgr *
-nouveau_vmmgr(void *obj)
+static inline struct nouveau_mmu *
+nouveau_mmu(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_VM);
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MMU);
}
-#define nouveau_vmmgr_create(p,e,o,i,f,d) \
+#define nouveau_mmu_create(p,e,o,i,f,d) \
nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d))
-#define nouveau_vmmgr_destroy(p) \
+#define nouveau_mmu_destroy(p) \
nouveau_subdev_destroy(&(p)->base)
-#define nouveau_vmmgr_init(p) \
+#define nouveau_mmu_init(p) \
nouveau_subdev_init(&(p)->base)
-#define nouveau_vmmgr_fini(p,s) \
+#define nouveau_mmu_fini(p,s) \
nouveau_subdev_fini(&(p)->base, (s))
-#define _nouveau_vmmgr_dtor _nouveau_subdev_dtor
-#define _nouveau_vmmgr_init _nouveau_subdev_init
-#define _nouveau_vmmgr_fini _nouveau_subdev_fini
+#define _nouveau_mmu_dtor _nouveau_subdev_dtor
+#define _nouveau_mmu_init _nouveau_subdev_init
+#define _nouveau_mmu_fini _nouveau_subdev_fini
-extern struct nouveau_oclass nv04_vmmgr_oclass;
-extern struct nouveau_oclass nv41_vmmgr_oclass;
-extern struct nouveau_oclass nv44_vmmgr_oclass;
-extern struct nouveau_oclass nv50_vmmgr_oclass;
-extern struct nouveau_oclass nvc0_vmmgr_oclass;
+extern struct nouveau_oclass nv04_mmu_oclass;
+extern struct nouveau_oclass nv41_mmu_oclass;
+extern struct nouveau_oclass nv44_mmu_oclass;
+extern struct nouveau_oclass nv50_mmu_oclass;
+extern struct nouveau_oclass nvc0_mmu_oclass;
-int nv04_vm_create(struct nouveau_vmmgr *, u64, u64, u64,
+int nv04_vm_create(struct nouveau_mmu *, u64, u64, u64,
struct nouveau_vm **);
-void nv04_vmmgr_dtor(struct nouveau_object *);
+void nv04_mmu_dtor(struct nouveau_object *);
/* nouveau_vm.c */
-int nouveau_vm_create(struct nouveau_vmmgr *, u64 offset, u64 length,
+int nouveau_vm_create(struct nouveau_mmu *, u64 offset, u64 length,
u64 mm_offset, u32 block, struct nouveau_vm **);
int nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length,
u64 mm_offset, struct nouveau_vm **);
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index d96fe3524dbd..d2f0929c2d73 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -193,7 +193,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align,
int max_size;
if (drm->client.vm)
- lpg_shift = drm->client.vm->vmm->lpg_shift;
+ lpg_shift = drm->client.vm->mmu->lpg_shift;
max_size = INT_MAX & ~((1 << lpg_shift) - 1);
if (size <= 0 || size > max_size) {
@@ -220,7 +220,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align,
nvbo->page_shift = 12;
if (drm->client.vm) {
if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
- nvbo->page_shift = drm->client.vm->vmm->lpg_shift;
+ nvbo->page_shift = drm->client.vm->mmu->lpg_shift;
}
nouveau_bo_fixup_align(nvbo, flags, &align, &size);
@@ -1240,7 +1240,7 @@ nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
list_for_each_entry(vma, &nvbo->vma_list, head) {
if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
(new_mem->mem_type == TTM_PL_VRAM ||
- nvbo->page_shift != vma->vm->vmm->lpg_shift)) {
+ nvbo->page_shift != vma->vm->mmu->lpg_shift)) {
nouveau_vm_map(vma, new_mem->mm_node);
} else {
nouveau_vm_unmap(vma);
@@ -1639,7 +1639,7 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
(nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
- nvbo->page_shift != vma->vm->vmm->lpg_shift))
+ nvbo->page_shift != vma->vm->mmu->lpg_shift))
nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
list_add_tail(&vma->head, &nvbo->vma_list);
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c
index aff9099aae6c..80302530ead7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_chan.c
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.c
@@ -88,7 +88,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
u32 handle, u32 size, struct nouveau_channel **pchan)
{
struct nouveau_cli *cli = (void *)nvif_client(&device->base);
- struct nouveau_vmmgr *vmm = nvkm_vmmgr(device);
+ struct nouveau_mmu *mmu = nvkm_mmu(device);
struct nv_dma_v0 args = {};
struct nouveau_channel *chan;
u32 target;
@@ -136,7 +136,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
args.target = NV_DMA_V0_TARGET_VM;
args.access = NV_DMA_V0_ACCESS_VM;
args.start = 0;
- args.limit = cli->vm->vmm->limit - 1;
+ args.limit = cli->vm->mmu->limit - 1;
} else
if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
@@ -165,7 +165,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
args.target = NV_DMA_V0_TARGET_VM;
args.access = NV_DMA_V0_ACCESS_RDWR;
args.start = 0;
- args.limit = vmm->limit - 1;
+ args.limit = mmu->limit - 1;
}
}
@@ -281,7 +281,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
{
struct nvif_device *device = chan->device;
struct nouveau_cli *cli = (void *)nvif_client(&device->base);
- struct nouveau_vmmgr *vmm = nvkm_vmmgr(device);
+ struct nouveau_mmu *mmu = nvkm_mmu(device);
struct nouveau_software_chan *swch;
struct nv_dma_v0 args = {};
int ret, i;
@@ -294,7 +294,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
args.target = NV_DMA_V0_TARGET_VM;
args.access = NV_DMA_V0_ACCESS_VM;
args.start = 0;
- args.limit = cli->vm->vmm->limit - 1;
+ args.limit = cli->vm->mmu->limit - 1;
} else {
args.target = NV_DMA_V0_TARGET_VRAM;
args.access = NV_DMA_V0_ACCESS_RDWR;
@@ -312,7 +312,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
args.target = NV_DMA_V0_TARGET_VM;
args.access = NV_DMA_V0_ACCESS_VM;
args.start = 0;
- args.limit = cli->vm->vmm->limit - 1;
+ args.limit = cli->vm->mmu->limit - 1;
} else
if (chan->drm->agp.stat == ENABLED) {
args.target = NV_DMA_V0_TARGET_AGP;
@@ -324,7 +324,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
args.target = NV_DMA_V0_TARGET_VM;
args.access = NV_DMA_V0_ACCESS_RDWR;
args.start = 0;
- args.limit = vmm->limit - 1;
+ args.limit = mmu->limit - 1;
}
ret = nvif_object_init(chan->object, NULL, gart,
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h
index be3d5947c6be..a94dcdaccf59 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.h
+++ b/drivers/gpu/drm/nouveau/nouveau_display.h
@@ -1,7 +1,7 @@
#ifndef __NOUVEAU_DISPLAY_H__
#define __NOUVEAU_DISPLAY_H__
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include "nouveau_drm.h"
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index 2e0d1d998ca6..aa8321706103 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -203,13 +203,13 @@ const struct ttm_mem_type_manager_func nouveau_gart_manager = {
};
/*XXX*/
-#include <subdev/vm/nv04.h>
+#include <subdev/mmu/nv04.h>
static int
nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
struct nouveau_drm *drm = nouveau_bdev(man->bdev);
- struct nouveau_vmmgr *vmm = nvkm_vmmgr(&drm->device);
- struct nv04_vmmgr_priv *priv = (void *)vmm;
+ struct nouveau_mmu *mmu = nvkm_mmu(&drm->device);
+ struct nv04_mmu_priv *priv = (void *)mmu;
struct nouveau_vm *vm = NULL;
nouveau_vm_ref(priv->vm, &vm, NULL);
man->priv = vm;
@@ -354,7 +354,7 @@ nouveau_ttm_init(struct nouveau_drm *drm)
u32 bits;
int ret;
- bits = nvkm_vmmgr(&drm->device)->dma_bits;
+ bits = nvkm_mmu(&drm->device)->dma_bits;
if (nv_device_is_pci(nvkm_device(&drm->device))) {
if (drm->agp.stat == ENABLED ||
!pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits)))
@@ -401,7 +401,7 @@ nouveau_ttm_init(struct nouveau_drm *drm)
/* GART init */
if (drm->agp.stat != ENABLED) {
- drm->gem.gart_available = nvkm_vmmgr(&drm->device)->limit;
+ drm->gem.gart_available = nvkm_mmu(&drm->device)->limit;
} else {
drm->gem.gart_available = drm->agp.size;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
index 16f09b1280dc..892baa461575 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
@@ -28,7 +28,7 @@
#include <core/client.h>
#include <core/engctx.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
static inline int
nouveau_engctx_exists(struct nouveau_object *parent,
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
index 0fa64576b8d6..68a4232d35cc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
@@ -27,7 +27,7 @@
#include <subdev/instmem.h>
#include <subdev/bar.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
void
nouveau_gpuobj_destroy(struct nouveau_gpuobj *gpuobj)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c
index 13c05e09ff87..6ae64969e2e5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c
@@ -27,7 +27,7 @@
#include <engine/copy.h>
#include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <core/client.h>
#include <core/enum.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index e141dff31553..eb9f387d7356 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -218,7 +218,7 @@ static const u64 disable_map[] = {
[NVDEV_SUBDEV_LTC] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_IBUS] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_V0_DISABLE_CORE,
- [NVDEV_SUBDEV_VM] = NV_DEVICE_V0_DISABLE_CORE,
+ [NVDEV_SUBDEV_MMU] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_BAR] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_VOLT] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_THERM] = NV_DEVICE_V0_DISABLE_CORE,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 763572fcb7d4..130d225377ee 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -37,7 +37,7 @@
#include <subdev/ltc.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/pmu.h>
#include <subdev/volt.h>
@@ -75,7 +75,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
@@ -119,7 +119,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
#if 0
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index dff51984ea94..7f98385acec7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -31,7 +31,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <engine/device.h>
#include <engine/dmaobj.h>
@@ -55,7 +55,7 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
@@ -73,7 +73,7 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index af63f5b95f01..6a7ece0fc789 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -32,7 +32,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <engine/device.h>
#include <engine/dmaobj.h>
@@ -57,7 +57,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -74,7 +74,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -93,7 +93,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -112,7 +112,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -131,7 +131,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -150,7 +150,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -169,7 +169,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -188,7 +188,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index eddeb126c7ec..e3b17fde89e6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -33,7 +33,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <engine/device.h>
#include <engine/dmaobj.h>
@@ -58,7 +58,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -77,7 +77,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -96,7 +96,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -115,7 +115,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index 6fe2d130a2ce..8f67f4d402d7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -32,7 +32,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <engine/device.h>
#include <engine/dmaobj.h>
@@ -58,7 +58,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -77,7 +77,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -96,7 +96,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -116,7 +116,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
@@ -136,7 +136,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index d85edd87cec8..49c68d7c093c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -24,7 +24,7 @@
#include <subdev/bios.h>
#include <subdev/bus.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/clk.h>
@@ -34,7 +34,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <subdev/volt.h>
#include <engine/device.h>
@@ -63,7 +63,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -86,7 +86,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -109,7 +109,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -132,7 +132,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -155,7 +155,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -178,7 +178,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -201,7 +201,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -224,7 +224,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -247,7 +247,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -270,7 +270,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -293,7 +293,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -316,7 +316,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -339,7 +339,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -362,7 +362,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -385,7 +385,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -408,7 +408,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 867b79a0679a..f9afee4f844d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -35,7 +35,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/pmu.h>
#include <subdev/volt.h>
@@ -73,7 +73,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -99,7 +99,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -128,7 +128,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -157,7 +157,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -186,7 +186,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -215,7 +215,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -244,7 +244,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -273,7 +273,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -302,7 +302,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -331,7 +331,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@@ -360,7 +360,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -391,7 +391,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -421,7 +421,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -451,7 +451,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index d54d6ac4cea5..0db51092732a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -37,7 +37,7 @@
#include <subdev/ltc.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/pmu.h>
#include <subdev/volt.h>
@@ -75,7 +75,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -108,7 +108,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -141,7 +141,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -173,7 +173,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -206,7 +206,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -238,7 +238,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -270,7 +270,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -303,7 +303,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -335,7 +335,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 39b3fe32b9fb..a565bc8b6636 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -37,7 +37,7 @@
#include <subdev/ltc.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/pmu.h>
#include <subdev/volt.h>
@@ -75,7 +75,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -109,7 +109,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -143,7 +143,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -171,7 +171,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
@@ -199,7 +199,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -233,7 +233,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -267,7 +267,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -300,7 +300,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
index 20c9dbfe3b2e..8089310f1157 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
@@ -26,7 +26,7 @@
#include <nvif/class.h>
#include <subdev/fb.h>
-#include <subdev/vm/nv04.h>
+#include <subdev/mmu/nv04.h>
#include "priv.h"
@@ -62,8 +62,8 @@ nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
}
if (priv->clone) {
- struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaobj);
- struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0];
+ struct nv04_mmu_priv *mmu = nv04_mmu(dmaobj);
+ struct nouveau_gpuobj *pgt = mmu->vm->pgt[0].obj[0];
if (!dmaobj->start)
return nouveau_gpuobj_dup(parent, pgt, pgpuobj);
offset = nv_ro32(pgt, 8 + (offset >> 10));
@@ -88,7 +88,7 @@ nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_object **pobject)
{
struct nouveau_dmaeng *dmaeng = (void *)engine;
- struct nv04_vmmgr_priv *vmm = nv04_vmmgr(engine);
+ struct nv04_mmu_priv *mmu = nv04_mmu(engine);
struct nv04_dmaobj_priv *priv;
int ret;
@@ -98,7 +98,7 @@ nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
if (priv->base.target == NV_MEM_TARGET_VM) {
- if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass)
+ if (nv_object(mmu)->oclass == &nv04_mmu_oclass)
priv->clone = true;
priv->base.target = NV_MEM_TARGET_PCI;
priv->base.access = NV_MEM_ACCESS_RW;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
index e8ef8cb058cd..e5d1e969945e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
@@ -35,7 +35,7 @@
#include <subdev/timer.h>
#include <subdev/bar.h>
#include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
index c9c168035b4d..bf2b9e2df3d0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
@@ -35,7 +35,7 @@
#include <subdev/timer.h>
#include <subdev/bar.h>
#include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <engine/dmaobj.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c
index 38e0aa26f1cd..896e17b56f45 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c
@@ -29,7 +29,7 @@
#include <core/enum.h>
#include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <subdev/timer.h>
#include <engine/fifo.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h
index 7ed9e89c3435..86b7735242e1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h
@@ -34,7 +34,7 @@
#include <nvif/class.h>
#include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/timer.h>
#include <subdev/mc.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
index cae33f86b11a..b62c301b31a1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
@@ -25,7 +25,7 @@
#include <core/os.h>
#include <core/engctx.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/timer.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c
index e9cc8b116a24..97c8343e1a08 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c
@@ -25,7 +25,7 @@
#include <core/os.h>
#include <core/engctx.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/timer.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
index 55090f73bab4..dbcea4930a1d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
@@ -15,5 +15,5 @@ include $(src)/nvkm/subdev/mxm/Kbuild
include $(src)/nvkm/subdev/pmu/Kbuild
include $(src)/nvkm/subdev/therm/Kbuild
include $(src)/nvkm/subdev/timer/Kbuild
-include $(src)/nvkm/subdev/vm/Kbuild
+include $(src)/nvkm/subdev/mmu/Kbuild
include $(src)/nvkm/subdev/volt/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
index 188c638411b2..1b37afe4a4ea 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
@@ -25,7 +25,7 @@
#include <core/object.h>
#include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include "priv.h"
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
index f748ba49dfc8..6d0dd6a01e64 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
@@ -26,7 +26,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include "priv.h"
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c
index 8320ee0509c3..c7ac57ba8e35 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c
@@ -26,7 +26,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include "priv.h"
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
new file mode 100644
index 000000000000..729e27f2cbd4
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
@@ -0,0 +1,6 @@
+nvkm-y += nvkm/subdev/mmu/base.o
+nvkm-y += nvkm/subdev/mmu/nv04.o
+nvkm-y += nvkm/subdev/mmu/nv41.o
+nvkm-y += nvkm/subdev/mmu/nv44.o
+nvkm-y += nvkm/subdev/mmu/nv50.o
+nvkm-y += nvkm/subdev/mmu/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
similarity index 73%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
index f75a683bd47a..e3cb186c440b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
@@ -26,20 +26,20 @@
#include <core/mm.h>
#include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
void
nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
{
struct nouveau_vm *vm = vma->vm;
- struct nouveau_vmmgr *vmm = vm->vmm;
+ struct nouveau_mmu *mmu = vm->mmu;
struct nouveau_mm_node *r;
- int big = vma->node->type != vmm->spg_shift;
+ int big = vma->node->type != mmu->spg_shift;
u32 offset = vma->node->offset + (delta >> 12);
u32 bits = vma->node->type - 12;
- u32 pde = (offset >> vmm->pgt_bits) - vm->fpde;
- u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits;
- u32 max = 1 << (vmm->pgt_bits - bits);
+ u32 pde = (offset >> mmu->pgt_bits) - vm->fpde;
+ u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
+ u32 max = 1 << (mmu->pgt_bits - bits);
u32 end, len;
delta = 0;
@@ -55,7 +55,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
end = max;
len = end - pte;
- vmm->map(vma, pgt, node, pte, len, phys, delta);
+ mmu->map(vma, pgt, node, pte, len, phys, delta);
num -= len;
pte += len;
@@ -69,7 +69,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
}
}
- vmm->flush(vm);
+ mmu->flush(vm);
}
static void
@@ -77,14 +77,14 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
struct nouveau_mem *mem)
{
struct nouveau_vm *vm = vma->vm;
- struct nouveau_vmmgr *vmm = vm->vmm;
- int big = vma->node->type != vmm->spg_shift;
+ struct nouveau_mmu *mmu = vm->mmu;
+ int big = vma->node->type != mmu->spg_shift;
u32 offset = vma->node->offset + (delta >> 12);
u32 bits = vma->node->type - 12;
u32 num = length >> vma->node->type;
- u32 pde = (offset >> vmm->pgt_bits) - vm->fpde;
- u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits;
- u32 max = 1 << (vmm->pgt_bits - bits);
+ u32 pde = (offset >> mmu->pgt_bits) - vm->fpde;
+ u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
+ u32 max = 1 << (mmu->pgt_bits - bits);
unsigned m, sglen;
u32 end, len;
int i;
@@ -102,7 +102,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
for (m = 0; m < len; m++) {
dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
- vmm->map_sg(vma, pgt, mem, pte, 1, &addr);
+ mmu->map_sg(vma, pgt, mem, pte, 1, &addr);
num--;
pte++;
@@ -117,7 +117,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
for (; m < sglen; m++) {
dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
- vmm->map_sg(vma, pgt, mem, pte, 1, &addr);
+ mmu->map_sg(vma, pgt, mem, pte, 1, &addr);
num--;
pte++;
if (num == 0)
@@ -127,7 +127,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
}
finish:
- vmm->flush(vm);
+ mmu->flush(vm);
}
static void
@@ -135,15 +135,15 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
struct nouveau_mem *mem)
{
struct nouveau_vm *vm = vma->vm;
- struct nouveau_vmmgr *vmm = vm->vmm;
+ struct nouveau_mmu *mmu = vm->mmu;
dma_addr_t *list = mem->pages;
- int big = vma->node->type != vmm->spg_shift;
+ int big = vma->node->type != mmu->spg_shift;
u32 offset = vma->node->offset + (delta >> 12);
u32 bits = vma->node->type - 12;
u32 num = length >> vma->node->type;
- u32 pde = (offset >> vmm->pgt_bits) - vm->fpde;
- u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits;
- u32 max = 1 << (vmm->pgt_bits - bits);
+ u32 pde = (offset >> mmu->pgt_bits) - vm->fpde;
+ u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
+ u32 max = 1 << (mmu->pgt_bits - bits);
u32 end, len;
while (num) {
@@ -154,7 +154,7 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
end = max;
len = end - pte;
- vmm->map_sg(vma, pgt, mem, pte, len, list);
+ mmu->map_sg(vma, pgt, mem, pte, len, list);
num -= len;
pte += len;
@@ -165,7 +165,7 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
}
}
- vmm->flush(vm);
+ mmu->flush(vm);
}
void
@@ -184,14 +184,14 @@ void
nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
{
struct nouveau_vm *vm = vma->vm;
- struct nouveau_vmmgr *vmm = vm->vmm;
- int big = vma->node->type != vmm->spg_shift;
+ struct nouveau_mmu *mmu = vm->mmu;
+ int big = vma->node->type != mmu->spg_shift;
u32 offset = vma->node->offset + (delta >> 12);
u32 bits = vma->node->type - 12;
u32 num = length >> vma->node->type;
- u32 pde = (offset >> vmm->pgt_bits) - vm->fpde;
- u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits;
- u32 max = 1 << (vmm->pgt_bits - bits);
+ u32 pde = (offset >> mmu->pgt_bits) - vm->fpde;
+ u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
+ u32 max = 1 << (mmu->pgt_bits - bits);
u32 end, len;
while (num) {
@@ -202,7 +202,7 @@ nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
end = max;
len = end - pte;
- vmm->unmap(pgt, pte, len);
+ mmu->unmap(pgt, pte, len);
num -= len;
pte += len;
@@ -212,7 +212,7 @@ nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
}
}
- vmm->flush(vm);
+ mmu->flush(vm);
}
void
@@ -224,7 +224,7 @@ nouveau_vm_unmap(struct nouveau_vma *vma)
static void
nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde)
{
- struct nouveau_vmmgr *vmm = vm->vmm;
+ struct nouveau_mmu *mmu = vm->mmu;
struct nouveau_vm_pgd *vpgd;
struct nouveau_vm_pgt *vpgt;
struct nouveau_gpuobj *pgt;
@@ -239,47 +239,47 @@ nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde)
vpgt->obj[big] = NULL;
list_for_each_entry(vpgd, &vm->pgd_list, head) {
- vmm->map_pgt(vpgd->obj, pde, vpgt->obj);
+ mmu->map_pgt(vpgd->obj, pde, vpgt->obj);
}
- mutex_unlock(&nv_subdev(vmm)->mutex);
+ mutex_unlock(&nv_subdev(mmu)->mutex);
nouveau_gpuobj_ref(NULL, &pgt);
- mutex_lock(&nv_subdev(vmm)->mutex);
+ mutex_lock(&nv_subdev(mmu)->mutex);
}
}
static int
nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
{
- struct nouveau_vmmgr *vmm = vm->vmm;
+ struct nouveau_mmu *mmu = vm->mmu;
struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
struct nouveau_vm_pgd *vpgd;
struct nouveau_gpuobj *pgt;
- int big = (type != vmm->spg_shift);
+ int big = (type != mmu->spg_shift);
u32 pgt_size;
int ret;
- pgt_size = (1 << (vmm->pgt_bits + 12)) >> type;
+ pgt_size = (1 << (mmu->pgt_bits + 12)) >> type;
pgt_size *= 8;
- mutex_unlock(&nv_subdev(vmm)->mutex);
- ret = nouveau_gpuobj_new(nv_object(vm->vmm), NULL, pgt_size, 0x1000,
+ mutex_unlock(&nv_subdev(mmu)->mutex);
+ ret = nouveau_gpuobj_new(nv_object(vm->mmu), NULL, pgt_size, 0x1000,
NVOBJ_FLAG_ZERO_ALLOC, &pgt);
- mutex_lock(&nv_subdev(vmm)->mutex);
+ mutex_lock(&nv_subdev(mmu)->mutex);
if (unlikely(ret))
return ret;
/* someone beat us to filling the PDE while we didn't have the lock */
if (unlikely(vpgt->refcount[big]++)) {
- mutex_unlock(&nv_subdev(vmm)->mutex);
+ mutex_unlock(&nv_subdev(mmu)->mutex);
nouveau_gpuobj_ref(NULL, &pgt);
- mutex_lock(&nv_subdev(vmm)->mutex);
+ mutex_lock(&nv_subdev(mmu)->mutex);
return 0;
}
vpgt->obj[big] = pgt;
list_for_each_entry(vpgd, &vm->pgd_list, head) {
- vmm->map_pgt(vpgd->obj, pde, vpgt->obj);
+ mmu->map_pgt(vpgd->obj, pde, vpgt->obj);
}
return 0;
@@ -289,26 +289,26 @@ int
nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
u32 access, struct nouveau_vma *vma)
{
- struct nouveau_vmmgr *vmm = vm->vmm;
+ struct nouveau_mmu *mmu = vm->mmu;
u32 align = (1 << page_shift) >> 12;
u32 msize = size >> 12;
u32 fpde, lpde, pde;
int ret;
- mutex_lock(&nv_subdev(vmm)->mutex);
+ mutex_lock(&nv_subdev(mmu)->mutex);
ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align,
&vma->node);
if (unlikely(ret != 0)) {
- mutex_unlock(&nv_subdev(vmm)->mutex);
+ mutex_unlock(&nv_subdev(mmu)->mutex);
return ret;
}
- fpde = (vma->node->offset >> vmm->pgt_bits);
- lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits;
+ fpde = (vma->node->offset >> mmu->pgt_bits);
+ lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits;
for (pde = fpde; pde <= lpde; pde++) {
struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
- int big = (vma->node->type != vmm->spg_shift);
+ int big = (vma->node->type != mmu->spg_shift);
if (likely(vpgt->refcount[big])) {
vpgt->refcount[big]++;
@@ -320,11 +320,11 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
if (pde != fpde)
nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1);
nouveau_mm_free(&vm->mm, &vma->node);
- mutex_unlock(&nv_subdev(vmm)->mutex);
+ mutex_unlock(&nv_subdev(mmu)->mutex);
return ret;
}
}
- mutex_unlock(&nv_subdev(vmm)->mutex);
+ mutex_unlock(&nv_subdev(mmu)->mutex);
vma->vm = NULL;
nouveau_vm_ref(vm, &vma->vm, NULL);
@@ -337,24 +337,24 @@ void
nouveau_vm_put(struct nouveau_vma *vma)
{
struct nouveau_vm *vm = vma->vm;
- struct nouveau_vmmgr *vmm = vm->vmm;
+ struct nouveau_mmu *mmu = vm->mmu;
u32 fpde, lpde;
if (unlikely(vma->node == NULL))
return;
- fpde = (vma->node->offset >> vmm->pgt_bits);
- lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits;
+ fpde = (vma->node->offset >> mmu->pgt_bits);
+ lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits;
- mutex_lock(&nv_subdev(vmm)->mutex);
- nouveau_vm_unmap_pgt(vm, vma->node->type != vmm->spg_shift, fpde, lpde);
+ mutex_lock(&nv_subdev(mmu)->mutex);
+ nouveau_vm_unmap_pgt(vm, vma->node->type != mmu->spg_shift, fpde, lpde);
nouveau_mm_free(&vm->mm, &vma->node);
- mutex_unlock(&nv_subdev(vmm)->mutex);
+ mutex_unlock(&nv_subdev(mmu)->mutex);
nouveau_vm_ref(NULL, &vma->vm, NULL);
}
int
-nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
+nouveau_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
u64 mm_offset, u32 block, struct nouveau_vm **pvm)
{
struct nouveau_vm *vm;
@@ -366,10 +366,10 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
return -ENOMEM;
INIT_LIST_HEAD(&vm->pgd_list);
- vm->vmm = vmm;
+ vm->mmu = mmu;
kref_init(&vm->refcount);
- vm->fpde = offset >> (vmm->pgt_bits + 12);
- vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12);
+ vm->fpde = offset >> (mmu->pgt_bits + 12);
+ vm->lpde = (offset + length - 1) >> (mmu->pgt_bits + 12);
vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt));
if (!vm->pgt) {
@@ -394,14 +394,14 @@ int
nouveau_vm_new(struct nouveau_device *device, u64 offset, u64 length,
u64 mm_offset, struct nouveau_vm **pvm)
{
- struct nouveau_vmmgr *vmm = nouveau_vmmgr(device);
- return vmm->create(vmm, offset, length, mm_offset, pvm);
+ struct nouveau_mmu *mmu = nouveau_mmu(device);
+ return mmu->create(mmu, offset, length, mm_offset, pvm);
}
static int
nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
{
- struct nouveau_vmmgr *vmm = vm->vmm;
+ struct nouveau_mmu *mmu = vm->mmu;
struct nouveau_vm_pgd *vpgd;
int i;
@@ -414,25 +414,25 @@ nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
nouveau_gpuobj_ref(pgd, &vpgd->obj);
- mutex_lock(&nv_subdev(vmm)->mutex);
+ mutex_lock(&nv_subdev(mmu)->mutex);
for (i = vm->fpde; i <= vm->lpde; i++)
- vmm->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj);
+ mmu->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj);
list_add(&vpgd->head, &vm->pgd_list);
- mutex_unlock(&nv_subdev(vmm)->mutex);
+ mutex_unlock(&nv_subdev(mmu)->mutex);
return 0;
}
static void
nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd)
{
- struct nouveau_vmmgr *vmm = vm->vmm;
+ struct nouveau_mmu *mmu = vm->mmu;
struct nouveau_vm_pgd *vpgd, *tmp;
struct nouveau_gpuobj *pgd = NULL;
if (!mpgd)
return;
- mutex_lock(&nv_subdev(vmm)->mutex);
+ mutex_lock(&nv_subdev(mmu)->mutex);
list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) {
if (vpgd->obj == mpgd) {
pgd = vpgd->obj;
@@ -441,7 +441,7 @@ nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd)
break;
}
}
- mutex_unlock(&nv_subdev(vmm)->mutex);
+ mutex_unlock(&nv_subdev(mmu)->mutex);
nouveau_gpuobj_ref(NULL, &pgd);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
similarity index 86%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
index ed45437167f2..a317d8f13570 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
@@ -70,26 +70,26 @@ nv04_vm_flush(struct nouveau_vm *vm)
******************************************************************************/
int
-nv04_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, u64 mmstart,
+nv04_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, u64 mmstart,
struct nouveau_vm **pvm)
{
return -EINVAL;
}
/*******************************************************************************
- * VMMGR subdev
+ * MMU subdev
******************************************************************************/
static int
-nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv04_vmmgr_priv *priv;
+ struct nv04_mmu_priv *priv;
struct nouveau_gpuobj *dma;
int ret;
- ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIGART",
+ ret = nouveau_mmu_create(parent, engine, oclass, "PCIGART",
"pcigart", &priv);
*pobject = nv_object(priv);
if (ret)
@@ -125,9 +125,9 @@ nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
void
-nv04_vmmgr_dtor(struct nouveau_object *object)
+nv04_mmu_dtor(struct nouveau_object *object)
{
- struct nv04_vmmgr_priv *priv = (void *)object;
+ struct nv04_mmu_priv *priv = (void *)object;
if (priv->vm) {
nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]);
nouveau_vm_ref(NULL, &priv->vm, NULL);
@@ -136,16 +136,16 @@ nv04_vmmgr_dtor(struct nouveau_object *object)
pci_free_consistent(nv_device(priv)->pdev, 16 * 1024,
priv->nullp, priv->null);
}
- nouveau_vmmgr_destroy(&priv->base);
+ nouveau_mmu_destroy(&priv->base);
}
struct nouveau_oclass
-nv04_vmmgr_oclass = {
- .handle = NV_SUBDEV(VM, 0x04),
+nv04_mmu_oclass = {
+ .handle = NV_SUBDEV(MMU, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv04_vmmgr_ctor,
- .dtor = nv04_vmmgr_dtor,
- .init = _nouveau_vmmgr_init,
- .fini = _nouveau_vmmgr_fini,
+ .ctor = nv04_mmu_ctor,
+ .dtor = nv04_mmu_dtor,
+ .init = _nouveau_mmu_init,
+ .fini = _nouveau_mmu_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h
new file mode 100644
index 000000000000..919b254ef6a1
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h
@@ -0,0 +1,19 @@
+#ifndef __NV04_MMU_PRIV__
+#define __NV04_MMU_PRIV__
+
+#include <subdev/mmu.h>
+
+struct nv04_mmu_priv {
+ struct nouveau_mmu base;
+ struct nouveau_vm *vm;
+ dma_addr_t null;
+ void *nullp;
+};
+
+static inline struct nv04_mmu_priv *
+nv04_mmu(void *obj)
+{
+ return (void *)nouveau_mmu(obj);
+}
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
similarity index 86%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
index 064c76262876..61af036f1252 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv41.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
@@ -26,7 +26,7 @@
#include <core/option.h>
#include <subdev/timer.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include "nv04.h"
@@ -67,7 +67,7 @@ nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
static void
nv41_vm_flush(struct nouveau_vm *vm)
{
- struct nv04_vmmgr_priv *priv = (void *)vm->vmm;
+ struct nv04_mmu_priv *priv = (void *)vm->mmu;
mutex_lock(&nv_subdev(priv)->mutex);
nv_wr32(priv, 0x100810, 0x00000022);
@@ -80,25 +80,25 @@ nv41_vm_flush(struct nouveau_vm *vm)
}
/*******************************************************************************
- * VMMGR subdev
+ * MMU subdev
******************************************************************************/
static int
-nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_device *device = nv_device(parent);
- struct nv04_vmmgr_priv *priv;
+ struct nv04_mmu_priv *priv;
int ret;
if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
!nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
- return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass,
+ return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass,
data, size, pobject);
}
- ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART",
+ ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART",
"pciegart", &priv);
*pobject = nv_object(priv);
if (ret)
@@ -131,13 +131,13 @@ nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
static int
-nv41_vmmgr_init(struct nouveau_object *object)
+nv41_mmu_init(struct nouveau_object *object)
{
- struct nv04_vmmgr_priv *priv = (void *)object;
+ struct nv04_mmu_priv *priv = (void *)object;
struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0];
int ret;
- ret = nouveau_vmmgr_init(&priv->base);
+ ret = nouveau_mmu_init(&priv->base);
if (ret)
return ret;
@@ -148,12 +148,12 @@ nv41_vmmgr_init(struct nouveau_object *object)
}
struct nouveau_oclass
-nv41_vmmgr_oclass = {
- .handle = NV_SUBDEV(VM, 0x41),
+nv41_mmu_oclass = {
+ .handle = NV_SUBDEV(MMU, 0x41),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv41_vmmgr_ctor,
- .dtor = nv04_vmmgr_dtor,
- .init = nv41_vmmgr_init,
- .fini = _nouveau_vmmgr_fini,
+ .ctor = nv41_mmu_ctor,
+ .dtor = nv04_mmu_dtor,
+ .init = nv41_mmu_init,
+ .fini = _nouveau_mmu_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
similarity index 89%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
index fae1f67d5948..f5319e3e7fe5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv44.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
@@ -26,7 +26,7 @@
#include <core/option.h>
#include <subdev/timer.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include "nv04.h"
@@ -87,7 +87,7 @@ static void
nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
- struct nv04_vmmgr_priv *priv = (void *)vma->vm->vmm;
+ struct nv04_mmu_priv *priv = (void *)vma->vm->mmu;
u32 tmp[4];
int i;
@@ -117,7 +117,7 @@ nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
static void
nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
{
- struct nv04_vmmgr_priv *priv = (void *)nouveau_vmmgr(pgt);
+ struct nv04_mmu_priv *priv = (void *)nouveau_mmu(pgt);
if (pte & 3) {
u32 max = 4 - (pte & 3);
@@ -142,7 +142,7 @@ nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
static void
nv44_vm_flush(struct nouveau_vm *vm)
{
- struct nv04_vmmgr_priv *priv = (void *)vm->vmm;
+ struct nv04_mmu_priv *priv = (void *)vm->mmu;
nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE);
nv_wr32(priv, 0x100808, 0x00000020);
if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001))
@@ -151,25 +151,25 @@ nv44_vm_flush(struct nouveau_vm *vm)
}
/*******************************************************************************
- * VMMGR subdev
+ * MMU subdev
******************************************************************************/
static int
-nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_device *device = nv_device(parent);
- struct nv04_vmmgr_priv *priv;
+ struct nv04_mmu_priv *priv;
int ret;
if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
!nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
- return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass,
+ return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass,
data, size, pobject);
}
- ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART",
+ ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART",
"pciegart", &priv);
*pobject = nv_object(priv);
if (ret)
@@ -208,14 +208,14 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
static int
-nv44_vmmgr_init(struct nouveau_object *object)
+nv44_mmu_init(struct nouveau_object *object)
{
- struct nv04_vmmgr_priv *priv = (void *)object;
+ struct nv04_mmu_priv *priv = (void *)object;
struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0];
u32 addr;
int ret;
- ret = nouveau_vmmgr_init(&priv->base);
+ ret = nouveau_mmu_init(&priv->base);
if (ret)
return ret;
@@ -238,12 +238,12 @@ nv44_vmmgr_init(struct nouveau_object *object)
}
struct nouveau_oclass
-nv44_vmmgr_oclass = {
- .handle = NV_SUBDEV(VM, 0x44),
+nv44_mmu_oclass = {
+ .handle = NV_SUBDEV(MMU, 0x44),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv44_vmmgr_ctor,
- .dtor = nv04_vmmgr_dtor,
- .init = nv44_vmmgr_init,
- .fini = _nouveau_vmmgr_fini,
+ .ctor = nv44_mmu_ctor,
+ .dtor = nv04_mmu_dtor,
+ .init = nv44_mmu_init,
+ .fini = _nouveau_mmu_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
similarity index 88%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
index a4aa81a2173b..6ddc65dc684d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
@@ -28,10 +28,10 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/bar.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
-struct nv50_vmmgr_priv {
- struct nouveau_vmmgr base;
+struct nv50_mmu_priv {
+ struct nouveau_mmu base;
};
static void
@@ -86,8 +86,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
/* IGPs don't have real VRAM, re-target to stolen system memory */
target = 0;
- if (nouveau_fb(vma->vm->vmm)->ram->stolen) {
- phys += nouveau_fb(vma->vm->vmm)->ram->stolen;
+ if (nouveau_fb(vma->vm->mmu)->ram->stolen) {
+ phys += nouveau_fb(vma->vm->mmu)->ram->stolen;
target = 3;
}
@@ -151,7 +151,7 @@ nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
static void
nv50_vm_flush(struct nouveau_vm *vm)
{
- struct nv50_vmmgr_priv *priv = (void *)vm->vmm;
+ struct nv50_mmu_priv *priv = (void *)vm->mmu;
struct nouveau_bar *bar = nouveau_bar(priv);
struct nouveau_engine *engine;
int i, vme;
@@ -191,25 +191,25 @@ nv50_vm_flush(struct nouveau_vm *vm)
}
static int
-nv50_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
+nv50_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
u64 mm_offset, struct nouveau_vm **pvm)
{
- u32 block = (1 << (vmm->pgt_bits + 12));
+ u32 block = (1 << (mmu->pgt_bits + 12));
if (block > length)
block = length;
- return nouveau_vm_create(vmm, offset, length, mm_offset, block, pvm);
+ return nouveau_vm_create(mmu, offset, length, mm_offset, block, pvm);
}
static int
-nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv50_vmmgr_priv *priv;
+ struct nv50_mmu_priv *priv;
int ret;
- ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv);
+ ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -229,12 +229,12 @@ nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
struct nouveau_oclass
-nv50_vmmgr_oclass = {
- .handle = NV_SUBDEV(VM, 0x50),
+nv50_mmu_oclass = {
+ .handle = NV_SUBDEV(MMU, 0x50),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv50_vmmgr_ctor,
- .dtor = _nouveau_vmmgr_dtor,
- .init = _nouveau_vmmgr_init,
- .fini = _nouveau_vmmgr_fini,
+ .ctor = nv50_mmu_ctor,
+ .dtor = _nouveau_mmu_dtor,
+ .init = _nouveau_mmu_init,
+ .fini = _nouveau_mmu_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c
similarity index 91%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c
index c0a3389204fa..bd695c59aac7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c
@@ -27,12 +27,12 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
-#include <subdev/vm.h>
+#include <subdev/mmu.h>
#include <subdev/ltc.h>
#include <subdev/bar.h>
-struct nvc0_vmmgr_priv {
- struct nouveau_vmmgr base;
+struct nvc0_mmu_priv {
+ struct nouveau_mmu base;
};
@@ -116,7 +116,7 @@ nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
pte <<= 3;
if (mem->tag) {
- struct nouveau_ltc *ltc = nouveau_ltc(vma->vm->vmm);
+ struct nouveau_ltc *ltc = nouveau_ltc(vma->vm->mmu);
u32 tag = mem->tag->offset + (delta >> 17);
phys |= (u64)tag << (32 + 12);
next |= (u64)1 << (32 + 12);
@@ -162,7 +162,7 @@ nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
static void
nvc0_vm_flush(struct nouveau_vm *vm)
{
- struct nvc0_vmmgr_priv *priv = (void *)vm->vmm;
+ struct nvc0_mmu_priv *priv = (void *)vm->mmu;
struct nouveau_bar *bar = nouveau_bar(priv);
struct nouveau_vm_pgd *vpgd;
u32 type;
@@ -196,21 +196,21 @@ nvc0_vm_flush(struct nouveau_vm *vm)
}
static int
-nvc0_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
+nvc0_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
u64 mm_offset, struct nouveau_vm **pvm)
{
- return nouveau_vm_create(vmm, offset, length, mm_offset, 4096, pvm);
+ return nouveau_vm_create(mmu, offset, length, mm_offset, 4096, pvm);
}
static int
-nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvc0_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvc0_vmmgr_priv *priv;
+ struct nvc0_mmu_priv *priv;
int ret;
- ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv);
+ ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -230,12 +230,12 @@ nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
struct nouveau_oclass
-nvc0_vmmgr_oclass = {
- .handle = NV_SUBDEV(VM, 0xc0),
+nvc0_mmu_oclass = {
+ .handle = NV_SUBDEV(MMU, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_vmmgr_ctor,
- .dtor = _nouveau_vmmgr_dtor,
- .init = _nouveau_vmmgr_init,
- .fini = _nouveau_vmmgr_fini,
+ .ctor = nvc0_mmu_ctor,
+ .dtor = _nouveau_mmu_dtor,
+ .init = _nouveau_mmu_init,
+ .fini = _nouveau_mmu_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild
deleted file mode 100644
index b0290c056630..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/Kbuild
+++ /dev/null
@@ -1,6 +0,0 @@
-nvkm-y += nvkm/subdev/vm/base.o
-nvkm-y += nvkm/subdev/vm/nv04.o
-nvkm-y += nvkm/subdev/vm/nv41.o
-nvkm-y += nvkm/subdev/vm/nv44.o
-nvkm-y += nvkm/subdev/vm/nv50.o
-nvkm-y += nvkm/subdev/vm/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h
deleted file mode 100644
index ec42d4bc86a6..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/vm/nv04.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __NV04_VMMGR_PRIV__
-#define __NV04_VMMGR_PRIV__
-
-#include <subdev/vm.h>
-
-struct nv04_vmmgr_priv {
- struct nouveau_vmmgr base;
- struct nouveau_vm *vm;
- dma_addr_t null;
- void *nullp;
-};
-
-static inline struct nv04_vmmgr_priv *
-nv04_vmmgr(void *obj)
-{
- return (void *)nouveau_vmmgr(obj);
-}
-
-#endif
From eccf7e8ad28e64401519e49f56abc7c799f809b5 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 10:09:24 +1000
Subject: [PATCH 40/86] drm/nouveau/msvld: separate from bsp
Switch to NVIDIA's name for the device.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/include/nvif/class.h | 3 +-
.../drm/nouveau/include/nvkm/core/device.h | 1 +
.../gpu/drm/nouveau/include/nvkm/engine/bsp.h | 5 ---
.../drm/nouveau/include/nvkm/engine/msvld.h | 6 +++
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 1 +
.../gpu/drm/nouveau/nvkm/engine/bsp/Kbuild | 3 --
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 1 +
.../drm/nouveau/nvkm/engine/device/gm100.c | 5 ++-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 15 ++++----
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 19 +++++-----
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 15 ++++----
.../gpu/drm/nouveau/nvkm/engine/fifo/nv84.c | 11 ++++--
.../gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c | 16 ++++----
.../gpu/drm/nouveau/nvkm/engine/fifo/nve0.c | 10 ++---
.../gpu/drm/nouveau/nvkm/engine/msvld/Kbuild | 3 ++
.../nouveau/nvkm/engine/{bsp => msvld}/nv98.c | 38 +++++++++----------
.../nouveau/nvkm/engine/{bsp => msvld}/nvc0.c | 38 +++++++++----------
.../nouveau/nvkm/engine/{bsp => msvld}/nve0.c | 38 +++++++++----------
.../drm/nouveau/nvkm/subdev/devinit/nv98.c | 4 +-
.../drm/nouveau/nvkm/subdev/devinit/nva3.c | 2 +-
.../drm/nouveau/nvkm/subdev/devinit/nvaf.c | 2 +-
.../drm/nouveau/nvkm/subdev/devinit/nvc0.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 3 ++
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 3 +-
26 files changed, 133 insertions(+), 115 deletions(-)
create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild
rename drivers/gpu/drm/nouveau/nvkm/engine/{bsp => msvld}/nv98.c (81%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{bsp => msvld}/nvc0.c (81%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{bsp => msvld}/nve0.c (81%)
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h
index 4e308eacb27a..6ed8ecca8dbf 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
@@ -134,6 +134,7 @@ struct nv_device_v0 {
#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
#define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL
#define NV_DEVICE_V0_DISABLE_COPY2 0x0000080000000000ULL
+#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL
__u64 disable; /* disable particular subsystems */
__u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */
};
@@ -348,7 +349,7 @@ struct kepler_channel_gpfifo_a_v0 {
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP 0x04
-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_BSP 0x08
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 82625c5d68d7..7205d07f5cc9 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -59,6 +59,7 @@ enum nv_subdev_type {
NVDEV_ENGINE_VENC,
NVDEV_ENGINE_DISP,
NVDEV_ENGINE_PERFMON,
+ NVDEV_ENGINE_MSVLD,
NVDEV_SUBDEV_NR,
};
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
index 67662e2c4547..5ce3b620e6a9 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
@@ -1,9 +1,4 @@
#ifndef __NOUVEAU_BSP_H__
#define __NOUVEAU_BSP_H__
-
extern struct nouveau_oclass nv84_bsp_oclass;
-extern struct nouveau_oclass nv98_bsp_oclass;
-extern struct nouveau_oclass nvc0_bsp_oclass;
-extern struct nouveau_oclass nve0_bsp_oclass;
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
new file mode 100644
index 000000000000..f031bb9de74c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
@@ -0,0 +1,6 @@
+#ifndef __NVKM_MSVLD_H__
+#define __NVKM_MSVLD_H__
+extern struct nouveau_oclass nv98_msvld_oclass;
+extern struct nouveau_oclass nvc0_msvld_oclass;
+extern struct nouveau_oclass nve0_msvld_oclass;
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
index ebd30be3a62d..b410eb1e2228 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
@@ -10,6 +10,7 @@ include $(src)/nvkm/engine/dmaobj/Kbuild
include $(src)/nvkm/engine/fifo/Kbuild
include $(src)/nvkm/engine/graph/Kbuild
include $(src)/nvkm/engine/mpeg/Kbuild
+include $(src)/nvkm/engine/msvld/Kbuild
include $(src)/nvkm/engine/perfmon/Kbuild
include $(src)/nvkm/engine/ppp/Kbuild
include $(src)/nvkm/engine/software/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild
index da54c5610a67..3c8757202931 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild
@@ -1,4 +1 @@
nvkm-y += nvkm/engine/bsp/nv84.o
-nvkm-y += nvkm/engine/bsp/nv98.o
-nvkm-y += nvkm/engine/bsp/nvc0.o
-nvkm-y += nvkm/engine/bsp/nve0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index eb9f387d7356..7945bba5e794 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -241,6 +241,7 @@ static const u64 disable_map[] = {
[NVDEV_ENGINE_VIC] = NV_DEVICE_V0_DISABLE_VIC,
[NVDEV_ENGINE_VENC] = NV_DEVICE_V0_DISABLE_VENC,
[NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP,
+ [NVDEV_ENGINE_MSVLD] = NV_DEVICE_V0_DISABLE_MSVLD,
[NVDEV_SUBDEV_NR] = 0,
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 130d225377ee..391369a1c034 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -50,6 +50,7 @@
#include <engine/disp.h>
#include <engine/copy.h>
#include <engine/bsp.h>
+#include <engine/msvld.h>
#include <engine/vp.h>
#include <engine/ppp.h>
#include <engine/perfmon.h>
@@ -93,7 +94,7 @@ gm100_identify(struct nouveau_device *device)
#endif
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
#if 0
- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
#endif
@@ -136,7 +137,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &gm204_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &gm204_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &gm204_copy2_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index f9afee4f844d..90f0e23f582e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -49,6 +49,7 @@
#include <engine/vp.h>
#include <engine/crypt.h>
#include <engine/bsp.h>
+#include <engine/msvld.h>
#include <engine/ppp.h>
#include <engine/copy.h>
#include <engine/disp.h>
@@ -253,7 +254,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
@@ -311,7 +312,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
@@ -340,7 +341,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
@@ -370,7 +371,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@@ -400,7 +401,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@@ -430,7 +431,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@@ -460,7 +461,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 0db51092732a..0e1be5e2472e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -49,6 +49,7 @@
#include <engine/graph.h>
#include <engine/vp.h>
#include <engine/bsp.h>
+#include <engine/msvld.h>
#include <engine/ppp.h>
#include <engine/copy.h>
#include <engine/disp.h>
@@ -84,7 +85,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
@@ -117,7 +118,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
@@ -150,7 +151,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@@ -182,7 +183,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
@@ -215,7 +216,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@@ -247,7 +248,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@@ -279,7 +280,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
@@ -312,7 +313,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
@@ -342,7 +343,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index a565bc8b6636..1460a1650d0e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -50,6 +50,7 @@
#include <engine/disp.h>
#include <engine/copy.h>
#include <engine/bsp.h>
+#include <engine/msvld.h>
#include <engine/vp.h>
#include <engine/ppp.h>
#include <engine/perfmon.h>
@@ -87,7 +88,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
@@ -121,7 +122,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
@@ -155,7 +156,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
@@ -211,7 +212,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
@@ -245,7 +246,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
@@ -279,7 +280,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
break;
@@ -312,7 +313,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
index b18386b8a842..7183bf1d7f5b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
@@ -60,7 +60,8 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_VP : addr = 0x0040; break;
case NVDEV_ENGINE_PPP :
case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
- case NVDEV_ENGINE_BSP : addr = 0x0080; break;
+ case NVDEV_ENGINE_BSP :
+ case NVDEV_ENGINE_MSVLD: addr = 0x0080; break;
case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
default:
@@ -96,7 +97,8 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
case NVDEV_ENGINE_PPP :
case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
- case NVDEV_ENGINE_BSP : engn = 5; addr = 0x0080; break;
+ case NVDEV_ENGINE_BSP :
+ case NVDEV_ENGINE_MSVLD: engn = 5; addr = 0x0080; break;
case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
default:
@@ -147,7 +149,8 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_VP : context |= 0x00400000; break;
case NVDEV_ENGINE_CRYPT :
case NVDEV_ENGINE_VIC : context |= 0x00500000; break;
- case NVDEV_ENGINE_BSP : context |= 0x00600000; break;
+ case NVDEV_ENGINE_BSP :
+ case NVDEV_ENGINE_MSVLD : context |= 0x00600000; break;
default:
return -EINVAL;
}
@@ -187,6 +190,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_VP) |
(1ULL << NVDEV_ENGINE_CRYPT) |
(1ULL << NVDEV_ENGINE_BSP) |
+ (1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_PPP) |
(1ULL << NVDEV_ENGINE_COPY0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
@@ -260,6 +264,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_VP) |
(1ULL << NVDEV_ENGINE_CRYPT) |
(1ULL << NVDEV_ENGINE_BSP) |
+ (1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_PPP) |
(1ULL << NVDEV_ENGINE_COPY0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
index e5d1e969945e..2af40b208860 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
@@ -124,7 +124,7 @@ nvc0_fifo_context_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_GR : addr = 0x0210; break;
case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
- case NVDEV_ENGINE_BSP : addr = 0x0270; break;
+ case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
default:
@@ -161,7 +161,7 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
case NVDEV_ENGINE_GR : addr = 0x0210; break;
case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
- case NVDEV_ENGINE_BSP : addr = 0x0270; break;
+ case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
default:
@@ -214,7 +214,7 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_GR) |
(1ULL << NVDEV_ENGINE_COPY0) |
(1ULL << NVDEV_ENGINE_COPY1) |
- (1ULL << NVDEV_ENGINE_BSP) |
+ (1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_VP) |
(1ULL << NVDEV_ENGINE_PPP), &chan);
*pobject = nv_object(chan);
@@ -382,7 +382,7 @@ nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
{
switch (engn) {
case NVDEV_ENGINE_GR : engn = 0; break;
- case NVDEV_ENGINE_BSP : engn = 1; break;
+ case NVDEV_ENGINE_MSVLD: engn = 1; break;
case NVDEV_ENGINE_PPP : engn = 2; break;
case NVDEV_ENGINE_VP : engn = 3; break;
case NVDEV_ENGINE_COPY0: engn = 4; break;
@@ -399,7 +399,7 @@ nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
{
switch (engn) {
case 0: engn = NVDEV_ENGINE_GR; break;
- case 1: engn = NVDEV_ENGINE_BSP; break;
+ case 1: engn = NVDEV_ENGINE_MSVLD; break;
case 2: engn = NVDEV_ENGINE_PPP; break;
case 3: engn = NVDEV_ENGINE_VP; break;
case 4: engn = NVDEV_ENGINE_COPY0; break;
@@ -548,7 +548,7 @@ nvc0_fifo_fault_engine[] = {
{ 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
{ 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
{ 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
- { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP },
+ { 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD },
{ 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x13, "PCOUNTER" },
{ 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
@@ -583,7 +583,7 @@ nvc0_fifo_fault_hubclient[] = {
{ 0x08, "BAR_WRITE" },
{ 0x0b, "PVP" },
{ 0x0c, "PPPP" },
- { 0x0d, "PBSP" },
+ { 0x0d, "PMSVLD" },
{ 0x11, "PCOUNTER" },
{ 0x12, "PDAEMON" },
{ 0x14, "CCACHE" },
@@ -941,7 +941,7 @@ nvc0_fifo_init(struct nouveau_object *object)
nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
- nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */
+ nv_wr32(priv, 0x002214, ~(1 << 1)); /* PMSVLD */
nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
index bf2b9e2df3d0..b415b309f4b8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
@@ -50,7 +50,7 @@ static const struct {
(1ULL << NVDEV_ENGINE_COPY2)),
_(NVDEV_ENGINE_VP , 0),
_(NVDEV_ENGINE_PPP , 0),
- _(NVDEV_ENGINE_BSP , 0),
+ _(NVDEV_ENGINE_MSVLD , 0),
_(NVDEV_ENGINE_COPY0 , 0),
_(NVDEV_ENGINE_COPY1 , 0),
_(NVDEV_ENGINE_VENC , 0),
@@ -149,7 +149,7 @@ nve0_fifo_context_attach(struct nouveau_object *parent,
nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
return 0;
case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_BSP : addr = 0x0270; break;
+ case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
default:
@@ -187,7 +187,7 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
case NVDEV_ENGINE_COPY1:
case NVDEV_ENGINE_COPY2: addr = 0x0000; break;
case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_BSP : addr = 0x0270; break;
+ case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
default:
@@ -416,7 +416,7 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
switch (engn) {
case NVDEV_ENGINE_GR :
case NVDEV_ENGINE_COPY2: engn = 0; break;
- case NVDEV_ENGINE_BSP : engn = 1; break;
+ case NVDEV_ENGINE_MSVLD: engn = 1; break;
case NVDEV_ENGINE_PPP : engn = 2; break;
case NVDEV_ENGINE_VP : engn = 3; break;
case NVDEV_ENGINE_COPY0: engn = 4; break;
@@ -619,7 +619,7 @@ nve0_fifo_fault_engine[] = {
{ 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO },
{ 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO },
{ 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO },
- { 0x10, "MSVLD", NULL, NVDEV_ENGINE_BSP },
+ { 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD },
{ 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x13, "PERF" },
{ 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild
new file mode 100644
index 000000000000..1deb463a2b0b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild
@@ -0,0 +1,3 @@
+nvkm-y += nvkm/engine/msvld/nv98.o
+nvkm-y += nvkm/engine/msvld/nvc0.o
+nvkm-y += nvkm/engine/msvld/nve0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nv98.c
similarity index 81%
rename from drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/msvld/nv98.c
index 6b089e022fd2..4bafba59226c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nv98.c
@@ -23,18 +23,18 @@
*/
#include <engine/falcon.h>
-#include <engine/bsp.h>
+#include <engine/msvld.h>
-struct nv98_bsp_priv {
+struct nv98_msvld_priv {
struct nouveau_falcon base;
};
/*******************************************************************************
- * BSP object classes
+ * MSVLD object classes
******************************************************************************/
static struct nouveau_oclass
-nv98_bsp_sclass[] = {
+nv98_msvld_sclass[] = {
{ 0x88b1, &nouveau_object_ofuncs },
{ 0x85b1, &nouveau_object_ofuncs },
{ 0x86b1, &nouveau_object_ofuncs },
@@ -42,12 +42,12 @@ nv98_bsp_sclass[] = {
};
/*******************************************************************************
- * PBSP context
+ * PMSVLD context
******************************************************************************/
static struct nouveau_oclass
-nv98_bsp_cclass = {
- .handle = NV_ENGCTX(BSP, 0x98),
+nv98_msvld_cclass = {
+ .handle = NV_ENGCTX(MSVLD, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@@ -59,13 +59,13 @@ nv98_bsp_cclass = {
};
/*******************************************************************************
- * PBSP engine/subdev functions
+ * PMSVLD engine/subdev functions
******************************************************************************/
static int
-nv98_bsp_init(struct nouveau_object *object)
+nv98_msvld_init(struct nouveau_object *object)
{
- struct nv98_bsp_priv *priv = (void *)object;
+ struct nv98_msvld_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
@@ -78,32 +78,32 @@ nv98_bsp_init(struct nouveau_object *object)
}
static int
-nv98_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv98_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv98_bsp_priv *priv;
+ struct nv98_msvld_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
- "PBSP", "bsp", &priv);
+ "PMSVLD", "msvld", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x04008000;
- nv_engine(priv)->cclass = &nv98_bsp_cclass;
- nv_engine(priv)->sclass = nv98_bsp_sclass;
+ nv_engine(priv)->cclass = &nv98_msvld_cclass;
+ nv_engine(priv)->sclass = nv98_msvld_sclass;
return 0;
}
struct nouveau_oclass
-nv98_bsp_oclass = {
- .handle = NV_ENGINE(BSP, 0x98),
+nv98_msvld_oclass = {
+ .handle = NV_ENGINE(MSVLD, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv98_bsp_ctor,
+ .ctor = nv98_msvld_ctor,
.dtor = _nouveau_falcon_dtor,
- .init = nv98_bsp_init,
+ .init = nv98_msvld_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nvc0.c
similarity index 81%
rename from drivers/gpu/drm/nouveau/nvkm/engine/bsp/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/msvld/nvc0.c
index ce860de43e61..fd2ac0d620c6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nvc0.c
@@ -23,29 +23,29 @@
*/
#include <engine/falcon.h>
-#include <engine/bsp.h>
+#include <engine/msvld.h>
-struct nvc0_bsp_priv {
+struct nvc0_msvld_priv {
struct nouveau_falcon base;
};
/*******************************************************************************
- * BSP object classes
+ * MSVLD object classes
******************************************************************************/
static struct nouveau_oclass
-nvc0_bsp_sclass[] = {
+nvc0_msvld_sclass[] = {
{ 0x90b1, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
- * PBSP context
+ * PMSVLD context
******************************************************************************/
static struct nouveau_oclass
-nvc0_bsp_cclass = {
- .handle = NV_ENGCTX(BSP, 0xc0),
+nvc0_msvld_cclass = {
+ .handle = NV_ENGCTX(MSVLD, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@@ -57,13 +57,13 @@ nvc0_bsp_cclass = {
};
/*******************************************************************************
- * PBSP engine/subdev functions
+ * PMSVLD engine/subdev functions
******************************************************************************/
static int
-nvc0_bsp_init(struct nouveau_object *object)
+nvc0_msvld_init(struct nouveau_object *object)
{
- struct nvc0_bsp_priv *priv = (void *)object;
+ struct nvc0_msvld_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
@@ -76,33 +76,33 @@ nvc0_bsp_init(struct nouveau_object *object)
}
static int
-nvc0_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvc0_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvc0_bsp_priv *priv;
+ struct nvc0_msvld_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
- "PBSP", "bsp", &priv);
+ "PMSVLD", "msvld", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00008000;
nv_subdev(priv)->intr = nouveau_falcon_intr;
- nv_engine(priv)->cclass = &nvc0_bsp_cclass;
- nv_engine(priv)->sclass = nvc0_bsp_sclass;
+ nv_engine(priv)->cclass = &nvc0_msvld_cclass;
+ nv_engine(priv)->sclass = nvc0_msvld_sclass;
return 0;
}
struct nouveau_oclass
-nvc0_bsp_oclass = {
- .handle = NV_ENGINE(BSP, 0xc0),
+nvc0_msvld_oclass = {
+ .handle = NV_ENGINE(MSVLD, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_bsp_ctor,
+ .ctor = nvc0_msvld_ctor,
.dtor = _nouveau_falcon_dtor,
- .init = nvc0_bsp_init,
+ .init = nvc0_msvld_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nve0.c
similarity index 81%
rename from drivers/gpu/drm/nouveau/nvkm/engine/bsp/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/msvld/nve0.c
index ba6aeca0285e..4b3d3ca80eff 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nve0.c
@@ -23,29 +23,29 @@
*/
#include <engine/falcon.h>
-#include <engine/bsp.h>
+#include <engine/msvld.h>
-struct nve0_bsp_priv {
+struct nve0_msvld_priv {
struct nouveau_falcon base;
};
/*******************************************************************************
- * BSP object classes
+ * MSVLD object classes
******************************************************************************/
static struct nouveau_oclass
-nve0_bsp_sclass[] = {
+nve0_msvld_sclass[] = {
{ 0x95b1, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
- * PBSP context
+ * PMSVLD context
******************************************************************************/
static struct nouveau_oclass
-nve0_bsp_cclass = {
- .handle = NV_ENGCTX(BSP, 0xe0),
+nve0_msvld_cclass = {
+ .handle = NV_ENGCTX(MSVLD, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@@ -57,13 +57,13 @@ nve0_bsp_cclass = {
};
/*******************************************************************************
- * PBSP engine/subdev functions
+ * PMSVLD engine/subdev functions
******************************************************************************/
static int
-nve0_bsp_init(struct nouveau_object *object)
+nve0_msvld_init(struct nouveau_object *object)
{
- struct nve0_bsp_priv *priv = (void *)object;
+ struct nve0_msvld_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
@@ -76,33 +76,33 @@ nve0_bsp_init(struct nouveau_object *object)
}
static int
-nve0_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nve0_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nve0_bsp_priv *priv;
+ struct nve0_msvld_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
- "PBSP", "bsp", &priv);
+ "PMSVLD", "msvld", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00008000;
nv_subdev(priv)->intr = nouveau_falcon_intr;
- nv_engine(priv)->cclass = &nve0_bsp_cclass;
- nv_engine(priv)->sclass = nve0_bsp_sclass;
+ nv_engine(priv)->cclass = &nve0_msvld_cclass;
+ nv_engine(priv)->sclass = nve0_msvld_sclass;
return 0;
}
struct nouveau_oclass
-nve0_bsp_oclass = {
- .handle = NV_ENGINE(BSP, 0xe0),
+nve0_msvld_oclass = {
+ .handle = NV_ENGINE(MSVLD, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_bsp_ctor,
+ .ctor = nve0_msvld_ctor,
.dtor = _nouveau_falcon_dtor,
- .init = nve0_bsp_init,
+ .init = nve0_msvld_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
index a773253a17f6..820f069fbaac 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
@@ -34,14 +34,14 @@ nv98_devinit_disable(struct nouveau_devinit *devinit)
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVDEV_ENGINE_VP);
- disable |= (1ULL << NVDEV_ENGINE_BSP);
+ disable |= (1ULL << NVDEV_ENGINE_MSVLD);
disable |= (1ULL << NVDEV_ENGINE_PPP);
}
if (!(r00154c & 0x00000004))
disable |= (1ULL << NVDEV_ENGINE_DISP);
if (!(r00154c & 0x00000020))
- disable |= (1ULL << NVDEV_ENGINE_BSP);
+ disable |= (1ULL << NVDEV_ENGINE_MSVLD);
if (!(r00154c & 0x00000040))
disable |= (1ULL << NVDEV_ENGINE_CRYPT);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
index b9cd9e53f760..f662a261cc65 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
@@ -74,7 +74,7 @@ nva3_devinit_disable(struct nouveau_devinit *devinit)
if (!(r00154c & 0x00000004))
disable |= (1ULL << NVDEV_ENGINE_DISP);
if (!(r00154c & 0x00000020))
- disable |= (1ULL << NVDEV_ENGINE_BSP);
+ disable |= (1ULL << NVDEV_ENGINE_MSVLD);
if (!(r00154c & 0x00000200))
disable |= (1ULL << NVDEV_ENGINE_COPY0);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
index 3729846a8e5c..6f8ef894e4ef 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
@@ -40,7 +40,7 @@ nvaf_devinit_disable(struct nouveau_devinit *devinit)
if (!(r00154c & 0x00000004))
disable |= (1ULL << NVDEV_ENGINE_DISP);
if (!(r00154c & 0x00000020))
- disable |= (1ULL << NVDEV_ENGINE_BSP);
+ disable |= (1ULL << NVDEV_ENGINE_MSVLD);
if (!(r00154c & 0x00000040))
disable |= (1ULL << NVDEV_ENGINE_VIC);
if (!(r00154c & 0x00000200))
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
index 80bd7f5eda3d..ac699a366f60 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
@@ -75,7 +75,7 @@ nvc0_devinit_disable(struct nouveau_devinit *devinit)
}
if (r022500 & 0x00000004)
- disable |= (1ULL << NVDEV_ENGINE_BSP);
+ disable |= (1ULL << NVDEV_ENGINE_MSVLD);
if (r022500 & 0x00000008)
disable |= (1ULL << NVDEV_ENGINE_VENC);
if (r022500 & 0x00000100)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
index 4150b0d10af8..df07c046213e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
@@ -189,6 +189,9 @@ nv50_fb_intr(struct nouveau_subdev *subdev)
const struct nouveau_enum *orig_en = en;
while (en->name && en->value == st0 && en->data2) {
engine = nouveau_engine(subdev, en->data2);
+ /*XXX: clean this up */
+ if (!engine && en->data2 == NVDEV_ENGINE_BSP)
+ engine = nouveau_engine(subdev, NVDEV_ENGINE_MSVLD);
if (engine) {
engctx = nouveau_engctx_get(engine, chan);
if (engctx)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
index aa1c690fe0e1..bb1346f6fa12 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
@@ -31,7 +31,7 @@ nv98_mc_intr[] = {
{ 0x00000100, NVDEV_ENGINE_FIFO },
{ 0x00001000, NVDEV_ENGINE_GR },
{ 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84:NVA3 */
- { 0x00008000, NVDEV_ENGINE_BSP },
+ { 0x00008000, NVDEV_ENGINE_MSVLD },
{ 0x00020000, NVDEV_ENGINE_VP },
{ 0x00040000, NVDEV_SUBDEV_PMU }, /* NVA3:NVC0 */
{ 0x00080000, NVDEV_SUBDEV_THERM }, /* NVA3:NVC0 */
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
index 7053ae3db08e..1e352152cadd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
@@ -34,7 +34,7 @@ nvc0_mc_intr[] = {
{ 0x00000100, NVDEV_ENGINE_FIFO },
{ 0x00001000, NVDEV_ENGINE_GR },
{ 0x00002000, NVDEV_SUBDEV_FB },
- { 0x00008000, NVDEV_ENGINE_BSP },
+ { 0x00008000, NVDEV_ENGINE_MSVLD },
{ 0x00040000, NVDEV_SUBDEV_THERM },
{ 0x00020000, NVDEV_ENGINE_VP },
{ 0x00100000, NVDEV_SUBDEV_TIMER },
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
index 6ddc65dc684d..eabf2bab1d10 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
@@ -176,7 +176,8 @@ nv50_vm_flush(struct nouveau_vm *vm)
case NVDEV_SUBDEV_BAR : vme = 0x06; break;
case NVDEV_ENGINE_PPP :
case NVDEV_ENGINE_MPEG : vme = 0x08; break;
- case NVDEV_ENGINE_BSP : vme = 0x09; break;
+ case NVDEV_ENGINE_BSP :
+ case NVDEV_ENGINE_MSVLD: vme = 0x09; break;
case NVDEV_ENGINE_CRYPT: vme = 0x0a; break;
case NVDEV_ENGINE_COPY0: vme = 0x0d; break;
default:
From 93d90ad708b8da6efc0e487b66111aa9db7f70c7 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 10:46:55 +1000
Subject: [PATCH 41/86] drm/nouveau/sec: separate from cipher (formerly crypt)
Switch to NVIDIA's name for the device.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/include/nvif/class.h | 3 +-
.../drm/nouveau/include/nvkm/core/device.h | 3 +-
.../drm/nouveau/include/nvkm/engine/cipher.h | 4 +
.../drm/nouveau/include/nvkm/engine/crypt.h | 7 --
.../gpu/drm/nouveau/include/nvkm/engine/sec.h | 4 +
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 3 +-
.../gpu/drm/nouveau/nvkm/engine/cipher/Kbuild | 1 +
.../nvkm/engine/{crypt => cipher}/nv84.c | 54 ++++-----
.../gpu/drm/nouveau/nvkm/engine/crypt/Kbuild | 2 -
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 3 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 21 ++--
.../gpu/drm/nouveau/nvkm/engine/fifo/nv84.c | 47 ++++----
.../gpu/drm/nouveau/nvkm/engine/sec/Kbuild | 1 +
.../nvkm/engine/{crypt => sec}/fuc/nv98.fuc0s | 104 +++++++++---------
.../engine/{crypt => sec}/fuc/nv98.fuc0s.h | 54 ++++-----
.../nouveau/nvkm/engine/{crypt => sec}/nv98.c | 48 ++++----
.../drm/nouveau/nvkm/subdev/devinit/nv84.c | 4 +-
.../drm/nouveau/nvkm/subdev/devinit/nv98.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 4 +-
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 19 ++--
22 files changed, 203 insertions(+), 189 deletions(-)
create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h
delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/crypt.h
create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild
rename drivers/gpu/drm/nouveau/nvkm/engine/{crypt => cipher}/nv84.c (80%)
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild
rename drivers/gpu/drm/nouveau/nvkm/engine/{crypt => sec}/fuc/nv98.fuc0s (88%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{crypt => sec}/fuc/nv98.fuc0s.h (90%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{crypt => sec}/nv98.c (80%)
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h
index 6ed8ecca8dbf..d5da658d9d43 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
@@ -126,7 +126,7 @@ struct nv_device_v0 {
#define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL
#define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL
#define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL
-#define NV_DEVICE_V0_DISABLE_CRYPT 0x0000001000000000ULL
+#define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL
#define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL
#define NV_DEVICE_V0_DISABLE_PPP 0x0000004000000000ULL
#define NV_DEVICE_V0_DISABLE_COPY0 0x0000008000000000ULL
@@ -135,6 +135,7 @@ struct nv_device_v0 {
#define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL
#define NV_DEVICE_V0_DISABLE_COPY2 0x0000080000000000ULL
#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL
+#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL
__u64 disable; /* disable particular subsystems */
__u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */
};
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 7205d07f5cc9..cefa8774e11c 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -49,7 +49,7 @@ enum nv_subdev_type {
NVDEV_ENGINE_MPEG,
NVDEV_ENGINE_ME,
NVDEV_ENGINE_VP,
- NVDEV_ENGINE_CRYPT,
+ NVDEV_ENGINE_CIPHER,
NVDEV_ENGINE_BSP,
NVDEV_ENGINE_PPP,
NVDEV_ENGINE_COPY0,
@@ -60,6 +60,7 @@ enum nv_subdev_type {
NVDEV_ENGINE_DISP,
NVDEV_ENGINE_PERFMON,
NVDEV_ENGINE_MSVLD,
+ NVDEV_ENGINE_SEC,
NVDEV_SUBDEV_NR,
};
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h
new file mode 100644
index 000000000000..813bca367331
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h
@@ -0,0 +1,4 @@
+#ifndef __NVKM_CIPHER_H__
+#define __NVKM_CIPHER_H__
+extern struct nouveau_oclass nv84_cipher_oclass;
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/crypt.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/crypt.h
deleted file mode 100644
index db975618e937..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/crypt.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __NOUVEAU_CRYPT_H__
-#define __NOUVEAU_CRYPT_H__
-
-extern struct nouveau_oclass nv84_crypt_oclass;
-extern struct nouveau_oclass nv98_crypt_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h
new file mode 100644
index 000000000000..32cd4cb0744c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h
@@ -0,0 +1,4 @@
+#ifndef __NVKM_SEC_H__
+#define __NVKM_SEC_H__
+extern struct nouveau_oclass nv98_sec_oclass;
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
index b410eb1e2228..aad171d3cbcc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
@@ -2,8 +2,8 @@ nvkm-y += nvkm/engine/falcon.o
nvkm-y += nvkm/engine/xtensa.o
include $(src)/nvkm/engine/bsp/Kbuild
+include $(src)/nvkm/engine/cipher/Kbuild
include $(src)/nvkm/engine/copy/Kbuild
-include $(src)/nvkm/engine/crypt/Kbuild
include $(src)/nvkm/engine/device/Kbuild
include $(src)/nvkm/engine/disp/Kbuild
include $(src)/nvkm/engine/dmaobj/Kbuild
@@ -13,5 +13,6 @@ include $(src)/nvkm/engine/mpeg/Kbuild
include $(src)/nvkm/engine/msvld/Kbuild
include $(src)/nvkm/engine/perfmon/Kbuild
include $(src)/nvkm/engine/ppp/Kbuild
+include $(src)/nvkm/engine/sec/Kbuild
include $(src)/nvkm/engine/software/Kbuild
include $(src)/nvkm/engine/vp/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild
new file mode 100644
index 000000000000..07cc2150463b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild
@@ -0,0 +1 @@
+nvkm-y += nvkm/engine/cipher/nv84.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/nv84.c
similarity index 80%
rename from drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/cipher/nv84.c
index ea5c42f31791..d4ecd91ccbe6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/nv84.c
@@ -31,9 +31,9 @@
#include <subdev/fb.h>
#include <engine/fifo.h>
-#include <engine/crypt.h>
+#include <engine/cipher.h>
-struct nv84_crypt_priv {
+struct nv84_cipher_priv {
struct nouveau_engine base;
};
@@ -42,7 +42,7 @@ struct nv84_crypt_priv {
******************************************************************************/
static int
-nv84_crypt_object_ctor(struct nouveau_object *parent,
+nv84_cipher_object_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
@@ -64,8 +64,8 @@ nv84_crypt_object_ctor(struct nouveau_object *parent,
}
static struct nouveau_ofuncs
-nv84_crypt_ofuncs = {
- .ctor = nv84_crypt_object_ctor,
+nv84_cipher_ofuncs = {
+ .ctor = nv84_cipher_object_ctor,
.dtor = _nouveau_gpuobj_dtor,
.init = _nouveau_gpuobj_init,
.fini = _nouveau_gpuobj_fini,
@@ -74,18 +74,18 @@ nv84_crypt_ofuncs = {
};
static struct nouveau_oclass
-nv84_crypt_sclass[] = {
- { 0x74c1, &nv84_crypt_ofuncs },
+nv84_cipher_sclass[] = {
+ { 0x74c1, &nv84_cipher_ofuncs },
{}
};
/*******************************************************************************
- * PCRYPT context
+ * PCIPHER context
******************************************************************************/
static struct nouveau_oclass
-nv84_crypt_cclass = {
- .handle = NV_ENGCTX(CRYPT, 0x84),
+nv84_cipher_cclass = {
+ .handle = NV_ENGCTX(CIPHER, 0x84),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_engctx_ctor,
.dtor = _nouveau_engctx_dtor,
@@ -97,10 +97,10 @@ nv84_crypt_cclass = {
};
/*******************************************************************************
- * PCRYPT engine/subdev functions
+ * PCIPHER engine/subdev functions
******************************************************************************/
-static const struct nouveau_bitfield nv84_crypt_intr_mask[] = {
+static const struct nouveau_bitfield nv84_cipher_intr_mask[] = {
{ 0x00000001, "INVALID_STATE" },
{ 0x00000002, "ILLEGAL_MTHD" },
{ 0x00000004, "ILLEGAL_CLASS" },
@@ -110,12 +110,12 @@ static const struct nouveau_bitfield nv84_crypt_intr_mask[] = {
};
static void
-nv84_crypt_intr(struct nouveau_subdev *subdev)
+nv84_cipher_intr(struct nouveau_subdev *subdev)
{
struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
struct nouveau_engine *engine = nv_engine(subdev);
struct nouveau_object *engctx;
- struct nv84_crypt_priv *priv = (void *)subdev;
+ struct nv84_cipher_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, 0x102130);
u32 mthd = nv_rd32(priv, 0x102190);
u32 data = nv_rd32(priv, 0x102194);
@@ -127,7 +127,7 @@ nv84_crypt_intr(struct nouveau_subdev *subdev)
if (stat) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv84_crypt_intr_mask, stat);
+ nouveau_bitfield_print(nv84_cipher_intr_mask, stat);
pr_cont(" ch %d [0x%010llx %s] mthd 0x%04x data 0x%08x\n",
chid, (u64)inst << 12, nouveau_client_name(engctx),
mthd, data);
@@ -140,30 +140,30 @@ nv84_crypt_intr(struct nouveau_subdev *subdev)
}
static int
-nv84_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv84_cipher_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv84_crypt_priv *priv;
+ struct nv84_cipher_priv *priv;
int ret;
ret = nouveau_engine_create(parent, engine, oclass, true,
- "PCRYPT", "crypt", &priv);
+ "PCIPHER", "cipher", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00004000;
- nv_subdev(priv)->intr = nv84_crypt_intr;
- nv_engine(priv)->cclass = &nv84_crypt_cclass;
- nv_engine(priv)->sclass = nv84_crypt_sclass;
+ nv_subdev(priv)->intr = nv84_cipher_intr;
+ nv_engine(priv)->cclass = &nv84_cipher_cclass;
+ nv_engine(priv)->sclass = nv84_cipher_sclass;
return 0;
}
static int
-nv84_crypt_init(struct nouveau_object *object)
+nv84_cipher_init(struct nouveau_object *object)
{
- struct nv84_crypt_priv *priv = (void *)object;
+ struct nv84_cipher_priv *priv = (void *)object;
int ret;
ret = nouveau_engine_init(&priv->base);
@@ -177,12 +177,12 @@ nv84_crypt_init(struct nouveau_object *object)
}
struct nouveau_oclass
-nv84_crypt_oclass = {
- .handle = NV_ENGINE(CRYPT, 0x84),
+nv84_cipher_oclass = {
+ .handle = NV_ENGINE(CIPHER, 0x84),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv84_crypt_ctor,
+ .ctor = nv84_cipher_ctor,
.dtor = _nouveau_engine_dtor,
- .init = nv84_crypt_init,
+ .init = nv84_cipher_init,
.fini = _nouveau_engine_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild
deleted file mode 100644
index eaeafdf3bc81..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild
+++ /dev/null
@@ -1,2 +0,0 @@
-nvkm-y += nvkm/engine/crypt/nv84.o
-nvkm-y += nvkm/engine/crypt/nv98.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 7945bba5e794..fe269ef00355 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -232,7 +232,7 @@ static const u64 disable_map[] = {
[NVDEV_ENGINE_MPEG] = NV_DEVICE_V0_DISABLE_MPEG,
[NVDEV_ENGINE_ME] = NV_DEVICE_V0_DISABLE_ME,
[NVDEV_ENGINE_VP] = NV_DEVICE_V0_DISABLE_VP,
- [NVDEV_ENGINE_CRYPT] = NV_DEVICE_V0_DISABLE_CRYPT,
+ [NVDEV_ENGINE_CIPHER] = NV_DEVICE_V0_DISABLE_CIPHER,
[NVDEV_ENGINE_BSP] = NV_DEVICE_V0_DISABLE_BSP,
[NVDEV_ENGINE_PPP] = NV_DEVICE_V0_DISABLE_PPP,
[NVDEV_ENGINE_COPY0] = NV_DEVICE_V0_DISABLE_COPY0,
@@ -242,6 +242,7 @@ static const u64 disable_map[] = {
[NVDEV_ENGINE_VENC] = NV_DEVICE_V0_DISABLE_VENC,
[NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP,
[NVDEV_ENGINE_MSVLD] = NV_DEVICE_V0_DISABLE_MSVLD,
+ [NVDEV_ENGINE_SEC] = NV_DEVICE_V0_DISABLE_SEC,
[NVDEV_SUBDEV_NR] = 0,
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 90f0e23f582e..2fb06eb451f3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -47,7 +47,8 @@
#include <engine/graph.h>
#include <engine/mpeg.h>
#include <engine/vp.h>
-#include <engine/crypt.h>
+#include <engine/cipher.h>
+#include <engine/sec.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/ppp.h>
@@ -109,7 +110,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
+ device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
@@ -138,7 +139,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
+ device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
@@ -167,7 +168,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
+ device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
@@ -196,7 +197,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
+ device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
@@ -225,7 +226,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
+ device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
@@ -253,7 +254,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
+ device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
@@ -283,7 +284,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
+ device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
@@ -311,7 +312,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
+ device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
@@ -340,7 +341,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
+ device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
index 7183bf1d7f5b..392843991663 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
@@ -55,15 +55,16 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
u32 addr;
switch (nv_engidx(object->engine)) {
- case NVDEV_ENGINE_SW : return 0;
- case NVDEV_ENGINE_GR : addr = 0x0020; break;
- case NVDEV_ENGINE_VP : addr = 0x0040; break;
- case NVDEV_ENGINE_PPP :
- case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
- case NVDEV_ENGINE_BSP :
- case NVDEV_ENGINE_MSVLD: addr = 0x0080; break;
- case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
- case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
+ case NVDEV_ENGINE_SW : return 0;
+ case NVDEV_ENGINE_GR : addr = 0x0020; break;
+ case NVDEV_ENGINE_VP : addr = 0x0040; break;
+ case NVDEV_ENGINE_PPP :
+ case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
+ case NVDEV_ENGINE_BSP :
+ case NVDEV_ENGINE_MSVLD : addr = 0x0080; break;
+ case NVDEV_ENGINE_CIPHER:
+ case NVDEV_ENGINE_SEC : addr = 0x00a0; break;
+ case NVDEV_ENGINE_COPY0 : addr = 0x00c0; break;
default:
return -EINVAL;
}
@@ -92,15 +93,16 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
bool done;
switch (nv_engidx(object->engine)) {
- case NVDEV_ENGINE_SW : return 0;
- case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
- case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
- case NVDEV_ENGINE_PPP :
- case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
- case NVDEV_ENGINE_BSP :
- case NVDEV_ENGINE_MSVLD: engn = 5; addr = 0x0080; break;
- case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
- case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
+ case NVDEV_ENGINE_SW : return 0;
+ case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
+ case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
+ case NVDEV_ENGINE_PPP :
+ case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
+ case NVDEV_ENGINE_BSP :
+ case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break;
+ case NVDEV_ENGINE_CIPHER:
+ case NVDEV_ENGINE_SEC : engn = 4; addr = 0x00a0; break;
+ case NVDEV_ENGINE_COPY0 : engn = 2; addr = 0x00c0; break;
default:
return -EINVAL;
}
@@ -147,7 +149,8 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_ME :
case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
case NVDEV_ENGINE_VP : context |= 0x00400000; break;
- case NVDEV_ENGINE_CRYPT :
+ case NVDEV_ENGINE_CIPHER:
+ case NVDEV_ENGINE_SEC :
case NVDEV_ENGINE_VIC : context |= 0x00500000; break;
case NVDEV_ENGINE_BSP :
case NVDEV_ENGINE_MSVLD : context |= 0x00600000; break;
@@ -188,7 +191,8 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_MPEG) |
(1ULL << NVDEV_ENGINE_ME) |
(1ULL << NVDEV_ENGINE_VP) |
- (1ULL << NVDEV_ENGINE_CRYPT) |
+ (1ULL << NVDEV_ENGINE_CIPHER) |
+ (1ULL << NVDEV_ENGINE_SEC) |
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_PPP) |
@@ -262,7 +266,8 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_MPEG) |
(1ULL << NVDEV_ENGINE_ME) |
(1ULL << NVDEV_ENGINE_VP) |
- (1ULL << NVDEV_ENGINE_CRYPT) |
+ (1ULL << NVDEV_ENGINE_CIPHER) |
+ (1ULL << NVDEV_ENGINE_SEC) |
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_PPP) |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild
new file mode 100644
index 000000000000..5ce7a5073c97
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild
@@ -0,0 +1 @@
+nvkm-y += nvkm/engine/sec/nv98.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s
similarity index 88%
rename from drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s
rename to drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s
index 629da02dc352..0b9e77782a57 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s
@@ -1,5 +1,5 @@
/*
- * fuc microcode for nv98 pcrypt engine
+ * fuc microcode for nv98 psec engine
* Copyright (C) 2010 Marcin Kościelnicki
*
* This program is free software; you can redistribute it and/or modify
@@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-.section #nv98_pcrypt_data
+.section #nv98_psec_data
ctx_dma:
ctx_dma_query: .b32 0
@@ -70,31 +70,31 @@ engine_cmd_dtable:
.b32 #ctx_src_address_low + 0x20000 ~0xfffffff0
.b32 #ctx_dst_address_high + 0x20000 ~0xff
.b32 #ctx_dst_address_low + 0x20000 ~0xfffffff0
-.b32 #crypt_cmd_mode + 0x00000 ~0xf
-.b32 #crypt_cmd_length + 0x10000 ~0x0ffffff0
+.b32 #sec_cmd_mode + 0x00000 ~0xf
+.b32 #sec_cmd_length + 0x10000 ~0x0ffffff0
.equ #engine_cmd_max 0xce
.align 4
-crypt_dtable:
-.b16 #crypt_copy_prep #crypt_do_inout
-.b16 #crypt_store_prep #crypt_do_out
-.b16 #crypt_ecb_e_prep #crypt_do_inout
-.b16 #crypt_ecb_d_prep #crypt_do_inout
-.b16 #crypt_cbc_e_prep #crypt_do_inout
-.b16 #crypt_cbc_d_prep #crypt_do_inout
-.b16 #crypt_pcbc_e_prep #crypt_do_inout
-.b16 #crypt_pcbc_d_prep #crypt_do_inout
-.b16 #crypt_cfb_e_prep #crypt_do_inout
-.b16 #crypt_cfb_d_prep #crypt_do_inout
-.b16 #crypt_ofb_prep #crypt_do_inout
-.b16 #crypt_ctr_prep #crypt_do_inout
-.b16 #crypt_cbc_mac_prep #crypt_do_in
-.b16 #crypt_cmac_finish_complete_prep #crypt_do_in
-.b16 #crypt_cmac_finish_partial_prep #crypt_do_in
+sec_dtable:
+.b16 #sec_copy_prep #sec_do_inout
+.b16 #sec_store_prep #sec_do_out
+.b16 #sec_ecb_e_prep #sec_do_inout
+.b16 #sec_ecb_d_prep #sec_do_inout
+.b16 #sec_cbc_e_prep #sec_do_inout
+.b16 #sec_cbc_d_prep #sec_do_inout
+.b16 #sec_pcbc_e_prep #sec_do_inout
+.b16 #sec_pcbc_d_prep #sec_do_inout
+.b16 #sec_cfb_e_prep #sec_do_inout
+.b16 #sec_cfb_d_prep #sec_do_inout
+.b16 #sec_ofb_prep #sec_do_inout
+.b16 #sec_ctr_prep #sec_do_inout
+.b16 #sec_cbc_mac_prep #sec_do_in
+.b16 #sec_cmac_finish_complete_prep #sec_do_in
+.b16 #sec_cmac_finish_partial_prep #sec_do_in
.align 0x100
-.section #nv98_pcrypt_code
+.section #nv98_psec_code
// $r0 is always set to 0 in our code - this allows some space savings.
clear b32 $r0
@@ -417,23 +417,23 @@ cmd_wrcache_flush:
iowr I[$r2] $r3
ret
-crypt_cmd_mode:
+sec_cmd_mode:
// if >= 0xf, INVALID_ENUM
bset $flags $p1
or $r2 2
cmpu b32 $r3 0xf
- bra nc #crypt_cmd_mode_return
+ bra nc #sec_cmd_mode_return
bclr $flags $p1
st b32 D[$r0 + #ctx_mode] $r3
- crypt_cmd_mode_return:
+ sec_cmd_mode_return:
ret
-crypt_cmd_length:
+sec_cmd_length:
// nop if length == 0
cmpu b32 $r3 0
- bra e #crypt_cmd_mode_return
+ bra e #sec_cmd_mode_return
// init key, IV
cxset 3
@@ -471,11 +471,11 @@ crypt_cmd_length:
shl b32 $r8 2
// run prep
- ld b16 $r9 D[$r8 + #crypt_dtable]
+ ld b16 $r9 D[$r8 + #sec_dtable]
call $r9
// do it
- ld b16 $r9 D[$r8 + #crypt_dtable + 2]
+ ld b16 $r9 D[$r8 + #sec_dtable + 2]
call $r9
cxset 1
xdwait
@@ -509,25 +509,25 @@ crypt_cmd_length:
ret
-crypt_copy_prep:
+sec_copy_prep:
cs0begin 2
cxsin $c0
cxsout $c0
ret
-crypt_store_prep:
+sec_store_prep:
cs0begin 1
cxsout $c6
ret
-crypt_ecb_e_prep:
+sec_ecb_e_prep:
cs0begin 3
cxsin $c0
cenc $c0 $c0
cxsout $c0
ret
-crypt_ecb_d_prep:
+sec_ecb_d_prep:
ckexp $c7 $c7
cs0begin 3
cxsin $c0
@@ -535,7 +535,7 @@ crypt_ecb_d_prep:
cxsout $c0
ret
-crypt_cbc_e_prep:
+sec_cbc_e_prep:
cs0begin 4
cxsin $c0
cxor $c6 $c0
@@ -543,7 +543,7 @@ crypt_cbc_e_prep:
cxsout $c6
ret
-crypt_cbc_d_prep:
+sec_cbc_d_prep:
ckexp $c7 $c7
cs0begin 5
cmov $c2 $c6
@@ -553,7 +553,7 @@ crypt_cbc_d_prep:
cxsout $c0
ret
-crypt_pcbc_e_prep:
+sec_pcbc_e_prep:
cs0begin 5
cxsin $c0
cxor $c6 $c0
@@ -562,7 +562,7 @@ crypt_pcbc_e_prep:
cxor $c6 $c0
ret
-crypt_pcbc_d_prep:
+sec_pcbc_d_prep:
ckexp $c7 $c7
cs0begin 5
cxsin $c0
@@ -572,7 +572,7 @@ crypt_pcbc_d_prep:
cxor $c6 $c0
ret
-crypt_cfb_e_prep:
+sec_cfb_e_prep:
cs0begin 4
cenc $c6 $c6
cxsin $c0
@@ -580,7 +580,7 @@ crypt_cfb_e_prep:
cxsout $c6
ret
-crypt_cfb_d_prep:
+sec_cfb_d_prep:
cs0begin 4
cenc $c0 $c6
cxsin $c6
@@ -588,7 +588,7 @@ crypt_cfb_d_prep:
cxsout $c0
ret
-crypt_ofb_prep:
+sec_ofb_prep:
cs0begin 4
cenc $c6 $c6
cxsin $c0
@@ -596,7 +596,7 @@ crypt_ofb_prep:
cxsout $c0
ret
-crypt_ctr_prep:
+sec_ctr_prep:
cs0begin 5
cenc $c1 $c6
cadd $c6 1
@@ -605,14 +605,14 @@ crypt_ctr_prep:
cxsout $c0
ret
-crypt_cbc_mac_prep:
+sec_cbc_mac_prep:
cs0begin 3
cxsin $c0
cxor $c6 $c0
cenc $c6 $c6
ret
-crypt_cmac_finish_complete_prep:
+sec_cmac_finish_complete_prep:
cs0begin 7
cxsin $c0
cxor $c6 $c0
@@ -623,7 +623,7 @@ crypt_cmac_finish_complete_prep:
cenc $c6 $c6
ret
-crypt_cmac_finish_partial_prep:
+sec_cmac_finish_partial_prep:
cs0begin 8
cxsin $c0
cxor $c6 $c0
@@ -636,12 +636,12 @@ crypt_cmac_finish_partial_prep:
ret
// TODO
-crypt_do_in:
+sec_do_in:
add b32 $r3 $r5
mov $xdbase $r4
mov $r9 #swap
sethi $r9 0x20000
- crypt_do_in_loop:
+ sec_do_in_loop:
xdld $r5 $r9
xdwait
cxset 0x22
@@ -650,17 +650,17 @@ crypt_do_in:
xdwait
add b32 $r5 0x10
cmpu b32 $r5 $r3
- bra ne #crypt_do_in_loop
+ bra ne #sec_do_in_loop
cxset 1
xdwait
ret
-crypt_do_out:
+sec_do_out:
add b32 $r3 $r7
mov $xdbase $r6
mov $r9 #swap
sethi $r9 0x20000
- crypt_do_out_loop:
+ sec_do_out_loop:
cs0exec 1
cxset 0x61
xdld $r7 $r9
@@ -669,14 +669,14 @@ crypt_do_out:
xdwait
add b32 $r7 0x10
cmpu b32 $r7 $r3
- bra ne #crypt_do_out_loop
+ bra ne #sec_do_out_loop
ret
-crypt_do_inout:
+sec_do_inout:
add b32 $r3 $r5
mov $r9 #swap
sethi $r9 0x20000
- crypt_do_inout_loop:
+ sec_do_inout_loop:
mov $xdbase $r4
xdld $r5 $r9
xdwait
@@ -692,7 +692,7 @@ crypt_do_inout:
add b32 $r5 0x10
add b32 $r7 0x10
cmpu b32 $r5 $r3
- bra ne #crypt_do_inout_loop
+ bra ne #sec_do_inout_loop
ret
.align 0x100
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s.h b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s.h
similarity index 90%
rename from drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s.h
index 38676c74e6e0..f7e1e135b59b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s.h
@@ -1,4 +1,4 @@
-uint32_t nv98_pcrypt_data[] = {
+uint32_t nv98_psec_data[] = {
/* 0x0000: ctx_dma */
/* 0x0000: ctx_dma_query */
0x00000000,
@@ -103,7 +103,7 @@ uint32_t nv98_pcrypt_data[] = {
0xfffffff0,
0x00010285,
0xf000000f,
-/* 0x0150: crypt_dtable */
+/* 0x0150: sec_dtable */
0x04db0321,
0x04b1032f,
0x04db0339,
@@ -150,7 +150,7 @@ uint32_t nv98_pcrypt_data[] = {
0x00000000,
};
-uint32_t nv98_pcrypt_code[] = {
+uint32_t nv98_psec_code[] = {
0x17f004bd,
0x0010fe35,
0xf10004fe,
@@ -329,14 +329,14 @@ uint32_t nv98_pcrypt_code[] = {
0xbd220027,
0x0133f034,
0xf80023d0,
-/* 0x0271: crypt_cmd_mode */
+/* 0x0271: sec_cmd_mode */
0x0131f400,
0xb00225f0,
0x18f40f34,
0x0132f409,
-/* 0x0283: crypt_cmd_mode_return */
+/* 0x0283: sec_cmd_mode_return */
0xf80d0380,
-/* 0x0285: crypt_cmd_length */
+/* 0x0285: sec_cmd_length */
0x0034b000,
0xf4fb0bf4,
0x47f0033c,
@@ -376,33 +376,33 @@ uint32_t nv98_pcrypt_code[] = {
0xf05047f0,
0x04fa0643,
0xf803f805,
-/* 0x0321: crypt_copy_prep */
+/* 0x0321: sec_copy_prep */
0x203cf500,
0x003cf594,
0x003cf588,
-/* 0x032f: crypt_store_prep */
+/* 0x032f: sec_store_prep */
0xf500f88c,
0xf594103c,
0xf88c063c,
-/* 0x0339: crypt_ecb_e_prep */
+/* 0x0339: sec_ecb_e_prep */
0x303cf500,
0x003cf594,
0x003cf588,
0x003cf5d0,
-/* 0x034b: crypt_ecb_d_prep */
+/* 0x034b: sec_ecb_d_prep */
0xf500f88c,
0xf5c8773c,
0xf594303c,
0xf588003c,
0xf5d4003c,
0xf88c003c,
-/* 0x0361: crypt_cbc_e_prep */
+/* 0x0361: sec_cbc_e_prep */
0x403cf500,
0x003cf594,
0x063cf588,
0x663cf5ac,
0x063cf5d0,
-/* 0x0377: crypt_cbc_d_prep */
+/* 0x0377: sec_cbc_d_prep */
0xf500f88c,
0xf5c8773c,
0xf594503c,
@@ -411,14 +411,14 @@ uint32_t nv98_pcrypt_code[] = {
0xf5d4603c,
0xf5ac203c,
0xf88c003c,
-/* 0x0395: crypt_pcbc_e_prep */
+/* 0x0395: sec_pcbc_e_prep */
0x503cf500,
0x003cf594,
0x063cf588,
0x663cf5ac,
0x063cf5d0,
0x063cf58c,
-/* 0x03af: crypt_pcbc_d_prep */
+/* 0x03af: sec_pcbc_d_prep */
0xf500f8ac,
0xf5c8773c,
0xf594503c,
@@ -427,26 +427,26 @@ uint32_t nv98_pcrypt_code[] = {
0xf5ac163c,
0xf58c063c,
0xf8ac063c,
-/* 0x03cd: crypt_cfb_e_prep */
+/* 0x03cd: sec_cfb_e_prep */
0x403cf500,
0x663cf594,
0x003cf5d0,
0x063cf588,
0x063cf5ac,
-/* 0x03e3: crypt_cfb_d_prep */
+/* 0x03e3: sec_cfb_d_prep */
0xf500f88c,
0xf594403c,
0xf5d0603c,
0xf588063c,
0xf5ac603c,
0xf88c003c,
-/* 0x03f9: crypt_ofb_prep */
+/* 0x03f9: sec_ofb_prep */
0x403cf500,
0x663cf594,
0x003cf5d0,
0x603cf588,
0x003cf5ac,
-/* 0x040f: crypt_ctr_prep */
+/* 0x040f: sec_ctr_prep */
0xf500f88c,
0xf594503c,
0xf5d0613c,
@@ -454,12 +454,12 @@ uint32_t nv98_pcrypt_code[] = {
0xf588003c,
0xf5ac103c,
0xf88c003c,
-/* 0x0429: crypt_cbc_mac_prep */
+/* 0x0429: sec_cbc_mac_prep */
0x303cf500,
0x003cf594,
0x063cf588,
0x663cf5ac,
-/* 0x043b: crypt_cmac_finish_complete_prep */
+/* 0x043b: sec_cmac_finish_complete_prep */
0xf500f8d0,
0xf594703c,
0xf588003c,
@@ -469,7 +469,7 @@ uint32_t nv98_pcrypt_code[] = {
0xf5bc003c,
0xf5ac063c,
0xf8d0663c,
-/* 0x045d: crypt_cmac_finish_partial_prep */
+/* 0x045d: sec_cmac_finish_partial_prep */
0x803cf500,
0x003cf594,
0x063cf588,
@@ -479,12 +479,12 @@ uint32_t nv98_pcrypt_code[] = {
0x003cf5bc,
0x063cf5bc,
0x663cf5ac,
-/* 0x0483: crypt_do_in */
+/* 0x0483: sec_do_in */
0xbb00f8d0,
0x47fe0035,
0x8097f100,
0x0293f000,
-/* 0x0490: crypt_do_in_loop */
+/* 0x0490: sec_do_in_loop */
0xf80559fa,
0x223cf403,
0xf50609fa,
@@ -493,11 +493,11 @@ uint32_t nv98_pcrypt_code[] = {
0xf40453b8,
0x3cf4e91b,
0xf803f801,
-/* 0x04b1: crypt_do_out */
+/* 0x04b1: sec_do_out */
0x0037bb00,
0xf10067fe,
0xf0008097,
-/* 0x04be: crypt_do_out_loop */
+/* 0x04be: sec_do_out_loop */
0x3cf50293,
0x3cf49810,
0x0579fa61,
@@ -505,11 +505,11 @@ uint32_t nv98_pcrypt_code[] = {
0x03f8013c,
0xb81070b6,
0x1bf40473,
-/* 0x04db: crypt_do_inout */
+/* 0x04db: sec_do_inout */
0xbb00f8e8,
0x97f10035,
0x93f00080,
-/* 0x04e5: crypt_do_inout_loop */
+/* 0x04e5: sec_do_inout_loop */
0x0047fe02,
0xf80559fa,
0x213cf403,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/nv98.c
similarity index 80%
rename from drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/sec/nv98.c
index e0838c46ec17..10d0d1ff2694 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/nv98.c
@@ -32,11 +32,11 @@
#include <engine/falcon.h>
#include <engine/fifo.h>
-#include <engine/crypt.h>
+#include <engine/sec.h>
#include "fuc/nv98.fuc0s.h"
-struct nv98_crypt_priv {
+struct nv98_sec_priv {
struct nouveau_falcon base;
};
@@ -45,18 +45,18 @@ struct nv98_crypt_priv {
******************************************************************************/
static struct nouveau_oclass
-nv98_crypt_sclass[] = {
+nv98_sec_sclass[] = {
{ 0x88b4, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
- * PCRYPT context
+ * PSEC context
******************************************************************************/
static struct nouveau_oclass
-nv98_crypt_cclass = {
- .handle = NV_ENGCTX(CRYPT, 0x98),
+nv98_sec_cclass = {
+ .handle = NV_ENGCTX(SEC, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@@ -68,10 +68,10 @@ nv98_crypt_cclass = {
};
/*******************************************************************************
- * PCRYPT engine/subdev functions
+ * PSEC engine/subdev functions
******************************************************************************/
-static const struct nouveau_enum nv98_crypt_isr_error_name[] = {
+static const struct nouveau_enum nv98_sec_isr_error_name[] = {
{ 0x0000, "ILLEGAL_MTHD" },
{ 0x0001, "INVALID_BITFIELD" },
{ 0x0002, "INVALID_ENUM" },
@@ -80,12 +80,12 @@ static const struct nouveau_enum nv98_crypt_isr_error_name[] = {
};
static void
-nv98_crypt_intr(struct nouveau_subdev *subdev)
+nv98_sec_intr(struct nouveau_subdev *subdev)
{
struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
struct nouveau_engine *engine = nv_engine(subdev);
struct nouveau_object *engctx;
- struct nv98_crypt_priv *priv = (void *)subdev;
+ struct nv98_sec_priv *priv = (void *)subdev;
u32 disp = nv_rd32(priv, 0x08701c);
u32 stat = nv_rd32(priv, 0x087008) & disp & ~(disp >> 16);
u32 inst = nv_rd32(priv, 0x087050) & 0x3fffffff;
@@ -101,7 +101,7 @@ nv98_crypt_intr(struct nouveau_subdev *subdev)
if (stat & 0x00000040) {
nv_error(priv, "DISPATCH_ERROR [");
- nouveau_enum_print(nv98_crypt_isr_error_name, ssta);
+ nouveau_enum_print(nv98_sec_isr_error_name, ssta);
pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
chid, (u64)inst << 12, nouveau_client_name(engctx),
subc, mthd, data);
@@ -118,35 +118,35 @@ nv98_crypt_intr(struct nouveau_subdev *subdev)
}
static int
-nv98_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv98_sec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv98_crypt_priv *priv;
+ struct nv98_sec_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x087000, true,
- "PCRYPT", "crypt", &priv);
+ "PSEC", "sec", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00004000;
- nv_subdev(priv)->intr = nv98_crypt_intr;
- nv_engine(priv)->cclass = &nv98_crypt_cclass;
- nv_engine(priv)->sclass = nv98_crypt_sclass;
- nv_falcon(priv)->code.data = nv98_pcrypt_code;
- nv_falcon(priv)->code.size = sizeof(nv98_pcrypt_code);
- nv_falcon(priv)->data.data = nv98_pcrypt_data;
- nv_falcon(priv)->data.size = sizeof(nv98_pcrypt_data);
+ nv_subdev(priv)->intr = nv98_sec_intr;
+ nv_engine(priv)->cclass = &nv98_sec_cclass;
+ nv_engine(priv)->sclass = nv98_sec_sclass;
+ nv_falcon(priv)->code.data = nv98_psec_code;
+ nv_falcon(priv)->code.size = sizeof(nv98_psec_code);
+ nv_falcon(priv)->data.data = nv98_psec_data;
+ nv_falcon(priv)->data.size = sizeof(nv98_psec_data);
return 0;
}
struct nouveau_oclass
-nv98_crypt_oclass = {
- .handle = NV_ENGINE(CRYPT, 0x98),
+nv98_sec_oclass = {
+ .handle = NV_ENGINE(SEC, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv98_crypt_ctor,
+ .ctor = nv98_sec_ctor,
.dtor = _nouveau_falcon_dtor,
.init = _nouveau_falcon_init,
.fini = _nouveau_falcon_fini,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c
index a7c80ded77cd..c4f4c158dc1b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c
@@ -36,7 +36,7 @@ nv84_devinit_disable(struct nouveau_devinit *devinit)
disable |= (1ULL << NVDEV_ENGINE_MPEG);
disable |= (1ULL << NVDEV_ENGINE_VP);
disable |= (1ULL << NVDEV_ENGINE_BSP);
- disable |= (1ULL << NVDEV_ENGINE_CRYPT);
+ disable |= (1ULL << NVDEV_ENGINE_CIPHER);
}
if (!(r00154c & 0x00000004))
@@ -44,7 +44,7 @@ nv84_devinit_disable(struct nouveau_devinit *devinit)
if (!(r00154c & 0x00000020))
disable |= (1ULL << NVDEV_ENGINE_BSP);
if (!(r00154c & 0x00000040))
- disable |= (1ULL << NVDEV_ENGINE_CRYPT);
+ disable |= (1ULL << NVDEV_ENGINE_CIPHER);
return disable;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
index 820f069fbaac..b27984bbfebb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
@@ -43,7 +43,7 @@ nv98_devinit_disable(struct nouveau_devinit *devinit)
if (!(r00154c & 0x00000020))
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
if (!(r00154c & 0x00000040))
- disable |= (1ULL << NVDEV_ENGINE_CRYPT);
+ disable |= (1ULL << NVDEV_ENGINE_SEC);
return disable;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
index df07c046213e..31c90dbea579 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
@@ -124,7 +124,7 @@ static const struct nouveau_enum vm_engine[] = {
{ 0x00000008, "PPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG },
{ 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP },
- { 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CRYPT },
+ { 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CIPHER },
{ 0x0000000b, "PCOUNTER", NULL },
{ 0x0000000c, "SEMAPHORE_BG", NULL },
{ 0x0000000d, "PCOPY", NULL, NVDEV_ENGINE_COPY0 },
@@ -192,6 +192,8 @@ nv50_fb_intr(struct nouveau_subdev *subdev)
/*XXX: clean this up */
if (!engine && en->data2 == NVDEV_ENGINE_BSP)
engine = nouveau_engine(subdev, NVDEV_ENGINE_MSVLD);
+ if (!engine && en->data2 == NVDEV_ENGINE_CIPHER)
+ engine = nouveau_engine(subdev, NVDEV_ENGINE_SEC);
if (engine) {
engctx = nouveau_engctx_get(engine, chan);
if (engctx)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
index 9ca93e2718f7..9100f2875636 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
@@ -30,7 +30,7 @@ nv50_mc_intr[] = {
{ 0x00000001, NVDEV_ENGINE_MPEG },
{ 0x00000100, NVDEV_ENGINE_FIFO },
{ 0x00001000, NVDEV_ENGINE_GR },
- { 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84- */
+ { 0x00004000, NVDEV_ENGINE_CIPHER }, /* NV84- */
{ 0x00008000, NVDEV_ENGINE_BSP }, /* NV84- */
{ 0x00020000, NVDEV_ENGINE_VP }, /* NV84- */
{ 0x00100000, NVDEV_SUBDEV_TIMER },
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
index bb1346f6fa12..17ea7e74ed28 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
@@ -30,7 +30,7 @@ nv98_mc_intr[] = {
{ 0x00000001, NVDEV_ENGINE_PPP },
{ 0x00000100, NVDEV_ENGINE_FIFO },
{ 0x00001000, NVDEV_ENGINE_GR },
- { 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84:NVA3 */
+ { 0x00004000, NVDEV_ENGINE_SEC }, /* NV84:NVA3 */
{ 0x00008000, NVDEV_ENGINE_MSVLD },
{ 0x00020000, NVDEV_ENGINE_VP },
{ 0x00040000, NVDEV_SUBDEV_PMU }, /* NVA3:NVC0 */
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
index eabf2bab1d10..9a8cbfb0718e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
@@ -171,15 +171,16 @@ nv50_vm_flush(struct nouveau_vm *vm)
}
switch (i) {
- case NVDEV_ENGINE_GR : vme = 0x00; break;
- case NVDEV_ENGINE_VP : vme = 0x01; break;
- case NVDEV_SUBDEV_BAR : vme = 0x06; break;
- case NVDEV_ENGINE_PPP :
- case NVDEV_ENGINE_MPEG : vme = 0x08; break;
- case NVDEV_ENGINE_BSP :
- case NVDEV_ENGINE_MSVLD: vme = 0x09; break;
- case NVDEV_ENGINE_CRYPT: vme = 0x0a; break;
- case NVDEV_ENGINE_COPY0: vme = 0x0d; break;
+ case NVDEV_ENGINE_GR : vme = 0x00; break;
+ case NVDEV_ENGINE_VP : vme = 0x01; break;
+ case NVDEV_SUBDEV_BAR : vme = 0x06; break;
+ case NVDEV_ENGINE_PPP :
+ case NVDEV_ENGINE_MPEG : vme = 0x08; break;
+ case NVDEV_ENGINE_BSP :
+ case NVDEV_ENGINE_MSVLD : vme = 0x09; break;
+ case NVDEV_ENGINE_CIPHER:
+ case NVDEV_ENGINE_SEC : vme = 0x0a; break;
+ case NVDEV_ENGINE_COPY0 : vme = 0x0d; break;
default:
continue;
}
From aedf24ff354e3d8f32f0264edcb37f07a1826f59 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 11:50:20 +1000
Subject: [PATCH 42/86] drm/nouveau/ce: rename from copy (no binary change)
Switch to NVIDIA's name for the device.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/include/nvif/class.h | 6 +-
.../drm/nouveau/include/nvkm/core/device.h | 6 +-
.../gpu/drm/nouveau/include/nvkm/engine/ce.h | 13 +++
.../drm/nouveau/include/nvkm/engine/copy.h | 13 ---
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 2 +-
drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild | 3 +
.../nvkm/engine/{copy => ce}/fuc/com.fuc | 8 +-
.../nvkm/engine/{copy => ce}/fuc/nva3.fuc3 | 0
.../nvkm/engine/{copy => ce}/fuc/nva3.fuc3.h | 4 +-
.../nvkm/engine/{copy => ce}/fuc/nvc0.fuc3 | 0
.../nvkm/engine/{copy => ce}/fuc/nvc0.fuc3.h | 4 +-
.../nouveau/nvkm/engine/{copy => ce}/nva3.c | 46 +++++-----
.../nouveau/nvkm/engine/{copy => ce}/nvc0.c | 88 +++++++++----------
.../nouveau/nvkm/engine/{copy => ce}/nve0.c | 78 ++++++++--------
.../gpu/drm/nouveau/nvkm/engine/copy/Kbuild | 3 -
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 6 +-
.../drm/nouveau/nvkm/engine/device/gm100.c | 14 +--
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 10 +--
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 28 +++---
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 46 +++++-----
.../gpu/drm/nouveau/nvkm/engine/fifo/nv84.c | 10 +--
.../gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c | 24 ++---
.../gpu/drm/nouveau/nvkm/engine/fifo/nve0.c | 32 +++----
.../drm/nouveau/nvkm/subdev/devinit/gm107.c | 4 +-
.../drm/nouveau/nvkm/subdev/devinit/nva3.c | 2 +-
.../drm/nouveau/nvkm/subdev/devinit/nvaf.c | 2 +-
.../drm/nouveau/nvkm/subdev/devinit/nvc0.c | 4 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c | 6 +-
.../gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 2 +-
31 files changed, 234 insertions(+), 234 deletions(-)
create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/copy.h
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild
rename drivers/gpu/drm/nouveau/nvkm/engine/{copy => ce}/fuc/com.fuc (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{copy => ce}/fuc/nva3.fuc3 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{copy => ce}/fuc/nva3.fuc3.h (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{copy => ce}/fuc/nvc0.fuc3 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{copy => ce}/fuc/nvc0.fuc3.h (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{copy => ce}/nva3.c (81%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{copy => ce}/nvc0.c (67%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{copy => ce}/nve0.c (71%)
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/copy/Kbuild
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h
index d5da658d9d43..0fe20917e05d 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
@@ -129,11 +129,11 @@ struct nv_device_v0 {
#define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL
#define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL
#define NV_DEVICE_V0_DISABLE_PPP 0x0000004000000000ULL
-#define NV_DEVICE_V0_DISABLE_COPY0 0x0000008000000000ULL
-#define NV_DEVICE_V0_DISABLE_COPY1 0x0000010000000000ULL
+#define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL
+#define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL
#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
#define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL
-#define NV_DEVICE_V0_DISABLE_COPY2 0x0000080000000000ULL
+#define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL
#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL
#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL
__u64 disable; /* disable particular subsystems */
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index cefa8774e11c..952e36cdb71c 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -52,9 +52,9 @@ enum nv_subdev_type {
NVDEV_ENGINE_CIPHER,
NVDEV_ENGINE_BSP,
NVDEV_ENGINE_PPP,
- NVDEV_ENGINE_COPY0,
- NVDEV_ENGINE_COPY1,
- NVDEV_ENGINE_COPY2,
+ NVDEV_ENGINE_CE0,
+ NVDEV_ENGINE_CE1,
+ NVDEV_ENGINE_CE2,
NVDEV_ENGINE_VIC,
NVDEV_ENGINE_VENC,
NVDEV_ENGINE_DISP,
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
new file mode 100644
index 000000000000..639d0fd64cad
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
@@ -0,0 +1,13 @@
+#ifndef __NVKM_CE_H__
+#define __NVKM_CE_H__
+
+void nva3_ce_intr(struct nouveau_subdev *);
+
+extern struct nouveau_oclass nva3_ce_oclass;
+extern struct nouveau_oclass nvc0_ce0_oclass;
+extern struct nouveau_oclass nvc0_ce1_oclass;
+extern struct nouveau_oclass nve0_ce0_oclass;
+extern struct nouveau_oclass nve0_ce1_oclass;
+extern struct nouveau_oclass nve0_ce2_oclass;
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/copy.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/copy.h
deleted file mode 100644
index 316a28ae5f5c..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/copy.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __NOUVEAU_COPY_H__
-#define __NOUVEAU_COPY_H__
-
-void nva3_copy_intr(struct nouveau_subdev *);
-
-extern struct nouveau_oclass nva3_copy_oclass;
-extern struct nouveau_oclass nvc0_copy0_oclass;
-extern struct nouveau_oclass nvc0_copy1_oclass;
-extern struct nouveau_oclass nve0_copy0_oclass;
-extern struct nouveau_oclass nve0_copy1_oclass;
-extern struct nouveau_oclass nve0_copy2_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
index aad171d3cbcc..71d6542147a2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
@@ -3,7 +3,7 @@ nvkm-y += nvkm/engine/xtensa.o
include $(src)/nvkm/engine/bsp/Kbuild
include $(src)/nvkm/engine/cipher/Kbuild
-include $(src)/nvkm/engine/copy/Kbuild
+include $(src)/nvkm/engine/ce/Kbuild
include $(src)/nvkm/engine/device/Kbuild
include $(src)/nvkm/engine/disp/Kbuild
include $(src)/nvkm/engine/dmaobj/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild
new file mode 100644
index 000000000000..834523d8420f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild
@@ -0,0 +1,3 @@
+nvkm-y += nvkm/engine/ce/nva3.o
+nvkm-y += nvkm/engine/ce/nvc0.o
+nvkm-y += nvkm/engine/ce/nve0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/com.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/com.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc
index 33b67dc711ac..fcc4ba172443 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/com.fuc
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc
@@ -31,9 +31,9 @@
*/
#ifdef NVA3
-.section #nva3_pcopy_data
+.section #nva3_pce_data
#else
-.section #nvc0_pcopy_data
+.section #nvc0_pce_data
#endif
ctx_object: .b32 0
@@ -135,9 +135,9 @@ dispatch_dma:
.b16 0x800 0
#ifdef NVA3
-.section #nva3_pcopy_code
+.section #nva3_pce_code
#else
-.section #nvc0_pcopy_code
+.section #nvc0_pce_code
#endif
main:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3.h
index 241b27201206..362872df592a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nva3.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nva3_pcopy_data[] = {
+uint32_t nva3_pce_data[] = {
/* 0x0000: ctx_object */
0x00000000,
/* 0x0004: ctx_dma */
@@ -183,7 +183,7 @@ uint32_t nva3_pcopy_data[] = {
0x00000800,
};
-uint32_t nva3_pcopy_code[] = {
+uint32_t nva3_pce_code[] = {
/* 0x0000: main */
0x04fe04bd,
0x3517f000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3.h
index 98cc4216a372..042257daef8b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/fuc/nvc0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvc0_pcopy_data[] = {
+uint32_t nvc0_pce_data[] = {
/* 0x0000: ctx_object */
0x00000000,
/* 0x0004: ctx_query_address_high */
@@ -171,7 +171,7 @@ uint32_t nvc0_pcopy_data[] = {
0x00000800,
};
-uint32_t nvc0_pcopy_code[] = {
+uint32_t nvc0_pce_code[] = {
/* 0x0000: main */
0x04fe04bd,
0x3517f000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c
similarity index 81%
rename from drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c
index 6ae64969e2e5..b193b5f4037a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c
@@ -24,7 +24,7 @@
#include <engine/falcon.h>
#include <engine/fifo.h>
-#include <engine/copy.h>
+#include <engine/ce.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>
@@ -35,7 +35,7 @@
#include "fuc/nva3.fuc3.h"
-struct nva3_copy_priv {
+struct nva3_ce_priv {
struct nouveau_falcon base;
};
@@ -44,18 +44,18 @@ struct nva3_copy_priv {
******************************************************************************/
static struct nouveau_oclass
-nva3_copy_sclass[] = {
+nva3_ce_sclass[] = {
{ 0x85b5, &nouveau_object_ofuncs },
{}
};
/*******************************************************************************
- * PCOPY context
+ * PCE context
******************************************************************************/
static struct nouveau_oclass
-nva3_copy_cclass = {
- .handle = NV_ENGCTX(COPY0, 0xa3),
+nva3_ce_cclass = {
+ .handle = NV_ENGCTX(CE0, 0xa3),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@@ -68,10 +68,10 @@ nva3_copy_cclass = {
};
/*******************************************************************************
- * PCOPY engine/subdev functions
+ * PCE engine/subdev functions
******************************************************************************/
-static const struct nouveau_enum nva3_copy_isr_error_name[] = {
+static const struct nouveau_enum nva3_ce_isr_error_name[] = {
{ 0x0001, "ILLEGAL_MTHD" },
{ 0x0002, "INVALID_ENUM" },
{ 0x0003, "INVALID_BITFIELD" },
@@ -79,7 +79,7 @@ static const struct nouveau_enum nva3_copy_isr_error_name[] = {
};
void
-nva3_copy_intr(struct nouveau_subdev *subdev)
+nva3_ce_intr(struct nouveau_subdev *subdev)
{
struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
struct nouveau_engine *engine = nv_engine(subdev);
@@ -100,7 +100,7 @@ nva3_copy_intr(struct nouveau_subdev *subdev)
if (stat & 0x00000040) {
nv_error(falcon, "DISPATCH_ERROR [");
- nouveau_enum_print(nva3_copy_isr_error_name, ssta);
+ nouveau_enum_print(nva3_ce_isr_error_name, ssta);
pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
chid, inst << 12, nouveau_client_name(engctx), subc,
mthd, data);
@@ -117,36 +117,36 @@ nva3_copy_intr(struct nouveau_subdev *subdev)
}
static int
-nva3_copy_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nva3_ce_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
bool enable = (nv_device(parent)->chipset != 0xaf);
- struct nva3_copy_priv *priv;
+ struct nva3_ce_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, enable,
- "PCE0", "copy0", &priv);
+ "PCE0", "ce0", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00802000;
- nv_subdev(priv)->intr = nva3_copy_intr;
- nv_engine(priv)->cclass = &nva3_copy_cclass;
- nv_engine(priv)->sclass = nva3_copy_sclass;
- nv_falcon(priv)->code.data = nva3_pcopy_code;
- nv_falcon(priv)->code.size = sizeof(nva3_pcopy_code);
- nv_falcon(priv)->data.data = nva3_pcopy_data;
- nv_falcon(priv)->data.size = sizeof(nva3_pcopy_data);
+ nv_subdev(priv)->intr = nva3_ce_intr;
+ nv_engine(priv)->cclass = &nva3_ce_cclass;
+ nv_engine(priv)->sclass = nva3_ce_sclass;
+ nv_falcon(priv)->code.data = nva3_pce_code;
+ nv_falcon(priv)->code.size = sizeof(nva3_pce_code);
+ nv_falcon(priv)->data.data = nva3_pce_data;
+ nv_falcon(priv)->data.size = sizeof(nva3_pce_data);
return 0;
}
struct nouveau_oclass
-nva3_copy_oclass = {
- .handle = NV_ENGINE(COPY0, 0xa3),
+nva3_ce_oclass = {
+ .handle = NV_ENGINE(CE0, 0xa3),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nva3_copy_ctor,
+ .ctor = nva3_ce_ctor,
.dtor = _nouveau_falcon_dtor,
.init = _nouveau_falcon_init,
.fini = _nouveau_falcon_fini,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c
similarity index 67%
rename from drivers/gpu/drm/nouveau/nvkm/engine/copy/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c
index abe324993eaf..f5dff133362d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c
@@ -24,14 +24,14 @@
#include <engine/falcon.h>
#include <engine/fifo.h>
-#include <engine/copy.h>
+#include <engine/ce.h>
#include <core/enum.h>
#include <core/enum.h>
#include "fuc/nvc0.fuc3.h"
-struct nvc0_copy_priv {
+struct nvc0_ce_priv {
struct nouveau_falcon base;
};
@@ -40,23 +40,23 @@ struct nvc0_copy_priv {
******************************************************************************/
static struct nouveau_oclass
-nvc0_copy0_sclass[] = {
+nvc0_ce0_sclass[] = {
{ 0x90b5, &nouveau_object_ofuncs },
{},
};
static struct nouveau_oclass
-nvc0_copy1_sclass[] = {
+nvc0_ce1_sclass[] = {
{ 0x90b8, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
- * PCOPY context
+ * PCE context
******************************************************************************/
static struct nouveau_ofuncs
-nvc0_copy_context_ofuncs = {
+nvc0_ce_context_ofuncs = {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
.init = _nouveau_falcon_context_init,
@@ -66,92 +66,92 @@ nvc0_copy_context_ofuncs = {
};
static struct nouveau_oclass
-nvc0_copy0_cclass = {
- .handle = NV_ENGCTX(COPY0, 0xc0),
- .ofuncs = &nvc0_copy_context_ofuncs,
+nvc0_ce0_cclass = {
+ .handle = NV_ENGCTX(CE0, 0xc0),
+ .ofuncs = &nvc0_ce_context_ofuncs,
};
static struct nouveau_oclass
-nvc0_copy1_cclass = {
- .handle = NV_ENGCTX(COPY1, 0xc0),
- .ofuncs = &nvc0_copy_context_ofuncs,
+nvc0_ce1_cclass = {
+ .handle = NV_ENGCTX(CE1, 0xc0),
+ .ofuncs = &nvc0_ce_context_ofuncs,
};
/*******************************************************************************
- * PCOPY engine/subdev functions
+ * PCE engine/subdev functions
******************************************************************************/
static int
-nvc0_copy_init(struct nouveau_object *object)
+nvc0_ce_init(struct nouveau_object *object)
{
- struct nvc0_copy_priv *priv = (void *)object;
+ struct nvc0_ce_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
if (ret)
return ret;
- nv_wo32(priv, 0x084, nv_engidx(&priv->base.base) - NVDEV_ENGINE_COPY0);
+ nv_wo32(priv, 0x084, nv_engidx(&priv->base.base) - NVDEV_ENGINE_CE0);
return 0;
}
static int
-nvc0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvc0_ce0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvc0_copy_priv *priv;
+ struct nvc0_ce_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, true,
- "PCE0", "copy0", &priv);
+ "PCE0", "ce0", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000040;
- nv_subdev(priv)->intr = nva3_copy_intr;
- nv_engine(priv)->cclass = &nvc0_copy0_cclass;
- nv_engine(priv)->sclass = nvc0_copy0_sclass;
- nv_falcon(priv)->code.data = nvc0_pcopy_code;
- nv_falcon(priv)->code.size = sizeof(nvc0_pcopy_code);
- nv_falcon(priv)->data.data = nvc0_pcopy_data;
- nv_falcon(priv)->data.size = sizeof(nvc0_pcopy_data);
+ nv_subdev(priv)->intr = nva3_ce_intr;
+ nv_engine(priv)->cclass = &nvc0_ce0_cclass;
+ nv_engine(priv)->sclass = nvc0_ce0_sclass;
+ nv_falcon(priv)->code.data = nvc0_pce_code;
+ nv_falcon(priv)->code.size = sizeof(nvc0_pce_code);
+ nv_falcon(priv)->data.data = nvc0_pce_data;
+ nv_falcon(priv)->data.size = sizeof(nvc0_pce_data);
return 0;
}
static int
-nvc0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvc0_ce1_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvc0_copy_priv *priv;
+ struct nvc0_ce_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x105000, true,
- "PCE1", "copy1", &priv);
+ "PCE1", "ce1", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000080;
- nv_subdev(priv)->intr = nva3_copy_intr;
- nv_engine(priv)->cclass = &nvc0_copy1_cclass;
- nv_engine(priv)->sclass = nvc0_copy1_sclass;
- nv_falcon(priv)->code.data = nvc0_pcopy_code;
- nv_falcon(priv)->code.size = sizeof(nvc0_pcopy_code);
- nv_falcon(priv)->data.data = nvc0_pcopy_data;
- nv_falcon(priv)->data.size = sizeof(nvc0_pcopy_data);
+ nv_subdev(priv)->intr = nva3_ce_intr;
+ nv_engine(priv)->cclass = &nvc0_ce1_cclass;
+ nv_engine(priv)->sclass = nvc0_ce1_sclass;
+ nv_falcon(priv)->code.data = nvc0_pce_code;
+ nv_falcon(priv)->code.size = sizeof(nvc0_pce_code);
+ nv_falcon(priv)->data.data = nvc0_pce_data;
+ nv_falcon(priv)->data.size = sizeof(nvc0_pce_data);
return 0;
}
struct nouveau_oclass
-nvc0_copy0_oclass = {
- .handle = NV_ENGINE(COPY0, 0xc0),
+nvc0_ce0_oclass = {
+ .handle = NV_ENGINE(CE0, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_copy0_ctor,
+ .ctor = nvc0_ce0_ctor,
.dtor = _nouveau_falcon_dtor,
- .init = nvc0_copy_init,
+ .init = nvc0_ce_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
@@ -159,12 +159,12 @@ nvc0_copy0_oclass = {
};
struct nouveau_oclass
-nvc0_copy1_oclass = {
- .handle = NV_ENGINE(COPY1, 0xc0),
+nvc0_ce1_oclass = {
+ .handle = NV_ENGINE(CE1, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_copy1_ctor,
+ .ctor = nvc0_ce1_ctor,
.dtor = _nouveau_falcon_dtor,
- .init = nvc0_copy_init,
+ .init = nvc0_ce_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nve0.c
similarity index 71%
rename from drivers/gpu/drm/nouveau/nvkm/engine/copy/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/nve0.c
index b140a01dd323..b2b31d1b768c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nve0.c
@@ -26,9 +26,9 @@
#include <core/enum.h>
#include <core/engctx.h>
-#include <engine/copy.h>
+#include <engine/ce.h>
-struct nve0_copy_priv {
+struct nve0_ce_priv {
struct nouveau_engine base;
};
@@ -37,17 +37,17 @@ struct nve0_copy_priv {
******************************************************************************/
static struct nouveau_oclass
-nve0_copy_sclass[] = {
+nve0_ce_sclass[] = {
{ 0xa0b5, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
- * PCOPY context
+ * PCE context
******************************************************************************/
static struct nouveau_ofuncs
-nve0_copy_context_ofuncs = {
+nve0_ce_context_ofuncs = {
.ctor = _nouveau_engctx_ctor,
.dtor = _nouveau_engctx_dtor,
.init = _nouveau_engctx_init,
@@ -57,20 +57,20 @@ nve0_copy_context_ofuncs = {
};
static struct nouveau_oclass
-nve0_copy_cclass = {
- .handle = NV_ENGCTX(COPY0, 0xc0),
- .ofuncs = &nve0_copy_context_ofuncs,
+nve0_ce_cclass = {
+ .handle = NV_ENGCTX(CE0, 0xc0),
+ .ofuncs = &nve0_ce_context_ofuncs,
};
/*******************************************************************************
- * PCOPY engine/subdev functions
+ * PCE engine/subdev functions
******************************************************************************/
static void
-nve0_copy_intr(struct nouveau_subdev *subdev)
+nve0_ce_intr(struct nouveau_subdev *subdev)
{
- const int ce = nv_subidx(subdev) - NVDEV_ENGINE_COPY0;
- struct nve0_copy_priv *priv = (void *)subdev;
+ const int ce = nv_subidx(subdev) - NVDEV_ENGINE_CE0;
+ struct nve0_ce_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000));
if (stat) {
@@ -80,73 +80,73 @@ nve0_copy_intr(struct nouveau_subdev *subdev)
}
static int
-nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nve0_ce0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nve0_copy_priv *priv;
+ struct nve0_ce_priv *priv;
int ret;
ret = nouveau_engine_create(parent, engine, oclass, true,
- "PCE0", "copy0", &priv);
+ "PCE0", "ce0", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000040;
- nv_subdev(priv)->intr = nve0_copy_intr;
- nv_engine(priv)->cclass = &nve0_copy_cclass;
- nv_engine(priv)->sclass = nve0_copy_sclass;
+ nv_subdev(priv)->intr = nve0_ce_intr;
+ nv_engine(priv)->cclass = &nve0_ce_cclass;
+ nv_engine(priv)->sclass = nve0_ce_sclass;
return 0;
}
static int
-nve0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nve0_ce1_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nve0_copy_priv *priv;
+ struct nve0_ce_priv *priv;
int ret;
ret = nouveau_engine_create(parent, engine, oclass, true,
- "PCE1", "copy1", &priv);
+ "PCE1", "ce1", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000080;
- nv_subdev(priv)->intr = nve0_copy_intr;
- nv_engine(priv)->cclass = &nve0_copy_cclass;
- nv_engine(priv)->sclass = nve0_copy_sclass;
+ nv_subdev(priv)->intr = nve0_ce_intr;
+ nv_engine(priv)->cclass = &nve0_ce_cclass;
+ nv_engine(priv)->sclass = nve0_ce_sclass;
return 0;
}
static int
-nve0_copy2_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nve0_ce2_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nve0_copy_priv *priv;
+ struct nve0_ce_priv *priv;
int ret;
ret = nouveau_engine_create(parent, engine, oclass, true,
- "PCE2", "copy2", &priv);
+ "PCE2", "ce2", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00200000;
- nv_subdev(priv)->intr = nve0_copy_intr;
- nv_engine(priv)->cclass = &nve0_copy_cclass;
- nv_engine(priv)->sclass = nve0_copy_sclass;
+ nv_subdev(priv)->intr = nve0_ce_intr;
+ nv_engine(priv)->cclass = &nve0_ce_cclass;
+ nv_engine(priv)->sclass = nve0_ce_sclass;
return 0;
}
struct nouveau_oclass
-nve0_copy0_oclass = {
- .handle = NV_ENGINE(COPY0, 0xe0),
+nve0_ce0_oclass = {
+ .handle = NV_ENGINE(CE0, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_copy0_ctor,
+ .ctor = nve0_ce0_ctor,
.dtor = _nouveau_engine_dtor,
.init = _nouveau_engine_init,
.fini = _nouveau_engine_fini,
@@ -154,10 +154,10 @@ nve0_copy0_oclass = {
};
struct nouveau_oclass
-nve0_copy1_oclass = {
- .handle = NV_ENGINE(COPY1, 0xe0),
+nve0_ce1_oclass = {
+ .handle = NV_ENGINE(CE1, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_copy1_ctor,
+ .ctor = nve0_ce1_ctor,
.dtor = _nouveau_engine_dtor,
.init = _nouveau_engine_init,
.fini = _nouveau_engine_fini,
@@ -165,10 +165,10 @@ nve0_copy1_oclass = {
};
struct nouveau_oclass
-nve0_copy2_oclass = {
- .handle = NV_ENGINE(COPY2, 0xe0),
+nve0_ce2_oclass = {
+ .handle = NV_ENGINE(CE2, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_copy2_ctor,
+ .ctor = nve0_ce2_ctor,
.dtor = _nouveau_engine_dtor,
.init = _nouveau_engine_init,
.fini = _nouveau_engine_fini,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/copy/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/copy/Kbuild
deleted file mode 100644
index d8aa5edba726..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/copy/Kbuild
+++ /dev/null
@@ -1,3 +0,0 @@
-nvkm-y += nvkm/engine/copy/nva3.o
-nvkm-y += nvkm/engine/copy/nvc0.o
-nvkm-y += nvkm/engine/copy/nve0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index fe269ef00355..96050a487226 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -235,9 +235,9 @@ static const u64 disable_map[] = {
[NVDEV_ENGINE_CIPHER] = NV_DEVICE_V0_DISABLE_CIPHER,
[NVDEV_ENGINE_BSP] = NV_DEVICE_V0_DISABLE_BSP,
[NVDEV_ENGINE_PPP] = NV_DEVICE_V0_DISABLE_PPP,
- [NVDEV_ENGINE_COPY0] = NV_DEVICE_V0_DISABLE_COPY0,
- [NVDEV_ENGINE_COPY1] = NV_DEVICE_V0_DISABLE_COPY1,
- [NVDEV_ENGINE_COPY2] = NV_DEVICE_V0_DISABLE_COPY1,
+ [NVDEV_ENGINE_CE0] = NV_DEVICE_V0_DISABLE_CE0,
+ [NVDEV_ENGINE_CE1] = NV_DEVICE_V0_DISABLE_CE1,
+ [NVDEV_ENGINE_CE2] = NV_DEVICE_V0_DISABLE_CE2,
[NVDEV_ENGINE_VIC] = NV_DEVICE_V0_DISABLE_VIC,
[NVDEV_ENGINE_VENC] = NV_DEVICE_V0_DISABLE_VENC,
[NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 391369a1c034..c9c18dc6f216 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -48,7 +48,7 @@
#include <engine/software.h>
#include <engine/graph.h>
#include <engine/disp.h>
-#include <engine/copy.h>
+#include <engine/ce.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/vp.h>
@@ -88,11 +88,11 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
#if 0
- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
#endif
- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
#if 0
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
@@ -134,9 +134,9 @@ gm100_identify(struct nouveau_device *device)
#endif
device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
#if 0
- device->oclass[NVDEV_ENGINE_COPY0 ] = &gm204_copy0_oclass;
- device->oclass[NVDEV_ENGINE_COPY1 ] = &gm204_copy1_oclass;
- device->oclass[NVDEV_ENGINE_COPY2 ] = &gm204_copy2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 2fb06eb451f3..cb978023d472 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -52,7 +52,7 @@
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/ppp.h>
-#include <engine/copy.h>
+#include <engine/ce.h>
#include <engine/disp.h>
#include <engine/perfmon.h>
@@ -374,7 +374,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break;
@@ -404,7 +404,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break;
@@ -434,7 +434,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break;
@@ -464,7 +464,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 0e1be5e2472e..39bf7d115bc6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -51,7 +51,7 @@
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/ppp.h>
-#include <engine/copy.h>
+#include <engine/ce.h>
#include <engine/disp.h>
#include <engine/perfmon.h>
@@ -87,8 +87,8 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
- device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
@@ -120,8 +120,8 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
- device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
@@ -153,7 +153,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
@@ -185,8 +185,8 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
- device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
@@ -218,7 +218,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
@@ -250,7 +250,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
@@ -282,8 +282,8 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
- device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
@@ -315,7 +315,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
@@ -345,7 +345,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 1460a1650d0e..1f6d515fb641 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -48,7 +48,7 @@
#include <engine/software.h>
#include <engine/graph.h>
#include <engine/disp.h>
-#include <engine/copy.h>
+#include <engine/ce.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/vp.h>
@@ -85,9 +85,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -119,9 +119,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -153,9 +153,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -178,7 +178,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk20a_graph_oclass;
- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass;
@@ -209,9 +209,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -243,9 +243,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110b_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -277,9 +277,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -310,9 +310,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
index 392843991663..4a3638e1944e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
@@ -64,7 +64,7 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_MSVLD : addr = 0x0080; break;
case NVDEV_ENGINE_CIPHER:
case NVDEV_ENGINE_SEC : addr = 0x00a0; break;
- case NVDEV_ENGINE_COPY0 : addr = 0x00c0; break;
+ case NVDEV_ENGINE_CE0 : addr = 0x00c0; break;
default:
return -EINVAL;
}
@@ -102,7 +102,7 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break;
case NVDEV_ENGINE_CIPHER:
case NVDEV_ENGINE_SEC : engn = 4; addr = 0x00a0; break;
- case NVDEV_ENGINE_COPY0 : engn = 2; addr = 0x00c0; break;
+ case NVDEV_ENGINE_CE0 : engn = 2; addr = 0x00c0; break;
default:
return -EINVAL;
}
@@ -147,7 +147,7 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_MPEG :
case NVDEV_ENGINE_PPP : context |= 0x00200000; break;
case NVDEV_ENGINE_ME :
- case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
+ case NVDEV_ENGINE_CE0 : context |= 0x00300000; break;
case NVDEV_ENGINE_VP : context |= 0x00400000; break;
case NVDEV_ENGINE_CIPHER:
case NVDEV_ENGINE_SEC :
@@ -196,7 +196,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_PPP) |
- (1ULL << NVDEV_ENGINE_COPY0) |
+ (1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);
if (ret)
@@ -271,7 +271,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_PPP) |
- (1ULL << NVDEV_ENGINE_COPY0) |
+ (1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);
if (ret)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
index 2af40b208860..1511e387fd5d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
@@ -122,8 +122,8 @@ nvc0_fifo_context_attach(struct nouveau_object *parent,
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
- case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
+ case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
+ case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
@@ -159,8 +159,8 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
- case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
+ case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
+ case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
@@ -212,8 +212,8 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent,
args->v0.pushbuf,
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_COPY0) |
- (1ULL << NVDEV_ENGINE_COPY1) |
+ (1ULL << NVDEV_ENGINE_CE0) |
+ (1ULL << NVDEV_ENGINE_CE1) |
(1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_VP) |
(1ULL << NVDEV_ENGINE_PPP), &chan);
@@ -385,8 +385,8 @@ nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
case NVDEV_ENGINE_MSVLD: engn = 1; break;
case NVDEV_ENGINE_PPP : engn = 2; break;
case NVDEV_ENGINE_VP : engn = 3; break;
- case NVDEV_ENGINE_COPY0: engn = 4; break;
- case NVDEV_ENGINE_COPY1: engn = 5; break;
+ case NVDEV_ENGINE_CE0 : engn = 4; break;
+ case NVDEV_ENGINE_CE1 : engn = 5; break;
default:
return -1;
}
@@ -402,8 +402,8 @@ nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
case 1: engn = NVDEV_ENGINE_MSVLD; break;
case 2: engn = NVDEV_ENGINE_PPP; break;
case 3: engn = NVDEV_ENGINE_VP; break;
- case 4: engn = NVDEV_ENGINE_COPY0; break;
- case 5: engn = NVDEV_ENGINE_COPY1; break;
+ case 4: engn = NVDEV_ENGINE_CE0; break;
+ case 5: engn = NVDEV_ENGINE_CE1; break;
default:
return NULL;
}
@@ -552,8 +552,8 @@ nvc0_fifo_fault_engine[] = {
{ 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x13, "PCOUNTER" },
{ 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
- { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 },
- { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 },
+ { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 },
+ { 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 },
{ 0x17, "PDAEMON" },
{}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
index b415b309f4b8..324008e8fa9b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
@@ -47,12 +47,12 @@ static const struct {
u64 mask;
} fifo_engine[] = {
_(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_COPY2)),
+ (1ULL << NVDEV_ENGINE_CE2)),
_(NVDEV_ENGINE_VP , 0),
_(NVDEV_ENGINE_PPP , 0),
_(NVDEV_ENGINE_MSVLD , 0),
- _(NVDEV_ENGINE_COPY0 , 0),
- _(NVDEV_ENGINE_COPY1 , 0),
+ _(NVDEV_ENGINE_CE0 , 0),
+ _(NVDEV_ENGINE_CE1 , 0),
_(NVDEV_ENGINE_VENC , 0),
};
#undef _
@@ -143,9 +143,9 @@ nve0_fifo_context_attach(struct nouveau_object *parent,
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW :
return 0;
- case NVDEV_ENGINE_COPY0:
- case NVDEV_ENGINE_COPY1:
- case NVDEV_ENGINE_COPY2:
+ case NVDEV_ENGINE_CE0:
+ case NVDEV_ENGINE_CE1:
+ case NVDEV_ENGINE_CE2:
nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
return 0;
case NVDEV_ENGINE_GR : addr = 0x0210; break;
@@ -183,9 +183,9 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW : return 0;
- case NVDEV_ENGINE_COPY0:
- case NVDEV_ENGINE_COPY1:
- case NVDEV_ENGINE_COPY2: addr = 0x0000; break;
+ case NVDEV_ENGINE_CE0 :
+ case NVDEV_ENGINE_CE1 :
+ case NVDEV_ENGINE_CE2 : addr = 0x0000; break;
case NVDEV_ENGINE_GR : addr = 0x0210; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
@@ -415,12 +415,12 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
{
switch (engn) {
case NVDEV_ENGINE_GR :
- case NVDEV_ENGINE_COPY2: engn = 0; break;
+ case NVDEV_ENGINE_CE2 : engn = 0; break;
case NVDEV_ENGINE_MSVLD: engn = 1; break;
case NVDEV_ENGINE_PPP : engn = 2; break;
case NVDEV_ENGINE_VP : engn = 3; break;
- case NVDEV_ENGINE_COPY0: engn = 4; break;
- case NVDEV_ENGINE_COPY1: engn = 5; break;
+ case NVDEV_ENGINE_CE0 : engn = 4; break;
+ case NVDEV_ENGINE_CE1 : engn = 5; break;
case NVDEV_ENGINE_VENC : engn = 6; break;
default:
return -1;
@@ -623,11 +623,11 @@ nve0_fifo_fault_engine[] = {
{ 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x13, "PERF" },
{ 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
- { 0x15, "CE0", NULL, NVDEV_ENGINE_COPY0 },
- { 0x16, "CE1", NULL, NVDEV_ENGINE_COPY1 },
+ { 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },
+ { 0x16, "CE1", NULL, NVDEV_ENGINE_CE1 },
{ 0x17, "PMU" },
{ 0x19, "MSENC", NULL, NVDEV_ENGINE_VENC },
- { 0x1b, "CE2", NULL, NVDEV_ENGINE_COPY2 },
+ { 0x1b, "CE2", NULL, NVDEV_ENGINE_CE2 },
{}
};
@@ -678,7 +678,7 @@ nve0_fifo_fault_hubclient[] = {
{ 0x15, "SCC_NB" },
{ 0x16, "SEC" },
{ 0x17, "SSYNC" },
- { 0x18, "GR_COPY" },
+ { 0x18, "GR_CE" },
{ 0x19, "CE2" },
{ 0x1a, "XV" },
{ 0x1b, "MMU_NB" },
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
index 4ba43d6a1ec8..04c04efcc8c4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
@@ -33,9 +33,9 @@ gm107_devinit_disable(struct nouveau_devinit *devinit)
u64 disable = 0ULL;
if (r021c00 & 0x00000001)
- disable |= (1ULL << NVDEV_ENGINE_COPY0);
+ disable |= (1ULL << NVDEV_ENGINE_CE0);
if (r021c00 & 0x00000004)
- disable |= (1ULL << NVDEV_ENGINE_COPY2);
+ disable |= (1ULL << NVDEV_ENGINE_CE2);
if (r021c04 & 0x00000001)
disable |= (1ULL << NVDEV_ENGINE_DISP);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
index f662a261cc65..b116f8040bbc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
@@ -76,7 +76,7 @@ nva3_devinit_disable(struct nouveau_devinit *devinit)
if (!(r00154c & 0x00000020))
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
if (!(r00154c & 0x00000200))
- disable |= (1ULL << NVDEV_ENGINE_COPY0);
+ disable |= (1ULL << NVDEV_ENGINE_CE0);
return disable;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
index 6f8ef894e4ef..140c300c7038 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
@@ -44,7 +44,7 @@ nvaf_devinit_disable(struct nouveau_devinit *devinit)
if (!(r00154c & 0x00000040))
disable |= (1ULL << NVDEV_ENGINE_VIC);
if (!(r00154c & 0x00000200))
- disable |= (1ULL << NVDEV_ENGINE_COPY0);
+ disable |= (1ULL << NVDEV_ENGINE_CE0);
return disable;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
index ac699a366f60..c7b2311f497e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
@@ -79,9 +79,9 @@ nvc0_devinit_disable(struct nouveau_devinit *devinit)
if (r022500 & 0x00000008)
disable |= (1ULL << NVDEV_ENGINE_VENC);
if (r022500 & 0x00000100)
- disable |= (1ULL << NVDEV_ENGINE_COPY0);
+ disable |= (1ULL << NVDEV_ENGINE_CE0);
if (r022500 & 0x00000200)
- disable |= (1ULL << NVDEV_ENGINE_COPY1);
+ disable |= (1ULL << NVDEV_ENGINE_CE1);
return disable;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
index 31c90dbea579..be129c3297a3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
@@ -127,7 +127,7 @@ static const struct nouveau_enum vm_engine[] = {
{ 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CIPHER },
{ 0x0000000b, "PCOUNTER", NULL },
{ 0x0000000c, "SEMAPHORE_BG", NULL },
- { 0x0000000d, "PCOPY", NULL, NVDEV_ENGINE_COPY0 },
+ { 0x0000000d, "PCE0", NULL, NVDEV_ENGINE_CE0 },
{ 0x0000000e, "PDAEMON", NULL },
{}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
index 17ea7e74ed28..60b250f34cd2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
@@ -38,7 +38,7 @@ nv98_mc_intr[] = {
{ 0x00100000, NVDEV_SUBDEV_TIMER },
{ 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */
{ 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */
- { 0x00400000, NVDEV_ENGINE_COPY0 }, /* NVA3- */
+ { 0x00400000, NVDEV_ENGINE_CE0 }, /* NVA3- */
{ 0x10000000, NVDEV_SUBDEV_BUS },
{ 0x80000000, NVDEV_ENGINE_SW },
{ 0x0042d101, NVDEV_SUBDEV_FB },
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
index 1e352152cadd..5217a5a40447 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
@@ -28,9 +28,9 @@ const struct nouveau_mc_intr
nvc0_mc_intr[] = {
{ 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */
{ 0x00000001, NVDEV_ENGINE_PPP },
- { 0x00000020, NVDEV_ENGINE_COPY0 },
- { 0x00000040, NVDEV_ENGINE_COPY1 },
- { 0x00000080, NVDEV_ENGINE_COPY2 },
+ { 0x00000020, NVDEV_ENGINE_CE0 },
+ { 0x00000040, NVDEV_ENGINE_CE1 },
+ { 0x00000080, NVDEV_ENGINE_CE2 },
{ 0x00000100, NVDEV_ENGINE_FIFO },
{ 0x00001000, NVDEV_ENGINE_GR },
{ 0x00002000, NVDEV_SUBDEV_FB },
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
index 9a8cbfb0718e..701b9c4ec869 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
@@ -180,7 +180,7 @@ nv50_vm_flush(struct nouveau_vm *vm)
case NVDEV_ENGINE_MSVLD : vme = 0x09; break;
case NVDEV_ENGINE_CIPHER:
case NVDEV_ENGINE_SEC : vme = 0x0a; break;
- case NVDEV_ENGINE_COPY0 : vme = 0x0d; break;
+ case NVDEV_ENGINE_CE0 : vme = 0x0d; break;
default:
continue;
}
From b8bf04e1fd3aba5cdd81ec766fc0372c7894497c Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 12:02:28 +1000
Subject: [PATCH 43/86] drm/nouveau/gr: rename from graph (no binary change)
Shorter device name, match Tegra and our existing enums.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/include/nvif/class.h | 2 +-
drivers/gpu/drm/nouveau/include/nvif/device.h | 4 +-
.../gpu/drm/nouveau/include/nvkm/engine/gr.h | 86 +++
.../drm/nouveau/include/nvkm/engine/graph.h | 86 ---
drivers/gpu/drm/nouveau/nouveau_abi16.c | 4 +-
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 2 +-
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +-
.../drm/nouveau/nvkm/engine/device/gm100.c | 6 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv04.c | 6 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv10.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv20.c | 10 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv30.c | 12 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv40.c | 34 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 30 +-
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 20 +-
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 18 +-
drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild | 36 ++
.../nouveau/nvkm/engine/{graph => gr}/ctx.h | 0
.../nvkm/engine/{graph => gr}/ctxgk110b.c | 16 +-
.../nvkm/engine/{graph => gr}/ctxgk20a.c | 14 +-
.../nvkm/engine/{graph => gr}/ctxgm107.c | 76 +--
.../nvkm/engine/{graph => gr}/ctxnv108.c | 50 +-
.../nvkm/engine/{graph => gr}/ctxnv40.c | 38 +-
.../nvkm/engine/{graph => gr}/ctxnv50.c | 238 +++----
.../nvkm/engine/{graph => gr}/ctxnvc0.c | 116 ++--
.../gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h | 202 ++++++
.../nvkm/engine/{graph => gr}/ctxnvc1.c | 48 +-
.../nvkm/engine/{graph => gr}/ctxnvc4.c | 20 +-
.../nvkm/engine/{graph => gr}/ctxnvc8.c | 26 +-
.../nvkm/engine/{graph => gr}/ctxnvd7.c | 56 +-
.../nvkm/engine/{graph => gr}/ctxnvd9.c | 48 +-
.../nvkm/engine/{graph => gr}/ctxnve4.c | 80 +--
.../nvkm/engine/{graph => gr}/ctxnvf0.c | 52 +-
.../nvkm/engine/{graph => gr}/fuc/com.fuc | 0
.../nvkm/engine/{graph => gr}/fuc/gpc.fuc | 0
.../engine/{graph => gr}/fuc/gpcgm107.fuc5 | 0
.../engine/{graph => gr}/fuc/gpcgm107.fuc5.h | 0
.../engine/{graph => gr}/fuc/gpcnv108.fuc5 | 0
.../engine/{graph => gr}/fuc/gpcnv108.fuc5.h | 0
.../engine/{graph => gr}/fuc/gpcnvc0.fuc3 | 0
.../engine/{graph => gr}/fuc/gpcnvc0.fuc3.h | 0
.../engine/{graph => gr}/fuc/gpcnvd7.fuc3 | 0
.../engine/{graph => gr}/fuc/gpcnvd7.fuc3.h | 0
.../engine/{graph => gr}/fuc/gpcnve0.fuc3 | 0
.../engine/{graph => gr}/fuc/gpcnve0.fuc3.h | 0
.../engine/{graph => gr}/fuc/gpcnvf0.fuc3 | 0
.../engine/{graph => gr}/fuc/gpcnvf0.fuc3.h | 0
.../nvkm/engine/{graph => gr}/fuc/hub.fuc | 0
.../engine/{graph => gr}/fuc/hubgm107.fuc5 | 0
.../engine/{graph => gr}/fuc/hubgm107.fuc5.h | 0
.../engine/{graph => gr}/fuc/hubnv108.fuc5 | 0
.../engine/{graph => gr}/fuc/hubnv108.fuc5.h | 0
.../engine/{graph => gr}/fuc/hubnvc0.fuc3 | 0
.../engine/{graph => gr}/fuc/hubnvc0.fuc3.h | 0
.../engine/{graph => gr}/fuc/hubnvd7.fuc3 | 0
.../engine/{graph => gr}/fuc/hubnvd7.fuc3.h | 0
.../engine/{graph => gr}/fuc/hubnve0.fuc3 | 0
.../engine/{graph => gr}/fuc/hubnve0.fuc3.h | 0
.../engine/{graph => gr}/fuc/hubnvf0.fuc3 | 0
.../engine/{graph => gr}/fuc/hubnvf0.fuc3.h | 0
.../nvkm/engine/{graph => gr}/fuc/macros.fuc | 0
.../nvkm/engine/{graph => gr}/fuc/os.h | 0
.../nvkm/engine/{graph => gr}/gk110b.c | 88 +--
.../nouveau/nvkm/engine/{graph => gr}/gk20a.c | 20 +-
.../nouveau/nvkm/engine/{graph => gr}/gm107.c | 190 +++---
.../nouveau/nvkm/engine/{graph => gr}/nv04.c | 594 +++++++++---------
.../nouveau/nvkm/engine/{graph => gr}/nv10.c | 362 +++++------
.../nouveau/nvkm/engine/{graph => gr}/nv108.c | 120 ++--
.../nouveau/nvkm/engine/{graph => gr}/nv20.c | 122 ++--
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h | 31 +
.../nouveau/nvkm/engine/{graph => gr}/nv25.c | 78 +--
.../nouveau/nvkm/engine/{graph => gr}/nv2a.c | 46 +-
.../nouveau/nvkm/engine/{graph => gr}/nv30.c | 88 +--
.../nouveau/nvkm/engine/{graph => gr}/nv34.c | 82 +--
.../nouveau/nvkm/engine/{graph => gr}/nv35.c | 80 +--
.../nouveau/nvkm/engine/{graph => gr}/nv40.c | 168 ++---
.../nouveau/nvkm/engine/{graph => gr}/nv40.h | 6 +-
.../nouveau/nvkm/engine/{graph => gr}/nv50.c | 206 +++---
.../nouveau/nvkm/engine/{graph => gr}/nv50.h | 4 +-
.../nouveau/nvkm/engine/{graph => gr}/nvc0.c | 412 ++++++------
drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h | 270 ++++++++
.../nouveau/nvkm/engine/{graph => gr}/nvc1.c | 98 +--
.../nouveau/nvkm/engine/{graph => gr}/nvc4.c | 90 +--
.../nouveau/nvkm/engine/{graph => gr}/nvc8.c | 90 +--
.../nouveau/nvkm/engine/{graph => gr}/nvd7.c | 100 +--
.../nouveau/nvkm/engine/{graph => gr}/nvd9.c | 118 ++--
.../nouveau/nvkm/engine/{graph => gr}/nve4.c | 148 ++---
.../nouveau/nvkm/engine/{graph => gr}/nvf0.c | 132 ++--
.../nouveau/nvkm/engine/{graph => gr}/regs.h | 4 +-
.../gpu/drm/nouveau/nvkm/engine/graph/Kbuild | 36 --
.../drm/nouveau/nvkm/engine/graph/ctxnvc0.h | 202 ------
.../gpu/drm/nouveau/nvkm/engine/graph/nv20.h | 31 -
.../gpu/drm/nouveau/nvkm/engine/graph/nvc0.h | 270 --------
.../drm/nouveau/nvkm/subdev/instmem/nv40.c | 6 +-
94 files changed, 2874 insertions(+), 2874 deletions(-)
create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/graph.h
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctx.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxgk110b.c (92%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxgk20a.c (88%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxgm107.c (95%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxnv108.c (95%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxnv40.c (95%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxnv50.c (95%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxnvc0.c (95%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxnvc1.c (96%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxnvc4.c (90%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxnvc8.c (96%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxnvd7.c (87%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxnvd9.c (95%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxnve4.c (95%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/ctxnvf0.c (97%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/com.fuc (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/gpc.fuc (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/gpcgm107.fuc5 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/gpcgm107.fuc5.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/gpcnv108.fuc5 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/gpcnv108.fuc5.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/gpcnvc0.fuc3 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/gpcnvc0.fuc3.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/gpcnvd7.fuc3 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/gpcnvd7.fuc3.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/gpcnve0.fuc3 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/gpcnve0.fuc3.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/gpcnvf0.fuc3 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/gpcnvf0.fuc3.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/hub.fuc (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/hubgm107.fuc5 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/hubgm107.fuc5.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/hubnv108.fuc5 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/hubnv108.fuc5.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/hubnvc0.fuc3 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/hubnvc0.fuc3.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/hubnvd7.fuc3 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/hubnvd7.fuc3.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/hubnve0.fuc3 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/hubnve0.fuc3.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/hubnvf0.fuc3 (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/hubnvf0.fuc3.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/macros.fuc (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/fuc/os.h (100%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/gk110b.c (66%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/gk20a.c (79%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/gm107.c (77%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nv04.c (61%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nv10.c (77%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nv108.c (71%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nv20.c (77%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nv25.c (67%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nv2a.c (76%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nv30.c (74%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nv34.c (65%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nv35.c (65%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nv40.c (75%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nv40.h (86%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nv50.c (84%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nv50.h (73%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nvc0.c (81%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nvc1.c (63%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nvc4.c (67%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nvc8.c (63%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nvd7.c (64%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nvd9.c (68%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nve4.c (78%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/nvf0.c (71%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{graph => gr}/regs.h (99%)
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.h
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.h
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h
index 0fe20917e05d..c88bb7c1010e 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
@@ -122,7 +122,7 @@ struct nv_device_v0 {
#define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL
#define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL
#define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL
-#define NV_DEVICE_V0_DISABLE_GRAPH 0x0000000100000000ULL
+#define NV_DEVICE_V0_DISABLE_GR 0x0000000100000000ULL
#define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL
#define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL
#define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL
diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h
index 93acd5153bee..7f1770beff21 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/device.h
@@ -52,11 +52,11 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
#include <engine/device.h>
#include <engine/fifo.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include <engine/software.h>
#define nvkm_fifo(a) nouveau_fifo(nvkm_device(a))
#define nvkm_fifo_chan(a) ((struct nouveau_fifo_chan *)nvkm_object(a))
-#define nvkm_gr(a) ((struct nouveau_graph *)nouveau_engine(nvkm_object(a), NVDEV_ENGINE_GR))
+#define nvkm_gr(a) ((struct nouveau_gr *)nouveau_engine(nvkm_object(a), NVDEV_ENGINE_GR))
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
new file mode 100644
index 000000000000..9985adca0fda
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
@@ -0,0 +1,86 @@
+#ifndef __NOUVEAU_GR_H__
+#define __NOUVEAU_GR_H__
+
+#include <core/engine.h>
+#include <core/engctx.h>
+#include <core/enum.h>
+
+struct nouveau_gr_chan {
+ struct nouveau_engctx base;
+};
+
+#define nouveau_gr_context_create(p,e,c,g,s,a,f,d) \
+ nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
+#define nouveau_gr_context_destroy(d) \
+ nouveau_engctx_destroy(&(d)->base)
+#define nouveau_gr_context_init(d) \
+ nouveau_engctx_init(&(d)->base)
+#define nouveau_gr_context_fini(d,s) \
+ nouveau_engctx_fini(&(d)->base, (s))
+
+#define _nouveau_gr_context_dtor _nouveau_engctx_dtor
+#define _nouveau_gr_context_init _nouveau_engctx_init
+#define _nouveau_gr_context_fini _nouveau_engctx_fini
+#define _nouveau_gr_context_rd32 _nouveau_engctx_rd32
+#define _nouveau_gr_context_wr32 _nouveau_engctx_wr32
+
+struct nouveau_gr {
+ struct nouveau_engine base;
+
+ /* Returns chipset-specific counts of units packed into an u64.
+ */
+ u64 (*units)(struct nouveau_gr *);
+};
+
+static inline struct nouveau_gr *
+nouveau_gr(void *obj)
+{
+ return (void *)nouveau_engine(obj, NVDEV_ENGINE_GR);
+}
+
+#define nouveau_gr_create(p,e,c,y,d) \
+ nouveau_engine_create((p), (e), (c), (y), "PGR", "graphics", (d))
+#define nouveau_gr_destroy(d) \
+ nouveau_engine_destroy(&(d)->base)
+#define nouveau_gr_init(d) \
+ nouveau_engine_init(&(d)->base)
+#define nouveau_gr_fini(d,s) \
+ nouveau_engine_fini(&(d)->base, (s))
+
+#define _nouveau_gr_dtor _nouveau_engine_dtor
+#define _nouveau_gr_init _nouveau_engine_init
+#define _nouveau_gr_fini _nouveau_engine_fini
+
+extern struct nouveau_oclass nv04_gr_oclass;
+extern struct nouveau_oclass nv10_gr_oclass;
+extern struct nouveau_oclass nv20_gr_oclass;
+extern struct nouveau_oclass nv25_gr_oclass;
+extern struct nouveau_oclass nv2a_gr_oclass;
+extern struct nouveau_oclass nv30_gr_oclass;
+extern struct nouveau_oclass nv34_gr_oclass;
+extern struct nouveau_oclass nv35_gr_oclass;
+extern struct nouveau_oclass nv40_gr_oclass;
+extern struct nouveau_oclass nv50_gr_oclass;
+extern struct nouveau_oclass *nvc0_gr_oclass;
+extern struct nouveau_oclass *nvc1_gr_oclass;
+extern struct nouveau_oclass *nvc4_gr_oclass;
+extern struct nouveau_oclass *nvc8_gr_oclass;
+extern struct nouveau_oclass *nvd7_gr_oclass;
+extern struct nouveau_oclass *nvd9_gr_oclass;
+extern struct nouveau_oclass *nve4_gr_oclass;
+extern struct nouveau_oclass *gk20a_gr_oclass;
+extern struct nouveau_oclass *nvf0_gr_oclass;
+extern struct nouveau_oclass *gk110b_gr_oclass;
+extern struct nouveau_oclass *nv108_gr_oclass;
+extern struct nouveau_oclass *gm107_gr_oclass;
+
+extern const struct nouveau_bitfield nv04_gr_nsource[];
+extern struct nouveau_ofuncs nv04_gr_ofuncs;
+bool nv04_gr_idle(void *obj);
+
+extern const struct nouveau_bitfield nv10_gr_intr_name[];
+extern const struct nouveau_bitfield nv10_gr_nstatus[];
+
+extern const struct nouveau_enum nv50_data_error_names[];
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/graph.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/graph.h
deleted file mode 100644
index d61dcb7d6d5f..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/graph.h
+++ /dev/null
@@ -1,86 +0,0 @@
-#ifndef __NOUVEAU_GRAPH_H__
-#define __NOUVEAU_GRAPH_H__
-
-#include <core/engine.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-struct nouveau_graph_chan {
- struct nouveau_engctx base;
-};
-
-#define nouveau_graph_context_create(p,e,c,g,s,a,f,d) \
- nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
-#define nouveau_graph_context_destroy(d) \
- nouveau_engctx_destroy(&(d)->base)
-#define nouveau_graph_context_init(d) \
- nouveau_engctx_init(&(d)->base)
-#define nouveau_graph_context_fini(d,s) \
- nouveau_engctx_fini(&(d)->base, (s))
-
-#define _nouveau_graph_context_dtor _nouveau_engctx_dtor
-#define _nouveau_graph_context_init _nouveau_engctx_init
-#define _nouveau_graph_context_fini _nouveau_engctx_fini
-#define _nouveau_graph_context_rd32 _nouveau_engctx_rd32
-#define _nouveau_graph_context_wr32 _nouveau_engctx_wr32
-
-struct nouveau_graph {
- struct nouveau_engine base;
-
- /* Returns chipset-specific counts of units packed into an u64.
- */
- u64 (*units)(struct nouveau_graph *);
-};
-
-static inline struct nouveau_graph *
-nouveau_graph(void *obj)
-{
- return (void *)nouveau_engine(obj, NVDEV_ENGINE_GR);
-}
-
-#define nouveau_graph_create(p,e,c,y,d) \
- nouveau_engine_create((p), (e), (c), (y), "PGRAPH", "graphics", (d))
-#define nouveau_graph_destroy(d) \
- nouveau_engine_destroy(&(d)->base)
-#define nouveau_graph_init(d) \
- nouveau_engine_init(&(d)->base)
-#define nouveau_graph_fini(d,s) \
- nouveau_engine_fini(&(d)->base, (s))
-
-#define _nouveau_graph_dtor _nouveau_engine_dtor
-#define _nouveau_graph_init _nouveau_engine_init
-#define _nouveau_graph_fini _nouveau_engine_fini
-
-extern struct nouveau_oclass nv04_graph_oclass;
-extern struct nouveau_oclass nv10_graph_oclass;
-extern struct nouveau_oclass nv20_graph_oclass;
-extern struct nouveau_oclass nv25_graph_oclass;
-extern struct nouveau_oclass nv2a_graph_oclass;
-extern struct nouveau_oclass nv30_graph_oclass;
-extern struct nouveau_oclass nv34_graph_oclass;
-extern struct nouveau_oclass nv35_graph_oclass;
-extern struct nouveau_oclass nv40_graph_oclass;
-extern struct nouveau_oclass nv50_graph_oclass;
-extern struct nouveau_oclass *nvc0_graph_oclass;
-extern struct nouveau_oclass *nvc1_graph_oclass;
-extern struct nouveau_oclass *nvc4_graph_oclass;
-extern struct nouveau_oclass *nvc8_graph_oclass;
-extern struct nouveau_oclass *nvd7_graph_oclass;
-extern struct nouveau_oclass *nvd9_graph_oclass;
-extern struct nouveau_oclass *nve4_graph_oclass;
-extern struct nouveau_oclass *gk20a_graph_oclass;
-extern struct nouveau_oclass *nvf0_graph_oclass;
-extern struct nouveau_oclass *gk110b_graph_oclass;
-extern struct nouveau_oclass *nv108_graph_oclass;
-extern struct nouveau_oclass *gm107_graph_oclass;
-
-extern const struct nouveau_bitfield nv04_graph_nsource[];
-extern struct nouveau_ofuncs nv04_graph_ofuncs;
-bool nv04_graph_idle(void *obj);
-
-extern const struct nouveau_bitfield nv10_graph_intr_name[];
-extern const struct nouveau_bitfield nv10_graph_nstatus[];
-
-extern const struct nouveau_enum nv50_data_error_names[];
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index d39a15000068..16ab6b187a52 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -165,7 +165,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
struct nouveau_timer *ptimer = nvkm_timer(device);
- struct nouveau_graph *graph = nvkm_gr(device);
+ struct nouveau_gr *gr = nvkm_gr(device);
struct drm_nouveau_getparam *getparam = data;
switch (getparam->param) {
@@ -215,7 +215,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
getparam->value = 1;
break;
case NOUVEAU_GETPARAM_GRAPH_UNITS:
- getparam->value = graph->units ? graph->units(graph) : 0;
+ getparam->value = gr->units ? gr->units(gr) : 0;
break;
default:
NV_PRINTK(debug, cli, "unknown parameter %lld\n", getparam->param);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
index 71d6542147a2..183475e2a924 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
@@ -8,7 +8,7 @@ include $(src)/nvkm/engine/device/Kbuild
include $(src)/nvkm/engine/disp/Kbuild
include $(src)/nvkm/engine/dmaobj/Kbuild
include $(src)/nvkm/engine/fifo/Kbuild
-include $(src)/nvkm/engine/graph/Kbuild
+include $(src)/nvkm/engine/gr/Kbuild
include $(src)/nvkm/engine/mpeg/Kbuild
include $(src)/nvkm/engine/msvld/Kbuild
include $(src)/nvkm/engine/perfmon/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 96050a487226..baad4ad22058 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -228,7 +228,7 @@ static const u64 disable_map[] = {
[NVDEV_ENGINE_PERFMON] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_ENGINE_FIFO] = NV_DEVICE_V0_DISABLE_FIFO,
[NVDEV_ENGINE_SW] = NV_DEVICE_V0_DISABLE_FIFO,
- [NVDEV_ENGINE_GR] = NV_DEVICE_V0_DISABLE_GRAPH,
+ [NVDEV_ENGINE_GR] = NV_DEVICE_V0_DISABLE_GR,
[NVDEV_ENGINE_MPEG] = NV_DEVICE_V0_DISABLE_MPEG,
[NVDEV_ENGINE_ME] = NV_DEVICE_V0_DISABLE_ME,
[NVDEV_ENGINE_VP] = NV_DEVICE_V0_DISABLE_VP,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index c9c18dc6f216..e7289fd2da9b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -46,7 +46,7 @@
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include <engine/disp.h>
#include <engine/ce.h>
#include <engine/bsp.h>
@@ -86,7 +86,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = gm107_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
#if 0
@@ -130,7 +130,7 @@ gm100_identify(struct nouveau_device *device)
#if 0
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = gm107_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
#endif
device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
#if 0
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index 7f98385acec7..dcb53917b5e0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -37,7 +37,7 @@
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include <engine/disp.h>
int
@@ -59,7 +59,7 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x05:
@@ -77,7 +77,7 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index 6a7ece0fc789..f292e7b88628 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -38,7 +38,7 @@
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include <engine/disp.h>
int
@@ -59,7 +59,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x15:
@@ -78,7 +78,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x16:
@@ -97,7 +97,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1a:
@@ -116,7 +116,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x11:
@@ -135,7 +135,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x17:
@@ -154,7 +154,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1f:
@@ -173,7 +173,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x18:
@@ -192,7 +192,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index e3b17fde89e6..a03420ca82b1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -39,7 +39,7 @@
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include <engine/disp.h>
int
@@ -62,7 +62,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv20_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x25:
@@ -81,7 +81,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x28:
@@ -100,7 +100,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x2a:
@@ -119,7 +119,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv2a_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index 8f67f4d402d7..59b6baa64b4c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -38,7 +38,7 @@
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include <engine/mpeg.h>
#include <engine/disp.h>
@@ -62,7 +62,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x35:
@@ -81,7 +81,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x31:
@@ -100,7 +100,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -120,7 +120,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -140,7 +140,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index 49c68d7c093c..3b16fdc4c95e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -41,7 +41,7 @@
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include <engine/mpeg.h>
#include <engine/disp.h>
#include <engine/perfmon.h>
@@ -68,7 +68,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -91,7 +91,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -114,7 +114,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -137,7 +137,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -160,7 +160,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -183,7 +183,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -206,7 +206,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -229,7 +229,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -252,7 +252,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -275,7 +275,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -298,7 +298,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -321,7 +321,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -344,7 +344,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -367,7 +367,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -390,7 +390,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
@@ -413,7 +413,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index cb978023d472..a9788b4999c6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -44,7 +44,7 @@
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include <engine/mpeg.h>
#include <engine/vp.h>
#include <engine/cipher.h>
@@ -81,7 +81,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass;
@@ -107,7 +107,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -136,7 +136,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -165,7 +165,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -194,7 +194,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -223,7 +223,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -252,7 +252,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
@@ -281,7 +281,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -310,7 +310,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
@@ -339,7 +339,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
@@ -369,7 +369,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
@@ -400,7 +400,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
@@ -430,7 +430,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
@@ -460,7 +460,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 39bf7d115bc6..1f93c9611f37 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -46,7 +46,7 @@
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include <engine/vp.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
@@ -83,7 +83,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -116,7 +116,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -149,7 +149,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -181,7 +181,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -214,7 +214,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -246,7 +246,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -278,7 +278,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -311,7 +311,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
@@ -341,7 +341,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 1f6d515fb641..c18f5821c3cf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -46,7 +46,7 @@
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include <engine/disp.h>
#include <engine/ce.h>
#include <engine/bsp.h>
@@ -83,7 +83,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
@@ -117,7 +117,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
@@ -151,7 +151,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
@@ -177,7 +177,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = gk20a_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
@@ -207,7 +207,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
@@ -241,7 +241,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = gk110b_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
@@ -275,7 +275,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
@@ -308,7 +308,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
new file mode 100644
index 000000000000..ce508e85b8f0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
@@ -0,0 +1,36 @@
+nvkm-y += nvkm/engine/gr/ctxnv40.o
+nvkm-y += nvkm/engine/gr/ctxnv50.o
+nvkm-y += nvkm/engine/gr/ctxnvc0.o
+nvkm-y += nvkm/engine/gr/ctxnvc1.o
+nvkm-y += nvkm/engine/gr/ctxnvc4.o
+nvkm-y += nvkm/engine/gr/ctxnvc8.o
+nvkm-y += nvkm/engine/gr/ctxnvd7.o
+nvkm-y += nvkm/engine/gr/ctxnvd9.o
+nvkm-y += nvkm/engine/gr/ctxnve4.o
+nvkm-y += nvkm/engine/gr/ctxgk20a.o
+nvkm-y += nvkm/engine/gr/ctxnvf0.o
+nvkm-y += nvkm/engine/gr/ctxgk110b.o
+nvkm-y += nvkm/engine/gr/ctxnv108.o
+nvkm-y += nvkm/engine/gr/ctxgm107.o
+nvkm-y += nvkm/engine/gr/nv04.o
+nvkm-y += nvkm/engine/gr/nv10.o
+nvkm-y += nvkm/engine/gr/nv20.o
+nvkm-y += nvkm/engine/gr/nv25.o
+nvkm-y += nvkm/engine/gr/nv2a.o
+nvkm-y += nvkm/engine/gr/nv30.o
+nvkm-y += nvkm/engine/gr/nv34.o
+nvkm-y += nvkm/engine/gr/nv35.o
+nvkm-y += nvkm/engine/gr/nv40.o
+nvkm-y += nvkm/engine/gr/nv50.o
+nvkm-y += nvkm/engine/gr/nvc0.o
+nvkm-y += nvkm/engine/gr/nvc1.o
+nvkm-y += nvkm/engine/gr/nvc4.o
+nvkm-y += nvkm/engine/gr/nvc8.o
+nvkm-y += nvkm/engine/gr/nvd7.o
+nvkm-y += nvkm/engine/gr/nvd9.o
+nvkm-y += nvkm/engine/gr/nve4.o
+nvkm-y += nvkm/engine/gr/gk20a.o
+nvkm-y += nvkm/engine/gr/nvf0.o
+nvkm-y += nvkm/engine/gr/gk110b.o
+nvkm-y += nvkm/engine/gr/nv108.o
+nvkm-y += nvkm/engine/gr/gm107.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctx.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctx.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c
similarity index 92%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk110b.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c
index 3adb7fe91772..05a69ca48f25 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk110b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c
@@ -28,7 +28,7 @@
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gk110b_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
@@ -56,7 +56,7 @@ gk110b_grctx_init_sm_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
gk110b_grctx_pack_tpc[] = {
{ nvd7_grctx_init_pe_0 },
{ nvf0_grctx_init_tex_0 },
@@ -74,12 +74,12 @@ struct nouveau_oclass *
gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xf1),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_context_ctor,
- .dtor = nvc0_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = _nouveau_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nvc0_gr_context_ctor,
+ .dtor = nvc0_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = _nouveau_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
.main = nve4_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
similarity index 88%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
index 36fc9831cc93..5aae94ced9ed 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
@@ -22,7 +22,7 @@
#include "ctxnvc0.h"
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
gk20a_grctx_pack_mthd[] = {
{ nve4_grctx_init_a097_0, 0xa297 },
{ nvc0_grctx_init_902d_0, 0x902d },
@@ -33,12 +33,12 @@ struct nouveau_oclass *
gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xea),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_context_ctor,
- .dtor = nvc0_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = _nouveau_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nvc0_gr_context_ctor,
+ .dtor = nvc0_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = _nouveau_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
.main = nve4_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
similarity index 95%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgm107.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
index 62e918b9fa81..cf6199fe3b59 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
@@ -28,7 +28,7 @@
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
@@ -287,13 +287,13 @@ gm107_grctx_init_icmd_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
gm107_grctx_pack_icmd[] = {
{ gm107_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_b097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
@@ -610,14 +610,14 @@ gm107_grctx_init_b097_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
gm107_grctx_pack_mthd[] = {
{ gm107_grctx_init_b097_0, 0xb097 },
{ nvc0_grctx_init_902d_0, 0x902d },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
@@ -639,7 +639,7 @@ gm107_grctx_init_fe_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8001bf },
{ 0x405830, 1, 0x04, 0x0aa01000 },
@@ -653,7 +653,7 @@ gm107_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x07410001 },
{ 0x406028, 4, 0x04, 0x00000001 },
@@ -669,7 +669,7 @@ gm107_grctx_init_pd_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x32802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
@@ -682,7 +682,7 @@ gm107_grctx_init_be_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
gm107_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ gm107_grctx_init_fe_0 },
@@ -697,13 +697,13 @@ gm107_grctx_pack_hub[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_gpc_unk_0[] = {
{ 0x418380, 1, 0x04, 0x00000056 },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000007f },
{ 0x418684, 1, 0x04, 0x0000001f },
@@ -714,7 +714,7 @@ gm107_grctx_init_gpc_unk_1[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006863a },
{ 0x418810, 1, 0x04, 0x00000000 },
@@ -727,7 +727,7 @@ gm107_grctx_init_setup_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_gpc_unk_2[] = {
{ 0x418d24, 1, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x90000000 },
@@ -741,7 +741,7 @@ gm107_grctx_init_gpc_unk_2[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
gm107_grctx_pack_gpc[] = {
{ gm107_grctx_init_gpc_unk_0 },
{ nv108_grctx_init_prop_0 },
@@ -755,7 +755,7 @@ gm107_grctx_pack_gpc[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000300f0 },
{ 0x419a04, 1, 0x04, 0x00000005 },
@@ -771,7 +771,7 @@ gm107_grctx_init_tex_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000001a },
{ 0x419c04, 1, 0x04, 0x80000006 },
@@ -785,13 +785,13 @@ gm107_grctx_init_mpc_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_l1c_0[] = {
{ 0x419c84, 1, 0x04, 0x00000020 },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00001c02 },
@@ -812,7 +812,7 @@ gm107_grctx_init_sm_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
gm107_grctx_pack_tpc[] = {
{ nvd7_grctx_init_pe_0 },
{ gm107_grctx_init_tex_0 },
@@ -822,7 +822,7 @@ gm107_grctx_pack_tpc[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x00000000 },
{ 0x41bec4, 1, 0x04, 0x01050000 },
@@ -832,7 +832,7 @@ gm107_grctx_init_cbm_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
gm107_grctx_init_wwdx_0[] = {
{ 0x41bf00, 1, 0x04, 0x0a418820 },
{ 0x41bf04, 1, 0x04, 0x062080e6 },
@@ -846,7 +846,7 @@ gm107_grctx_init_wwdx_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
gm107_grctx_pack_ppc[] = {
{ nve4_grctx_init_pes_0 },
{ gm107_grctx_init_cbm_0 },
@@ -893,7 +893,7 @@ gm107_grctx_generate_pagepool(struct nvc0_grctx *info)
static void
gm107_grctx_generate_attrib(struct nvc0_grctx *info)
{
- struct nvc0_graph_priv *priv = info->priv;
+ struct nvc0_gr_priv *priv = info->priv;
const struct nvc0_grctx_oclass *impl = (void *)nvc0_grctx_impl(priv);
const u32 alpha = impl->alpha_nr;
const u32 attrib = impl->attrib_nr;
@@ -930,7 +930,7 @@ gm107_grctx_generate_attrib(struct nvc0_grctx *info)
}
static void
-gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
+gm107_grctx_generate_tpcid(struct nvc0_gr_priv *priv)
{
int gpc, tpc, id;
@@ -950,16 +950,16 @@ gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
}
static void
-gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+gm107_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
{
struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
int i;
- nvc0_graph_mmio(priv, oclass->hub);
- nvc0_graph_mmio(priv, oclass->gpc);
- nvc0_graph_mmio(priv, oclass->zcull);
- nvc0_graph_mmio(priv, oclass->tpc);
- nvc0_graph_mmio(priv, oclass->ppc);
+ nvc0_gr_mmio(priv, oclass->hub);
+ nvc0_gr_mmio(priv, oclass->gpc);
+ nvc0_gr_mmio(priv, oclass->zcull);
+ nvc0_gr_mmio(priv, oclass->tpc);
+ nvc0_gr_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
@@ -988,9 +988,9 @@ gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
}
- nvc0_graph_icmd(priv, oclass->icmd);
+ nvc0_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
- nvc0_graph_mthd(priv, oclass->mthd);
+ nvc0_gr_mthd(priv, oclass->mthd);
nv_mask(priv, 0x419e00, 0x00808080, 0x00808080);
nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000);
@@ -1002,12 +1002,12 @@ struct nouveau_oclass *
gm107_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0x08),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_context_ctor,
- .dtor = nvc0_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = _nouveau_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nvc0_gr_context_ctor,
+ .dtor = nvc0_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = _nouveau_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
.main = gm107_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c
similarity index 95%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv108.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c
index ce252adbef81..f56d77e307c1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv108.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c
@@ -28,7 +28,7 @@
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nv108_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
@@ -278,13 +278,13 @@ nv108_grctx_init_icmd_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nv108_grctx_pack_icmd[] = {
{ nv108_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nv108_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
@@ -311,7 +311,7 @@ nv108_grctx_init_fe_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nv108_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180648 },
@@ -325,7 +325,7 @@ nv108_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nv108_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x034103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
@@ -340,7 +340,7 @@ nv108_grctx_init_pd_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nv108_grctx_init_rstr2d_0[] = {
{ 0x407804, 1, 0x04, 0x00000063 },
{ 0x40780c, 1, 0x04, 0x0a418820 },
@@ -353,7 +353,7 @@ nv108_grctx_init_rstr2d_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nv108_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x32802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
@@ -366,7 +366,7 @@ nv108_grctx_init_be_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nv108_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nv108_grctx_init_fe_0 },
@@ -381,7 +381,7 @@ nv108_grctx_pack_hub[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nv108_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38005e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
@@ -394,7 +394,7 @@ nv108_grctx_init_prop_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nv108_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000007f },
{ 0x418684, 1, 0x04, 0x0000001f },
@@ -404,7 +404,7 @@ nv108_grctx_init_gpc_unk_1[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nv108_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006863a },
{ 0x418808, 1, 0x04, 0x00000000 },
@@ -419,7 +419,7 @@ nv108_grctx_init_setup_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nv108_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x0000001e },
{ 0x418b08, 1, 0x04, 0x0a418820 },
@@ -432,7 +432,7 @@ nv108_grctx_init_crstr_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nv108_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
@@ -443,7 +443,7 @@ nv108_grctx_init_gpm_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nv108_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nv108_grctx_init_prop_0 },
@@ -457,7 +457,7 @@ nv108_grctx_pack_gpc[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nv108_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000100f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
@@ -472,7 +472,7 @@ nv108_grctx_init_tex_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nv108_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
@@ -500,7 +500,7 @@ nv108_grctx_init_sm_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nv108_grctx_pack_tpc[] = {
{ nvd7_grctx_init_pe_0 },
{ nv108_grctx_init_tex_0 },
@@ -510,7 +510,7 @@ nv108_grctx_pack_tpc[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nv108_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x10000000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
@@ -519,7 +519,7 @@ nv108_grctx_init_cbm_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nv108_grctx_pack_ppc[] = {
{ nve4_grctx_init_pes_0 },
{ nv108_grctx_init_cbm_0 },
@@ -535,12 +535,12 @@ struct nouveau_oclass *
nv108_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0x08),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_context_ctor,
- .dtor = nvc0_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = _nouveau_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nvc0_gr_context_ctor,
+ .dtor = nvc0_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = _nouveau_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
.main = nve4_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c
similarity index 95%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv40.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c
index 7bbb1e1b7a8d..9e311411f1b1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c
@@ -119,7 +119,7 @@
*/
static int
-nv40_graph_vs_count(struct nouveau_device *device)
+nv40_gr_vs_count(struct nouveau_device *device)
{
switch (device->chipset) {
@@ -158,7 +158,7 @@ enum cp_label {
};
static void
-nv40_graph_construct_general(struct nouveau_grctx *ctx)
+nv40_gr_construct_general(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int i;
@@ -208,7 +208,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx)
gr_def(ctx, 0x4009dc, 0x80000000);
} else {
cp_ctx(ctx, 0x400840, 20);
- if (nv44_graph_class(ctx->device)) {
+ if (nv44_gr_class(ctx->device)) {
for (i = 0; i < 8; i++)
gr_def(ctx, 0x400860 + (i * 4), 0x00000001);
}
@@ -217,7 +217,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx)
gr_def(ctx, 0x400888, 0x00000040);
cp_ctx(ctx, 0x400894, 11);
gr_def(ctx, 0x400894, 0x00000040);
- if (!nv44_graph_class(ctx->device)) {
+ if (!nv44_gr_class(ctx->device)) {
for (i = 0; i < 8; i++)
gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000);
}
@@ -264,7 +264,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx)
}
static void
-nv40_graph_construct_state3d(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int i;
@@ -369,7 +369,7 @@ nv40_graph_construct_state3d(struct nouveau_grctx *ctx)
}
static void
-nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d_2(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int i;
@@ -504,8 +504,8 @@ nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3);
cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3);
- cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->device));
- for (i = 0; i < nv40_graph_vs_count(ctx->device); i++)
+ cp_ctx(ctx, 0x403420, nv40_gr_vs_count(ctx->device));
+ for (i = 0; i < nv40_gr_vs_count(ctx->device); i++)
gr_def(ctx, 0x403420 + (i * 4), 0x00005555);
if (device->chipset != 0x40) {
@@ -533,9 +533,9 @@ nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
}
static void
-nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d_3(struct nouveau_grctx *ctx)
{
- int len = nv44_graph_class(ctx->device) ? 0x0084 : 0x0684;
+ int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684;
cp_out (ctx, 0x300000);
cp_lsr (ctx, len - 4);
@@ -548,14 +548,14 @@ nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx)
}
static void
-nv40_graph_construct_shader(struct nouveau_grctx *ctx)
+nv40_gr_construct_shader(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
struct nouveau_gpuobj *obj = ctx->data;
int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset;
int offset, i;
- vs_nr = nv40_graph_vs_count(ctx->device);
+ vs_nr = nv40_gr_vs_count(ctx->device);
vs_nr_b0 = 363;
vs_nr_b1 = device->chipset == 0x40 ? 128 : 64;
if (device->chipset == 0x40) {
@@ -570,11 +570,11 @@ nv40_graph_construct_shader(struct nouveau_grctx *ctx)
} else {
b0_offset = 0x1d40/4; /* 2200 */
b1_offset = 0x3f40/4; /* 0b00 : 0a40 */
- vs_len = nv44_graph_class(device) ? 0x4980/4 : 0x4a40/4;
+ vs_len = nv44_gr_class(device) ? 0x4980/4 : 0x4a40/4;
}
cp_lsr(ctx, vs_len * vs_nr + 0x300/4);
- cp_out(ctx, nv44_graph_class(device) ? 0x800029 : 0x800041);
+ cp_out(ctx, nv44_gr_class(device) ? 0x800029 : 0x800041);
offset = ctx->ctxvals_pos;
ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len));
@@ -629,23 +629,23 @@ nv40_grctx_generate(struct nouveau_grctx *ctx)
/* general PGRAPH state */
cp_name(ctx, cp_swap_state);
cp_pos (ctx, 0x00020/4);
- nv40_graph_construct_general(ctx);
+ nv40_gr_construct_general(ctx);
cp_wait(ctx, STATUS, IDLE);
/* 3D state, block 1 */
cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit);
- nv40_graph_construct_state3d(ctx);
+ nv40_gr_construct_state3d(ctx);
cp_wait(ctx, STATUS, IDLE);
/* 3D state, block 2 */
- nv40_graph_construct_state3d_2(ctx);
+ nv40_gr_construct_state3d_2(ctx);
/* Some other block of "random" state */
- nv40_graph_construct_state3d_3(ctx);
+ nv40_gr_construct_state3d_3(ctx);
/* Per-vertex shader state */
cp_pos (ctx, ctx->ctxvals_pos);
- nv40_graph_construct_shader(ctx);
+ nv40_gr_construct_shader(ctx);
/* pre-exit state updates */
cp_name(ctx, cp_prepare_exit);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
similarity index 95%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
index 1d0e33fb5f61..8b7d879a7fa1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
@@ -169,9 +169,9 @@ enum cp_label {
cp_exit,
};
-static void nv50_graph_construct_mmio(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_xfer1(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_xfer2(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_mmio(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_xfer1(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_xfer2(struct nouveau_grctx *ctx);
/* Main function: construct the ctxprog skeleton, call the other functions. */
@@ -219,9 +219,9 @@ nv50_grctx_generate(struct nouveau_grctx *ctx)
cp_pos (ctx, 0x00004/4);
cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */
cp_pos (ctx, 0x00100/4);
- nv50_graph_construct_mmio(ctx);
- nv50_graph_construct_xfer1(ctx);
- nv50_graph_construct_xfer2(ctx);
+ nv50_gr_construct_mmio(ctx);
+ nv50_gr_construct_xfer1(ctx);
+ nv50_gr_construct_xfer2(ctx);
cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load);
@@ -293,10 +293,10 @@ nv50_grctx_init(struct nouveau_device *device, u32 *size)
*/
static void
-nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx);
+nv50_gr_construct_mmio_ddata(struct nouveau_grctx *ctx);
static void
-nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
+nv50_gr_construct_mmio(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int i, j;
@@ -334,7 +334,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
gr_def(ctx, 0x400b20, 0x0001629d);
}
- nv50_graph_construct_mmio_ddata(ctx);
+ nv50_gr_construct_mmio_ddata(ctx);
/* 0C00: VFETCH */
cp_ctx(ctx, 0x400c08, 0x2);
@@ -793,7 +793,7 @@ dd_emit(struct nouveau_grctx *ctx, int num, u32 val) {
}
static void
-nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
+nv50_gr_construct_mmio_ddata(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int base, num;
@@ -1166,27 +1166,27 @@ xf_emit(struct nouveau_grctx *ctx, int num, u32 val) {
/* Gene declarations... */
-static void nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx);
-static void nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_dispatch(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_m2mf(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_ccache(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_unk10xx(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_unk14xx(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_zcull(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_clipid(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_unk24xx(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_vfetch(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_eng2d(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_csched(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_unk1cxx(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_strmout(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_unk34xx(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_ropm1(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_ropm2(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_ropc(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_xfer_tp(struct nouveau_grctx *ctx);
static void
-nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer1(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int i;
@@ -1200,32 +1200,32 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
if (device->chipset < 0xa0) {
/* Strand 0 */
ctx->ctxvals_pos = offset;
- nv50_graph_construct_gene_dispatch(ctx);
- nv50_graph_construct_gene_m2mf(ctx);
- nv50_graph_construct_gene_unk24xx(ctx);
- nv50_graph_construct_gene_clipid(ctx);
- nv50_graph_construct_gene_zcull(ctx);
+ nv50_gr_construct_gene_dispatch(ctx);
+ nv50_gr_construct_gene_m2mf(ctx);
+ nv50_gr_construct_gene_unk24xx(ctx);
+ nv50_gr_construct_gene_clipid(ctx);
+ nv50_gr_construct_gene_zcull(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 1 */
ctx->ctxvals_pos = offset + 0x1;
- nv50_graph_construct_gene_vfetch(ctx);
- nv50_graph_construct_gene_eng2d(ctx);
- nv50_graph_construct_gene_csched(ctx);
- nv50_graph_construct_gene_ropm1(ctx);
- nv50_graph_construct_gene_ropm2(ctx);
+ nv50_gr_construct_gene_vfetch(ctx);
+ nv50_gr_construct_gene_eng2d(ctx);
+ nv50_gr_construct_gene_csched(ctx);
+ nv50_gr_construct_gene_ropm1(ctx);
+ nv50_gr_construct_gene_ropm2(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 2 */
ctx->ctxvals_pos = offset + 0x2;
- nv50_graph_construct_gene_ccache(ctx);
- nv50_graph_construct_gene_unk1cxx(ctx);
- nv50_graph_construct_gene_strmout(ctx);
- nv50_graph_construct_gene_unk14xx(ctx);
- nv50_graph_construct_gene_unk10xx(ctx);
- nv50_graph_construct_gene_unk34xx(ctx);
+ nv50_gr_construct_gene_ccache(ctx);
+ nv50_gr_construct_gene_unk1cxx(ctx);
+ nv50_gr_construct_gene_strmout(ctx);
+ nv50_gr_construct_gene_unk14xx(ctx);
+ nv50_gr_construct_gene_unk10xx(ctx);
+ nv50_gr_construct_gene_unk34xx(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
@@ -1233,7 +1233,7 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
ctx->ctxvals_pos = offset + 3;
for (i = 0; i < 6; i++)
if (units & (1 << (i + 16)))
- nv50_graph_construct_gene_ropc(ctx);
+ nv50_gr_construct_gene_ropc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
@@ -1241,74 +1241,74 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
for (i = 0; i < 4; i++) {
ctx->ctxvals_pos = offset + 4 + i;
if (units & (1 << (2 * i)))
- nv50_graph_construct_xfer_tp(ctx);
+ nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << (2 * i + 1)))
- nv50_graph_construct_xfer_tp(ctx);
+ nv50_gr_construct_xfer_tp(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
}
} else {
/* Strand 0 */
ctx->ctxvals_pos = offset;
- nv50_graph_construct_gene_dispatch(ctx);
- nv50_graph_construct_gene_m2mf(ctx);
- nv50_graph_construct_gene_unk34xx(ctx);
- nv50_graph_construct_gene_csched(ctx);
- nv50_graph_construct_gene_unk1cxx(ctx);
- nv50_graph_construct_gene_strmout(ctx);
+ nv50_gr_construct_gene_dispatch(ctx);
+ nv50_gr_construct_gene_m2mf(ctx);
+ nv50_gr_construct_gene_unk34xx(ctx);
+ nv50_gr_construct_gene_csched(ctx);
+ nv50_gr_construct_gene_unk1cxx(ctx);
+ nv50_gr_construct_gene_strmout(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 1 */
ctx->ctxvals_pos = offset + 1;
- nv50_graph_construct_gene_unk10xx(ctx);
+ nv50_gr_construct_gene_unk10xx(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 2 */
ctx->ctxvals_pos = offset + 2;
if (device->chipset == 0xa0)
- nv50_graph_construct_gene_unk14xx(ctx);
- nv50_graph_construct_gene_unk24xx(ctx);
+ nv50_gr_construct_gene_unk14xx(ctx);
+ nv50_gr_construct_gene_unk24xx(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 3 */
ctx->ctxvals_pos = offset + 3;
- nv50_graph_construct_gene_vfetch(ctx);
+ nv50_gr_construct_gene_vfetch(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 4 */
ctx->ctxvals_pos = offset + 4;
- nv50_graph_construct_gene_ccache(ctx);
+ nv50_gr_construct_gene_ccache(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 5 */
ctx->ctxvals_pos = offset + 5;
- nv50_graph_construct_gene_ropm2(ctx);
- nv50_graph_construct_gene_ropm1(ctx);
+ nv50_gr_construct_gene_ropm2(ctx);
+ nv50_gr_construct_gene_ropm1(ctx);
/* per-ROP context */
for (i = 0; i < 8; i++)
if (units & (1<<(i+16)))
- nv50_graph_construct_gene_ropc(ctx);
+ nv50_gr_construct_gene_ropc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 6 */
ctx->ctxvals_pos = offset + 6;
- nv50_graph_construct_gene_zcull(ctx);
- nv50_graph_construct_gene_clipid(ctx);
- nv50_graph_construct_gene_eng2d(ctx);
+ nv50_gr_construct_gene_zcull(ctx);
+ nv50_gr_construct_gene_clipid(ctx);
+ nv50_gr_construct_gene_eng2d(ctx);
if (units & (1 << 0))
- nv50_graph_construct_xfer_tp(ctx);
+ nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 1))
- nv50_graph_construct_xfer_tp(ctx);
+ nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 2))
- nv50_graph_construct_xfer_tp(ctx);
+ nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 3))
- nv50_graph_construct_xfer_tp(ctx);
+ nv50_gr_construct_xfer_tp(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
@@ -1316,19 +1316,19 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
ctx->ctxvals_pos = offset + 7;
if (device->chipset == 0xa0) {
if (units & (1 << 4))
- nv50_graph_construct_xfer_tp(ctx);
+ nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 5))
- nv50_graph_construct_xfer_tp(ctx);
+ nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 6))
- nv50_graph_construct_xfer_tp(ctx);
+ nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 7))
- nv50_graph_construct_xfer_tp(ctx);
+ nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 8))
- nv50_graph_construct_xfer_tp(ctx);
+ nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 9))
- nv50_graph_construct_xfer_tp(ctx);
+ nv50_gr_construct_xfer_tp(ctx);
} else {
- nv50_graph_construct_gene_unk14xx(ctx);
+ nv50_gr_construct_gene_unk14xx(ctx);
}
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
@@ -1349,7 +1349,7 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
*/
static void
-nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_dispatch(struct nouveau_grctx *ctx)
{
/* start of strand 0 */
struct nouveau_device *device = ctx->device;
@@ -1405,7 +1405,7 @@ nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_m2mf(struct nouveau_grctx *ctx)
{
/* Strand 0, right after dispatch */
struct nouveau_device *device = ctx->device;
@@ -1457,7 +1457,7 @@ nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ccache(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
xf_emit(ctx, 2, 0); /* RO */
@@ -1525,7 +1525,7 @@ nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk10xx(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int i;
@@ -1585,7 +1585,7 @@ nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk34xx(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
/* end of area 2 on pre-NVA0, area 1 on NVAx */
@@ -1610,7 +1610,7 @@ nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk14xx(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
/* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */
@@ -1721,7 +1721,7 @@ nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_zcull(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
/* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */
@@ -1782,7 +1782,7 @@ nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_clipid(struct nouveau_grctx *ctx)
{
/* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */
/* SEEK */
@@ -1802,7 +1802,7 @@ nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk24xx(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int i;
@@ -1885,7 +1885,7 @@ nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_vfetch(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int acnt = 0x10, rep, i;
@@ -2071,7 +2071,7 @@ nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_eng2d(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
/* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */
@@ -2133,7 +2133,7 @@ nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_csched(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
/* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */
@@ -2232,7 +2232,7 @@ nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
@@ -2328,7 +2328,7 @@ nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_strmout(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */
@@ -2370,7 +2370,7 @@ nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ropm1(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */
@@ -2383,7 +2383,7 @@ nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ropm2(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
/* SEEK */
@@ -2409,7 +2409,7 @@ nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ropc(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int magic2;
@@ -2644,7 +2644,7 @@ nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int magic3;
@@ -2736,7 +2736,7 @@ nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_tprop(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int magic1, magic2;
@@ -3036,7 +3036,7 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_tex(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
xf_emit(ctx, 2, 0); /* 1 LINKED_TSC. yes, 2. */
@@ -3082,7 +3082,7 @@ nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
@@ -3121,24 +3121,24 @@ nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_tp(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
if (device->chipset < 0xa0) {
- nv50_graph_construct_xfer_unk84xx(ctx);
- nv50_graph_construct_xfer_tprop(ctx);
- nv50_graph_construct_xfer_tex(ctx);
- nv50_graph_construct_xfer_unk8cxx(ctx);
+ nv50_gr_construct_xfer_unk84xx(ctx);
+ nv50_gr_construct_xfer_tprop(ctx);
+ nv50_gr_construct_xfer_tex(ctx);
+ nv50_gr_construct_xfer_unk8cxx(ctx);
} else {
- nv50_graph_construct_xfer_tex(ctx);
- nv50_graph_construct_xfer_tprop(ctx);
- nv50_graph_construct_xfer_unk8cxx(ctx);
- nv50_graph_construct_xfer_unk84xx(ctx);
+ nv50_gr_construct_xfer_tex(ctx);
+ nv50_gr_construct_xfer_tprop(ctx);
+ nv50_gr_construct_xfer_unk8cxx(ctx);
+ nv50_gr_construct_xfer_unk84xx(ctx);
}
}
static void
-nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_mpc(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int i, mpcnt = 2;
@@ -3270,7 +3270,7 @@ nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
}
static void
-nv50_graph_construct_xfer2(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer2(struct nouveau_grctx *ctx)
{
struct nouveau_device *device = ctx->device;
int i;
@@ -3288,7 +3288,7 @@ nv50_graph_construct_xfer2(struct nouveau_grctx *ctx)
if (i == 0)
xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */
if (units & (1 << i))
- nv50_graph_construct_xfer_mpc(ctx);
+ nv50_gr_construct_xfer_mpc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
}
@@ -3299,40 +3299,40 @@ nv50_graph_construct_xfer2(struct nouveau_grctx *ctx)
* what it's doing here. */
xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */
if (units & (1 << 0))
- nv50_graph_construct_xfer_mpc(ctx);
+ nv50_gr_construct_xfer_mpc(ctx);
if (units & (1 << 1))
- nv50_graph_construct_xfer_mpc(ctx);
+ nv50_gr_construct_xfer_mpc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 1: TPs 2, 3 */
ctx->ctxvals_pos = offset + 1;
if (units & (1 << 2))
- nv50_graph_construct_xfer_mpc(ctx);
+ nv50_gr_construct_xfer_mpc(ctx);
if (units & (1 << 3))
- nv50_graph_construct_xfer_mpc(ctx);
+ nv50_gr_construct_xfer_mpc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 2: TPs 4, 5, 6 */
ctx->ctxvals_pos = offset + 2;
if (units & (1 << 4))
- nv50_graph_construct_xfer_mpc(ctx);
+ nv50_gr_construct_xfer_mpc(ctx);
if (units & (1 << 5))
- nv50_graph_construct_xfer_mpc(ctx);
+ nv50_gr_construct_xfer_mpc(ctx);
if (units & (1 << 6))
- nv50_graph_construct_xfer_mpc(ctx);
+ nv50_gr_construct_xfer_mpc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 3: TPs 7, 8, 9 */
ctx->ctxvals_pos = offset + 3;
if (units & (1 << 7))
- nv50_graph_construct_xfer_mpc(ctx);
+ nv50_gr_construct_xfer_mpc(ctx);
if (units & (1 << 8))
- nv50_graph_construct_xfer_mpc(ctx);
+ nv50_gr_construct_xfer_mpc(ctx);
if (units & (1 << 9))
- nv50_graph_construct_xfer_mpc(ctx);
+ nv50_gr_construct_xfer_mpc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c
similarity index 95%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c
index b8e5fe60a1eb..08a925efecf2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c
@@ -28,7 +28,7 @@
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc0_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
@@ -266,13 +266,13 @@ nvc0_grctx_init_icmd_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nvc0_grctx_pack_icmd[] = {
{ nvc0_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc0_grctx_init_9097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
@@ -575,7 +575,7 @@ nvc0_grctx_init_9097_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_902d_0[] = {
{ 0x000200, 1, 0x04, 0x000000cf },
{ 0x000204, 1, 0x04, 0x00000001 },
@@ -594,7 +594,7 @@ nvc0_grctx_init_902d_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_9039_0[] = {
{ 0x00030c, 3, 0x04, 0x00000000 },
{ 0x000320, 1, 0x04, 0x00000000 },
@@ -603,7 +603,7 @@ nvc0_grctx_init_9039_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_90c0_0[] = {
{ 0x00270c, 8, 0x20, 0x00000000 },
{ 0x00030c, 1, 0x04, 0x00000001 },
@@ -621,7 +621,7 @@ nvc0_grctx_init_90c0_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nvc0_grctx_pack_mthd[] = {
{ nvc0_grctx_init_9097_0, 0x9097 },
{ nvc0_grctx_init_902d_0, 0x902d },
@@ -630,13 +630,13 @@ nvc0_grctx_pack_mthd[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_main_0[] = {
{ 0x400204, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_fe_0[] = {
{ 0x404004, 11, 0x04, 0x00000000 },
{ 0x404044, 1, 0x04, 0x00000000 },
@@ -657,7 +657,7 @@ nvc0_grctx_init_fe_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_pri_0[] = {
{ 0x404404, 14, 0x04, 0x00000000 },
{ 0x404460, 2, 0x04, 0x00000000 },
@@ -668,7 +668,7 @@ nvc0_grctx_init_pri_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_memfmt_0[] = {
{ 0x404604, 1, 0x04, 0x00000015 },
{ 0x404608, 1, 0x04, 0x00000000 },
@@ -690,7 +690,7 @@ nvc0_grctx_init_memfmt_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc0_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x078000bf },
{ 0x405830, 1, 0x04, 0x02180000 },
@@ -702,7 +702,7 @@ nvc0_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc0_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
@@ -712,7 +712,7 @@ nvc0_grctx_init_pd_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_rstr2d_0[] = {
{ 0x407804, 1, 0x04, 0x00000023 },
{ 0x40780c, 1, 0x04, 0x0a418820 },
@@ -725,7 +725,7 @@ nvc0_grctx_init_rstr2d_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_scc_0[] = {
{ 0x408000, 2, 0x04, 0x00000000 },
{ 0x408008, 1, 0x04, 0x00000018 },
@@ -736,7 +736,7 @@ nvc0_grctx_init_scc_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc0_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
@@ -748,7 +748,7 @@ nvc0_grctx_init_be_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nvc0_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nvc0_grctx_init_fe_0 },
@@ -762,13 +762,13 @@ nvc0_grctx_pack_hub[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_gpc_unk_0[] = {
{ 0x418380, 1, 0x04, 0x00000016 },
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38004e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
@@ -782,7 +782,7 @@ nvc0_grctx_init_prop_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000001f },
{ 0x418684, 1, 0x04, 0x0000000f },
@@ -794,7 +794,7 @@ nvc0_grctx_init_gpc_unk_1[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc0_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
@@ -807,7 +807,7 @@ nvc0_grctx_init_setup_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_zcull_0[] = {
{ 0x41891c, 1, 0x04, 0x00ff00ff },
{ 0x418924, 1, 0x04, 0x00000000 },
@@ -816,7 +816,7 @@ nvc0_grctx_init_zcull_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x00000000 },
{ 0x418b08, 1, 0x04, 0x0a418820 },
@@ -829,7 +829,7 @@ nvc0_grctx_init_crstr_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
@@ -838,7 +838,7 @@ nvc0_grctx_init_gpm_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_gcc_0[] = {
{ 0x419000, 1, 0x04, 0x00000780 },
{ 0x419004, 2, 0x04, 0x00000000 },
@@ -846,7 +846,7 @@ nvc0_grctx_init_gcc_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nvc0_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nvc0_grctx_init_prop_0 },
@@ -859,7 +859,7 @@ nvc0_grctx_pack_gpc[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc0_grctx_init_zcullr_0[] = {
{ 0x418a00, 3, 0x04, 0x00000000 },
{ 0x418a0c, 1, 0x04, 0x00010000 },
@@ -888,13 +888,13 @@ nvc0_grctx_init_zcullr_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nvc0_grctx_pack_zcull[] = {
{ nvc0_grctx_init_zcullr_0 },
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_pe_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
@@ -904,7 +904,7 @@ nvc0_grctx_init_pe_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc0_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
@@ -915,7 +915,7 @@ nvc0_grctx_init_tex_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_wwdx_0[] = {
{ 0x419b00, 1, 0x04, 0x0a418820 },
{ 0x419b04, 1, 0x04, 0x062080e6 },
@@ -929,7 +929,7 @@ nvc0_grctx_init_wwdx_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x00000002 },
{ 0x419c04, 1, 0x04, 0x00000006 },
@@ -938,7 +938,7 @@ nvc0_grctx_init_mpc_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc0_grctx_init_l1c_0[] = {
{ 0x419cb0, 1, 0x04, 0x00060048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
@@ -946,14 +946,14 @@ nvc0_grctx_init_l1c_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc0_grctx_init_tpccs_0[] = {
{ 0x419d20, 1, 0x04, 0x02180000 },
{ 0x419d24, 1, 0x04, 0x00001fff },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc0_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
@@ -966,7 +966,7 @@ nvc0_grctx_init_sm_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nvc0_grctx_pack_tpc[] = {
{ nvc0_grctx_init_pe_0 },
{ nvc0_grctx_init_tex_0 },
@@ -1049,7 +1049,7 @@ nvc0_grctx_generate_pagepool(struct nvc0_grctx *info)
void
nvc0_grctx_generate_attrib(struct nvc0_grctx *info)
{
- struct nvc0_graph_priv *priv = info->priv;
+ struct nvc0_gr_priv *priv = info->priv;
const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
const u32 attrib = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
@@ -1074,12 +1074,12 @@ nvc0_grctx_generate_attrib(struct nvc0_grctx *info)
}
void
-nvc0_grctx_generate_unkn(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate_unkn(struct nvc0_gr_priv *priv)
{
}
void
-nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate_tpcid(struct nvc0_gr_priv *priv)
{
int gpc, tpc, id;
@@ -1100,7 +1100,7 @@ nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
}
void
-nvc0_grctx_generate_r406028(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate_r406028(struct nvc0_gr_priv *priv)
{
u32 tmp[GPC_MAX / 8] = {}, i = 0;
for (i = 0; i < priv->gpc_nr; i++)
@@ -1112,7 +1112,7 @@ nvc0_grctx_generate_r406028(struct nvc0_graph_priv *priv)
}
void
-nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate_r4060a8(struct nvc0_gr_priv *priv)
{
u8 tpcnr[GPC_MAX], data[TPC_MAX];
int gpc, tpc, i;
@@ -1134,7 +1134,7 @@ nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *priv)
}
void
-nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate_r418bb8(struct nvc0_gr_priv *priv)
{
u32 data[6] = {}, data2[2] = {};
u8 tpcnr[GPC_MAX];
@@ -1192,7 +1192,7 @@ nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
}
void
-nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate_r406800(struct nvc0_gr_priv *priv)
{
u64 tpc_mask = 0, tpc_set = 0;
u8 tpcnr[GPC_MAX];
@@ -1225,17 +1225,17 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
}
void
-nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+nvc0_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
{
struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
- nvc0_graph_mmio(priv, oclass->hub);
- nvc0_graph_mmio(priv, oclass->gpc);
- nvc0_graph_mmio(priv, oclass->zcull);
- nvc0_graph_mmio(priv, oclass->tpc);
- nvc0_graph_mmio(priv, oclass->ppc);
+ nvc0_gr_mmio(priv, oclass->hub);
+ nvc0_gr_mmio(priv, oclass->gpc);
+ nvc0_gr_mmio(priv, oclass->zcull);
+ nvc0_gr_mmio(priv, oclass->tpc);
+ nvc0_gr_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
@@ -1250,14 +1250,14 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
nvc0_grctx_generate_r418bb8(priv);
nvc0_grctx_generate_r406800(priv);
- nvc0_graph_icmd(priv, oclass->icmd);
+ nvc0_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
- nvc0_graph_mthd(priv, oclass->mthd);
+ nvc0_gr_mthd(priv, oclass->mthd);
nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
}
int
-nvc0_grctx_generate(struct nvc0_graph_priv *priv)
+nvc0_grctx_generate(struct nvc0_gr_priv *priv)
{
struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
struct nouveau_bar *bar = nouveau_bar(priv);
@@ -1361,12 +1361,12 @@ struct nouveau_oclass *
nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_context_ctor,
- .dtor = nvc0_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = _nouveau_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nvc0_gr_context_ctor,
+ .dtor = nvc0_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = _nouveau_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
.main = nvc0_grctx_generate_main,
.unkn = nvc0_grctx_generate_unkn,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h
new file mode 100644
index 000000000000..0dbcd5839252
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h
@@ -0,0 +1,202 @@
+#ifndef __NVKM_GRCTX_NVC0_H__
+#define __NVKM_GRCTX_NVC0_H__
+
+#include "nvc0.h"
+
+struct nvc0_grctx {
+ struct nvc0_gr_priv *priv;
+ struct nvc0_gr_data *data;
+ struct nvc0_gr_mmio *mmio;
+ int buffer_nr;
+ u64 buffer[4];
+ u64 addr;
+};
+
+int nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access);
+void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int);
+
+#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d))
+#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e))
+#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1)
+#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1)
+
+struct nvc0_grctx_oclass {
+ struct nouveau_oclass base;
+ /* main context generation function */
+ void (*main)(struct nvc0_gr_priv *, struct nvc0_grctx *);
+ /* context-specific modify-on-first-load list generation function */
+ void (*unkn)(struct nvc0_gr_priv *);
+ /* mmio context data */
+ const struct nvc0_gr_pack *hub;
+ const struct nvc0_gr_pack *gpc;
+ const struct nvc0_gr_pack *zcull;
+ const struct nvc0_gr_pack *tpc;
+ const struct nvc0_gr_pack *ppc;
+ /* indirect context data, generated with icmds/mthds */
+ const struct nvc0_gr_pack *icmd;
+ const struct nvc0_gr_pack *mthd;
+ /* bundle circular buffer */
+ void (*bundle)(struct nvc0_grctx *);
+ u32 bundle_size;
+ u32 bundle_min_gpm_fifo_depth;
+ u32 bundle_token_limit;
+ /* pagepool */
+ void (*pagepool)(struct nvc0_grctx *);
+ u32 pagepool_size;
+ /* attribute(/alpha) circular buffer */
+ void (*attrib)(struct nvc0_grctx *);
+ u32 attrib_nr_max;
+ u32 attrib_nr;
+ u32 alpha_nr_max;
+ u32 alpha_nr;
+};
+
+static inline const struct nvc0_grctx_oclass *
+nvc0_grctx_impl(struct nvc0_gr_priv *priv)
+{
+ return (void *)nv_engine(priv)->cclass;
+}
+
+extern struct nouveau_oclass *nvc0_grctx_oclass;
+int nvc0_grctx_generate(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *);
+void nvc0_grctx_generate_bundle(struct nvc0_grctx *);
+void nvc0_grctx_generate_pagepool(struct nvc0_grctx *);
+void nvc0_grctx_generate_attrib(struct nvc0_grctx *);
+void nvc0_grctx_generate_unkn(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_tpcid(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_r406028(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_r4060a8(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_r418bb8(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_r406800(struct nvc0_gr_priv *);
+
+extern struct nouveau_oclass *nvc1_grctx_oclass;
+void nvc1_grctx_generate_attrib(struct nvc0_grctx *);
+void nvc1_grctx_generate_unkn(struct nvc0_gr_priv *);
+
+extern struct nouveau_oclass *nvc4_grctx_oclass;
+extern struct nouveau_oclass *nvc8_grctx_oclass;
+
+extern struct nouveau_oclass *nvd7_grctx_oclass;
+void nvd7_grctx_generate_attrib(struct nvc0_grctx *);
+
+extern struct nouveau_oclass *nvd9_grctx_oclass;
+
+extern struct nouveau_oclass *nve4_grctx_oclass;
+extern struct nouveau_oclass *gk20a_grctx_oclass;
+void nve4_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *);
+void nve4_grctx_generate_bundle(struct nvc0_grctx *);
+void nve4_grctx_generate_pagepool(struct nvc0_grctx *);
+void nve4_grctx_generate_unkn(struct nvc0_gr_priv *);
+void nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *);
+
+extern struct nouveau_oclass *nvf0_grctx_oclass;
+extern struct nouveau_oclass *gk110b_grctx_oclass;
+extern struct nouveau_oclass *nv108_grctx_oclass;
+extern struct nouveau_oclass *gm107_grctx_oclass;
+
+/* context init value lists */
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_icmd[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_mthd[];
+extern const struct nvc0_gr_init nvc0_grctx_init_902d_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_9039_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_90c0_0[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_hub[];
+extern const struct nvc0_gr_init nvc0_grctx_init_main_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_fe_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_pri_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_memfmt_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_rstr2d_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_scc_0[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_gpc[];
+extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_prop_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_1[];
+extern const struct nvc0_gr_init nvc0_grctx_init_zcull_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_crstr_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_gpm_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_gcc_0[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_zcull[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_tpc[];
+extern const struct nvc0_gr_init nvc0_grctx_init_pe_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_wwdx_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_mpc_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_tpccs_0[];
+
+extern const struct nvc0_gr_init nvc4_grctx_init_tex_0[];
+extern const struct nvc0_gr_init nvc4_grctx_init_l1c_0[];
+extern const struct nvc0_gr_init nvc4_grctx_init_sm_0[];
+
+extern const struct nvc0_gr_init nvc1_grctx_init_9097_0[];
+
+extern const struct nvc0_gr_init nvc1_grctx_init_gpm_0[];
+
+extern const struct nvc0_gr_init nvc1_grctx_init_pe_0[];
+extern const struct nvc0_gr_init nvc1_grctx_init_wwdx_0[];
+extern const struct nvc0_gr_init nvc1_grctx_init_tpccs_0[];
+
+extern const struct nvc0_gr_init nvc8_grctx_init_9197_0[];
+extern const struct nvc0_gr_init nvc8_grctx_init_9297_0[];
+
+extern const struct nvc0_gr_pack nvd9_grctx_pack_icmd[];
+
+extern const struct nvc0_gr_pack nvd9_grctx_pack_mthd[];
+
+extern const struct nvc0_gr_init nvd9_grctx_init_fe_0[];
+extern const struct nvc0_gr_init nvd9_grctx_init_be_0[];
+
+extern const struct nvc0_gr_init nvd9_grctx_init_prop_0[];
+extern const struct nvc0_gr_init nvd9_grctx_init_gpc_unk_1[];
+extern const struct nvc0_gr_init nvd9_grctx_init_crstr_0[];
+
+extern const struct nvc0_gr_init nvd9_grctx_init_sm_0[];
+
+extern const struct nvc0_gr_init nvd7_grctx_init_pe_0[];
+
+extern const struct nvc0_gr_init nvd7_grctx_init_wwdx_0[];
+
+extern const struct nvc0_gr_init nve4_grctx_init_memfmt_0[];
+extern const struct nvc0_gr_init nve4_grctx_init_ds_0[];
+extern const struct nvc0_gr_init nve4_grctx_init_scc_0[];
+
+extern const struct nvc0_gr_init nve4_grctx_init_gpm_0[];
+
+extern const struct nvc0_gr_init nve4_grctx_init_pes_0[];
+
+extern const struct nvc0_gr_pack nve4_grctx_pack_hub[];
+extern const struct nvc0_gr_pack nve4_grctx_pack_gpc[];
+extern const struct nvc0_gr_pack nve4_grctx_pack_tpc[];
+extern const struct nvc0_gr_pack nve4_grctx_pack_ppc[];
+extern const struct nvc0_gr_pack nve4_grctx_pack_icmd[];
+extern const struct nvc0_gr_init nve4_grctx_init_a097_0[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_icmd[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_mthd[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_hub[];
+extern const struct nvc0_gr_init nvf0_grctx_init_pri_0[];
+extern const struct nvc0_gr_init nvf0_grctx_init_cwd_0[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_gpc[];
+extern const struct nvc0_gr_init nvf0_grctx_init_gpc_unk_2[];
+
+extern const struct nvc0_gr_init nvf0_grctx_init_tex_0[];
+extern const struct nvc0_gr_init nvf0_grctx_init_mpc_0[];
+extern const struct nvc0_gr_init nvf0_grctx_init_l1c_0[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_ppc[];
+
+extern const struct nvc0_gr_init nv108_grctx_init_rstr2d_0[];
+
+extern const struct nvc0_gr_init nv108_grctx_init_prop_0[];
+extern const struct nvc0_gr_init nv108_grctx_init_crstr_0[];
+
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc1.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c
index c6ba8fed18f1..b5ced99abce9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc1.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c
@@ -28,7 +28,7 @@
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc1_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
@@ -267,13 +267,13 @@ nvc1_grctx_init_icmd_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvc1_grctx_pack_icmd[] = {
{ nvc1_grctx_init_icmd_0 },
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc1_grctx_init_9097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
@@ -575,14 +575,14 @@ nvc1_grctx_init_9097_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc1_grctx_init_9197_0[] = {
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvc1_grctx_pack_mthd[] = {
{ nvc1_grctx_init_9097_0, 0x9097 },
{ nvc1_grctx_init_9197_0, 0x9197 },
@@ -592,7 +592,7 @@ nvc1_grctx_pack_mthd[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc1_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180218 },
@@ -604,7 +604,7 @@ nvc1_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc1_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
@@ -616,7 +616,7 @@ nvc1_grctx_init_pd_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc1_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
@@ -628,7 +628,7 @@ nvc1_grctx_init_be_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvc1_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nvc0_grctx_init_fe_0 },
@@ -642,7 +642,7 @@ nvc1_grctx_pack_hub[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc1_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
@@ -655,7 +655,7 @@ nvc1_grctx_init_setup_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc1_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
@@ -665,7 +665,7 @@ nvc1_grctx_init_gpm_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvc1_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nvc0_grctx_init_prop_0 },
@@ -678,7 +678,7 @@ nvc1_grctx_pack_gpc[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc1_grctx_init_pe_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
@@ -688,7 +688,7 @@ nvc1_grctx_init_pe_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc1_grctx_init_wwdx_0[] = {
{ 0x419b00, 1, 0x04, 0x0a418820 },
{ 0x419b04, 1, 0x04, 0x062080e6 },
@@ -702,7 +702,7 @@ nvc1_grctx_init_wwdx_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc1_grctx_init_tpccs_0[] = {
{ 0x419d20, 1, 0x04, 0x12180000 },
{ 0x419d24, 1, 0x04, 0x00001fff },
@@ -710,7 +710,7 @@ nvc1_grctx_init_tpccs_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvc1_grctx_pack_tpc[] = {
{ nvc1_grctx_init_pe_0 },
{ nvc4_grctx_init_tex_0 },
@@ -729,7 +729,7 @@ nvc1_grctx_pack_tpc[] = {
void
nvc1_grctx_generate_attrib(struct nvc0_grctx *info)
{
- struct nvc0_graph_priv *priv = info->priv;
+ struct nvc0_gr_priv *priv = info->priv;
const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
const u32 alpha = impl->alpha_nr;
const u32 beta = impl->attrib_nr;
@@ -764,7 +764,7 @@ nvc1_grctx_generate_attrib(struct nvc0_grctx *info)
}
void
-nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv)
+nvc1_grctx_generate_unkn(struct nvc0_gr_priv *priv)
{
nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
@@ -778,12 +778,12 @@ struct nouveau_oclass *
nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc1),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_context_ctor,
- .dtor = nvc0_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = _nouveau_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nvc0_gr_context_ctor,
+ .dtor = nvc0_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = _nouveau_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
.main = nvc0_grctx_generate_main,
.unkn = nvc1_grctx_generate_unkn,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c
similarity index 90%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c
index 41705c60cc47..c883e7229fd5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c
@@ -28,7 +28,7 @@
* PGRAPH context register lists
******************************************************************************/
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc4_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
@@ -42,7 +42,7 @@ nvc4_grctx_init_tex_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc4_grctx_init_l1c_0[] = {
{ 0x419cb0, 1, 0x04, 0x00020048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
@@ -50,7 +50,7 @@ nvc4_grctx_init_l1c_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc4_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
@@ -64,7 +64,7 @@ nvc4_grctx_init_sm_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvc4_grctx_pack_tpc[] = {
{ nvc0_grctx_init_pe_0 },
{ nvc4_grctx_init_tex_0 },
@@ -84,12 +84,12 @@ struct nouveau_oclass *
nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc3),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_context_ctor,
- .dtor = nvc0_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = _nouveau_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nvc0_gr_context_ctor,
+ .dtor = nvc0_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = _nouveau_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
.main = nvc0_grctx_generate_main,
.unkn = nvc0_grctx_generate_unkn,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc8.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c
index 8f804cd8f9c7..4876a9375803 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc8.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c
@@ -28,7 +28,7 @@
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc8_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
@@ -268,19 +268,19 @@ nvc8_grctx_init_icmd_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvc8_grctx_pack_icmd[] = {
{ nvc8_grctx_init_icmd_0 },
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc8_grctx_init_9197_0[] = {
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvc8_grctx_init_9297_0[] = {
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x00036c, 2, 0x04, 0x00000000 },
@@ -290,7 +290,7 @@ nvc8_grctx_init_9297_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvc8_grctx_pack_mthd[] = {
{ nvc1_grctx_init_9097_0, 0x9097 },
{ nvc8_grctx_init_9197_0, 0x9197 },
@@ -301,7 +301,7 @@ nvc8_grctx_pack_mthd[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvc8_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
@@ -314,7 +314,7 @@ nvc8_grctx_init_setup_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvc8_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nvc0_grctx_init_prop_0 },
@@ -335,12 +335,12 @@ struct nouveau_oclass *
nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc8),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_context_ctor,
- .dtor = nvc0_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = _nouveau_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nvc0_gr_context_ctor,
+ .dtor = nvc0_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = _nouveau_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
.main = nvc0_grctx_generate_main,
.unkn = nvc0_grctx_generate_unkn,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c
similarity index 87%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd7.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c
index fcf534fd9e65..b53896c511d9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd7.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c
@@ -28,7 +28,7 @@
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd7_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180324 },
@@ -41,7 +41,7 @@ nvd7_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd7_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
@@ -54,7 +54,7 @@ nvd7_grctx_init_pd_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvd7_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nvd9_grctx_init_fe_0 },
@@ -68,7 +68,7 @@ nvd7_grctx_pack_hub[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd7_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
@@ -81,7 +81,7 @@ nvd7_grctx_init_setup_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvd7_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nvd9_grctx_init_prop_0 },
@@ -94,7 +94,7 @@ nvd7_grctx_pack_gpc[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvd7_grctx_init_pe_0[] = {
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
@@ -102,7 +102,7 @@ nvd7_grctx_init_pe_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd7_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
@@ -116,7 +116,7 @@ nvd7_grctx_init_tex_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd7_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x00000006 },
@@ -127,7 +127,7 @@ nvd7_grctx_init_mpc_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvd7_grctx_pack_tpc[] = {
{ nvd7_grctx_init_pe_0 },
{ nvd7_grctx_init_tex_0 },
@@ -137,13 +137,13 @@ nvd7_grctx_pack_tpc[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd7_grctx_init_pes_0[] = {
{ 0x41be24, 1, 0x04, 0x00000002 },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd7_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x12180000 },
{ 0x41bec4, 1, 0x04, 0x00003fff },
@@ -151,7 +151,7 @@ nvd7_grctx_init_cbm_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvd7_grctx_init_wwdx_0[] = {
{ 0x41bf00, 1, 0x04, 0x0a418820 },
{ 0x41bf04, 1, 0x04, 0x062080e6 },
@@ -165,7 +165,7 @@ nvd7_grctx_init_wwdx_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvd7_grctx_pack_ppc[] = {
{ nvd7_grctx_init_pes_0 },
{ nvd7_grctx_init_cbm_0 },
@@ -180,7 +180,7 @@ nvd7_grctx_pack_ppc[] = {
void
nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
{
- struct nvc0_graph_priv *priv = info->priv;
+ struct nvc0_gr_priv *priv = info->priv;
const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
const u32 alpha = impl->alpha_nr;
const u32 beta = impl->attrib_nr;
@@ -215,18 +215,18 @@ nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
}
void
-nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+nvd7_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
{
struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
int i;
nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
- nvc0_graph_mmio(priv, oclass->hub);
- nvc0_graph_mmio(priv, oclass->gpc);
- nvc0_graph_mmio(priv, oclass->zcull);
- nvc0_graph_mmio(priv, oclass->tpc);
- nvc0_graph_mmio(priv, oclass->ppc);
+ nvc0_gr_mmio(priv, oclass->hub);
+ nvc0_gr_mmio(priv, oclass->gpc);
+ nvc0_gr_mmio(priv, oclass->zcull);
+ nvc0_gr_mmio(priv, oclass->tpc);
+ nvc0_gr_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
@@ -244,9 +244,9 @@ nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
for (i = 0; i < 8; i++)
nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
- nvc0_graph_icmd(priv, oclass->icmd);
+ nvc0_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
- nvc0_graph_mthd(priv, oclass->mthd);
+ nvc0_gr_mthd(priv, oclass->mthd);
nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
}
@@ -254,12 +254,12 @@ struct nouveau_oclass *
nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xd7),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_context_ctor,
- .dtor = nvc0_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = _nouveau_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nvc0_gr_context_ctor,
+ .dtor = nvc0_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = _nouveau_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
.main = nvd7_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c
similarity index 95%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd9.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c
index b9a301b6fd9f..adc69e247bf2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd9.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c
@@ -28,7 +28,7 @@
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd9_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
@@ -270,13 +270,13 @@ nvd9_grctx_init_icmd_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nvd9_grctx_pack_icmd[] = {
{ nvd9_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd9_grctx_init_90c0_0[] = {
{ 0x002700, 8, 0x20, 0x00000000 },
{ 0x002704, 8, 0x20, 0x00000000 },
@@ -299,7 +299,7 @@ nvd9_grctx_init_90c0_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nvd9_grctx_pack_mthd[] = {
{ nvc1_grctx_init_9097_0, 0x9097 },
{ nvc8_grctx_init_9197_0, 0x9197 },
@@ -310,7 +310,7 @@ nvd9_grctx_pack_mthd[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvd9_grctx_init_fe_0[] = {
{ 0x404004, 10, 0x04, 0x00000000 },
{ 0x404044, 1, 0x04, 0x00000000 },
@@ -331,7 +331,7 @@ nvd9_grctx_init_fe_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd9_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180218 },
@@ -344,7 +344,7 @@ nvd9_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd9_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
@@ -356,7 +356,7 @@ nvd9_grctx_init_pd_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvd9_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
@@ -368,7 +368,7 @@ nvd9_grctx_init_be_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvd9_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nvd9_grctx_init_fe_0 },
@@ -382,7 +382,7 @@ nvd9_grctx_pack_hub[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvd9_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38004e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
@@ -395,7 +395,7 @@ nvd9_grctx_init_prop_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvd9_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000001f },
{ 0x418684, 1, 0x04, 0x0000000f },
@@ -405,7 +405,7 @@ nvd9_grctx_init_gpc_unk_1[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd9_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
@@ -418,7 +418,7 @@ nvd9_grctx_init_setup_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvd9_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x00000006 },
{ 0x418b08, 1, 0x04, 0x0a418820 },
@@ -431,7 +431,7 @@ nvd9_grctx_init_crstr_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvd9_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nvd9_grctx_init_prop_0 },
@@ -444,7 +444,7 @@ nvd9_grctx_pack_gpc[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd9_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
@@ -458,7 +458,7 @@ nvd9_grctx_init_tex_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvd9_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x00000006 },
@@ -469,7 +469,7 @@ nvd9_grctx_init_mpc_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvd9_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
@@ -483,7 +483,7 @@ nvd9_grctx_init_sm_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvd9_grctx_pack_tpc[] = {
{ nvc1_grctx_init_pe_0 },
{ nvd9_grctx_init_tex_0 },
@@ -503,12 +503,12 @@ struct nouveau_oclass *
nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xd9),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_context_ctor,
- .dtor = nvc0_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = _nouveau_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nvc0_gr_context_ctor,
+ .dtor = nvc0_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = _nouveau_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
.main = nvc0_grctx_generate_main,
.unkn = nvc1_grctx_generate_unkn,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c
similarity index 95%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnve4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c
index ccac2ee1a1cb..d78c7e7bbda0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnve4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c
@@ -28,7 +28,7 @@
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nve4_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
@@ -272,13 +272,13 @@ nve4_grctx_init_icmd_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nve4_grctx_pack_icmd[] = {
{ nve4_grctx_init_icmd_0 },
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nve4_grctx_init_a097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
@@ -578,14 +578,14 @@ nve4_grctx_init_a097_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nve4_grctx_pack_mthd[] = {
{ nve4_grctx_init_a097_0, 0xa097 },
{ nvc0_grctx_init_902d_0, 0x902d },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nve4_grctx_init_fe_0[] = {
{ 0x404010, 5, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
@@ -606,7 +606,7 @@ nve4_grctx_init_fe_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nve4_grctx_init_memfmt_0[] = {
{ 0x404604, 1, 0x04, 0x00000014 },
{ 0x404608, 1, 0x04, 0x00000000 },
@@ -632,7 +632,7 @@ nve4_grctx_init_memfmt_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nve4_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180648 },
@@ -645,14 +645,14 @@ nve4_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nve4_grctx_init_cwd_0[] = {
{ 0x405b00, 1, 0x04, 0x00000000 },
{ 0x405b10, 1, 0x04, 0x00001000 },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nve4_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x004103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
@@ -667,13 +667,13 @@ nve4_grctx_init_pd_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nve4_grctx_init_sked_0[] = {
{ 0x407040, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nve4_grctx_init_scc_0[] = {
{ 0x408000, 2, 0x04, 0x00000000 },
{ 0x408008, 1, 0x04, 0x00000030 },
@@ -684,7 +684,7 @@ nve4_grctx_init_scc_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nve4_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
@@ -697,7 +697,7 @@ nve4_grctx_init_be_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nve4_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nve4_grctx_init_fe_0 },
@@ -713,7 +713,7 @@ nve4_grctx_pack_hub[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nve4_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
@@ -726,7 +726,7 @@ nve4_grctx_init_setup_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nve4_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
@@ -737,7 +737,7 @@ nve4_grctx_init_gpm_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nve4_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nvd9_grctx_init_prop_0 },
@@ -750,7 +750,7 @@ nve4_grctx_pack_gpc[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nve4_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000000f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
@@ -765,7 +765,7 @@ nve4_grctx_init_tex_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nve4_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x80000006 },
@@ -776,14 +776,14 @@ nve4_grctx_init_mpc_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nve4_grctx_init_l1c_0[] = {
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00003203 },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nve4_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000402 },
@@ -802,7 +802,7 @@ nve4_grctx_init_sm_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nve4_grctx_pack_tpc[] = {
{ nvd7_grctx_init_pe_0 },
{ nve4_grctx_init_tex_0 },
@@ -812,13 +812,13 @@ nve4_grctx_pack_tpc[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nve4_grctx_init_pes_0[] = {
{ 0x41be24, 1, 0x04, 0x00000006 },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nve4_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x12180000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
@@ -826,7 +826,7 @@ nve4_grctx_init_cbm_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nve4_grctx_pack_ppc[] = {
{ nve4_grctx_init_pes_0 },
{ nve4_grctx_init_cbm_0 },
@@ -870,7 +870,7 @@ nve4_grctx_generate_pagepool(struct nvc0_grctx *info)
}
void
-nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv)
+nve4_grctx_generate_unkn(struct nvc0_gr_priv *priv)
{
nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
@@ -881,7 +881,7 @@ nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv)
}
void
-nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
+nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *priv)
{
u32 data[6] = {}, data2[2] = {};
u8 tpcnr[GPC_MAX];
@@ -939,18 +939,18 @@ nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
}
void
-nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+nve4_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
{
struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
int i;
nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
- nvc0_graph_mmio(priv, oclass->hub);
- nvc0_graph_mmio(priv, oclass->gpc);
- nvc0_graph_mmio(priv, oclass->zcull);
- nvc0_graph_mmio(priv, oclass->tpc);
- nvc0_graph_mmio(priv, oclass->ppc);
+ nvc0_gr_mmio(priv, oclass->hub);
+ nvc0_gr_mmio(priv, oclass->gpc);
+ nvc0_gr_mmio(priv, oclass->zcull);
+ nvc0_gr_mmio(priv, oclass->tpc);
+ nvc0_gr_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
@@ -977,9 +977,9 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
}
nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
- nvc0_graph_icmd(priv, oclass->icmd);
+ nvc0_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
- nvc0_graph_mthd(priv, oclass->mthd);
+ nvc0_gr_mthd(priv, oclass->mthd);
nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
nv_mask(priv, 0x418800, 0x00200000, 0x00200000);
@@ -990,12 +990,12 @@ struct nouveau_oclass *
nve4_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xe4),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_context_ctor,
- .dtor = nvc0_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = _nouveau_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nvc0_gr_context_ctor,
+ .dtor = nvc0_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = _nouveau_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
.main = nve4_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c
similarity index 97%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvf0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c
index e9b0dcf95a49..f7444690b4d4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvf0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c
@@ -28,7 +28,7 @@
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvf0_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
@@ -279,13 +279,13 @@ nvf0_grctx_init_icmd_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nvf0_grctx_pack_icmd[] = {
{ nvf0_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvf0_grctx_init_a197_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
@@ -587,14 +587,14 @@ nvf0_grctx_init_a197_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nvf0_grctx_pack_mthd[] = {
{ nvf0_grctx_init_a197_0, 0xa197 },
{ nvc0_grctx_init_902d_0, 0x902d },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvf0_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
@@ -620,7 +620,7 @@ nvf0_grctx_init_fe_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvf0_grctx_init_pri_0[] = {
{ 0x404404, 12, 0x04, 0x00000000 },
{ 0x404438, 1, 0x04, 0x00000000 },
@@ -632,7 +632,7 @@ nvf0_grctx_init_pri_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvf0_grctx_init_cwd_0[] = {
{ 0x405b00, 1, 0x04, 0x00000000 },
{ 0x405b10, 1, 0x04, 0x00001000 },
@@ -640,7 +640,7 @@ nvf0_grctx_init_cwd_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvf0_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x034103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
@@ -655,7 +655,7 @@ nvf0_grctx_init_pd_0[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvf0_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x12802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
@@ -668,7 +668,7 @@ nvf0_grctx_init_be_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nvf0_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nvf0_grctx_init_fe_0 },
@@ -683,7 +683,7 @@ nvf0_grctx_pack_hub[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvf0_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 1, 0x04, 0x00000000 },
@@ -698,13 +698,13 @@ nvf0_grctx_init_setup_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvf0_grctx_init_gpc_unk_2[] = {
{ 0x418d24, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nvf0_grctx_pack_gpc[] = {
{ nvc0_grctx_init_gpc_unk_0 },
{ nvd9_grctx_init_prop_0 },
@@ -718,7 +718,7 @@ nvf0_grctx_pack_gpc[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvf0_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000000f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
@@ -733,7 +733,7 @@ nvf0_grctx_init_tex_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvf0_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000001a },
{ 0x419c04, 1, 0x04, 0x80000006 },
@@ -744,14 +744,14 @@ nvf0_grctx_init_mpc_0[] = {
{}
};
-const struct nvc0_graph_init
+const struct nvc0_gr_init
nvf0_grctx_init_l1c_0[] = {
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000203 },
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvf0_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
@@ -779,7 +779,7 @@ nvf0_grctx_init_sm_0[] = {
{}
};
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
nvf0_grctx_pack_tpc[] = {
{ nvd7_grctx_init_pe_0 },
{ nvf0_grctx_init_tex_0 },
@@ -789,7 +789,7 @@ nvf0_grctx_pack_tpc[] = {
{}
};
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
nvf0_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x10000000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
@@ -797,7 +797,7 @@ nvf0_grctx_init_cbm_0[] = {
{}
};
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
nvf0_grctx_pack_ppc[] = {
{ nve4_grctx_init_pes_0 },
{ nvf0_grctx_init_cbm_0 },
@@ -813,12 +813,12 @@ struct nouveau_oclass *
nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xf0),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_context_ctor,
- .dtor = nvc0_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = _nouveau_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nvc0_gr_context_ctor,
+ .dtor = nvc0_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = _nouveau_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
.main = nve4_grctx_generate_main,
.unkn = nve4_grctx_generate_unkn,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/com.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/com.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpc.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcgm107.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnv108.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvc0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvd7.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnve0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/gpcnvf0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hub.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hub.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubgm107.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnv108.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvc0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvd7.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnve0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/hubnvf0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/macros.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/macros.fuc
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/os.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/fuc/os.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
similarity index 66%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/gk110b.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
index d07b19dc168d..59d7d9bf7bb5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/gk110b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
@@ -29,8 +29,8 @@
* PGRAPH register lists
******************************************************************************/
-static const struct nvc0_graph_init
-gk110b_graph_init_l1c_0[] = {
+static const struct nvc0_gr_init
+gk110b_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x09000000 },
@@ -44,8 +44,8 @@ gk110b_graph_init_l1c_0[] = {
{}
};
-static const struct nvc0_graph_init
-gk110b_graph_init_sm_0[] = {
+static const struct nvc0_gr_init
+gk110b_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000080 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
@@ -61,37 +61,37 @@ gk110b_graph_init_sm_0[] = {
{}
};
-static const struct nvc0_graph_pack
-gk110b_graph_pack_mmio[] = {
- { nve4_graph_init_main_0 },
- { nvf0_graph_init_fe_0 },
- { nvc0_graph_init_pri_0 },
- { nvc0_graph_init_rstr2d_0 },
- { nvd9_graph_init_pd_0 },
- { nvf0_graph_init_ds_0 },
- { nvc0_graph_init_scc_0 },
- { nvf0_graph_init_sked_0 },
- { nvf0_graph_init_cwd_0 },
- { nvd9_graph_init_prop_0 },
- { nvc1_graph_init_gpc_unk_0 },
- { nvc0_graph_init_setup_0 },
- { nvc0_graph_init_crstr_0 },
- { nvc1_graph_init_setup_1 },
- { nvc0_graph_init_zcull_0 },
- { nvd9_graph_init_gpm_0 },
- { nvf0_graph_init_gpc_unk_1 },
- { nvc0_graph_init_gcc_0 },
- { nve4_graph_init_tpccs_0 },
- { nvf0_graph_init_tex_0 },
- { nve4_graph_init_pe_0 },
- { gk110b_graph_init_l1c_0 },
- { nvc0_graph_init_mpc_0 },
- { gk110b_graph_init_sm_0 },
- { nvd7_graph_init_pes_0 },
- { nvd7_graph_init_wwdx_0 },
- { nvd7_graph_init_cbm_0 },
- { nve4_graph_init_be_0 },
- { nvc0_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+gk110b_gr_pack_mmio[] = {
+ { nve4_gr_init_main_0 },
+ { nvf0_gr_init_fe_0 },
+ { nvc0_gr_init_pri_0 },
+ { nvc0_gr_init_rstr2d_0 },
+ { nvd9_gr_init_pd_0 },
+ { nvf0_gr_init_ds_0 },
+ { nvc0_gr_init_scc_0 },
+ { nvf0_gr_init_sked_0 },
+ { nvf0_gr_init_cwd_0 },
+ { nvd9_gr_init_prop_0 },
+ { nvc1_gr_init_gpc_unk_0 },
+ { nvc0_gr_init_setup_0 },
+ { nvc0_gr_init_crstr_0 },
+ { nvc1_gr_init_setup_1 },
+ { nvc0_gr_init_zcull_0 },
+ { nvd9_gr_init_gpm_0 },
+ { nvf0_gr_init_gpc_unk_1 },
+ { nvc0_gr_init_gcc_0 },
+ { nve4_gr_init_tpccs_0 },
+ { nvf0_gr_init_tex_0 },
+ { nve4_gr_init_pe_0 },
+ { gk110b_gr_init_l1c_0 },
+ { nvc0_gr_init_mpc_0 },
+ { gk110b_gr_init_sm_0 },
+ { nvd7_gr_init_pes_0 },
+ { nvd7_gr_init_wwdx_0 },
+ { nvd7_gr_init_cbm_0 },
+ { nve4_gr_init_be_0 },
+ { nvc0_gr_init_fe_1 },
{}
};
@@ -100,18 +100,18 @@ gk110b_graph_pack_mmio[] = {
******************************************************************************/
struct nouveau_oclass *
-gk110b_graph_oclass = &(struct nvc0_graph_oclass) {
+gk110b_gr_oclass = &(struct nvc0_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xf1),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_ctor,
- .dtor = nvc0_graph_dtor,
- .init = nve4_graph_init,
- .fini = nvf0_graph_fini,
+ .ctor = nvc0_gr_ctor,
+ .dtor = nvc0_gr_dtor,
+ .init = nve4_gr_init,
+ .fini = nvf0_gr_fini,
},
.cclass = &gk110b_grctx_oclass,
- .sclass = nvf0_graph_sclass,
- .mmio = gk110b_graph_pack_mmio,
- .fecs.ucode = &nvf0_graph_fecs_ucode,
- .gpccs.ucode = &nvf0_graph_gpccs_ucode,
+ .sclass = nvf0_gr_sclass,
+ .mmio = gk110b_gr_pack_mmio,
+ .fecs.ucode = &nvf0_gr_fecs_ucode,
+ .gpccs.ucode = &nvf0_gr_gpccs_ucode,
.ppc_nr = 2,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
similarity index 79%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
index 7d0abe9f3fe7..082ea9f08e1c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
@@ -24,25 +24,25 @@
#include "ctxnvc0.h"
static struct nouveau_oclass
-gk20a_graph_sclass[] = {
+gk20a_gr_sclass[] = {
{ 0x902d, &nouveau_object_ofuncs },
{ 0xa040, &nouveau_object_ofuncs },
- { KEPLER_C, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
- { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+ { KEPLER_C, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+ { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
{}
};
struct nouveau_oclass *
-gk20a_graph_oclass = &(struct nvc0_graph_oclass) {
+gk20a_gr_oclass = &(struct nvc0_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xea),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_ctor,
- .dtor = nvc0_graph_dtor,
- .init = nve4_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nvc0_gr_ctor,
+ .dtor = nvc0_gr_dtor,
+ .init = nve4_gr_init,
+ .fini = _nouveau_gr_fini,
},
.cclass = &gk20a_grctx_oclass,
- .sclass = gk20a_graph_sclass,
- .mmio = nve4_graph_pack_mmio,
+ .sclass = gk20a_gr_sclass,
+ .mmio = nve4_gr_pack_mmio,
.ppc_nr = 1,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
similarity index 77%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/gm107.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
index 4bdbdab2fd9a..5a4669087a17 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
@@ -33,11 +33,11 @@
******************************************************************************/
static struct nouveau_oclass
-gm107_graph_sclass[] = {
+gm107_gr_sclass[] = {
{ 0x902d, &nouveau_object_ofuncs },
{ 0xa140, &nouveau_object_ofuncs },
- { MAXWELL_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
- { MAXWELL_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+ { MAXWELL_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+ { MAXWELL_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
{}
};
@@ -45,8 +45,8 @@ gm107_graph_sclass[] = {
* PGRAPH register lists
******************************************************************************/
-static const struct nvc0_graph_init
-gm107_graph_init_main_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003003c2 },
{ 0x400088, 1, 0x04, 0x0001bfe7 },
{ 0x40008c, 1, 0x04, 0x00060000 },
@@ -61,8 +61,8 @@ gm107_graph_init_main_0[] = {
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_ds_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00000000 },
@@ -70,37 +70,37 @@ gm107_graph_init_ds_0[] = {
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_scc_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_scc_0[] = {
{ 0x40803c, 1, 0x04, 0x00000010 },
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_sked_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_sked_0[] = {
{ 0x407010, 1, 0x04, 0x00000000 },
{ 0x407040, 1, 0x04, 0x40440424 },
{ 0x407048, 1, 0x04, 0x0000000a },
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_prop_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_prop_0[] = {
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_setup_1[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_setup_1[] = {
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
{ 0x4188d4, 1, 0x04, 0x00010201 },
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_zcull_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_zcull_0[] = {
{ 0x418910, 1, 0x04, 0x00010001 },
{ 0x418914, 1, 0x04, 0x00000301 },
{ 0x418918, 1, 0x04, 0x00800000 },
@@ -110,8 +110,8 @@ gm107_graph_init_zcull_0[] = {
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_gpc_unk_1[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000400 },
{ 0x418f08, 1, 0x04, 0x00000000 },
@@ -119,8 +119,8 @@ gm107_graph_init_gpc_unk_1[] = {
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_tpccs_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_tpccs_0[] = {
{ 0x419dc4, 1, 0x04, 0x00000000 },
{ 0x419dc8, 1, 0x04, 0x00000501 },
{ 0x419dd0, 1, 0x04, 0x00000000 },
@@ -133,8 +133,8 @@ gm107_graph_init_tpccs_0[] = {
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_tex_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 1, 0x04, 0x00000000 },
@@ -147,8 +147,8 @@ gm107_graph_init_tex_0[] = {
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_pe_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_pe_0[] = {
{ 0x419900, 1, 0x04, 0x000000ff },
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
@@ -159,15 +159,15 @@ gm107_graph_init_pe_0[] = {
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_l1c_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_sm_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_sm_0[] = {
{ 0x419e30, 1, 0x04, 0x000000ff },
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
@@ -185,16 +185,16 @@ gm107_graph_init_sm_0[] = {
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_l1c_1[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_l1c_1[] = {
{ 0x419ccc, 2, 0x04, 0x00000000 },
{ 0x419c80, 1, 0x04, 0x3f006022 },
{ 0x419c88, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_pes_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_pes_0[] = {
{ 0x41be50, 1, 0x04, 0x000000ff },
{ 0x41be04, 1, 0x04, 0x00000000 },
{ 0x41be08, 1, 0x04, 0x00000004 },
@@ -205,21 +205,21 @@ gm107_graph_init_pes_0[] = {
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_wwdx_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_wwdx_0[] = {
{ 0x41bfd4, 1, 0x04, 0x00800000 },
{ 0x41bfdc, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_cbm_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_cbm_0[] = {
{ 0x41becc, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_be_0[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_be_0[] = {
{ 0x408890, 1, 0x04, 0x000000ff },
{ 0x40880c, 1, 0x04, 0x00000000 },
{ 0x408850, 1, 0x04, 0x00000004 },
@@ -244,45 +244,45 @@ gm107_graph_init_be_0[] = {
{}
};
-static const struct nvc0_graph_init
-gm107_graph_init_sm_1[] = {
+static const struct nvc0_gr_init
+gm107_gr_init_sm_1[] = {
{ 0x419e5c, 1, 0x04, 0x00000000 },
{ 0x419e58, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_graph_pack
-gm107_graph_pack_mmio[] = {
- { gm107_graph_init_main_0 },
- { nvf0_graph_init_fe_0 },
- { nvc0_graph_init_pri_0 },
- { nvc0_graph_init_rstr2d_0 },
- { nvc0_graph_init_pd_0 },
- { gm107_graph_init_ds_0 },
- { gm107_graph_init_scc_0 },
- { gm107_graph_init_sked_0 },
- { nvf0_graph_init_cwd_0 },
- { gm107_graph_init_prop_0 },
- { nv108_graph_init_gpc_unk_0 },
- { nvc0_graph_init_setup_0 },
- { nvc0_graph_init_crstr_0 },
- { gm107_graph_init_setup_1 },
- { gm107_graph_init_zcull_0 },
- { nvc0_graph_init_gpm_0 },
- { gm107_graph_init_gpc_unk_1 },
- { nvc0_graph_init_gcc_0 },
- { gm107_graph_init_tpccs_0 },
- { gm107_graph_init_tex_0 },
- { gm107_graph_init_pe_0 },
- { gm107_graph_init_l1c_0 },
- { nvc0_graph_init_mpc_0 },
- { gm107_graph_init_sm_0 },
- { gm107_graph_init_l1c_1 },
- { gm107_graph_init_pes_0 },
- { gm107_graph_init_wwdx_0 },
- { gm107_graph_init_cbm_0 },
- { gm107_graph_init_be_0 },
- { gm107_graph_init_sm_1 },
+static const struct nvc0_gr_pack
+gm107_gr_pack_mmio[] = {
+ { gm107_gr_init_main_0 },
+ { nvf0_gr_init_fe_0 },
+ { nvc0_gr_init_pri_0 },
+ { nvc0_gr_init_rstr2d_0 },
+ { nvc0_gr_init_pd_0 },
+ { gm107_gr_init_ds_0 },
+ { gm107_gr_init_scc_0 },
+ { gm107_gr_init_sked_0 },
+ { nvf0_gr_init_cwd_0 },
+ { gm107_gr_init_prop_0 },
+ { nv108_gr_init_gpc_unk_0 },
+ { nvc0_gr_init_setup_0 },
+ { nvc0_gr_init_crstr_0 },
+ { gm107_gr_init_setup_1 },
+ { gm107_gr_init_zcull_0 },
+ { nvc0_gr_init_gpm_0 },
+ { gm107_gr_init_gpc_unk_1 },
+ { nvc0_gr_init_gcc_0 },
+ { gm107_gr_init_tpccs_0 },
+ { gm107_gr_init_tex_0 },
+ { gm107_gr_init_pe_0 },
+ { gm107_gr_init_l1c_0 },
+ { nvc0_gr_init_mpc_0 },
+ { gm107_gr_init_sm_0 },
+ { gm107_gr_init_l1c_1 },
+ { gm107_gr_init_pes_0 },
+ { gm107_gr_init_wwdx_0 },
+ { gm107_gr_init_cbm_0 },
+ { gm107_gr_init_be_0 },
+ { gm107_gr_init_sm_1 },
{}
};
@@ -291,7 +291,7 @@ gm107_graph_pack_mmio[] = {
******************************************************************************/
static void
-gm107_graph_init_bios(struct nvc0_graph_priv *priv)
+gm107_gr_init_bios(struct nvc0_gr_priv *priv)
{
static const struct {
u32 ctrl;
@@ -319,17 +319,17 @@ gm107_graph_init_bios(struct nvc0_graph_priv *priv)
}
int
-gm107_graph_init(struct nouveau_object *object)
+gm107_gr_init(struct nouveau_object *object)
{
- struct nvc0_graph_oclass *oclass = (void *)object->oclass;
- struct nvc0_graph_priv *priv = (void *)object;
+ struct nvc0_gr_oclass *oclass = (void *)object->oclass;
+ struct nvc0_gr_priv *priv = (void *)object;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, ppc, rop;
int ret, i;
- ret = nouveau_graph_init(&priv->base);
+ ret = nouveau_gr_init(&priv->base);
if (ret)
return ret;
@@ -339,9 +339,9 @@ gm107_graph_init(struct nouveau_object *object)
nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
- nvc0_graph_mmio(priv, oclass->mmio);
+ nvc0_gr_mmio(priv, oclass->mmio);
- gm107_graph_init_bios(priv);
+ gm107_gr_init_bios(priv);
nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
@@ -426,15 +426,15 @@ gm107_graph_init(struct nouveau_object *object)
nv_wr32(priv, 0x400054, 0x2c350f63);
- nvc0_graph_zbc_init(priv);
+ nvc0_gr_zbc_init(priv);
- return nvc0_graph_init_ctxctl(priv);
+ return nvc0_gr_init_ctxctl(priv);
}
#include "fuc/hubgm107.fuc5.h"
-static struct nvc0_graph_ucode
-gm107_graph_fecs_ucode = {
+static struct nvc0_gr_ucode
+gm107_gr_fecs_ucode = {
.code.data = gm107_grhub_code,
.code.size = sizeof(gm107_grhub_code),
.data.data = gm107_grhub_data,
@@ -443,8 +443,8 @@ gm107_graph_fecs_ucode = {
#include "fuc/gpcgm107.fuc5.h"
-static struct nvc0_graph_ucode
-gm107_graph_gpccs_ucode = {
+static struct nvc0_gr_ucode
+gm107_gr_gpccs_ucode = {
.code.data = gm107_grgpc_code,
.code.size = sizeof(gm107_grgpc_code),
.data.data = gm107_grgpc_data,
@@ -452,18 +452,18 @@ gm107_graph_gpccs_ucode = {
};
struct nouveau_oclass *
-gm107_graph_oclass = &(struct nvc0_graph_oclass) {
+gm107_gr_oclass = &(struct nvc0_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0x07),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_ctor,
- .dtor = nvc0_graph_dtor,
- .init = gm107_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nvc0_gr_ctor,
+ .dtor = nvc0_gr_dtor,
+ .init = gm107_gr_init,
+ .fini = _nouveau_gr_fini,
},
.cclass = &gm107_grctx_oclass,
- .sclass = gm107_graph_sclass,
- .mmio = gm107_graph_pack_mmio,
- .fecs.ucode = 0 ? &gm107_graph_fecs_ucode : NULL,
- .gpccs.ucode = &gm107_graph_gpccs_ucode,
+ .sclass = gm107_gr_sclass,
+ .mmio = gm107_gr_pack_mmio,
+ .fecs.ucode = 0 ? &gm107_gr_fecs_ucode : NULL,
+ .gpccs.ucode = &gm107_gr_gpccs_ucode,
.ppc_nr = 2,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
similarity index 61%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
index f70e2f67a4dd..4d25c9532b2b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
@@ -10,7 +10,7 @@
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
+ * paragr) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
@@ -32,12 +32,12 @@
#include <subdev/timer.h>
#include <engine/fifo.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include "regs.h"
static u32
-nv04_graph_ctx_regs[] = {
+nv04_gr_ctx_regs[] = {
0x0040053c,
0x00400544,
0x00400540,
@@ -351,21 +351,21 @@ nv04_graph_ctx_regs[] = {
NV04_PGRAPH_DEBUG_3
};
-struct nv04_graph_priv {
- struct nouveau_graph base;
- struct nv04_graph_chan *chan[16];
+struct nv04_gr_priv {
+ struct nouveau_gr base;
+ struct nv04_gr_chan *chan[16];
spinlock_t lock;
};
-struct nv04_graph_chan {
+struct nv04_gr_chan {
struct nouveau_object base;
int chid;
- u32 nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
+ u32 nv04[ARRAY_SIZE(nv04_gr_ctx_regs)];
};
-static inline struct nv04_graph_priv *
-nv04_graph_priv(struct nv04_graph_chan *chan)
+static inline struct nv04_gr_priv *
+nv04_gr_priv(struct nv04_gr_chan *chan)
{
return (void *)nv_object(chan)->engine;
}
@@ -449,9 +449,9 @@ nv04_graph_priv(struct nv04_graph_chan *chan)
*/
static void
-nv04_graph_set_ctx1(struct nouveau_object *object, u32 mask, u32 value)
+nv04_gr_set_ctx1(struct nouveau_object *object, u32 mask, u32 value)
{
- struct nv04_graph_priv *priv = (void *)object->engine;
+ struct nv04_gr_priv *priv = (void *)object->engine;
int subc = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
u32 tmp;
@@ -465,7 +465,7 @@ nv04_graph_set_ctx1(struct nouveau_object *object, u32 mask, u32 value)
}
static void
-nv04_graph_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value)
+nv04_gr_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value)
{
int class, op, valid = 1;
u32 tmp, ctx1;
@@ -509,11 +509,11 @@ nv04_graph_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value)
break;
}
- nv04_graph_set_ctx1(object, 0x01000000, valid << 24);
+ nv04_gr_set_ctx1(object, 0x01000000, valid << 24);
}
static int
-nv04_graph_mthd_set_operation(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_set_operation(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
u32 class = nv_ro32(object, 0) & 0xff;
@@ -523,17 +523,17 @@ nv04_graph_mthd_set_operation(struct nouveau_object *object, u32 mthd,
/* Old versions of the objects only accept first three operations. */
if (data > 2 && class < 0x40)
return 1;
- nv04_graph_set_ctx1(object, 0x00038000, data << 15);
+ nv04_gr_set_ctx1(object, 0x00038000, data << 15);
/* changing operation changes set of objects needed for validation */
- nv04_graph_set_ctx_val(object, 0, 0);
+ nv04_gr_set_ctx_val(object, 0, 0);
return 0;
}
static int
-nv04_graph_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv04_graph_priv *priv = (void *)object->engine;
+ struct nv04_gr_priv *priv = (void *)object->engine;
u32 data = *(u32 *)args;
u32 min = data & 0xffff, max;
u32 w = data >> 16;
@@ -551,10 +551,10 @@ nv04_graph_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd,
}
static int
-nv04_graph_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv04_graph_priv *priv = (void *)object->engine;
+ struct nv04_gr_priv *priv = (void *)object->engine;
u32 data = *(u32 *)args;
u32 min = data & 0xffff, max;
u32 w = data >> 16;
@@ -572,7 +572,7 @@ nv04_graph_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd,
}
static u16
-nv04_graph_mthd_bind_class(struct nouveau_object *object, u32 *args, u32 size)
+nv04_gr_mthd_bind_class(struct nouveau_object *object, u32 *args, u32 size)
{
struct nouveau_instmem *imem = nouveau_instmem(object);
u32 inst = *(u32 *)args << 4;
@@ -580,380 +580,380 @@ nv04_graph_mthd_bind_class(struct nouveau_object *object, u32 *args, u32 size)
}
static int
-nv04_graph_mthd_bind_surf2d(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf2d(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- switch (nv04_graph_mthd_bind_class(object, args, size)) {
+ switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
- nv04_graph_set_ctx1(object, 0x00004000, 0);
- nv04_graph_set_ctx_val(object, 0x02000000, 0);
+ nv04_gr_set_ctx1(object, 0x00004000, 0);
+ nv04_gr_set_ctx_val(object, 0x02000000, 0);
return 0;
case 0x42:
- nv04_graph_set_ctx1(object, 0x00004000, 0);
- nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
+ nv04_gr_set_ctx1(object, 0x00004000, 0);
+ nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000);
return 0;
}
return 1;
}
static int
-nv04_graph_mthd_bind_surf2d_swzsurf(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf2d_swzsurf(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- switch (nv04_graph_mthd_bind_class(object, args, size)) {
+ switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
- nv04_graph_set_ctx1(object, 0x00004000, 0);
- nv04_graph_set_ctx_val(object, 0x02000000, 0);
+ nv04_gr_set_ctx1(object, 0x00004000, 0);
+ nv04_gr_set_ctx_val(object, 0x02000000, 0);
return 0;
case 0x42:
- nv04_graph_set_ctx1(object, 0x00004000, 0);
- nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
+ nv04_gr_set_ctx1(object, 0x00004000, 0);
+ nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000);
return 0;
case 0x52:
- nv04_graph_set_ctx1(object, 0x00004000, 0x00004000);
- nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
+ nv04_gr_set_ctx1(object, 0x00004000, 0x00004000);
+ nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000);
return 0;
}
return 1;
}
static int
-nv01_graph_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
+nv01_gr_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- switch (nv04_graph_mthd_bind_class(object, args, size)) {
+ switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
- nv04_graph_set_ctx_val(object, 0x08000000, 0);
+ nv04_gr_set_ctx_val(object, 0x08000000, 0);
return 0;
case 0x18:
- nv04_graph_set_ctx_val(object, 0x08000000, 0x08000000);
+ nv04_gr_set_ctx_val(object, 0x08000000, 0x08000000);
return 0;
}
return 1;
}
static int
-nv04_graph_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- switch (nv04_graph_mthd_bind_class(object, args, size)) {
+ switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
- nv04_graph_set_ctx_val(object, 0x08000000, 0);
+ nv04_gr_set_ctx_val(object, 0x08000000, 0);
return 0;
case 0x44:
- nv04_graph_set_ctx_val(object, 0x08000000, 0x08000000);
+ nv04_gr_set_ctx_val(object, 0x08000000, 0x08000000);
return 0;
}
return 1;
}
static int
-nv04_graph_mthd_bind_rop(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_rop(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- switch (nv04_graph_mthd_bind_class(object, args, size)) {
+ switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
- nv04_graph_set_ctx_val(object, 0x10000000, 0);
+ nv04_gr_set_ctx_val(object, 0x10000000, 0);
return 0;
case 0x43:
- nv04_graph_set_ctx_val(object, 0x10000000, 0x10000000);
+ nv04_gr_set_ctx_val(object, 0x10000000, 0x10000000);
return 0;
}
return 1;
}
static int
-nv04_graph_mthd_bind_beta1(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_beta1(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- switch (nv04_graph_mthd_bind_class(object, args, size)) {
+ switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
- nv04_graph_set_ctx_val(object, 0x20000000, 0);
+ nv04_gr_set_ctx_val(object, 0x20000000, 0);
return 0;
case 0x12:
- nv04_graph_set_ctx_val(object, 0x20000000, 0x20000000);
+ nv04_gr_set_ctx_val(object, 0x20000000, 0x20000000);
return 0;
}
return 1;
}
static int
-nv04_graph_mthd_bind_beta4(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_beta4(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- switch (nv04_graph_mthd_bind_class(object, args, size)) {
+ switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
- nv04_graph_set_ctx_val(object, 0x40000000, 0);
+ nv04_gr_set_ctx_val(object, 0x40000000, 0);
return 0;
case 0x72:
- nv04_graph_set_ctx_val(object, 0x40000000, 0x40000000);
+ nv04_gr_set_ctx_val(object, 0x40000000, 0x40000000);
return 0;
}
return 1;
}
static int
-nv04_graph_mthd_bind_surf_dst(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf_dst(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- switch (nv04_graph_mthd_bind_class(object, args, size)) {
+ switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
- nv04_graph_set_ctx_val(object, 0x02000000, 0);
+ nv04_gr_set_ctx_val(object, 0x02000000, 0);
return 0;
case 0x58:
- nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
+ nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000);
return 0;
}
return 1;
}
static int
-nv04_graph_mthd_bind_surf_src(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf_src(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- switch (nv04_graph_mthd_bind_class(object, args, size)) {
+ switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
- nv04_graph_set_ctx_val(object, 0x04000000, 0);
+ nv04_gr_set_ctx_val(object, 0x04000000, 0);
return 0;
case 0x59:
- nv04_graph_set_ctx_val(object, 0x04000000, 0x04000000);
+ nv04_gr_set_ctx_val(object, 0x04000000, 0x04000000);
return 0;
}
return 1;
}
static int
-nv04_graph_mthd_bind_surf_color(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf_color(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- switch (nv04_graph_mthd_bind_class(object, args, size)) {
+ switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
- nv04_graph_set_ctx_val(object, 0x02000000, 0);
+ nv04_gr_set_ctx_val(object, 0x02000000, 0);
return 0;
case 0x5a:
- nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000);
+ nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000);
return 0;
}
return 1;
}
static int
-nv04_graph_mthd_bind_surf_zeta(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf_zeta(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- switch (nv04_graph_mthd_bind_class(object, args, size)) {
+ switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
- nv04_graph_set_ctx_val(object, 0x04000000, 0);
+ nv04_gr_set_ctx_val(object, 0x04000000, 0);
return 0;
case 0x5b:
- nv04_graph_set_ctx_val(object, 0x04000000, 0x04000000);
+ nv04_gr_set_ctx_val(object, 0x04000000, 0x04000000);
return 0;
}
return 1;
}
static int
-nv01_graph_mthd_bind_clip(struct nouveau_object *object, u32 mthd,
+nv01_gr_mthd_bind_clip(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- switch (nv04_graph_mthd_bind_class(object, args, size)) {
+ switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
- nv04_graph_set_ctx1(object, 0x2000, 0);
+ nv04_gr_set_ctx1(object, 0x2000, 0);
return 0;
case 0x19:
- nv04_graph_set_ctx1(object, 0x2000, 0x2000);
+ nv04_gr_set_ctx1(object, 0x2000, 0x2000);
return 0;
}
return 1;
}
static int
-nv01_graph_mthd_bind_chroma(struct nouveau_object *object, u32 mthd,
+nv01_gr_mthd_bind_chroma(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- switch (nv04_graph_mthd_bind_class(object, args, size)) {
+ switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
- nv04_graph_set_ctx1(object, 0x1000, 0);
+ nv04_gr_set_ctx1(object, 0x1000, 0);
return 0;
/* Yes, for some reason even the old versions of objects
* accept 0x57 and not 0x17. Consistency be damned.
*/
case 0x57:
- nv04_graph_set_ctx1(object, 0x1000, 0x1000);
+ nv04_gr_set_ctx1(object, 0x1000, 0x1000);
return 0;
}
return 1;
}
static struct nouveau_omthds
-nv03_graph_gdi_omthds[] = {
- { 0x0184, 0x0184, nv01_graph_mthd_bind_patt },
- { 0x0188, 0x0188, nv04_graph_mthd_bind_rop },
- { 0x018c, 0x018c, nv04_graph_mthd_bind_beta1 },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_surf_dst },
- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv03_gr_gdi_omthds[] = {
+ { 0x0184, 0x0184, nv01_gr_mthd_bind_patt },
+ { 0x0188, 0x0188, nv04_gr_mthd_bind_rop },
+ { 0x018c, 0x018c, nv04_gr_mthd_bind_beta1 },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_surf_dst },
+ { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
{}
};
static struct nouveau_omthds
-nv04_graph_gdi_omthds[] = {
- { 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
- { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv04_gr_gdi_omthds[] = {
+ { 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
+ { 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+ { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 },
+ { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d },
+ { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
{}
};
static struct nouveau_omthds
-nv01_graph_blit_omthds[] = {
- { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
- { 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
- { 0x018c, 0x018c, nv01_graph_mthd_bind_patt },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
- { 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst },
- { 0x019c, 0x019c, nv04_graph_mthd_bind_surf_src },
- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv01_gr_blit_omthds[] = {
+ { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
+ { 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
+ { 0x018c, 0x018c, nv01_gr_mthd_bind_patt },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_rop },
+ { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 },
+ { 0x0198, 0x0198, nv04_gr_mthd_bind_surf_dst },
+ { 0x019c, 0x019c, nv04_gr_mthd_bind_surf_src },
+ { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
{}
};
static struct nouveau_omthds
-nv04_graph_blit_omthds[] = {
- { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
- { 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
- { 0x018c, 0x018c, nv04_graph_mthd_bind_patt },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
- { 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 },
- { 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d },
- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv04_gr_blit_omthds[] = {
+ { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
+ { 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
+ { 0x018c, 0x018c, nv04_gr_mthd_bind_patt },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_rop },
+ { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 },
+ { 0x0198, 0x0198, nv04_gr_mthd_bind_beta4 },
+ { 0x019c, 0x019c, nv04_gr_mthd_bind_surf2d },
+ { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
{}
};
static struct nouveau_omthds
-nv04_graph_iifc_omthds[] = {
- { 0x0188, 0x0188, nv01_graph_mthd_bind_chroma },
- { 0x018c, 0x018c, nv01_graph_mthd_bind_clip },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_patt },
- { 0x0194, 0x0194, nv04_graph_mthd_bind_rop },
- { 0x0198, 0x0198, nv04_graph_mthd_bind_beta1 },
- { 0x019c, 0x019c, nv04_graph_mthd_bind_beta4 },
- { 0x01a0, 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf },
- { 0x03e4, 0x03e4, nv04_graph_mthd_set_operation },
+nv04_gr_iifc_omthds[] = {
+ { 0x0188, 0x0188, nv01_gr_mthd_bind_chroma },
+ { 0x018c, 0x018c, nv01_gr_mthd_bind_clip },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_patt },
+ { 0x0194, 0x0194, nv04_gr_mthd_bind_rop },
+ { 0x0198, 0x0198, nv04_gr_mthd_bind_beta1 },
+ { 0x019c, 0x019c, nv04_gr_mthd_bind_beta4 },
+ { 0x01a0, 0x01a0, nv04_gr_mthd_bind_surf2d_swzsurf },
+ { 0x03e4, 0x03e4, nv04_gr_mthd_set_operation },
{}
};
static struct nouveau_omthds
-nv01_graph_ifc_omthds[] = {
- { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
- { 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
- { 0x018c, 0x018c, nv01_graph_mthd_bind_patt },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
- { 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst },
- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv01_gr_ifc_omthds[] = {
+ { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
+ { 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
+ { 0x018c, 0x018c, nv01_gr_mthd_bind_patt },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_rop },
+ { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 },
+ { 0x0198, 0x0198, nv04_gr_mthd_bind_surf_dst },
+ { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
{}
};
static struct nouveau_omthds
-nv04_graph_ifc_omthds[] = {
- { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
- { 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
- { 0x018c, 0x018c, nv04_graph_mthd_bind_patt },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_rop },
- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 },
- { 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 },
- { 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d },
- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv04_gr_ifc_omthds[] = {
+ { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
+ { 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
+ { 0x018c, 0x018c, nv04_gr_mthd_bind_patt },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_rop },
+ { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 },
+ { 0x0198, 0x0198, nv04_gr_mthd_bind_beta4 },
+ { 0x019c, 0x019c, nv04_gr_mthd_bind_surf2d },
+ { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
{}
};
static struct nouveau_omthds
-nv03_graph_sifc_omthds[] = {
- { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
- { 0x0188, 0x0188, nv01_graph_mthd_bind_patt },
- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
- { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst },
- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv03_gr_sifc_omthds[] = {
+ { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
+ { 0x0188, 0x0188, nv01_gr_mthd_bind_patt },
+ { 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+ { 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst },
+ { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
{}
};
static struct nouveau_omthds
-nv04_graph_sifc_omthds[] = {
- { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma },
- { 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
- { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv04_gr_sifc_omthds[] = {
+ { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
+ { 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
+ { 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+ { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 },
+ { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d },
+ { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
{}
};
static struct nouveau_omthds
-nv03_graph_sifm_omthds[] = {
- { 0x0188, 0x0188, nv01_graph_mthd_bind_patt },
- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
- { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst },
- { 0x0304, 0x0304, nv04_graph_mthd_set_operation },
+nv03_gr_sifm_omthds[] = {
+ { 0x0188, 0x0188, nv01_gr_mthd_bind_patt },
+ { 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+ { 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst },
+ { 0x0304, 0x0304, nv04_gr_mthd_set_operation },
{}
};
static struct nouveau_omthds
-nv04_graph_sifm_omthds[] = {
- { 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
- { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
- { 0x0304, 0x0304, nv04_graph_mthd_set_operation },
+nv04_gr_sifm_omthds[] = {
+ { 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
+ { 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+ { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 },
+ { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d },
+ { 0x0304, 0x0304, nv04_gr_mthd_set_operation },
{}
};
static struct nouveau_omthds
-nv04_graph_surf3d_omthds[] = {
- { 0x02f8, 0x02f8, nv04_graph_mthd_surf3d_clip_h },
- { 0x02fc, 0x02fc, nv04_graph_mthd_surf3d_clip_v },
+nv04_gr_surf3d_omthds[] = {
+ { 0x02f8, 0x02f8, nv04_gr_mthd_surf3d_clip_h },
+ { 0x02fc, 0x02fc, nv04_gr_mthd_surf3d_clip_v },
{}
};
static struct nouveau_omthds
-nv03_graph_ttri_omthds[] = {
- { 0x0188, 0x0188, nv01_graph_mthd_bind_clip },
- { 0x018c, 0x018c, nv04_graph_mthd_bind_surf_color },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_surf_zeta },
+nv03_gr_ttri_omthds[] = {
+ { 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
+ { 0x018c, 0x018c, nv04_gr_mthd_bind_surf_color },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_surf_zeta },
{}
};
static struct nouveau_omthds
-nv01_graph_prim_omthds[] = {
- { 0x0184, 0x0184, nv01_graph_mthd_bind_clip },
- { 0x0188, 0x0188, nv01_graph_mthd_bind_patt },
- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
- { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst },
- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv01_gr_prim_omthds[] = {
+ { 0x0184, 0x0184, nv01_gr_mthd_bind_clip },
+ { 0x0188, 0x0188, nv01_gr_mthd_bind_patt },
+ { 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+ { 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst },
+ { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
{}
};
static struct nouveau_omthds
-nv04_graph_prim_omthds[] = {
- { 0x0184, 0x0184, nv01_graph_mthd_bind_clip },
- { 0x0188, 0x0188, nv04_graph_mthd_bind_patt },
- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop },
- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 },
- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 },
- { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d },
- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation },
+nv04_gr_prim_omthds[] = {
+ { 0x0184, 0x0184, nv01_gr_mthd_bind_clip },
+ { 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
+ { 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
+ { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 },
+ { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 },
+ { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d },
+ { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation },
{}
};
static int
-nv04_graph_object_ctor(struct nouveau_object *parent,
+nv04_gr_object_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
@@ -978,8 +978,8 @@ nv04_graph_object_ctor(struct nouveau_object *parent,
}
struct nouveau_ofuncs
-nv04_graph_ofuncs = {
- .ctor = nv04_graph_object_ctor,
+nv04_gr_ofuncs = {
+ .ctor = nv04_gr_object_ctor,
.dtor = _nouveau_gpuobj_dtor,
.init = _nouveau_gpuobj_init,
.fini = _nouveau_gpuobj_fini,
@@ -988,48 +988,48 @@ nv04_graph_ofuncs = {
};
static struct nouveau_oclass
-nv04_graph_sclass[] = {
- { 0x0012, &nv04_graph_ofuncs }, /* beta1 */
- { 0x0017, &nv04_graph_ofuncs }, /* chroma */
- { 0x0018, &nv04_graph_ofuncs }, /* pattern (nv01) */
- { 0x0019, &nv04_graph_ofuncs }, /* clip */
- { 0x001c, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* line */
- { 0x001d, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* tri */
- { 0x001e, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* rect */
- { 0x001f, &nv04_graph_ofuncs, nv01_graph_blit_omthds },
- { 0x0021, &nv04_graph_ofuncs, nv01_graph_ifc_omthds },
- { 0x0030, &nv04_graph_ofuncs }, /* null */
- { 0x0036, &nv04_graph_ofuncs, nv03_graph_sifc_omthds },
- { 0x0037, &nv04_graph_ofuncs, nv03_graph_sifm_omthds },
- { 0x0038, &nv04_graph_ofuncs }, /* dvd subpicture */
- { 0x0039, &nv04_graph_ofuncs }, /* m2mf */
- { 0x0042, &nv04_graph_ofuncs }, /* surf2d */
- { 0x0043, &nv04_graph_ofuncs }, /* rop */
- { 0x0044, &nv04_graph_ofuncs }, /* pattern */
- { 0x0048, &nv04_graph_ofuncs, nv03_graph_ttri_omthds },
- { 0x004a, &nv04_graph_ofuncs, nv04_graph_gdi_omthds },
- { 0x004b, &nv04_graph_ofuncs, nv03_graph_gdi_omthds },
- { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */
- { 0x0053, &nv04_graph_ofuncs, nv04_graph_surf3d_omthds },
- { 0x0054, &nv04_graph_ofuncs }, /* ttri */
- { 0x0055, &nv04_graph_ofuncs }, /* mtri */
- { 0x0057, &nv04_graph_ofuncs }, /* chroma */
- { 0x0058, &nv04_graph_ofuncs }, /* surf_dst */
- { 0x0059, &nv04_graph_ofuncs }, /* surf_src */
- { 0x005a, &nv04_graph_ofuncs }, /* surf_color */
- { 0x005b, &nv04_graph_ofuncs }, /* surf_zeta */
- { 0x005c, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* line */
- { 0x005d, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* tri */
- { 0x005e, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* rect */
- { 0x005f, &nv04_graph_ofuncs, nv04_graph_blit_omthds },
- { 0x0060, &nv04_graph_ofuncs, nv04_graph_iifc_omthds },
- { 0x0061, &nv04_graph_ofuncs, nv04_graph_ifc_omthds },
- { 0x0064, &nv04_graph_ofuncs }, /* iifc (nv05) */
- { 0x0065, &nv04_graph_ofuncs }, /* ifc (nv05) */
- { 0x0066, &nv04_graph_ofuncs }, /* sifc (nv05) */
- { 0x0072, &nv04_graph_ofuncs }, /* beta4 */
- { 0x0076, &nv04_graph_ofuncs, nv04_graph_sifc_omthds },
- { 0x0077, &nv04_graph_ofuncs, nv04_graph_sifm_omthds },
+nv04_gr_sclass[] = {
+ { 0x0012, &nv04_gr_ofuncs }, /* beta1 */
+ { 0x0017, &nv04_gr_ofuncs }, /* chroma */
+ { 0x0018, &nv04_gr_ofuncs }, /* pattern (nv01) */
+ { 0x0019, &nv04_gr_ofuncs }, /* clip */
+ { 0x001c, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* line */
+ { 0x001d, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* tri */
+ { 0x001e, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* rect */
+ { 0x001f, &nv04_gr_ofuncs, nv01_gr_blit_omthds },
+ { 0x0021, &nv04_gr_ofuncs, nv01_gr_ifc_omthds },
+ { 0x0030, &nv04_gr_ofuncs }, /* null */
+ { 0x0036, &nv04_gr_ofuncs, nv03_gr_sifc_omthds },
+ { 0x0037, &nv04_gr_ofuncs, nv03_gr_sifm_omthds },
+ { 0x0038, &nv04_gr_ofuncs }, /* dvd subpicture */
+ { 0x0039, &nv04_gr_ofuncs }, /* m2mf */
+ { 0x0042, &nv04_gr_ofuncs }, /* surf2d */
+ { 0x0043, &nv04_gr_ofuncs }, /* rop */
+ { 0x0044, &nv04_gr_ofuncs }, /* pattern */
+ { 0x0048, &nv04_gr_ofuncs, nv03_gr_ttri_omthds },
+ { 0x004a, &nv04_gr_ofuncs, nv04_gr_gdi_omthds },
+ { 0x004b, &nv04_gr_ofuncs, nv03_gr_gdi_omthds },
+ { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */
+ { 0x0053, &nv04_gr_ofuncs, nv04_gr_surf3d_omthds },
+ { 0x0054, &nv04_gr_ofuncs }, /* ttri */
+ { 0x0055, &nv04_gr_ofuncs }, /* mtri */
+ { 0x0057, &nv04_gr_ofuncs }, /* chroma */
+ { 0x0058, &nv04_gr_ofuncs }, /* surf_dst */
+ { 0x0059, &nv04_gr_ofuncs }, /* surf_src */
+ { 0x005a, &nv04_gr_ofuncs }, /* surf_color */
+ { 0x005b, &nv04_gr_ofuncs }, /* surf_zeta */
+ { 0x005c, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* line */
+ { 0x005d, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* tri */
+ { 0x005e, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* rect */
+ { 0x005f, &nv04_gr_ofuncs, nv04_gr_blit_omthds },
+ { 0x0060, &nv04_gr_ofuncs, nv04_gr_iifc_omthds },
+ { 0x0061, &nv04_gr_ofuncs, nv04_gr_ifc_omthds },
+ { 0x0064, &nv04_gr_ofuncs }, /* iifc (nv05) */
+ { 0x0065, &nv04_gr_ofuncs }, /* ifc (nv05) */
+ { 0x0066, &nv04_gr_ofuncs }, /* sifc (nv05) */
+ { 0x0072, &nv04_gr_ofuncs }, /* beta4 */
+ { 0x0076, &nv04_gr_ofuncs, nv04_gr_sifc_omthds },
+ { 0x0077, &nv04_gr_ofuncs, nv04_gr_sifm_omthds },
{},
};
@@ -1037,10 +1037,10 @@ nv04_graph_sclass[] = {
* PGRAPH context
******************************************************************************/
-static struct nv04_graph_chan *
-nv04_graph_channel(struct nv04_graph_priv *priv)
+static struct nv04_gr_chan *
+nv04_gr_channel(struct nv04_gr_priv *priv)
{
- struct nv04_graph_chan *chan = NULL;
+ struct nv04_gr_chan *chan = NULL;
if (nv_rd32(priv, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) {
int chid = nv_rd32(priv, NV04_PGRAPH_CTX_USER) >> 24;
if (chid < ARRAY_SIZE(priv->chan))
@@ -1050,13 +1050,13 @@ nv04_graph_channel(struct nv04_graph_priv *priv)
}
static int
-nv04_graph_load_context(struct nv04_graph_chan *chan, int chid)
+nv04_gr_load_context(struct nv04_gr_chan *chan, int chid)
{
- struct nv04_graph_priv *priv = nv04_graph_priv(chan);
+ struct nv04_gr_priv *priv = nv04_gr_priv(chan);
int i;
- for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
- nv_wr32(priv, nv04_graph_ctx_regs[i], chan->nv04[i]);
+ for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++)
+ nv_wr32(priv, nv04_gr_ctx_regs[i], chan->nv04[i]);
nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24);
@@ -1065,13 +1065,13 @@ nv04_graph_load_context(struct nv04_graph_chan *chan, int chid)
}
static int
-nv04_graph_unload_context(struct nv04_graph_chan *chan)
+nv04_gr_unload_context(struct nv04_gr_chan *chan)
{
- struct nv04_graph_priv *priv = nv04_graph_priv(chan);
+ struct nv04_gr_priv *priv = nv04_gr_priv(chan);
int i;
- for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
- chan->nv04[i] = nv_rd32(priv, nv04_graph_ctx_regs[i]);
+ for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++)
+ chan->nv04[i] = nv_rd32(priv, nv04_gr_ctx_regs[i]);
nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
@@ -1079,36 +1079,36 @@ nv04_graph_unload_context(struct nv04_graph_chan *chan)
}
static void
-nv04_graph_context_switch(struct nv04_graph_priv *priv)
+nv04_gr_context_switch(struct nv04_gr_priv *priv)
{
- struct nv04_graph_chan *prev = NULL;
- struct nv04_graph_chan *next = NULL;
+ struct nv04_gr_chan *prev = NULL;
+ struct nv04_gr_chan *next = NULL;
unsigned long flags;
int chid;
spin_lock_irqsave(&priv->lock, flags);
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
/* If previous context is valid, we need to save it */
- prev = nv04_graph_channel(priv);
+ prev = nv04_gr_channel(priv);
if (prev)
- nv04_graph_unload_context(prev);
+ nv04_gr_unload_context(prev);
/* load context for next channel */
chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f;
next = priv->chan[chid];
if (next)
- nv04_graph_load_context(next, chid);
+ nv04_gr_load_context(next, chid);
spin_unlock_irqrestore(&priv->lock, flags);
}
-static u32 *ctx_reg(struct nv04_graph_chan *chan, u32 reg)
+static u32 *ctx_reg(struct nv04_gr_chan *chan, u32 reg)
{
int i;
- for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) {
- if (nv04_graph_ctx_regs[i] == reg)
+ for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) {
+ if (nv04_gr_ctx_regs[i] == reg)
return &chan->nv04[i];
}
@@ -1116,14 +1116,14 @@ static u32 *ctx_reg(struct nv04_graph_chan *chan, u32 reg)
}
static int
-nv04_graph_context_ctor(struct nouveau_object *parent,
+nv04_gr_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_fifo_chan *fifo = (void *)parent;
- struct nv04_graph_priv *priv = (void *)engine;
- struct nv04_graph_chan *chan;
+ struct nv04_gr_priv *priv = (void *)engine;
+ struct nv04_gr_chan *chan;
unsigned long flags;
int ret;
@@ -1150,10 +1150,10 @@ nv04_graph_context_ctor(struct nouveau_object *parent,
}
static void
-nv04_graph_context_dtor(struct nouveau_object *object)
+nv04_gr_context_dtor(struct nouveau_object *object)
{
- struct nv04_graph_priv *priv = (void *)object->engine;
- struct nv04_graph_chan *chan = (void *)object;
+ struct nv04_gr_priv *priv = (void *)object->engine;
+ struct nv04_gr_chan *chan = (void *)object;
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
@@ -1164,16 +1164,16 @@ nv04_graph_context_dtor(struct nouveau_object *object)
}
static int
-nv04_graph_context_fini(struct nouveau_object *object, bool suspend)
+nv04_gr_context_fini(struct nouveau_object *object, bool suspend)
{
- struct nv04_graph_priv *priv = (void *)object->engine;
- struct nv04_graph_chan *chan = (void *)object;
+ struct nv04_gr_priv *priv = (void *)object->engine;
+ struct nv04_gr_chan *chan = (void *)object;
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
- if (nv04_graph_channel(priv) == chan)
- nv04_graph_unload_context(chan);
+ if (nv04_gr_channel(priv) == chan)
+ nv04_gr_unload_context(chan);
nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&priv->lock, flags);
@@ -1181,13 +1181,13 @@ nv04_graph_context_fini(struct nouveau_object *object, bool suspend)
}
static struct nouveau_oclass
-nv04_graph_cclass = {
+nv04_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv04_graph_context_ctor,
- .dtor = nv04_graph_context_dtor,
+ .ctor = nv04_gr_context_ctor,
+ .dtor = nv04_gr_context_dtor,
.init = nouveau_object_init,
- .fini = nv04_graph_context_fini,
+ .fini = nv04_gr_context_fini,
},
};
@@ -1196,17 +1196,17 @@ nv04_graph_cclass = {
******************************************************************************/
bool
-nv04_graph_idle(void *obj)
+nv04_gr_idle(void *obj)
{
- struct nouveau_graph *graph = nouveau_graph(obj);
+ struct nouveau_gr *gr = nouveau_gr(obj);
u32 mask = 0xffffffff;
if (nv_device(obj)->card_type == NV_40)
mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
- if (!nv_wait(graph, NV04_PGRAPH_STATUS, mask, 0)) {
- nv_error(graph, "idle timed out with status 0x%08x\n",
- nv_rd32(graph, NV04_PGRAPH_STATUS));
+ if (!nv_wait(gr, NV04_PGRAPH_STATUS, mask, 0)) {
+ nv_error(gr, "idle timed out with status 0x%08x\n",
+ nv_rd32(gr, NV04_PGRAPH_STATUS));
return false;
}
@@ -1214,13 +1214,13 @@ nv04_graph_idle(void *obj)
}
static const struct nouveau_bitfield
-nv04_graph_intr_name[] = {
+nv04_gr_intr_name[] = {
{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
{}
};
static const struct nouveau_bitfield
-nv04_graph_nstatus[] = {
+nv04_gr_nstatus[] = {
{ NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
{ NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
{ NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
@@ -1229,7 +1229,7 @@ nv04_graph_nstatus[] = {
};
const struct nouveau_bitfield
-nv04_graph_nsource[] = {
+nv04_gr_nsource[] = {
{ NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
{ NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
{ NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
@@ -1253,10 +1253,10 @@ nv04_graph_nsource[] = {
};
static void
-nv04_graph_intr(struct nouveau_subdev *subdev)
+nv04_gr_intr(struct nouveau_subdev *subdev)
{
- struct nv04_graph_priv *priv = (void *)subdev;
- struct nv04_graph_chan *chan = NULL;
+ struct nv04_gr_priv *priv = (void *)subdev;
+ struct nv04_gr_chan *chan = NULL;
struct nouveau_namedb *namedb = NULL;
struct nouveau_handle *handle = NULL;
u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
@@ -1290,7 +1290,7 @@ nv04_graph_intr(struct nouveau_subdev *subdev)
nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
- nv04_graph_context_switch(priv);
+ nv04_gr_context_switch(priv);
}
nv_wr32(priv, NV03_PGRAPH_INTR, stat);
@@ -1298,11 +1298,11 @@ nv04_graph_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv04_graph_intr_name, show);
+ nouveau_bitfield_print(nv04_gr_intr_name, show);
pr_cont(" nsource:");
- nouveau_bitfield_print(nv04_graph_nsource, nsource);
+ nouveau_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
- nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
+ nouveau_bitfield_print(nv04_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(priv,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
@@ -1314,34 +1314,34 @@ nv04_graph_intr(struct nouveau_subdev *subdev)
}
static int
-nv04_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv04_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv04_graph_priv *priv;
+ struct nv04_gr_priv *priv;
int ret;
- ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+ ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv04_graph_intr;
- nv_engine(priv)->cclass = &nv04_graph_cclass;
- nv_engine(priv)->sclass = nv04_graph_sclass;
+ nv_subdev(priv)->intr = nv04_gr_intr;
+ nv_engine(priv)->cclass = &nv04_gr_cclass;
+ nv_engine(priv)->sclass = nv04_gr_sclass;
spin_lock_init(&priv->lock);
return 0;
}
static int
-nv04_graph_init(struct nouveau_object *object)
+nv04_gr_init(struct nouveau_object *object)
{
struct nouveau_engine *engine = nv_engine(object);
- struct nv04_graph_priv *priv = (void *)engine;
+ struct nv04_gr_priv *priv = (void *)engine;
int ret;
- ret = nouveau_graph_init(&priv->base);
+ ret = nouveau_gr_init(&priv->base);
if (ret)
return ret;
@@ -1377,12 +1377,12 @@ nv04_graph_init(struct nouveau_object *object)
}
struct nouveau_oclass
-nv04_graph_oclass = {
+nv04_gr_oclass = {
.handle = NV_ENGINE(GR, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv04_graph_ctor,
- .dtor = _nouveau_graph_dtor,
- .init = nv04_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nv04_gr_ctor,
+ .dtor = _nouveau_gr_dtor,
+ .init = nv04_gr_init,
+ .fini = _nouveau_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
similarity index 77%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nv10.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
index 2b12b09683c8..9cc5c25f571b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
@@ -10,7 +10,7 @@
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
+ * paragr) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
@@ -29,7 +29,7 @@
#include <subdev/fb.h>
#include <engine/fifo.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include "regs.h"
@@ -46,7 +46,7 @@ struct pipe_state {
u32 pipe_0x7800[0x0c0/4];
};
-static int nv10_graph_ctx_regs[] = {
+static int nv10_gr_ctx_regs[] = {
NV10_PGRAPH_CTX_SWITCH(0),
NV10_PGRAPH_CTX_SWITCH(1),
NV10_PGRAPH_CTX_SWITCH(2),
@@ -368,7 +368,7 @@ static int nv10_graph_ctx_regs[] = {
NV04_PGRAPH_VALID2,
};
-static int nv17_graph_ctx_regs[] = {
+static int nv17_gr_ctx_regs[] = {
NV10_PGRAPH_DEBUG_4,
0x004006b0,
0x00400eac,
@@ -389,24 +389,24 @@ static int nv17_graph_ctx_regs[] = {
0x00400a04,
};
-struct nv10_graph_priv {
- struct nouveau_graph base;
- struct nv10_graph_chan *chan[32];
+struct nv10_gr_priv {
+ struct nouveau_gr base;
+ struct nv10_gr_chan *chan[32];
spinlock_t lock;
};
-struct nv10_graph_chan {
+struct nv10_gr_chan {
struct nouveau_object base;
int chid;
- int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)];
- int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)];
+ int nv10[ARRAY_SIZE(nv10_gr_ctx_regs)];
+ int nv17[ARRAY_SIZE(nv17_gr_ctx_regs)];
struct pipe_state pipe_state;
u32 lma_window[4];
};
-static inline struct nv10_graph_priv *
-nv10_graph_priv(struct nv10_graph_chan *chan)
+static inline struct nv10_gr_priv *
+nv10_gr_priv(struct nv10_gr_chan *chan)
{
return (void *)nv_object(chan)->engine;
}
@@ -432,57 +432,57 @@ nv10_graph_priv(struct nv10_graph_chan *chan)
} while (0)
static struct nouveau_oclass
-nv10_graph_sclass[] = {
- { 0x0012, &nv04_graph_ofuncs }, /* beta1 */
- { 0x0019, &nv04_graph_ofuncs }, /* clip */
- { 0x0030, &nv04_graph_ofuncs }, /* null */
- { 0x0039, &nv04_graph_ofuncs }, /* m2mf */
- { 0x0043, &nv04_graph_ofuncs }, /* rop */
- { 0x0044, &nv04_graph_ofuncs }, /* pattern */
- { 0x004a, &nv04_graph_ofuncs }, /* gdi */
- { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */
- { 0x005f, &nv04_graph_ofuncs }, /* blit */
- { 0x0062, &nv04_graph_ofuncs }, /* surf2d */
- { 0x0072, &nv04_graph_ofuncs }, /* beta4 */
- { 0x0089, &nv04_graph_ofuncs }, /* sifm */
- { 0x008a, &nv04_graph_ofuncs }, /* ifc */
- { 0x009f, &nv04_graph_ofuncs }, /* blit */
- { 0x0093, &nv04_graph_ofuncs }, /* surf3d */
- { 0x0094, &nv04_graph_ofuncs }, /* ttri */
- { 0x0095, &nv04_graph_ofuncs }, /* mtri */
- { 0x0056, &nv04_graph_ofuncs }, /* celcius */
+nv10_gr_sclass[] = {
+ { 0x0012, &nv04_gr_ofuncs }, /* beta1 */
+ { 0x0019, &nv04_gr_ofuncs }, /* clip */
+ { 0x0030, &nv04_gr_ofuncs }, /* null */
+ { 0x0039, &nv04_gr_ofuncs }, /* m2mf */
+ { 0x0043, &nv04_gr_ofuncs }, /* rop */
+ { 0x0044, &nv04_gr_ofuncs }, /* pattern */
+ { 0x004a, &nv04_gr_ofuncs }, /* gdi */
+ { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */
+ { 0x005f, &nv04_gr_ofuncs }, /* blit */
+ { 0x0062, &nv04_gr_ofuncs }, /* surf2d */
+ { 0x0072, &nv04_gr_ofuncs }, /* beta4 */
+ { 0x0089, &nv04_gr_ofuncs }, /* sifm */
+ { 0x008a, &nv04_gr_ofuncs }, /* ifc */
+ { 0x009f, &nv04_gr_ofuncs }, /* blit */
+ { 0x0093, &nv04_gr_ofuncs }, /* surf3d */
+ { 0x0094, &nv04_gr_ofuncs }, /* ttri */
+ { 0x0095, &nv04_gr_ofuncs }, /* mtri */
+ { 0x0056, &nv04_gr_ofuncs }, /* celcius */
{},
};
static struct nouveau_oclass
-nv15_graph_sclass[] = {
- { 0x0012, &nv04_graph_ofuncs }, /* beta1 */
- { 0x0019, &nv04_graph_ofuncs }, /* clip */
- { 0x0030, &nv04_graph_ofuncs }, /* null */
- { 0x0039, &nv04_graph_ofuncs }, /* m2mf */
- { 0x0043, &nv04_graph_ofuncs }, /* rop */
- { 0x0044, &nv04_graph_ofuncs }, /* pattern */
- { 0x004a, &nv04_graph_ofuncs }, /* gdi */
- { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */
- { 0x005f, &nv04_graph_ofuncs }, /* blit */
- { 0x0062, &nv04_graph_ofuncs }, /* surf2d */
- { 0x0072, &nv04_graph_ofuncs }, /* beta4 */
- { 0x0089, &nv04_graph_ofuncs }, /* sifm */
- { 0x008a, &nv04_graph_ofuncs }, /* ifc */
- { 0x009f, &nv04_graph_ofuncs }, /* blit */
- { 0x0093, &nv04_graph_ofuncs }, /* surf3d */
- { 0x0094, &nv04_graph_ofuncs }, /* ttri */
- { 0x0095, &nv04_graph_ofuncs }, /* mtri */
- { 0x0096, &nv04_graph_ofuncs }, /* celcius */
+nv15_gr_sclass[] = {
+ { 0x0012, &nv04_gr_ofuncs }, /* beta1 */
+ { 0x0019, &nv04_gr_ofuncs }, /* clip */
+ { 0x0030, &nv04_gr_ofuncs }, /* null */
+ { 0x0039, &nv04_gr_ofuncs }, /* m2mf */
+ { 0x0043, &nv04_gr_ofuncs }, /* rop */
+ { 0x0044, &nv04_gr_ofuncs }, /* pattern */
+ { 0x004a, &nv04_gr_ofuncs }, /* gdi */
+ { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */
+ { 0x005f, &nv04_gr_ofuncs }, /* blit */
+ { 0x0062, &nv04_gr_ofuncs }, /* surf2d */
+ { 0x0072, &nv04_gr_ofuncs }, /* beta4 */
+ { 0x0089, &nv04_gr_ofuncs }, /* sifm */
+ { 0x008a, &nv04_gr_ofuncs }, /* ifc */
+ { 0x009f, &nv04_gr_ofuncs }, /* blit */
+ { 0x0093, &nv04_gr_ofuncs }, /* surf3d */
+ { 0x0094, &nv04_gr_ofuncs }, /* ttri */
+ { 0x0095, &nv04_gr_ofuncs }, /* mtri */
+ { 0x0096, &nv04_gr_ofuncs }, /* celcius */
{},
};
static int
-nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd,
+nv17_gr_mthd_lma_window(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv10_graph_chan *chan = (void *)object->parent;
- struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+ struct nv10_gr_chan *chan = (void *)object->parent;
+ struct nv10_gr_priv *priv = nv10_gr_priv(chan);
struct pipe_state *pipe = &chan->pipe_state;
u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3];
u32 xfmode0, xfmode1;
@@ -494,14 +494,14 @@ nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd,
if (mthd != 0x1644)
return 0;
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
PIPE_SAVE(priv, pipe_0x0040, 0x0040);
PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200);
PIPE_RESTORE(priv, chan->lma_window, 0x6790);
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0);
xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1);
@@ -511,7 +511,7 @@ nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd,
PIPE_SAVE(priv, pipe_0x6ab0, 0x6ab0);
PIPE_SAVE(priv, pipe_0x6a80, 0x6a80);
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000);
nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000);
@@ -534,7 +534,7 @@ nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd,
PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200);
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
PIPE_RESTORE(priv, pipe_0x0040, 0x0040);
@@ -549,19 +549,19 @@ nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd,
nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0);
nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
return 0;
}
static int
-nv17_graph_mthd_lma_enable(struct nouveau_object *object, u32 mthd,
+nv17_gr_mthd_lma_enable(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv10_graph_chan *chan = (void *)object->parent;
- struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+ struct nv10_gr_chan *chan = (void *)object->parent;
+ struct nv10_gr_priv *priv = nv10_gr_priv(chan);
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
nv_mask(priv, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100);
nv_mask(priv, 0x4006b0, 0x08000000, 0x08000000);
@@ -570,34 +570,34 @@ nv17_graph_mthd_lma_enable(struct nouveau_object *object, u32 mthd,
static struct nouveau_omthds
nv17_celcius_omthds[] = {
- { 0x1638, 0x1638, nv17_graph_mthd_lma_window },
- { 0x163c, 0x163c, nv17_graph_mthd_lma_window },
- { 0x1640, 0x1640, nv17_graph_mthd_lma_window },
- { 0x1644, 0x1644, nv17_graph_mthd_lma_window },
- { 0x1658, 0x1658, nv17_graph_mthd_lma_enable },
+ { 0x1638, 0x1638, nv17_gr_mthd_lma_window },
+ { 0x163c, 0x163c, nv17_gr_mthd_lma_window },
+ { 0x1640, 0x1640, nv17_gr_mthd_lma_window },
+ { 0x1644, 0x1644, nv17_gr_mthd_lma_window },
+ { 0x1658, 0x1658, nv17_gr_mthd_lma_enable },
{}
};
static struct nouveau_oclass
-nv17_graph_sclass[] = {
- { 0x0012, &nv04_graph_ofuncs }, /* beta1 */
- { 0x0019, &nv04_graph_ofuncs }, /* clip */
- { 0x0030, &nv04_graph_ofuncs }, /* null */
- { 0x0039, &nv04_graph_ofuncs }, /* m2mf */
- { 0x0043, &nv04_graph_ofuncs }, /* rop */
- { 0x0044, &nv04_graph_ofuncs }, /* pattern */
- { 0x004a, &nv04_graph_ofuncs }, /* gdi */
- { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */
- { 0x005f, &nv04_graph_ofuncs }, /* blit */
- { 0x0062, &nv04_graph_ofuncs }, /* surf2d */
- { 0x0072, &nv04_graph_ofuncs }, /* beta4 */
- { 0x0089, &nv04_graph_ofuncs }, /* sifm */
- { 0x008a, &nv04_graph_ofuncs }, /* ifc */
- { 0x009f, &nv04_graph_ofuncs }, /* blit */
- { 0x0093, &nv04_graph_ofuncs }, /* surf3d */
- { 0x0094, &nv04_graph_ofuncs }, /* ttri */
- { 0x0095, &nv04_graph_ofuncs }, /* mtri */
- { 0x0099, &nv04_graph_ofuncs, nv17_celcius_omthds },
+nv17_gr_sclass[] = {
+ { 0x0012, &nv04_gr_ofuncs }, /* beta1 */
+ { 0x0019, &nv04_gr_ofuncs }, /* clip */
+ { 0x0030, &nv04_gr_ofuncs }, /* null */
+ { 0x0039, &nv04_gr_ofuncs }, /* m2mf */
+ { 0x0043, &nv04_gr_ofuncs }, /* rop */
+ { 0x0044, &nv04_gr_ofuncs }, /* pattern */
+ { 0x004a, &nv04_gr_ofuncs }, /* gdi */
+ { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */
+ { 0x005f, &nv04_gr_ofuncs }, /* blit */
+ { 0x0062, &nv04_gr_ofuncs }, /* surf2d */
+ { 0x0072, &nv04_gr_ofuncs }, /* beta4 */
+ { 0x0089, &nv04_gr_ofuncs }, /* sifm */
+ { 0x008a, &nv04_gr_ofuncs }, /* ifc */
+ { 0x009f, &nv04_gr_ofuncs }, /* blit */
+ { 0x0093, &nv04_gr_ofuncs }, /* surf3d */
+ { 0x0094, &nv04_gr_ofuncs }, /* ttri */
+ { 0x0095, &nv04_gr_ofuncs }, /* mtri */
+ { 0x0099, &nv04_gr_ofuncs, nv17_celcius_omthds },
{},
};
@@ -605,10 +605,10 @@ nv17_graph_sclass[] = {
* PGRAPH context
******************************************************************************/
-static struct nv10_graph_chan *
-nv10_graph_channel(struct nv10_graph_priv *priv)
+static struct nv10_gr_chan *
+nv10_gr_channel(struct nv10_gr_priv *priv)
{
- struct nv10_graph_chan *chan = NULL;
+ struct nv10_gr_chan *chan = NULL;
if (nv_rd32(priv, 0x400144) & 0x00010000) {
int chid = nv_rd32(priv, 0x400148) >> 24;
if (chid < ARRAY_SIZE(priv->chan))
@@ -618,9 +618,9 @@ nv10_graph_channel(struct nv10_graph_priv *priv)
}
static void
-nv10_graph_save_pipe(struct nv10_graph_chan *chan)
+nv10_gr_save_pipe(struct nv10_gr_chan *chan)
{
- struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+ struct nv10_gr_priv *priv = nv10_gr_priv(chan);
struct pipe_state *pipe = &chan->pipe_state;
PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400);
@@ -636,14 +636,14 @@ nv10_graph_save_pipe(struct nv10_graph_chan *chan)
}
static void
-nv10_graph_load_pipe(struct nv10_graph_chan *chan)
+nv10_gr_load_pipe(struct nv10_gr_chan *chan)
{
- struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+ struct nv10_gr_priv *priv = nv10_gr_priv(chan);
struct pipe_state *pipe = &chan->pipe_state;
u32 xfmode0, xfmode1;
int i;
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
/* XXX check haiku comments */
xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0);
xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1);
@@ -668,7 +668,7 @@ nv10_graph_load_pipe(struct nv10_graph_chan *chan)
PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200);
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
/* restore XFMODE */
nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0);
@@ -682,13 +682,13 @@ nv10_graph_load_pipe(struct nv10_graph_chan *chan)
PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400);
PIPE_RESTORE(priv, pipe->pipe_0x0000, 0x0000);
PIPE_RESTORE(priv, pipe->pipe_0x0040, 0x0040);
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
}
static void
-nv10_graph_create_pipe(struct nv10_graph_chan *chan)
+nv10_gr_create_pipe(struct nv10_gr_chan *chan)
{
- struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+ struct nv10_gr_priv *priv = nv10_gr_priv(chan);
struct pipe_state *pipe_state = &chan->pipe_state;
u32 *pipe_state_addr;
int i;
@@ -841,11 +841,11 @@ nv10_graph_create_pipe(struct nv10_graph_chan *chan)
}
static int
-nv10_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg)
+nv10_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg)
{
int i;
- for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) {
- if (nv10_graph_ctx_regs[i] == reg)
+ for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) {
+ if (nv10_gr_ctx_regs[i] == reg)
return i;
}
nv_error(priv, "unknow offset nv10_ctx_regs %d\n", reg);
@@ -853,11 +853,11 @@ nv10_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg)
}
static int
-nv17_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg)
+nv17_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg)
{
int i;
- for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) {
- if (nv17_graph_ctx_regs[i] == reg)
+ for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) {
+ if (nv17_gr_ctx_regs[i] == reg)
return i;
}
nv_error(priv, "unknow offset nv17_ctx_regs %d\n", reg);
@@ -865,9 +865,9 @@ nv17_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg)
}
static void
-nv10_graph_load_dma_vtxbuf(struct nv10_graph_chan *chan, int chid, u32 inst)
+nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst)
{
- struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+ struct nv10_gr_priv *priv = nv10_gr_priv(chan);
u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4];
u32 ctx_user, ctx_switch[5];
int i, subchan = -1;
@@ -935,25 +935,25 @@ nv10_graph_load_dma_vtxbuf(struct nv10_graph_chan *chan, int chid, u32 inst)
}
static int
-nv10_graph_load_context(struct nv10_graph_chan *chan, int chid)
+nv10_gr_load_context(struct nv10_gr_chan *chan, int chid)
{
- struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+ struct nv10_gr_priv *priv = nv10_gr_priv(chan);
u32 inst;
int i;
- for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
- nv_wr32(priv, nv10_graph_ctx_regs[i], chan->nv10[i]);
+ for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++)
+ nv_wr32(priv, nv10_gr_ctx_regs[i], chan->nv10[i]);
if (nv_device(priv)->card_type >= NV_11 &&
nv_device(priv)->chipset >= 0x17) {
- for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
- nv_wr32(priv, nv17_graph_ctx_regs[i], chan->nv17[i]);
+ for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++)
+ nv_wr32(priv, nv17_gr_ctx_regs[i], chan->nv17[i]);
}
- nv10_graph_load_pipe(chan);
+ nv10_gr_load_pipe(chan);
inst = nv_rd32(priv, NV10_PGRAPH_GLOBALSTATE1) & 0xffff;
- nv10_graph_load_dma_vtxbuf(chan, chid, inst);
+ nv10_gr_load_dma_vtxbuf(chan, chid, inst);
nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24);
@@ -962,21 +962,21 @@ nv10_graph_load_context(struct nv10_graph_chan *chan, int chid)
}
static int
-nv10_graph_unload_context(struct nv10_graph_chan *chan)
+nv10_gr_unload_context(struct nv10_gr_chan *chan)
{
- struct nv10_graph_priv *priv = nv10_graph_priv(chan);
+ struct nv10_gr_priv *priv = nv10_gr_priv(chan);
int i;
- for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
- chan->nv10[i] = nv_rd32(priv, nv10_graph_ctx_regs[i]);
+ for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++)
+ chan->nv10[i] = nv_rd32(priv, nv10_gr_ctx_regs[i]);
if (nv_device(priv)->card_type >= NV_11 &&
nv_device(priv)->chipset >= 0x17) {
- for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
- chan->nv17[i] = nv_rd32(priv, nv17_graph_ctx_regs[i]);
+ for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++)
+ chan->nv17[i] = nv_rd32(priv, nv17_gr_ctx_regs[i]);
}
- nv10_graph_save_pipe(chan);
+ nv10_gr_save_pipe(chan);
nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);
@@ -984,51 +984,51 @@ nv10_graph_unload_context(struct nv10_graph_chan *chan)
}
static void
-nv10_graph_context_switch(struct nv10_graph_priv *priv)
+nv10_gr_context_switch(struct nv10_gr_priv *priv)
{
- struct nv10_graph_chan *prev = NULL;
- struct nv10_graph_chan *next = NULL;
+ struct nv10_gr_chan *prev = NULL;
+ struct nv10_gr_chan *next = NULL;
unsigned long flags;
int chid;
spin_lock_irqsave(&priv->lock, flags);
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
/* If previous context is valid, we need to save it */
- prev = nv10_graph_channel(priv);
+ prev = nv10_gr_channel(priv);
if (prev)
- nv10_graph_unload_context(prev);
+ nv10_gr_unload_context(prev);
/* load context for next channel */
chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
next = priv->chan[chid];
if (next)
- nv10_graph_load_context(next, chid);
+ nv10_gr_load_context(next, chid);
spin_unlock_irqrestore(&priv->lock, flags);
}
#define NV_WRITE_CTX(reg, val) do { \
- int offset = nv10_graph_ctx_regs_find_offset(priv, reg); \
+ int offset = nv10_gr_ctx_regs_find_offset(priv, reg); \
if (offset > 0) \
chan->nv10[offset] = val; \
} while (0)
#define NV17_WRITE_CTX(reg, val) do { \
- int offset = nv17_graph_ctx_regs_find_offset(priv, reg); \
+ int offset = nv17_gr_ctx_regs_find_offset(priv, reg); \
if (offset > 0) \
chan->nv17[offset] = val; \
} while (0)
static int
-nv10_graph_context_ctor(struct nouveau_object *parent,
+nv10_gr_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_fifo_chan *fifo = (void *)parent;
- struct nv10_graph_priv *priv = (void *)engine;
- struct nv10_graph_chan *chan;
+ struct nv10_gr_priv *priv = (void *)engine;
+ struct nv10_gr_chan *chan;
unsigned long flags;
int ret;
@@ -1066,7 +1066,7 @@ nv10_graph_context_ctor(struct nouveau_object *parent,
}
NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->chid << 24);
- nv10_graph_create_pipe(chan);
+ nv10_gr_create_pipe(chan);
priv->chan[fifo->chid] = chan;
chan->chid = fifo->chid;
@@ -1075,10 +1075,10 @@ nv10_graph_context_ctor(struct nouveau_object *parent,
}
static void
-nv10_graph_context_dtor(struct nouveau_object *object)
+nv10_gr_context_dtor(struct nouveau_object *object)
{
- struct nv10_graph_priv *priv = (void *)object->engine;
- struct nv10_graph_chan *chan = (void *)object;
+ struct nv10_gr_priv *priv = (void *)object->engine;
+ struct nv10_gr_chan *chan = (void *)object;
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
@@ -1089,16 +1089,16 @@ nv10_graph_context_dtor(struct nouveau_object *object)
}
static int
-nv10_graph_context_fini(struct nouveau_object *object, bool suspend)
+nv10_gr_context_fini(struct nouveau_object *object, bool suspend)
{
- struct nv10_graph_priv *priv = (void *)object->engine;
- struct nv10_graph_chan *chan = (void *)object;
+ struct nv10_gr_priv *priv = (void *)object->engine;
+ struct nv10_gr_chan *chan = (void *)object;
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
- if (nv10_graph_channel(priv) == chan)
- nv10_graph_unload_context(chan);
+ if (nv10_gr_channel(priv) == chan)
+ nv10_gr_unload_context(chan);
nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&priv->lock, flags);
@@ -1106,13 +1106,13 @@ nv10_graph_context_fini(struct nouveau_object *object, bool suspend)
}
static struct nouveau_oclass
-nv10_graph_cclass = {
+nv10_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x10),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv10_graph_context_ctor,
- .dtor = nv10_graph_context_dtor,
+ .ctor = nv10_gr_context_ctor,
+ .dtor = nv10_gr_context_dtor,
.init = nouveau_object_init,
- .fini = nv10_graph_context_fini,
+ .fini = nv10_gr_context_fini,
},
};
@@ -1121,15 +1121,15 @@ nv10_graph_cclass = {
******************************************************************************/
static void
-nv10_graph_tile_prog(struct nouveau_engine *engine, int i)
+nv10_gr_tile_prog(struct nouveau_engine *engine, int i)
{
struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
struct nouveau_fifo *pfifo = nouveau_fifo(engine);
- struct nv10_graph_priv *priv = (void *)engine;
+ struct nv10_gr_priv *priv = (void *)engine;
unsigned long flags;
pfifo->pause(pfifo, &flags);
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
nv_wr32(priv, NV10_PGRAPH_TLIMIT(i), tile->limit);
nv_wr32(priv, NV10_PGRAPH_TSIZE(i), tile->pitch);
@@ -1138,13 +1138,13 @@ nv10_graph_tile_prog(struct nouveau_engine *engine, int i)
pfifo->start(pfifo, &flags);
}
-const struct nouveau_bitfield nv10_graph_intr_name[] = {
+const struct nouveau_bitfield nv10_gr_intr_name[] = {
{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
{ NV_PGRAPH_INTR_ERROR, "ERROR" },
{}
};
-const struct nouveau_bitfield nv10_graph_nstatus[] = {
+const struct nouveau_bitfield nv10_gr_nstatus[] = {
{ NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
{ NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
{ NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
@@ -1153,10 +1153,10 @@ const struct nouveau_bitfield nv10_graph_nstatus[] = {
};
static void
-nv10_graph_intr(struct nouveau_subdev *subdev)
+nv10_gr_intr(struct nouveau_subdev *subdev)
{
- struct nv10_graph_priv *priv = (void *)subdev;
- struct nv10_graph_chan *chan = NULL;
+ struct nv10_gr_priv *priv = (void *)subdev;
+ struct nv10_gr_chan *chan = NULL;
struct nouveau_namedb *namedb = NULL;
struct nouveau_handle *handle = NULL;
u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
@@ -1189,7 +1189,7 @@ nv10_graph_intr(struct nouveau_subdev *subdev)
nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
- nv10_graph_context_switch(priv);
+ nv10_gr_context_switch(priv);
}
nv_wr32(priv, NV03_PGRAPH_INTR, stat);
@@ -1197,11 +1197,11 @@ nv10_graph_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv10_graph_intr_name, show);
+ nouveau_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
- nouveau_bitfield_print(nv04_graph_nsource, nsource);
+ nouveau_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
- nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
+ nouveau_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(priv,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
@@ -1213,52 +1213,52 @@ nv10_graph_intr(struct nouveau_subdev *subdev)
}
static int
-nv10_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv10_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv10_graph_priv *priv;
+ struct nv10_gr_priv *priv;
int ret;
- ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+ ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv10_graph_intr;
- nv_engine(priv)->cclass = &nv10_graph_cclass;
+ nv_subdev(priv)->intr = nv10_gr_intr;
+ nv_engine(priv)->cclass = &nv10_gr_cclass;
if (nv_device(priv)->chipset <= 0x10)
- nv_engine(priv)->sclass = nv10_graph_sclass;
+ nv_engine(priv)->sclass = nv10_gr_sclass;
else
if (nv_device(priv)->chipset < 0x17 ||
nv_device(priv)->card_type < NV_11)
- nv_engine(priv)->sclass = nv15_graph_sclass;
+ nv_engine(priv)->sclass = nv15_gr_sclass;
else
- nv_engine(priv)->sclass = nv17_graph_sclass;
+ nv_engine(priv)->sclass = nv17_gr_sclass;
- nv_engine(priv)->tile_prog = nv10_graph_tile_prog;
+ nv_engine(priv)->tile_prog = nv10_gr_tile_prog;
spin_lock_init(&priv->lock);
return 0;
}
static void
-nv10_graph_dtor(struct nouveau_object *object)
+nv10_gr_dtor(struct nouveau_object *object)
{
- struct nv10_graph_priv *priv = (void *)object;
- nouveau_graph_destroy(&priv->base);
+ struct nv10_gr_priv *priv = (void *)object;
+ nouveau_gr_destroy(&priv->base);
}
static int
-nv10_graph_init(struct nouveau_object *object)
+nv10_gr_init(struct nouveau_object *object)
{
struct nouveau_engine *engine = nv_engine(object);
struct nouveau_fb *pfb = nouveau_fb(object);
- struct nv10_graph_priv *priv = (void *)engine;
+ struct nv10_gr_priv *priv = (void *)engine;
int ret, i;
- ret = nouveau_graph_init(&priv->base);
+ ret = nouveau_gr_init(&priv->base);
if (ret)
return ret;
@@ -1301,19 +1301,19 @@ nv10_graph_init(struct nouveau_object *object)
}
static int
-nv10_graph_fini(struct nouveau_object *object, bool suspend)
+nv10_gr_fini(struct nouveau_object *object, bool suspend)
{
- struct nv10_graph_priv *priv = (void *)object;
- return nouveau_graph_fini(&priv->base, suspend);
+ struct nv10_gr_priv *priv = (void *)object;
+ return nouveau_gr_fini(&priv->base, suspend);
}
struct nouveau_oclass
-nv10_graph_oclass = {
+nv10_gr_oclass = {
.handle = NV_ENGINE(GR, 0x10),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv10_graph_ctor,
- .dtor = nv10_graph_dtor,
- .init = nv10_graph_init,
- .fini = nv10_graph_fini,
+ .ctor = nv10_gr_ctor,
+ .dtor = nv10_gr_dtor,
+ .init = nv10_gr_init,
+ .fini = nv10_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c
similarity index 71%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nv108.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c
index 2b0e8f48c029..669ee49ba58b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv108.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c
@@ -30,7 +30,7 @@
******************************************************************************/
static struct nouveau_oclass
-nv108_graph_sclass[] = {
+nv108_gr_sclass[] = {
{ 0x902d, &nouveau_object_ofuncs },
{ 0xa140, &nouveau_object_ofuncs },
{ KEPLER_B, &nvc0_fermi_ofuncs },
@@ -42,8 +42,8 @@ nv108_graph_sclass[] = {
* PGRAPH register lists
******************************************************************************/
-static const struct nvc0_graph_init
-nv108_graph_init_main_0[] = {
+static const struct nvc0_gr_init
+nv108_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x0001bfe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
@@ -58,8 +58,8 @@ nv108_graph_init_main_0[] = {
{}
};
-static const struct nvc0_graph_init
-nv108_graph_init_ds_0[] = {
+static const struct nvc0_gr_init
+nv108_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00000000 },
@@ -68,8 +68,8 @@ nv108_graph_init_ds_0[] = {
{}
};
-const struct nvc0_graph_init
-nv108_graph_init_gpc_unk_0[] = {
+const struct nvc0_gr_init
+nv108_gr_init_gpc_unk_0[] = {
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x00000000 },
@@ -77,16 +77,16 @@ nv108_graph_init_gpc_unk_0[] = {
{}
};
-static const struct nvc0_graph_init
-nv108_graph_init_setup_1[] = {
+static const struct nvc0_gr_init
+nv108_gr_init_setup_1[] = {
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
{ 0x4188d4, 1, 0x04, 0x00000201 },
{}
};
-static const struct nvc0_graph_init
-nv108_graph_init_tex_0[] = {
+static const struct nvc0_gr_init
+nv108_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -96,8 +96,8 @@ nv108_graph_init_tex_0[] = {
{}
};
-static const struct nvc0_graph_init
-nv108_graph_init_l1c_0[] = {
+static const struct nvc0_gr_init
+nv108_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
@@ -111,37 +111,37 @@ nv108_graph_init_l1c_0[] = {
{}
};
-static const struct nvc0_graph_pack
-nv108_graph_pack_mmio[] = {
- { nv108_graph_init_main_0 },
- { nvf0_graph_init_fe_0 },
- { nvc0_graph_init_pri_0 },
- { nvc0_graph_init_rstr2d_0 },
- { nvd9_graph_init_pd_0 },
- { nv108_graph_init_ds_0 },
- { nvc0_graph_init_scc_0 },
- { nvf0_graph_init_sked_0 },
- { nvf0_graph_init_cwd_0 },
- { nvd9_graph_init_prop_0 },
- { nv108_graph_init_gpc_unk_0 },
- { nvc0_graph_init_setup_0 },
- { nvc0_graph_init_crstr_0 },
- { nv108_graph_init_setup_1 },
- { nvc0_graph_init_zcull_0 },
- { nvd9_graph_init_gpm_0 },
- { nvf0_graph_init_gpc_unk_1 },
- { nvc0_graph_init_gcc_0 },
- { nve4_graph_init_tpccs_0 },
- { nv108_graph_init_tex_0 },
- { nve4_graph_init_pe_0 },
- { nv108_graph_init_l1c_0 },
- { nvc0_graph_init_mpc_0 },
- { nvf0_graph_init_sm_0 },
- { nvd7_graph_init_pes_0 },
- { nvd7_graph_init_wwdx_0 },
- { nvd7_graph_init_cbm_0 },
- { nve4_graph_init_be_0 },
- { nvc0_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+nv108_gr_pack_mmio[] = {
+ { nv108_gr_init_main_0 },
+ { nvf0_gr_init_fe_0 },
+ { nvc0_gr_init_pri_0 },
+ { nvc0_gr_init_rstr2d_0 },
+ { nvd9_gr_init_pd_0 },
+ { nv108_gr_init_ds_0 },
+ { nvc0_gr_init_scc_0 },
+ { nvf0_gr_init_sked_0 },
+ { nvf0_gr_init_cwd_0 },
+ { nvd9_gr_init_prop_0 },
+ { nv108_gr_init_gpc_unk_0 },
+ { nvc0_gr_init_setup_0 },
+ { nvc0_gr_init_crstr_0 },
+ { nv108_gr_init_setup_1 },
+ { nvc0_gr_init_zcull_0 },
+ { nvd9_gr_init_gpm_0 },
+ { nvf0_gr_init_gpc_unk_1 },
+ { nvc0_gr_init_gcc_0 },
+ { nve4_gr_init_tpccs_0 },
+ { nv108_gr_init_tex_0 },
+ { nve4_gr_init_pe_0 },
+ { nv108_gr_init_l1c_0 },
+ { nvc0_gr_init_mpc_0 },
+ { nvf0_gr_init_sm_0 },
+ { nvd7_gr_init_pes_0 },
+ { nvd7_gr_init_wwdx_0 },
+ { nvd7_gr_init_cbm_0 },
+ { nve4_gr_init_be_0 },
+ { nvc0_gr_init_fe_1 },
{}
};
@@ -150,9 +150,9 @@ nv108_graph_pack_mmio[] = {
******************************************************************************/
static int
-nv108_graph_fini(struct nouveau_object *object, bool suspend)
+nv108_gr_fini(struct nouveau_object *object, bool suspend)
{
- struct nvc0_graph_priv *priv = (void *)object;
+ struct nvc0_gr_priv *priv = (void *)object;
static const struct {
u32 addr;
u32 data;
@@ -183,13 +183,13 @@ nv108_graph_fini(struct nouveau_object *object, bool suspend)
nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
}
- return nouveau_graph_fini(&priv->base, suspend);
+ return nouveau_gr_fini(&priv->base, suspend);
}
#include "fuc/hubnv108.fuc5.h"
-static struct nvc0_graph_ucode
-nv108_graph_fecs_ucode = {
+static struct nvc0_gr_ucode
+nv108_gr_fecs_ucode = {
.code.data = nv108_grhub_code,
.code.size = sizeof(nv108_grhub_code),
.data.data = nv108_grhub_data,
@@ -198,8 +198,8 @@ nv108_graph_fecs_ucode = {
#include "fuc/gpcnv108.fuc5.h"
-static struct nvc0_graph_ucode
-nv108_graph_gpccs_ucode = {
+static struct nvc0_gr_ucode
+nv108_gr_gpccs_ucode = {
.code.data = nv108_grgpc_code,
.code.size = sizeof(nv108_grgpc_code),
.data.data = nv108_grgpc_data,
@@ -207,18 +207,18 @@ nv108_graph_gpccs_ucode = {
};
struct nouveau_oclass *
-nv108_graph_oclass = &(struct nvc0_graph_oclass) {
+nv108_gr_oclass = &(struct nvc0_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0x08),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_ctor,
- .dtor = nvc0_graph_dtor,
- .init = nve4_graph_init,
- .fini = nv108_graph_fini,
+ .ctor = nvc0_gr_ctor,
+ .dtor = nvc0_gr_dtor,
+ .init = nve4_gr_init,
+ .fini = nv108_gr_fini,
},
.cclass = &nv108_grctx_oclass,
- .sclass = nv108_graph_sclass,
- .mmio = nv108_graph_pack_mmio,
- .fecs.ucode = &nv108_graph_fecs_ucode,
- .gpccs.ucode = &nv108_graph_gpccs_ucode,
+ .sclass = nv108_gr_sclass,
+ .mmio = nv108_gr_pack_mmio,
+ .fecs.ucode = &nv108_gr_fecs_ucode,
+ .gpccs.ucode = &nv108_gr_gpccs_ucode,
.ppc_nr = 1,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
similarity index 77%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
index ceb9c746d94e..8caf0c338425 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
@@ -7,7 +7,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include <engine/fifo.h>
#include "nv20.h"
@@ -18,22 +18,22 @@
******************************************************************************/
static struct nouveau_oclass
-nv20_graph_sclass[] = {
- { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
- { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
- { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
- { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
- { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
- { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
- { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
- { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
- { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
- { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
- { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
- { 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */
- { 0x0097, &nv04_graph_ofuncs, NULL }, /* kelvin */
- { 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */
- { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
+nv20_gr_sclass[] = {
+ { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
+ { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
+ { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
+ { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
+ { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
+ { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
+ { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
+ { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
+ { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
+ { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
+ { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
+ { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
+ { 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */
+ { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
+ { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
{},
};
@@ -42,15 +42,15 @@ nv20_graph_sclass[] = {
******************************************************************************/
static int
-nv20_graph_context_ctor(struct nouveau_object *parent,
+nv20_gr_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv20_graph_chan *chan;
+ struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
+ ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC,
&chan);
*pobject = nv_object(chan);
@@ -107,13 +107,13 @@ nv20_graph_context_ctor(struct nouveau_object *parent,
}
int
-nv20_graph_context_init(struct nouveau_object *object)
+nv20_gr_context_init(struct nouveau_object *object)
{
- struct nv20_graph_priv *priv = (void *)object->engine;
- struct nv20_graph_chan *chan = (void *)object;
+ struct nv20_gr_priv *priv = (void *)object->engine;
+ struct nv20_gr_chan *chan = (void *)object;
int ret;
- ret = nouveau_graph_context_init(&chan->base);
+ ret = nouveau_gr_context_init(&chan->base);
if (ret)
return ret;
@@ -122,10 +122,10 @@ nv20_graph_context_init(struct nouveau_object *object)
}
int
-nv20_graph_context_fini(struct nouveau_object *object, bool suspend)
+nv20_gr_context_fini(struct nouveau_object *object, bool suspend)
{
- struct nv20_graph_priv *priv = (void *)object->engine;
- struct nv20_graph_chan *chan = (void *)object;
+ struct nv20_gr_priv *priv = (void *)object->engine;
+ struct nv20_gr_chan *chan = (void *)object;
int chid = -1;
nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
@@ -141,19 +141,19 @@ nv20_graph_context_fini(struct nouveau_object *object, bool suspend)
nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
- return nouveau_graph_context_fini(&chan->base, suspend);
+ return nouveau_gr_context_fini(&chan->base, suspend);
}
static struct nouveau_oclass
-nv20_graph_cclass = {
+nv20_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x20),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv20_graph_context_ctor,
- .dtor = _nouveau_graph_context_dtor,
- .init = nv20_graph_context_init,
- .fini = nv20_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nv20_gr_context_ctor,
+ .dtor = _nouveau_gr_context_dtor,
+ .init = nv20_gr_context_init,
+ .fini = nv20_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
};
@@ -162,15 +162,15 @@ nv20_graph_cclass = {
******************************************************************************/
void
-nv20_graph_tile_prog(struct nouveau_engine *engine, int i)
+nv20_gr_tile_prog(struct nouveau_engine *engine, int i)
{
struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
struct nouveau_fifo *pfifo = nouveau_fifo(engine);
- struct nv20_graph_priv *priv = (void *)engine;
+ struct nv20_gr_priv *priv = (void *)engine;
unsigned long flags;
pfifo->pause(pfifo, &flags);
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
@@ -193,12 +193,12 @@ nv20_graph_tile_prog(struct nouveau_engine *engine, int i)
}
void
-nv20_graph_intr(struct nouveau_subdev *subdev)
+nv20_gr_intr(struct nouveau_subdev *subdev)
{
struct nouveau_engine *engine = nv_engine(subdev);
struct nouveau_object *engctx;
struct nouveau_handle *handle;
- struct nv20_graph_priv *priv = (void *)subdev;
+ struct nv20_gr_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
@@ -225,11 +225,11 @@ nv20_graph_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv10_graph_intr_name, show);
+ nouveau_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
- nouveau_bitfield_print(nv04_graph_nsource, nsource);
+ nouveau_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
- nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
+ nouveau_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(priv,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
@@ -241,14 +241,14 @@ nv20_graph_intr(struct nouveau_subdev *subdev)
}
static int
-nv20_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv20_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv20_graph_priv *priv;
+ struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+ ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -259,31 +259,31 @@ nv20_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv20_graph_intr;
- nv_engine(priv)->cclass = &nv20_graph_cclass;
- nv_engine(priv)->sclass = nv20_graph_sclass;
- nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
+ nv_subdev(priv)->intr = nv20_gr_intr;
+ nv_engine(priv)->cclass = &nv20_gr_cclass;
+ nv_engine(priv)->sclass = nv20_gr_sclass;
+ nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
return 0;
}
void
-nv20_graph_dtor(struct nouveau_object *object)
+nv20_gr_dtor(struct nouveau_object *object)
{
- struct nv20_graph_priv *priv = (void *)object;
+ struct nv20_gr_priv *priv = (void *)object;
nouveau_gpuobj_ref(NULL, &priv->ctxtab);
- nouveau_graph_destroy(&priv->base);
+ nouveau_gr_destroy(&priv->base);
}
int
-nv20_graph_init(struct nouveau_object *object)
+nv20_gr_init(struct nouveau_object *object)
{
struct nouveau_engine *engine = nv_engine(object);
- struct nv20_graph_priv *priv = (void *)engine;
+ struct nv20_gr_priv *priv = (void *)engine;
struct nouveau_fb *pfb = nouveau_fb(object);
u32 tmp, vramsz;
int ret, i;
- ret = nouveau_graph_init(&priv->base);
+ ret = nouveau_gr_init(&priv->base);
if (ret)
return ret;
@@ -372,12 +372,12 @@ nv20_graph_init(struct nouveau_object *object)
}
struct nouveau_oclass
-nv20_graph_oclass = {
+nv20_gr_oclass = {
.handle = NV_ENGINE(GR, 0x20),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv20_graph_ctor,
- .dtor = nv20_graph_dtor,
- .init = nv20_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nv20_gr_ctor,
+ .dtor = nv20_gr_dtor,
+ .init = nv20_gr_init,
+ .fini = _nouveau_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
new file mode 100644
index 000000000000..9019eea4a613
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
@@ -0,0 +1,31 @@
+#ifndef __NV20_GR_H__
+#define __NV20_GR_H__
+
+#include <core/enum.h>
+
+#include <engine/gr.h>
+#include <engine/fifo.h>
+
+struct nv20_gr_priv {
+ struct nouveau_gr base;
+ struct nouveau_gpuobj *ctxtab;
+};
+
+struct nv20_gr_chan {
+ struct nouveau_gr_chan base;
+ int chid;
+};
+
+extern struct nouveau_oclass nv25_gr_sclass[];
+int nv20_gr_context_init(struct nouveau_object *);
+int nv20_gr_context_fini(struct nouveau_object *, bool);
+
+void nv20_gr_tile_prog(struct nouveau_engine *, int);
+void nv20_gr_intr(struct nouveau_subdev *);
+
+void nv20_gr_dtor(struct nouveau_object *);
+int nv20_gr_init(struct nouveau_object *);
+
+int nv30_gr_init(struct nouveau_object *);
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
similarity index 67%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nv25.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
index f8a6fdd7d5e8..903a2ec361ce 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv25.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
@@ -5,7 +5,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include "nv20.h"
#include "regs.h"
@@ -15,22 +15,22 @@
******************************************************************************/
struct nouveau_oclass
-nv25_graph_sclass[] = {
- { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
- { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
- { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
- { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
- { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
- { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
- { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
- { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
- { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
- { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
- { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
- { 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */
- { 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */
- { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
- { 0x0597, &nv04_graph_ofuncs, NULL }, /* kelvin */
+nv25_gr_sclass[] = {
+ { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
+ { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
+ { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
+ { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
+ { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
+ { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
+ { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
+ { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
+ { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
+ { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
+ { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
+ { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
+ { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
+ { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
+ { 0x0597, &nv04_gr_ofuncs, NULL }, /* kelvin */
{},
};
@@ -39,15 +39,15 @@ nv25_graph_sclass[] = {
******************************************************************************/
static int
-nv25_graph_context_ctor(struct nouveau_object *parent,
+nv25_gr_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv20_graph_chan *chan;
+ struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x3724,
+ ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x3724,
16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
@@ -112,15 +112,15 @@ nv25_graph_context_ctor(struct nouveau_object *parent,
}
static struct nouveau_oclass
-nv25_graph_cclass = {
+nv25_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x25),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv25_graph_context_ctor,
- .dtor = _nouveau_graph_context_dtor,
- .init = nv20_graph_context_init,
- .fini = nv20_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nv25_gr_context_ctor,
+ .dtor = _nouveau_gr_context_dtor,
+ .init = nv20_gr_context_init,
+ .fini = nv20_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
};
@@ -129,14 +129,14 @@ nv25_graph_cclass = {
******************************************************************************/
static int
-nv25_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv25_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv20_graph_priv *priv;
+ struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+ ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -147,20 +147,20 @@ nv25_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv20_graph_intr;
- nv_engine(priv)->cclass = &nv25_graph_cclass;
- nv_engine(priv)->sclass = nv25_graph_sclass;
- nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
+ nv_subdev(priv)->intr = nv20_gr_intr;
+ nv_engine(priv)->cclass = &nv25_gr_cclass;
+ nv_engine(priv)->sclass = nv25_gr_sclass;
+ nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
return 0;
}
struct nouveau_oclass
-nv25_graph_oclass = {
+nv25_gr_oclass = {
.handle = NV_ENGINE(GR, 0x25),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv25_graph_ctor,
- .dtor = nv20_graph_dtor,
- .init = nv20_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nv25_gr_ctor,
+ .dtor = nv20_gr_dtor,
+ .init = nv20_gr_init,
+ .fini = _nouveau_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
similarity index 76%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nv2a.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
index 5de9caa2ef67..e31f6c766729 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv2a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
@@ -5,7 +5,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include "nv20.h"
#include "regs.h"
@@ -15,15 +15,15 @@
******************************************************************************/
static int
-nv2a_graph_context_ctor(struct nouveau_object *parent,
+nv2a_gr_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv20_graph_chan *chan;
+ struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x36b0,
+ ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x36b0,
16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
@@ -79,15 +79,15 @@ nv2a_graph_context_ctor(struct nouveau_object *parent,
}
static struct nouveau_oclass
-nv2a_graph_cclass = {
+nv2a_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x2a),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv2a_graph_context_ctor,
- .dtor = _nouveau_graph_context_dtor,
- .init = nv20_graph_context_init,
- .fini = nv20_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nv2a_gr_context_ctor,
+ .dtor = _nouveau_gr_context_dtor,
+ .init = nv20_gr_context_init,
+ .fini = nv20_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
};
@@ -96,14 +96,14 @@ nv2a_graph_cclass = {
******************************************************************************/
static int
-nv2a_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv2a_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv20_graph_priv *priv;
+ struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+ ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -114,20 +114,20 @@ nv2a_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv20_graph_intr;
- nv_engine(priv)->cclass = &nv2a_graph_cclass;
- nv_engine(priv)->sclass = nv25_graph_sclass;
- nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
+ nv_subdev(priv)->intr = nv20_gr_intr;
+ nv_engine(priv)->cclass = &nv2a_gr_cclass;
+ nv_engine(priv)->sclass = nv25_gr_sclass;
+ nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
return 0;
}
struct nouveau_oclass
-nv2a_graph_oclass = {
+nv2a_gr_oclass = {
.handle = NV_ENGINE(GR, 0x2a),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv2a_graph_ctor,
- .dtor = nv20_graph_dtor,
- .init = nv20_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nv2a_gr_ctor,
+ .dtor = nv20_gr_dtor,
+ .init = nv20_gr_init,
+ .fini = _nouveau_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
similarity index 74%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nv30.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
index 2f9dbc709389..d9d85508cbcf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
@@ -5,7 +5,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include "nv20.h"
#include "regs.h"
@@ -15,24 +15,24 @@
******************************************************************************/
static struct nouveau_oclass
-nv30_graph_sclass[] = {
- { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
- { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
- { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
- { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
- { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
- { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
- { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
- { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
- { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
- { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
- { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
- { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
- { 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */
- { 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */
- { 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */
- { 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */
- { 0x0397, &nv04_graph_ofuncs, NULL }, /* rankine */
+nv30_gr_sclass[] = {
+ { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
+ { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
+ { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
+ { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
+ { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
+ { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
+ { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
+ { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
+ { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
+ { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
+ { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
+ { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
+ { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */
+ { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */
+ { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */
+ { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */
+ { 0x0397, &nv04_gr_ofuncs, NULL }, /* rankine */
{},
};
@@ -41,15 +41,15 @@ nv30_graph_sclass[] = {
******************************************************************************/
static int
-nv30_graph_context_ctor(struct nouveau_object *parent,
+nv30_gr_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv20_graph_chan *chan;
+ struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x5f48,
+ ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x5f48,
16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
@@ -113,15 +113,15 @@ nv30_graph_context_ctor(struct nouveau_object *parent,
}
static struct nouveau_oclass
-nv30_graph_cclass = {
+nv30_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x30),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv30_graph_context_ctor,
- .dtor = _nouveau_graph_context_dtor,
- .init = nv20_graph_context_init,
- .fini = nv20_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nv30_gr_context_ctor,
+ .dtor = _nouveau_gr_context_dtor,
+ .init = nv20_gr_context_init,
+ .fini = nv20_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
};
@@ -130,14 +130,14 @@ nv30_graph_cclass = {
******************************************************************************/
static int
-nv30_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv30_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv20_graph_priv *priv;
+ struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+ ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -148,22 +148,22 @@ nv30_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv20_graph_intr;
- nv_engine(priv)->cclass = &nv30_graph_cclass;
- nv_engine(priv)->sclass = nv30_graph_sclass;
- nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
+ nv_subdev(priv)->intr = nv20_gr_intr;
+ nv_engine(priv)->cclass = &nv30_gr_cclass;
+ nv_engine(priv)->sclass = nv30_gr_sclass;
+ nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
return 0;
}
int
-nv30_graph_init(struct nouveau_object *object)
+nv30_gr_init(struct nouveau_object *object)
{
struct nouveau_engine *engine = nv_engine(object);
- struct nv20_graph_priv *priv = (void *)engine;
+ struct nv20_gr_priv *priv = (void *)engine;
struct nouveau_fb *pfb = nouveau_fb(object);
int ret, i;
- ret = nouveau_graph_init(&priv->base);
+ ret = nouveau_gr_init(&priv->base);
if (ret)
return ret;
@@ -226,12 +226,12 @@ nv30_graph_init(struct nouveau_object *object)
}
struct nouveau_oclass
-nv30_graph_oclass = {
+nv30_gr_oclass = {
.handle = NV_ENGINE(GR, 0x30),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv30_graph_ctor,
- .dtor = nv20_graph_dtor,
- .init = nv30_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nv30_gr_ctor,
+ .dtor = nv20_gr_dtor,
+ .init = nv30_gr_init,
+ .fini = _nouveau_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
similarity index 65%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nv34.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
index 34dd26c70b64..5c2787056292 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv34.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
@@ -5,7 +5,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include "nv20.h"
#include "regs.h"
@@ -15,24 +15,24 @@
******************************************************************************/
static struct nouveau_oclass
-nv34_graph_sclass[] = {
- { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
- { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
- { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
- { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
- { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
- { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
- { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
- { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
- { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
- { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
- { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
- { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
- { 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */
- { 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */
- { 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */
- { 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */
- { 0x0697, &nv04_graph_ofuncs, NULL }, /* rankine */
+nv34_gr_sclass[] = {
+ { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
+ { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
+ { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
+ { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
+ { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
+ { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
+ { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
+ { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
+ { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
+ { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
+ { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
+ { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
+ { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */
+ { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */
+ { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */
+ { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */
+ { 0x0697, &nv04_gr_ofuncs, NULL }, /* rankine */
{},
};
@@ -41,15 +41,15 @@ nv34_graph_sclass[] = {
******************************************************************************/
static int
-nv34_graph_context_ctor(struct nouveau_object *parent,
+nv34_gr_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv20_graph_chan *chan;
+ struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x46dc,
+ ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x46dc,
16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
@@ -113,15 +113,15 @@ nv34_graph_context_ctor(struct nouveau_object *parent,
}
static struct nouveau_oclass
-nv34_graph_cclass = {
+nv34_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x34),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv34_graph_context_ctor,
- .dtor = _nouveau_graph_context_dtor,
- .init = nv20_graph_context_init,
- .fini = nv20_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nv34_gr_context_ctor,
+ .dtor = _nouveau_gr_context_dtor,
+ .init = nv20_gr_context_init,
+ .fini = nv20_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
};
@@ -130,14 +130,14 @@ nv34_graph_cclass = {
******************************************************************************/
static int
-nv34_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv34_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv20_graph_priv *priv;
+ struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+ ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -148,20 +148,20 @@ nv34_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv20_graph_intr;
- nv_engine(priv)->cclass = &nv34_graph_cclass;
- nv_engine(priv)->sclass = nv34_graph_sclass;
- nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
+ nv_subdev(priv)->intr = nv20_gr_intr;
+ nv_engine(priv)->cclass = &nv34_gr_cclass;
+ nv_engine(priv)->sclass = nv34_gr_sclass;
+ nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
return 0;
}
struct nouveau_oclass
-nv34_graph_oclass = {
+nv34_gr_oclass = {
.handle = NV_ENGINE(GR, 0x34),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv34_graph_ctor,
- .dtor = nv20_graph_dtor,
- .init = nv30_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nv34_gr_ctor,
+ .dtor = nv20_gr_dtor,
+ .init = nv30_gr_init,
+ .fini = _nouveau_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
similarity index 65%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nv35.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
index 2fb5756d9f66..af3f914813e2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv35.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
@@ -13,24 +13,24 @@
******************************************************************************/
static struct nouveau_oclass
-nv35_graph_sclass[] = {
- { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
- { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
- { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
- { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
- { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
- { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
- { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
- { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
- { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
- { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
- { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
- { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
- { 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */
- { 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */
- { 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */
- { 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */
- { 0x0497, &nv04_graph_ofuncs, NULL }, /* rankine */
+nv35_gr_sclass[] = {
+ { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
+ { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
+ { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
+ { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
+ { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
+ { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
+ { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
+ { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
+ { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
+ { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
+ { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
+ { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
+ { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */
+ { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */
+ { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */
+ { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */
+ { 0x0497, &nv04_gr_ofuncs, NULL }, /* rankine */
{},
};
@@ -39,15 +39,15 @@ nv35_graph_sclass[] = {
******************************************************************************/
static int
-nv35_graph_context_ctor(struct nouveau_object *parent,
+nv35_gr_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv20_graph_chan *chan;
+ struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x577c,
+ ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x577c,
16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
@@ -111,15 +111,15 @@ nv35_graph_context_ctor(struct nouveau_object *parent,
}
static struct nouveau_oclass
-nv35_graph_cclass = {
+nv35_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x35),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv35_graph_context_ctor,
- .dtor = _nouveau_graph_context_dtor,
- .init = nv20_graph_context_init,
- .fini = nv20_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nv35_gr_context_ctor,
+ .dtor = _nouveau_gr_context_dtor,
+ .init = nv20_gr_context_init,
+ .fini = nv20_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
};
@@ -128,14 +128,14 @@ nv35_graph_cclass = {
******************************************************************************/
static int
-nv35_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv35_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv20_graph_priv *priv;
+ struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+ ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -146,20 +146,20 @@ nv35_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv20_graph_intr;
- nv_engine(priv)->cclass = &nv35_graph_cclass;
- nv_engine(priv)->sclass = nv35_graph_sclass;
- nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
+ nv_subdev(priv)->intr = nv20_gr_intr;
+ nv_engine(priv)->cclass = &nv35_gr_cclass;
+ nv_engine(priv)->sclass = nv35_gr_sclass;
+ nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
return 0;
}
struct nouveau_oclass
-nv35_graph_oclass = {
+nv35_gr_oclass = {
.handle = NV_ENGINE(GR, 0x35),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv35_graph_ctor,
- .dtor = nv20_graph_dtor,
- .init = nv30_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nv35_gr_ctor,
+ .dtor = nv20_gr_dtor,
+ .init = nv30_gr_init,
+ .fini = _nouveau_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
similarity index 75%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
index 4f401174868d..6fadd830bc25 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
@@ -30,25 +30,25 @@
#include <subdev/fb.h>
#include <subdev/timer.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include <engine/fifo.h>
#include "nv40.h"
#include "regs.h"
-struct nv40_graph_priv {
- struct nouveau_graph base;
+struct nv40_gr_priv {
+ struct nouveau_gr base;
u32 size;
};
-struct nv40_graph_chan {
- struct nouveau_graph_chan base;
+struct nv40_gr_chan {
+ struct nouveau_gr_chan base;
};
static u64
-nv40_graph_units(struct nouveau_graph *graph)
+nv40_gr_units(struct nouveau_gr *gr)
{
- struct nv40_graph_priv *priv = (void *)graph;
+ struct nv40_gr_priv *priv = (void *)gr;
return nv_rd32(priv, 0x1540);
}
@@ -58,7 +58,7 @@ nv40_graph_units(struct nouveau_graph *graph)
******************************************************************************/
static int
-nv40_graph_object_ctor(struct nouveau_object *parent,
+nv40_gr_object_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
@@ -84,8 +84,8 @@ nv40_graph_object_ctor(struct nouveau_object *parent,
}
static struct nouveau_ofuncs
-nv40_graph_ofuncs = {
- .ctor = nv40_graph_object_ctor,
+nv40_gr_ofuncs = {
+ .ctor = nv40_gr_object_ctor,
.dtor = _nouveau_gpuobj_dtor,
.init = _nouveau_gpuobj_init,
.fini = _nouveau_gpuobj_fini,
@@ -94,44 +94,44 @@ nv40_graph_ofuncs = {
};
static struct nouveau_oclass
-nv40_graph_sclass[] = {
- { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
- { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
- { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
- { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
- { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
- { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
- { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
- { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
- { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
- { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
- { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
- { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
- { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
- { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
- { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
- { 0x4097, &nv40_graph_ofuncs, NULL }, /* curie */
+nv40_gr_sclass[] = {
+ { 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */
+ { 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */
+ { 0x0030, &nv40_gr_ofuncs, NULL }, /* null */
+ { 0x0039, &nv40_gr_ofuncs, NULL }, /* m2mf */
+ { 0x0043, &nv40_gr_ofuncs, NULL }, /* rop */
+ { 0x0044, &nv40_gr_ofuncs, NULL }, /* patt */
+ { 0x004a, &nv40_gr_ofuncs, NULL }, /* gdi */
+ { 0x0062, &nv40_gr_ofuncs, NULL }, /* surf2d */
+ { 0x0072, &nv40_gr_ofuncs, NULL }, /* beta4 */
+ { 0x0089, &nv40_gr_ofuncs, NULL }, /* sifm */
+ { 0x008a, &nv40_gr_ofuncs, NULL }, /* ifc */
+ { 0x009f, &nv40_gr_ofuncs, NULL }, /* imageblit */
+ { 0x3062, &nv40_gr_ofuncs, NULL }, /* surf2d (nv40) */
+ { 0x3089, &nv40_gr_ofuncs, NULL }, /* sifm (nv40) */
+ { 0x309e, &nv40_gr_ofuncs, NULL }, /* swzsurf (nv40) */
+ { 0x4097, &nv40_gr_ofuncs, NULL }, /* curie */
{},
};
static struct nouveau_oclass
-nv44_graph_sclass[] = {
- { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
- { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
- { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
- { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
- { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
- { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
- { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
- { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
- { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
- { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
- { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
- { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
- { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
- { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
- { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
- { 0x4497, &nv40_graph_ofuncs, NULL }, /* curie */
+nv44_gr_sclass[] = {
+ { 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */
+ { 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */
+ { 0x0030, &nv40_gr_ofuncs, NULL }, /* null */
+ { 0x0039, &nv40_gr_ofuncs, NULL }, /* m2mf */
+ { 0x0043, &nv40_gr_ofuncs, NULL }, /* rop */
+ { 0x0044, &nv40_gr_ofuncs, NULL }, /* patt */
+ { 0x004a, &nv40_gr_ofuncs, NULL }, /* gdi */
+ { 0x0062, &nv40_gr_ofuncs, NULL }, /* surf2d */
+ { 0x0072, &nv40_gr_ofuncs, NULL }, /* beta4 */
+ { 0x0089, &nv40_gr_ofuncs, NULL }, /* sifm */
+ { 0x008a, &nv40_gr_ofuncs, NULL }, /* ifc */
+ { 0x009f, &nv40_gr_ofuncs, NULL }, /* imageblit */
+ { 0x3062, &nv40_gr_ofuncs, NULL }, /* surf2d (nv40) */
+ { 0x3089, &nv40_gr_ofuncs, NULL }, /* sifm (nv40) */
+ { 0x309e, &nv40_gr_ofuncs, NULL }, /* swzsurf (nv40) */
+ { 0x4497, &nv40_gr_ofuncs, NULL }, /* curie */
{},
};
@@ -140,16 +140,16 @@ nv44_graph_sclass[] = {
******************************************************************************/
static int
-nv40_graph_context_ctor(struct nouveau_object *parent,
+nv40_gr_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv40_graph_priv *priv = (void *)engine;
- struct nv40_graph_chan *chan;
+ struct nv40_gr_priv *priv = (void *)engine;
+ struct nv40_gr_chan *chan;
int ret;
- ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
+ ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
priv->size, 16,
NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
@@ -162,10 +162,10 @@ nv40_graph_context_ctor(struct nouveau_object *parent,
}
static int
-nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
+nv40_gr_context_fini(struct nouveau_object *object, bool suspend)
{
- struct nv40_graph_priv *priv = (void *)object->engine;
- struct nv40_graph_chan *chan = (void *)object;
+ struct nv40_gr_priv *priv = (void *)object->engine;
+ struct nv40_gr_chan *chan = (void *)object;
u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
int ret = 0;
@@ -195,15 +195,15 @@ nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
}
static struct nouveau_oclass
-nv40_graph_cclass = {
+nv40_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x40),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv40_graph_context_ctor,
- .dtor = _nouveau_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = nv40_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nv40_gr_context_ctor,
+ .dtor = _nouveau_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = nv40_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
};
@@ -212,15 +212,15 @@ nv40_graph_cclass = {
******************************************************************************/
static void
-nv40_graph_tile_prog(struct nouveau_engine *engine, int i)
+nv40_gr_tile_prog(struct nouveau_engine *engine, int i)
{
struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
struct nouveau_fifo *pfifo = nouveau_fifo(engine);
- struct nv40_graph_priv *priv = (void *)engine;
+ struct nv40_gr_priv *priv = (void *)engine;
unsigned long flags;
pfifo->pause(pfifo, &flags);
- nv04_graph_idle(priv);
+ nv04_gr_idle(priv);
switch (nv_device(priv)->chipset) {
case 0x40:
@@ -290,13 +290,13 @@ nv40_graph_tile_prog(struct nouveau_engine *engine, int i)
}
static void
-nv40_graph_intr(struct nouveau_subdev *subdev)
+nv40_gr_intr(struct nouveau_subdev *subdev)
{
struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
struct nouveau_engine *engine = nv_engine(subdev);
struct nouveau_object *engctx;
struct nouveau_handle *handle = NULL;
- struct nv40_graph_priv *priv = (void *)subdev;
+ struct nv40_gr_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
@@ -330,11 +330,11 @@ nv40_graph_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv10_graph_intr_name, show);
+ nouveau_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
- nouveau_bitfield_print(nv04_graph_nsource, nsource);
+ nouveau_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
- nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
+ nouveau_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(priv,
"ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
@@ -346,41 +346,41 @@ nv40_graph_intr(struct nouveau_subdev *subdev)
}
static int
-nv40_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv40_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv40_graph_priv *priv;
+ struct nv40_gr_priv *priv;
int ret;
- ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+ ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00001000;
- nv_subdev(priv)->intr = nv40_graph_intr;
- nv_engine(priv)->cclass = &nv40_graph_cclass;
- if (nv44_graph_class(priv))
- nv_engine(priv)->sclass = nv44_graph_sclass;
+ nv_subdev(priv)->intr = nv40_gr_intr;
+ nv_engine(priv)->cclass = &nv40_gr_cclass;
+ if (nv44_gr_class(priv))
+ nv_engine(priv)->sclass = nv44_gr_sclass;
else
- nv_engine(priv)->sclass = nv40_graph_sclass;
- nv_engine(priv)->tile_prog = nv40_graph_tile_prog;
+ nv_engine(priv)->sclass = nv40_gr_sclass;
+ nv_engine(priv)->tile_prog = nv40_gr_tile_prog;
- priv->base.units = nv40_graph_units;
+ priv->base.units = nv40_gr_units;
return 0;
}
static int
-nv40_graph_init(struct nouveau_object *object)
+nv40_gr_init(struct nouveau_object *object)
{
struct nouveau_engine *engine = nv_engine(object);
struct nouveau_fb *pfb = nouveau_fb(object);
- struct nv40_graph_priv *priv = (void *)engine;
+ struct nv40_gr_priv *priv = (void *)engine;
int ret, i, j;
u32 vramsz;
- ret = nouveau_graph_init(&priv->base);
+ ret = nouveau_gr_init(&priv->base);
if (ret)
return ret;
@@ -525,12 +525,12 @@ nv40_graph_init(struct nouveau_object *object)
}
struct nouveau_oclass
-nv40_graph_oclass = {
+nv40_gr_oclass = {
.handle = NV_ENGINE(GR, 0x40),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv40_graph_ctor,
- .dtor = _nouveau_graph_dtor,
- .init = nv40_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nv40_gr_ctor,
+ .dtor = _nouveau_gr_dtor,
+ .init = nv40_gr_init,
+ .fini = _nouveau_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
similarity index 86%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
index ad8209377529..40545f260c0d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
@@ -1,5 +1,5 @@
-#ifndef __NV40_GRAPH_H__
-#define __NV40_GRAPH_H__
+#ifndef __NV40_GR_H__
+#define __NV40_GR_H__
#include <core/device.h>
#include <core/gpuobj.h>
@@ -8,7 +8,7 @@
* helpful to determine a number of other hardware features
*/
static inline int
-nv44_graph_class(void *priv)
+nv44_gr_class(void *priv)
{
struct nouveau_device *device = nv_device(priv);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
similarity index 84%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
index 896e17b56f45..bd7687c683c8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
@@ -33,24 +33,24 @@
#include <subdev/timer.h>
#include <engine/fifo.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
#include "nv50.h"
-struct nv50_graph_priv {
- struct nouveau_graph base;
+struct nv50_gr_priv {
+ struct nouveau_gr base;
spinlock_t lock;
u32 size;
};
-struct nv50_graph_chan {
- struct nouveau_graph_chan base;
+struct nv50_gr_chan {
+ struct nouveau_gr_chan base;
};
static u64
-nv50_graph_units(struct nouveau_graph *graph)
+nv50_gr_units(struct nouveau_gr *gr)
{
- struct nv50_graph_priv *priv = (void *)graph;
+ struct nv50_gr_priv *priv = (void *)gr;
return nv_rd32(priv, 0x1540);
}
@@ -60,7 +60,7 @@ nv50_graph_units(struct nouveau_graph *graph)
******************************************************************************/
static int
-nv50_graph_object_ctor(struct nouveau_object *parent,
+nv50_gr_object_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
@@ -82,8 +82,8 @@ nv50_graph_object_ctor(struct nouveau_object *parent,
}
static struct nouveau_ofuncs
-nv50_graph_ofuncs = {
- .ctor = nv50_graph_object_ctor,
+nv50_gr_ofuncs = {
+ .ctor = nv50_gr_object_ctor,
.dtor = _nouveau_gpuobj_dtor,
.init = _nouveau_gpuobj_init,
.fini = _nouveau_gpuobj_fini,
@@ -92,54 +92,54 @@ nv50_graph_ofuncs = {
};
static struct nouveau_oclass
-nv50_graph_sclass[] = {
- { 0x0030, &nv50_graph_ofuncs },
- { 0x502d, &nv50_graph_ofuncs },
- { 0x5039, &nv50_graph_ofuncs },
- { 0x5097, &nv50_graph_ofuncs },
- { 0x50c0, &nv50_graph_ofuncs },
+nv50_gr_sclass[] = {
+ { 0x0030, &nv50_gr_ofuncs },
+ { 0x502d, &nv50_gr_ofuncs },
+ { 0x5039, &nv50_gr_ofuncs },
+ { 0x5097, &nv50_gr_ofuncs },
+ { 0x50c0, &nv50_gr_ofuncs },
{}
};
static struct nouveau_oclass
-nv84_graph_sclass[] = {
- { 0x0030, &nv50_graph_ofuncs },
- { 0x502d, &nv50_graph_ofuncs },
- { 0x5039, &nv50_graph_ofuncs },
- { 0x50c0, &nv50_graph_ofuncs },
- { 0x8297, &nv50_graph_ofuncs },
+nv84_gr_sclass[] = {
+ { 0x0030, &nv50_gr_ofuncs },
+ { 0x502d, &nv50_gr_ofuncs },
+ { 0x5039, &nv50_gr_ofuncs },
+ { 0x50c0, &nv50_gr_ofuncs },
+ { 0x8297, &nv50_gr_ofuncs },
{}
};
static struct nouveau_oclass
-nva0_graph_sclass[] = {
- { 0x0030, &nv50_graph_ofuncs },
- { 0x502d, &nv50_graph_ofuncs },
- { 0x5039, &nv50_graph_ofuncs },
- { 0x50c0, &nv50_graph_ofuncs },
- { 0x8397, &nv50_graph_ofuncs },
+nva0_gr_sclass[] = {
+ { 0x0030, &nv50_gr_ofuncs },
+ { 0x502d, &nv50_gr_ofuncs },
+ { 0x5039, &nv50_gr_ofuncs },
+ { 0x50c0, &nv50_gr_ofuncs },
+ { 0x8397, &nv50_gr_ofuncs },
{}
};
static struct nouveau_oclass
-nva3_graph_sclass[] = {
- { 0x0030, &nv50_graph_ofuncs },
- { 0x502d, &nv50_graph_ofuncs },
- { 0x5039, &nv50_graph_ofuncs },
- { 0x50c0, &nv50_graph_ofuncs },
- { 0x8597, &nv50_graph_ofuncs },
- { 0x85c0, &nv50_graph_ofuncs },
+nva3_gr_sclass[] = {
+ { 0x0030, &nv50_gr_ofuncs },
+ { 0x502d, &nv50_gr_ofuncs },
+ { 0x5039, &nv50_gr_ofuncs },
+ { 0x50c0, &nv50_gr_ofuncs },
+ { 0x8597, &nv50_gr_ofuncs },
+ { 0x85c0, &nv50_gr_ofuncs },
{}
};
static struct nouveau_oclass
-nvaf_graph_sclass[] = {
- { 0x0030, &nv50_graph_ofuncs },
- { 0x502d, &nv50_graph_ofuncs },
- { 0x5039, &nv50_graph_ofuncs },
- { 0x50c0, &nv50_graph_ofuncs },
- { 0x85c0, &nv50_graph_ofuncs },
- { 0x8697, &nv50_graph_ofuncs },
+nvaf_gr_sclass[] = {
+ { 0x0030, &nv50_gr_ofuncs },
+ { 0x502d, &nv50_gr_ofuncs },
+ { 0x5039, &nv50_gr_ofuncs },
+ { 0x50c0, &nv50_gr_ofuncs },
+ { 0x85c0, &nv50_gr_ofuncs },
+ { 0x8697, &nv50_gr_ofuncs },
{}
};
@@ -148,16 +148,16 @@ nvaf_graph_sclass[] = {
******************************************************************************/
static int
-nv50_graph_context_ctor(struct nouveau_object *parent,
+nv50_gr_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv50_graph_priv *priv = (void *)engine;
- struct nv50_graph_chan *chan;
+ struct nv50_gr_priv *priv = (void *)engine;
+ struct nv50_gr_chan *chan;
int ret;
- ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
+ ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
priv->size, 0,
NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
@@ -169,15 +169,15 @@ nv50_graph_context_ctor(struct nouveau_object *parent,
}
static struct nouveau_oclass
-nv50_graph_cclass = {
+nv50_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x50),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv50_graph_context_ctor,
- .dtor = _nouveau_graph_context_dtor,
- .init = _nouveau_graph_context_init,
- .fini = _nouveau_graph_context_fini,
- .rd32 = _nouveau_graph_context_rd32,
- .wr32 = _nouveau_graph_context_wr32,
+ .ctor = nv50_gr_context_ctor,
+ .dtor = _nouveau_gr_context_dtor,
+ .init = _nouveau_gr_context_init,
+ .fini = _nouveau_gr_context_fini,
+ .rd32 = _nouveau_gr_context_rd32,
+ .wr32 = _nouveau_gr_context_wr32,
},
};
@@ -185,7 +185,7 @@ nv50_graph_cclass = {
* PGRAPH engine/subdev functions
******************************************************************************/
-static const struct nouveau_bitfield nv50_pgraph_status[] = {
+static const struct nouveau_bitfield nv50_pgr_status[] = {
{ 0x00000001, "BUSY" }, /* set when any bit is set */
{ 0x00000002, "DISPATCH" },
{ 0x00000004, "UNK2" },
@@ -214,21 +214,21 @@ static const struct nouveau_bitfield nv50_pgraph_status[] = {
{}
};
-static const char *const nv50_pgraph_vstatus_0[] = {
+static const char *const nv50_pgr_vstatus_0[] = {
"VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP",
NULL
};
-static const char *const nv50_pgraph_vstatus_1[] = {
+static const char *const nv50_pgr_vstatus_1[] = {
"TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL
};
-static const char *const nv50_pgraph_vstatus_2[] = {
+static const char *const nv50_pgr_vstatus_2[] = {
"RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK",
"ROP", NULL
};
-static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r,
+static void nouveau_pgr_vstatus_print(struct nv50_gr_priv *priv, int r,
const char *const units[], u32 status)
{
int i;
@@ -246,10 +246,10 @@ static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r,
}
static int
-nv84_graph_tlb_flush(struct nouveau_engine *engine)
+nv84_gr_tlb_flush(struct nouveau_engine *engine)
{
struct nouveau_timer *ptimer = nouveau_timer(engine);
- struct nv50_graph_priv *priv = (void *)engine;
+ struct nv50_gr_priv *priv = (void *)engine;
bool idle, timeout = false;
unsigned long flags;
u64 start;
@@ -284,14 +284,14 @@ nv84_graph_tlb_flush(struct nouveau_engine *engine)
tmp = nv_rd32(priv, 0x400700);
nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp);
- nouveau_bitfield_print(nv50_pgraph_status, tmp);
+ nouveau_bitfield_print(nv50_pgr_status, tmp);
pr_cont("\n");
- nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0,
+ nouveau_pgr_vstatus_print(priv, 0, nv50_pgr_vstatus_0,
nv_rd32(priv, 0x400380));
- nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1,
+ nouveau_pgr_vstatus_print(priv, 1, nv50_pgr_vstatus_1,
nv_rd32(priv, 0x400384));
- nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2,
+ nouveau_pgr_vstatus_print(priv, 2, nv50_pgr_vstatus_2,
nv_rd32(priv, 0x400388));
}
@@ -338,24 +338,24 @@ static const struct nouveau_bitfield nv50_tex_traps[] = {
{}
};
-static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
+static const struct nouveau_bitfield nv50_gr_trap_m2mf[] = {
{ 0x00000001, "NOTIFY" },
{ 0x00000002, "IN" },
{ 0x00000004, "OUT" },
{}
};
-static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
+static const struct nouveau_bitfield nv50_gr_trap_vfetch[] = {
{ 0x00000001, "FAULT" },
{}
};
-static const struct nouveau_bitfield nv50_graph_trap_strmout[] = {
+static const struct nouveau_bitfield nv50_gr_trap_strmout[] = {
{ 0x00000001, "FAULT" },
{}
};
-static const struct nouveau_bitfield nv50_graph_trap_ccache[] = {
+static const struct nouveau_bitfield nv50_gr_trap_ccache[] = {
{ 0x00000001, "FAULT" },
{}
};
@@ -407,7 +407,7 @@ const struct nouveau_enum nv50_data_error_names[] = {
{}
};
-static const struct nouveau_bitfield nv50_graph_intr_name[] = {
+static const struct nouveau_bitfield nv50_gr_intr_name[] = {
{ 0x00000001, "NOTIFY" },
{ 0x00000002, "COMPUTE_QUERY" },
{ 0x00000010, "ILLEGAL_MTHD" },
@@ -421,7 +421,7 @@ static const struct nouveau_bitfield nv50_graph_intr_name[] = {
{}
};
-static const struct nouveau_bitfield nv50_graph_trap_prop[] = {
+static const struct nouveau_bitfield nv50_gr_trap_prop[] = {
{ 0x00000004, "SURF_WIDTH_OVERRUN" },
{ 0x00000008, "SURF_HEIGHT_OVERRUN" },
{ 0x00000010, "DST2D_FAULT" },
@@ -437,7 +437,7 @@ static const struct nouveau_bitfield nv50_graph_trap_prop[] = {
};
static void
-nv50_priv_prop_trap(struct nv50_graph_priv *priv,
+nv50_priv_prop_trap(struct nv50_gr_priv *priv,
u32 ustatus_addr, u32 ustatus, u32 tp)
{
u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
@@ -468,7 +468,7 @@ nv50_priv_prop_trap(struct nv50_graph_priv *priv,
}
if (ustatus) {
nv_error(priv, "TRAP_PROP - TP %d -", tp);
- nouveau_bitfield_print(nv50_graph_trap_prop, ustatus);
+ nouveau_bitfield_print(nv50_gr_trap_prop, ustatus);
pr_cont(" - Address %02x%08x\n", e14, e10);
}
nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
@@ -476,7 +476,7 @@ nv50_priv_prop_trap(struct nv50_graph_priv *priv,
}
static void
-nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
+nv50_priv_mp_trap(struct nv50_gr_priv *priv, int tpid, int display)
{
u32 units = nv_rd32(priv, 0x1540);
u32 addr, mp10, status, pc, oplow, ophigh;
@@ -515,7 +515,7 @@ nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
}
static void
-nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
+nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old,
u32 ustatus_new, int display, const char *name)
{
int tps = 0;
@@ -580,7 +580,7 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
}
static int
-nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
+nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display,
int chid, u64 inst, struct nouveau_object *engctx)
{
u32 status = nv_rd32(priv, 0x400108);
@@ -670,7 +670,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff;
if (display) {
nv_error(priv, "TRAP_M2MF");
- nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
+ nouveau_bitfield_print(nv50_gr_trap_m2mf, ustatus);
pr_cont("\n");
nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
@@ -691,7 +691,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff;
if (display) {
nv_error(priv, "TRAP_VFETCH");
- nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
+ nouveau_bitfield_print(nv50_gr_trap_vfetch, ustatus);
pr_cont("\n");
nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
@@ -708,7 +708,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff;
if (display) {
nv_error(priv, "TRAP_STRMOUT");
- nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
+ nouveau_bitfield_print(nv50_gr_trap_strmout, ustatus);
pr_cont("\n");
nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
@@ -729,7 +729,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff;
if (display) {
nv_error(priv, "TRAP_CCACHE");
- nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
+ nouveau_bitfield_print(nv50_gr_trap_ccache, ustatus);
pr_cont("\n");
nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
" %08x %08x %08x\n",
@@ -791,13 +791,13 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
}
static void
-nv50_graph_intr(struct nouveau_subdev *subdev)
+nv50_gr_intr(struct nouveau_subdev *subdev)
{
struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
struct nouveau_engine *engine = nv_engine(subdev);
struct nouveau_object *engctx;
struct nouveau_handle *handle = NULL;
- struct nv50_graph_priv *priv = (void *)subdev;
+ struct nv50_gr_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, 0x400100);
u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff;
u32 addr = nv_rd32(priv, 0x400704);
@@ -827,7 +827,7 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
}
if (stat & 0x00200000) {
- if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12,
+ if (!nv50_gr_trap_handler(priv, show, chid, (u64)inst << 12,
engctx))
show &= ~0x00200000;
show_bitfield &= ~0x00200000;
@@ -840,7 +840,7 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
show &= show_bitfield;
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv50_graph_intr_name, show);
+ nouveau_bitfield_print(nv50_gr_intr_name, show);
pr_cont("\n");
}
nv_error(priv,
@@ -856,27 +856,27 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
}
static int
-nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv50_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv50_graph_priv *priv;
+ struct nv50_gr_priv *priv;
int ret;
- ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+ ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00201000;
- nv_subdev(priv)->intr = nv50_graph_intr;
- nv_engine(priv)->cclass = &nv50_graph_cclass;
+ nv_subdev(priv)->intr = nv50_gr_intr;
+ nv_engine(priv)->cclass = &nv50_gr_cclass;
- priv->base.units = nv50_graph_units;
+ priv->base.units = nv50_gr_units;
switch (nv_device(priv)->chipset) {
case 0x50:
- nv_engine(priv)->sclass = nv50_graph_sclass;
+ nv_engine(priv)->sclass = nv50_gr_sclass;
break;
case 0x84:
case 0x86:
@@ -884,20 +884,20 @@ nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
case 0x94:
case 0x96:
case 0x98:
- nv_engine(priv)->sclass = nv84_graph_sclass;
+ nv_engine(priv)->sclass = nv84_gr_sclass;
break;
case 0xa0:
case 0xaa:
case 0xac:
- nv_engine(priv)->sclass = nva0_graph_sclass;
+ nv_engine(priv)->sclass = nva0_gr_sclass;
break;
case 0xa3:
case 0xa5:
case 0xa8:
- nv_engine(priv)->sclass = nva3_graph_sclass;
+ nv_engine(priv)->sclass = nva3_gr_sclass;
break;
case 0xaf:
- nv_engine(priv)->sclass = nvaf_graph_sclass;
+ nv_engine(priv)->sclass = nvaf_gr_sclass;
break;
}
@@ -905,19 +905,19 @@ nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
/* unfortunate hw bug workaround... */
if (nv_device(priv)->chipset != 0x50 &&
nv_device(priv)->chipset != 0xac)
- nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush;
+ nv_engine(priv)->tlb_flush = nv84_gr_tlb_flush;
spin_lock_init(&priv->lock);
return 0;
}
static int
-nv50_graph_init(struct nouveau_object *object)
+nv50_gr_init(struct nouveau_object *object)
{
- struct nv50_graph_priv *priv = (void *)object;
+ struct nv50_gr_priv *priv = (void *)object;
int ret, units, i;
- ret = nouveau_graph_init(&priv->base);
+ ret = nouveau_gr_init(&priv->base);
if (ret)
return ret;
@@ -998,12 +998,12 @@ nv50_graph_init(struct nouveau_object *object)
}
struct nouveau_oclass
-nv50_graph_oclass = {
+nv50_gr_oclass = {
.handle = NV_ENGINE(GR, 0x50),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv50_graph_ctor,
- .dtor = _nouveau_graph_dtor,
- .init = nv50_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nv50_gr_ctor,
+ .dtor = _nouveau_gr_dtor,
+ .init = nv50_gr_init,
+ .fini = _nouveau_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
similarity index 73%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
index 0505fb419bde..eb39af055bbb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
@@ -1,5 +1,5 @@
-#ifndef __NV50_GRAPH_H__
-#define __NV50_GRAPH_H__
+#ifndef __NV50_GR_H__
+#define __NV50_GR_H__
int nv50_grctx_init(struct nouveau_device *, u32 *size);
void nv50_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c
similarity index 81%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c
index 3e90e437dbbe..8133650b2777 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c
@@ -30,7 +30,7 @@
******************************************************************************/
static void
-nvc0_graph_zbc_clear_color(struct nvc0_graph_priv *priv, int zbc)
+nvc0_gr_zbc_clear_color(struct nvc0_gr_priv *priv, int zbc)
{
if (priv->zbc_color[zbc].format) {
nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]);
@@ -44,7 +44,7 @@ nvc0_graph_zbc_clear_color(struct nvc0_graph_priv *priv, int zbc)
}
static int
-nvc0_graph_zbc_color_get(struct nvc0_graph_priv *priv, int format,
+nvc0_gr_zbc_color_get(struct nvc0_gr_priv *priv, int format,
const u32 ds[4], const u32 l2[4])
{
struct nouveau_ltc *ltc = nouveau_ltc(priv);
@@ -75,12 +75,12 @@ nvc0_graph_zbc_color_get(struct nvc0_graph_priv *priv, int format,
memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2));
priv->zbc_color[zbc].format = format;
ltc->zbc_color_get(ltc, zbc, l2);
- nvc0_graph_zbc_clear_color(priv, zbc);
+ nvc0_gr_zbc_clear_color(priv, zbc);
return zbc;
}
static void
-nvc0_graph_zbc_clear_depth(struct nvc0_graph_priv *priv, int zbc)
+nvc0_gr_zbc_clear_depth(struct nvc0_gr_priv *priv, int zbc)
{
if (priv->zbc_depth[zbc].format)
nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds);
@@ -90,7 +90,7 @@ nvc0_graph_zbc_clear_depth(struct nvc0_graph_priv *priv, int zbc)
}
static int
-nvc0_graph_zbc_depth_get(struct nvc0_graph_priv *priv, int format,
+nvc0_gr_zbc_depth_get(struct nvc0_gr_priv *priv, int format,
const u32 ds, const u32 l2)
{
struct nouveau_ltc *ltc = nouveau_ltc(priv);
@@ -119,7 +119,7 @@ nvc0_graph_zbc_depth_get(struct nvc0_graph_priv *priv, int format,
priv->zbc_depth[zbc].ds = ds;
priv->zbc_depth[zbc].l2 = l2;
ltc->zbc_depth_get(ltc, zbc, l2);
- nvc0_graph_zbc_clear_depth(priv, zbc);
+ nvc0_gr_zbc_clear_depth(priv, zbc);
return zbc;
}
@@ -130,7 +130,7 @@ nvc0_graph_zbc_depth_get(struct nvc0_graph_priv *priv, int format,
static int
nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size)
{
- struct nvc0_graph_priv *priv = (void *)object->engine;
+ struct nvc0_gr_priv *priv = (void *)object->engine;
union {
struct fermi_a_zbc_color_v0 v0;
} *args = data;
@@ -157,7 +157,7 @@ nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size)
case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
- ret = nvc0_graph_zbc_color_get(priv, args->v0.format,
+ ret = nvc0_gr_zbc_color_get(priv, args->v0.format,
args->v0.ds,
args->v0.l2);
if (ret >= 0) {
@@ -176,7 +176,7 @@ nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size)
static int
nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size)
{
- struct nvc0_graph_priv *priv = (void *)object->engine;
+ struct nvc0_gr_priv *priv = (void *)object->engine;
union {
struct fermi_a_zbc_depth_v0 v0;
} *args = data;
@@ -185,7 +185,7 @@ nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size)
if (nvif_unpack(args->v0, 0, 0, false)) {
switch (args->v0.format) {
case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
- ret = nvc0_graph_zbc_depth_get(priv, args->v0.format,
+ ret = nvc0_gr_zbc_depth_get(priv, args->v0.format,
args->v0.ds,
args->v0.l2);
return (ret >= 0) ? 0 : -ENOSPC;
@@ -221,10 +221,10 @@ nvc0_fermi_ofuncs = {
};
static int
-nvc0_graph_set_shader_exceptions(struct nouveau_object *object, u32 mthd,
+nvc0_gr_set_shader_exceptions(struct nouveau_object *object, u32 mthd,
void *pdata, u32 size)
{
- struct nvc0_graph_priv *priv = (void *)nv_engine(object);
+ struct nvc0_gr_priv *priv = (void *)nv_engine(object);
if (size >= sizeof(u32)) {
u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000;
nv_wr32(priv, 0x419e44, data);
@@ -235,23 +235,23 @@ nvc0_graph_set_shader_exceptions(struct nouveau_object *object, u32 mthd,
}
struct nouveau_omthds
-nvc0_graph_9097_omthds[] = {
- { 0x1528, 0x1528, nvc0_graph_set_shader_exceptions },
+nvc0_gr_9097_omthds[] = {
+ { 0x1528, 0x1528, nvc0_gr_set_shader_exceptions },
{}
};
struct nouveau_omthds
-nvc0_graph_90c0_omthds[] = {
- { 0x1528, 0x1528, nvc0_graph_set_shader_exceptions },
+nvc0_gr_90c0_omthds[] = {
+ { 0x1528, 0x1528, nvc0_gr_set_shader_exceptions },
{}
};
struct nouveau_oclass
-nvc0_graph_sclass[] = {
+nvc0_gr_sclass[] = {
{ 0x902d, &nouveau_object_ofuncs },
{ 0x9039, &nouveau_object_ofuncs },
- { FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
- { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+ { FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+ { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
{}
};
@@ -260,20 +260,20 @@ nvc0_graph_sclass[] = {
******************************************************************************/
int
-nvc0_graph_context_ctor(struct nouveau_object *parent,
+nvc0_gr_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *args, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_vm *vm = nouveau_client(parent)->vm;
- struct nvc0_graph_priv *priv = (void *)engine;
- struct nvc0_graph_data *data = priv->mmio_data;
- struct nvc0_graph_mmio *mmio = priv->mmio_list;
- struct nvc0_graph_chan *chan;
+ struct nvc0_gr_priv *priv = (void *)engine;
+ struct nvc0_gr_data *data = priv->mmio_data;
+ struct nvc0_gr_mmio *mmio = priv->mmio_list;
+ struct nvc0_gr_chan *chan;
int ret, i;
/* allocate memory for context, and fill with default values */
- ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
+ ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
priv->size, 0x100,
NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
@@ -347,9 +347,9 @@ nvc0_graph_context_ctor(struct nouveau_object *parent,
}
void
-nvc0_graph_context_dtor(struct nouveau_object *object)
+nvc0_gr_context_dtor(struct nouveau_object *object)
{
- struct nvc0_graph_chan *chan = (void *)object;
+ struct nvc0_gr_chan *chan = (void *)object;
int i;
for (i = 0; i < ARRAY_SIZE(chan->data); i++) {
@@ -360,15 +360,15 @@ nvc0_graph_context_dtor(struct nouveau_object *object)
nouveau_gpuobj_unmap(&chan->mmio_vma);
nouveau_gpuobj_ref(NULL, &chan->mmio);
- nouveau_graph_context_destroy(&chan->base);
+ nouveau_gr_context_destroy(&chan->base);
}
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_graph_init
-nvc0_graph_init_main_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x00006fe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
@@ -383,53 +383,53 @@ nvc0_graph_init_main_0[] = {
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_fe_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_fe_0[] = {
{ 0x40415c, 1, 0x04, 0x00000000 },
{ 0x404170, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_pri_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_pri_0[] = {
{ 0x404488, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_rstr2d_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_rstr2d_0[] = {
{ 0x407808, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_pd_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_pd_0[] = {
{ 0x406024, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_ds_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405908, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_scc_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_scc_0[] = {
{ 0x40803c, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_prop_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_prop_0[] = {
{ 0x4184a0, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_gpc_unk_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_gpc_unk_0[] = {
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x80000000 },
@@ -437,20 +437,20 @@ nvc0_graph_init_gpc_unk_0[] = {
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_setup_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_setup_0[] = {
{ 0x418814, 3, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_crstr_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_crstr_0[] = {
{ 0x418b04, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_setup_1[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_setup_1[] = {
{ 0x4188c8, 1, 0x04, 0x80000000 },
{ 0x4188cc, 1, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
@@ -458,8 +458,8 @@ nvc0_graph_init_setup_1[] = {
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_zcull_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_zcull_0[] = {
{ 0x418910, 1, 0x04, 0x00010001 },
{ 0x418914, 1, 0x04, 0x00000301 },
{ 0x418918, 1, 0x04, 0x00800000 },
@@ -468,15 +468,15 @@ nvc0_graph_init_zcull_0[] = {
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_gpm_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_gpm_0[] = {
{ 0x418c04, 1, 0x04, 0x00000000 },
{ 0x418c88, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_gpc_unk_1[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000050 },
@@ -484,30 +484,30 @@ nvc0_graph_init_gpc_unk_1[] = {
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_gcc_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_gcc_0[] = {
{ 0x41900c, 1, 0x04, 0x00000000 },
{ 0x419018, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_tpccs_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_tpccs_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_tex_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_pe_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_pe_0[] = {
{ 0x41980c, 3, 0x04, 0x00000000 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc5 },
@@ -515,8 +515,8 @@ nvc0_graph_init_pe_0[] = {
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_l1c_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x80000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
@@ -526,27 +526,27 @@ nvc0_graph_init_l1c_0[] = {
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_wwdx_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_wwdx_0[] = {
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_tpccs_1[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_tpccs_1[] = {
{ 0x419d2c, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_mpc_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_mpc_0[] = {
{ 0x419c0c, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_graph_init
-nvc0_graph_init_sm_0[] = {
+static const struct nvc0_gr_init
+nvc0_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@@ -563,8 +563,8 @@ nvc0_graph_init_sm_0[] = {
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_be_0[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_be_0[] = {
{ 0x40880c, 1, 0x04, 0x00000000 },
{ 0x408910, 9, 0x04, 0x00000000 },
{ 0x408950, 1, 0x04, 0x00000000 },
@@ -575,47 +575,47 @@ nvc0_graph_init_be_0[] = {
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_fe_1[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_fe_1[] = {
{ 0x4040f0, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvc0_graph_init_pe_1[] = {
+const struct nvc0_gr_init
+nvc0_gr_init_pe_1[] = {
{ 0x419880, 1, 0x04, 0x00000002 },
{}
};
-static const struct nvc0_graph_pack
-nvc0_graph_pack_mmio[] = {
- { nvc0_graph_init_main_0 },
- { nvc0_graph_init_fe_0 },
- { nvc0_graph_init_pri_0 },
- { nvc0_graph_init_rstr2d_0 },
- { nvc0_graph_init_pd_0 },
- { nvc0_graph_init_ds_0 },
- { nvc0_graph_init_scc_0 },
- { nvc0_graph_init_prop_0 },
- { nvc0_graph_init_gpc_unk_0 },
- { nvc0_graph_init_setup_0 },
- { nvc0_graph_init_crstr_0 },
- { nvc0_graph_init_setup_1 },
- { nvc0_graph_init_zcull_0 },
- { nvc0_graph_init_gpm_0 },
- { nvc0_graph_init_gpc_unk_1 },
- { nvc0_graph_init_gcc_0 },
- { nvc0_graph_init_tpccs_0 },
- { nvc0_graph_init_tex_0 },
- { nvc0_graph_init_pe_0 },
- { nvc0_graph_init_l1c_0 },
- { nvc0_graph_init_wwdx_0 },
- { nvc0_graph_init_tpccs_1 },
- { nvc0_graph_init_mpc_0 },
- { nvc0_graph_init_sm_0 },
- { nvc0_graph_init_be_0 },
- { nvc0_graph_init_fe_1 },
- { nvc0_graph_init_pe_1 },
+static const struct nvc0_gr_pack
+nvc0_gr_pack_mmio[] = {
+ { nvc0_gr_init_main_0 },
+ { nvc0_gr_init_fe_0 },
+ { nvc0_gr_init_pri_0 },
+ { nvc0_gr_init_rstr2d_0 },
+ { nvc0_gr_init_pd_0 },
+ { nvc0_gr_init_ds_0 },
+ { nvc0_gr_init_scc_0 },
+ { nvc0_gr_init_prop_0 },
+ { nvc0_gr_init_gpc_unk_0 },
+ { nvc0_gr_init_setup_0 },
+ { nvc0_gr_init_crstr_0 },
+ { nvc0_gr_init_setup_1 },
+ { nvc0_gr_init_zcull_0 },
+ { nvc0_gr_init_gpm_0 },
+ { nvc0_gr_init_gpc_unk_1 },
+ { nvc0_gr_init_gcc_0 },
+ { nvc0_gr_init_tpccs_0 },
+ { nvc0_gr_init_tex_0 },
+ { nvc0_gr_init_pe_0 },
+ { nvc0_gr_init_l1c_0 },
+ { nvc0_gr_init_wwdx_0 },
+ { nvc0_gr_init_tpccs_1 },
+ { nvc0_gr_init_mpc_0 },
+ { nvc0_gr_init_sm_0 },
+ { nvc0_gr_init_be_0 },
+ { nvc0_gr_init_fe_1 },
+ { nvc0_gr_init_pe_1 },
{}
};
@@ -624,7 +624,7 @@ nvc0_graph_pack_mmio[] = {
******************************************************************************/
void
-nvc0_graph_zbc_init(struct nvc0_graph_priv *priv)
+nvc0_gr_zbc_init(struct nvc0_gr_priv *priv)
{
const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000 };
@@ -638,25 +638,25 @@ nvc0_graph_zbc_init(struct nvc0_graph_priv *priv)
int index;
if (!priv->zbc_color[0].format) {
- nvc0_graph_zbc_color_get(priv, 1, & zero[0], &zero[4]);
- nvc0_graph_zbc_color_get(priv, 2, & one[0], &one[4]);
- nvc0_graph_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]);
- nvc0_graph_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]);
- nvc0_graph_zbc_depth_get(priv, 1, 0x00000000, 0x00000000);
- nvc0_graph_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000);
+ nvc0_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]);
+ nvc0_gr_zbc_color_get(priv, 2, & one[0], &one[4]);
+ nvc0_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]);
+ nvc0_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]);
+ nvc0_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000);
+ nvc0_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000);
}
for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
- nvc0_graph_zbc_clear_color(priv, index);
+ nvc0_gr_zbc_clear_color(priv, index);
for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
- nvc0_graph_zbc_clear_depth(priv, index);
+ nvc0_gr_zbc_clear_depth(priv, index);
}
void
-nvc0_graph_mmio(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
+nvc0_gr_mmio(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
{
- const struct nvc0_graph_pack *pack;
- const struct nvc0_graph_init *init;
+ const struct nvc0_gr_pack *pack;
+ const struct nvc0_gr_init *init;
pack_for_each_init(init, pack, p) {
u32 next = init->addr + init->count * init->pitch;
@@ -669,10 +669,10 @@ nvc0_graph_mmio(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
}
void
-nvc0_graph_icmd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
+nvc0_gr_icmd(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
{
- const struct nvc0_graph_pack *pack;
- const struct nvc0_graph_init *init;
+ const struct nvc0_gr_pack *pack;
+ const struct nvc0_gr_init *init;
u32 data = 0;
nv_wr32(priv, 0x400208, 0x80000000);
@@ -697,10 +697,10 @@ nvc0_graph_icmd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
}
void
-nvc0_graph_mthd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
+nvc0_gr_mthd(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
{
- const struct nvc0_graph_pack *pack;
- const struct nvc0_graph_init *init;
+ const struct nvc0_gr_pack *pack;
+ const struct nvc0_gr_init *init;
u32 data = 0;
pack_for_each_init(init, pack, p) {
@@ -721,9 +721,9 @@ nvc0_graph_mthd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p)
}
u64
-nvc0_graph_units(struct nouveau_graph *graph)
+nvc0_gr_units(struct nouveau_gr *gr)
{
- struct nvc0_graph_priv *priv = (void *)graph;
+ struct nvc0_gr_priv *priv = (void *)gr;
u64 cfg;
cfg = (u32)priv->gpc_nr;
@@ -759,7 +759,7 @@ static const struct nouveau_enum nvc0_gpc_rop_error[] = {
};
static void
-nvc0_graph_trap_gpc_rop(struct nvc0_graph_priv *priv, int gpc)
+nvc0_gr_trap_gpc_rop(struct nvc0_gr_priv *priv, int gpc)
{
u32 trap[4];
int i;
@@ -804,7 +804,7 @@ static const struct nouveau_bitfield nvc0_mp_global_error[] = {
};
static void
-nvc0_graph_trap_mp(struct nvc0_graph_priv *priv, int gpc, int tpc)
+nvc0_gr_trap_mp(struct nvc0_gr_priv *priv, int gpc, int tpc)
{
u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648));
u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650));
@@ -822,7 +822,7 @@ nvc0_graph_trap_mp(struct nvc0_graph_priv *priv, int gpc, int tpc)
}
static void
-nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
+nvc0_gr_trap_tpc(struct nvc0_gr_priv *priv, int gpc, int tpc)
{
u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508));
@@ -834,7 +834,7 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
}
if (stat & 0x00000002) {
- nvc0_graph_trap_mp(priv, gpc, tpc);
+ nvc0_gr_trap_mp(priv, gpc, tpc);
stat &= ~0x00000002;
}
@@ -858,13 +858,13 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
}
static void
-nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
+nvc0_gr_trap_gpc(struct nvc0_gr_priv *priv, int gpc)
{
u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90));
int tpc;
if (stat & 0x00000001) {
- nvc0_graph_trap_gpc_rop(priv, gpc);
+ nvc0_gr_trap_gpc_rop(priv, gpc);
stat &= ~0x00000001;
}
@@ -892,7 +892,7 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
u32 mask = 0x00010000 << tpc;
if (stat & mask) {
- nvc0_graph_trap_tpc(priv, gpc, tpc);
+ nvc0_gr_trap_tpc(priv, gpc, tpc);
nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask);
stat &= ~mask;
}
@@ -904,7 +904,7 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
}
static void
-nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
+nvc0_gr_trap_intr(struct nvc0_gr_priv *priv)
{
u32 trap = nv_rd32(priv, 0x400108);
int rop, gpc, i;
@@ -980,7 +980,7 @@ nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) {
u32 mask = 0x00000001 << gpc;
if (stat & mask) {
- nvc0_graph_trap_gpc(priv, gpc);
+ nvc0_gr_trap_gpc(priv, gpc);
nv_wr32(priv, 0x400118, mask);
stat &= ~mask;
}
@@ -1009,7 +1009,7 @@ nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
}
static void
-nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base)
+nvc0_gr_ctxctl_debug_unit(struct nvc0_gr_priv *priv, u32 base)
{
nv_error(priv, "%06x - done 0x%08x\n", base,
nv_rd32(priv, base + 0x400));
@@ -1022,18 +1022,18 @@ nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base)
}
void
-nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv)
+nvc0_gr_ctxctl_debug(struct nvc0_gr_priv *priv)
{
u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff;
u32 gpc;
- nvc0_graph_ctxctl_debug_unit(priv, 0x409000);
+ nvc0_gr_ctxctl_debug_unit(priv, 0x409000);
for (gpc = 0; gpc < gpcnr; gpc++)
- nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
+ nvc0_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
}
static void
-nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
+nvc0_gr_ctxctl_isr(struct nvc0_gr_priv *priv)
{
u32 stat = nv_rd32(priv, 0x409c18);
@@ -1059,26 +1059,26 @@ nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
if (stat & 0x00080000) {
nv_error(priv, "FECS watchdog timeout\n");
- nvc0_graph_ctxctl_debug(priv);
+ nvc0_gr_ctxctl_debug(priv);
nv_wr32(priv, 0x409c20, 0x00080000);
stat &= ~0x00080000;
}
if (stat) {
nv_error(priv, "FECS 0x%08x\n", stat);
- nvc0_graph_ctxctl_debug(priv);
+ nvc0_gr_ctxctl_debug(priv);
nv_wr32(priv, 0x409c20, stat);
}
}
static void
-nvc0_graph_intr(struct nouveau_subdev *subdev)
+nvc0_gr_intr(struct nouveau_subdev *subdev)
{
struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
struct nouveau_engine *engine = nv_engine(subdev);
struct nouveau_object *engctx;
struct nouveau_handle *handle;
- struct nvc0_graph_priv *priv = (void *)subdev;
+ struct nvc0_gr_priv *priv = (void *)subdev;
u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff;
u32 stat = nv_rd32(priv, 0x400100);
u32 addr = nv_rd32(priv, 0x400704);
@@ -1127,13 +1127,13 @@ nvc0_graph_intr(struct nouveau_subdev *subdev)
if (stat & 0x00200000) {
nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
nouveau_client_name(engctx));
- nvc0_graph_trap_intr(priv);
+ nvc0_gr_trap_intr(priv);
nv_wr32(priv, 0x400100, 0x00200000);
stat &= ~0x00200000;
}
if (stat & 0x00080000) {
- nvc0_graph_ctxctl_isr(priv);
+ nvc0_gr_ctxctl_isr(priv);
nv_wr32(priv, 0x400100, 0x00080000);
stat &= ~0x00080000;
}
@@ -1148,8 +1148,8 @@ nvc0_graph_intr(struct nouveau_subdev *subdev)
}
void
-nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base,
- struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
+nvc0_gr_init_fw(struct nvc0_gr_priv *priv, u32 fuc_base,
+ struct nvc0_gr_fuc *code, struct nvc0_gr_fuc *data)
{
int i;
@@ -1170,12 +1170,12 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base,
}
static void
-nvc0_graph_init_csdata(struct nvc0_graph_priv *priv,
- const struct nvc0_graph_pack *pack,
+nvc0_gr_init_csdata(struct nvc0_gr_priv *priv,
+ const struct nvc0_gr_pack *pack,
u32 falcon, u32 starstar, u32 base)
{
- const struct nvc0_graph_pack *iter;
- const struct nvc0_graph_init *init;
+ const struct nvc0_gr_pack *iter;
+ const struct nvc0_gr_init *init;
u32 addr = ~0, prev = ~0, xfer = 0;
u32 star, temp;
@@ -1211,18 +1211,18 @@ nvc0_graph_init_csdata(struct nvc0_graph_priv *priv,
}
int
-nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
+nvc0_gr_init_ctxctl(struct nvc0_gr_priv *priv)
{
- struct nvc0_graph_oclass *oclass = (void *)nv_object(priv)->oclass;
+ struct nvc0_gr_oclass *oclass = (void *)nv_object(priv)->oclass;
struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
int i;
if (priv->firmware) {
/* load fuc microcode */
nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
- nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c,
+ nvc0_gr_init_fw(priv, 0x409000, &priv->fuc409c,
&priv->fuc409d);
- nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac,
+ nvc0_gr_init_fw(priv, 0x41a000, &priv->fuc41ac,
&priv->fuc41ad);
nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
@@ -1337,17 +1337,17 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
/* load register lists */
- nvc0_graph_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000);
- nvc0_graph_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000);
- nvc0_graph_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800);
- nvc0_graph_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00);
+ nvc0_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000);
+ nvc0_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000);
+ nvc0_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800);
+ nvc0_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00);
/* start HUB ucode running, it'll init the GPCs */
nv_wr32(priv, 0x40910c, 0x00000000);
nv_wr32(priv, 0x409100, 0x00000002);
if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
nv_error(priv, "HUB_INIT timed out\n");
- nvc0_graph_ctxctl_debug(priv);
+ nvc0_gr_ctxctl_debug(priv);
return -EBUSY;
}
@@ -1364,17 +1364,17 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
}
int
-nvc0_graph_init(struct nouveau_object *object)
+nvc0_gr_init(struct nouveau_object *object)
{
- struct nvc0_graph_oclass *oclass = (void *)object->oclass;
- struct nvc0_graph_priv *priv = (void *)object;
+ struct nvc0_gr_oclass *oclass = (void *)object->oclass;
+ struct nvc0_gr_priv *priv = (void *)object;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, rop;
int ret, i;
- ret = nouveau_graph_init(&priv->base);
+ ret = nouveau_gr_init(&priv->base);
if (ret)
return ret;
@@ -1387,7 +1387,7 @@ nvc0_graph_init(struct nouveau_object *object)
nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
- nvc0_graph_mmio(priv, oclass->mmio);
+ nvc0_gr_mmio(priv, oclass->mmio);
memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
@@ -1470,21 +1470,21 @@ nvc0_graph_init(struct nouveau_object *object)
nv_wr32(priv, 0x400054, 0x34ce3464);
- nvc0_graph_zbc_init(priv);
+ nvc0_gr_zbc_init(priv);
- return nvc0_graph_init_ctxctl(priv);
+ return nvc0_gr_init_ctxctl(priv);
}
static void
-nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc)
+nvc0_gr_dtor_fw(struct nvc0_gr_fuc *fuc)
{
kfree(fuc->data);
fuc->data = NULL;
}
int
-nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname,
- struct nvc0_graph_fuc *fuc)
+nvc0_gr_ctor_fw(struct nvc0_gr_priv *priv, const char *fwname,
+ struct nvc0_gr_fuc *fuc)
{
struct nouveau_device *device = nv_device(priv);
const struct firmware *fw;
@@ -1509,31 +1509,31 @@ nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname,
}
void
-nvc0_graph_dtor(struct nouveau_object *object)
+nvc0_gr_dtor(struct nouveau_object *object)
{
- struct nvc0_graph_priv *priv = (void *)object;
+ struct nvc0_gr_priv *priv = (void *)object;
kfree(priv->data);
- nvc0_graph_dtor_fw(&priv->fuc409c);
- nvc0_graph_dtor_fw(&priv->fuc409d);
- nvc0_graph_dtor_fw(&priv->fuc41ac);
- nvc0_graph_dtor_fw(&priv->fuc41ad);
+ nvc0_gr_dtor_fw(&priv->fuc409c);
+ nvc0_gr_dtor_fw(&priv->fuc409d);
+ nvc0_gr_dtor_fw(&priv->fuc41ac);
+ nvc0_gr_dtor_fw(&priv->fuc41ad);
nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
- nouveau_graph_destroy(&priv->base);
+ nouveau_gr_destroy(&priv->base);
}
int
-nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvc0_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *bclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvc0_graph_oclass *oclass = (void *)bclass;
+ struct nvc0_gr_oclass *oclass = (void *)bclass;
struct nouveau_device *device = nv_device(parent);
- struct nvc0_graph_priv *priv;
+ struct nvc0_gr_priv *priv;
bool use_ext_fw, enable;
int ret, i, j;
@@ -1541,22 +1541,22 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
oclass->fecs.ucode == NULL);
enable = use_ext_fw || oclass->fecs.ucode != NULL;
- ret = nouveau_graph_create(parent, engine, bclass, enable, &priv);
+ ret = nouveau_gr_create(parent, engine, bclass, enable, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x08001000;
- nv_subdev(priv)->intr = nvc0_graph_intr;
+ nv_subdev(priv)->intr = nvc0_gr_intr;
- priv->base.units = nvc0_graph_units;
+ priv->base.units = nvc0_gr_units;
if (use_ext_fw) {
nv_info(priv, "using external firmware\n");
- if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
- nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
- nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
- nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
+ if (nvc0_gr_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
+ nvc0_gr_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
+ nvc0_gr_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
+ nvc0_gr_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
return -ENODEV;
priv->firmware = true;
}
@@ -1632,8 +1632,8 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
#include "fuc/hubnvc0.fuc3.h"
-struct nvc0_graph_ucode
-nvc0_graph_fecs_ucode = {
+struct nvc0_gr_ucode
+nvc0_gr_fecs_ucode = {
.code.data = nvc0_grhub_code,
.code.size = sizeof(nvc0_grhub_code),
.data.data = nvc0_grhub_data,
@@ -1642,8 +1642,8 @@ nvc0_graph_fecs_ucode = {
#include "fuc/gpcnvc0.fuc3.h"
-struct nvc0_graph_ucode
-nvc0_graph_gpccs_ucode = {
+struct nvc0_gr_ucode
+nvc0_gr_gpccs_ucode = {
.code.data = nvc0_grgpc_code,
.code.size = sizeof(nvc0_grgpc_code),
.data.data = nvc0_grgpc_data,
@@ -1651,17 +1651,17 @@ nvc0_graph_gpccs_ucode = {
};
struct nouveau_oclass *
-nvc0_graph_oclass = &(struct nvc0_graph_oclass) {
+nvc0_gr_oclass = &(struct nvc0_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_ctor,
- .dtor = nvc0_graph_dtor,
- .init = nvc0_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nvc0_gr_ctor,
+ .dtor = nvc0_gr_dtor,
+ .init = nvc0_gr_init,
+ .fini = _nouveau_gr_fini,
},
.cclass = &nvc0_grctx_oclass,
- .sclass = nvc0_graph_sclass,
- .mmio = nvc0_graph_pack_mmio,
- .fecs.ucode = &nvc0_graph_fecs_ucode,
- .gpccs.ucode = &nvc0_graph_gpccs_ucode,
+ .sclass = nvc0_gr_sclass,
+ .mmio = nvc0_gr_pack_mmio,
+ .fecs.ucode = &nvc0_gr_fecs_ucode,
+ .gpccs.ucode = &nvc0_gr_gpccs_ucode,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
new file mode 100644
index 000000000000..f2818a2b6d68
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
@@ -0,0 +1,270 @@
+/*
+ * Copyright 2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#ifndef __NVC0_GR_H__
+#define __NVC0_GR_H__
+
+#include <core/client.h>
+#include <core/handle.h>
+#include <core/gpuobj.h>
+#include <core/option.h>
+
+#include <nvif/unpack.h>
+#include <nvif/class.h>
+
+#include <subdev/fb.h>
+#include <subdev/mmu.h>
+#include <subdev/bar.h>
+#include <subdev/timer.h>
+#include <subdev/mc.h>
+#include <subdev/ltc.h>
+
+#include <engine/fifo.h>
+#include <engine/gr.h>
+
+#include "fuc/os.h"
+
+#define GPC_MAX 32
+#define TPC_MAX (GPC_MAX * 8)
+
+#define ROP_BCAST(r) (0x408800 + (r))
+#define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r))
+#define GPC_BCAST(r) (0x418000 + (r))
+#define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r))
+#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r))
+#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
+
+struct nvc0_gr_data {
+ u32 size;
+ u32 align;
+ u32 access;
+};
+
+struct nvc0_gr_mmio {
+ u32 addr;
+ u32 data;
+ u32 shift;
+ int buffer;
+};
+
+struct nvc0_gr_fuc {
+ u32 *data;
+ u32 size;
+};
+
+struct nvc0_gr_zbc_color {
+ u32 format;
+ u32 ds[4];
+ u32 l2[4];
+};
+
+struct nvc0_gr_zbc_depth {
+ u32 format;
+ u32 ds;
+ u32 l2;
+};
+
+struct nvc0_gr_priv {
+ struct nouveau_gr base;
+
+ struct nvc0_gr_fuc fuc409c;
+ struct nvc0_gr_fuc fuc409d;
+ struct nvc0_gr_fuc fuc41ac;
+ struct nvc0_gr_fuc fuc41ad;
+ bool firmware;
+
+ struct nvc0_gr_zbc_color zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT];
+ struct nvc0_gr_zbc_depth zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT];
+
+ u8 rop_nr;
+ u8 gpc_nr;
+ u8 tpc_nr[GPC_MAX];
+ u8 tpc_total;
+ u8 ppc_nr[GPC_MAX];
+ u8 ppc_tpc_nr[GPC_MAX][4];
+
+ struct nouveau_gpuobj *unk4188b4;
+ struct nouveau_gpuobj *unk4188b8;
+
+ struct nvc0_gr_data mmio_data[4];
+ struct nvc0_gr_mmio mmio_list[4096/8];
+ u32 size;
+ u32 *data;
+
+ u8 magic_not_rop_nr;
+};
+
+struct nvc0_gr_chan {
+ struct nouveau_gr_chan base;
+
+ struct nouveau_gpuobj *mmio;
+ struct nouveau_vma mmio_vma;
+ int mmio_nr;
+ struct {
+ struct nouveau_gpuobj *mem;
+ struct nouveau_vma vma;
+ } data[4];
+};
+
+int nvc0_gr_context_ctor(struct nouveau_object *, struct nouveau_object *,
+ struct nouveau_oclass *, void *, u32,
+ struct nouveau_object **);
+void nvc0_gr_context_dtor(struct nouveau_object *);
+
+void nvc0_gr_ctxctl_debug(struct nvc0_gr_priv *);
+
+u64 nvc0_gr_units(struct nouveau_gr *);
+int nvc0_gr_ctor(struct nouveau_object *, struct nouveau_object *,
+ struct nouveau_oclass *, void *data, u32 size,
+ struct nouveau_object **);
+void nvc0_gr_dtor(struct nouveau_object *);
+int nvc0_gr_init(struct nouveau_object *);
+void nvc0_gr_zbc_init(struct nvc0_gr_priv *);
+
+int nve4_gr_fini(struct nouveau_object *, bool);
+int nve4_gr_init(struct nouveau_object *);
+
+int nvf0_gr_fini(struct nouveau_object *, bool);
+
+extern struct nouveau_ofuncs nvc0_fermi_ofuncs;
+
+extern struct nouveau_oclass nvc0_gr_sclass[];
+extern struct nouveau_omthds nvc0_gr_9097_omthds[];
+extern struct nouveau_omthds nvc0_gr_90c0_omthds[];
+extern struct nouveau_oclass nvc8_gr_sclass[];
+extern struct nouveau_oclass nvf0_gr_sclass[];
+
+struct nvc0_gr_init {
+ u32 addr;
+ u8 count;
+ u8 pitch;
+ u32 data;
+};
+
+struct nvc0_gr_pack {
+ const struct nvc0_gr_init *init;
+ u32 type;
+};
+
+#define pack_for_each_init(init, pack, head) \
+ for (pack = head; pack && pack->init; pack++) \
+ for (init = pack->init; init && init->count; init++)
+
+struct nvc0_gr_ucode {
+ struct nvc0_gr_fuc code;
+ struct nvc0_gr_fuc data;
+};
+
+extern struct nvc0_gr_ucode nvc0_gr_fecs_ucode;
+extern struct nvc0_gr_ucode nvc0_gr_gpccs_ucode;
+
+extern struct nvc0_gr_ucode nvf0_gr_fecs_ucode;
+extern struct nvc0_gr_ucode nvf0_gr_gpccs_ucode;
+
+struct nvc0_gr_oclass {
+ struct nouveau_oclass base;
+ struct nouveau_oclass **cclass;
+ struct nouveau_oclass *sclass;
+ const struct nvc0_gr_pack *mmio;
+ struct {
+ struct nvc0_gr_ucode *ucode;
+ } fecs;
+ struct {
+ struct nvc0_gr_ucode *ucode;
+ } gpccs;
+ int ppc_nr;
+};
+
+void nvc0_gr_mmio(struct nvc0_gr_priv *, const struct nvc0_gr_pack *);
+void nvc0_gr_icmd(struct nvc0_gr_priv *, const struct nvc0_gr_pack *);
+void nvc0_gr_mthd(struct nvc0_gr_priv *, const struct nvc0_gr_pack *);
+int nvc0_gr_init_ctxctl(struct nvc0_gr_priv *);
+
+/* register init value lists */
+
+extern const struct nvc0_gr_init nvc0_gr_init_main_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_fe_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_pri_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_rstr2d_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_pd_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_ds_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_scc_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_prop_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_gpc_unk_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_setup_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_crstr_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_setup_1[];
+extern const struct nvc0_gr_init nvc0_gr_init_zcull_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_gpm_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_gpc_unk_1[];
+extern const struct nvc0_gr_init nvc0_gr_init_gcc_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_tpccs_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_tex_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_pe_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_l1c_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_wwdx_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_tpccs_1[];
+extern const struct nvc0_gr_init nvc0_gr_init_mpc_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_be_0[];
+extern const struct nvc0_gr_init nvc0_gr_init_fe_1[];
+extern const struct nvc0_gr_init nvc0_gr_init_pe_1[];
+
+extern const struct nvc0_gr_init nvc4_gr_init_ds_0[];
+extern const struct nvc0_gr_init nvc4_gr_init_tex_0[];
+extern const struct nvc0_gr_init nvc4_gr_init_sm_0[];
+
+extern const struct nvc0_gr_init nvc1_gr_init_gpc_unk_0[];
+extern const struct nvc0_gr_init nvc1_gr_init_setup_1[];
+
+extern const struct nvc0_gr_init nvd9_gr_init_pd_0[];
+extern const struct nvc0_gr_init nvd9_gr_init_ds_0[];
+extern const struct nvc0_gr_init nvd9_gr_init_prop_0[];
+extern const struct nvc0_gr_init nvd9_gr_init_gpm_0[];
+extern const struct nvc0_gr_init nvd9_gr_init_gpc_unk_1[];
+extern const struct nvc0_gr_init nvd9_gr_init_tex_0[];
+extern const struct nvc0_gr_init nvd9_gr_init_sm_0[];
+extern const struct nvc0_gr_init nvd9_gr_init_fe_1[];
+
+extern const struct nvc0_gr_init nvd7_gr_init_pes_0[];
+extern const struct nvc0_gr_init nvd7_gr_init_wwdx_0[];
+extern const struct nvc0_gr_init nvd7_gr_init_cbm_0[];
+
+extern const struct nvc0_gr_init nve4_gr_init_main_0[];
+extern const struct nvc0_gr_init nve4_gr_init_tpccs_0[];
+extern const struct nvc0_gr_init nve4_gr_init_pe_0[];
+extern const struct nvc0_gr_init nve4_gr_init_be_0[];
+extern const struct nvc0_gr_pack nve4_gr_pack_mmio[];
+
+extern const struct nvc0_gr_init nvf0_gr_init_fe_0[];
+extern const struct nvc0_gr_init nvf0_gr_init_ds_0[];
+extern const struct nvc0_gr_init nvf0_gr_init_sked_0[];
+extern const struct nvc0_gr_init nvf0_gr_init_cwd_0[];
+extern const struct nvc0_gr_init nvf0_gr_init_gpc_unk_1[];
+extern const struct nvc0_gr_init nvf0_gr_init_tex_0[];
+extern const struct nvc0_gr_init nvf0_gr_init_sm_0[];
+
+extern const struct nvc0_gr_init nv108_gr_init_gpc_unk_0[];
+
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c
similarity index 63%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc1.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c
index 93d58e5b82c2..4a70ea30bae9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc1.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c
@@ -30,12 +30,12 @@
******************************************************************************/
static struct nouveau_oclass
-nvc1_graph_sclass[] = {
+nvc1_gr_sclass[] = {
{ 0x902d, &nouveau_object_ofuncs },
{ 0x9039, &nouveau_object_ofuncs },
- { FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
- { FERMI_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
- { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+ { FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+ { FERMI_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+ { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
{}
};
@@ -43,8 +43,8 @@ nvc1_graph_sclass[] = {
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_graph_init
-nvc1_graph_init_gpc_unk_0[] = {
+const struct nvc0_gr_init
+nvc1_gr_init_gpc_unk_0[] = {
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x00000000 },
@@ -52,16 +52,16 @@ nvc1_graph_init_gpc_unk_0[] = {
{}
};
-const struct nvc0_graph_init
-nvc1_graph_init_setup_1[] = {
+const struct nvc0_gr_init
+nvc1_gr_init_setup_1[] = {
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
{ 0x4188d4, 1, 0x04, 0x00000001 },
{}
};
-static const struct nvc0_graph_init
-nvc1_graph_init_gpc_unk_1[] = {
+static const struct nvc0_gr_init
+nvc1_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000003 },
@@ -69,8 +69,8 @@ nvc1_graph_init_gpc_unk_1[] = {
{}
};
-static const struct nvc0_graph_init
-nvc1_graph_init_pe_0[] = {
+static const struct nvc0_gr_init
+nvc1_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419810, 1, 0x04, 0x00000000 },
{ 0x419814, 1, 0x04, 0x00000004 },
@@ -81,34 +81,34 @@ nvc1_graph_init_pe_0[] = {
{}
};
-static const struct nvc0_graph_pack
-nvc1_graph_pack_mmio[] = {
- { nvc0_graph_init_main_0 },
- { nvc0_graph_init_fe_0 },
- { nvc0_graph_init_pri_0 },
- { nvc0_graph_init_rstr2d_0 },
- { nvc0_graph_init_pd_0 },
- { nvc4_graph_init_ds_0 },
- { nvc0_graph_init_scc_0 },
- { nvc0_graph_init_prop_0 },
- { nvc1_graph_init_gpc_unk_0 },
- { nvc0_graph_init_setup_0 },
- { nvc0_graph_init_crstr_0 },
- { nvc1_graph_init_setup_1 },
- { nvc0_graph_init_zcull_0 },
- { nvc0_graph_init_gpm_0 },
- { nvc1_graph_init_gpc_unk_1 },
- { nvc0_graph_init_gcc_0 },
- { nvc0_graph_init_tpccs_0 },
- { nvc4_graph_init_tex_0 },
- { nvc1_graph_init_pe_0 },
- { nvc0_graph_init_l1c_0 },
- { nvc0_graph_init_wwdx_0 },
- { nvc0_graph_init_tpccs_1 },
- { nvc0_graph_init_mpc_0 },
- { nvc4_graph_init_sm_0 },
- { nvc0_graph_init_be_0 },
- { nvc0_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+nvc1_gr_pack_mmio[] = {
+ { nvc0_gr_init_main_0 },
+ { nvc0_gr_init_fe_0 },
+ { nvc0_gr_init_pri_0 },
+ { nvc0_gr_init_rstr2d_0 },
+ { nvc0_gr_init_pd_0 },
+ { nvc4_gr_init_ds_0 },
+ { nvc0_gr_init_scc_0 },
+ { nvc0_gr_init_prop_0 },
+ { nvc1_gr_init_gpc_unk_0 },
+ { nvc0_gr_init_setup_0 },
+ { nvc0_gr_init_crstr_0 },
+ { nvc1_gr_init_setup_1 },
+ { nvc0_gr_init_zcull_0 },
+ { nvc0_gr_init_gpm_0 },
+ { nvc1_gr_init_gpc_unk_1 },
+ { nvc0_gr_init_gcc_0 },
+ { nvc0_gr_init_tpccs_0 },
+ { nvc4_gr_init_tex_0 },
+ { nvc1_gr_init_pe_0 },
+ { nvc0_gr_init_l1c_0 },
+ { nvc0_gr_init_wwdx_0 },
+ { nvc0_gr_init_tpccs_1 },
+ { nvc0_gr_init_mpc_0 },
+ { nvc4_gr_init_sm_0 },
+ { nvc0_gr_init_be_0 },
+ { nvc0_gr_init_fe_1 },
{}
};
@@ -117,17 +117,17 @@ nvc1_graph_pack_mmio[] = {
******************************************************************************/
struct nouveau_oclass *
-nvc1_graph_oclass = &(struct nvc0_graph_oclass) {
+nvc1_gr_oclass = &(struct nvc0_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xc1),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_ctor,
- .dtor = nvc0_graph_dtor,
- .init = nvc0_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nvc0_gr_ctor,
+ .dtor = nvc0_gr_dtor,
+ .init = nvc0_gr_init,
+ .fini = _nouveau_gr_fini,
},
.cclass = &nvc1_grctx_oclass,
- .sclass = nvc1_graph_sclass,
- .mmio = nvc1_graph_pack_mmio,
- .fecs.ucode = &nvc0_graph_fecs_ucode,
- .gpccs.ucode = &nvc0_graph_gpccs_ucode,
+ .sclass = nvc1_gr_sclass,
+ .mmio = nvc1_gr_pack_mmio,
+ .fecs.ucode = &nvc0_gr_fecs_ucode,
+ .gpccs.ucode = &nvc0_gr_gpccs_ucode,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c
similarity index 67%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c
index e82e70c53132..0af6335efa50 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c
@@ -29,8 +29,8 @@
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_graph_init
-nvc4_graph_init_ds_0[] = {
+const struct nvc0_gr_init
+nvc4_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00002834 },
@@ -38,8 +38,8 @@ nvc4_graph_init_ds_0[] = {
{}
};
-const struct nvc0_graph_init
-nvc4_graph_init_tex_0[] = {
+const struct nvc0_gr_init
+nvc4_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -47,8 +47,8 @@ nvc4_graph_init_tex_0[] = {
{}
};
-static const struct nvc0_graph_init
-nvc4_graph_init_pe_0[] = {
+static const struct nvc0_gr_init
+nvc4_gr_init_pe_0[] = {
{ 0x41980c, 3, 0x04, 0x00000000 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc5 },
@@ -57,8 +57,8 @@ nvc4_graph_init_pe_0[] = {
{}
};
-const struct nvc0_graph_init
-nvc4_graph_init_sm_0[] = {
+const struct nvc0_gr_init
+nvc4_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@@ -76,34 +76,34 @@ nvc4_graph_init_sm_0[] = {
{}
};
-static const struct nvc0_graph_pack
-nvc4_graph_pack_mmio[] = {
- { nvc0_graph_init_main_0 },
- { nvc0_graph_init_fe_0 },
- { nvc0_graph_init_pri_0 },
- { nvc0_graph_init_rstr2d_0 },
- { nvc0_graph_init_pd_0 },
- { nvc4_graph_init_ds_0 },
- { nvc0_graph_init_scc_0 },
- { nvc0_graph_init_prop_0 },
- { nvc0_graph_init_gpc_unk_0 },
- { nvc0_graph_init_setup_0 },
- { nvc0_graph_init_crstr_0 },
- { nvc0_graph_init_setup_1 },
- { nvc0_graph_init_zcull_0 },
- { nvc0_graph_init_gpm_0 },
- { nvc0_graph_init_gpc_unk_1 },
- { nvc0_graph_init_gcc_0 },
- { nvc0_graph_init_tpccs_0 },
- { nvc4_graph_init_tex_0 },
- { nvc4_graph_init_pe_0 },
- { nvc0_graph_init_l1c_0 },
- { nvc0_graph_init_wwdx_0 },
- { nvc0_graph_init_tpccs_1 },
- { nvc0_graph_init_mpc_0 },
- { nvc4_graph_init_sm_0 },
- { nvc0_graph_init_be_0 },
- { nvc0_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+nvc4_gr_pack_mmio[] = {
+ { nvc0_gr_init_main_0 },
+ { nvc0_gr_init_fe_0 },
+ { nvc0_gr_init_pri_0 },
+ { nvc0_gr_init_rstr2d_0 },
+ { nvc0_gr_init_pd_0 },
+ { nvc4_gr_init_ds_0 },
+ { nvc0_gr_init_scc_0 },
+ { nvc0_gr_init_prop_0 },
+ { nvc0_gr_init_gpc_unk_0 },
+ { nvc0_gr_init_setup_0 },
+ { nvc0_gr_init_crstr_0 },
+ { nvc0_gr_init_setup_1 },
+ { nvc0_gr_init_zcull_0 },
+ { nvc0_gr_init_gpm_0 },
+ { nvc0_gr_init_gpc_unk_1 },
+ { nvc0_gr_init_gcc_0 },
+ { nvc0_gr_init_tpccs_0 },
+ { nvc4_gr_init_tex_0 },
+ { nvc4_gr_init_pe_0 },
+ { nvc0_gr_init_l1c_0 },
+ { nvc0_gr_init_wwdx_0 },
+ { nvc0_gr_init_tpccs_1 },
+ { nvc0_gr_init_mpc_0 },
+ { nvc4_gr_init_sm_0 },
+ { nvc0_gr_init_be_0 },
+ { nvc0_gr_init_fe_1 },
{}
};
@@ -112,17 +112,17 @@ nvc4_graph_pack_mmio[] = {
******************************************************************************/
struct nouveau_oclass *
-nvc4_graph_oclass = &(struct nvc0_graph_oclass) {
+nvc4_gr_oclass = &(struct nvc0_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xc3),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_ctor,
- .dtor = nvc0_graph_dtor,
- .init = nvc0_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nvc0_gr_ctor,
+ .dtor = nvc0_gr_dtor,
+ .init = nvc0_gr_init,
+ .fini = _nouveau_gr_fini,
},
.cclass = &nvc4_grctx_oclass,
- .sclass = nvc0_graph_sclass,
- .mmio = nvc4_graph_pack_mmio,
- .fecs.ucode = &nvc0_graph_fecs_ucode,
- .gpccs.ucode = &nvc0_graph_gpccs_ucode,
+ .sclass = nvc0_gr_sclass,
+ .mmio = nvc4_gr_pack_mmio,
+ .fecs.ucode = &nvc0_gr_fecs_ucode,
+ .gpccs.ucode = &nvc0_gr_gpccs_ucode,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c
similarity index 63%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc8.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c
index 692e1eda0eb4..692ee30855fb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc8.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c
@@ -30,13 +30,13 @@
******************************************************************************/
struct nouveau_oclass
-nvc8_graph_sclass[] = {
+nvc8_gr_sclass[] = {
{ 0x902d, &nouveau_object_ofuncs },
{ 0x9039, &nouveau_object_ofuncs },
- { FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
- { FERMI_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
- { FERMI_C, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
- { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+ { FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+ { FERMI_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+ { FERMI_C, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+ { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
{}
};
@@ -44,8 +44,8 @@ nvc8_graph_sclass[] = {
* PGRAPH register lists
******************************************************************************/
-static const struct nvc0_graph_init
-nvc8_graph_init_sm_0[] = {
+static const struct nvc0_gr_init
+nvc8_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@@ -62,35 +62,35 @@ nvc8_graph_init_sm_0[] = {
{}
};
-static const struct nvc0_graph_pack
-nvc8_graph_pack_mmio[] = {
- { nvc0_graph_init_main_0 },
- { nvc0_graph_init_fe_0 },
- { nvc0_graph_init_pri_0 },
- { nvc0_graph_init_rstr2d_0 },
- { nvc0_graph_init_pd_0 },
- { nvc0_graph_init_ds_0 },
- { nvc0_graph_init_scc_0 },
- { nvc0_graph_init_prop_0 },
- { nvc0_graph_init_gpc_unk_0 },
- { nvc0_graph_init_setup_0 },
- { nvc0_graph_init_crstr_0 },
- { nvc1_graph_init_setup_1 },
- { nvc0_graph_init_zcull_0 },
- { nvc0_graph_init_gpm_0 },
- { nvc0_graph_init_gpc_unk_1 },
- { nvc0_graph_init_gcc_0 },
- { nvc0_graph_init_tpccs_0 },
- { nvc0_graph_init_tex_0 },
- { nvc0_graph_init_pe_0 },
- { nvc0_graph_init_l1c_0 },
- { nvc0_graph_init_wwdx_0 },
- { nvc0_graph_init_tpccs_1 },
- { nvc0_graph_init_mpc_0 },
- { nvc8_graph_init_sm_0 },
- { nvc0_graph_init_be_0 },
- { nvc0_graph_init_fe_1 },
- { nvc0_graph_init_pe_1 },
+static const struct nvc0_gr_pack
+nvc8_gr_pack_mmio[] = {
+ { nvc0_gr_init_main_0 },
+ { nvc0_gr_init_fe_0 },
+ { nvc0_gr_init_pri_0 },
+ { nvc0_gr_init_rstr2d_0 },
+ { nvc0_gr_init_pd_0 },
+ { nvc0_gr_init_ds_0 },
+ { nvc0_gr_init_scc_0 },
+ { nvc0_gr_init_prop_0 },
+ { nvc0_gr_init_gpc_unk_0 },
+ { nvc0_gr_init_setup_0 },
+ { nvc0_gr_init_crstr_0 },
+ { nvc1_gr_init_setup_1 },
+ { nvc0_gr_init_zcull_0 },
+ { nvc0_gr_init_gpm_0 },
+ { nvc0_gr_init_gpc_unk_1 },
+ { nvc0_gr_init_gcc_0 },
+ { nvc0_gr_init_tpccs_0 },
+ { nvc0_gr_init_tex_0 },
+ { nvc0_gr_init_pe_0 },
+ { nvc0_gr_init_l1c_0 },
+ { nvc0_gr_init_wwdx_0 },
+ { nvc0_gr_init_tpccs_1 },
+ { nvc0_gr_init_mpc_0 },
+ { nvc8_gr_init_sm_0 },
+ { nvc0_gr_init_be_0 },
+ { nvc0_gr_init_fe_1 },
+ { nvc0_gr_init_pe_1 },
{}
};
@@ -99,17 +99,17 @@ nvc8_graph_pack_mmio[] = {
******************************************************************************/
struct nouveau_oclass *
-nvc8_graph_oclass = &(struct nvc0_graph_oclass) {
+nvc8_gr_oclass = &(struct nvc0_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xc8),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_ctor,
- .dtor = nvc0_graph_dtor,
- .init = nvc0_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nvc0_gr_ctor,
+ .dtor = nvc0_gr_dtor,
+ .init = nvc0_gr_init,
+ .fini = _nouveau_gr_fini,
},
.cclass = &nvc8_grctx_oclass,
- .sclass = nvc8_graph_sclass,
- .mmio = nvc8_graph_pack_mmio,
- .fecs.ucode = &nvc0_graph_fecs_ucode,
- .gpccs.ucode = &nvc0_graph_gpccs_ucode,
+ .sclass = nvc8_gr_sclass,
+ .mmio = nvc8_gr_pack_mmio,
+ .fecs.ucode = &nvc0_gr_fecs_ucode,
+ .gpccs.ucode = &nvc0_gr_gpccs_ucode,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c
similarity index 64%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd7.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c
index 6f9f5ede5588..a2371a9f21de 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd7.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c
@@ -29,8 +29,8 @@
* PGRAPH register lists
******************************************************************************/
-static const struct nvc0_graph_init
-nvd7_graph_init_pe_0[] = {
+static const struct nvc0_gr_init
+nvd7_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc8 },
@@ -38,8 +38,8 @@ nvd7_graph_init_pe_0[] = {
{}
};
-const struct nvc0_graph_init
-nvd7_graph_init_pes_0[] = {
+const struct nvc0_gr_init
+nvd7_gr_init_pes_0[] = {
{ 0x41be04, 1, 0x04, 0x00000000 },
{ 0x41be08, 1, 0x04, 0x00000004 },
{ 0x41be0c, 1, 0x04, 0x00000000 },
@@ -48,50 +48,50 @@ nvd7_graph_init_pes_0[] = {
{}
};
-const struct nvc0_graph_init
-nvd7_graph_init_wwdx_0[] = {
+const struct nvc0_gr_init
+nvd7_gr_init_wwdx_0[] = {
{ 0x41bfd4, 1, 0x04, 0x00800000 },
{ 0x41bfdc, 1, 0x04, 0x00000000 },
{ 0x41bff8, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvd7_graph_init_cbm_0[] = {
+const struct nvc0_gr_init
+nvd7_gr_init_cbm_0[] = {
{ 0x41becc, 1, 0x04, 0x00000000 },
{ 0x41bee8, 2, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_graph_pack
-nvd7_graph_pack_mmio[] = {
- { nvc0_graph_init_main_0 },
- { nvc0_graph_init_fe_0 },
- { nvc0_graph_init_pri_0 },
- { nvc0_graph_init_rstr2d_0 },
- { nvd9_graph_init_pd_0 },
- { nvd9_graph_init_ds_0 },
- { nvc0_graph_init_scc_0 },
- { nvd9_graph_init_prop_0 },
- { nvc1_graph_init_gpc_unk_0 },
- { nvc0_graph_init_setup_0 },
- { nvc0_graph_init_crstr_0 },
- { nvc1_graph_init_setup_1 },
- { nvc0_graph_init_zcull_0 },
- { nvd9_graph_init_gpm_0 },
- { nvd9_graph_init_gpc_unk_1 },
- { nvc0_graph_init_gcc_0 },
- { nvc0_graph_init_tpccs_0 },
- { nvd9_graph_init_tex_0 },
- { nvd7_graph_init_pe_0 },
- { nvc0_graph_init_l1c_0 },
- { nvc0_graph_init_mpc_0 },
- { nvd9_graph_init_sm_0 },
- { nvd7_graph_init_pes_0 },
- { nvd7_graph_init_wwdx_0 },
- { nvd7_graph_init_cbm_0 },
- { nvc0_graph_init_be_0 },
- { nvd9_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+nvd7_gr_pack_mmio[] = {
+ { nvc0_gr_init_main_0 },
+ { nvc0_gr_init_fe_0 },
+ { nvc0_gr_init_pri_0 },
+ { nvc0_gr_init_rstr2d_0 },
+ { nvd9_gr_init_pd_0 },
+ { nvd9_gr_init_ds_0 },
+ { nvc0_gr_init_scc_0 },
+ { nvd9_gr_init_prop_0 },
+ { nvc1_gr_init_gpc_unk_0 },
+ { nvc0_gr_init_setup_0 },
+ { nvc0_gr_init_crstr_0 },
+ { nvc1_gr_init_setup_1 },
+ { nvc0_gr_init_zcull_0 },
+ { nvd9_gr_init_gpm_0 },
+ { nvd9_gr_init_gpc_unk_1 },
+ { nvc0_gr_init_gcc_0 },
+ { nvc0_gr_init_tpccs_0 },
+ { nvd9_gr_init_tex_0 },
+ { nvd7_gr_init_pe_0 },
+ { nvc0_gr_init_l1c_0 },
+ { nvc0_gr_init_mpc_0 },
+ { nvd9_gr_init_sm_0 },
+ { nvd7_gr_init_pes_0 },
+ { nvd7_gr_init_wwdx_0 },
+ { nvd7_gr_init_cbm_0 },
+ { nvc0_gr_init_be_0 },
+ { nvd9_gr_init_fe_1 },
{}
};
@@ -101,8 +101,8 @@ nvd7_graph_pack_mmio[] = {
#include "fuc/hubnvd7.fuc3.h"
-struct nvc0_graph_ucode
-nvd7_graph_fecs_ucode = {
+struct nvc0_gr_ucode
+nvd7_gr_fecs_ucode = {
.code.data = nvd7_grhub_code,
.code.size = sizeof(nvd7_grhub_code),
.data.data = nvd7_grhub_data,
@@ -111,8 +111,8 @@ nvd7_graph_fecs_ucode = {
#include "fuc/gpcnvd7.fuc3.h"
-struct nvc0_graph_ucode
-nvd7_graph_gpccs_ucode = {
+struct nvc0_gr_ucode
+nvd7_gr_gpccs_ucode = {
.code.data = nvd7_grgpc_code,
.code.size = sizeof(nvd7_grgpc_code),
.data.data = nvd7_grgpc_data,
@@ -120,18 +120,18 @@ nvd7_graph_gpccs_ucode = {
};
struct nouveau_oclass *
-nvd7_graph_oclass = &(struct nvc0_graph_oclass) {
+nvd7_gr_oclass = &(struct nvc0_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xd7),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_ctor,
- .dtor = nvc0_graph_dtor,
- .init = nvc0_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nvc0_gr_ctor,
+ .dtor = nvc0_gr_dtor,
+ .init = nvc0_gr_init,
+ .fini = _nouveau_gr_fini,
},
.cclass = &nvd7_grctx_oclass,
- .sclass = nvc8_graph_sclass,
- .mmio = nvd7_graph_pack_mmio,
- .fecs.ucode = &nvd7_graph_fecs_ucode,
- .gpccs.ucode = &nvd7_graph_gpccs_ucode,
+ .sclass = nvc8_gr_sclass,
+ .mmio = nvd7_gr_pack_mmio,
+ .fecs.ucode = &nvd7_gr_fecs_ucode,
+ .gpccs.ucode = &nvd7_gr_gpccs_ucode,
.ppc_nr = 1,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c
similarity index 68%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd9.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c
index 00fdf202fb92..25f5905a2b78 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvd9.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c
@@ -29,15 +29,15 @@
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_graph_init
-nvd9_graph_init_pd_0[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_pd_0[] = {
{ 0x406024, 1, 0x04, 0x00000000 },
{ 0x4064f0, 3, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvd9_graph_init_ds_0[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00002834 },
@@ -46,15 +46,15 @@ nvd9_graph_init_ds_0[] = {
{}
};
-const struct nvc0_graph_init
-nvd9_graph_init_prop_0[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_prop_0[] = {
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 3, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvd9_graph_init_gpm_0[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_gpm_0[] = {
{ 0x418c04, 1, 0x04, 0x00000000 },
{ 0x418c64, 2, 0x04, 0x00000000 },
{ 0x418c88, 1, 0x04, 0x00000000 },
@@ -62,8 +62,8 @@ nvd9_graph_init_gpm_0[] = {
{}
};
-const struct nvc0_graph_init
-nvd9_graph_init_gpc_unk_1[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000000 },
@@ -75,8 +75,8 @@ nvd9_graph_init_gpc_unk_1[] = {
{}
};
-const struct nvc0_graph_init
-nvd9_graph_init_tex_0[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -85,8 +85,8 @@ nvd9_graph_init_tex_0[] = {
{}
};
-static const struct nvc0_graph_init
-nvd9_graph_init_pe_0[] = {
+static const struct nvc0_gr_init
+nvd9_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419810, 1, 0x04, 0x00000000 },
{ 0x419814, 1, 0x04, 0x00000004 },
@@ -97,23 +97,23 @@ nvd9_graph_init_pe_0[] = {
{}
};
-static const struct nvc0_graph_init
-nvd9_graph_init_wwdx_0[] = {
+static const struct nvc0_gr_init
+nvd9_gr_init_wwdx_0[] = {
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{ 0x419bf8, 2, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_graph_init
-nvd9_graph_init_tpccs_1[] = {
+static const struct nvc0_gr_init
+nvd9_gr_init_tpccs_1[] = {
{ 0x419d2c, 1, 0x04, 0x00000000 },
{ 0x419d48, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvd9_graph_init_sm_0[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@@ -131,42 +131,42 @@ nvd9_graph_init_sm_0[] = {
{}
};
-const struct nvc0_graph_init
-nvd9_graph_init_fe_1[] = {
+const struct nvc0_gr_init
+nvd9_gr_init_fe_1[] = {
{ 0x40402c, 1, 0x04, 0x00000000 },
{ 0x4040f0, 1, 0x04, 0x00000000 },
{ 0x404174, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_graph_pack
-nvd9_graph_pack_mmio[] = {
- { nvc0_graph_init_main_0 },
- { nvc0_graph_init_fe_0 },
- { nvc0_graph_init_pri_0 },
- { nvc0_graph_init_rstr2d_0 },
- { nvd9_graph_init_pd_0 },
- { nvd9_graph_init_ds_0 },
- { nvc0_graph_init_scc_0 },
- { nvd9_graph_init_prop_0 },
- { nvc1_graph_init_gpc_unk_0 },
- { nvc0_graph_init_setup_0 },
- { nvc0_graph_init_crstr_0 },
- { nvc1_graph_init_setup_1 },
- { nvc0_graph_init_zcull_0 },
- { nvd9_graph_init_gpm_0 },
- { nvd9_graph_init_gpc_unk_1 },
- { nvc0_graph_init_gcc_0 },
- { nvc0_graph_init_tpccs_0 },
- { nvd9_graph_init_tex_0 },
- { nvd9_graph_init_pe_0 },
- { nvc0_graph_init_l1c_0 },
- { nvd9_graph_init_wwdx_0 },
- { nvd9_graph_init_tpccs_1 },
- { nvc0_graph_init_mpc_0 },
- { nvd9_graph_init_sm_0 },
- { nvc0_graph_init_be_0 },
- { nvd9_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+nvd9_gr_pack_mmio[] = {
+ { nvc0_gr_init_main_0 },
+ { nvc0_gr_init_fe_0 },
+ { nvc0_gr_init_pri_0 },
+ { nvc0_gr_init_rstr2d_0 },
+ { nvd9_gr_init_pd_0 },
+ { nvd9_gr_init_ds_0 },
+ { nvc0_gr_init_scc_0 },
+ { nvd9_gr_init_prop_0 },
+ { nvc1_gr_init_gpc_unk_0 },
+ { nvc0_gr_init_setup_0 },
+ { nvc0_gr_init_crstr_0 },
+ { nvc1_gr_init_setup_1 },
+ { nvc0_gr_init_zcull_0 },
+ { nvd9_gr_init_gpm_0 },
+ { nvd9_gr_init_gpc_unk_1 },
+ { nvc0_gr_init_gcc_0 },
+ { nvc0_gr_init_tpccs_0 },
+ { nvd9_gr_init_tex_0 },
+ { nvd9_gr_init_pe_0 },
+ { nvc0_gr_init_l1c_0 },
+ { nvd9_gr_init_wwdx_0 },
+ { nvd9_gr_init_tpccs_1 },
+ { nvc0_gr_init_mpc_0 },
+ { nvd9_gr_init_sm_0 },
+ { nvc0_gr_init_be_0 },
+ { nvd9_gr_init_fe_1 },
{}
};
@@ -175,17 +175,17 @@ nvd9_graph_pack_mmio[] = {
******************************************************************************/
struct nouveau_oclass *
-nvd9_graph_oclass = &(struct nvc0_graph_oclass) {
+nvd9_gr_oclass = &(struct nvc0_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xd9),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_ctor,
- .dtor = nvc0_graph_dtor,
- .init = nvc0_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nvc0_gr_ctor,
+ .dtor = nvc0_gr_dtor,
+ .init = nvc0_gr_init,
+ .fini = _nouveau_gr_fini,
},
.cclass = &nvd9_grctx_oclass,
- .sclass = nvc8_graph_sclass,
- .mmio = nvd9_graph_pack_mmio,
- .fecs.ucode = &nvc0_graph_fecs_ucode,
- .gpccs.ucode = &nvc0_graph_gpccs_ucode,
+ .sclass = nvc8_gr_sclass,
+ .mmio = nvd9_gr_pack_mmio,
+ .fecs.ucode = &nvc0_gr_fecs_ucode,
+ .gpccs.ucode = &nvc0_gr_gpccs_ucode,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c
similarity index 78%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c
index 8e6b62c4706c..f03ef38e8157 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nve4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c
@@ -32,11 +32,11 @@
******************************************************************************/
static struct nouveau_oclass
-nve4_graph_sclass[] = {
+nve4_gr_sclass[] = {
{ 0x902d, &nouveau_object_ofuncs },
{ 0xa040, &nouveau_object_ofuncs },
- { KEPLER_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
- { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+ { KEPLER_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+ { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
{}
};
@@ -44,8 +44,8 @@ nve4_graph_sclass[] = {
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_graph_init
-nve4_graph_init_main_0[] = {
+const struct nvc0_gr_init
+nve4_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x0001ffe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
@@ -60,8 +60,8 @@ nve4_graph_init_main_0[] = {
{}
};
-static const struct nvc0_graph_init
-nve4_graph_init_ds_0[] = {
+static const struct nvc0_gr_init
+nve4_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x0000ff34 },
@@ -70,20 +70,20 @@ nve4_graph_init_ds_0[] = {
{}
};
-static const struct nvc0_graph_init
-nve4_graph_init_sked_0[] = {
+static const struct nvc0_gr_init
+nve4_gr_init_sked_0[] = {
{ 0x407010, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_graph_init
-nve4_graph_init_cwd_0[] = {
+static const struct nvc0_gr_init
+nve4_gr_init_cwd_0[] = {
{ 0x405b50, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_graph_init
-nve4_graph_init_gpc_unk_1[] = {
+static const struct nvc0_gr_init
+nve4_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000000 },
@@ -95,15 +95,15 @@ nve4_graph_init_gpc_unk_1[] = {
{}
};
-const struct nvc0_graph_init
-nve4_graph_init_tpccs_0[] = {
+const struct nvc0_gr_init
+nve4_gr_init_tpccs_0[] = {
{ 0x419d0c, 1, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{}
};
-const struct nvc0_graph_init
-nve4_graph_init_pe_0[] = {
+const struct nvc0_gr_init
+nve4_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x419850, 1, 0x04, 0x00000004 },
@@ -111,8 +111,8 @@ nve4_graph_init_pe_0[] = {
{}
};
-static const struct nvc0_graph_init
-nve4_graph_init_l1c_0[] = {
+static const struct nvc0_gr_init
+nve4_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
@@ -125,8 +125,8 @@ nve4_graph_init_l1c_0[] = {
{}
};
-static const struct nvc0_graph_init
-nve4_graph_init_sm_0[] = {
+static const struct nvc0_gr_init
+nve4_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
@@ -139,8 +139,8 @@ nve4_graph_init_sm_0[] = {
{}
};
-const struct nvc0_graph_init
-nve4_graph_init_be_0[] = {
+const struct nvc0_gr_init
+nve4_gr_init_be_0[] = {
{ 0x40880c, 1, 0x04, 0x00000000 },
{ 0x408850, 1, 0x04, 0x00000004 },
{ 0x408910, 9, 0x04, 0x00000000 },
@@ -153,37 +153,37 @@ nve4_graph_init_be_0[] = {
{}
};
-const struct nvc0_graph_pack
-nve4_graph_pack_mmio[] = {
- { nve4_graph_init_main_0 },
- { nvc0_graph_init_fe_0 },
- { nvc0_graph_init_pri_0 },
- { nvc0_graph_init_rstr2d_0 },
- { nvd9_graph_init_pd_0 },
- { nve4_graph_init_ds_0 },
- { nvc0_graph_init_scc_0 },
- { nve4_graph_init_sked_0 },
- { nve4_graph_init_cwd_0 },
- { nvd9_graph_init_prop_0 },
- { nvc1_graph_init_gpc_unk_0 },
- { nvc0_graph_init_setup_0 },
- { nvc0_graph_init_crstr_0 },
- { nvc1_graph_init_setup_1 },
- { nvc0_graph_init_zcull_0 },
- { nvd9_graph_init_gpm_0 },
- { nve4_graph_init_gpc_unk_1 },
- { nvc0_graph_init_gcc_0 },
- { nve4_graph_init_tpccs_0 },
- { nvd9_graph_init_tex_0 },
- { nve4_graph_init_pe_0 },
- { nve4_graph_init_l1c_0 },
- { nvc0_graph_init_mpc_0 },
- { nve4_graph_init_sm_0 },
- { nvd7_graph_init_pes_0 },
- { nvd7_graph_init_wwdx_0 },
- { nvd7_graph_init_cbm_0 },
- { nve4_graph_init_be_0 },
- { nvc0_graph_init_fe_1 },
+const struct nvc0_gr_pack
+nve4_gr_pack_mmio[] = {
+ { nve4_gr_init_main_0 },
+ { nvc0_gr_init_fe_0 },
+ { nvc0_gr_init_pri_0 },
+ { nvc0_gr_init_rstr2d_0 },
+ { nvd9_gr_init_pd_0 },
+ { nve4_gr_init_ds_0 },
+ { nvc0_gr_init_scc_0 },
+ { nve4_gr_init_sked_0 },
+ { nve4_gr_init_cwd_0 },
+ { nvd9_gr_init_prop_0 },
+ { nvc1_gr_init_gpc_unk_0 },
+ { nvc0_gr_init_setup_0 },
+ { nvc0_gr_init_crstr_0 },
+ { nvc1_gr_init_setup_1 },
+ { nvc0_gr_init_zcull_0 },
+ { nvd9_gr_init_gpm_0 },
+ { nve4_gr_init_gpc_unk_1 },
+ { nvc0_gr_init_gcc_0 },
+ { nve4_gr_init_tpccs_0 },
+ { nvd9_gr_init_tex_0 },
+ { nve4_gr_init_pe_0 },
+ { nve4_gr_init_l1c_0 },
+ { nvc0_gr_init_mpc_0 },
+ { nve4_gr_init_sm_0 },
+ { nvd7_gr_init_pes_0 },
+ { nvd7_gr_init_wwdx_0 },
+ { nvd7_gr_init_cbm_0 },
+ { nve4_gr_init_be_0 },
+ { nvc0_gr_init_fe_1 },
{}
};
@@ -192,10 +192,10 @@ nve4_graph_pack_mmio[] = {
******************************************************************************/
int
-nve4_graph_init(struct nouveau_object *object)
+nve4_gr_init(struct nouveau_object *object)
{
- struct nvc0_graph_oclass *oclass = (void *)object->oclass;
- struct nvc0_graph_priv *priv = (void *)object;
+ struct nvc0_gr_oclass *oclass = (void *)object->oclass;
+ struct nvc0_gr_priv *priv = (void *)object;
struct nouveau_pmu *pmu = nouveau_pmu(priv);
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
u32 data[TPC_MAX / 8] = {};
@@ -206,7 +206,7 @@ nve4_graph_init(struct nouveau_object *object)
if (pmu)
pmu->pgob(pmu, false);
- ret = nouveau_graph_init(&priv->base);
+ ret = nouveau_gr_init(&priv->base);
if (ret)
return ret;
@@ -219,7 +219,7 @@ nve4_graph_init(struct nouveau_object *object)
nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
- nvc0_graph_mmio(priv, oclass->mmio);
+ nvc0_gr_mmio(priv, oclass->mmio);
nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
@@ -304,15 +304,15 @@ nve4_graph_init(struct nouveau_object *object)
nv_wr32(priv, 0x400054, 0x34ce3464);
- nvc0_graph_zbc_init(priv);
+ nvc0_gr_zbc_init(priv);
- return nvc0_graph_init_ctxctl(priv);
+ return nvc0_gr_init_ctxctl(priv);
}
#include "fuc/hubnve0.fuc3.h"
-static struct nvc0_graph_ucode
-nve4_graph_fecs_ucode = {
+static struct nvc0_gr_ucode
+nve4_gr_fecs_ucode = {
.code.data = nve0_grhub_code,
.code.size = sizeof(nve0_grhub_code),
.data.data = nve0_grhub_data,
@@ -321,8 +321,8 @@ nve4_graph_fecs_ucode = {
#include "fuc/gpcnve0.fuc3.h"
-static struct nvc0_graph_ucode
-nve4_graph_gpccs_ucode = {
+static struct nvc0_gr_ucode
+nve4_gr_gpccs_ucode = {
.code.data = nve0_grgpc_code,
.code.size = sizeof(nve0_grgpc_code),
.data.data = nve0_grgpc_data,
@@ -330,18 +330,18 @@ nve4_graph_gpccs_ucode = {
};
struct nouveau_oclass *
-nve4_graph_oclass = &(struct nvc0_graph_oclass) {
+nve4_gr_oclass = &(struct nvc0_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xe4),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_ctor,
- .dtor = nvc0_graph_dtor,
- .init = nve4_graph_init,
- .fini = _nouveau_graph_fini,
+ .ctor = nvc0_gr_ctor,
+ .dtor = nvc0_gr_dtor,
+ .init = nve4_gr_init,
+ .fini = _nouveau_gr_fini,
},
.cclass = &nve4_grctx_oclass,
- .sclass = nve4_graph_sclass,
- .mmio = nve4_graph_pack_mmio,
- .fecs.ucode = &nve4_graph_fecs_ucode,
- .gpccs.ucode = &nve4_graph_gpccs_ucode,
+ .sclass = nve4_gr_sclass,
+ .mmio = nve4_gr_pack_mmio,
+ .fecs.ucode = &nve4_gr_fecs_ucode,
+ .gpccs.ucode = &nve4_gr_gpccs_ucode,
.ppc_nr = 1,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c
similarity index 71%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/nvf0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c
index 73f77fa04a62..84d4456503c2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvf0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c
@@ -30,11 +30,11 @@
******************************************************************************/
struct nouveau_oclass
-nvf0_graph_sclass[] = {
+nvf0_gr_sclass[] = {
{ 0x902d, &nouveau_object_ofuncs },
{ 0xa140, &nouveau_object_ofuncs },
- { KEPLER_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
- { KEPLER_COMPUTE_B, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+ { KEPLER_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+ { KEPLER_COMPUTE_B, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
{}
};
@@ -42,16 +42,16 @@ nvf0_graph_sclass[] = {
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_graph_init
-nvf0_graph_init_fe_0[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_fe_0[] = {
{ 0x40415c, 1, 0x04, 0x00000000 },
{ 0x404170, 1, 0x04, 0x00000000 },
{ 0x4041b4, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvf0_graph_init_ds_0[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x0000ff00 },
@@ -60,23 +60,23 @@ nvf0_graph_init_ds_0[] = {
{}
};
-const struct nvc0_graph_init
-nvf0_graph_init_sked_0[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_sked_0[] = {
{ 0x407010, 1, 0x04, 0x00000000 },
{ 0x407040, 1, 0x04, 0x80440424 },
{ 0x407048, 1, 0x04, 0x0000000a },
{}
};
-const struct nvc0_graph_init
-nvf0_graph_init_cwd_0[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_cwd_0[] = {
{ 0x405b44, 1, 0x04, 0x00000000 },
{ 0x405b50, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_graph_init
-nvf0_graph_init_gpc_unk_1[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000400 },
@@ -88,8 +88,8 @@ nvf0_graph_init_gpc_unk_1[] = {
{}
};
-const struct nvc0_graph_init
-nvf0_graph_init_tex_0[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -100,8 +100,8 @@ nvf0_graph_init_tex_0[] = {
{}
};
-static const struct nvc0_graph_init
-nvf0_graph_init_l1c_0[] = {
+static const struct nvc0_gr_init
+nvf0_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
@@ -115,8 +115,8 @@ nvf0_graph_init_l1c_0[] = {
{}
};
-const struct nvc0_graph_init
-nvf0_graph_init_sm_0[] = {
+const struct nvc0_gr_init
+nvf0_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000080 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
@@ -132,37 +132,37 @@ nvf0_graph_init_sm_0[] = {
{}
};
-static const struct nvc0_graph_pack
-nvf0_graph_pack_mmio[] = {
- { nve4_graph_init_main_0 },
- { nvf0_graph_init_fe_0 },
- { nvc0_graph_init_pri_0 },
- { nvc0_graph_init_rstr2d_0 },
- { nvd9_graph_init_pd_0 },
- { nvf0_graph_init_ds_0 },
- { nvc0_graph_init_scc_0 },
- { nvf0_graph_init_sked_0 },
- { nvf0_graph_init_cwd_0 },
- { nvd9_graph_init_prop_0 },
- { nvc1_graph_init_gpc_unk_0 },
- { nvc0_graph_init_setup_0 },
- { nvc0_graph_init_crstr_0 },
- { nvc1_graph_init_setup_1 },
- { nvc0_graph_init_zcull_0 },
- { nvd9_graph_init_gpm_0 },
- { nvf0_graph_init_gpc_unk_1 },
- { nvc0_graph_init_gcc_0 },
- { nve4_graph_init_tpccs_0 },
- { nvf0_graph_init_tex_0 },
- { nve4_graph_init_pe_0 },
- { nvf0_graph_init_l1c_0 },
- { nvc0_graph_init_mpc_0 },
- { nvf0_graph_init_sm_0 },
- { nvd7_graph_init_pes_0 },
- { nvd7_graph_init_wwdx_0 },
- { nvd7_graph_init_cbm_0 },
- { nve4_graph_init_be_0 },
- { nvc0_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+nvf0_gr_pack_mmio[] = {
+ { nve4_gr_init_main_0 },
+ { nvf0_gr_init_fe_0 },
+ { nvc0_gr_init_pri_0 },
+ { nvc0_gr_init_rstr2d_0 },
+ { nvd9_gr_init_pd_0 },
+ { nvf0_gr_init_ds_0 },
+ { nvc0_gr_init_scc_0 },
+ { nvf0_gr_init_sked_0 },
+ { nvf0_gr_init_cwd_0 },
+ { nvd9_gr_init_prop_0 },
+ { nvc1_gr_init_gpc_unk_0 },
+ { nvc0_gr_init_setup_0 },
+ { nvc0_gr_init_crstr_0 },
+ { nvc1_gr_init_setup_1 },
+ { nvc0_gr_init_zcull_0 },
+ { nvd9_gr_init_gpm_0 },
+ { nvf0_gr_init_gpc_unk_1 },
+ { nvc0_gr_init_gcc_0 },
+ { nve4_gr_init_tpccs_0 },
+ { nvf0_gr_init_tex_0 },
+ { nve4_gr_init_pe_0 },
+ { nvf0_gr_init_l1c_0 },
+ { nvc0_gr_init_mpc_0 },
+ { nvf0_gr_init_sm_0 },
+ { nvd7_gr_init_pes_0 },
+ { nvd7_gr_init_wwdx_0 },
+ { nvd7_gr_init_cbm_0 },
+ { nve4_gr_init_be_0 },
+ { nvc0_gr_init_fe_1 },
{}
};
@@ -171,9 +171,9 @@ nvf0_graph_pack_mmio[] = {
******************************************************************************/
int
-nvf0_graph_fini(struct nouveau_object *object, bool suspend)
+nvf0_gr_fini(struct nouveau_object *object, bool suspend)
{
- struct nvc0_graph_priv *priv = (void *)object;
+ struct nvc0_gr_priv *priv = (void *)object;
static const struct {
u32 addr;
u32 data;
@@ -204,13 +204,13 @@ nvf0_graph_fini(struct nouveau_object *object, bool suspend)
nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
}
- return nouveau_graph_fini(&priv->base, suspend);
+ return nouveau_gr_fini(&priv->base, suspend);
}
#include "fuc/hubnvf0.fuc3.h"
-struct nvc0_graph_ucode
-nvf0_graph_fecs_ucode = {
+struct nvc0_gr_ucode
+nvf0_gr_fecs_ucode = {
.code.data = nvf0_grhub_code,
.code.size = sizeof(nvf0_grhub_code),
.data.data = nvf0_grhub_data,
@@ -219,8 +219,8 @@ nvf0_graph_fecs_ucode = {
#include "fuc/gpcnvf0.fuc3.h"
-struct nvc0_graph_ucode
-nvf0_graph_gpccs_ucode = {
+struct nvc0_gr_ucode
+nvf0_gr_gpccs_ucode = {
.code.data = nvf0_grgpc_code,
.code.size = sizeof(nvf0_grgpc_code),
.data.data = nvf0_grgpc_data,
@@ -228,18 +228,18 @@ nvf0_graph_gpccs_ucode = {
};
struct nouveau_oclass *
-nvf0_graph_oclass = &(struct nvc0_graph_oclass) {
+nvf0_gr_oclass = &(struct nvc0_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xf0),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_graph_ctor,
- .dtor = nvc0_graph_dtor,
- .init = nve4_graph_init,
- .fini = nvf0_graph_fini,
+ .ctor = nvc0_gr_ctor,
+ .dtor = nvc0_gr_dtor,
+ .init = nve4_gr_init,
+ .fini = nvf0_gr_fini,
},
.cclass = &nvf0_grctx_oclass,
- .sclass = nvf0_graph_sclass,
- .mmio = nvf0_graph_pack_mmio,
- .fecs.ucode = &nvf0_graph_fecs_ucode,
- .gpccs.ucode = &nvf0_graph_gpccs_ucode,
+ .sclass = nvf0_gr_sclass,
+ .mmio = nvf0_gr_pack_mmio,
+ .fecs.ucode = &nvf0_gr_fecs_ucode,
+ .gpccs.ucode = &nvf0_gr_gpccs_ucode,
.ppc_nr = 2,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/regs.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/graph/regs.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h
index fde8e24415e4..de69c5995edd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/regs.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h
@@ -1,5 +1,5 @@
-#ifndef __NOUVEAU_GRAPH_REGS_H__
-#define __NOUVEAU_GRAPH_REGS_H__
+#ifndef __NOUVEAU_GR_REGS_H__
+#define __NOUVEAU_GR_REGS_H__
#define NV04_PGRAPH_DEBUG_0 0x00400080
#define NV04_PGRAPH_DEBUG_1 0x00400084
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild
deleted file mode 100644
index fd56e979344b..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild
+++ /dev/null
@@ -1,36 +0,0 @@
-nvkm-y += nvkm/engine/graph/ctxnv40.o
-nvkm-y += nvkm/engine/graph/ctxnv50.o
-nvkm-y += nvkm/engine/graph/ctxnvc0.o
-nvkm-y += nvkm/engine/graph/ctxnvc1.o
-nvkm-y += nvkm/engine/graph/ctxnvc4.o
-nvkm-y += nvkm/engine/graph/ctxnvc8.o
-nvkm-y += nvkm/engine/graph/ctxnvd7.o
-nvkm-y += nvkm/engine/graph/ctxnvd9.o
-nvkm-y += nvkm/engine/graph/ctxnve4.o
-nvkm-y += nvkm/engine/graph/ctxgk20a.o
-nvkm-y += nvkm/engine/graph/ctxnvf0.o
-nvkm-y += nvkm/engine/graph/ctxgk110b.o
-nvkm-y += nvkm/engine/graph/ctxnv108.o
-nvkm-y += nvkm/engine/graph/ctxgm107.o
-nvkm-y += nvkm/engine/graph/nv04.o
-nvkm-y += nvkm/engine/graph/nv10.o
-nvkm-y += nvkm/engine/graph/nv20.o
-nvkm-y += nvkm/engine/graph/nv25.o
-nvkm-y += nvkm/engine/graph/nv2a.o
-nvkm-y += nvkm/engine/graph/nv30.o
-nvkm-y += nvkm/engine/graph/nv34.o
-nvkm-y += nvkm/engine/graph/nv35.o
-nvkm-y += nvkm/engine/graph/nv40.o
-nvkm-y += nvkm/engine/graph/nv50.o
-nvkm-y += nvkm/engine/graph/nvc0.o
-nvkm-y += nvkm/engine/graph/nvc1.o
-nvkm-y += nvkm/engine/graph/nvc4.o
-nvkm-y += nvkm/engine/graph/nvc8.o
-nvkm-y += nvkm/engine/graph/nvd7.o
-nvkm-y += nvkm/engine/graph/nvd9.o
-nvkm-y += nvkm/engine/graph/nve4.o
-nvkm-y += nvkm/engine/graph/gk20a.o
-nvkm-y += nvkm/engine/graph/nvf0.o
-nvkm-y += nvkm/engine/graph/gk110b.o
-nvkm-y += nvkm/engine/graph/nv108.o
-nvkm-y += nvkm/engine/graph/gm107.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.h
deleted file mode 100644
index c776cd715e33..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc0.h
+++ /dev/null
@@ -1,202 +0,0 @@
-#ifndef __NVKM_GRCTX_NVC0_H__
-#define __NVKM_GRCTX_NVC0_H__
-
-#include "nvc0.h"
-
-struct nvc0_grctx {
- struct nvc0_graph_priv *priv;
- struct nvc0_graph_data *data;
- struct nvc0_graph_mmio *mmio;
- int buffer_nr;
- u64 buffer[4];
- u64 addr;
-};
-
-int nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access);
-void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int);
-
-#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d))
-#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e))
-#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1)
-#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1)
-
-struct nvc0_grctx_oclass {
- struct nouveau_oclass base;
- /* main context generation function */
- void (*main)(struct nvc0_graph_priv *, struct nvc0_grctx *);
- /* context-specific modify-on-first-load list generation function */
- void (*unkn)(struct nvc0_graph_priv *);
- /* mmio context data */
- const struct nvc0_graph_pack *hub;
- const struct nvc0_graph_pack *gpc;
- const struct nvc0_graph_pack *zcull;
- const struct nvc0_graph_pack *tpc;
- const struct nvc0_graph_pack *ppc;
- /* indirect context data, generated with icmds/mthds */
- const struct nvc0_graph_pack *icmd;
- const struct nvc0_graph_pack *mthd;
- /* bundle circular buffer */
- void (*bundle)(struct nvc0_grctx *);
- u32 bundle_size;
- u32 bundle_min_gpm_fifo_depth;
- u32 bundle_token_limit;
- /* pagepool */
- void (*pagepool)(struct nvc0_grctx *);
- u32 pagepool_size;
- /* attribute(/alpha) circular buffer */
- void (*attrib)(struct nvc0_grctx *);
- u32 attrib_nr_max;
- u32 attrib_nr;
- u32 alpha_nr_max;
- u32 alpha_nr;
-};
-
-static inline const struct nvc0_grctx_oclass *
-nvc0_grctx_impl(struct nvc0_graph_priv *priv)
-{
- return (void *)nv_engine(priv)->cclass;
-}
-
-extern struct nouveau_oclass *nvc0_grctx_oclass;
-int nvc0_grctx_generate(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
-void nvc0_grctx_generate_bundle(struct nvc0_grctx *);
-void nvc0_grctx_generate_pagepool(struct nvc0_grctx *);
-void nvc0_grctx_generate_attrib(struct nvc0_grctx *);
-void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *);
-void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *);
-
-extern struct nouveau_oclass *nvc1_grctx_oclass;
-void nvc1_grctx_generate_attrib(struct nvc0_grctx *);
-void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *);
-
-extern struct nouveau_oclass *nvc4_grctx_oclass;
-extern struct nouveau_oclass *nvc8_grctx_oclass;
-
-extern struct nouveau_oclass *nvd7_grctx_oclass;
-void nvd7_grctx_generate_attrib(struct nvc0_grctx *);
-
-extern struct nouveau_oclass *nvd9_grctx_oclass;
-
-extern struct nouveau_oclass *nve4_grctx_oclass;
-extern struct nouveau_oclass *gk20a_grctx_oclass;
-void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
-void nve4_grctx_generate_bundle(struct nvc0_grctx *);
-void nve4_grctx_generate_pagepool(struct nvc0_grctx *);
-void nve4_grctx_generate_unkn(struct nvc0_graph_priv *);
-void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
-
-extern struct nouveau_oclass *nvf0_grctx_oclass;
-extern struct nouveau_oclass *gk110b_grctx_oclass;
-extern struct nouveau_oclass *nv108_grctx_oclass;
-extern struct nouveau_oclass *gm107_grctx_oclass;
-
-/* context init value lists */
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_icmd[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_mthd[];
-extern const struct nvc0_graph_init nvc0_grctx_init_902d_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_9039_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_90c0_0[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_hub[];
-extern const struct nvc0_graph_init nvc0_grctx_init_main_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_fe_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_pri_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_memfmt_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_rstr2d_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_scc_0[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_gpc[];
-extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_prop_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvc0_grctx_init_zcull_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_crstr_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_gpm_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_gcc_0[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_zcull[];
-
-extern const struct nvc0_graph_pack nvc0_grctx_pack_tpc[];
-extern const struct nvc0_graph_init nvc0_grctx_init_pe_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_wwdx_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_mpc_0[];
-extern const struct nvc0_graph_init nvc0_grctx_init_tpccs_0[];
-
-extern const struct nvc0_graph_init nvc4_grctx_init_tex_0[];
-extern const struct nvc0_graph_init nvc4_grctx_init_l1c_0[];
-extern const struct nvc0_graph_init nvc4_grctx_init_sm_0[];
-
-extern const struct nvc0_graph_init nvc1_grctx_init_9097_0[];
-
-extern const struct nvc0_graph_init nvc1_grctx_init_gpm_0[];
-
-extern const struct nvc0_graph_init nvc1_grctx_init_pe_0[];
-extern const struct nvc0_graph_init nvc1_grctx_init_wwdx_0[];
-extern const struct nvc0_graph_init nvc1_grctx_init_tpccs_0[];
-
-extern const struct nvc0_graph_init nvc8_grctx_init_9197_0[];
-extern const struct nvc0_graph_init nvc8_grctx_init_9297_0[];
-
-extern const struct nvc0_graph_pack nvd9_grctx_pack_icmd[];
-
-extern const struct nvc0_graph_pack nvd9_grctx_pack_mthd[];
-
-extern const struct nvc0_graph_init nvd9_grctx_init_fe_0[];
-extern const struct nvc0_graph_init nvd9_grctx_init_be_0[];
-
-extern const struct nvc0_graph_init nvd9_grctx_init_prop_0[];
-extern const struct nvc0_graph_init nvd9_grctx_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvd9_grctx_init_crstr_0[];
-
-extern const struct nvc0_graph_init nvd9_grctx_init_sm_0[];
-
-extern const struct nvc0_graph_init nvd7_grctx_init_pe_0[];
-
-extern const struct nvc0_graph_init nvd7_grctx_init_wwdx_0[];
-
-extern const struct nvc0_graph_init nve4_grctx_init_memfmt_0[];
-extern const struct nvc0_graph_init nve4_grctx_init_ds_0[];
-extern const struct nvc0_graph_init nve4_grctx_init_scc_0[];
-
-extern const struct nvc0_graph_init nve4_grctx_init_gpm_0[];
-
-extern const struct nvc0_graph_init nve4_grctx_init_pes_0[];
-
-extern const struct nvc0_graph_pack nve4_grctx_pack_hub[];
-extern const struct nvc0_graph_pack nve4_grctx_pack_gpc[];
-extern const struct nvc0_graph_pack nve4_grctx_pack_tpc[];
-extern const struct nvc0_graph_pack nve4_grctx_pack_ppc[];
-extern const struct nvc0_graph_pack nve4_grctx_pack_icmd[];
-extern const struct nvc0_graph_init nve4_grctx_init_a097_0[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_icmd[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_mthd[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_hub[];
-extern const struct nvc0_graph_init nvf0_grctx_init_pri_0[];
-extern const struct nvc0_graph_init nvf0_grctx_init_cwd_0[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_gpc[];
-extern const struct nvc0_graph_init nvf0_grctx_init_gpc_unk_2[];
-
-extern const struct nvc0_graph_init nvf0_grctx_init_tex_0[];
-extern const struct nvc0_graph_init nvf0_grctx_init_mpc_0[];
-extern const struct nvc0_graph_init nvf0_grctx_init_l1c_0[];
-
-extern const struct nvc0_graph_pack nvf0_grctx_pack_ppc[];
-
-extern const struct nvc0_graph_init nv108_grctx_init_rstr2d_0[];
-
-extern const struct nvc0_graph_init nv108_grctx_init_prop_0[];
-extern const struct nvc0_graph_init nv108_grctx_init_crstr_0[];
-
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.h
deleted file mode 100644
index 2bea7313e03f..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nv20.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __NV20_GRAPH_H__
-#define __NV20_GRAPH_H__
-
-#include <core/enum.h>
-
-#include <engine/graph.h>
-#include <engine/fifo.h>
-
-struct nv20_graph_priv {
- struct nouveau_graph base;
- struct nouveau_gpuobj *ctxtab;
-};
-
-struct nv20_graph_chan {
- struct nouveau_graph_chan base;
- int chid;
-};
-
-extern struct nouveau_oclass nv25_graph_sclass[];
-int nv20_graph_context_init(struct nouveau_object *);
-int nv20_graph_context_fini(struct nouveau_object *, bool);
-
-void nv20_graph_tile_prog(struct nouveau_engine *, int);
-void nv20_graph_intr(struct nouveau_subdev *);
-
-void nv20_graph_dtor(struct nouveau_object *);
-int nv20_graph_init(struct nouveau_object *);
-
-int nv30_graph_init(struct nouveau_object *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h
deleted file mode 100644
index 86b7735242e1..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/graph/nvc0.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifndef __NVC0_GRAPH_H__
-#define __NVC0_GRAPH_H__
-
-#include <core/client.h>
-#include <core/handle.h>
-#include <core/gpuobj.h>
-#include <core/option.h>
-
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/fb.h>
-#include <subdev/mmu.h>
-#include <subdev/bar.h>
-#include <subdev/timer.h>
-#include <subdev/mc.h>
-#include <subdev/ltc.h>
-
-#include <engine/fifo.h>
-#include <engine/graph.h>
-
-#include "fuc/os.h"
-
-#define GPC_MAX 32
-#define TPC_MAX (GPC_MAX * 8)
-
-#define ROP_BCAST(r) (0x408800 + (r))
-#define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r))
-#define GPC_BCAST(r) (0x418000 + (r))
-#define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r))
-#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r))
-#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
-
-struct nvc0_graph_data {
- u32 size;
- u32 align;
- u32 access;
-};
-
-struct nvc0_graph_mmio {
- u32 addr;
- u32 data;
- u32 shift;
- int buffer;
-};
-
-struct nvc0_graph_fuc {
- u32 *data;
- u32 size;
-};
-
-struct nvc0_graph_zbc_color {
- u32 format;
- u32 ds[4];
- u32 l2[4];
-};
-
-struct nvc0_graph_zbc_depth {
- u32 format;
- u32 ds;
- u32 l2;
-};
-
-struct nvc0_graph_priv {
- struct nouveau_graph base;
-
- struct nvc0_graph_fuc fuc409c;
- struct nvc0_graph_fuc fuc409d;
- struct nvc0_graph_fuc fuc41ac;
- struct nvc0_graph_fuc fuc41ad;
- bool firmware;
-
- struct nvc0_graph_zbc_color zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT];
- struct nvc0_graph_zbc_depth zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT];
-
- u8 rop_nr;
- u8 gpc_nr;
- u8 tpc_nr[GPC_MAX];
- u8 tpc_total;
- u8 ppc_nr[GPC_MAX];
- u8 ppc_tpc_nr[GPC_MAX][4];
-
- struct nouveau_gpuobj *unk4188b4;
- struct nouveau_gpuobj *unk4188b8;
-
- struct nvc0_graph_data mmio_data[4];
- struct nvc0_graph_mmio mmio_list[4096/8];
- u32 size;
- u32 *data;
-
- u8 magic_not_rop_nr;
-};
-
-struct nvc0_graph_chan {
- struct nouveau_graph_chan base;
-
- struct nouveau_gpuobj *mmio;
- struct nouveau_vma mmio_vma;
- int mmio_nr;
- struct {
- struct nouveau_gpuobj *mem;
- struct nouveau_vma vma;
- } data[4];
-};
-
-int nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nvc0_graph_context_dtor(struct nouveau_object *);
-
-void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *);
-
-u64 nvc0_graph_units(struct nouveau_graph *);
-int nvc0_graph_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *data, u32 size,
- struct nouveau_object **);
-void nvc0_graph_dtor(struct nouveau_object *);
-int nvc0_graph_init(struct nouveau_object *);
-void nvc0_graph_zbc_init(struct nvc0_graph_priv *);
-
-int nve4_graph_fini(struct nouveau_object *, bool);
-int nve4_graph_init(struct nouveau_object *);
-
-int nvf0_graph_fini(struct nouveau_object *, bool);
-
-extern struct nouveau_ofuncs nvc0_fermi_ofuncs;
-
-extern struct nouveau_oclass nvc0_graph_sclass[];
-extern struct nouveau_omthds nvc0_graph_9097_omthds[];
-extern struct nouveau_omthds nvc0_graph_90c0_omthds[];
-extern struct nouveau_oclass nvc8_graph_sclass[];
-extern struct nouveau_oclass nvf0_graph_sclass[];
-
-struct nvc0_graph_init {
- u32 addr;
- u8 count;
- u8 pitch;
- u32 data;
-};
-
-struct nvc0_graph_pack {
- const struct nvc0_graph_init *init;
- u32 type;
-};
-
-#define pack_for_each_init(init, pack, head) \
- for (pack = head; pack && pack->init; pack++) \
- for (init = pack->init; init && init->count; init++)
-
-struct nvc0_graph_ucode {
- struct nvc0_graph_fuc code;
- struct nvc0_graph_fuc data;
-};
-
-extern struct nvc0_graph_ucode nvc0_graph_fecs_ucode;
-extern struct nvc0_graph_ucode nvc0_graph_gpccs_ucode;
-
-extern struct nvc0_graph_ucode nvf0_graph_fecs_ucode;
-extern struct nvc0_graph_ucode nvf0_graph_gpccs_ucode;
-
-struct nvc0_graph_oclass {
- struct nouveau_oclass base;
- struct nouveau_oclass **cclass;
- struct nouveau_oclass *sclass;
- const struct nvc0_graph_pack *mmio;
- struct {
- struct nvc0_graph_ucode *ucode;
- } fecs;
- struct {
- struct nvc0_graph_ucode *ucode;
- } gpccs;
- int ppc_nr;
-};
-
-void nvc0_graph_mmio(struct nvc0_graph_priv *, const struct nvc0_graph_pack *);
-void nvc0_graph_icmd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *);
-void nvc0_graph_mthd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *);
-int nvc0_graph_init_ctxctl(struct nvc0_graph_priv *);
-
-/* register init value lists */
-
-extern const struct nvc0_graph_init nvc0_graph_init_main_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_fe_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_pri_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_rstr2d_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_pd_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_ds_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_scc_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_prop_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_gpc_unk_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_setup_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_crstr_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_setup_1[];
-extern const struct nvc0_graph_init nvc0_graph_init_zcull_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_gpm_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvc0_graph_init_gcc_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_tpccs_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_tex_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_pe_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_l1c_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_wwdx_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_tpccs_1[];
-extern const struct nvc0_graph_init nvc0_graph_init_mpc_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_be_0[];
-extern const struct nvc0_graph_init nvc0_graph_init_fe_1[];
-extern const struct nvc0_graph_init nvc0_graph_init_pe_1[];
-
-extern const struct nvc0_graph_init nvc4_graph_init_ds_0[];
-extern const struct nvc0_graph_init nvc4_graph_init_tex_0[];
-extern const struct nvc0_graph_init nvc4_graph_init_sm_0[];
-
-extern const struct nvc0_graph_init nvc1_graph_init_gpc_unk_0[];
-extern const struct nvc0_graph_init nvc1_graph_init_setup_1[];
-
-extern const struct nvc0_graph_init nvd9_graph_init_pd_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_ds_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_prop_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_gpm_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvd9_graph_init_tex_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_sm_0[];
-extern const struct nvc0_graph_init nvd9_graph_init_fe_1[];
-
-extern const struct nvc0_graph_init nvd7_graph_init_pes_0[];
-extern const struct nvc0_graph_init nvd7_graph_init_wwdx_0[];
-extern const struct nvc0_graph_init nvd7_graph_init_cbm_0[];
-
-extern const struct nvc0_graph_init nve4_graph_init_main_0[];
-extern const struct nvc0_graph_init nve4_graph_init_tpccs_0[];
-extern const struct nvc0_graph_init nve4_graph_init_pe_0[];
-extern const struct nvc0_graph_init nve4_graph_init_be_0[];
-extern const struct nvc0_graph_pack nve4_graph_pack_mmio[];
-
-extern const struct nvc0_graph_init nvf0_graph_init_fe_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_ds_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_sked_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_cwd_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_gpc_unk_1[];
-extern const struct nvc0_graph_init nvf0_graph_init_tex_0[];
-extern const struct nvc0_graph_init nvf0_graph_init_sm_0[];
-
-extern const struct nvc0_graph_init nv108_graph_init_gpc_unk_0[];
-
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
index 8803809f9fc5..f65bc796bcde 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
@@ -22,7 +22,7 @@
* Authors: Ben Skeggs
*/
-#include <engine/graph/nv40.h>
+#include <engine/gr/nv40.h>
#include "nv04.h"
@@ -73,12 +73,12 @@ nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
/* PRAMIN aperture maps over the end of vram, reserve enough space
* to fit graphics contexts for every channel, the magics come
- * from engine/graph/nv40.c
+ * from engine/gr/nv40.c
*/
vs = hweight8((nv_rd32(priv, 0x001540) & 0x0000ff00) >> 8);
if (device->chipset == 0x40) priv->base.reserved = 0x6aa0 * vs;
else if (device->chipset < 0x43) priv->base.reserved = 0x4f00 * vs;
- else if (nv44_graph_class(priv)) priv->base.reserved = 0x4980 * vs;
+ else if (nv44_gr_class(priv)) priv->base.reserved = 0x4980 * vs;
else priv->base.reserved = 0x4a40 * vs;
priv->base.reserved += 16 * 1024;
priv->base.reserved *= 32; /* per-channel */
From d5752b9b86fbfb8febd9d45ac4431325031e25e0 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 12:11:28 +1000
Subject: [PATCH 44/86] drm/nouveau/pm: rename from perfmon (no binary change)
Switch to NVIDIA's name for the device.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/core/device.h | 2 +-
.../drm/nouveau/include/nvkm/engine/perfmon.h | 38 --------
.../gpu/drm/nouveau/include/nvkm/engine/pm.h | 38 ++++++++
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 2 +-
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 4 +-
.../drm/nouveau/nvkm/engine/device/gm100.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv40.c | 34 +++----
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 30 +++---
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 20 ++--
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 +--
.../drm/nouveau/nvkm/engine/perfmon/Kbuild | 9 --
.../drm/nouveau/nvkm/engine/perfmon/priv.h | 91 -------------------
drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild | 9 ++
.../nvkm/engine/{perfmon => pm}/base.c | 40 ++++----
.../nvkm/engine/{perfmon => pm}/daemon.c | 12 +--
.../nvkm/engine/{perfmon => pm}/nv40.c | 44 ++++-----
.../nvkm/engine/{perfmon => pm}/nv40.h | 10 +-
.../nvkm/engine/{perfmon => pm}/nv50.c | 16 ++--
.../nvkm/engine/{perfmon => pm}/nv84.c | 16 ++--
.../nvkm/engine/{perfmon => pm}/nva3.c | 24 ++---
.../nvkm/engine/{perfmon => pm}/nvc0.c | 58 ++++++------
.../nvkm/engine/{perfmon => pm}/nvc0.h | 8 +-
.../nvkm/engine/{perfmon => pm}/nve0.c | 36 ++++----
.../nvkm/engine/{perfmon => pm}/nvf0.c | 24 ++---
drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h | 91 +++++++++++++++++++
25 files changed, 336 insertions(+), 336 deletions(-)
delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/perfmon.h
create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/perfmon/Kbuild
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/perfmon/priv.h
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild
rename drivers/gpu/drm/nouveau/nvkm/engine/{perfmon => pm}/base.c (91%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{perfmon => pm}/daemon.c (90%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{perfmon => pm}/nv40.c (77%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{perfmon => pm}/nv40.h (65%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{perfmon => pm}/nv50.c (89%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{perfmon => pm}/nv84.c (90%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{perfmon => pm}/nva3.c (84%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{perfmon => pm}/nvc0.c (75%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{perfmon => pm}/nvc0.h (55%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{perfmon => pm}/nve0.c (85%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{perfmon => pm}/nvf0.c (80%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 952e36cdb71c..3d87d3daa5a8 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -58,7 +58,7 @@ enum nv_subdev_type {
NVDEV_ENGINE_VIC,
NVDEV_ENGINE_VENC,
NVDEV_ENGINE_DISP,
- NVDEV_ENGINE_PERFMON,
+ NVDEV_ENGINE_PM,
NVDEV_ENGINE_MSVLD,
NVDEV_ENGINE_SEC,
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/perfmon.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/perfmon.h
deleted file mode 100644
index 251c8545ca58..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/perfmon.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef __NVKM_PERFMON_H__
-#define __NVKM_PERFMON_H__
-
-#include <core/device.h>
-#include <core/engine.h>
-#include <core/engctx.h>
-
-struct nouveau_perfdom;
-struct nouveau_perfctr;
-struct nouveau_perfmon {
- struct nouveau_engine base;
-
- struct nouveau_perfctx *context;
- void *profile_data;
-
- struct list_head domains;
- u32 sequence;
-
- /*XXX: temp for daemon backend */
- u32 pwr[8];
- u32 last;
-};
-
-static inline struct nouveau_perfmon *
-nouveau_perfmon(void *obj)
-{
- return (void *)nouveau_engine(obj, NVDEV_ENGINE_PERFMON);
-}
-
-extern struct nouveau_oclass *nv40_perfmon_oclass;
-extern struct nouveau_oclass *nv50_perfmon_oclass;
-extern struct nouveau_oclass *nv84_perfmon_oclass;
-extern struct nouveau_oclass *nva3_perfmon_oclass;
-extern struct nouveau_oclass nvc0_perfmon_oclass;
-extern struct nouveau_oclass nve0_perfmon_oclass;
-extern struct nouveau_oclass nvf0_perfmon_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
new file mode 100644
index 000000000000..c9ffe2c70746
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
@@ -0,0 +1,38 @@
+#ifndef __NVKM_PM_H__
+#define __NVKM_PM_H__
+
+#include <core/device.h>
+#include <core/engine.h>
+#include <core/engctx.h>
+
+struct nouveau_perfdom;
+struct nouveau_perfctr;
+struct nouveau_pm {
+ struct nouveau_engine base;
+
+ struct nouveau_perfctx *context;
+ void *profile_data;
+
+ struct list_head domains;
+ u32 sequence;
+
+ /*XXX: temp for daemon backend */
+ u32 pwr[8];
+ u32 last;
+};
+
+static inline struct nouveau_pm *
+nouveau_pm(void *obj)
+{
+ return (void *)nouveau_engine(obj, NVDEV_ENGINE_PM);
+}
+
+extern struct nouveau_oclass *nv40_pm_oclass;
+extern struct nouveau_oclass *nv50_pm_oclass;
+extern struct nouveau_oclass *nv84_pm_oclass;
+extern struct nouveau_oclass *nva3_pm_oclass;
+extern struct nouveau_oclass nvc0_pm_oclass;
+extern struct nouveau_oclass nve0_pm_oclass;
+extern struct nouveau_oclass nvf0_pm_oclass;
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
index 183475e2a924..16c3a91b7e4a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
@@ -11,7 +11,7 @@ include $(src)/nvkm/engine/fifo/Kbuild
include $(src)/nvkm/engine/gr/Kbuild
include $(src)/nvkm/engine/mpeg/Kbuild
include $(src)/nvkm/engine/msvld/Kbuild
-include $(src)/nvkm/engine/perfmon/Kbuild
+include $(src)/nvkm/engine/pm/Kbuild
include $(src)/nvkm/engine/ppp/Kbuild
include $(src)/nvkm/engine/sec/Kbuild
include $(src)/nvkm/engine/software/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index baad4ad22058..5b226cb04298 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -225,7 +225,7 @@ static const u64 disable_map[] = {
[NVDEV_SUBDEV_PMU] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_FUSE] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_V0_DISABLE_CORE,
- [NVDEV_ENGINE_PERFMON] = NV_DEVICE_V0_DISABLE_CORE,
+ [NVDEV_ENGINE_PM ] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_ENGINE_FIFO] = NV_DEVICE_V0_DISABLE_FIFO,
[NVDEV_ENGINE_SW] = NV_DEVICE_V0_DISABLE_FIFO,
[NVDEV_ENGINE_GR] = NV_DEVICE_V0_DISABLE_GR,
@@ -319,7 +319,7 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_FIFO) |
(1ULL << NVDEV_ENGINE_DISP) |
- (1ULL << NVDEV_ENGINE_PERFMON), &devobj);
+ (1ULL << NVDEV_ENGINE_PM ), &devobj);
*pobject = nv_object(devobj);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index e7289fd2da9b..2ea1dbcf641f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -53,7 +53,7 @@
#include <engine/msvld.h>
#include <engine/vp.h>
#include <engine/ppp.h>
-#include <engine/perfmon.h>
+#include <engine/pm.h>
int
gm100_identify(struct nouveau_device *device)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index 3b16fdc4c95e..cd859b081db4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -44,7 +44,7 @@
#include <engine/gr.h>
#include <engine/mpeg.h>
#include <engine/disp.h>
-#include <engine/perfmon.h>
+#include <engine/pm.h>
int
nv40_identify(struct nouveau_device *device)
@@ -71,7 +71,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x41:
device->cname = "NV41";
@@ -94,7 +94,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x42:
device->cname = "NV42";
@@ -117,7 +117,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x43:
device->cname = "NV43";
@@ -140,7 +140,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x45:
device->cname = "NV45";
@@ -163,7 +163,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x47:
device->cname = "G70";
@@ -186,7 +186,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x49:
device->cname = "G71";
@@ -209,7 +209,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4b:
device->cname = "G73";
@@ -232,7 +232,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x44:
device->cname = "NV44";
@@ -255,7 +255,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x46:
device->cname = "G72";
@@ -278,7 +278,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4a:
device->cname = "NV44A";
@@ -301,7 +301,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4c:
device->cname = "C61";
@@ -324,7 +324,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4e:
device->cname = "C51";
@@ -347,7 +347,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x63:
device->cname = "C73";
@@ -370,7 +370,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x67:
device->cname = "C67";
@@ -393,7 +393,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x68:
device->cname = "C68";
@@ -416,7 +416,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
default:
nv_fatal(device, "unknown Curie chipset\n");
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index a9788b4999c6..6e5ccb371372 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -54,7 +54,7 @@
#include <engine/ppp.h>
#include <engine/ce.h>
#include <engine/disp.h>
-#include <engine/perfmon.h>
+#include <engine/pm.h>
int
nv50_identify(struct nouveau_device *device)
@@ -84,7 +84,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
break;
case 0x84:
device->cname = "G84";
@@ -113,7 +113,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0x86:
device->cname = "G86";
@@ -142,7 +142,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0x92:
device->cname = "G92";
@@ -171,7 +171,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0x94:
device->cname = "G94";
@@ -200,7 +200,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0x96:
device->cname = "G96";
@@ -229,7 +229,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0x98:
device->cname = "G98";
@@ -258,7 +258,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0xa0:
device->cname = "G200";
@@ -287,7 +287,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0xaa:
device->cname = "MCP77/MCP78";
@@ -316,7 +316,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0xac:
device->cname = "MCP79/MCP7A";
@@ -345,7 +345,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0xa3:
device->cname = "GT215";
@@ -376,7 +376,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
break;
case 0xa5:
device->cname = "GT216";
@@ -406,7 +406,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
break;
case 0xa8:
device->cname = "GT218";
@@ -436,7 +436,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
break;
case 0xaf:
device->cname = "MCP89";
@@ -466,7 +466,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
break;
default:
nv_fatal(device, "unknown Tesla chipset\n");
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 1f93c9611f37..d159d2993043 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -53,7 +53,7 @@
#include <engine/ppp.h>
#include <engine/ce.h>
#include <engine/disp.h>
-#include <engine/perfmon.h>
+#include <engine/pm.h>
int
nvc0_identify(struct nouveau_device *device)
@@ -90,7 +90,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xc4:
device->cname = "GF104";
@@ -123,7 +123,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xc3:
device->cname = "GF106";
@@ -155,7 +155,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xce:
device->cname = "GF114";
@@ -188,7 +188,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xcf:
device->cname = "GF116";
@@ -220,7 +220,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xc1:
device->cname = "GF108";
@@ -252,7 +252,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xc8:
device->cname = "GF110";
@@ -285,7 +285,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xd9:
device->cname = "GF119";
@@ -317,7 +317,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xd7:
device->cname = "GF117";
@@ -347,7 +347,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
default:
nv_fatal(device, "unknown Fermi chipset\n");
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index c18f5821c3cf..c68e76b40d51 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -53,7 +53,7 @@
#include <engine/msvld.h>
#include <engine/vp.h>
#include <engine/ppp.h>
-#include <engine/perfmon.h>
+#include <engine/pm.h>
int
nve0_identify(struct nouveau_device *device)
@@ -91,7 +91,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
case 0xe7:
device->cname = "GK107";
@@ -125,7 +125,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
case 0xe6:
device->cname = "GK106";
@@ -159,7 +159,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
case 0xea:
device->cname = "GK20A";
@@ -179,7 +179,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass;
break;
@@ -215,7 +215,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
case 0xf1:
device->cname = "GK110B";
@@ -249,7 +249,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
- device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
case 0x106:
device->cname = "GK208B";
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/Kbuild
deleted file mode 100644
index d5f574c4e7b2..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/Kbuild
+++ /dev/null
@@ -1,9 +0,0 @@
-nvkm-y += nvkm/engine/perfmon/base.o
-nvkm-y += nvkm/engine/perfmon/daemon.o
-nvkm-y += nvkm/engine/perfmon/nv40.o
-nvkm-y += nvkm/engine/perfmon/nv50.o
-nvkm-y += nvkm/engine/perfmon/nv84.o
-nvkm-y += nvkm/engine/perfmon/nva3.o
-nvkm-y += nvkm/engine/perfmon/nvc0.o
-nvkm-y += nvkm/engine/perfmon/nve0.o
-nvkm-y += nvkm/engine/perfmon/nvf0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/priv.h
deleted file mode 100644
index 0ac8714fe0ba..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/priv.h
+++ /dev/null
@@ -1,91 +0,0 @@
-#ifndef __NVKM_PERFMON_PRIV_H__
-#define __NVKM_PERFMON_PRIV_H__
-
-#include <engine/perfmon.h>
-
-struct nouveau_perfctr {
- struct nouveau_object base;
- struct list_head head;
- struct nouveau_perfsig *signal[4];
- int slot;
- u32 logic_op;
- u32 clk;
- u32 ctr;
-};
-
-extern struct nouveau_oclass nouveau_perfmon_sclass[];
-
-struct nouveau_perfctx {
- struct nouveau_engctx base;
-};
-
-extern struct nouveau_oclass nouveau_perfmon_cclass;
-
-struct nouveau_specsig {
- u8 signal;
- const char *name;
-};
-
-struct nouveau_perfsig {
- const char *name;
-};
-
-struct nouveau_perfdom;
-struct nouveau_perfctr *
-nouveau_perfsig_wrap(struct nouveau_perfmon *, const char *,
- struct nouveau_perfdom **);
-
-struct nouveau_specdom {
- u16 signal_nr;
- const struct nouveau_specsig *signal;
- const struct nouveau_funcdom *func;
-};
-
-extern const struct nouveau_specdom nva3_perfmon_pwr[];
-extern const struct nouveau_specdom nvc0_perfmon_pwr[];
-extern const struct nouveau_specdom nve0_perfmon_pwr[];
-
-struct nouveau_perfdom {
- struct list_head head;
- struct list_head list;
- const struct nouveau_funcdom *func;
- char name[32];
- u32 addr;
- u8 quad;
- u32 signal_nr;
- struct nouveau_perfsig signal[];
-};
-
-struct nouveau_funcdom {
- void (*init)(struct nouveau_perfmon *, struct nouveau_perfdom *,
- struct nouveau_perfctr *);
- void (*read)(struct nouveau_perfmon *, struct nouveau_perfdom *,
- struct nouveau_perfctr *);
- void (*next)(struct nouveau_perfmon *, struct nouveau_perfdom *);
-};
-
-int nouveau_perfdom_new(struct nouveau_perfmon *, const char *, u32,
- u32, u32, u32, const struct nouveau_specdom *);
-
-#define nouveau_perfmon_create(p,e,o,d) \
- nouveau_perfmon_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_perfmon_dtor(p) ({ \
- struct nouveau_perfmon *c = (p); \
- _nouveau_perfmon_dtor(nv_object(c)); \
-})
-#define nouveau_perfmon_init(p) ({ \
- struct nouveau_perfmon *c = (p); \
- _nouveau_perfmon_init(nv_object(c)); \
-})
-#define nouveau_perfmon_fini(p,s) ({ \
- struct nouveau_perfmon *c = (p); \
- _nouveau_perfmon_fini(nv_object(c), (s)); \
-})
-
-int nouveau_perfmon_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-void _nouveau_perfmon_dtor(struct nouveau_object *);
-int _nouveau_perfmon_init(struct nouveau_object *);
-int _nouveau_perfmon_fini(struct nouveau_object *, bool);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild
new file mode 100644
index 000000000000..fde0dc250b55
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild
@@ -0,0 +1,9 @@
+nvkm-y += nvkm/engine/pm/base.o
+nvkm-y += nvkm/engine/pm/daemon.o
+nvkm-y += nvkm/engine/pm/nv40.o
+nvkm-y += nvkm/engine/pm/nv50.o
+nvkm-y += nvkm/engine/pm/nv84.o
+nvkm-y += nvkm/engine/pm/nva3.o
+nvkm-y += nvkm/engine/pm/nvc0.o
+nvkm-y += nvkm/engine/pm/nve0.o
+nvkm-y += nvkm/engine/pm/nvf0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
similarity index 91%
rename from drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
index 3a9359e29179..5efb308e5d1c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
@@ -59,7 +59,7 @@ nouveau_perfsig_find_(struct nouveau_perfdom *dom, const char *name, u32 size)
}
struct nouveau_perfsig *
-nouveau_perfsig_find(struct nouveau_perfmon *ppm, const char *name, u32 size,
+nouveau_perfsig_find(struct nouveau_pm *ppm, const char *name, u32 size,
struct nouveau_perfdom **pdom)
{
struct nouveau_perfdom *dom = *pdom;
@@ -81,7 +81,7 @@ nouveau_perfsig_find(struct nouveau_perfmon *ppm, const char *name, u32 size,
}
struct nouveau_perfctr *
-nouveau_perfsig_wrap(struct nouveau_perfmon *ppm, const char *name,
+nouveau_perfsig_wrap(struct nouveau_pm *ppm, const char *name,
struct nouveau_perfdom **pdom)
{
struct nouveau_perfsig *sig;
@@ -110,7 +110,7 @@ nouveau_perfctr_query(struct nouveau_object *object, void *data, u32 size)
struct nvif_perfctr_query_v0 v0;
} *args = data;
struct nouveau_device *device = nv_device(object);
- struct nouveau_perfmon *ppm = (void *)object->engine;
+ struct nouveau_pm *ppm = (void *)object->engine;
struct nouveau_perfdom *dom = NULL, *chk;
const bool all = nouveau_boolopt(device->cfgopt, "NvPmShowAll", false);
const bool raw = nouveau_boolopt(device->cfgopt, "NvPmUnnamed", all);
@@ -168,7 +168,7 @@ nouveau_perfctr_sample(struct nouveau_object *object, void *data, u32 size)
union {
struct nvif_perfctr_sample none;
} *args = data;
- struct nouveau_perfmon *ppm = (void *)object->engine;
+ struct nouveau_pm *ppm = (void *)object->engine;
struct nouveau_perfctr *ctr, *tmp;
struct nouveau_perfdom *dom;
int ret;
@@ -273,7 +273,7 @@ nouveau_perfctr_ctor(struct nouveau_object *parent,
union {
struct nvif_perfctr_v0 v0;
} *args = data;
- struct nouveau_perfmon *ppm = (void *)engine;
+ struct nouveau_pm *ppm = (void *)engine;
struct nouveau_perfdom *dom = NULL;
struct nouveau_perfsig *sig[4] = {};
struct nouveau_perfctr *ctr;
@@ -321,7 +321,7 @@ nouveau_perfctr_ofuncs = {
};
struct nouveau_oclass
-nouveau_perfmon_sclass[] = {
+nouveau_pm_sclass[] = {
{ .handle = NVIF_IOCTL_NEW_V0_PERFCTR,
.ofuncs = &nouveau_perfctr_ofuncs,
},
@@ -334,7 +334,7 @@ nouveau_perfmon_sclass[] = {
static void
nouveau_perfctx_dtor(struct nouveau_object *object)
{
- struct nouveau_perfmon *ppm = (void *)object->engine;
+ struct nouveau_pm *ppm = (void *)object->engine;
mutex_lock(&nv_subdev(ppm)->mutex);
nouveau_engctx_destroy(&ppm->context->base);
ppm->context = NULL;
@@ -347,7 +347,7 @@ nouveau_perfctx_ctor(struct nouveau_object *parent,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nouveau_perfmon *ppm = (void *)engine;
+ struct nouveau_pm *ppm = (void *)engine;
struct nouveau_perfctx *ctx;
int ret;
@@ -369,8 +369,8 @@ nouveau_perfctx_ctor(struct nouveau_object *parent,
}
struct nouveau_oclass
-nouveau_perfmon_cclass = {
- .handle = NV_ENGCTX(PERFMON, 0x00),
+nouveau_pm_cclass = {
+ .handle = NV_ENGCTX(PM, 0x00),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nouveau_perfctx_ctor,
.dtor = nouveau_perfctx_dtor,
@@ -383,7 +383,7 @@ nouveau_perfmon_cclass = {
* PPM engine/subdev functions
******************************************************************************/
int
-nouveau_perfdom_new(struct nouveau_perfmon *ppm, const char *name, u32 mask,
+nouveau_perfdom_new(struct nouveau_pm *ppm, const char *name, u32 mask,
u32 base, u32 size_unit, u32 size_domain,
const struct nouveau_specdom *spec)
{
@@ -436,23 +436,23 @@ nouveau_perfdom_new(struct nouveau_perfmon *ppm, const char *name, u32 mask,
}
int
-_nouveau_perfmon_fini(struct nouveau_object *object, bool suspend)
+_nouveau_pm_fini(struct nouveau_object *object, bool suspend)
{
- struct nouveau_perfmon *ppm = (void *)object;
+ struct nouveau_pm *ppm = (void *)object;
return nouveau_engine_fini(&ppm->base, suspend);
}
int
-_nouveau_perfmon_init(struct nouveau_object *object)
+_nouveau_pm_init(struct nouveau_object *object)
{
- struct nouveau_perfmon *ppm = (void *)object;
+ struct nouveau_pm *ppm = (void *)object;
return nouveau_engine_init(&ppm->base);
}
void
-_nouveau_perfmon_dtor(struct nouveau_object *object)
+_nouveau_pm_dtor(struct nouveau_object *object)
{
- struct nouveau_perfmon *ppm = (void *)object;
+ struct nouveau_pm *ppm = (void *)object;
struct nouveau_perfdom *dom, *tmp;
list_for_each_entry_safe(dom, tmp, &ppm->domains, head) {
@@ -464,16 +464,16 @@ _nouveau_perfmon_dtor(struct nouveau_object *object)
}
int
-nouveau_perfmon_create_(struct nouveau_object *parent,
+nouveau_pm_create_(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass,
int length, void **pobject)
{
- struct nouveau_perfmon *ppm;
+ struct nouveau_pm *ppm;
int ret;
ret = nouveau_engine_create_(parent, engine, oclass, true, "PPM",
- "perfmon", length, pobject);
+ "pm", length, pobject);
ppm = *pobject;
if (ret)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/daemon.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c
similarity index 90%
rename from drivers/gpu/drm/nouveau/nvkm/engine/perfmon/daemon.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c
index 50696cc7b7d7..1fd51b815707 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/daemon.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c
@@ -25,7 +25,7 @@
#include "priv.h"
static void
-pwr_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
+pwr_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
u32 mask = 0x00000000;
@@ -41,7 +41,7 @@ pwr_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
}
static void
-pwr_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
+pwr_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
ctr->ctr = ppm->pwr[ctr->slot];
@@ -49,7 +49,7 @@ pwr_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
}
static void
-pwr_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
+pwr_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
{
int i;
@@ -67,7 +67,7 @@ pwr_perfctr_func = {
};
const struct nouveau_specdom
-nva3_perfmon_pwr[] = {
+nva3_pm_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
@@ -80,7 +80,7 @@ nva3_perfmon_pwr[] = {
};
const struct nouveau_specdom
-nvc0_perfmon_pwr[] = {
+nvc0_pm_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
@@ -94,7 +94,7 @@ nvc0_perfmon_pwr[] = {
};
const struct nouveau_specdom
-nve0_perfmon_pwr[] = {
+nve0_pm_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c
similarity index 77%
rename from drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c
index b2a10785adb1..82a1777a3e11 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c
@@ -37,11 +37,11 @@
******************************************************************************/
static void
-nv40_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
+nv40_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
- struct nv40_perfmon_priv *priv = (void *)ppm;
- struct nv40_perfmon_cntr *cntr = (void *)ctr;
+ struct nv40_pm_priv *priv = (void *)ppm;
+ struct nv40_pm_cntr *cntr = (void *)ctr;
u32 log = ctr->logic_op;
u32 src = 0x00000000;
int i;
@@ -55,11 +55,11 @@ nv40_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
}
static void
-nv40_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
+nv40_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
- struct nv40_perfmon_priv *priv = (void *)ppm;
- struct nv40_perfmon_cntr *cntr = (void *)ctr;
+ struct nv40_pm_priv *priv = (void *)ppm;
+ struct nv40_pm_cntr *cntr = (void *)ctr;
switch (cntr->base.slot) {
case 0: cntr->base.ctr = nv_rd32(priv, 0x00a700 + dom->addr); break;
@@ -71,9 +71,9 @@ nv40_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
}
static void
-nv40_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
+nv40_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
{
- struct nv40_perfmon_priv *priv = (void *)ppm;
+ struct nv40_pm_priv *priv = (void *)ppm;
if (priv->sequence != ppm->sequence) {
nv_wr32(priv, 0x400084, 0x00000020);
priv->sequence = ppm->sequence;
@@ -88,7 +88,7 @@ nv40_perfctr_func = {
};
static const struct nouveau_specdom
-nv40_perfmon[] = {
+nv40_pm[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
@@ -108,15 +108,15 @@ nv40_perfmon[] = {
};
int
-nv40_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv40_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv40_perfmon_oclass *mclass = (void *)oclass;
- struct nv40_perfmon_priv *priv;
+ struct nv40_pm_oclass *mclass = (void *)oclass;
+ struct nv40_pm_priv *priv;
int ret;
- ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
+ ret = nouveau_pm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -125,19 +125,19 @@ nv40_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret)
return ret;
- nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
- nv_engine(priv)->sclass = nouveau_perfmon_sclass;
+ nv_engine(priv)->cclass = &nouveau_pm_cclass;
+ nv_engine(priv)->sclass = nouveau_pm_sclass;
return 0;
}
struct nouveau_oclass *
-nv40_perfmon_oclass = &(struct nv40_perfmon_oclass) {
- .base.handle = NV_ENGINE(PERFMON, 0x40),
+nv40_pm_oclass = &(struct nv40_pm_oclass) {
+ .base.handle = NV_ENGINE(PM, 0x40),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv40_perfmon_ctor,
- .dtor = _nouveau_perfmon_dtor,
- .init = _nouveau_perfmon_init,
- .fini = _nouveau_perfmon_fini,
+ .ctor = nv40_pm_ctor,
+ .dtor = _nouveau_pm_dtor,
+ .init = _nouveau_pm_init,
+ .fini = _nouveau_pm_fini,
},
- .doms = nv40_perfmon,
+ .doms = nv40_pm,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h
similarity index 65%
rename from drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h
index 1b5792d1df14..e83a0efd5d89 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h
@@ -3,21 +3,21 @@
#include "priv.h"
-struct nv40_perfmon_oclass {
+struct nv40_pm_oclass {
struct nouveau_oclass base;
const struct nouveau_specdom *doms;
};
-struct nv40_perfmon_priv {
- struct nouveau_perfmon base;
+struct nv40_pm_priv {
+ struct nouveau_pm base;
u32 sequence;
};
-int nv40_perfmon_ctor(struct nouveau_object *, struct nouveau_object *,
+int nv40_pm_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *data, u32 size,
struct nouveau_object **pobject);
-struct nv40_perfmon_cntr {
+struct nv40_pm_cntr {
struct nouveau_perfctr base;
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c
similarity index 89%
rename from drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c
index 94217691fe67..db2f9a17abb5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c
@@ -37,7 +37,7 @@
******************************************************************************/
static const struct nouveau_specdom
-nv50_perfmon[] = {
+nv50_pm[] = {
{ 0x040, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
@@ -58,13 +58,13 @@ nv50_perfmon[] = {
};
struct nouveau_oclass *
-nv50_perfmon_oclass = &(struct nv40_perfmon_oclass) {
- .base.handle = NV_ENGINE(PERFMON, 0x50),
+nv50_pm_oclass = &(struct nv40_pm_oclass) {
+ .base.handle = NV_ENGINE(PM, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv40_perfmon_ctor,
- .dtor = _nouveau_perfmon_dtor,
- .init = _nouveau_perfmon_init,
- .fini = _nouveau_perfmon_fini,
+ .ctor = nv40_pm_ctor,
+ .dtor = _nouveau_pm_dtor,
+ .init = _nouveau_pm_init,
+ .fini = _nouveau_pm_fini,
},
- .doms = nv50_perfmon,
+ .doms = nv50_pm,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv84.c
similarity index 90%
rename from drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/nv84.c
index 9232c7fc6253..37a4fc9c346b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv84.c
@@ -37,7 +37,7 @@
******************************************************************************/
static const struct nouveau_specdom
-nv84_perfmon[] = {
+nv84_pm[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
@@ -66,13 +66,13 @@ nv84_perfmon[] = {
};
struct nouveau_oclass *
-nv84_perfmon_oclass = &(struct nv40_perfmon_oclass) {
- .base.handle = NV_ENGINE(PERFMON, 0x84),
+nv84_pm_oclass = &(struct nv40_pm_oclass) {
+ .base.handle = NV_ENGINE(PM, 0x84),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv40_perfmon_ctor,
- .dtor = _nouveau_perfmon_dtor,
- .init = _nouveau_perfmon_init,
- .fini = _nouveau_perfmon_fini,
+ .ctor = nv40_pm_ctor,
+ .dtor = _nouveau_pm_dtor,
+ .init = _nouveau_pm_init,
+ .fini = _nouveau_pm_fini,
},
- .doms = nv84_perfmon,
+ .doms = nv84_pm,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nva3.c
similarity index 84%
rename from drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/nva3.c
index 6197ebdeb648..d54dc57c4e61 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nva3.c
@@ -37,7 +37,7 @@
******************************************************************************/
static const struct nouveau_specdom
-nva3_perfmon[] = {
+nva3_pm[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
@@ -66,15 +66,15 @@ nva3_perfmon[] = {
};
static int
-nva3_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nva3_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **object)
{
- int ret = nv40_perfmon_ctor(parent, engine, oclass, data, size, object);
+ int ret = nv40_pm_ctor(parent, engine, oclass, data, size, object);
if (ret == 0) {
- struct nv40_perfmon_priv *priv = (void *)*object;
+ struct nv40_pm_priv *priv = (void *)*object;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
- nva3_perfmon_pwr);
+ nva3_pm_pwr);
if (ret)
return ret;
@@ -84,13 +84,13 @@ nva3_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
struct nouveau_oclass *
-nva3_perfmon_oclass = &(struct nv40_perfmon_oclass) {
- .base.handle = NV_ENGINE(PERFMON, 0xa3),
+nva3_pm_oclass = &(struct nv40_pm_oclass) {
+ .base.handle = NV_ENGINE(PM, 0xa3),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nva3_perfmon_ctor,
- .dtor = _nouveau_perfmon_dtor,
- .init = _nouveau_perfmon_init,
- .fini = _nouveau_perfmon_fini,
+ .ctor = nva3_pm_ctor,
+ .dtor = _nouveau_pm_dtor,
+ .init = _nouveau_pm_init,
+ .fini = _nouveau_pm_fini,
},
- .doms = nva3_perfmon,
+ .doms = nva3_pm,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.c
similarity index 75%
rename from drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.c
index 74b241042502..fb00e82bbed0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.c
@@ -37,26 +37,26 @@
******************************************************************************/
static const struct nouveau_specdom
-nvc0_perfmon_hub[] = {
+nvc0_pm_hub[] = {
{}
};
static const struct nouveau_specdom
-nvc0_perfmon_gpc[] = {
+nvc0_pm_gpc[] = {
{}
};
static const struct nouveau_specdom
-nvc0_perfmon_part[] = {
+nvc0_pm_part[] = {
{}
};
static void
-nvc0_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
+nvc0_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
- struct nvc0_perfmon_priv *priv = (void *)ppm;
- struct nvc0_perfmon_cntr *cntr = (void *)ctr;
+ struct nvc0_pm_priv *priv = (void *)ppm;
+ struct nvc0_pm_cntr *cntr = (void *)ctr;
u32 log = ctr->logic_op;
u32 src = 0x00000000;
int i;
@@ -71,11 +71,11 @@ nvc0_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
}
static void
-nvc0_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
+nvc0_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
- struct nvc0_perfmon_priv *priv = (void *)ppm;
- struct nvc0_perfmon_cntr *cntr = (void *)ctr;
+ struct nvc0_pm_priv *priv = (void *)ppm;
+ struct nvc0_pm_cntr *cntr = (void *)ctr;
switch (cntr->base.slot) {
case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break;
@@ -87,9 +87,9 @@ nvc0_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
}
static void
-nvc0_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
+nvc0_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
{
- struct nvc0_perfmon_priv *priv = (void *)ppm;
+ struct nvc0_pm_priv *priv = (void *)ppm;
nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27);
nv_wr32(priv, dom->addr + 0x0ec, 0x00000011);
}
@@ -102,36 +102,36 @@ nvc0_perfctr_func = {
};
int
-nvc0_perfmon_fini(struct nouveau_object *object, bool suspend)
+nvc0_pm_fini(struct nouveau_object *object, bool suspend)
{
- struct nvc0_perfmon_priv *priv = (void *)object;
+ struct nvc0_pm_priv *priv = (void *)object;
nv_mask(priv, 0x000200, 0x10000000, 0x00000000);
nv_mask(priv, 0x000200, 0x10000000, 0x10000000);
- return nouveau_perfmon_fini(&priv->base, suspend);
+ return nouveau_pm_fini(&priv->base, suspend);
}
static int
-nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvc0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvc0_perfmon_priv *priv;
+ struct nvc0_pm_priv *priv;
u32 mask;
int ret;
- ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
+ ret = nouveau_pm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
- nvc0_perfmon_pwr);
+ nvc0_pm_pwr);
if (ret)
return ret;
/* HUB */
ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
- nvc0_perfmon_hub);
+ nvc0_pm_hub);
if (ret)
return ret;
@@ -141,7 +141,7 @@ nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
mask &= ~nv_rd32(priv, 0x022584);
ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
- 0x1000, 0x200, nvc0_perfmon_gpc);
+ 0x1000, 0x200, nvc0_pm_gpc);
if (ret)
return ret;
@@ -151,23 +151,23 @@ nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
mask &= ~nv_rd32(priv, 0x0225c8);
ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
- 0x1000, 0x200, nvc0_perfmon_part);
+ 0x1000, 0x200, nvc0_pm_part);
if (ret)
return ret;
- nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
- nv_engine(priv)->sclass = nouveau_perfmon_sclass;
+ nv_engine(priv)->cclass = &nouveau_pm_cclass;
+ nv_engine(priv)->sclass = nouveau_pm_sclass;
priv->base.last = 7;
return 0;
}
struct nouveau_oclass
-nvc0_perfmon_oclass = {
- .handle = NV_ENGINE(PERFMON, 0xc0),
+nvc0_pm_oclass = {
+ .handle = NV_ENGINE(PM, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_perfmon_ctor,
- .dtor = _nouveau_perfmon_dtor,
- .init = _nouveau_perfmon_init,
- .fini = nvc0_perfmon_fini,
+ .ctor = nvc0_pm_ctor,
+ .dtor = _nouveau_pm_dtor,
+ .init = _nouveau_pm_init,
+ .fini = nvc0_pm_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.h
similarity index 55%
rename from drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.h
index f66bca484263..e0e0e02600d4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.h
@@ -3,15 +3,15 @@
#include "priv.h"
-struct nvc0_perfmon_priv {
- struct nouveau_perfmon base;
+struct nvc0_pm_priv {
+ struct nouveau_pm base;
};
-struct nvc0_perfmon_cntr {
+struct nvc0_pm_cntr {
struct nouveau_perfctr base;
};
extern const struct nouveau_funcdom nvc0_perfctr_func;
-int nvc0_perfmon_fini(struct nouveau_object *, bool);
+int nvc0_pm_fini(struct nouveau_object *, bool);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nve0.c
similarity index 85%
rename from drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/nve0.c
index 71d718c12075..11b17cced966 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nve0.c
@@ -37,7 +37,7 @@
******************************************************************************/
static const struct nouveau_specdom
-nve0_perfmon_hub[] = {
+nve0_pm_hub[] = {
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub00_user_0" },
{}
@@ -77,7 +77,7 @@ nve0_perfmon_hub[] = {
};
static const struct nouveau_specdom
-nve0_perfmon_gpc[] = {
+nve0_pm_gpc[] = {
{ 0xe0, (const struct nouveau_specsig[]) {
{ 0xc7, "gpc00_user_0" },
{}
@@ -86,7 +86,7 @@ nve0_perfmon_gpc[] = {
};
static const struct nouveau_specdom
-nve0_perfmon_part[] = {
+nve0_pm_part[] = {
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "part00_user_0" },
{}
@@ -99,28 +99,28 @@ nve0_perfmon_part[] = {
};
static int
-nve0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nve0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvc0_perfmon_priv *priv;
+ struct nvc0_pm_priv *priv;
u32 mask;
int ret;
- ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
+ ret = nouveau_pm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
/* PDAEMON */
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
- nve0_perfmon_pwr);
+ nve0_pm_pwr);
if (ret)
return ret;
/* HUB */
ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
- nve0_perfmon_hub);
+ nve0_pm_hub);
if (ret)
return ret;
@@ -130,7 +130,7 @@ nve0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
mask &= ~nv_rd32(priv, 0x022584);
ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
- 0x1000, 0x200, nve0_perfmon_gpc);
+ 0x1000, 0x200, nve0_pm_gpc);
if (ret)
return ret;
@@ -140,23 +140,23 @@ nve0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
mask &= ~nv_rd32(priv, 0x0225c8);
ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
- 0x1000, 0x200, nve0_perfmon_part);
+ 0x1000, 0x200, nve0_pm_part);
if (ret)
return ret;
- nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
- nv_engine(priv)->sclass = nouveau_perfmon_sclass;
+ nv_engine(priv)->cclass = &nouveau_pm_cclass;
+ nv_engine(priv)->sclass = nouveau_pm_sclass;
priv->base.last = 7;
return 0;
}
struct nouveau_oclass
-nve0_perfmon_oclass = {
- .handle = NV_ENGINE(PERFMON, 0xe0),
+nve0_pm_oclass = {
+ .handle = NV_ENGINE(PM, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_perfmon_ctor,
- .dtor = _nouveau_perfmon_dtor,
- .init = _nouveau_perfmon_init,
- .fini = nvc0_perfmon_fini,
+ .ctor = nve0_pm_ctor,
+ .dtor = _nouveau_pm_dtor,
+ .init = _nouveau_pm_init,
+ .fini = nvc0_pm_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvf0.c
similarity index 80%
rename from drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvf0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/nvf0.c
index 47256f78a895..7d5a8dddae9d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvf0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvf0.c
@@ -37,35 +37,35 @@
******************************************************************************/
static int
-nvf0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvf0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvc0_perfmon_priv *priv;
+ struct nvc0_pm_priv *priv;
int ret;
- ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
+ ret = nouveau_pm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
- nve0_perfmon_pwr);
+ nve0_pm_pwr);
if (ret)
return ret;
- nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
- nv_engine(priv)->sclass = nouveau_perfmon_sclass;
+ nv_engine(priv)->cclass = &nouveau_pm_cclass;
+ nv_engine(priv)->sclass = nouveau_pm_sclass;
return 0;
}
struct nouveau_oclass
-nvf0_perfmon_oclass = {
- .handle = NV_ENGINE(PERFMON, 0xf0),
+nvf0_pm_oclass = {
+ .handle = NV_ENGINE(PM, 0xf0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvf0_perfmon_ctor,
- .dtor = _nouveau_perfmon_dtor,
- .init = _nouveau_perfmon_init,
- .fini = nvc0_perfmon_fini,
+ .ctor = nvf0_pm_ctor,
+ .dtor = _nouveau_pm_dtor,
+ .init = _nouveau_pm_init,
+ .fini = nvc0_pm_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
new file mode 100644
index 000000000000..af3938fb19e0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
@@ -0,0 +1,91 @@
+#ifndef __NVKM_PM_PRIV_H__
+#define __NVKM_PM_PRIV_H__
+
+#include <engine/pm.h>
+
+struct nouveau_perfctr {
+ struct nouveau_object base;
+ struct list_head head;
+ struct nouveau_perfsig *signal[4];
+ int slot;
+ u32 logic_op;
+ u32 clk;
+ u32 ctr;
+};
+
+extern struct nouveau_oclass nouveau_pm_sclass[];
+
+struct nouveau_perfctx {
+ struct nouveau_engctx base;
+};
+
+extern struct nouveau_oclass nouveau_pm_cclass;
+
+struct nouveau_specsig {
+ u8 signal;
+ const char *name;
+};
+
+struct nouveau_perfsig {
+ const char *name;
+};
+
+struct nouveau_perfdom;
+struct nouveau_perfctr *
+nouveau_perfsig_wrap(struct nouveau_pm *, const char *,
+ struct nouveau_perfdom **);
+
+struct nouveau_specdom {
+ u16 signal_nr;
+ const struct nouveau_specsig *signal;
+ const struct nouveau_funcdom *func;
+};
+
+extern const struct nouveau_specdom nva3_pm_pwr[];
+extern const struct nouveau_specdom nvc0_pm_pwr[];
+extern const struct nouveau_specdom nve0_pm_pwr[];
+
+struct nouveau_perfdom {
+ struct list_head head;
+ struct list_head list;
+ const struct nouveau_funcdom *func;
+ char name[32];
+ u32 addr;
+ u8 quad;
+ u32 signal_nr;
+ struct nouveau_perfsig signal[];
+};
+
+struct nouveau_funcdom {
+ void (*init)(struct nouveau_pm *, struct nouveau_perfdom *,
+ struct nouveau_perfctr *);
+ void (*read)(struct nouveau_pm *, struct nouveau_perfdom *,
+ struct nouveau_perfctr *);
+ void (*next)(struct nouveau_pm *, struct nouveau_perfdom *);
+};
+
+int nouveau_perfdom_new(struct nouveau_pm *, const char *, u32,
+ u32, u32, u32, const struct nouveau_specdom *);
+
+#define nouveau_pm_create(p,e,o,d) \
+ nouveau_pm_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nouveau_pm_dtor(p) ({ \
+ struct nouveau_pm *c = (p); \
+ _nouveau_pm_dtor(nv_object(c)); \
+})
+#define nouveau_pm_init(p) ({ \
+ struct nouveau_pm *c = (p); \
+ _nouveau_pm_init(nv_object(c)); \
+})
+#define nouveau_pm_fini(p,s) ({ \
+ struct nouveau_pm *c = (p); \
+ _nouveau_pm_fini(nv_object(c), (s)); \
+})
+
+int nouveau_pm_create_(struct nouveau_object *, struct nouveau_object *,
+ struct nouveau_oclass *, int, void **);
+void _nouveau_pm_dtor(struct nouveau_object *);
+int _nouveau_pm_init(struct nouveau_object *);
+int _nouveau_pm_fini(struct nouveau_object *, bool);
+
+#endif
From fd8666f7db94afc1b63b8439d902783b27a2f27f Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 12:26:28 +1000
Subject: [PATCH 45/86] drm/nouveau/msppp: rename from ppp (no binary change)
Switch to NVIDIA's name for the device.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/include/nvif/class.h | 4 +-
.../drm/nouveau/include/nvkm/core/device.h | 2 +-
.../drm/nouveau/include/nvkm/engine/msppp.h | 7 ++++
.../gpu/drm/nouveau/include/nvkm/engine/ppp.h | 7 ----
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 2 +-
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +-
.../drm/nouveau/nvkm/engine/device/gm100.c | 6 +--
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 16 ++++----
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 20 +++++-----
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 16 ++++----
.../gpu/drm/nouveau/nvkm/engine/fifo/nv84.c | 10 ++---
.../gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c | 16 ++++----
.../gpu/drm/nouveau/nvkm/engine/fifo/nve0.c | 10 ++---
.../gpu/drm/nouveau/nvkm/engine/msppp/Kbuild | 2 +
.../nouveau/nvkm/engine/{ppp => msppp}/nv98.c | 38 +++++++++----------
.../nouveau/nvkm/engine/{ppp => msppp}/nvc0.c | 38 +++++++++----------
.../gpu/drm/nouveau/nvkm/engine/ppp/Kbuild | 2 -
.../drm/nouveau/nvkm/subdev/devinit/nv98.c | 2 +-
.../drm/nouveau/nvkm/subdev/devinit/nva3.c | 2 +-
.../drm/nouveau/nvkm/subdev/devinit/nvaf.c | 2 +-
.../drm/nouveau/nvkm/subdev/devinit/nvc0.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 4 +-
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 2 +-
25 files changed, 108 insertions(+), 108 deletions(-)
create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/ppp.h
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
rename drivers/gpu/drm/nouveau/nvkm/engine/{ppp => msppp}/nv98.c (81%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{ppp => msppp}/nvc0.c (81%)
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/ppp/Kbuild
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h
index c88bb7c1010e..e35988aa255b 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
@@ -128,7 +128,7 @@ struct nv_device_v0 {
#define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL
#define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL
#define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL
-#define NV_DEVICE_V0_DISABLE_PPP 0x0000004000000000ULL
+#define NV_DEVICE_V0_DISABLE_MSPPP 0x0000004000000000ULL
#define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL
#define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL
#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
@@ -349,7 +349,7 @@ struct kepler_channel_gpfifo_a_v0 {
__u8 version;
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02
-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP 0x04
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 3d87d3daa5a8..1a6a49c7f84b 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -51,7 +51,7 @@ enum nv_subdev_type {
NVDEV_ENGINE_VP,
NVDEV_ENGINE_CIPHER,
NVDEV_ENGINE_BSP,
- NVDEV_ENGINE_PPP,
+ NVDEV_ENGINE_MSPPP,
NVDEV_ENGINE_CE0,
NVDEV_ENGINE_CE1,
NVDEV_ENGINE_CE2,
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
new file mode 100644
index 000000000000..5f2f82ed9598
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
@@ -0,0 +1,7 @@
+#ifndef __NOUVEAU_MSPPP_H__
+#define __NOUVEAU_MSPPP_H__
+
+extern struct nouveau_oclass nv98_msppp_oclass;
+extern struct nouveau_oclass nvc0_msppp_oclass;
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ppp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ppp.h
deleted file mode 100644
index 0a66781e8cf1..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/ppp.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __NOUVEAU_PPP_H__
-#define __NOUVEAU_PPP_H__
-
-extern struct nouveau_oclass nv98_ppp_oclass;
-extern struct nouveau_oclass nvc0_ppp_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
index 16c3a91b7e4a..0607d595f6e7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
@@ -12,7 +12,7 @@ include $(src)/nvkm/engine/gr/Kbuild
include $(src)/nvkm/engine/mpeg/Kbuild
include $(src)/nvkm/engine/msvld/Kbuild
include $(src)/nvkm/engine/pm/Kbuild
-include $(src)/nvkm/engine/ppp/Kbuild
+include $(src)/nvkm/engine/msppp/Kbuild
include $(src)/nvkm/engine/sec/Kbuild
include $(src)/nvkm/engine/software/Kbuild
include $(src)/nvkm/engine/vp/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 5b226cb04298..fda8d729aa30 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -234,7 +234,7 @@ static const u64 disable_map[] = {
[NVDEV_ENGINE_VP] = NV_DEVICE_V0_DISABLE_VP,
[NVDEV_ENGINE_CIPHER] = NV_DEVICE_V0_DISABLE_CIPHER,
[NVDEV_ENGINE_BSP] = NV_DEVICE_V0_DISABLE_BSP,
- [NVDEV_ENGINE_PPP] = NV_DEVICE_V0_DISABLE_PPP,
+ [NVDEV_ENGINE_MSPPP] = NV_DEVICE_V0_DISABLE_MSPPP,
[NVDEV_ENGINE_CE0] = NV_DEVICE_V0_DISABLE_CE0,
[NVDEV_ENGINE_CE1] = NV_DEVICE_V0_DISABLE_CE1,
[NVDEV_ENGINE_CE2] = NV_DEVICE_V0_DISABLE_CE2,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 2ea1dbcf641f..690250503332 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -52,7 +52,7 @@
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/vp.h>
-#include <engine/ppp.h>
+#include <engine/msppp.h>
#include <engine/pm.h>
int
@@ -96,7 +96,7 @@ gm100_identify(struct nouveau_device *device)
#if 0
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
#endif
break;
case 0x124:
@@ -139,7 +139,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
#endif
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 6e5ccb371372..3f3d2ea1a930 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -51,7 +51,7 @@
#include <engine/sec.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
-#include <engine/ppp.h>
+#include <engine/msppp.h>
#include <engine/ce.h>
#include <engine/disp.h>
#include <engine/pm.h>
@@ -256,7 +256,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@@ -314,7 +314,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@@ -343,7 +343,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@@ -373,7 +373,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
@@ -403,7 +403,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
@@ -433,7 +433,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
@@ -463,7 +463,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index d159d2993043..b241421e76a2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -50,7 +50,7 @@
#include <engine/vp.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
-#include <engine/ppp.h>
+#include <engine/msppp.h>
#include <engine/ce.h>
#include <engine/disp.h>
#include <engine/pm.h>
@@ -86,7 +86,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@@ -119,7 +119,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@@ -152,7 +152,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
@@ -184,7 +184,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@@ -217,7 +217,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
@@ -249,7 +249,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
@@ -281,7 +281,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@@ -314,7 +314,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
@@ -344,7 +344,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index c68e76b40d51..df975987b9ca 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -52,7 +52,7 @@
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/vp.h>
-#include <engine/ppp.h>
+#include <engine/msppp.h>
#include <engine/pm.h>
int
@@ -90,7 +90,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
case 0xe7:
@@ -124,7 +124,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
case 0xe6:
@@ -158,7 +158,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
case 0xea:
@@ -214,7 +214,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
case 0xf1:
@@ -248,7 +248,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
case 0x106:
@@ -282,7 +282,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
break;
case 0x108:
device->cname = "GK208";
@@ -315,7 +315,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
break;
default:
nv_fatal(device, "unknown Kepler chipset\n");
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
index 4a3638e1944e..6abcd5c3e773 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
@@ -58,7 +58,7 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : addr = 0x0020; break;
case NVDEV_ENGINE_VP : addr = 0x0040; break;
- case NVDEV_ENGINE_PPP :
+ case NVDEV_ENGINE_MSPPP :
case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
case NVDEV_ENGINE_BSP :
case NVDEV_ENGINE_MSVLD : addr = 0x0080; break;
@@ -96,7 +96,7 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
- case NVDEV_ENGINE_PPP :
+ case NVDEV_ENGINE_MSPPP :
case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
case NVDEV_ENGINE_BSP :
case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break;
@@ -145,7 +145,7 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_SW : context |= 0x00000000; break;
case NVDEV_ENGINE_GR : context |= 0x00100000; break;
case NVDEV_ENGINE_MPEG :
- case NVDEV_ENGINE_PPP : context |= 0x00200000; break;
+ case NVDEV_ENGINE_MSPPP : context |= 0x00200000; break;
case NVDEV_ENGINE_ME :
case NVDEV_ENGINE_CE0 : context |= 0x00300000; break;
case NVDEV_ENGINE_VP : context |= 0x00400000; break;
@@ -195,7 +195,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_SEC) |
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
- (1ULL << NVDEV_ENGINE_PPP) |
+ (1ULL << NVDEV_ENGINE_MSPPP) |
(1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);
@@ -270,7 +270,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_SEC) |
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
- (1ULL << NVDEV_ENGINE_PPP) |
+ (1ULL << NVDEV_ENGINE_MSPPP) |
(1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
index 1511e387fd5d..d86601c02368 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
@@ -126,7 +126,7 @@ nvc0_fifo_context_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
- case NVDEV_ENGINE_PPP : addr = 0x0260; break;
+ case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
default:
return -EINVAL;
}
@@ -163,7 +163,7 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
- case NVDEV_ENGINE_PPP : addr = 0x0260; break;
+ case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
default:
return -EINVAL;
}
@@ -216,7 +216,7 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_CE1) |
(1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_VP) |
- (1ULL << NVDEV_ENGINE_PPP), &chan);
+ (1ULL << NVDEV_ENGINE_MSPPP), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -383,7 +383,7 @@ nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
switch (engn) {
case NVDEV_ENGINE_GR : engn = 0; break;
case NVDEV_ENGINE_MSVLD: engn = 1; break;
- case NVDEV_ENGINE_PPP : engn = 2; break;
+ case NVDEV_ENGINE_MSPPP: engn = 2; break;
case NVDEV_ENGINE_VP : engn = 3; break;
case NVDEV_ENGINE_CE0 : engn = 4; break;
case NVDEV_ENGINE_CE1 : engn = 5; break;
@@ -400,7 +400,7 @@ nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
switch (engn) {
case 0: engn = NVDEV_ENGINE_GR; break;
case 1: engn = NVDEV_ENGINE_MSVLD; break;
- case 2: engn = NVDEV_ENGINE_PPP; break;
+ case 2: engn = NVDEV_ENGINE_MSPPP; break;
case 3: engn = NVDEV_ENGINE_VP; break;
case 4: engn = NVDEV_ENGINE_CE0; break;
case 5: engn = NVDEV_ENGINE_CE1; break;
@@ -549,7 +549,7 @@ nvc0_fifo_fault_engine[] = {
{ 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
{ 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
{ 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD },
- { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
+ { 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
{ 0x13, "PCOUNTER" },
{ 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
{ 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 },
@@ -582,7 +582,7 @@ nvc0_fifo_fault_hubclient[] = {
{ 0x07, "BAR_READ" },
{ 0x08, "BAR_WRITE" },
{ 0x0b, "PVP" },
- { 0x0c, "PPPP" },
+ { 0x0c, "PMSPPP" },
{ 0x0d, "PMSVLD" },
{ 0x11, "PCOUNTER" },
{ 0x12, "PDAEMON" },
@@ -940,7 +940,7 @@ nvc0_fifo_init(struct nouveau_object *object)
if (priv->spoon_nr >= 3) {
nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
- nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
+ nv_wr32(priv, 0x002210, ~(1 << 1)); /* PMSPP */
nv_wr32(priv, 0x002214, ~(1 << 1)); /* PMSVLD */
nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
index 324008e8fa9b..81dc280c0022 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
@@ -49,7 +49,7 @@ static const struct {
_(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_CE2)),
_(NVDEV_ENGINE_VP , 0),
- _(NVDEV_ENGINE_PPP , 0),
+ _(NVDEV_ENGINE_MSPPP , 0),
_(NVDEV_ENGINE_MSVLD , 0),
_(NVDEV_ENGINE_CE0 , 0),
_(NVDEV_ENGINE_CE1 , 0),
@@ -151,7 +151,7 @@ nve0_fifo_context_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_GR : addr = 0x0210; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
- case NVDEV_ENGINE_PPP : addr = 0x0260; break;
+ case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
default:
return -EINVAL;
}
@@ -189,7 +189,7 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
case NVDEV_ENGINE_GR : addr = 0x0210; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
- case NVDEV_ENGINE_PPP : addr = 0x0260; break;
+ case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
default:
return -EINVAL;
}
@@ -417,7 +417,7 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
case NVDEV_ENGINE_GR :
case NVDEV_ENGINE_CE2 : engn = 0; break;
case NVDEV_ENGINE_MSVLD: engn = 1; break;
- case NVDEV_ENGINE_PPP : engn = 2; break;
+ case NVDEV_ENGINE_MSPPP: engn = 2; break;
case NVDEV_ENGINE_VP : engn = 3; break;
case NVDEV_ENGINE_CE0 : engn = 4; break;
case NVDEV_ENGINE_CE1 : engn = 5; break;
@@ -620,7 +620,7 @@ nve0_fifo_fault_engine[] = {
{ 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO },
{ 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO },
{ 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD },
- { 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP },
+ { 0x11, "MSPPP", NULL, NVDEV_ENGINE_MSPPP },
{ 0x13, "PERF" },
{ 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
{ 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
new file mode 100644
index 000000000000..9b90ce948425
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
@@ -0,0 +1,2 @@
+nvkm-y += nvkm/engine/msppp/nv98.o
+nvkm-y += nvkm/engine/msppp/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ppp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c
similarity index 81%
rename from drivers/gpu/drm/nouveau/nvkm/engine/ppp/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c
index 13bf31c40aa1..c044943c3fc7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ppp/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c
@@ -23,30 +23,30 @@
*/
#include <engine/falcon.h>
-#include <engine/ppp.h>
+#include <engine/msppp.h>
-struct nv98_ppp_priv {
+struct nv98_msppp_priv {
struct nouveau_falcon base;
};
/*******************************************************************************
- * PPP object classes
+ * MSPPP object classes
******************************************************************************/
static struct nouveau_oclass
-nv98_ppp_sclass[] = {
+nv98_msppp_sclass[] = {
{ 0x88b3, &nouveau_object_ofuncs },
{ 0x85b3, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
- * PPPP context
+ * PMSPPP context
******************************************************************************/
static struct nouveau_oclass
-nv98_ppp_cclass = {
- .handle = NV_ENGCTX(PPP, 0x98),
+nv98_msppp_cclass = {
+ .handle = NV_ENGCTX(MSPPP, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@@ -58,13 +58,13 @@ nv98_ppp_cclass = {
};
/*******************************************************************************
- * PPPP engine/subdev functions
+ * PMSPPP engine/subdev functions
******************************************************************************/
static int
-nv98_ppp_init(struct nouveau_object *object)
+nv98_msppp_init(struct nouveau_object *object)
{
- struct nv98_ppp_priv *priv = (void *)object;
+ struct nv98_msppp_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
@@ -77,32 +77,32 @@ nv98_ppp_init(struct nouveau_object *object)
}
static int
-nv98_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv98_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv98_ppp_priv *priv;
+ struct nv98_msppp_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
- "PPPP", "ppp", &priv);
+ "PMSPPP", "msppp", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00400002;
- nv_engine(priv)->cclass = &nv98_ppp_cclass;
- nv_engine(priv)->sclass = nv98_ppp_sclass;
+ nv_engine(priv)->cclass = &nv98_msppp_cclass;
+ nv_engine(priv)->sclass = nv98_msppp_sclass;
return 0;
}
struct nouveau_oclass
-nv98_ppp_oclass = {
- .handle = NV_ENGINE(PPP, 0x98),
+nv98_msppp_oclass = {
+ .handle = NV_ENGINE(MSPPP, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv98_ppp_ctor,
+ .ctor = nv98_msppp_ctor,
.dtor = _nouveau_falcon_dtor,
- .init = nv98_ppp_init,
+ .init = nv98_msppp_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ppp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c
similarity index 81%
rename from drivers/gpu/drm/nouveau/nvkm/engine/ppp/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c
index 73719aaa62d6..91398e639395 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ppp/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c
@@ -23,29 +23,29 @@
*/
#include <engine/falcon.h>
-#include <engine/ppp.h>
+#include <engine/msppp.h>
-struct nvc0_ppp_priv {
+struct nvc0_msppp_priv {
struct nouveau_falcon base;
};
/*******************************************************************************
- * PPP object classes
+ * MSPPP object classes
******************************************************************************/
static struct nouveau_oclass
-nvc0_ppp_sclass[] = {
+nvc0_msppp_sclass[] = {
{ 0x90b3, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
- * PPPP context
+ * PMSPPP context
******************************************************************************/
static struct nouveau_oclass
-nvc0_ppp_cclass = {
- .handle = NV_ENGCTX(PPP, 0xc0),
+nvc0_msppp_cclass = {
+ .handle = NV_ENGCTX(MSPPP, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@@ -57,13 +57,13 @@ nvc0_ppp_cclass = {
};
/*******************************************************************************
- * PPPP engine/subdev functions
+ * PMSPPP engine/subdev functions
******************************************************************************/
static int
-nvc0_ppp_init(struct nouveau_object *object)
+nvc0_msppp_init(struct nouveau_object *object)
{
- struct nvc0_ppp_priv *priv = (void *)object;
+ struct nvc0_msppp_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
@@ -76,33 +76,33 @@ nvc0_ppp_init(struct nouveau_object *object)
}
static int
-nvc0_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvc0_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvc0_ppp_priv *priv;
+ struct nvc0_msppp_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
- "PPPP", "ppp", &priv);
+ "PMSPPP", "msppp", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000002;
nv_subdev(priv)->intr = nouveau_falcon_intr;
- nv_engine(priv)->cclass = &nvc0_ppp_cclass;
- nv_engine(priv)->sclass = nvc0_ppp_sclass;
+ nv_engine(priv)->cclass = &nvc0_msppp_cclass;
+ nv_engine(priv)->sclass = nvc0_msppp_sclass;
return 0;
}
struct nouveau_oclass
-nvc0_ppp_oclass = {
- .handle = NV_ENGINE(PPP, 0xc0),
+nvc0_msppp_oclass = {
+ .handle = NV_ENGINE(MSPPP, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_ppp_ctor,
+ .ctor = nvc0_msppp_ctor,
.dtor = _nouveau_falcon_dtor,
- .init = nvc0_ppp_init,
+ .init = nvc0_msppp_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ppp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/ppp/Kbuild
deleted file mode 100644
index 0c1de976f45d..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ppp/Kbuild
+++ /dev/null
@@ -1,2 +0,0 @@
-nvkm-y += nvkm/engine/ppp/nv98.o
-nvkm-y += nvkm/engine/ppp/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
index b27984bbfebb..1da2bedce00a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
@@ -35,7 +35,7 @@ nv98_devinit_disable(struct nouveau_devinit *devinit)
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVDEV_ENGINE_VP);
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
- disable |= (1ULL << NVDEV_ENGINE_PPP);
+ disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
if (!(r00154c & 0x00000004))
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
index b116f8040bbc..8bc7668faede 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
@@ -68,7 +68,7 @@ nva3_devinit_disable(struct nouveau_devinit *devinit)
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVDEV_ENGINE_VP);
- disable |= (1ULL << NVDEV_ENGINE_PPP);
+ disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
if (!(r00154c & 0x00000004))
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
index 140c300c7038..fea3be514553 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
@@ -34,7 +34,7 @@ nvaf_devinit_disable(struct nouveau_devinit *devinit)
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVDEV_ENGINE_VP);
- disable |= (1ULL << NVDEV_ENGINE_PPP);
+ disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
if (!(r00154c & 0x00000004))
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
index c7b2311f497e..4fbe8e9c97f0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
@@ -71,7 +71,7 @@ nvc0_devinit_disable(struct nouveau_devinit *devinit)
if (r022500 & 0x00000002) {
disable |= (1ULL << NVDEV_ENGINE_VP);
- disable |= (1ULL << NVDEV_ENGINE_PPP);
+ disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
if (r022500 & 0x00000004)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
index be129c3297a3..384d7eee830a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
@@ -101,7 +101,7 @@ static const struct nouveau_enum vm_client[] = {
{ 0x00000003, "DISPATCH", vm_dispatch_subclients },
{ 0x00000004, "PFIFO_WRITE", NULL },
{ 0x00000005, "CCACHE", vm_ccache_subclients },
- { 0x00000006, "PPPP", NULL },
+ { 0x00000006, "PMSPPP", NULL },
{ 0x00000007, "CLIPID", NULL },
{ 0x00000008, "PFIFO_READ", NULL },
{ 0x00000009, "VFETCH", NULL },
@@ -121,7 +121,7 @@ static const struct nouveau_enum vm_engine[] = {
{ 0x00000004, "PEEPHOLE", NULL },
{ 0x00000005, "PFIFO", vm_pfifo_subclients, NVDEV_ENGINE_FIFO },
{ 0x00000006, "BAR", vm_bar_subclients },
- { 0x00000008, "PPPP", NULL, NVDEV_ENGINE_PPP },
+ { 0x00000008, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
{ 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG },
{ 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP },
{ 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CIPHER },
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
index 60b250f34cd2..06fc28b5e890 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
@@ -27,7 +27,7 @@
static const struct nouveau_mc_intr
nv98_mc_intr[] = {
{ 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */
- { 0x00000001, NVDEV_ENGINE_PPP },
+ { 0x00000001, NVDEV_ENGINE_MSPPP },
{ 0x00000100, NVDEV_ENGINE_FIFO },
{ 0x00001000, NVDEV_ENGINE_GR },
{ 0x00004000, NVDEV_ENGINE_SEC }, /* NV84:NVA3 */
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
index 5217a5a40447..76f440efa764 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
@@ -27,7 +27,7 @@
const struct nouveau_mc_intr
nvc0_mc_intr[] = {
{ 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */
- { 0x00000001, NVDEV_ENGINE_PPP },
+ { 0x00000001, NVDEV_ENGINE_MSPPP },
{ 0x00000020, NVDEV_ENGINE_CE0 },
{ 0x00000040, NVDEV_ENGINE_CE1 },
{ 0x00000080, NVDEV_ENGINE_CE2 },
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
index 701b9c4ec869..4ac6eb99d55f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
@@ -174,7 +174,7 @@ nv50_vm_flush(struct nouveau_vm *vm)
case NVDEV_ENGINE_GR : vme = 0x00; break;
case NVDEV_ENGINE_VP : vme = 0x01; break;
case NVDEV_SUBDEV_BAR : vme = 0x06; break;
- case NVDEV_ENGINE_PPP :
+ case NVDEV_ENGINE_MSPPP :
case NVDEV_ENGINE_MPEG : vme = 0x08; break;
case NVDEV_ENGINE_BSP :
case NVDEV_ENGINE_MSVLD : vme = 0x09; break;
From 8700287be2b12d091d477fe0568c3858bdedf4e7 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 12:34:00 +1000
Subject: [PATCH 46/86] drm/nouveau/sw: rename from software (no binary change)
Shorter device name, make consistent with our engine enums.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/include/nvif/device.h | 2 +-
.../nouveau/include/nvkm/engine/software.h | 51 ----------
.../gpu/drm/nouveau/include/nvkm/engine/sw.h | 51 ++++++++++
drivers/gpu/drm/nouveau/nouveau_chan.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_drm.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_reg.h | 2 +-
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 2 +-
.../drm/nouveau/nvkm/engine/device/gm100.c | 6 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv04.c | 6 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv10.c | 16 ++--
.../gpu/drm/nouveau/nvkm/engine/device/nv20.c | 10 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv30.c | 12 +--
.../gpu/drm/nouveau/nvkm/engine/device/nv40.c | 34 +++----
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 30 +++---
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 20 ++--
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 18 ++--
.../gpu/drm/nouveau/nvkm/engine/disp/gm107.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/disp/gm204.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/disp/nv84.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/disp/nv94.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/disp/nva0.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/disp/nva3.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/disp/nve0.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/disp/nvf0.c | 2 +-
.../drm/nouveau/nvkm/engine/software/Kbuild | 4 -
.../drm/nouveau/nvkm/engine/software/nv50.h | 46 ---------
drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild | 4 +
.../nvkm/engine/{software => sw}/nv04.c | 66 ++++++-------
.../nvkm/engine/{software => sw}/nv10.c | 60 ++++++------
.../nvkm/engine/{software => sw}/nv50.c | 94 +++++++++----------
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h | 46 +++++++++
.../nvkm/engine/{software => sw}/nvc0.c | 68 +++++++-------
32 files changed, 334 insertions(+), 334 deletions(-)
delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/software.h
create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild
rename drivers/gpu/drm/nouveau/nvkm/engine/{software => sw}/nv04.c (66%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{software => sw}/nv10.c (66%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{software => sw}/nv50.c (66%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
rename drivers/gpu/drm/nouveau/nvkm/engine/{software => sw}/nvc0.c (66%)
diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h
index 7f1770beff21..90e2d9706f23 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/device.h
@@ -53,7 +53,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
#include <engine/device.h>
#include <engine/fifo.h>
#include <engine/gr.h>
-#include <engine/software.h>
+#include <engine/sw.h>
#define nvkm_fifo(a) nouveau_fifo(nvkm_device(a))
#define nvkm_fifo_chan(a) ((struct nouveau_fifo_chan *)nvkm_object(a))
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/software.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/software.h
deleted file mode 100644
index 23a462b50d03..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/software.h
+++ /dev/null
@@ -1,51 +0,0 @@
-#ifndef __NOUVEAU_SOFTWARE_H__
-#define __NOUVEAU_SOFTWARE_H__
-
-#include <core/engine.h>
-#include <core/engctx.h>
-
-struct nouveau_software_chan {
- struct nouveau_engctx base;
-
- int (*flip)(void *);
- void *flip_data;
-};
-
-#define nouveau_software_context_create(p,e,c,d) \
- nouveau_engctx_create((p), (e), (c), (p), 0, 0, 0, (d))
-#define nouveau_software_context_destroy(d) \
- nouveau_engctx_destroy(&(d)->base)
-#define nouveau_software_context_init(d) \
- nouveau_engctx_init(&(d)->base)
-#define nouveau_software_context_fini(d,s) \
- nouveau_engctx_fini(&(d)->base, (s))
-
-#define _nouveau_software_context_dtor _nouveau_engctx_dtor
-#define _nouveau_software_context_init _nouveau_engctx_init
-#define _nouveau_software_context_fini _nouveau_engctx_fini
-
-struct nouveau_software {
- struct nouveau_engine base;
-};
-
-#define nouveau_software_create(p,e,c,d) \
- nouveau_engine_create((p), (e), (c), true, "SW", "software", (d))
-#define nouveau_software_destroy(d) \
- nouveau_engine_destroy(&(d)->base)
-#define nouveau_software_init(d) \
- nouveau_engine_init(&(d)->base)
-#define nouveau_software_fini(d,s) \
- nouveau_engine_fini(&(d)->base, (s))
-
-#define _nouveau_software_dtor _nouveau_engine_dtor
-#define _nouveau_software_init _nouveau_engine_init
-#define _nouveau_software_fini _nouveau_engine_fini
-
-extern struct nouveau_oclass *nv04_software_oclass;
-extern struct nouveau_oclass *nv10_software_oclass;
-extern struct nouveau_oclass *nv50_software_oclass;
-extern struct nouveau_oclass *nvc0_software_oclass;
-
-void nv04_software_intr(struct nouveau_subdev *);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
new file mode 100644
index 000000000000..4c61a39222bb
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
@@ -0,0 +1,51 @@
+#ifndef __NOUVEAU_SW_H__
+#define __NOUVEAU_SW_H__
+
+#include <core/engine.h>
+#include <core/engctx.h>
+
+struct nouveau_sw_chan {
+ struct nouveau_engctx base;
+
+ int (*flip)(void *);
+ void *flip_data;
+};
+
+#define nouveau_sw_context_create(p,e,c,d) \
+ nouveau_engctx_create((p), (e), (c), (p), 0, 0, 0, (d))
+#define nouveau_sw_context_destroy(d) \
+ nouveau_engctx_destroy(&(d)->base)
+#define nouveau_sw_context_init(d) \
+ nouveau_engctx_init(&(d)->base)
+#define nouveau_sw_context_fini(d,s) \
+ nouveau_engctx_fini(&(d)->base, (s))
+
+#define _nouveau_sw_context_dtor _nouveau_engctx_dtor
+#define _nouveau_sw_context_init _nouveau_engctx_init
+#define _nouveau_sw_context_fini _nouveau_engctx_fini
+
+struct nouveau_sw {
+ struct nouveau_engine base;
+};
+
+#define nouveau_sw_create(p,e,c,d) \
+ nouveau_engine_create((p), (e), (c), true, "SW", "software", (d))
+#define nouveau_sw_destroy(d) \
+ nouveau_engine_destroy(&(d)->base)
+#define nouveau_sw_init(d) \
+ nouveau_engine_init(&(d)->base)
+#define nouveau_sw_fini(d,s) \
+ nouveau_engine_fini(&(d)->base, (s))
+
+#define _nouveau_sw_dtor _nouveau_engine_dtor
+#define _nouveau_sw_init _nouveau_engine_init
+#define _nouveau_sw_fini _nouveau_engine_fini
+
+extern struct nouveau_oclass *nv04_sw_oclass;
+extern struct nouveau_oclass *nv10_sw_oclass;
+extern struct nouveau_oclass *nv50_sw_oclass;
+extern struct nouveau_oclass *nvc0_sw_oclass;
+
+void nv04_sw_intr(struct nouveau_subdev *);
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c
index 80302530ead7..58b8b6423026 100644
--- a/drivers/gpu/drm/nouveau/nouveau_chan.c
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.c
@@ -282,7 +282,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
struct nvif_device *device = chan->device;
struct nouveau_cli *cli = (void *)nvif_client(&device->base);
struct nouveau_mmu *mmu = nvkm_mmu(device);
- struct nouveau_software_chan *swch;
+ struct nouveau_sw_chan *swch;
struct nv_dma_v0 args = {};
int ret, i;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 1118efa56817..e684040ccf11 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -231,7 +231,7 @@ nouveau_accel_init(struct nouveau_drm *drm)
ret = nvif_object_init(drm->channel->object, NULL, NVDRM_NVSW,
nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw);
if (ret == 0) {
- struct nouveau_software_chan *swch;
+ struct nouveau_sw_chan *swch;
ret = RING_SPACE(drm->channel, 2);
if (ret == 0) {
if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index 43a96b99e180..7226f1f60901 100644
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -72,7 +72,7 @@
# define NV_RAMHT_CONTEXT_VALID (1<<31)
# define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24
# define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16
-# define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0
+# define NV_RAMHT_CONTEXT_ENGINE_SW 0
# define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1
# define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0
# define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
index 0607d595f6e7..bc51b0581ba5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
@@ -14,5 +14,5 @@ include $(src)/nvkm/engine/msvld/Kbuild
include $(src)/nvkm/engine/pm/Kbuild
include $(src)/nvkm/engine/msppp/Kbuild
include $(src)/nvkm/engine/sec/Kbuild
-include $(src)/nvkm/engine/software/Kbuild
+include $(src)/nvkm/engine/sw/Kbuild
include $(src)/nvkm/engine/vp/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 690250503332..55e463396c8c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -45,7 +45,7 @@
#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/disp.h>
#include <engine/ce.h>
@@ -85,7 +85,7 @@ gm100_identify(struct nouveau_device *device)
#endif
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -129,7 +129,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
#if 0
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
#endif
device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index dcb53917b5e0..1d409af560da 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -36,7 +36,7 @@
#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/disp.h>
@@ -58,7 +58,7 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -76,7 +76,7 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index f292e7b88628..66d8c338ae98 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -37,7 +37,7 @@
#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/disp.h>
@@ -77,7 +77,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -96,7 +96,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -115,7 +115,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -134,7 +134,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -153,7 +153,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -172,7 +172,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -191,7 +191,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index a03420ca82b1..59cefdd46897 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -38,7 +38,7 @@
#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/disp.h>
@@ -61,7 +61,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -80,7 +80,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -99,7 +99,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -118,7 +118,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index 59b6baa64b4c..dfb610f837b0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -37,7 +37,7 @@
#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/mpeg.h>
#include <engine/disp.h>
@@ -61,7 +61,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -80,7 +80,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -99,7 +99,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -119,7 +119,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -139,7 +139,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index cd859b081db4..7bdb7d6729b7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -40,7 +40,7 @@
#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/mpeg.h>
#include <engine/disp.h>
@@ -67,7 +67,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -90,7 +90,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -113,7 +113,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -136,7 +136,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -159,7 +159,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -182,7 +182,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -205,7 +205,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -228,7 +228,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -251,7 +251,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -274,7 +274,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -297,7 +297,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -320,7 +320,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -343,7 +343,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -366,7 +366,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -389,7 +389,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -412,7 +412,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 3f3d2ea1a930..13203f53c80d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -43,7 +43,7 @@
#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/mpeg.h>
#include <engine/vp.h>
@@ -80,7 +80,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
@@ -106,7 +106,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
@@ -135,7 +135,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
@@ -164,7 +164,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
@@ -193,7 +193,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
@@ -222,7 +222,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
@@ -251,7 +251,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
@@ -280,7 +280,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
@@ -309,7 +309,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
@@ -338,7 +338,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
@@ -368,7 +368,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
@@ -399,7 +399,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
@@ -429,7 +429,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
@@ -459,7 +459,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index b241421e76a2..ae856f8bcc75 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -45,7 +45,7 @@
#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/vp.h>
#include <engine/bsp.h>
@@ -82,7 +82,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -115,7 +115,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -148,7 +148,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -180,7 +180,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -213,7 +213,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -245,7 +245,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -277,7 +277,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -310,7 +310,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -340,7 +340,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index df975987b9ca..13934f2b9cbd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -45,7 +45,7 @@
#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/disp.h>
#include <engine/ce.h>
@@ -82,7 +82,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -116,7 +116,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -150,7 +150,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -176,7 +176,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
@@ -206,7 +206,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -240,7 +240,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -274,7 +274,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -307,7 +307,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
index e2ad0543fb31..26aaa2a201e5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
@@ -22,7 +22,7 @@
* Authors: Ben Skeggs
*/
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/disp.h>
#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
index 672ded79b2a9..40b44f990990 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
@@ -22,7 +22,7 @@
* Authors: Ben Skeggs
*/
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/disp.h>
#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c
index 13eff5e4ee51..547926678710 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c
@@ -22,7 +22,7 @@
* Authors: Ben Skeggs
*/
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/disp.h>
#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c
index 2bb7ac5cd0e6..c009be4fb11c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c
@@ -22,7 +22,7 @@
* Authors: Ben Skeggs
*/
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/disp.h>
#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c
index b32456c9494f..317fd1a22076 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c
@@ -22,7 +22,7 @@
* Authors: Ben Skeggs
*/
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/disp.h>
#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c
index 951d79f9b781..af9441338239 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c
@@ -22,7 +22,7 @@
* Authors: Ben Skeggs
*/
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/disp.h>
#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c
index 55debec7e68f..063cb4ad304c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c
@@ -22,7 +22,7 @@
* Authors: Ben Skeggs
*/
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/disp.h>
#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c
index 3e7e2d28744c..3fd9b462d51f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c
@@ -22,7 +22,7 @@
* Authors: Ben Skeggs
*/
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/disp.h>
#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild
deleted file mode 100644
index e1332a15dc1b..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild
+++ /dev/null
@@ -1,4 +0,0 @@
-nvkm-y += nvkm/engine/software/nv04.o
-nvkm-y += nvkm/engine/software/nv10.o
-nvkm-y += nvkm/engine/software/nv50.o
-nvkm-y += nvkm/engine/software/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h
deleted file mode 100644
index 41542e725b4b..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef __NVKM_SW_NV50_H__
-#define __NVKM_SW_NV50_H__
-
-#include <engine/software.h>
-
-struct nv50_software_oclass {
- struct nouveau_oclass base;
- struct nouveau_oclass *cclass;
- struct nouveau_oclass *sclass;
-};
-
-struct nv50_software_priv {
- struct nouveau_software base;
-};
-
-int nv50_software_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-
-struct nv50_software_cclass {
- struct nouveau_oclass base;
- int (*vblank)(struct nvkm_notify *);
-};
-
-struct nv50_software_chan {
- struct nouveau_software_chan base;
- struct {
- struct nvkm_notify notify[4];
- u32 channel;
- u32 ctxdma;
- u64 offset;
- u32 value;
- } vblank;
-};
-
-int nv50_software_context_ctor(struct nouveau_object *,
- struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nv50_software_context_dtor(struct nouveau_object *);
-
-int nv50_software_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32);
-int nv50_software_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32);
-int nv50_software_mthd_flip(struct nouveau_object *, u32, void *, u32);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild
new file mode 100644
index 000000000000..b8d215900fce
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild
@@ -0,0 +1,4 @@
+nvkm-y += nvkm/engine/sw/nv04.o
+nvkm-y += nvkm/engine/sw/nv10.o
+nvkm-y += nvkm/engine/sw/nv50.o
+nvkm-y += nvkm/engine/sw/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
similarity index 66%
rename from drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
index 64df15c7f051..3d0e4bc76389 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
@@ -25,15 +25,15 @@
#include <core/os.h>
#include <core/engctx.h>
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/fifo.h>
-struct nv04_software_priv {
- struct nouveau_software base;
+struct nv04_sw_priv {
+ struct nouveau_sw base;
};
-struct nv04_software_chan {
- struct nouveau_software_chan base;
+struct nv04_sw_chan {
+ struct nouveau_sw_chan base;
};
/*******************************************************************************
@@ -41,7 +41,7 @@ struct nv04_software_chan {
******************************************************************************/
static int
-nv04_software_set_ref(struct nouveau_object *object, u32 mthd,
+nv04_sw_set_ref(struct nouveau_object *object, u32 mthd,
void *data, u32 size)
{
struct nouveau_object *channel = (void *)nv_engctx(object->parent);
@@ -51,25 +51,25 @@ nv04_software_set_ref(struct nouveau_object *object, u32 mthd,
}
static int
-nv04_software_flip(struct nouveau_object *object, u32 mthd,
+nv04_sw_flip(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv04_software_chan *chan = (void *)nv_engctx(object->parent);
+ struct nv04_sw_chan *chan = (void *)nv_engctx(object->parent);
if (chan->base.flip)
return chan->base.flip(chan->base.flip_data);
return -EINVAL;
}
static struct nouveau_omthds
-nv04_software_omthds[] = {
- { 0x0150, 0x0150, nv04_software_set_ref },
- { 0x0500, 0x0500, nv04_software_flip },
+nv04_sw_omthds[] = {
+ { 0x0150, 0x0150, nv04_sw_set_ref },
+ { 0x0500, 0x0500, nv04_sw_flip },
{}
};
static struct nouveau_oclass
-nv04_software_sclass[] = {
- { 0x006e, &nouveau_object_ofuncs, nv04_software_omthds },
+nv04_sw_sclass[] = {
+ { 0x006e, &nouveau_object_ofuncs, nv04_sw_omthds },
{}
};
@@ -78,15 +78,15 @@ nv04_software_sclass[] = {
******************************************************************************/
static int
-nv04_software_context_ctor(struct nouveau_object *parent,
+nv04_sw_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv04_software_chan *chan;
+ struct nv04_sw_chan *chan;
int ret;
- ret = nouveau_software_context_create(parent, engine, oclass, &chan);
+ ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -95,13 +95,13 @@ nv04_software_context_ctor(struct nouveau_object *parent,
}
static struct nouveau_oclass
-nv04_software_cclass = {
+nv04_sw_cclass = {
.handle = NV_ENGCTX(SW, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv04_software_context_ctor,
- .dtor = _nouveau_software_context_dtor,
- .init = _nouveau_software_context_init,
- .fini = _nouveau_software_context_fini,
+ .ctor = nv04_sw_context_ctor,
+ .dtor = _nouveau_sw_context_dtor,
+ .init = _nouveau_sw_context_init,
+ .fini = _nouveau_sw_context_fini,
},
};
@@ -110,37 +110,37 @@ nv04_software_cclass = {
******************************************************************************/
void
-nv04_software_intr(struct nouveau_subdev *subdev)
+nv04_sw_intr(struct nouveau_subdev *subdev)
{
nv_mask(subdev, 0x000100, 0x80000000, 0x00000000);
}
static int
-nv04_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv04_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv04_software_priv *priv;
+ struct nv04_sw_priv *priv;
int ret;
- ret = nouveau_software_create(parent, engine, oclass, &priv);
+ ret = nouveau_sw_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- nv_engine(priv)->cclass = &nv04_software_cclass;
- nv_engine(priv)->sclass = nv04_software_sclass;
- nv_subdev(priv)->intr = nv04_software_intr;
+ nv_engine(priv)->cclass = &nv04_sw_cclass;
+ nv_engine(priv)->sclass = nv04_sw_sclass;
+ nv_subdev(priv)->intr = nv04_sw_intr;
return 0;
}
struct nouveau_oclass *
-nv04_software_oclass = &(struct nouveau_oclass) {
+nv04_sw_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(SW, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv04_software_ctor,
- .dtor = _nouveau_software_dtor,
- .init = _nouveau_software_init,
- .fini = _nouveau_software_fini,
+ .ctor = nv04_sw_ctor,
+ .dtor = _nouveau_sw_dtor,
+ .init = _nouveau_sw_init,
+ .fini = _nouveau_sw_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
similarity index 66%
rename from drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
index f54a2253deca..12775cdbde70 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
@@ -25,14 +25,14 @@
#include <core/os.h>
#include <core/engctx.h>
-#include <engine/software.h>
+#include <engine/sw.h>
-struct nv10_software_priv {
- struct nouveau_software base;
+struct nv10_sw_priv {
+ struct nouveau_sw base;
};
-struct nv10_software_chan {
- struct nouveau_software_chan base;
+struct nv10_sw_chan {
+ struct nouveau_sw_chan base;
};
/*******************************************************************************
@@ -40,24 +40,24 @@ struct nv10_software_chan {
******************************************************************************/
static int
-nv10_software_flip(struct nouveau_object *object, u32 mthd,
+nv10_sw_flip(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv10_software_chan *chan = (void *)nv_engctx(object->parent);
+ struct nv10_sw_chan *chan = (void *)nv_engctx(object->parent);
if (chan->base.flip)
return chan->base.flip(chan->base.flip_data);
return -EINVAL;
}
static struct nouveau_omthds
-nv10_software_omthds[] = {
- { 0x0500, 0x0500, nv10_software_flip },
+nv10_sw_omthds[] = {
+ { 0x0500, 0x0500, nv10_sw_flip },
{}
};
static struct nouveau_oclass
-nv10_software_sclass[] = {
- { 0x016e, &nouveau_object_ofuncs, nv10_software_omthds },
+nv10_sw_sclass[] = {
+ { 0x016e, &nouveau_object_ofuncs, nv10_sw_omthds },
{}
};
@@ -66,15 +66,15 @@ nv10_software_sclass[] = {
******************************************************************************/
static int
-nv10_software_context_ctor(struct nouveau_object *parent,
+nv10_sw_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv10_software_chan *chan;
+ struct nv10_sw_chan *chan;
int ret;
- ret = nouveau_software_context_create(parent, engine, oclass, &chan);
+ ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -83,13 +83,13 @@ nv10_software_context_ctor(struct nouveau_object *parent,
}
static struct nouveau_oclass
-nv10_software_cclass = {
+nv10_sw_cclass = {
.handle = NV_ENGCTX(SW, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv10_software_context_ctor,
- .dtor = _nouveau_software_context_dtor,
- .init = _nouveau_software_context_init,
- .fini = _nouveau_software_context_fini,
+ .ctor = nv10_sw_context_ctor,
+ .dtor = _nouveau_sw_context_dtor,
+ .init = _nouveau_sw_context_init,
+ .fini = _nouveau_sw_context_fini,
},
};
@@ -98,31 +98,31 @@ nv10_software_cclass = {
******************************************************************************/
static int
-nv10_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv10_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv10_software_priv *priv;
+ struct nv10_sw_priv *priv;
int ret;
- ret = nouveau_software_create(parent, engine, oclass, &priv);
+ ret = nouveau_sw_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- nv_engine(priv)->cclass = &nv10_software_cclass;
- nv_engine(priv)->sclass = nv10_software_sclass;
- nv_subdev(priv)->intr = nv04_software_intr;
+ nv_engine(priv)->cclass = &nv10_sw_cclass;
+ nv_engine(priv)->sclass = nv10_sw_sclass;
+ nv_subdev(priv)->intr = nv04_sw_intr;
return 0;
}
struct nouveau_oclass *
-nv10_software_oclass = &(struct nouveau_oclass) {
+nv10_sw_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(SW, 0x10),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv10_software_ctor,
- .dtor = _nouveau_software_dtor,
- .init = _nouveau_software_init,
- .fini = _nouveau_software_fini,
+ .ctor = nv10_sw_ctor,
+ .dtor = _nouveau_sw_dtor,
+ .init = _nouveau_sw_init,
+ .fini = _nouveau_sw_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
similarity index 66%
rename from drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
index a0fec205f9db..a214a4debcc4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
@@ -41,10 +41,10 @@
******************************************************************************/
static int
-nv50_software_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
+nv50_sw_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
struct nouveau_fifo_chan *fifo = (void *)nv_object(chan)->parent;
struct nouveau_handle *handle;
int ret = -EINVAL;
@@ -63,28 +63,28 @@ nv50_software_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
}
static int
-nv50_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
+nv50_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
chan->vblank.offset = *(u32 *)args;
return 0;
}
int
-nv50_software_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
+nv50_sw_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
chan->vblank.value = *(u32 *)args;
return 0;
}
int
-nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
+nv50_sw_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
u32 head = *(u32 *)args;
if (head >= nouveau_disp(chan)->vblank.index_nr)
return -EINVAL;
@@ -94,28 +94,28 @@ nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
}
int
-nv50_software_mthd_flip(struct nouveau_object *object, u32 mthd,
+nv50_sw_mthd_flip(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
if (chan->base.flip)
return chan->base.flip(chan->base.flip_data);
return -EINVAL;
}
static struct nouveau_omthds
-nv50_software_omthds[] = {
- { 0x018c, 0x018c, nv50_software_mthd_dma_vblsem },
- { 0x0400, 0x0400, nv50_software_mthd_vblsem_offset },
- { 0x0404, 0x0404, nv50_software_mthd_vblsem_value },
- { 0x0408, 0x0408, nv50_software_mthd_vblsem_release },
- { 0x0500, 0x0500, nv50_software_mthd_flip },
+nv50_sw_omthds[] = {
+ { 0x018c, 0x018c, nv50_sw_mthd_dma_vblsem },
+ { 0x0400, 0x0400, nv50_sw_mthd_vblsem_offset },
+ { 0x0404, 0x0404, nv50_sw_mthd_vblsem_value },
+ { 0x0408, 0x0408, nv50_sw_mthd_vblsem_release },
+ { 0x0500, 0x0500, nv50_sw_mthd_flip },
{}
};
static struct nouveau_oclass
-nv50_software_sclass[] = {
- { 0x506e, &nouveau_object_ofuncs, nv50_software_omthds },
+nv50_sw_sclass[] = {
+ { 0x506e, &nouveau_object_ofuncs, nv50_sw_omthds },
{}
};
@@ -124,11 +124,11 @@ nv50_software_sclass[] = {
******************************************************************************/
static int
-nv50_software_vblsem_release(struct nvkm_notify *notify)
+nv50_sw_vblsem_release(struct nvkm_notify *notify)
{
- struct nv50_software_chan *chan =
+ struct nv50_sw_chan *chan =
container_of(notify, typeof(*chan), vblank.notify[notify->index]);
- struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
+ struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
struct nouveau_bar *bar = nouveau_bar(priv);
nv_wr32(priv, 0x001704, chan->vblank.channel);
@@ -147,29 +147,29 @@ nv50_software_vblsem_release(struct nvkm_notify *notify)
}
void
-nv50_software_context_dtor(struct nouveau_object *object)
+nv50_sw_context_dtor(struct nouveau_object *object)
{
- struct nv50_software_chan *chan = (void *)object;
+ struct nv50_sw_chan *chan = (void *)object;
int i;
for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++)
nvkm_notify_fini(&chan->vblank.notify[i]);
- nouveau_software_context_destroy(&chan->base);
+ nouveau_sw_context_destroy(&chan->base);
}
int
-nv50_software_context_ctor(struct nouveau_object *parent,
+nv50_sw_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_disp *pdisp = nouveau_disp(parent);
- struct nv50_software_cclass *pclass = (void *)oclass;
- struct nv50_software_chan *chan;
+ struct nv50_sw_cclass *pclass = (void *)oclass;
+ struct nv50_sw_chan *chan;
int ret, i;
- ret = nouveau_software_context_create(parent, engine, oclass, &chan);
+ ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -191,16 +191,16 @@ nv50_software_context_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nv50_software_cclass
-nv50_software_cclass = {
+static struct nv50_sw_cclass
+nv50_sw_cclass = {
.base.handle = NV_ENGCTX(SW, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv50_software_context_ctor,
- .dtor = nv50_software_context_dtor,
- .init = _nouveau_software_context_init,
- .fini = _nouveau_software_context_fini,
+ .ctor = nv50_sw_context_ctor,
+ .dtor = nv50_sw_context_dtor,
+ .init = _nouveau_sw_context_init,
+ .fini = _nouveau_sw_context_fini,
},
- .vblank = nv50_software_vblsem_release,
+ .vblank = nv50_sw_vblsem_release,
};
/*******************************************************************************
@@ -208,34 +208,34 @@ nv50_software_cclass = {
******************************************************************************/
int
-nv50_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv50_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv50_software_oclass *pclass = (void *)oclass;
- struct nv50_software_priv *priv;
+ struct nv50_sw_oclass *pclass = (void *)oclass;
+ struct nv50_sw_priv *priv;
int ret;
- ret = nouveau_software_create(parent, engine, oclass, &priv);
+ ret = nouveau_sw_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_engine(priv)->cclass = pclass->cclass;
nv_engine(priv)->sclass = pclass->sclass;
- nv_subdev(priv)->intr = nv04_software_intr;
+ nv_subdev(priv)->intr = nv04_sw_intr;
return 0;
}
struct nouveau_oclass *
-nv50_software_oclass = &(struct nv50_software_oclass) {
+nv50_sw_oclass = &(struct nv50_sw_oclass) {
.base.handle = NV_ENGINE(SW, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv50_software_ctor,
- .dtor = _nouveau_software_dtor,
- .init = _nouveau_software_init,
- .fini = _nouveau_software_fini,
+ .ctor = nv50_sw_ctor,
+ .dtor = _nouveau_sw_dtor,
+ .init = _nouveau_sw_init,
+ .fini = _nouveau_sw_fini,
},
- .cclass = &nv50_software_cclass.base,
- .sclass = nv50_software_sclass,
+ .cclass = &nv50_sw_cclass.base,
+ .sclass = nv50_sw_sclass,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
new file mode 100644
index 000000000000..618e41fa36d0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
@@ -0,0 +1,46 @@
+#ifndef __NVKM_SW_NV50_H__
+#define __NVKM_SW_NV50_H__
+
+#include <engine/sw.h>
+
+struct nv50_sw_oclass {
+ struct nouveau_oclass base;
+ struct nouveau_oclass *cclass;
+ struct nouveau_oclass *sclass;
+};
+
+struct nv50_sw_priv {
+ struct nouveau_sw base;
+};
+
+int nv50_sw_ctor(struct nouveau_object *, struct nouveau_object *,
+ struct nouveau_oclass *, void *, u32,
+ struct nouveau_object **);
+
+struct nv50_sw_cclass {
+ struct nouveau_oclass base;
+ int (*vblank)(struct nvkm_notify *);
+};
+
+struct nv50_sw_chan {
+ struct nouveau_sw_chan base;
+ struct {
+ struct nvkm_notify notify[4];
+ u32 channel;
+ u32 ctxdma;
+ u64 offset;
+ u32 value;
+ } vblank;
+};
+
+int nv50_sw_context_ctor(struct nouveau_object *,
+ struct nouveau_object *,
+ struct nouveau_oclass *, void *, u32,
+ struct nouveau_object **);
+void nv50_sw_context_dtor(struct nouveau_object *);
+
+int nv50_sw_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32);
+int nv50_sw_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32);
+int nv50_sw_mthd_flip(struct nouveau_object *, u32, void *, u32);
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c
similarity index 66%
rename from drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c
index 6af370d3a06d..dcb056eae471 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c
@@ -28,7 +28,7 @@
#include <subdev/bar.h>
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/disp.h>
#include "nv50.h"
@@ -38,10 +38,10 @@
******************************************************************************/
static int
-nvc0_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
+nvc0_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
u64 data = *(u32 *)args;
if (mthd == 0x0400) {
chan->vblank.offset &= 0x00ffffffffULL;
@@ -54,11 +54,11 @@ nvc0_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
}
static int
-nvc0_software_mthd_mp_control(struct nouveau_object *object, u32 mthd,
+nvc0_sw_mthd_mp_control(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
- struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
+ struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
u32 data = *(u32 *)args;
switch (mthd) {
@@ -80,21 +80,21 @@ nvc0_software_mthd_mp_control(struct nouveau_object *object, u32 mthd,
}
static struct nouveau_omthds
-nvc0_software_omthds[] = {
- { 0x0400, 0x0400, nvc0_software_mthd_vblsem_offset },
- { 0x0404, 0x0404, nvc0_software_mthd_vblsem_offset },
- { 0x0408, 0x0408, nv50_software_mthd_vblsem_value },
- { 0x040c, 0x040c, nv50_software_mthd_vblsem_release },
- { 0x0500, 0x0500, nv50_software_mthd_flip },
- { 0x0600, 0x0600, nvc0_software_mthd_mp_control },
- { 0x0644, 0x0644, nvc0_software_mthd_mp_control },
- { 0x06ac, 0x06ac, nvc0_software_mthd_mp_control },
+nvc0_sw_omthds[] = {
+ { 0x0400, 0x0400, nvc0_sw_mthd_vblsem_offset },
+ { 0x0404, 0x0404, nvc0_sw_mthd_vblsem_offset },
+ { 0x0408, 0x0408, nv50_sw_mthd_vblsem_value },
+ { 0x040c, 0x040c, nv50_sw_mthd_vblsem_release },
+ { 0x0500, 0x0500, nv50_sw_mthd_flip },
+ { 0x0600, 0x0600, nvc0_sw_mthd_mp_control },
+ { 0x0644, 0x0644, nvc0_sw_mthd_mp_control },
+ { 0x06ac, 0x06ac, nvc0_sw_mthd_mp_control },
{}
};
static struct nouveau_oclass
-nvc0_software_sclass[] = {
- { 0x906e, &nouveau_object_ofuncs, nvc0_software_omthds },
+nvc0_sw_sclass[] = {
+ { 0x906e, &nouveau_object_ofuncs, nvc0_sw_omthds },
{}
};
@@ -103,11 +103,11 @@ nvc0_software_sclass[] = {
******************************************************************************/
static int
-nvc0_software_vblsem_release(struct nvkm_notify *notify)
+nvc0_sw_vblsem_release(struct nvkm_notify *notify)
{
- struct nv50_software_chan *chan =
+ struct nv50_sw_chan *chan =
container_of(notify, typeof(*chan), vblank.notify[notify->index]);
- struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
+ struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
struct nouveau_bar *bar = nouveau_bar(priv);
nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
@@ -119,16 +119,16 @@ nvc0_software_vblsem_release(struct nvkm_notify *notify)
return NVKM_NOTIFY_DROP;
}
-static struct nv50_software_cclass
-nvc0_software_cclass = {
+static struct nv50_sw_cclass
+nvc0_sw_cclass = {
.base.handle = NV_ENGCTX(SW, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv50_software_context_ctor,
- .dtor = nv50_software_context_dtor,
- .init = _nouveau_software_context_init,
- .fini = _nouveau_software_context_fini,
+ .ctor = nv50_sw_context_ctor,
+ .dtor = nv50_sw_context_dtor,
+ .init = _nouveau_sw_context_init,
+ .fini = _nouveau_sw_context_fini,
},
- .vblank = nvc0_software_vblsem_release,
+ .vblank = nvc0_sw_vblsem_release,
};
/*******************************************************************************
@@ -136,14 +136,14 @@ nvc0_software_cclass = {
******************************************************************************/
struct nouveau_oclass *
-nvc0_software_oclass = &(struct nv50_software_oclass) {
+nvc0_sw_oclass = &(struct nv50_sw_oclass) {
.base.handle = NV_ENGINE(SW, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv50_software_ctor,
- .dtor = _nouveau_software_dtor,
- .init = _nouveau_software_init,
- .fini = _nouveau_software_fini,
+ .ctor = nv50_sw_ctor,
+ .dtor = _nouveau_sw_dtor,
+ .init = _nouveau_sw_init,
+ .fini = _nouveau_sw_fini,
},
- .cclass = &nvc0_software_cclass.base,
- .sclass = nvc0_software_sclass,
+ .cclass = &nvc0_sw_cclass.base,
+ .sclass = nvc0_sw_sclass,
}.base;
From bd8369ecf5e7f5fce9f72b2934dc43a844134a13 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 12:37:00 +1000
Subject: [PATCH 47/86] drm/nouveau/msenc: rename from venc (no binary change)
Switch to NVIDIA's name for the device.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/include/nvif/class.h | 2 +-
drivers/gpu/drm/nouveau/include/nvkm/core/device.h | 2 +-
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c | 6 +++---
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c | 2 +-
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h
index e35988aa255b..157f59afa8bf 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
@@ -132,7 +132,7 @@ struct nv_device_v0 {
#define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL
#define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL
#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
-#define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL
+#define NV_DEVICE_V0_DISABLE_MSENC 0x0000040000000000ULL
#define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL
#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL
#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 1a6a49c7f84b..ddc3d5d49817 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -56,7 +56,7 @@ enum nv_subdev_type {
NVDEV_ENGINE_CE1,
NVDEV_ENGINE_CE2,
NVDEV_ENGINE_VIC,
- NVDEV_ENGINE_VENC,
+ NVDEV_ENGINE_MSENC,
NVDEV_ENGINE_DISP,
NVDEV_ENGINE_PM,
NVDEV_ENGINE_MSVLD,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index fda8d729aa30..60f538976f3b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -239,7 +239,7 @@ static const u64 disable_map[] = {
[NVDEV_ENGINE_CE1] = NV_DEVICE_V0_DISABLE_CE1,
[NVDEV_ENGINE_CE2] = NV_DEVICE_V0_DISABLE_CE2,
[NVDEV_ENGINE_VIC] = NV_DEVICE_V0_DISABLE_VIC,
- [NVDEV_ENGINE_VENC] = NV_DEVICE_V0_DISABLE_VENC,
+ [NVDEV_ENGINE_MSENC] = NV_DEVICE_V0_DISABLE_MSENC,
[NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP,
[NVDEV_ENGINE_MSVLD] = NV_DEVICE_V0_DISABLE_MSVLD,
[NVDEV_ENGINE_SEC] = NV_DEVICE_V0_DISABLE_SEC,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
index 81dc280c0022..ea31e2de3eab 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
@@ -53,7 +53,7 @@ static const struct {
_(NVDEV_ENGINE_MSVLD , 0),
_(NVDEV_ENGINE_CE0 , 0),
_(NVDEV_ENGINE_CE1 , 0),
- _(NVDEV_ENGINE_VENC , 0),
+ _(NVDEV_ENGINE_MSENC , 0),
};
#undef _
#define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine)
@@ -421,7 +421,7 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
case NVDEV_ENGINE_VP : engn = 3; break;
case NVDEV_ENGINE_CE0 : engn = 4; break;
case NVDEV_ENGINE_CE1 : engn = 5; break;
- case NVDEV_ENGINE_VENC : engn = 6; break;
+ case NVDEV_ENGINE_MSENC: engn = 6; break;
default:
return -1;
}
@@ -626,7 +626,7 @@ nve0_fifo_fault_engine[] = {
{ 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },
{ 0x16, "CE1", NULL, NVDEV_ENGINE_CE1 },
{ 0x17, "PMU" },
- { 0x19, "MSENC", NULL, NVDEV_ENGINE_VENC },
+ { 0x19, "MSENC", NULL, NVDEV_ENGINE_MSENC },
{ 0x1b, "CE2", NULL, NVDEV_ENGINE_CE2 },
{}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
index 4fbe8e9c97f0..4ad22a48ff3a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
@@ -77,7 +77,7 @@ nvc0_devinit_disable(struct nouveau_devinit *devinit)
if (r022500 & 0x00000004)
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
if (r022500 & 0x00000008)
- disable |= (1ULL << NVDEV_ENGINE_VENC);
+ disable |= (1ULL << NVDEV_ENGINE_MSENC);
if (r022500 & 0x00000100)
disable |= (1ULL << NVDEV_ENGINE_CE0);
if (r022500 & 0x00000200)
From 37a5d028913f7ac614cd79b1e7adaff19c59d2f1 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 12:50:04 +1000
Subject: [PATCH 48/86] drm/nouveau/mspdec: separate from vp
Switch to NVIDIA's name for the device.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/include/nvif/class.h | 3 +-
.../drm/nouveau/include/nvkm/core/device.h | 1 +
.../drm/nouveau/include/nvkm/engine/mspdec.h | 6 +++
.../gpu/drm/nouveau/include/nvkm/engine/vp.h | 5 --
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 5 +-
.../drm/nouveau/nvkm/engine/device/gm100.c | 6 +--
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 15 +++---
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 20 ++++----
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 16 +++----
.../gpu/drm/nouveau/nvkm/engine/fifo/nv84.c | 11 +++--
.../gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c | 46 +++++++++----------
.../gpu/drm/nouveau/nvkm/engine/fifo/nve0.c | 44 +++++++++---------
.../gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild | 3 ++
.../nouveau/nvkm/engine/{vp => mspdec}/nv98.c | 38 +++++++--------
.../nouveau/nvkm/engine/{vp => mspdec}/nvc0.c | 38 +++++++--------
.../nouveau/nvkm/engine/{vp => mspdec}/nve0.c | 38 +++++++--------
drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild | 3 --
drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild | 2 +-
.../drm/nouveau/nvkm/subdev/devinit/nv98.c | 2 +-
.../drm/nouveau/nvkm/subdev/devinit/nva3.c | 2 +-
.../drm/nouveau/nvkm/subdev/devinit/nvaf.c | 2 +-
.../drm/nouveau/nvkm/subdev/devinit/nvc0.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 2 +
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 3 +-
26 files changed, 165 insertions(+), 152 deletions(-)
create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild
rename drivers/gpu/drm/nouveau/nvkm/engine/{vp => mspdec}/nv98.c (80%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{vp => mspdec}/nvc0.c (80%)
rename drivers/gpu/drm/nouveau/nvkm/engine/{vp => mspdec}/nve0.c (80%)
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h
index 157f59afa8bf..5ad17fc36ae3 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
@@ -136,6 +136,7 @@ struct nv_device_v0 {
#define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL
#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL
#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL
+#define NV_DEVICE_V0_DISABLE_MSPDEC 0x0000400000000000ULL
__u64 disable; /* disable particular subsystems */
__u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */
};
@@ -348,7 +349,7 @@ struct nv50_channel_gpfifo_v0 {
struct kepler_channel_gpfifo_a_v0 {
__u8 version;
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index ddc3d5d49817..2b90ec900a8c 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -61,6 +61,7 @@ enum nv_subdev_type {
NVDEV_ENGINE_PM,
NVDEV_ENGINE_MSVLD,
NVDEV_ENGINE_SEC,
+ NVDEV_ENGINE_MSPDEC,
NVDEV_SUBDEV_NR,
};
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
new file mode 100644
index 000000000000..2457f871c2f7
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
@@ -0,0 +1,6 @@
+#ifndef __NVKM_MSPDEC_H__
+#define __NVKM_MSPDEC_H__
+extern struct nouveau_oclass nv98_mspdec_oclass;
+extern struct nouveau_oclass nvc0_mspdec_oclass;
+extern struct nouveau_oclass nve0_mspdec_oclass;
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
index 39baebec7fbb..7175e6e032cc 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
@@ -1,9 +1,4 @@
#ifndef __NOUVEAU_VP_H__
#define __NOUVEAU_VP_H__
-
extern struct nouveau_oclass nv84_vp_oclass;
-extern struct nouveau_oclass nv98_vp_oclass;
-extern struct nouveau_oclass nvc0_vp_oclass;
-extern struct nouveau_oclass nve0_vp_oclass;
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
index bc51b0581ba5..6bd3d756f32c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
@@ -2,17 +2,18 @@ nvkm-y += nvkm/engine/falcon.o
nvkm-y += nvkm/engine/xtensa.o
include $(src)/nvkm/engine/bsp/Kbuild
-include $(src)/nvkm/engine/cipher/Kbuild
include $(src)/nvkm/engine/ce/Kbuild
+include $(src)/nvkm/engine/cipher/Kbuild
include $(src)/nvkm/engine/device/Kbuild
include $(src)/nvkm/engine/disp/Kbuild
include $(src)/nvkm/engine/dmaobj/Kbuild
include $(src)/nvkm/engine/fifo/Kbuild
include $(src)/nvkm/engine/gr/Kbuild
include $(src)/nvkm/engine/mpeg/Kbuild
+include $(src)/nvkm/engine/mspdec/Kbuild
+include $(src)/nvkm/engine/msppp/Kbuild
include $(src)/nvkm/engine/msvld/Kbuild
include $(src)/nvkm/engine/pm/Kbuild
-include $(src)/nvkm/engine/msppp/Kbuild
include $(src)/nvkm/engine/sec/Kbuild
include $(src)/nvkm/engine/sw/Kbuild
include $(src)/nvkm/engine/vp/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 55e463396c8c..915ba957f075 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -51,7 +51,7 @@
#include <engine/ce.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
-#include <engine/vp.h>
+#include <engine/mspdec.h>
#include <engine/msppp.h>
#include <engine/pm.h>
@@ -95,7 +95,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
#if 0
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
#endif
break;
@@ -138,7 +138,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
#endif
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 13203f53c80d..4f100b261f28 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -51,6 +51,7 @@
#include <engine/sec.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
+#include <engine/mspdec.h>
#include <engine/msppp.h>
#include <engine/ce.h>
#include <engine/disp.h>
@@ -253,7 +254,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
@@ -311,7 +312,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
@@ -340,7 +341,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
@@ -371,7 +372,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
@@ -401,7 +402,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
@@ -431,7 +432,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
@@ -461,7 +462,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index ae856f8bcc75..2a6fc7f6fd85 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -47,7 +47,7 @@
#include <engine/fifo.h>
#include <engine/sw.h>
#include <engine/gr.h>
-#include <engine/vp.h>
+#include <engine/mspdec.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/msppp.h>
@@ -84,7 +84,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -117,7 +117,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -150,7 +150,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -182,7 +182,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -215,7 +215,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -247,7 +247,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -279,7 +279,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -312,7 +312,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -342,7 +342,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 13934f2b9cbd..b2225ec499b1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -51,7 +51,7 @@
#include <engine/ce.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
-#include <engine/vp.h>
+#include <engine/mspdec.h>
#include <engine/msppp.h>
#include <engine/pm.h>
@@ -89,7 +89,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
@@ -123,7 +123,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
@@ -157,7 +157,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
@@ -213,7 +213,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
@@ -247,7 +247,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
@@ -281,7 +281,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
break;
case 0x108:
@@ -314,7 +314,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
index 6abcd5c3e773..727358d8ac77 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
@@ -57,7 +57,8 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : addr = 0x0020; break;
- case NVDEV_ENGINE_VP : addr = 0x0040; break;
+ case NVDEV_ENGINE_VP :
+ case NVDEV_ENGINE_MSPDEC: addr = 0x0040; break;
case NVDEV_ENGINE_MSPPP :
case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
case NVDEV_ENGINE_BSP :
@@ -95,7 +96,8 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
- case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
+ case NVDEV_ENGINE_VP :
+ case NVDEV_ENGINE_MSPDEC: engn = 3; addr = 0x0040; break;
case NVDEV_ENGINE_MSPPP :
case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
case NVDEV_ENGINE_BSP :
@@ -148,7 +150,8 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_MSPPP : context |= 0x00200000; break;
case NVDEV_ENGINE_ME :
case NVDEV_ENGINE_CE0 : context |= 0x00300000; break;
- case NVDEV_ENGINE_VP : context |= 0x00400000; break;
+ case NVDEV_ENGINE_VP :
+ case NVDEV_ENGINE_MSPDEC: context |= 0x00400000; break;
case NVDEV_ENGINE_CIPHER:
case NVDEV_ENGINE_SEC :
case NVDEV_ENGINE_VIC : context |= 0x00500000; break;
@@ -195,6 +198,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_SEC) |
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
+ (1ULL << NVDEV_ENGINE_MSPDEC) |
(1ULL << NVDEV_ENGINE_MSPPP) |
(1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
@@ -270,6 +274,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_SEC) |
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
+ (1ULL << NVDEV_ENGINE_MSPDEC) |
(1ULL << NVDEV_ENGINE_MSPPP) |
(1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
index d86601c02368..6e05b0b706fa 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
@@ -120,13 +120,13 @@ nvc0_fifo_context_attach(struct nouveau_object *parent,
int ret;
switch (nv_engidx(object->engine)) {
- case NVDEV_ENGINE_SW : return 0;
- case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
- case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
- case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
- case NVDEV_ENGINE_VP : addr = 0x0250; break;
- case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
+ case NVDEV_ENGINE_SW : return 0;
+ case NVDEV_ENGINE_GR : addr = 0x0210; break;
+ case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
+ case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
+ case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
+ case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
+ case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
default:
return -EINVAL;
}
@@ -157,13 +157,13 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
u32 addr;
switch (nv_engidx(object->engine)) {
- case NVDEV_ENGINE_SW : return 0;
- case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
- case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
- case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
- case NVDEV_ENGINE_VP : addr = 0x0250; break;
- case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
+ case NVDEV_ENGINE_SW : return 0;
+ case NVDEV_ENGINE_GR : addr = 0x0210; break;
+ case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
+ case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
+ case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
+ case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
+ case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
default:
return -EINVAL;
}
@@ -215,7 +215,7 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_CE1) |
(1ULL << NVDEV_ENGINE_MSVLD) |
- (1ULL << NVDEV_ENGINE_VP) |
+ (1ULL << NVDEV_ENGINE_MSPDEC) |
(1ULL << NVDEV_ENGINE_MSPPP), &chan);
*pobject = nv_object(chan);
if (ret)
@@ -381,12 +381,12 @@ static inline int
nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
{
switch (engn) {
- case NVDEV_ENGINE_GR : engn = 0; break;
- case NVDEV_ENGINE_MSVLD: engn = 1; break;
- case NVDEV_ENGINE_MSPPP: engn = 2; break;
- case NVDEV_ENGINE_VP : engn = 3; break;
- case NVDEV_ENGINE_CE0 : engn = 4; break;
- case NVDEV_ENGINE_CE1 : engn = 5; break;
+ case NVDEV_ENGINE_GR : engn = 0; break;
+ case NVDEV_ENGINE_MSVLD : engn = 1; break;
+ case NVDEV_ENGINE_MSPPP : engn = 2; break;
+ case NVDEV_ENGINE_MSPDEC: engn = 3; break;
+ case NVDEV_ENGINE_CE0 : engn = 4; break;
+ case NVDEV_ENGINE_CE1 : engn = 5; break;
default:
return -1;
}
@@ -401,7 +401,7 @@ nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
case 0: engn = NVDEV_ENGINE_GR; break;
case 1: engn = NVDEV_ENGINE_MSVLD; break;
case 2: engn = NVDEV_ENGINE_MSPPP; break;
- case 3: engn = NVDEV_ENGINE_VP; break;
+ case 3: engn = NVDEV_ENGINE_MSPDEC; break;
case 4: engn = NVDEV_ENGINE_CE0; break;
case 5: engn = NVDEV_ENGINE_CE1; break;
default:
@@ -551,7 +551,7 @@ nvc0_fifo_fault_engine[] = {
{ 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD },
{ 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
{ 0x13, "PCOUNTER" },
- { 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
+ { 0x14, "PMSPDEC", NULL, NVDEV_ENGINE_MSPDEC },
{ 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 },
{ 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 },
{ 0x17, "PDAEMON" },
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
index ea31e2de3eab..f5965eb6b262 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
@@ -48,7 +48,7 @@ static const struct {
} fifo_engine[] = {
_(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_CE2)),
- _(NVDEV_ENGINE_VP , 0),
+ _(NVDEV_ENGINE_MSPDEC , 0),
_(NVDEV_ENGINE_MSPPP , 0),
_(NVDEV_ENGINE_MSVLD , 0),
_(NVDEV_ENGINE_CE0 , 0),
@@ -148,10 +148,10 @@ nve0_fifo_context_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_CE2:
nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
return 0;
- case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
- case NVDEV_ENGINE_VP : addr = 0x0250; break;
- case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
+ case NVDEV_ENGINE_GR : addr = 0x0210; break;
+ case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
+ case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
+ case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
default:
return -EINVAL;
}
@@ -182,14 +182,14 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
u32 addr;
switch (nv_engidx(object->engine)) {
- case NVDEV_ENGINE_SW : return 0;
- case NVDEV_ENGINE_CE0 :
- case NVDEV_ENGINE_CE1 :
- case NVDEV_ENGINE_CE2 : addr = 0x0000; break;
- case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
- case NVDEV_ENGINE_VP : addr = 0x0250; break;
- case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
+ case NVDEV_ENGINE_SW : return 0;
+ case NVDEV_ENGINE_CE0 :
+ case NVDEV_ENGINE_CE1 :
+ case NVDEV_ENGINE_CE2 : addr = 0x0000; break;
+ case NVDEV_ENGINE_GR : addr = 0x0210; break;
+ case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
+ case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
+ case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
default:
return -EINVAL;
}
@@ -414,14 +414,14 @@ static inline int
nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
{
switch (engn) {
- case NVDEV_ENGINE_GR :
- case NVDEV_ENGINE_CE2 : engn = 0; break;
- case NVDEV_ENGINE_MSVLD: engn = 1; break;
- case NVDEV_ENGINE_MSPPP: engn = 2; break;
- case NVDEV_ENGINE_VP : engn = 3; break;
- case NVDEV_ENGINE_CE0 : engn = 4; break;
- case NVDEV_ENGINE_CE1 : engn = 5; break;
- case NVDEV_ENGINE_MSENC: engn = 6; break;
+ case NVDEV_ENGINE_GR :
+ case NVDEV_ENGINE_CE2 : engn = 0; break;
+ case NVDEV_ENGINE_MSVLD : engn = 1; break;
+ case NVDEV_ENGINE_MSPPP : engn = 2; break;
+ case NVDEV_ENGINE_MSPDEC: engn = 3; break;
+ case NVDEV_ENGINE_CE0 : engn = 4; break;
+ case NVDEV_ENGINE_CE1 : engn = 5; break;
+ case NVDEV_ENGINE_MSENC : engn = 6; break;
default:
return -1;
}
@@ -622,7 +622,7 @@ nve0_fifo_fault_engine[] = {
{ 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD },
{ 0x11, "MSPPP", NULL, NVDEV_ENGINE_MSPPP },
{ 0x13, "PERF" },
- { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
+ { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_MSPDEC },
{ 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },
{ 0x16, "CE1", NULL, NVDEV_ENGINE_CE1 },
{ 0x17, "PMU" },
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild
new file mode 100644
index 000000000000..c05281cbd9b8
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild
@@ -0,0 +1,3 @@
+nvkm-y += nvkm/engine/mspdec/nv98.o
+nvkm-y += nvkm/engine/mspdec/nvc0.o
+nvkm-y += nvkm/engine/mspdec/nve0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nv98.c
similarity index 80%
rename from drivers/gpu/drm/nouveau/nvkm/engine/vp/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nv98.c
index fc9ae0ff1ef5..d47df06bb223 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nv98.c
@@ -23,30 +23,30 @@
*/
#include <engine/falcon.h>
-#include <engine/vp.h>
+#include <engine/mspdec.h>
-struct nv98_vp_priv {
+struct nv98_mspdec_priv {
struct nouveau_falcon base;
};
/*******************************************************************************
- * VP object classes
+ * MSPDEC object classes
******************************************************************************/
static struct nouveau_oclass
-nv98_vp_sclass[] = {
+nv98_mspdec_sclass[] = {
{ 0x88b2, &nouveau_object_ofuncs },
{ 0x85b2, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
- * PVP context
+ * PMSPDEC context
******************************************************************************/
static struct nouveau_oclass
-nv98_vp_cclass = {
- .handle = NV_ENGCTX(VP, 0x98),
+nv98_mspdec_cclass = {
+ .handle = NV_ENGCTX(MSPDEC, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@@ -58,13 +58,13 @@ nv98_vp_cclass = {
};
/*******************************************************************************
- * PVP engine/subdev functions
+ * PMSPDEC engine/subdev functions
******************************************************************************/
static int
-nv98_vp_init(struct nouveau_object *object)
+nv98_mspdec_init(struct nouveau_object *object)
{
- struct nv98_vp_priv *priv = (void *)object;
+ struct nv98_mspdec_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
@@ -77,32 +77,32 @@ nv98_vp_init(struct nouveau_object *object)
}
static int
-nv98_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv98_mspdec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv98_vp_priv *priv;
+ struct nv98_mspdec_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,
- "PVP", "vp", &priv);
+ "PMSPDEC", "mspdec", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x01020000;
- nv_engine(priv)->cclass = &nv98_vp_cclass;
- nv_engine(priv)->sclass = nv98_vp_sclass;
+ nv_engine(priv)->cclass = &nv98_mspdec_cclass;
+ nv_engine(priv)->sclass = nv98_mspdec_sclass;
return 0;
}
struct nouveau_oclass
-nv98_vp_oclass = {
- .handle = NV_ENGINE(VP, 0x98),
+nv98_mspdec_oclass = {
+ .handle = NV_ENGINE(MSPDEC, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv98_vp_ctor,
+ .ctor = nv98_mspdec_ctor,
.dtor = _nouveau_falcon_dtor,
- .init = nv98_vp_init,
+ .init = nv98_mspdec_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nvc0.c
similarity index 80%
rename from drivers/gpu/drm/nouveau/nvkm/engine/vp/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nvc0.c
index ac1f62aace72..c622010a6722 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nvc0.c
@@ -23,29 +23,29 @@
*/
#include <engine/falcon.h>
-#include <engine/vp.h>
+#include <engine/mspdec.h>
-struct nvc0_vp_priv {
+struct nvc0_mspdec_priv {
struct nouveau_falcon base;
};
/*******************************************************************************
- * VP object classes
+ * MSPDEC object classes
******************************************************************************/
static struct nouveau_oclass
-nvc0_vp_sclass[] = {
+nvc0_mspdec_sclass[] = {
{ 0x90b2, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
- * PVP context
+ * PMSPDEC context
******************************************************************************/
static struct nouveau_oclass
-nvc0_vp_cclass = {
- .handle = NV_ENGCTX(VP, 0xc0),
+nvc0_mspdec_cclass = {
+ .handle = NV_ENGCTX(MSPDEC, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@@ -57,13 +57,13 @@ nvc0_vp_cclass = {
};
/*******************************************************************************
- * PVP engine/subdev functions
+ * PMSPDEC engine/subdev functions
******************************************************************************/
static int
-nvc0_vp_init(struct nouveau_object *object)
+nvc0_mspdec_init(struct nouveau_object *object)
{
- struct nvc0_vp_priv *priv = (void *)object;
+ struct nvc0_mspdec_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
@@ -76,33 +76,33 @@ nvc0_vp_init(struct nouveau_object *object)
}
static int
-nvc0_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvc0_mspdec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvc0_vp_priv *priv;
+ struct nvc0_mspdec_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,
- "PVP", "vp", &priv);
+ "PMSPDEC", "mspdec", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00020000;
nv_subdev(priv)->intr = nouveau_falcon_intr;
- nv_engine(priv)->cclass = &nvc0_vp_cclass;
- nv_engine(priv)->sclass = nvc0_vp_sclass;
+ nv_engine(priv)->cclass = &nvc0_mspdec_cclass;
+ nv_engine(priv)->sclass = nvc0_mspdec_sclass;
return 0;
}
struct nouveau_oclass
-nvc0_vp_oclass = {
- .handle = NV_ENGINE(VP, 0xc0),
+nvc0_mspdec_oclass = {
+ .handle = NV_ENGINE(MSPDEC, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_vp_ctor,
+ .ctor = nvc0_mspdec_ctor,
.dtor = _nouveau_falcon_dtor,
- .init = nvc0_vp_init,
+ .init = nvc0_mspdec_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nve0.c
similarity index 80%
rename from drivers/gpu/drm/nouveau/nvkm/engine/vp/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nve0.c
index d4c3108479c9..84108b5728f9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nve0.c
@@ -23,29 +23,29 @@
*/
#include <engine/falcon.h>
-#include <engine/vp.h>
+#include <engine/mspdec.h>
-struct nve0_vp_priv {
+struct nve0_mspdec_priv {
struct nouveau_falcon base;
};
/*******************************************************************************
- * VP object classes
+ * MSPDEC object classes
******************************************************************************/
static struct nouveau_oclass
-nve0_vp_sclass[] = {
+nve0_mspdec_sclass[] = {
{ 0x95b2, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
- * PVP context
+ * PMSPDEC context
******************************************************************************/
static struct nouveau_oclass
-nve0_vp_cclass = {
- .handle = NV_ENGCTX(VP, 0xe0),
+nve0_mspdec_cclass = {
+ .handle = NV_ENGCTX(MSPDEC, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@@ -57,13 +57,13 @@ nve0_vp_cclass = {
};
/*******************************************************************************
- * PVP engine/subdev functions
+ * PMSPDEC engine/subdev functions
******************************************************************************/
static int
-nve0_vp_init(struct nouveau_object *object)
+nve0_mspdec_init(struct nouveau_object *object)
{
- struct nve0_vp_priv *priv = (void *)object;
+ struct nve0_mspdec_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
@@ -76,33 +76,33 @@ nve0_vp_init(struct nouveau_object *object)
}
static int
-nve0_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nve0_mspdec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nve0_vp_priv *priv;
+ struct nve0_mspdec_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,
- "PVP", "vp", &priv);
+ "PMSPDEC", "mspdec", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00020000;
nv_subdev(priv)->intr = nouveau_falcon_intr;
- nv_engine(priv)->cclass = &nve0_vp_cclass;
- nv_engine(priv)->sclass = nve0_vp_sclass;
+ nv_engine(priv)->cclass = &nve0_mspdec_cclass;
+ nv_engine(priv)->sclass = nve0_mspdec_sclass;
return 0;
}
struct nouveau_oclass
-nve0_vp_oclass = {
- .handle = NV_ENGINE(VP, 0xe0),
+nve0_mspdec_oclass = {
+ .handle = NV_ENGINE(MSPDEC, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_vp_ctor,
+ .ctor = nve0_mspdec_ctor,
.dtor = _nouveau_falcon_dtor,
- .init = nve0_vp_init,
+ .init = nve0_mspdec_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
index 6c1d9d1ede94..e4bfb6eb3d21 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
@@ -1,4 +1 @@
nvkm-y += nvkm/engine/vp/nv84.o
-nvkm-y += nvkm/engine/vp/nv98.o
-nvkm-y += nvkm/engine/vp/nvc0.o
-nvkm-y += nvkm/engine/vp/nve0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
index dbcea4930a1d..a1bb3e48739c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
@@ -11,9 +11,9 @@ include $(src)/nvkm/subdev/ibus/Kbuild
include $(src)/nvkm/subdev/instmem/Kbuild
include $(src)/nvkm/subdev/ltc/Kbuild
include $(src)/nvkm/subdev/mc/Kbuild
+include $(src)/nvkm/subdev/mmu/Kbuild
include $(src)/nvkm/subdev/mxm/Kbuild
include $(src)/nvkm/subdev/pmu/Kbuild
include $(src)/nvkm/subdev/therm/Kbuild
include $(src)/nvkm/subdev/timer/Kbuild
-include $(src)/nvkm/subdev/mmu/Kbuild
include $(src)/nvkm/subdev/volt/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
index 1da2bedce00a..3a629e02622f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
@@ -33,7 +33,7 @@ nv98_devinit_disable(struct nouveau_devinit *devinit)
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
- disable |= (1ULL << NVDEV_ENGINE_VP);
+ disable |= (1ULL << NVDEV_ENGINE_MSPDEC);
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
index 8bc7668faede..830fdffa9644 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
@@ -67,7 +67,7 @@ nva3_devinit_disable(struct nouveau_devinit *devinit)
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
- disable |= (1ULL << NVDEV_ENGINE_VP);
+ disable |= (1ULL << NVDEV_ENGINE_MSPDEC);
disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
index fea3be514553..f70b9542ad03 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
@@ -33,7 +33,7 @@ nvaf_devinit_disable(struct nouveau_devinit *devinit)
u64 disable = 0;
if (!(r001540 & 0x40000000)) {
- disable |= (1ULL << NVDEV_ENGINE_VP);
+ disable |= (1ULL << NVDEV_ENGINE_MSPDEC);
disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
index 4ad22a48ff3a..672aaf347efe 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
@@ -70,7 +70,7 @@ nvc0_devinit_disable(struct nouveau_devinit *devinit)
disable |= (1ULL << NVDEV_ENGINE_DISP);
if (r022500 & 0x00000002) {
- disable |= (1ULL << NVDEV_ENGINE_VP);
+ disable |= (1ULL << NVDEV_ENGINE_MSPDEC);
disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
index 384d7eee830a..962273e3e008 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
@@ -194,6 +194,8 @@ nv50_fb_intr(struct nouveau_subdev *subdev)
engine = nouveau_engine(subdev, NVDEV_ENGINE_MSVLD);
if (!engine && en->data2 == NVDEV_ENGINE_CIPHER)
engine = nouveau_engine(subdev, NVDEV_ENGINE_SEC);
+ if (!engine && en->data2 == NVDEV_ENGINE_VP)
+ engine = nouveau_engine(subdev, NVDEV_ENGINE_MSPDEC);
if (engine) {
engctx = nouveau_engctx_get(engine, chan);
if (engctx)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
index 06fc28b5e890..49de0cf57359 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
@@ -32,7 +32,7 @@ nv98_mc_intr[] = {
{ 0x00001000, NVDEV_ENGINE_GR },
{ 0x00004000, NVDEV_ENGINE_SEC }, /* NV84:NVA3 */
{ 0x00008000, NVDEV_ENGINE_MSVLD },
- { 0x00020000, NVDEV_ENGINE_VP },
+ { 0x00020000, NVDEV_ENGINE_MSPDEC },
{ 0x00040000, NVDEV_SUBDEV_PMU }, /* NVA3:NVC0 */
{ 0x00080000, NVDEV_SUBDEV_THERM }, /* NVA3:NVC0 */
{ 0x00100000, NVDEV_SUBDEV_TIMER },
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
index 76f440efa764..a52687a883f0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
@@ -36,7 +36,7 @@ nvc0_mc_intr[] = {
{ 0x00002000, NVDEV_SUBDEV_FB },
{ 0x00008000, NVDEV_ENGINE_MSVLD },
{ 0x00040000, NVDEV_SUBDEV_THERM },
- { 0x00020000, NVDEV_ENGINE_VP },
+ { 0x00020000, NVDEV_ENGINE_MSPDEC },
{ 0x00100000, NVDEV_SUBDEV_TIMER },
{ 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */
{ 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
index 4ac6eb99d55f..70e1a140e7a3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
@@ -172,7 +172,8 @@ nv50_vm_flush(struct nouveau_vm *vm)
switch (i) {
case NVDEV_ENGINE_GR : vme = 0x00; break;
- case NVDEV_ENGINE_VP : vme = 0x01; break;
+ case NVDEV_ENGINE_VP :
+ case NVDEV_ENGINE_MSPDEC: vme = 0x01; break;
case NVDEV_SUBDEV_BAR : vme = 0x06; break;
case NVDEV_ENGINE_MSPPP :
case NVDEV_ENGINE_MPEG : vme = 0x08; break;
From c4345146dbee38d949efd3a7b96d1bea962a29f2 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 16:58:51 +1000
Subject: [PATCH 49/86] drm/nouveau/core: split device index enum out on its
own
To avoid having to include core/device.h where it's not otherwise
required.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/core/device.h | 60 ------------------
.../drm/nouveau/include/nvkm/core/devidx.h | 62 +++++++++++++++++++
.../drm/nouveau/include/nvkm/core/subdev.h | 1 +
3 files changed, 63 insertions(+), 60 deletions(-)
create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 2b90ec900a8c..23d71c58c3f1 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -6,66 +6,6 @@
#include <core/engine.h>
#include <core/event.h>
-enum nv_subdev_type {
- NVDEV_ENGINE_DEVICE,
- NVDEV_SUBDEV_VBIOS,
-
- /* All subdevs from DEVINIT to DEVINIT_LAST will be created before
- * *any* of them are initialised. This subdev category is used
- * for any subdevs that the VBIOS init table parsing may call out
- * to during POST.
- */
- NVDEV_SUBDEV_DEVINIT,
- NVDEV_SUBDEV_IBUS,
- NVDEV_SUBDEV_GPIO,
- NVDEV_SUBDEV_I2C,
- NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C,
-
- /* This grouping of subdevs are initialised right after they've
- * been created, and are allowed to assume any subdevs in the
- * list above them exist and have been initialised.
- */
- NVDEV_SUBDEV_FUSE,
- NVDEV_SUBDEV_MXM,
- NVDEV_SUBDEV_MC,
- NVDEV_SUBDEV_BUS,
- NVDEV_SUBDEV_TIMER,
- NVDEV_SUBDEV_FB,
- NVDEV_SUBDEV_LTC,
- NVDEV_SUBDEV_INSTMEM,
- NVDEV_SUBDEV_MMU,
- NVDEV_SUBDEV_BAR,
- NVDEV_SUBDEV_PMU,
- NVDEV_SUBDEV_VOLT,
- NVDEV_SUBDEV_THERM,
- NVDEV_SUBDEV_CLK,
-
- NVDEV_ENGINE_FIRST,
- NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
- NVDEV_ENGINE_IFB,
- NVDEV_ENGINE_FIFO,
- NVDEV_ENGINE_SW,
- NVDEV_ENGINE_GR,
- NVDEV_ENGINE_MPEG,
- NVDEV_ENGINE_ME,
- NVDEV_ENGINE_VP,
- NVDEV_ENGINE_CIPHER,
- NVDEV_ENGINE_BSP,
- NVDEV_ENGINE_MSPPP,
- NVDEV_ENGINE_CE0,
- NVDEV_ENGINE_CE1,
- NVDEV_ENGINE_CE2,
- NVDEV_ENGINE_VIC,
- NVDEV_ENGINE_MSENC,
- NVDEV_ENGINE_DISP,
- NVDEV_ENGINE_PM,
- NVDEV_ENGINE_MSVLD,
- NVDEV_ENGINE_SEC,
- NVDEV_ENGINE_MSPDEC,
-
- NVDEV_SUBDEV_NR,
-};
-
struct nouveau_device {
struct nouveau_engine engine;
struct list_head head;
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h b/drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h
new file mode 100644
index 000000000000..60c5888b5df3
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h
@@ -0,0 +1,62 @@
+#ifndef __NVKM_DEVIDX_H__
+#define __NVKM_DEVIDX_H__
+enum nvkm_devidx {
+ NVDEV_ENGINE_DEVICE,
+ NVDEV_SUBDEV_VBIOS,
+
+ /* All subdevs from DEVINIT to DEVINIT_LAST will be created before
+ * *any* of them are initialised. This subdev category is used
+ * for any subdevs that the VBIOS init table parsing may call out
+ * to during POST.
+ */
+ NVDEV_SUBDEV_DEVINIT,
+ NVDEV_SUBDEV_IBUS,
+ NVDEV_SUBDEV_GPIO,
+ NVDEV_SUBDEV_I2C,
+ NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C,
+
+ /* This grouping of subdevs are initialised right after they've
+ * been created, and are allowed to assume any subdevs in the
+ * list above them exist and have been initialised.
+ */
+ NVDEV_SUBDEV_FUSE,
+ NVDEV_SUBDEV_MXM,
+ NVDEV_SUBDEV_MC,
+ NVDEV_SUBDEV_BUS,
+ NVDEV_SUBDEV_TIMER,
+ NVDEV_SUBDEV_FB,
+ NVDEV_SUBDEV_LTC,
+ NVDEV_SUBDEV_INSTMEM,
+ NVDEV_SUBDEV_MMU,
+ NVDEV_SUBDEV_BAR,
+ NVDEV_SUBDEV_PMU,
+ NVDEV_SUBDEV_VOLT,
+ NVDEV_SUBDEV_THERM,
+ NVDEV_SUBDEV_CLK,
+
+ NVDEV_ENGINE_FIRST,
+ NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
+ NVDEV_ENGINE_IFB,
+ NVDEV_ENGINE_FIFO,
+ NVDEV_ENGINE_SW,
+ NVDEV_ENGINE_GR,
+ NVDEV_ENGINE_MPEG,
+ NVDEV_ENGINE_ME,
+ NVDEV_ENGINE_VP,
+ NVDEV_ENGINE_CIPHER,
+ NVDEV_ENGINE_BSP,
+ NVDEV_ENGINE_MSPPP,
+ NVDEV_ENGINE_CE0,
+ NVDEV_ENGINE_CE1,
+ NVDEV_ENGINE_CE2,
+ NVDEV_ENGINE_VIC,
+ NVDEV_ENGINE_MSENC,
+ NVDEV_ENGINE_DISP,
+ NVDEV_ENGINE_PM,
+ NVDEV_ENGINE_MSVLD,
+ NVDEV_ENGINE_SEC,
+ NVDEV_ENGINE_MSPDEC,
+
+ NVDEV_SUBDEV_NR,
+};
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
index 68f1c419d156..152c842e1f66 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
@@ -2,6 +2,7 @@
#define __NOUVEAU_SUBDEV_H__
#include <core/object.h>
+#include <core/devidx.h>
#define NV_SUBDEV_(sub,var) (NV_SUBDEV_CLASS | ((var) << 8) | (sub))
#define NV_SUBDEV(name,var) NV_SUBDEV_(NVDEV_SUBDEV_##name, (var))
From 989aa5b76ad2af7653353cf01bdebec2ba9436aa Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Mon, 12 Jan 2015 12:33:37 +1000
Subject: [PATCH 50/86] drm/nouveau/nvif: namespace of nvkm accessors (no
binary change)
NVKM is having it's namespace switched to nvkm_, which will conflict
with these functions (which are workarounds for the fact that as of
yet, we still aren't able to split DRM and NVKM completely).
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4 +-
drivers/gpu/drm/nouveau/dispnv04/dac.c | 4 +-
drivers/gpu/drm/nouveau/dispnv04/dfp.c | 2 +-
drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +-
drivers/gpu/drm/nouveau/dispnv04/disp.h | 2 +-
drivers/gpu/drm/nouveau/dispnv04/hw.c | 10 ++--
drivers/gpu/drm/nouveau/dispnv04/tvnv04.c | 4 +-
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c | 10 ++--
drivers/gpu/drm/nouveau/include/nvif/client.h | 2 +-
drivers/gpu/drm/nouveau/include/nvif/device.h | 31 ++++++-----
drivers/gpu/drm/nouveau/include/nvif/object.h | 2 +-
drivers/gpu/drm/nouveau/nouveau_abi16.c | 10 ++--
drivers/gpu/drm/nouveau/nouveau_agp.c | 4 +-
drivers/gpu/drm/nouveau/nouveau_bios.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_bo.c | 24 ++++-----
drivers/gpu/drm/nouveau/nouveau_chan.c | 10 ++--
drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_display.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_drm.c | 18 +++----
drivers/gpu/drm/nouveau/nouveau_fence.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_gem.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_hwmon.c | 54 +++++++++----------
drivers/gpu/drm/nouveau/nouveau_platform.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_sysfs.c | 4 +-
drivers/gpu/drm/nouveau/nouveau_ttm.c | 18 +++----
drivers/gpu/drm/nouveau/nv04_fence.c | 2 +-
drivers/gpu/drm/nouveau/nv50_display.c | 18 +++----
drivers/gpu/drm/nouveau/nv84_fence.c | 2 +-
28 files changed, 124 insertions(+), 125 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
index f8ddae26dfbf..f32eecbe3c95 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
@@ -112,8 +112,8 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod
{
struct drm_device *dev = crtc->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_bios *bios = nvkm_bios(&drm->device);
- struct nouveau_clk *clk = nvkm_clk(&drm->device);
+ struct nouveau_bios *bios = nvxx_bios(&drm->device);
+ struct nouveau_clk *clk = nvxx_clk(&drm->device);
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
diff --git a/drivers/gpu/drm/nouveau/dispnv04/dac.c b/drivers/gpu/drm/nouveau/dispnv04/dac.c
index 2d8056cde996..043e07b01fd0 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/dac.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/dac.c
@@ -66,7 +66,7 @@ int nv04_dac_output_offset(struct drm_encoder *encoder)
static int sample_load_twice(struct drm_device *dev, bool sense[2])
{
struct nvif_device *device = &nouveau_drm(dev)->device;
- struct nouveau_timer *ptimer = nvkm_timer(device);
+ struct nouveau_timer *ptimer = nvxx_timer(device);
int i;
for (i = 0; i < 2; i++) {
@@ -232,7 +232,7 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
struct drm_device *dev = encoder->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &nouveau_drm(dev)->device;
- struct nouveau_gpio *gpio = nvkm_gpio(device);
+ struct nouveau_gpio *gpio = nvxx_gpio(device);
struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
diff --git a/drivers/gpu/drm/nouveau/dispnv04/dfp.c b/drivers/gpu/drm/nouveau/dispnv04/dfp.c
index 42a5435259f7..a326f374e37c 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/dfp.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/dfp.c
@@ -623,7 +623,7 @@ static void nv04_tmds_slave_init(struct drm_encoder *encoder)
struct drm_device *dev = encoder->dev;
struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
+ struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
struct nouveau_i2c_port *port = i2c->find(i2c, 2);
struct nouveau_i2c_board_info info[] = {
{
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c
index bdf7cf49afcd..3373a15eab5d 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c
@@ -35,7 +35,7 @@ int
nv04_display_create(struct drm_device *dev)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
+ struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
struct dcb_table *dcb = &drm->vbios.dcb;
struct drm_connector *connector, *ct;
struct drm_encoder *encoder;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h b/drivers/gpu/drm/nouveau/dispnv04/disp.h
index 3ad3ee818c1a..fe4901cfae27 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/disp.h
+++ b/drivers/gpu/drm/nouveau/dispnv04/disp.h
@@ -170,7 +170,7 @@ nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
struct dcb_output *outp, int crtc)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_bios *bios = nvkm_bios(&drm->device);
+ struct nouveau_bios *bios = nvxx_bios(&drm->device);
struct nvbios_init init = {
.subdev = nv_subdev(bios),
.bios = bios,
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
index f9491f926c14..a930c1e71148 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -166,7 +166,7 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
- struct nouveau_bios *bios = nvkm_bios(device);
+ struct nouveau_bios *bios = nvxx_bios(device);
uint32_t reg1, pll1, pll2 = 0;
struct nvbios_pll pll_lim;
int ret;
@@ -253,8 +253,8 @@ nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
- struct nouveau_clk *clk = nvkm_clk(device);
- struct nouveau_bios *bios = nvkm_bios(device);
+ struct nouveau_clk *clk = nvxx_clk(device);
+ struct nouveau_bios *bios = nvxx_bios(device);
struct nvbios_pll pll_lim;
struct nouveau_pll_vals pv;
enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0;
@@ -463,7 +463,7 @@ nv_load_state_ramdac(struct drm_device *dev, int head,
struct nv04_mode_state *state)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_clk *clk = nvkm_clk(&drm->device);
+ struct nouveau_clk *clk = nvxx_clk(&drm->device);
struct nv04_crtc_reg *regp = &state->crtc_reg[head];
uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
int i;
@@ -661,7 +661,7 @@ nv_load_state_ext(struct drm_device *dev, int head,
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
- struct nouveau_timer *ptimer = nvkm_timer(device);
+ struct nouveau_timer *ptimer = nvxx_timer(device);
struct nv04_crtc_reg *regp = &state->crtc_reg[head];
uint32_t reg900;
int i;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c
index 8061d8d0ce79..38a8196d1e92 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c
@@ -54,7 +54,7 @@ static struct nouveau_i2c_board_info nv04_tv_encoder_info[] = {
int nv04_tv_identify(struct drm_device *dev, int i2c_index)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
+ struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
return i2c->identify(i2c, i2c_index, "TV encoder",
nv04_tv_encoder_info, NULL, NULL);
@@ -204,7 +204,7 @@ nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry)
struct drm_encoder *encoder;
struct drm_device *dev = connector->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
+ struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
struct nouveau_i2c_port *port = i2c->find(i2c, entry->i2c_index);
int type, ret;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
index 72d2ab04db47..b86e36b4077d 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
@@ -46,7 +46,7 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_gpio *gpio = nvkm_gpio(&drm->device);
+ struct nouveau_gpio *gpio = nvxx_gpio(&drm->device);
uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
@@ -133,14 +133,14 @@ get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
struct nvif_device *device = &drm->device;
/* Zotac FX5200 */
- if (nv_device_match(nvkm_object(device), 0x0322, 0x19da, 0x1035) ||
- nv_device_match(nvkm_object(device), 0x0322, 0x19da, 0x2035)) {
+ if (nv_device_match(nvxx_object(device), 0x0322, 0x19da, 0x1035) ||
+ nv_device_match(nvxx_object(device), 0x0322, 0x19da, 0x2035)) {
*pin_mask = 0xc;
return false;
}
/* MSI nForce2 IGP */
- if (nv_device_match(nvkm_object(device), 0x01f0, 0x1462, 0x5710)) {
+ if (nv_device_match(nvxx_object(device), 0x01f0, 0x1462, 0x5710)) {
*pin_mask = 0xc;
return false;
}
@@ -370,7 +370,7 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
{
struct drm_device *dev = encoder->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_gpio *gpio = nvkm_gpio(&drm->device);
+ struct nouveau_gpio *gpio = nvxx_gpio(&drm->device);
struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
diff --git a/drivers/gpu/drm/nouveau/include/nvif/client.h b/drivers/gpu/drm/nouveau/include/nvif/client.h
index 8b0048426ee5..97694738abcf 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/client.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/client.h
@@ -31,7 +31,7 @@ int nvif_client_resume(struct nvif_client *);
/*XXX*/
#include <core/client.h>
-#define nvkm_client(a) ({ \
+#define nvxx_client(a) ({ \
struct nvif_client *_client = nvif_client(nvif_object(a)); \
nouveau_client(_client->base.priv); \
})
diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h
index 90e2d9706f23..1d186e21d123 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/device.h
@@ -37,26 +37,25 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
#include <subdev/timer.h>
#include <subdev/therm.h>
-#define nvkm_device(a) nv_device(nvkm_object((a)))
-#define nvkm_bios(a) nouveau_bios(nvkm_device(a))
-#define nvkm_fb(a) nouveau_fb(nvkm_device(a))
-#define nvkm_mmu(a) nouveau_mmu(nvkm_device(a))
-#define nvkm_bar(a) nouveau_bar(nvkm_device(a))
-#define nvkm_gpio(a) nouveau_gpio(nvkm_device(a))
-#define nvkm_clk(a) nouveau_clk(nvkm_device(a))
-#define nvkm_i2c(a) nouveau_i2c(nvkm_device(a))
-#define nvkm_timer(a) nouveau_timer(nvkm_device(a))
-#define nvkm_wait(a,b,c,d) nv_wait(nvkm_timer(a), (b), (c), (d))
-#define nvkm_wait_cb(a,b,c) nv_wait_cb(nvkm_timer(a), (b), (c))
-#define nvkm_therm(a) nouveau_therm(nvkm_device(a))
+#define nvxx_device(a) nv_device(nvxx_object((a)))
+#define nvxx_bios(a) nouveau_bios(nvxx_device(a))
+#define nvxx_fb(a) nouveau_fb(nvxx_device(a))
+#define nvxx_mmu(a) nouveau_mmu(nvxx_device(a))
+#define nvxx_bar(a) nouveau_bar(nvxx_device(a))
+#define nvxx_gpio(a) nouveau_gpio(nvxx_device(a))
+#define nvxx_clk(a) nouveau_clk(nvxx_device(a))
+#define nvxx_i2c(a) nouveau_i2c(nvxx_device(a))
+#define nvxx_timer(a) nouveau_timer(nvxx_device(a))
+#define nvxx_wait(a,b,c,d) nv_wait(nvxx_timer(a), (b), (c), (d))
+#define nvxx_wait_cb(a,b,c) nv_wait_cb(nvxx_timer(a), (b), (c))
+#define nvxx_therm(a) nouveau_therm(nvxx_device(a))
#include <engine/device.h>
#include <engine/fifo.h>
#include <engine/gr.h>
#include <engine/sw.h>
-#define nvkm_fifo(a) nouveau_fifo(nvkm_device(a))
-#define nvkm_fifo_chan(a) ((struct nouveau_fifo_chan *)nvkm_object(a))
-#define nvkm_gr(a) ((struct nouveau_gr *)nouveau_engine(nvkm_object(a), NVDEV_ENGINE_GR))
-
+#define nvxx_fifo(a) nouveau_fifo(nvxx_device(a))
+#define nvxx_fifo_chan(a) ((struct nouveau_fifo_chan *)nvxx_object(a))
+#define nvxx_gr(a) ((struct nouveau_gr *)nouveau_engine(nvxx_object(a), NVDEV_ENGINE_GR))
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/object.h b/drivers/gpu/drm/nouveau/include/nvif/object.h
index fe519179b76c..d47f5693cb5b 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/object.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/object.h
@@ -70,6 +70,6 @@ void nvif_object_unmap(struct nvif_object *);
/*XXX*/
#include <core/object.h>
-#define nvkm_object(a) ((struct nouveau_object *)nvif_object(a)->priv)
+#define nvxx_object(a) ((struct nouveau_object *)nvif_object(a)->priv)
#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index 16ab6b187a52..9322b515d305 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -164,8 +164,8 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
struct nouveau_cli *cli = nouveau_cli(file_priv);
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
- struct nouveau_timer *ptimer = nvkm_timer(device);
- struct nouveau_gr *gr = nvkm_gr(device);
+ struct nouveau_timer *ptimer = nvxx_timer(device);
+ struct nouveau_gr *gr = nvxx_gr(device);
struct drm_nouveau_getparam *getparam = data;
switch (getparam->param) {
@@ -173,19 +173,19 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
getparam->value = device->info.chipset;
break;
case NOUVEAU_GETPARAM_PCI_VENDOR:
- if (nv_device_is_pci(nvkm_device(device)))
+ if (nv_device_is_pci(nvxx_device(device)))
getparam->value = dev->pdev->vendor;
else
getparam->value = 0;
break;
case NOUVEAU_GETPARAM_PCI_DEVICE:
- if (nv_device_is_pci(nvkm_device(device)))
+ if (nv_device_is_pci(nvxx_device(device)))
getparam->value = dev->pdev->device;
else
getparam->value = 0;
break;
case NOUVEAU_GETPARAM_BUS_TYPE:
- if (!nv_device_is_pci(nvkm_device(device)))
+ if (!nv_device_is_pci(nvxx_device(device)))
getparam->value = 3;
else
if (drm_pci_device_is_agp(dev))
diff --git a/drivers/gpu/drm/nouveau/nouveau_agp.c b/drivers/gpu/drm/nouveau/nouveau_agp.c
index 1f6f6ba6847a..0b5970955604 100644
--- a/drivers/gpu/drm/nouveau/nouveau_agp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_agp.c
@@ -45,8 +45,8 @@ get_agp_mode(struct nouveau_drm *drm, const struct drm_agp_info *info)
while (agpmode == -1 && quirk->hostbridge_vendor) {
if (info->id_vendor == quirk->hostbridge_vendor &&
info->id_device == quirk->hostbridge_device &&
- nvkm_device(device)->pdev->vendor == quirk->chip_vendor &&
- nvkm_device(device)->pdev->device == quirk->chip_device) {
+ nvxx_device(device)->pdev->vendor == quirk->chip_vendor &&
+ nvxx_device(device)->pdev->device == quirk->chip_device) {
agpmode = quirk->mode;
NV_INFO(drm, "Forcing agp mode to %dX. Use agpmode to override.\n",
agpmode);
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 7df6acc8bb34..8058b68b0e3b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -2009,7 +2009,7 @@ uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
static bool NVInitVBIOS(struct drm_device *dev)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_bios *bios = nvkm_bios(&drm->device);
+ struct nouveau_bios *bios = nvxx_bios(&drm->device);
struct nvbios *legacy = &drm->vbios;
memset(legacy, 0, sizeof(struct nvbios));
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index d2f0929c2d73..902d93fd72cc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -48,7 +48,7 @@ nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
{
struct nouveau_drm *drm = nouveau_drm(dev);
int i = reg - drm->tile.reg;
- struct nouveau_fb *pfb = nvkm_fb(&drm->device);
+ struct nouveau_fb *pfb = nvxx_fb(&drm->device);
struct nouveau_fb_tile *tile = &pfb->tile.region[i];
struct nouveau_engine *engine;
@@ -105,7 +105,7 @@ nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
u32 size, u32 pitch, u32 flags)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_fb *pfb = nvkm_fb(&drm->device);
+ struct nouveau_fb *pfb = nvxx_fb(&drm->device);
struct nouveau_drm_tile *tile, *found = NULL;
int i;
@@ -214,7 +214,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align,
nvbo->tile_flags = tile_flags;
nvbo->bo.bdev = &drm->ttm.bdev;
- if (!nv_device_is_cpu_coherent(nvkm_device(&drm->device)))
+ if (!nv_device_is_cpu_coherent(nvxx_device(&drm->device)))
nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED;
nvbo->page_shift = 12;
@@ -459,7 +459,7 @@ void
nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
{
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
- struct nouveau_device *device = nvkm_device(&drm->device);
+ struct nouveau_device *device = nvxx_device(&drm->device);
struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
int i;
@@ -479,7 +479,7 @@ void
nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
{
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
- struct nouveau_device *device = nvkm_device(&drm->device);
+ struct nouveau_device *device = nvxx_device(&drm->device);
struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
int i;
@@ -620,7 +620,7 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
/* Some BARs do not support being ioremapped WC */
- if (nvkm_bar(&drm->device)->iomap_uncached) {
+ if (nvxx_bar(&drm->device)->iomap_uncached) {
man->available_caching = TTM_PL_FLAG_UNCACHED;
man->default_caching = TTM_PL_FLAG_UNCACHED;
}
@@ -1382,10 +1382,10 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
/* fallthrough, tiled memory */
case TTM_PL_VRAM:
mem->bus.offset = mem->start << PAGE_SHIFT;
- mem->bus.base = nv_device_resource_start(nvkm_device(&drm->device), 1);
+ mem->bus.base = nv_device_resource_start(nvxx_device(&drm->device), 1);
mem->bus.is_iomem = true;
if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
- struct nouveau_bar *bar = nvkm_bar(&drm->device);
+ struct nouveau_bar *bar = nvxx_bar(&drm->device);
ret = bar->umap(bar, node, NV_MEM_ACCESS_RW,
&node->bar_vma);
@@ -1405,7 +1405,7 @@ static void
nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
{
struct nouveau_drm *drm = nouveau_bdev(bdev);
- struct nouveau_bar *bar = nvkm_bar(&drm->device);
+ struct nouveau_bar *bar = nvxx_bar(&drm->device);
struct nouveau_mem *node = mem->mm_node;
if (!node->bar_vma.node)
@@ -1420,7 +1420,7 @@ nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
struct nouveau_bo *nvbo = nouveau_bo(bo);
struct nvif_device *device = &drm->device;
- u32 mappable = nv_device_resource_len(nvkm_device(device), 1) >> PAGE_SHIFT;
+ u32 mappable = nv_device_resource_len(nvxx_device(device), 1) >> PAGE_SHIFT;
int i, ret;
/* as long as the bo isn't in vram, and isn't tiled, we've got
@@ -1484,7 +1484,7 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm)
}
drm = nouveau_bdev(ttm->bdev);
- device = nvkm_device(&drm->device);
+ device = nvxx_device(&drm->device);
dev = drm->dev;
pdev = nv_device_base(device);
@@ -1549,7 +1549,7 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
return;
drm = nouveau_bdev(ttm->bdev);
- device = nvkm_device(&drm->device);
+ device = nvxx_device(&drm->device);
dev = drm->dev;
pdev = nv_device_base(device);
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c
index 58b8b6423026..3bcbbd329cf2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_chan.c
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.c
@@ -54,7 +54,7 @@ nouveau_channel_idle(struct nouveau_channel *chan)
if (ret)
NV_PRINTK(error, cli, "failed to idle channel 0x%08x [%s]\n",
- chan->object->handle, nvkm_client(&cli->base)->name);
+ chan->object->handle, nvxx_client(&cli->base)->name);
return ret;
}
@@ -88,7 +88,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
u32 handle, u32 size, struct nouveau_channel **pchan)
{
struct nouveau_cli *cli = (void *)nvif_client(&device->base);
- struct nouveau_mmu *mmu = nvkm_mmu(device);
+ struct nouveau_mmu *mmu = nvxx_mmu(device);
struct nv_dma_v0 args = {};
struct nouveau_channel *chan;
u32 target;
@@ -146,7 +146,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
*/
args.target = NV_DMA_V0_TARGET_PCI;
args.access = NV_DMA_V0_ACCESS_RDWR;
- args.start = nv_device_resource_start(nvkm_device(device), 1);
+ args.start = nv_device_resource_start(nvxx_device(device), 1);
args.limit = args.start + device->info.ram_user - 1;
} else {
args.target = NV_DMA_V0_TARGET_VRAM;
@@ -281,7 +281,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
{
struct nvif_device *device = chan->device;
struct nouveau_cli *cli = (void *)nvif_client(&device->base);
- struct nouveau_mmu *mmu = nvkm_mmu(device);
+ struct nouveau_mmu *mmu = nvxx_mmu(device);
struct nouveau_sw_chan *swch;
struct nv_dma_v0 args = {};
int ret, i;
@@ -372,7 +372,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
if (ret)
return ret;
- swch = (void *)nvkm_object(&chan->nvsw)->parent;
+ swch = (void *)nvxx_object(&chan->nvsw)->parent;
swch->flip = nouveau_flip_complete;
swch->flip_data = chan;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 9c871f93cc1e..4ab6340b0dac 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -115,7 +115,7 @@ nouveau_connector_ddc_detect(struct drm_connector *connector)
struct drm_device *dev = connector->dev;
struct nouveau_connector *nv_connector = nouveau_connector(connector);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_gpio *gpio = nvkm_gpio(&drm->device);
+ struct nouveau_gpio *gpio = nvxx_gpio(&drm->device);
struct nouveau_encoder *nv_encoder;
struct drm_encoder *encoder;
int i, panel = -ENODEV;
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index f972e9c1a23a..860b0e2d4181 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -450,7 +450,7 @@ nouveau_display_create(struct drm_device *dev)
drm_mode_create_dvi_i_properties(dev);
dev->mode_config.funcs = &nouveau_mode_config_funcs;
- dev->mode_config.fb_base = nv_device_resource_start(nvkm_device(&drm->device), 1);
+ dev->mode_config.fb_base = nv_device_resource_start(nvxx_device(&drm->device), 1);
dev->mode_config.min_width = 0;
dev->mode_config.min_height = 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index e684040ccf11..1de82ec6c276 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -124,7 +124,7 @@ nouveau_cli_create(u64 name, const char *sname,
static void
nouveau_cli_destroy(struct nouveau_cli *cli)
{
- nouveau_vm_ref(NULL, &nvkm_client(&cli->base)->vm, NULL);
+ nouveau_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL);
nvif_client_fini(&cli->base);
usif_client_fini(cli);
}
@@ -243,7 +243,7 @@ nouveau_accel_init(struct nouveau_drm *drm)
OUT_RING (drm->channel, 0x001f0000);
}
}
- swch = (void *)nvkm_object(&drm->nvsw)->parent;
+ swch = (void *)nvxx_object(&drm->nvsw)->parent;
swch->flip = nouveau_flip_complete;
swch->flip_data = drm->channel;
}
@@ -255,7 +255,7 @@ nouveau_accel_init(struct nouveau_drm *drm)
}
if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
- ret = nouveau_gpuobj_new(nvkm_object(&drm->device), NULL, 32,
+ ret = nouveau_gpuobj_new(nvxx_object(&drm->device), NULL, 32,
0, 0, &drm->notify);
if (ret) {
NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
@@ -379,7 +379,7 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
dev->dev_private = drm;
drm->dev = dev;
- nvkm_client(&drm->client.base)->debug =
+ nvxx_client(&drm->client.base)->debug =
nouveau_dbgopt(nouveau_debug, "DRM");
INIT_LIST_HEAD(&drm->clients);
@@ -435,12 +435,12 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
nouveau_agp_init(drm);
if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
- ret = nouveau_vm_new(nvkm_device(&drm->device), 0, (1ULL << 40),
+ ret = nouveau_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
0x1000, &drm->client.vm);
if (ret)
goto fail_device;
- nvkm_client(&drm->client.base)->vm = drm->client.vm;
+ nvxx_client(&drm->client.base)->vm = drm->client.vm;
}
ret = nouveau_ttm_init(drm);
@@ -527,7 +527,7 @@ nouveau_drm_device_remove(struct drm_device *dev)
struct nouveau_object *device;
dev->irq_enabled = false;
- client = nvkm_client(&drm->client.base);
+ client = nvxx_client(&drm->client.base);
device = client->device;
drm_put_dev(dev);
@@ -831,14 +831,14 @@ nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
cli->base.super = false;
if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
- ret = nouveau_vm_new(nvkm_device(&drm->device), 0, (1ULL << 40),
+ ret = nouveau_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
0x1000, &cli->vm);
if (ret) {
nouveau_cli_destroy(cli);
goto out_suspend;
}
- nvkm_client(&cli->base)->vm = cli->vm;
+ nvxx_client(&cli->base)->vm = cli->vm;
}
fpriv->driver_priv = cli;
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index f32a434724e3..c6d56bef5823 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -182,7 +182,7 @@ nouveau_fence_context_new(struct nouveau_channel *chan, struct nouveau_fence_cha
else if (chan == chan->drm->channel)
strcpy(fctx->name, "generic kernel channel");
else
- strcpy(fctx->name, nvkm_client(&cli->base)->name);
+ strcpy(fctx->name, nvxx_client(&cli->base)->name);
kref_init(&fctx->fence_ref);
if (!priv->uevent)
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 9eb8af4daeeb..8453d1aac0e2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -251,7 +251,7 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data,
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_cli *cli = nouveau_cli(file_priv);
- struct nouveau_fb *pfb = nvkm_fb(&drm->device);
+ struct nouveau_fb *pfb = nvxx_fb(&drm->device);
struct drm_nouveau_gem_new *req = data;
struct nouveau_bo *nvbo = NULL;
int ret = 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c b/drivers/gpu/drm/nouveau/nouveau_hwmon.c
index afb36d66e78d..e63c15112f2e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_hwmon.c
@@ -40,7 +40,7 @@ nouveau_hwmon_show_temp(struct device *d, struct device_attribute *a, char *buf)
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
int temp = therm->temp_get(therm);
if (temp < 0)
@@ -66,7 +66,7 @@ nouveau_hwmon_temp1_auto_point1_temp(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST) * 1000);
@@ -78,7 +78,7 @@ nouveau_hwmon_set_temp1_auto_point1_temp(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -99,7 +99,7 @@ nouveau_hwmon_temp1_auto_point1_temp_hyst(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST) * 1000);
@@ -111,7 +111,7 @@ nouveau_hwmon_set_temp1_auto_point1_temp_hyst(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -131,7 +131,7 @@ nouveau_hwmon_max_temp(struct device *d, struct device_attribute *a, char *buf)
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK) * 1000);
@@ -142,7 +142,7 @@ nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -162,7 +162,7 @@ nouveau_hwmon_max_temp_hyst(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST) * 1000);
@@ -173,7 +173,7 @@ nouveau_hwmon_set_max_temp_hyst(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -194,7 +194,7 @@ nouveau_hwmon_critical_temp(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL) * 1000);
@@ -206,7 +206,7 @@ nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -227,7 +227,7 @@ nouveau_hwmon_critical_temp_hyst(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST) * 1000);
@@ -240,7 +240,7 @@ nouveau_hwmon_set_critical_temp_hyst(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -260,7 +260,7 @@ nouveau_hwmon_emergency_temp(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN) * 1000);
@@ -272,7 +272,7 @@ nouveau_hwmon_set_emergency_temp(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -293,7 +293,7 @@ nouveau_hwmon_emergency_temp_hyst(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST) * 1000);
@@ -306,7 +306,7 @@ nouveau_hwmon_set_emergency_temp_hyst(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -346,7 +346,7 @@ nouveau_hwmon_show_fan1_input(struct device *d, struct device_attribute *attr,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n", therm->fan_sense(therm));
}
@@ -359,7 +359,7 @@ nouveau_hwmon_get_pwm1_enable(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
int ret;
ret = therm->attr_get(therm, NOUVEAU_THERM_ATTR_FAN_MODE);
@@ -375,7 +375,7 @@ nouveau_hwmon_set_pwm1_enable(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
long value;
int ret;
@@ -398,7 +398,7 @@ nouveau_hwmon_get_pwm1(struct device *d, struct device_attribute *a, char *buf)
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
int ret;
ret = therm->fan_get(therm);
@@ -414,7 +414,7 @@ nouveau_hwmon_set_pwm1(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
int ret = -ENODEV;
long value;
@@ -438,7 +438,7 @@ nouveau_hwmon_get_pwm1_min(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
int ret;
ret = therm->attr_get(therm, NOUVEAU_THERM_ATTR_FAN_MIN_DUTY);
@@ -454,7 +454,7 @@ nouveau_hwmon_set_pwm1_min(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
long value;
int ret;
@@ -478,7 +478,7 @@ nouveau_hwmon_get_pwm1_max(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
int ret;
ret = therm->attr_get(therm, NOUVEAU_THERM_ATTR_FAN_MAX_DUTY);
@@ -494,7 +494,7 @@ nouveau_hwmon_set_pwm1_max(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
long value;
int ret;
@@ -561,7 +561,7 @@ nouveau_hwmon_init(struct drm_device *dev)
{
#if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE))
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvkm_therm(&drm->device);
+ struct nouveau_therm *therm = nvxx_therm(&drm->device);
struct nouveau_hwmon *hwmon;
struct device *hwmon_dev;
int ret = 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.c b/drivers/gpu/drm/nouveau/nouveau_platform.c
index 34d78b288f97..5e6a2c90b8e2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_platform.c
+++ b/drivers/gpu/drm/nouveau/nouveau_platform.c
@@ -152,7 +152,7 @@ static int nouveau_platform_remove(struct platform_device *pdev)
{
struct drm_device *drm_dev = platform_get_drvdata(pdev);
struct nouveau_drm *drm = nouveau_drm(drm_dev);
- struct nouveau_device *device = nvkm_device(&drm->device);
+ struct nouveau_device *device = nvxx_device(&drm->device);
struct nouveau_platform_gpu *gpu = nv_device_to_platform(device)->gpu;
nouveau_drm_device_remove(drm_dev);
diff --git a/drivers/gpu/drm/nouveau/nouveau_sysfs.c b/drivers/gpu/drm/nouveau/nouveau_sysfs.c
index 8fbbf3093d86..1ec8f38ae69a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sysfs.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sysfs.c
@@ -165,7 +165,7 @@ nouveau_sysfs_fini(struct drm_device *dev)
struct nvif_device *device = &drm->device;
if (sysfs && sysfs->ctrl.priv) {
- device_remove_file(nv_device_base(nvkm_device(device)), &dev_attr_pstate);
+ device_remove_file(nv_device_base(nvxx_device(device)), &dev_attr_pstate);
nvif_object_fini(&sysfs->ctrl);
}
@@ -192,7 +192,7 @@ nouveau_sysfs_init(struct drm_device *dev)
NVIF_IOCTL_NEW_V0_CONTROL, NULL, 0,
&sysfs->ctrl);
if (ret == 0)
- device_create_file(nv_device_base(nvkm_device(device)), &dev_attr_pstate);
+ device_create_file(nv_device_base(nvxx_device(device)), &dev_attr_pstate);
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index aa8321706103..7149f6d1fb43 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -33,7 +33,7 @@ static int
nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
struct nouveau_drm *drm = nouveau_bdev(man->bdev);
- struct nouveau_fb *pfb = nvkm_fb(&drm->device);
+ struct nouveau_fb *pfb = nvxx_fb(&drm->device);
man->priv = pfb;
return 0;
}
@@ -64,7 +64,7 @@ nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
struct ttm_mem_reg *mem)
{
struct nouveau_drm *drm = nouveau_bdev(man->bdev);
- struct nouveau_fb *pfb = nvkm_fb(&drm->device);
+ struct nouveau_fb *pfb = nvxx_fb(&drm->device);
nouveau_mem_node_cleanup(mem->mm_node);
pfb->ram->put(pfb, (struct nouveau_mem **)&mem->mm_node);
}
@@ -76,7 +76,7 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
struct ttm_mem_reg *mem)
{
struct nouveau_drm *drm = nouveau_bdev(man->bdev);
- struct nouveau_fb *pfb = nvkm_fb(&drm->device);
+ struct nouveau_fb *pfb = nvxx_fb(&drm->device);
struct nouveau_bo *nvbo = nouveau_bo(bo);
struct nouveau_mem *node;
u32 size_nc = 0;
@@ -208,7 +208,7 @@ static int
nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
struct nouveau_drm *drm = nouveau_bdev(man->bdev);
- struct nouveau_mmu *mmu = nvkm_mmu(&drm->device);
+ struct nouveau_mmu *mmu = nvxx_mmu(&drm->device);
struct nv04_mmu_priv *priv = (void *)mmu;
struct nouveau_vm *vm = NULL;
nouveau_vm_ref(priv->vm, &vm, NULL);
@@ -354,8 +354,8 @@ nouveau_ttm_init(struct nouveau_drm *drm)
u32 bits;
int ret;
- bits = nvkm_mmu(&drm->device)->dma_bits;
- if (nv_device_is_pci(nvkm_device(&drm->device))) {
+ bits = nvxx_mmu(&drm->device)->dma_bits;
+ if (nv_device_is_pci(nvxx_device(&drm->device))) {
if (drm->agp.stat == ENABLED ||
!pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits)))
bits = 32;
@@ -396,12 +396,12 @@ nouveau_ttm_init(struct nouveau_drm *drm)
return ret;
}
- drm->ttm.mtrr = arch_phys_wc_add(nv_device_resource_start(nvkm_device(&drm->device), 1),
- nv_device_resource_len(nvkm_device(&drm->device), 1));
+ drm->ttm.mtrr = arch_phys_wc_add(nv_device_resource_start(nvxx_device(&drm->device), 1),
+ nv_device_resource_len(nvxx_device(&drm->device), 1));
/* GART init */
if (drm->agp.stat != ENABLED) {
- drm->gem.gart_available = nvkm_mmu(&drm->device)->limit;
+ drm->gem.gart_available = nvxx_mmu(&drm->device)->limit;
} else {
drm->gem.gart_available = drm->agp.size;
}
diff --git a/drivers/gpu/drm/nouveau/nv04_fence.c b/drivers/gpu/drm/nouveau/nv04_fence.c
index f9859deb108a..af0eaa7bcb33 100644
--- a/drivers/gpu/drm/nouveau/nv04_fence.c
+++ b/drivers/gpu/drm/nouveau/nv04_fence.c
@@ -57,7 +57,7 @@ nv04_fence_sync(struct nouveau_fence *fence,
static u32
nv04_fence_read(struct nouveau_channel *chan)
{
- struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(chan);;
+ struct nouveau_fifo_chan *fifo = nvxx_fifo_chan(chan);;
return atomic_read(&fifo->refcnt);
}
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 113e8cdb0b2b..bba84448144e 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -200,7 +200,7 @@ nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
nv50_chan_destroy(&dmac->base);
if (dmac->ptr) {
- struct pci_dev *pdev = nvkm_device(nvif_device(disp))->pdev;
+ struct pci_dev *pdev = nvxx_device(nvif_device(disp))->pdev;
pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
}
}
@@ -217,7 +217,7 @@ nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head,
mutex_init(&dmac->lock);
- dmac->ptr = pci_alloc_consistent(nvkm_device(device)->pdev,
+ dmac->ptr = pci_alloc_consistent(nvxx_device(device)->pdev,
PAGE_SIZE, &dmac->handle);
if (!dmac->ptr)
return -ENOMEM;
@@ -420,9 +420,9 @@ evo_wait(void *evoc, int nr)
dmac->ptr[put] = 0x20000000;
nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
- if (!nvkm_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) {
+ if (!nvxx_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) {
mutex_unlock(&dmac->lock);
- nv_error(nvkm_object(&dmac->base.user), "channel stalled\n");
+ nv_error(nvxx_object(&dmac->base.user), "channel stalled\n");
return NULL;
}
@@ -480,7 +480,7 @@ evo_sync(struct drm_device *dev)
evo_data(push, 0x00000000);
evo_data(push, 0x00000000);
evo_kick(push, mast);
- if (nv_wait_cb(nvkm_device(device), evo_sync_wait, disp->sync))
+ if (nv_wait_cb(nvxx_device(device), evo_sync_wait, disp->sync))
return 0;
}
@@ -535,7 +535,7 @@ nv50_display_flip_stop(struct drm_crtc *crtc)
evo_kick(push, flip.chan);
}
- nv_wait_cb(nvkm_device(device), nv50_display_flip_wait, &flip);
+ nv_wait_cb(nvxx_device(device), nv50_display_flip_wait, &flip);
}
int
@@ -1677,7 +1677,7 @@ static int
nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
{
struct nouveau_drm *drm = nouveau_drm(connector->dev);
- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
+ struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
struct nouveau_encoder *nv_encoder;
struct drm_encoder *encoder;
int type = DRM_MODE_ENCODER_DAC;
@@ -2062,7 +2062,7 @@ static int
nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
{
struct nouveau_drm *drm = nouveau_drm(connector->dev);
- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
+ struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
struct nouveau_encoder *nv_encoder;
struct drm_encoder *encoder;
int type;
@@ -2233,7 +2233,7 @@ static int
nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
{
struct nouveau_drm *drm = nouveau_drm(connector->dev);
- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
+ struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
struct nouveau_i2c_port *ddc = NULL;
struct nouveau_encoder *nv_encoder;
struct drm_encoder *encoder;
diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c
index cb5b88938d45..46fe1fb5c9be 100644
--- a/drivers/gpu/drm/nouveau/nv84_fence.c
+++ b/drivers/gpu/drm/nouveau/nv84_fence.c
@@ -213,7 +213,7 @@ nv84_fence_destroy(struct nouveau_drm *drm)
int
nv84_fence_create(struct nouveau_drm *drm)
{
- struct nouveau_fifo *pfifo = nvkm_fifo(&drm->device);
+ struct nouveau_fifo *pfifo = nvxx_fifo(&drm->device);
struct nv84_fence_priv *priv;
int ret;
From 5025407b9862349d17b1dff25737aaef6520a439 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 14:11:21 +1000
Subject: [PATCH 51/86] drm/nouveau/core: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/core/client.h | 48 +++--
.../gpu/drm/nouveau/include/nvkm/core/debug.h | 6 +-
.../drm/nouveau/include/nvkm/core/device.h | 37 ++--
.../drm/nouveau/include/nvkm/core/engctx.h | 49 +++--
.../drm/nouveau/include/nvkm/core/engine.h | 51 +++--
.../gpu/drm/nouveau/include/nvkm/core/enum.h | 19 +-
.../gpu/drm/nouveau/include/nvkm/core/event.h | 27 ++-
.../drm/nouveau/include/nvkm/core/gpuobj.h | 73 +++----
.../drm/nouveau/include/nvkm/core/handle.h | 36 ++--
.../gpu/drm/nouveau/include/nvkm/core/ioctl.h | 5 +-
.../gpu/drm/nouveau/include/nvkm/core/mm.h | 26 +--
.../drm/nouveau/include/nvkm/core/namedb.h | 65 +++---
.../drm/nouveau/include/nvkm/core/notify.h | 5 +-
.../drm/nouveau/include/nvkm/core/object.h | 109 +++++-----
.../drm/nouveau/include/nvkm/core/option.h | 13 +-
.../gpu/drm/nouveau/include/nvkm/core/os.h | 191 ++++++++++++++++++
.../drm/nouveau/include/nvkm/core/parent.h | 70 +++----
.../drm/nouveau/include/nvkm/core/printk.h | 13 +-
.../gpu/drm/nouveau/include/nvkm/core/ramht.h | 23 +--
.../drm/nouveau/include/nvkm/core/subdev.h | 52 +++--
.../drm/nouveau/include/nvkm/engine/device.h | 3 -
.../drm/nouveau/include/nvkm/engine/falcon.h | 86 ++++----
.../drm/nouveau/include/nvkm/engine/xtensa.h | 45 ++---
.../gpu/drm/nouveau/include/nvkm/subdev/clk.h | 1 +
drivers/gpu/drm/nouveau/nouveau_nvif.c | 10 +-
drivers/gpu/drm/nouveau/nvif/notify.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/core/client.c | 93 ++++-----
drivers/gpu/drm/nouveau/nvkm/core/engctx.c | 122 +++++------
drivers/gpu/drm/nouveau/nvkm/core/engine.c | 30 ++-
drivers/gpu/drm/nouveau/nvkm/core/enum.c | 14 +-
drivers/gpu/drm/nouveau/nvkm/core/event.c | 3 +-
drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c | 190 +++++++++--------
drivers/gpu/drm/nouveau/nvkm/core/handle.c | 97 +++++----
drivers/gpu/drm/nouveau/nvkm/core/ioctl.c | 162 +++++++--------
drivers/gpu/drm/nouveau/nvkm/core/mm.c | 71 +++----
drivers/gpu/drm/nouveau/nvkm/core/namedb.c | 108 +++++-----
drivers/gpu/drm/nouveau/nvkm/core/notify.c | 9 +-
drivers/gpu/drm/nouveau/nvkm/core/object.c | 106 +++++-----
drivers/gpu/drm/nouveau/nvkm/core/option.c | 9 +-
drivers/gpu/drm/nouveau/nvkm/core/parent.c | 54 +++--
drivers/gpu/drm/nouveau/nvkm/core/printk.c | 12 +-
drivers/gpu/drm/nouveau/nvkm/core/ramht.c | 45 ++---
drivers/gpu/drm/nouveau/nvkm/core/subdev.c | 55 +++--
.../gpu/drm/nouveau/nvkm/engine/bsp/nv84.c | 2 +
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 1 +
.../gpu/drm/nouveau/nvkm/engine/disp/conn.h | 3 +-
.../gpu/drm/nouveau/nvkm/engine/disp/outpdp.h | 1 +
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c | 50 +++--
.../gpu/drm/nouveau/nvkm/engine/fifo/base.c | 2 +
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h | 2 +-
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h | 2 +-
drivers/gpu/drm/nouveau/nvkm/engine/vp/nv84.c | 2 +
drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c | 69 +++----
.../gpu/drm/nouveau/nvkm/subdev/gpio/base.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/i2c/base.c | 1 +
55 files changed, 1232 insertions(+), 1149 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h
index 827c4e972ed3..a35b38244502 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h
@@ -1,15 +1,14 @@
-#ifndef __NOUVEAU_CLIENT_H__
-#define __NOUVEAU_CLIENT_H__
-
+#ifndef __NVKM_CLIENT_H__
+#define __NVKM_CLIENT_H__
#include <core/namedb.h>
-struct nouveau_client {
- struct nouveau_namedb namedb;
- struct nouveau_handle *root;
- struct nouveau_object *device;
+struct nvkm_client {
+ struct nvkm_namedb namedb;
+ struct nvkm_handle *root;
+ struct nvkm_object *device;
char name[32];
u32 debug;
- struct nouveau_vm *vm;
+ struct nvkm_vm *vm;
bool super;
void *data;
@@ -17,7 +16,7 @@ struct nouveau_client {
struct nvkm_client_notify *notify[16];
};
-static inline struct nouveau_client *
+static inline struct nvkm_client *
nv_client(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
@@ -27,31 +26,30 @@ nv_client(void *obj)
return obj;
}
-static inline struct nouveau_client *
-nouveau_client(void *obj)
+static inline struct nvkm_client *
+nvkm_client(void *obj)
{
- struct nouveau_object *client = nv_object(obj);
+ struct nvkm_object *client = nv_object(obj);
while (client && !(nv_iclass(client, NV_CLIENT_CLASS)))
client = client->parent;
return (void *)client;
}
-#define nouveau_client_create(n,c,oc,od,d) \
- nouveau_client_create_((n), (c), (oc), (od), sizeof(**d), (void **)d)
+#define nvkm_client_create(n,c,oc,od,d) \
+ nvkm_client_create_((n), (c), (oc), (od), sizeof(**d), (void **)d)
-int nouveau_client_create_(const char *name, u64 device, const char *cfg,
+int nvkm_client_create_(const char *name, u64 device, const char *cfg,
const char *dbg, int, void **);
-#define nouveau_client_destroy(p) \
- nouveau_namedb_destroy(&(p)->base)
+#define nvkm_client_destroy(p) \
+ nvkm_namedb_destroy(&(p)->base)
-int nouveau_client_init(struct nouveau_client *);
-int nouveau_client_fini(struct nouveau_client *, bool suspend);
-const char *nouveau_client_name(void *obj);
+int nvkm_client_init(struct nvkm_client *);
+int nvkm_client_fini(struct nvkm_client *, bool suspend);
+const char *nvkm_client_name(void *obj);
-int nvkm_client_notify_new(struct nouveau_object *, struct nvkm_event *,
+int nvkm_client_notify_new(struct nvkm_object *, struct nvkm_event *,
void *data, u32 size);
-int nvkm_client_notify_del(struct nouveau_client *, int index);
-int nvkm_client_notify_get(struct nouveau_client *, int index);
-int nvkm_client_notify_put(struct nouveau_client *, int index);
-
+int nvkm_client_notify_del(struct nvkm_client *, int index);
+int nvkm_client_notify_get(struct nvkm_client *, int index);
+int nvkm_client_notify_put(struct nvkm_client *, int index);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/debug.h b/drivers/gpu/drm/nouveau/include/nvkm/core/debug.h
index 8092e2e90323..d07cb860b56c 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/debug.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/debug.h
@@ -1,6 +1,5 @@
-#ifndef __NOUVEAU_DEBUG_H__
-#define __NOUVEAU_DEBUG_H__
-
+#ifndef __NVKM_DEBUG_H__
+#define __NVKM_DEBUG_H__
extern int nv_info_debug_level;
#define NV_DBG_FATAL 0
@@ -16,5 +15,4 @@ extern int nv_info_debug_level;
#define NV_DBG_INFO_SILENT NV_DBG_DEBUG
#define nv_debug_level(a) nv_info_debug_level = NV_DBG_INFO_##a
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 23d71c58c3f1..9c2f13694a57 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -1,13 +1,10 @@
-#ifndef __NOUVEAU_DEVICE_H__
-#define __NOUVEAU_DEVICE_H__
-
-#include <core/object.h>
-#include <core/subdev.h>
+#ifndef __NVKM_DEVICE_H__
+#define __NVKM_DEVICE_H__
#include <core/engine.h>
#include <core/event.h>
-struct nouveau_device {
- struct nouveau_engine engine;
+struct nvkm_device {
+ struct nvkm_engine engine;
struct list_head head;
struct pci_dev *pdev;
@@ -38,53 +35,53 @@ struct nouveau_device {
u8 chiprev;
u32 crystal;
- struct nouveau_oclass *oclass[NVDEV_SUBDEV_NR];
- struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
+ struct nvkm_oclass *oclass[NVDEV_SUBDEV_NR];
+ struct nvkm_object *subdev[NVDEV_SUBDEV_NR];
struct {
struct notifier_block nb;
} acpi;
};
-int nouveau_device_list(u64 *name, int size);
+struct nvkm_device *nvkm_device_find(u64 name);
+int nvkm_device_list(u64 *name, int size);
-struct nouveau_device *nv_device(void *obj);
+struct nvkm_device *nv_device(void *obj);
static inline bool
-nv_device_match(struct nouveau_object *object, u16 dev, u16 ven, u16 sub)
+nv_device_match(struct nvkm_object *object, u16 dev, u16 ven, u16 sub)
{
- struct nouveau_device *device = nv_device(object);
+ struct nvkm_device *device = nv_device(object);
return device->pdev->device == dev &&
device->pdev->subsystem_vendor == ven &&
device->pdev->subsystem_device == sub;
}
static inline bool
-nv_device_is_pci(struct nouveau_device *device)
+nv_device_is_pci(struct nvkm_device *device)
{
return device->pdev != NULL;
}
static inline bool
-nv_device_is_cpu_coherent(struct nouveau_device *device)
+nv_device_is_cpu_coherent(struct nvkm_device *device)
{
return (!IS_ENABLED(CONFIG_ARM) && nv_device_is_pci(device));
}
static inline struct device *
-nv_device_base(struct nouveau_device *device)
+nv_device_base(struct nvkm_device *device)
{
return nv_device_is_pci(device) ? &device->pdev->dev :
&device->platformdev->dev;
}
resource_size_t
-nv_device_resource_start(struct nouveau_device *device, unsigned int bar);
+nv_device_resource_start(struct nvkm_device *device, unsigned int bar);
resource_size_t
-nv_device_resource_len(struct nouveau_device *device, unsigned int bar);
+nv_device_resource_len(struct nvkm_device *device, unsigned int bar);
int
-nv_device_get_irq(struct nouveau_device *device, bool stall);
-
+nv_device_get_irq(struct nvkm_device *device, bool stall);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h
index 9d696e4747e7..1bf2e8eb4268 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h
@@ -1,7 +1,5 @@
-#ifndef __NOUVEAU_ENGCTX_H__
-#define __NOUVEAU_ENGCTX_H__
-
-#include <core/object.h>
+#ifndef __NVKM_ENGCTX_H__
+#define __NVKM_ENGCTX_H__
#include <core/gpuobj.h>
#include <subdev/mmu.h>
@@ -9,15 +7,15 @@
#define NV_ENGCTX_(eng,var) (NV_ENGCTX_CLASS | ((var) << 8) | (eng))
#define NV_ENGCTX(name,var) NV_ENGCTX_(NVDEV_ENGINE_##name, (var))
-struct nouveau_engctx {
- struct nouveau_gpuobj gpuobj;
- struct nouveau_vma vma;
+struct nvkm_engctx {
+ struct nvkm_gpuobj gpuobj;
+ struct nvkm_vma vma;
struct list_head head;
unsigned long save;
u64 addr;
};
-static inline struct nouveau_engctx *
+static inline struct nvkm_engctx *
nv_engctx(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
@@ -27,28 +25,27 @@ nv_engctx(void *obj)
return obj;
}
-#define nouveau_engctx_create(p,e,c,g,s,a,f,d) \
- nouveau_engctx_create_((p), (e), (c), (g), (s), (a), (f), \
+#define nvkm_engctx_create(p,e,c,g,s,a,f,d) \
+ nvkm_engctx_create_((p), (e), (c), (g), (s), (a), (f), \
sizeof(**d), (void **)d)
-int nouveau_engctx_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, struct nouveau_object *,
+int nvkm_engctx_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, struct nvkm_object *,
u32 size, u32 align, u32 flags,
int length, void **data);
-void nouveau_engctx_destroy(struct nouveau_engctx *);
-int nouveau_engctx_init(struct nouveau_engctx *);
-int nouveau_engctx_fini(struct nouveau_engctx *, bool suspend);
+void nvkm_engctx_destroy(struct nvkm_engctx *);
+int nvkm_engctx_init(struct nvkm_engctx *);
+int nvkm_engctx_fini(struct nvkm_engctx *, bool suspend);
-int _nouveau_engctx_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void _nouveau_engctx_dtor(struct nouveau_object *);
-int _nouveau_engctx_init(struct nouveau_object *);
-int _nouveau_engctx_fini(struct nouveau_object *, bool suspend);
-#define _nouveau_engctx_rd32 _nouveau_gpuobj_rd32
-#define _nouveau_engctx_wr32 _nouveau_gpuobj_wr32
-
-struct nouveau_object *nouveau_engctx_get(struct nouveau_engine *, u64 addr);
-void nouveau_engctx_put(struct nouveau_object *);
+int _nvkm_engctx_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void _nvkm_engctx_dtor(struct nvkm_object *);
+int _nvkm_engctx_init(struct nvkm_object *);
+int _nvkm_engctx_fini(struct nvkm_object *, bool suspend);
+#define _nvkm_engctx_rd32 _nvkm_gpuobj_rd32
+#define _nvkm_engctx_wr32 _nvkm_gpuobj_wr32
+struct nvkm_object *nvkm_engctx_get(struct nvkm_engine *, u64 addr);
+void nvkm_engctx_put(struct nvkm_object *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
index d7ebd35ef1ad..faf0fd2f0638 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
@@ -1,25 +1,23 @@
-#ifndef __NOUVEAU_ENGINE_H__
-#define __NOUVEAU_ENGINE_H__
-
-#include <core/object.h>
+#ifndef __NVKM_ENGINE_H__
+#define __NVKM_ENGINE_H__
#include <core/subdev.h>
#define NV_ENGINE_(eng,var) (NV_ENGINE_CLASS | ((var) << 8) | (eng))
#define NV_ENGINE(name,var) NV_ENGINE_(NVDEV_ENGINE_##name, (var))
-struct nouveau_engine {
- struct nouveau_subdev subdev;
- struct nouveau_oclass *cclass;
- struct nouveau_oclass *sclass;
+struct nvkm_engine {
+ struct nvkm_subdev subdev;
+ struct nvkm_oclass *cclass;
+ struct nvkm_oclass *sclass;
struct list_head contexts;
spinlock_t lock;
- void (*tile_prog)(struct nouveau_engine *, int region);
- int (*tlb_flush)(struct nouveau_engine *);
+ void (*tile_prog)(struct nvkm_engine *, int region);
+ int (*tlb_flush)(struct nvkm_engine *);
};
-static inline struct nouveau_engine *
+static inline struct nvkm_engine *
nv_engine(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
@@ -30,30 +28,29 @@ nv_engine(void *obj)
}
static inline int
-nv_engidx(struct nouveau_engine *engine)
+nv_engidx(struct nvkm_engine *engine)
{
return nv_subidx(&engine->subdev);
}
-struct nouveau_engine *nouveau_engine(void *obj, int idx);
+struct nvkm_engine *nvkm_engine(void *obj, int idx);
-#define nouveau_engine_create(p,e,c,d,i,f,r) \
- nouveau_engine_create_((p), (e), (c), (d), (i), (f), \
+#define nvkm_engine_create(p,e,c,d,i,f,r) \
+ nvkm_engine_create_((p), (e), (c), (d), (i), (f), \
sizeof(**r),(void **)r)
-#define nouveau_engine_destroy(p) \
- nouveau_subdev_destroy(&(p)->subdev)
-#define nouveau_engine_init(p) \
- nouveau_subdev_init(&(p)->subdev)
-#define nouveau_engine_fini(p,s) \
- nouveau_subdev_fini(&(p)->subdev, (s))
+#define nvkm_engine_destroy(p) \
+ nvkm_subdev_destroy(&(p)->subdev)
+#define nvkm_engine_init(p) \
+ nvkm_subdev_init(&(p)->subdev)
+#define nvkm_engine_fini(p,s) \
+ nvkm_subdev_fini(&(p)->subdev, (s))
-int nouveau_engine_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, bool, const char *,
+int nvkm_engine_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, bool, const char *,
const char *, int, void **);
-#define _nouveau_engine_dtor _nouveau_subdev_dtor
-#define _nouveau_engine_init _nouveau_subdev_init
-#define _nouveau_engine_fini _nouveau_subdev_fini
-
+#define _nvkm_engine_dtor _nvkm_subdev_dtor
+#define _nvkm_engine_init _nvkm_subdev_init
+#define _nvkm_engine_fini _nvkm_subdev_fini
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h b/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h
index 4fc62bb8c1f0..e76f76f115e9 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h
@@ -1,24 +1,21 @@
-#ifndef __NOUVEAU_ENUM_H__
-#define __NOUVEAU_ENUM_H__
+#ifndef __NVKM_ENUM_H__
+#define __NVKM_ENUM_H__
+#include <core/os.h>
-struct nouveau_enum {
+struct nvkm_enum {
u32 value;
const char *name;
const void *data;
u32 data2;
};
-const struct nouveau_enum *
-nouveau_enum_find(const struct nouveau_enum *, u32 value);
+const struct nvkm_enum *nvkm_enum_find(const struct nvkm_enum *, u32 value);
+const struct nvkm_enum *nvkm_enum_print(const struct nvkm_enum *, u32 value);
-const struct nouveau_enum *
-nouveau_enum_print(const struct nouveau_enum *en, u32 value);
-
-struct nouveau_bitfield {
+struct nvkm_bitfield {
u32 mask;
const char *name;
};
-void nouveau_bitfield_print(const struct nouveau_bitfield *, u32 value);
-
+void nvkm_bitfield_print(const struct nvkm_bitfield *, u32 value);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/event.h b/drivers/gpu/drm/nouveau/include/nvkm/core/event.h
index 92876528972f..b98fe2de546a 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/event.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/event.h
@@ -1,15 +1,8 @@
#ifndef __NVKM_EVENT_H__
#define __NVKM_EVENT_H__
-
-#include <core/notify.h>
-
-struct nvkm_event_func {
- int (*ctor)(struct nouveau_object *, void *data, u32 size,
- struct nvkm_notify *);
- void (*send)(void *data, u32 size, struct nvkm_notify *);
- void (*init)(struct nvkm_event *, int type, int index);
- void (*fini)(struct nvkm_event *, int type, int index);
-};
+#include <core/os.h>
+struct nvkm_notify;
+struct nvkm_object;
struct nvkm_event {
const struct nvkm_event_func *func;
@@ -23,13 +16,19 @@ struct nvkm_event {
int *refs;
};
-int nvkm_event_init(const struct nvkm_event_func *func,
- int types_nr, int index_nr,
- struct nvkm_event *);
+struct nvkm_event_func {
+ int (*ctor)(struct nvkm_object *, void *data, u32 size,
+ struct nvkm_notify *);
+ void (*send)(void *data, u32 size, struct nvkm_notify *);
+ void (*init)(struct nvkm_event *, int type, int index);
+ void (*fini)(struct nvkm_event *, int type, int index);
+};
+
+int nvkm_event_init(const struct nvkm_event_func *func, int types_nr,
+ int index_nr, struct nvkm_event *);
void nvkm_event_fini(struct nvkm_event *);
void nvkm_event_get(struct nvkm_event *, u32 types, int index);
void nvkm_event_put(struct nvkm_event *, u32 types, int index);
void nvkm_event_send(struct nvkm_event *, u32 types, int index,
void *data, u32 size);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h
index c262c2505164..e0187e7abb6e 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h
@@ -1,30 +1,26 @@
-#ifndef __NOUVEAU_GPUOBJ_H__
-#define __NOUVEAU_GPUOBJ_H__
-
+#ifndef __NVKM_GPUOBJ_H__
+#define __NVKM_GPUOBJ_H__
#include <core/object.h>
-#include <core/device.h>
-#include <core/parent.h>
#include <core/mm.h>
-
-struct nouveau_vma;
-struct nouveau_vm;
+struct nvkm_vma;
+struct nvkm_vm;
#define NVOBJ_FLAG_ZERO_ALLOC 0x00000001
#define NVOBJ_FLAG_ZERO_FREE 0x00000002
#define NVOBJ_FLAG_HEAP 0x00000004
-struct nouveau_gpuobj {
- struct nouveau_object object;
- struct nouveau_object *parent;
- struct nouveau_mm_node *node;
- struct nouveau_mm heap;
+struct nvkm_gpuobj {
+ struct nvkm_object object;
+ struct nvkm_object *parent;
+ struct nvkm_mm_node *node;
+ struct nvkm_mm heap;
u32 flags;
u64 addr;
u32 size;
};
-static inline struct nouveau_gpuobj *
+static inline struct nvkm_gpuobj *
nv_gpuobj(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
@@ -34,38 +30,35 @@ nv_gpuobj(void *obj)
return obj;
}
-#define nouveau_gpuobj_create(p,e,c,v,g,s,a,f,d) \
- nouveau_gpuobj_create_((p), (e), (c), (v), (g), (s), (a), (f), \
+#define nvkm_gpuobj_create(p,e,c,v,g,s,a,f,d) \
+ nvkm_gpuobj_create_((p), (e), (c), (v), (g), (s), (a), (f), \
sizeof(**d), (void **)d)
-#define nouveau_gpuobj_init(p) nouveau_object_init(&(p)->object)
-#define nouveau_gpuobj_fini(p,s) nouveau_object_fini(&(p)->object, (s))
-int nouveau_gpuobj_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, u32 pclass,
- struct nouveau_object *, u32 size, u32 align,
+#define nvkm_gpuobj_init(p) nvkm_object_init(&(p)->object)
+#define nvkm_gpuobj_fini(p,s) nvkm_object_fini(&(p)->object, (s))
+int nvkm_gpuobj_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, u32 pclass,
+ struct nvkm_object *, u32 size, u32 align,
u32 flags, int length, void **);
-void nouveau_gpuobj_destroy(struct nouveau_gpuobj *);
+void nvkm_gpuobj_destroy(struct nvkm_gpuobj *);
-int nouveau_gpuobj_new(struct nouveau_object *, struct nouveau_object *,
- u32 size, u32 align, u32 flags,
- struct nouveau_gpuobj **);
-int nouveau_gpuobj_dup(struct nouveau_object *, struct nouveau_gpuobj *,
- struct nouveau_gpuobj **);
-
-int nouveau_gpuobj_map(struct nouveau_gpuobj *, u32 acc, struct nouveau_vma *);
-int nouveau_gpuobj_map_vm(struct nouveau_gpuobj *, struct nouveau_vm *,
- u32 access, struct nouveau_vma *);
-void nouveau_gpuobj_unmap(struct nouveau_vma *);
+int nvkm_gpuobj_new(struct nvkm_object *, struct nvkm_object *, u32 size,
+ u32 align, u32 flags, struct nvkm_gpuobj **);
+int nvkm_gpuobj_dup(struct nvkm_object *, struct nvkm_gpuobj *,
+ struct nvkm_gpuobj **);
+int nvkm_gpuobj_map(struct nvkm_gpuobj *, u32 acc, struct nvkm_vma *);
+int nvkm_gpuobj_map_vm(struct nvkm_gpuobj *, struct nvkm_vm *, u32 access,
+ struct nvkm_vma *);
+void nvkm_gpuobj_unmap(struct nvkm_vma *);
static inline void
-nouveau_gpuobj_ref(struct nouveau_gpuobj *obj, struct nouveau_gpuobj **ref)
+nvkm_gpuobj_ref(struct nvkm_gpuobj *obj, struct nvkm_gpuobj **ref)
{
- nouveau_object_ref(&obj->object, (struct nouveau_object **)ref);
+ nvkm_object_ref(&obj->object, (struct nvkm_object **)ref);
}
-void _nouveau_gpuobj_dtor(struct nouveau_object *);
-int _nouveau_gpuobj_init(struct nouveau_object *);
-int _nouveau_gpuobj_fini(struct nouveau_object *, bool);
-u32 _nouveau_gpuobj_rd32(struct nouveau_object *, u64);
-void _nouveau_gpuobj_wr32(struct nouveau_object *, u64, u32);
-
+void _nvkm_gpuobj_dtor(struct nvkm_object *);
+int _nvkm_gpuobj_init(struct nvkm_object *);
+int _nvkm_gpuobj_fini(struct nvkm_object *, bool);
+u32 _nvkm_gpuobj_rd32(struct nvkm_object *, u64);
+void _nvkm_gpuobj_wr32(struct nvkm_object *, u64, u32);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/handle.h b/drivers/gpu/drm/nouveau/include/nvkm/core/handle.h
index d22a59138a9b..67f384d0916c 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/handle.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/handle.h
@@ -1,8 +1,10 @@
-#ifndef __NOUVEAU_HANDLE_H__
-#define __NOUVEAU_HANDLE_H__
+#ifndef __NVKM_HANDLE_H__
+#define __NVKM_HANDLE_H__
+#include <core/os.h>
+struct nvkm_object;
-struct nouveau_handle {
- struct nouveau_namedb *namedb;
+struct nvkm_handle {
+ struct nvkm_namedb *namedb;
struct list_head node;
struct list_head head;
@@ -13,22 +15,20 @@ struct nouveau_handle {
u8 route;
u64 token;
- struct nouveau_handle *parent;
- struct nouveau_object *object;
+ struct nvkm_handle *parent;
+ struct nvkm_object *object;
};
-int nouveau_handle_create(struct nouveau_object *, u32 parent, u32 handle,
- struct nouveau_object *, struct nouveau_handle **);
-void nouveau_handle_destroy(struct nouveau_handle *);
-int nouveau_handle_init(struct nouveau_handle *);
-int nouveau_handle_fini(struct nouveau_handle *, bool suspend);
+int nvkm_handle_create(struct nvkm_object *, u32 parent, u32 handle,
+ struct nvkm_object *, struct nvkm_handle **);
+void nvkm_handle_destroy(struct nvkm_handle *);
+int nvkm_handle_init(struct nvkm_handle *);
+int nvkm_handle_fini(struct nvkm_handle *, bool suspend);
-struct nouveau_object *
-nouveau_handle_ref(struct nouveau_object *, u32 name);
-
-struct nouveau_handle *nouveau_handle_get_class(struct nouveau_object *, u16);
-struct nouveau_handle *nouveau_handle_get_vinst(struct nouveau_object *, u64);
-struct nouveau_handle *nouveau_handle_get_cinst(struct nouveau_object *, u32);
-void nouveau_handle_put(struct nouveau_handle *);
+struct nvkm_object *nvkm_handle_ref(struct nvkm_object *, u32 name);
+struct nvkm_handle *nvkm_handle_get_class(struct nvkm_object *, u16);
+struct nvkm_handle *nvkm_handle_get_vinst(struct nvkm_object *, u64);
+struct nvkm_handle *nvkm_handle_get_cinst(struct nvkm_object *, u32);
+void nvkm_handle_put(struct nvkm_handle *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h b/drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h
index ac7935c2474e..88971eb37afa 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h
@@ -1,6 +1,7 @@
#ifndef __NVKM_IOCTL_H__
#define __NVKM_IOCTL_H__
+#include <core/os.h>
+struct nvkm_client;
-int nvkm_ioctl(struct nouveau_client *, bool, void *, u32, void **);
-
+int nvkm_ioctl(struct nvkm_client *, bool, void *, u32, void **);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h b/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h
index bfe6931544fe..096eb1a623ee 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h
@@ -1,7 +1,8 @@
-#ifndef __NOUVEAU_MM_H__
-#define __NOUVEAU_MM_H__
+#ifndef __NVKM_MM_H__
+#define __NVKM_MM_H__
+#include <core/os.h>
-struct nouveau_mm_node {
+struct nvkm_mm_node {
struct list_head nl_entry;
struct list_head fl_entry;
struct list_head rl_entry;
@@ -15,7 +16,7 @@ struct nouveau_mm_node {
u32 length;
};
-struct nouveau_mm {
+struct nvkm_mm {
struct list_head nodes;
struct list_head free;
@@ -24,17 +25,16 @@ struct nouveau_mm {
};
static inline bool
-nouveau_mm_initialised(struct nouveau_mm *mm)
+nvkm_mm_initialised(struct nvkm_mm *mm)
{
return mm->block_size != 0;
}
-int nouveau_mm_init(struct nouveau_mm *, u32 offset, u32 length, u32 block);
-int nouveau_mm_fini(struct nouveau_mm *);
-int nouveau_mm_head(struct nouveau_mm *, u8 heap, u8 type, u32 size_max,
- u32 size_min, u32 align, struct nouveau_mm_node **);
-int nouveau_mm_tail(struct nouveau_mm *, u8 heap, u8 type, u32 size_max,
- u32 size_min, u32 align, struct nouveau_mm_node **);
-void nouveau_mm_free(struct nouveau_mm *, struct nouveau_mm_node **);
-
+int nvkm_mm_init(struct nvkm_mm *, u32 offset, u32 length, u32 block);
+int nvkm_mm_fini(struct nvkm_mm *);
+int nvkm_mm_head(struct nvkm_mm *, u8 heap, u8 type, u32 size_max,
+ u32 size_min, u32 align, struct nvkm_mm_node **);
+int nvkm_mm_tail(struct nvkm_mm *, u8 heap, u8 type, u32 size_max,
+ u32 size_min, u32 align, struct nvkm_mm_node **);
+void nvkm_mm_free(struct nvkm_mm *, struct nvkm_mm_node **);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h b/drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h
index 98e666b1e375..4cfe16fcde9b 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h
@@ -1,17 +1,15 @@
-#ifndef __NOUVEAU_NAMEDB_H__
-#define __NOUVEAU_NAMEDB_H__
-
+#ifndef __NVKM_NAMEDB_H__
+#define __NVKM_NAMEDB_H__
#include <core/parent.h>
+struct nvkm_handle;
-struct nouveau_handle;
-
-struct nouveau_namedb {
- struct nouveau_parent parent;
+struct nvkm_namedb {
+ struct nvkm_parent parent;
rwlock_t lock;
struct list_head list;
};
-static inline struct nouveau_namedb *
+static inline struct nvkm_namedb *
nv_namedb(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
@@ -21,36 +19,35 @@ nv_namedb(void *obj)
return obj;
}
-#define nouveau_namedb_create(p,e,c,v,s,m,d) \
- nouveau_namedb_create_((p), (e), (c), (v), (s), (m), \
+#define nvkm_namedb_create(p,e,c,v,s,m,d) \
+ nvkm_namedb_create_((p), (e), (c), (v), (s), (m), \
sizeof(**d), (void **)d)
-#define nouveau_namedb_init(p) \
- nouveau_parent_init(&(p)->parent)
-#define nouveau_namedb_fini(p,s) \
- nouveau_parent_fini(&(p)->parent, (s))
-#define nouveau_namedb_destroy(p) \
- nouveau_parent_destroy(&(p)->parent)
+#define nvkm_namedb_init(p) \
+ nvkm_parent_init(&(p)->parent)
+#define nvkm_namedb_fini(p,s) \
+ nvkm_parent_fini(&(p)->parent, (s))
+#define nvkm_namedb_destroy(p) \
+ nvkm_parent_destroy(&(p)->parent)
-int nouveau_namedb_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, u32 pclass,
- struct nouveau_oclass *, u64 engcls,
+int nvkm_namedb_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, u32 pclass,
+ struct nvkm_oclass *, u64 engcls,
int size, void **);
-int _nouveau_namedb_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-#define _nouveau_namedb_dtor _nouveau_parent_dtor
-#define _nouveau_namedb_init _nouveau_parent_init
-#define _nouveau_namedb_fini _nouveau_parent_fini
+int _nvkm_namedb_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+#define _nvkm_namedb_dtor _nvkm_parent_dtor
+#define _nvkm_namedb_init _nvkm_parent_init
+#define _nvkm_namedb_fini _nvkm_parent_fini
-int nouveau_namedb_insert(struct nouveau_namedb *, u32 name,
- struct nouveau_object *, struct nouveau_handle *);
-void nouveau_namedb_remove(struct nouveau_handle *);
-
-struct nouveau_handle *nouveau_namedb_get(struct nouveau_namedb *, u32);
-struct nouveau_handle *nouveau_namedb_get_class(struct nouveau_namedb *, u16);
-struct nouveau_handle *nouveau_namedb_get_vinst(struct nouveau_namedb *, u64);
-struct nouveau_handle *nouveau_namedb_get_cinst(struct nouveau_namedb *, u32);
-void nouveau_namedb_put(struct nouveau_handle *);
+int nvkm_namedb_insert(struct nvkm_namedb *, u32 name, struct nvkm_object *,
+ struct nvkm_handle *);
+void nvkm_namedb_remove(struct nvkm_handle *);
+struct nvkm_handle *nvkm_namedb_get(struct nvkm_namedb *, u32);
+struct nvkm_handle *nvkm_namedb_get_class(struct nvkm_namedb *, u16);
+struct nvkm_handle *nvkm_namedb_get_vinst(struct nvkm_namedb *, u64);
+struct nvkm_handle *nvkm_namedb_get_cinst(struct nvkm_namedb *, u32);
+void nvkm_namedb_put(struct nvkm_handle *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/notify.h b/drivers/gpu/drm/nouveau/include/nvkm/core/notify.h
index a7c3c5f578cc..753d08c1767b 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/notify.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/notify.h
@@ -1,5 +1,7 @@
#ifndef __NVKM_NOTIFY_H__
#define __NVKM_NOTIFY_H__
+#include <core/os.h>
+struct nvkm_object;
struct nvkm_notify {
struct nvkm_event *event;
@@ -25,7 +27,7 @@ struct nvkm_notify {
const void *data;
};
-int nvkm_notify_init(struct nouveau_object *, struct nvkm_event *,
+int nvkm_notify_init(struct nvkm_object *, struct nvkm_event *,
int (*func)(struct nvkm_notify *), bool work,
void *data, u32 size, u32 reply,
struct nvkm_notify *);
@@ -33,5 +35,4 @@ void nvkm_notify_fini(struct nvkm_notify *);
void nvkm_notify_get(struct nvkm_notify *);
void nvkm_notify_put(struct nvkm_notify *);
void nvkm_notify_send(struct nvkm_notify *, void *data, u32 size);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/object.h b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h
index 64c0038f1971..6e3cd3908400 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/object.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h
@@ -1,6 +1,5 @@
-#ifndef __NOUVEAU_OBJECT_H__
-#define __NOUVEAU_OBJECT_H__
-
+#ifndef __NVKM_OBJECT_H__
+#define __NVKM_OBJECT_H__
#include <core/os.h>
#include <core/printk.h>
@@ -14,52 +13,52 @@
#define NV_ENGCTX_CLASS 0x01000000
#define NV_OBJECT_CLASS 0x0000ffff
-struct nouveau_object {
- struct nouveau_oclass *oclass;
- struct nouveau_object *parent;
- struct nouveau_engine *engine;
+struct nvkm_object {
+ struct nvkm_oclass *oclass;
+ struct nvkm_object *parent;
+ struct nvkm_engine *engine;
atomic_t refcount;
atomic_t usecount;
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
-#define NOUVEAU_OBJECT_MAGIC 0x75ef0bad
+#define NVKM_OBJECT_MAGIC 0x75ef0bad
struct list_head list;
u32 _magic;
#endif
};
-static inline struct nouveau_object *
+static inline struct nvkm_object *
nv_object(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
if (likely(obj)) {
- struct nouveau_object *object = obj;
- if (unlikely(object->_magic != NOUVEAU_OBJECT_MAGIC))
+ struct nvkm_object *object = obj;
+ if (unlikely(object->_magic != NVKM_OBJECT_MAGIC))
nv_assert("BAD CAST -> NvObject, invalid magic");
}
#endif
return obj;
}
-#define nouveau_object_create(p,e,c,s,d) \
- nouveau_object_create_((p), (e), (c), (s), sizeof(**d), (void **)d)
-int nouveau_object_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, u32, int size, void **);
-void nouveau_object_destroy(struct nouveau_object *);
-int nouveau_object_init(struct nouveau_object *);
-int nouveau_object_fini(struct nouveau_object *, bool suspend);
+#define nvkm_object_create(p,e,c,s,d) \
+ nvkm_object_create_((p), (e), (c), (s), sizeof(**d), (void **)d)
+int nvkm_object_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, u32, int size, void **);
+void nvkm_object_destroy(struct nvkm_object *);
+int nvkm_object_init(struct nvkm_object *);
+int nvkm_object_fini(struct nvkm_object *, bool suspend);
-int _nouveau_object_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
+int _nvkm_object_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
-extern struct nouveau_ofuncs nouveau_object_ofuncs;
+extern struct nvkm_ofuncs nvkm_object_ofuncs;
/* Don't allocate dynamically, because lockdep needs lock_class_keys to be in
* ".data". */
-struct nouveau_oclass {
+struct nvkm_oclass {
u32 handle;
- struct nouveau_ofuncs * const ofuncs;
- struct nouveau_omthds * const omthds;
+ struct nvkm_ofuncs * const ofuncs;
+ struct nvkm_omthds * const omthds;
struct lock_class_key lock_class_key;
};
@@ -68,58 +67,57 @@ struct nouveau_oclass {
#define nv_iclass(o,i) (nv_hclass(o) & (i))
#define nv_mclass(o) nv_iclass(o, NV_OBJECT_CLASS)
-static inline struct nouveau_object *
-nv_pclass(struct nouveau_object *parent, u32 oclass)
+static inline struct nvkm_object *
+nv_pclass(struct nvkm_object *parent, u32 oclass)
{
while (parent && !nv_iclass(parent, oclass))
parent = parent->parent;
return parent;
}
-struct nouveau_omthds {
+struct nvkm_omthds {
u32 start;
u32 limit;
- int (*call)(struct nouveau_object *, u32, void *, u32);
+ int (*call)(struct nvkm_object *, u32, void *, u32);
};
struct nvkm_event;
-struct nouveau_ofuncs {
- int (*ctor)(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *data, u32 size,
- struct nouveau_object **);
- void (*dtor)(struct nouveau_object *);
- int (*init)(struct nouveau_object *);
- int (*fini)(struct nouveau_object *, bool suspend);
- int (*mthd)(struct nouveau_object *, u32, void *, u32);
- int (*ntfy)(struct nouveau_object *, u32, struct nvkm_event **);
- int (* map)(struct nouveau_object *, u64 *, u32 *);
- u8 (*rd08)(struct nouveau_object *, u64 offset);
- u16 (*rd16)(struct nouveau_object *, u64 offset);
- u32 (*rd32)(struct nouveau_object *, u64 offset);
- void (*wr08)(struct nouveau_object *, u64 offset, u8 data);
- void (*wr16)(struct nouveau_object *, u64 offset, u16 data);
- void (*wr32)(struct nouveau_object *, u64 offset, u32 data);
+struct nvkm_ofuncs {
+ int (*ctor)(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *data, u32 size,
+ struct nvkm_object **);
+ void (*dtor)(struct nvkm_object *);
+ int (*init)(struct nvkm_object *);
+ int (*fini)(struct nvkm_object *, bool suspend);
+ int (*mthd)(struct nvkm_object *, u32, void *, u32);
+ int (*ntfy)(struct nvkm_object *, u32, struct nvkm_event **);
+ int (* map)(struct nvkm_object *, u64 *, u32 *);
+ u8 (*rd08)(struct nvkm_object *, u64 offset);
+ u16 (*rd16)(struct nvkm_object *, u64 offset);
+ u32 (*rd32)(struct nvkm_object *, u64 offset);
+ void (*wr08)(struct nvkm_object *, u64 offset, u8 data);
+ void (*wr16)(struct nvkm_object *, u64 offset, u16 data);
+ void (*wr32)(struct nvkm_object *, u64 offset, u32 data);
};
-static inline struct nouveau_ofuncs *
+static inline struct nvkm_ofuncs *
nv_ofuncs(void *obj)
{
return nv_oclass(obj)->ofuncs;
}
-int nouveau_object_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nouveau_object_ref(struct nouveau_object *, struct nouveau_object **);
-int nouveau_object_inc(struct nouveau_object *);
-int nouveau_object_dec(struct nouveau_object *, bool suspend);
-
-void nouveau_object_debug(void);
+int nvkm_object_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void nvkm_object_ref(struct nvkm_object *, struct nvkm_object **);
+int nvkm_object_inc(struct nvkm_object *);
+int nvkm_object_dec(struct nvkm_object *, bool suspend);
+void nvkm_object_debug(void);
static inline int
nv_exec(void *obj, u32 mthd, void *data, u32 size)
{
- struct nouveau_omthds *method = nv_oclass(obj)->omthds;
+ struct nvkm_omthds *method = nv_oclass(obj)->omthds;
while (method && method->call) {
if (mthd >= method->start && mthd <= method->limit)
@@ -202,5 +200,4 @@ nv_memcmp(void *obj, u32 addr, const char *str, u32 len)
}
return 0;
}
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/option.h b/drivers/gpu/drm/nouveau/include/nvkm/core/option.h
index ed055847887e..532bfa8e3f72 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/option.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/option.h
@@ -1,12 +1,10 @@
-#ifndef __NOUVEAU_OPTION_H__
-#define __NOUVEAU_OPTION_H__
-
+#ifndef __NVKM_OPTION_H__
+#define __NVKM_OPTION_H__
#include <core/os.h>
-const char *nouveau_stropt(const char *optstr, const char *opt, int *len);
-bool nouveau_boolopt(const char *optstr, const char *opt, bool value);
-
-int nouveau_dbgopt(const char *optstr, const char *sub);
+const char *nvkm_stropt(const char *optstr, const char *opt, int *len);
+bool nvkm_boolopt(const char *optstr, const char *opt, bool value);
+int nvkm_dbgopt(const char *optstr, const char *sub);
/* compares unterminated string 'str' with zero-terminated string 'cmp' */
static inline int
@@ -16,5 +14,4 @@ strncasecmpz(const char *str, const char *cmp, size_t len)
return len;
return strncasecmp(str, cmp, len);
}
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index cd57e238ddd3..0b5a1e4dff48 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -1,4 +1,195 @@
#ifndef __NVKM_OS_H__
#define __NVKM_OS_H__
#include <nvif/os.h>
+
+#define nouveau_client nvkm_client
+#define nouveau_client_name nvkm_client_name
+#define nouveau_client_create nvkm_client_create
+#define nouveau_client_init nvkm_client_init
+#define nouveau_client_fini nvkm_client_fini
+#define nouveau_engctx nvkm_engctx
+#define nouveau_engctx_create nvkm_engctx_create
+#define nouveau_engctx_create_ nvkm_engctx_create_
+#define nouveau_engctx_destroy nvkm_engctx_destroy
+#define nouveau_engctx_init nvkm_engctx_init
+#define nouveau_engctx_fini nvkm_engctx_fini
+#define _nouveau_engctx_ctor _nvkm_engctx_ctor
+#define _nouveau_engctx_dtor _nvkm_engctx_dtor
+#define _nouveau_engctx_init _nvkm_engctx_init
+#define _nouveau_engctx_fini _nvkm_engctx_fini
+#define _nouveau_engctx_rd32 _nvkm_engctx_rd32
+#define _nouveau_engctx_wr32 _nvkm_engctx_wr32
+#define nouveau_engctx_get nvkm_engctx_get
+#define nouveau_engctx_put nvkm_engctx_put
+#define nouveau_engine nvkm_engine
+#define nouveau_engine_create nvkm_engine_create
+#define nouveau_engine_create_ nvkm_engine_create_
+#define nouveau_engine_destroy nvkm_engine_destroy
+#define nouveau_engine_init nvkm_engine_init
+#define nouveau_engine_fini nvkm_engine_fini
+#define _nouveau_engine_ctor _nvkm_engine_ctor
+#define _nouveau_engine_dtor _nvkm_engine_dtor
+#define _nouveau_engine_init _nvkm_engine_init
+#define _nouveau_engine_fini _nvkm_engine_fini
+#define nouveau_enum nvkm_enum
+#define nouveau_gpuobj nvkm_gpuobj
+#define nouveau_gpuobj_create nvkm_gpuobj_create
+#define nouveau_gpuobj_destroy nvkm_gpuobj_destroy
+#define _nouveau_gpuobj_ctor _nvkm_gpuobj_ctor
+#define _nouveau_gpuobj_dtor _nvkm_gpuobj_dtor
+#define _nouveau_gpuobj_init _nvkm_gpuobj_init
+#define _nouveau_gpuobj_fini _nvkm_gpuobj_fini
+#define _nouveau_gpuobj_rd32 _nvkm_gpuobj_rd32
+#define _nouveau_gpuobj_wr32 _nvkm_gpuobj_wr32
+#define nouveau_gpuobj_new nvkm_gpuobj_new
+#define nouveau_gpuobj_dup nvkm_gpuobj_dup
+#define nouveau_gpuobj_ref nvkm_gpuobj_ref
+#define nouveau_gpuobj_map nvkm_gpuobj_map
+#define nouveau_gpuobj_map_vm nvkm_gpuobj_map_vm
+#define nouveau_gpuobj_unmap nvkm_gpuobj_unmap
+#define nouveau_handle nvkm_handle
+#define nouveau_handle_ref nvkm_handle_ref
+#define nouveau_handle_put nvkm_handle_put
+#define nouveau_handle_get_class nvkm_handle_get_class
+#define nouveau_handle_get_vinst nvkm_handle_get_vinst
+#define nouveau_handle_get_cinst nvkm_handle_get_cinst
+#define nouveau_mm nvkm_mm
+#define nouveau_mm_node nvkm_mm_node
+#define nouveau_mm_init nvkm_mm_init
+#define nouveau_mm_fini nvkm_mm_fini
+#define nouveau_mm_head nvkm_mm_head
+#define nouveau_mm_tail nvkm_mm_tail
+#define nouveau_mm_free nvkm_mm_free
+#define nouveau_mm_initialised nvkm_mm_initialised
+#define nouveau_namedb nvkm_namedb
+#define nouveau_namedb_create nvkm_namedb_create
+#define nouveau_namedb_create_ nvkm_namedb_create_
+#define nouveau_namedb_destroy nvkm_namedb_destroy
+#define nouveau_namedb_init nvkm_namedb_init
+#define nouveau_namedb_fini nvkm_namedb_fini
+#define _nouveau_namedb_ctor _nvkm_namedb_ctor
+#define _nouveau_namedb_dtor _nvkm_namedb_dtor
+#define _nouveau_namedb_init _nvkm_namedb_init
+#define _nouveau_namedb_fini _nvkm_namedb_fini
+#define nouveau_namedb_ref nvkm_namedb_ref
+#define nouveau_namedb_put nvkm_namedb_put
+#define nouveau_namedb_get nvkm_namedb_get
+#define nouveau_namedb_get_class nvkm_namedb_get_class
+#define nouveau_namedb_get_vinst nvkm_namedb_get_vinst
+#define nouveau_namedb_get_cinst nvkm_namedb_get_cinst
+#define nouveau_object_debug nvkm_object_debug
+#define nouveau_object nvkm_object
+#define nouveau_object_create nvkm_object_create
+#define nouveau_object_create_ nvkm_object_create_
+#define nouveau_object_destroy nvkm_object_destroy
+#define nouveau_object_init nvkm_object_init
+#define nouveau_object_fini nvkm_object_fini
+#define _nouveau_object_ctor _nvkm_object_ctor
+#define nouveau_object_ctor nvkm_object_ctor
+#define nouveau_object_ref nvkm_object_ref
+#define nouveau_object_ofuncs nvkm_object_ofuncs
+#define nouveau_object_inc nvkm_object_inc
+#define nouveau_object_dec nvkm_object_dec
+#define nouveau_ofuncs nvkm_ofuncs
+#define nouveau_oclass nvkm_oclass
+#define nouveau_omthds nvkm_omthds
+#define nouveau_parent nvkm_parent
+#define nouveau_parent_create nvkm_parent_create
+#define nouveau_parent_create_ nvkm_parent_create_
+#define nouveau_parent_destroy nvkm_parent_destroy
+#define nouveau_parent_init nvkm_parent_init
+#define nouveau_parent_fini nvkm_parent_fini
+#define _nouveau_parent_ctor _nvkm_parent_ctor
+#define _nouveau_parent_dtor _nvkm_parent_dtor
+#define _nouveau_parent_init _nvkm_parent_init
+#define _nouveau_parent_fini _nvkm_parent_fini
+#define nouveau_printk nvkm_printk
+#define nouveau_ramht nvkm_ramht
+#define nouveau_ramht_new nvkm_ramht_new
+#define nouveau_ramht_ref nvkm_ramht_ref
+#define nouveau_ramht_insert nvkm_ramht_insert
+#define nouveau_ramht_remove nvkm_ramht_remove
+#define nouveau_subdev nvkm_subdev
+#define nouveau_subdev_create nvkm_subdev_create
+#define nouveau_subdev_create_ nvkm_subdev_create_
+#define nouveau_subdev_destroy nvkm_subdev_destroy
+#define nouveau_subdev_init nvkm_subdev_init
+#define nouveau_subdev_fini nvkm_subdev_fini
+#define _nouveau_subdev_ctor _nvkm_subdev_ctor
+#define _nouveau_subdev_dtor _nvkm_subdev_dtor
+#define _nouveau_subdev_init _nvkm_subdev_init
+#define _nouveau_subdev_fini _nvkm_subdev_fini
+#define nouveau_subdev_reset nvkm_subdev_reset
+#define nouveau_bitfield nvkm_bitfield
+#define nouveau_bitfield_print nvkm_bitfield_print
+#define nouveau_enum nvkm_enum
+#define nouveau_enum_find nvkm_enum_find
+#define nouveau_enum_print nvkm_enum_print
+#define nouveau_stropt nvkm_stropt
+#define nouveau_boolopt nvkm_boolopt
+#define nouveau_dbgopt nvkm_dbgopt
+#define nouveau_device nvkm_device
+#define nouveau_device_find nvkm_device_find
+#define nouveau_device_list nvkm_device_list
+#define nouveau_vma nvkm_vma
+#define nouveau_vm nvkm_vm
+#define nouveau_vm_get nvkm_vm_get
+#define nouveau_vm_put nvkm_vm_put
+#define nouveau_vm_map nvkm_vm_map
+#define nouveau_vm_unmap nvkm_vm_unmap
+#define nouveau_instmem nvkm_instmem
+#define nouveau_instobj nvkm_instobj
+#define nouveau_mem nvkm_mem
+#define nouveau_bar nvkm_bar
+#define nouveau_falcon nvkm_falcon
+#define nouveau_falcon_create nvkm_falcon_create
+#define nouveau_falcon_create_ nvkm_falcon_create_
+#define nouveau_falcon_destroy nvkm_falcon_destroy
+#define nouveau_falcon_init nvkm_falcon_init
+#define nouveau_falcon_fini nvkm_falcon_fini
+#define _nouveau_falcon_ctor _nvkm_falcon_ctor
+#define _nouveau_falcon_dtor _nvkm_falcon_dtor
+#define _nouveau_falcon_init _nvkm_falcon_init
+#define _nouveau_falcon_fini _nvkm_falcon_fini
+#define _nouveau_falcon_rd32 _nvkm_falcon_rd32
+#define _nouveau_falcon_wr32 _nvkm_falcon_wr32
+#define nouveau_falcon_context nvkm_falcon_context
+#define nouveau_falcon_context_create nvkm_falcon_context_create
+#define nouveau_falcon_context_create_ nvkm_falcon_context_create_
+#define nouveau_falcon_context_destroy nvkm_falcon_context_destroy
+#define nouveau_falcon_context_init nvkm_falcon_context_init
+#define nouveau_falcon_context_fini nvkm_falcon_context_fini
+#define _nouveau_falcon_context_ctor _nvkm_falcon_context_ctor
+#define _nouveau_falcon_context_dtor _nvkm_falcon_context_dtor
+#define _nouveau_falcon_context_init _nvkm_falcon_context_init
+#define _nouveau_falcon_context_fini _nvkm_falcon_context_fini
+#define _nouveau_falcon_context_rd32 _nvkm_falcon_context_rd32
+#define _nouveau_falcon_context_wr32 _nvkm_falcon_context_wr32
+#define nouveau_falcon_intr nvkm_falcon_intr
+#define nouveau_xtensa nvkm_xtensa
+#define nouveau_xtensa_create nvkm_xtensa_create
+#define nouveau_xtensa_create_ nvkm_xtensa_create_
+#define nouveau_xtensa_destroy nvkm_xtensa_destroy
+#define nouveau_xtensa_init nvkm_xtensa_init
+#define nouveau_xtensa_fini nvkm_xtensa_fini
+#define _nouveau_xtensa_ctor _nvkm_xtensa_ctor
+#define _nouveau_xtensa_dtor _nvkm_xtensa_dtor
+#define _nouveau_xtensa_init _nvkm_xtensa_init
+#define _nouveau_xtensa_fini _nvkm_xtensa_fini
+#define _nouveau_xtensa_rd32 _nvkm_xtensa_rd32
+#define _nouveau_xtensa_wr32 _nvkm_xtensa_wr32
+#define nouveau_xtensa_context nvkm_xtensa_context
+#define nouveau_xtensa_context_create nvkm_xtensa_context_create
+#define nouveau_xtensa_context_create_ nvkm_xtensa_context_create_
+#define nouveau_xtensa_context_destroy nvkm_xtensa_context_destroy
+#define nouveau_xtensa_context_init nvkm_xtensa_context_init
+#define nouveau_xtensa_context_fini nvkm_xtensa_context_fini
+#define _nouveau_xtensa_engctx_ctor _nvkm_xtensa_engctx_ctor
+#define _nouveau_xtensa_context_dtor _nvkm_xtensa_context_dtor
+#define _nouveau_xtensa_context_init _nvkm_xtensa_context_init
+#define _nouveau_xtensa_context_fini _nvkm_xtensa_context_fini
+#define _nouveau_xtensa_context_rd32 _nvkm_xtensa_context_rd32
+#define _nouveau_xtensa_context_wr32 _nvkm_xtensa_context_wr32
+#define nouveau_xtensa_intr nvkm_xtensa_intr
+
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/parent.h b/drivers/gpu/drm/nouveau/include/nvkm/core/parent.h
index 4e2345a5cfdb..837e4fe966a5 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/parent.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/parent.h
@@ -1,32 +1,29 @@
-#ifndef __NOUVEAU_PARENT_H__
-#define __NOUVEAU_PARENT_H__
-
-#include <core/device.h>
+#ifndef __NVKM_PARENT_H__
+#define __NVKM_PARENT_H__
#include <core/object.h>
-struct nouveau_sclass {
- struct nouveau_sclass *sclass;
- struct nouveau_engine *engine;
- struct nouveau_oclass *oclass;
+struct nvkm_sclass {
+ struct nvkm_sclass *sclass;
+ struct nvkm_engine *engine;
+ struct nvkm_oclass *oclass;
};
-struct nouveau_parent {
- struct nouveau_object object;
+struct nvkm_parent {
+ struct nvkm_object object;
- struct nouveau_sclass *sclass;
+ struct nvkm_sclass *sclass;
u64 engine;
- int (*context_attach)(struct nouveau_object *,
- struct nouveau_object *);
- int (*context_detach)(struct nouveau_object *, bool suspend,
- struct nouveau_object *);
+ int (*context_attach)(struct nvkm_object *, struct nvkm_object *);
+ int (*context_detach)(struct nvkm_object *, bool suspend,
+ struct nvkm_object *);
- int (*object_attach)(struct nouveau_object *parent,
- struct nouveau_object *object, u32 name);
- void (*object_detach)(struct nouveau_object *parent, int cookie);
+ int (*object_attach)(struct nvkm_object *parent,
+ struct nvkm_object *object, u32 name);
+ void (*object_detach)(struct nvkm_object *parent, int cookie);
};
-static inline struct nouveau_parent *
+static inline struct nvkm_parent *
nv_parent(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
@@ -36,27 +33,26 @@ nv_parent(void *obj)
return obj;
}
-#define nouveau_parent_create(p,e,c,v,s,m,d) \
- nouveau_parent_create_((p), (e), (c), (v), (s), (m), \
+#define nvkm_parent_create(p,e,c,v,s,m,d) \
+ nvkm_parent_create_((p), (e), (c), (v), (s), (m), \
sizeof(**d), (void **)d)
-#define nouveau_parent_init(p) \
- nouveau_object_init(&(p)->object)
-#define nouveau_parent_fini(p,s) \
- nouveau_object_fini(&(p)->object, (s))
+#define nvkm_parent_init(p) \
+ nvkm_object_init(&(p)->object)
+#define nvkm_parent_fini(p,s) \
+ nvkm_object_fini(&(p)->object, (s))
-int nouveau_parent_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, u32 pclass,
- struct nouveau_oclass *, u64 engcls,
+int nvkm_parent_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, u32 pclass,
+ struct nvkm_oclass *, u64 engcls,
int size, void **);
-void nouveau_parent_destroy(struct nouveau_parent *);
+void nvkm_parent_destroy(struct nvkm_parent *);
-void _nouveau_parent_dtor(struct nouveau_object *);
-#define _nouveau_parent_init nouveau_object_init
-#define _nouveau_parent_fini nouveau_object_fini
-
-int nouveau_parent_sclass(struct nouveau_object *, u16 handle,
- struct nouveau_object **pengine,
- struct nouveau_oclass **poclass);
-int nouveau_parent_lclass(struct nouveau_object *, u32 *, int);
+void _nvkm_parent_dtor(struct nvkm_object *);
+#define _nvkm_parent_init nvkm_object_init
+#define _nvkm_parent_fini nvkm_object_fini
+int nvkm_parent_sclass(struct nvkm_object *, u16 handle,
+ struct nvkm_object **pengine,
+ struct nvkm_oclass **poclass);
+int nvkm_parent_lclass(struct nvkm_object *, u32 *, int);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/printk.h b/drivers/gpu/drm/nouveau/include/nvkm/core/printk.h
index 451b6ed20b7e..83648177059f 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/printk.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/printk.h
@@ -1,13 +1,11 @@
-#ifndef __NOUVEAU_PRINTK_H__
-#define __NOUVEAU_PRINTK_H__
-
+#ifndef __NVKM_PRINTK_H__
+#define __NVKM_PRINTK_H__
#include <core/os.h>
#include <core/debug.h>
-
-struct nouveau_object;
+struct nvkm_object;
void __printf(3, 4)
-nv_printk_(struct nouveau_object *, int, const char *, ...);
+nv_printk_(struct nvkm_object *, int, const char *, ...);
#define nv_printk(o,l,f,a...) do { \
if (NV_DBG_##l <= CONFIG_NOUVEAU_DEBUG) \
@@ -21,12 +19,11 @@ nv_printk_(struct nouveau_object *, int, const char *, ...);
#define nv_debug(o,f,a...) nv_printk((o), DEBUG, f, ##a)
#define nv_trace(o,f,a...) nv_printk((o), TRACE, f, ##a)
#define nv_spam(o,f,a...) nv_printk((o), SPAM, f, ##a)
-#define nv_ioctl(o,f,a...) nv_trace(nouveau_client(o), "ioctl: "f, ##a)
+#define nv_ioctl(o,f,a...) nv_trace(nvkm_client(o), "ioctl: "f, ##a)
#define nv_assert(f,a...) do { \
if (NV_DBG_FATAL <= CONFIG_NOUVEAU_DEBUG) \
nv_printk_(NULL, NV_DBG_FATAL, f "\n", ##a); \
BUG_ON(1); \
} while(0)
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h b/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h
index e51014337ebe..cc132eaa10cc 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h
@@ -1,23 +1,20 @@
-#ifndef __NOUVEAU_RAMHT_H__
-#define __NOUVEAU_RAMHT_H__
-
+#ifndef __NVKM_RAMHT_H__
+#define __NVKM_RAMHT_H__
#include <core/gpuobj.h>
-struct nouveau_ramht {
- struct nouveau_gpuobj gpuobj;
+struct nvkm_ramht {
+ struct nvkm_gpuobj gpuobj;
int bits;
};
-int nouveau_ramht_insert(struct nouveau_ramht *, int chid,
- u32 handle, u32 context);
-void nouveau_ramht_remove(struct nouveau_ramht *, int cookie);
-int nouveau_ramht_new(struct nouveau_object *, struct nouveau_object *,
- u32 size, u32 align, struct nouveau_ramht **);
+int nvkm_ramht_insert(struct nvkm_ramht *, int chid, u32 handle, u32 context);
+void nvkm_ramht_remove(struct nvkm_ramht *, int cookie);
+int nvkm_ramht_new(struct nvkm_object *, struct nvkm_object *, u32 size,
+ u32 align, struct nvkm_ramht **);
static inline void
-nouveau_ramht_ref(struct nouveau_ramht *obj, struct nouveau_ramht **ref)
+nvkm_ramht_ref(struct nvkm_ramht *obj, struct nvkm_ramht **ref)
{
- nouveau_gpuobj_ref(&obj->gpuobj, (struct nouveau_gpuobj **)ref);
+ nvkm_gpuobj_ref(&obj->gpuobj, (struct nvkm_gpuobj **)ref);
}
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
index 152c842e1f66..6fdc39116aac 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
@@ -1,24 +1,23 @@
-#ifndef __NOUVEAU_SUBDEV_H__
-#define __NOUVEAU_SUBDEV_H__
-
+#ifndef __NVKM_SUBDEV_H__
+#define __NVKM_SUBDEV_H__
#include <core/object.h>
#include <core/devidx.h>
#define NV_SUBDEV_(sub,var) (NV_SUBDEV_CLASS | ((var) << 8) | (sub))
#define NV_SUBDEV(name,var) NV_SUBDEV_(NVDEV_SUBDEV_##name, (var))
-struct nouveau_subdev {
- struct nouveau_object object;
+struct nvkm_subdev {
+ struct nvkm_object object;
struct mutex mutex;
const char *name;
void __iomem *mmio;
u32 debug;
u32 unit;
- void (*intr)(struct nouveau_subdev *);
+ void (*intr)(struct nvkm_subdev *);
};
-static inline struct nouveau_subdev *
+static inline struct nvkm_subdev *
nv_subdev(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
@@ -29,29 +28,29 @@ nv_subdev(void *obj)
}
static inline int
-nv_subidx(struct nouveau_subdev *subdev)
+nv_subidx(struct nvkm_subdev *subdev)
{
return nv_hclass(subdev) & 0xff;
}
-struct nouveau_subdev *nouveau_subdev(void *obj, int idx);
+struct nvkm_subdev *nvkm_subdev(void *obj, int idx);
-#define nouveau_subdev_create(p,e,o,v,s,f,d) \
- nouveau_subdev_create_((p), (e), (o), (v), (s), (f), \
+#define nvkm_subdev_create(p,e,o,v,s,f,d) \
+ nvkm_subdev_create_((p), (e), (o), (v), (s), (f), \
sizeof(**d),(void **)d)
-int nouveau_subdev_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, u32 pclass,
+int nvkm_subdev_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, u32 pclass,
const char *sname, const char *fname,
int size, void **);
-void nouveau_subdev_destroy(struct nouveau_subdev *);
-int nouveau_subdev_init(struct nouveau_subdev *);
-int nouveau_subdev_fini(struct nouveau_subdev *, bool suspend);
-void nouveau_subdev_reset(struct nouveau_object *);
+void nvkm_subdev_destroy(struct nvkm_subdev *);
+int nvkm_subdev_init(struct nvkm_subdev *);
+int nvkm_subdev_fini(struct nvkm_subdev *, bool suspend);
+void nvkm_subdev_reset(struct nvkm_object *);
-void _nouveau_subdev_dtor(struct nouveau_object *);
-int _nouveau_subdev_init(struct nouveau_object *);
-int _nouveau_subdev_fini(struct nouveau_object *, bool suspend);
+void _nvkm_subdev_dtor(struct nvkm_object *);
+int _nvkm_subdev_init(struct nvkm_object *);
+int _nvkm_subdev_fini(struct nvkm_object *, bool suspend);
#define s_printk(s,l,f,a...) do { \
if ((s)->debug >= OS_DBG_##l) { \
@@ -62,7 +61,7 @@ int _nouveau_subdev_fini(struct nouveau_object *, bool suspend);
static inline u8
nv_rd08(void *obj, u32 addr)
{
- struct nouveau_subdev *subdev = nv_subdev(obj);
+ struct nvkm_subdev *subdev = nv_subdev(obj);
u8 data = ioread8(subdev->mmio + addr);
nv_spam(subdev, "nv_rd08 0x%06x 0x%02x\n", addr, data);
return data;
@@ -71,7 +70,7 @@ nv_rd08(void *obj, u32 addr)
static inline u16
nv_rd16(void *obj, u32 addr)
{
- struct nouveau_subdev *subdev = nv_subdev(obj);
+ struct nvkm_subdev *subdev = nv_subdev(obj);
u16 data = ioread16_native(subdev->mmio + addr);
nv_spam(subdev, "nv_rd16 0x%06x 0x%04x\n", addr, data);
return data;
@@ -80,7 +79,7 @@ nv_rd16(void *obj, u32 addr)
static inline u32
nv_rd32(void *obj, u32 addr)
{
- struct nouveau_subdev *subdev = nv_subdev(obj);
+ struct nvkm_subdev *subdev = nv_subdev(obj);
u32 data = ioread32_native(subdev->mmio + addr);
nv_spam(subdev, "nv_rd32 0x%06x 0x%08x\n", addr, data);
return data;
@@ -89,7 +88,7 @@ nv_rd32(void *obj, u32 addr)
static inline void
nv_wr08(void *obj, u32 addr, u8 data)
{
- struct nouveau_subdev *subdev = nv_subdev(obj);
+ struct nvkm_subdev *subdev = nv_subdev(obj);
nv_spam(subdev, "nv_wr08 0x%06x 0x%02x\n", addr, data);
iowrite8(data, subdev->mmio + addr);
}
@@ -97,7 +96,7 @@ nv_wr08(void *obj, u32 addr, u8 data)
static inline void
nv_wr16(void *obj, u32 addr, u16 data)
{
- struct nouveau_subdev *subdev = nv_subdev(obj);
+ struct nvkm_subdev *subdev = nv_subdev(obj);
nv_spam(subdev, "nv_wr16 0x%06x 0x%04x\n", addr, data);
iowrite16_native(data, subdev->mmio + addr);
}
@@ -105,7 +104,7 @@ nv_wr16(void *obj, u32 addr, u16 data)
static inline void
nv_wr32(void *obj, u32 addr, u32 data)
{
- struct nouveau_subdev *subdev = nv_subdev(obj);
+ struct nvkm_subdev *subdev = nv_subdev(obj);
nv_spam(subdev, "nv_wr32 0x%06x 0x%08x\n", addr, data);
iowrite32_native(data, subdev->mmio + addr);
}
@@ -117,5 +116,4 @@ nv_mask(void *obj, u32 addr, u32 mask, u32 data)
nv_wr32(obj, addr, (temp & ~mask) | data);
return temp;
}
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/device.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/device.h
index 672d3c8f4145..5d4805e67e76 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/device.h
@@ -27,7 +27,4 @@ int nv50_identify(struct nouveau_device *);
int nvc0_identify(struct nouveau_device *);
int nve0_identify(struct nouveau_device *);
int gm100_identify(struct nouveau_device *);
-
-struct nouveau_device *nouveau_device_find(u64 name);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
index 181aa7da524d..bd38cf9130fc 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
@@ -1,42 +1,41 @@
-#ifndef __NOUVEAU_FALCON_H__
-#define __NOUVEAU_FALCON_H__
-
-#include <core/engine.h>
+#ifndef __NVKM_FALCON_H__
+#define __NVKM_FALCON_H__
#include <core/engctx.h>
-#include <core/gpuobj.h>
-struct nouveau_falcon_chan {
- struct nouveau_engctx base;
+struct nvkm_falcon_chan {
+ struct nvkm_engctx base;
};
-#define nouveau_falcon_context_create(p,e,c,g,s,a,f,d) \
- nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
-#define nouveau_falcon_context_destroy(d) \
- nouveau_engctx_destroy(&(d)->base)
-#define nouveau_falcon_context_init(d) \
- nouveau_engctx_init(&(d)->base)
-#define nouveau_falcon_context_fini(d,s) \
- nouveau_engctx_fini(&(d)->base, (s))
+#define nvkm_falcon_context_create(p,e,c,g,s,a,f,d) \
+ nvkm_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
+#define nvkm_falcon_context_destroy(d) \
+ nvkm_engctx_destroy(&(d)->base)
+#define nvkm_falcon_context_init(d) \
+ nvkm_engctx_init(&(d)->base)
+#define nvkm_falcon_context_fini(d,s) \
+ nvkm_engctx_fini(&(d)->base, (s))
-#define _nouveau_falcon_context_ctor _nouveau_engctx_ctor
-#define _nouveau_falcon_context_dtor _nouveau_engctx_dtor
-#define _nouveau_falcon_context_init _nouveau_engctx_init
-#define _nouveau_falcon_context_fini _nouveau_engctx_fini
-#define _nouveau_falcon_context_rd32 _nouveau_engctx_rd32
-#define _nouveau_falcon_context_wr32 _nouveau_engctx_wr32
+#define _nvkm_falcon_context_ctor _nvkm_engctx_ctor
+#define _nvkm_falcon_context_dtor _nvkm_engctx_dtor
+#define _nvkm_falcon_context_init _nvkm_engctx_init
+#define _nvkm_falcon_context_fini _nvkm_engctx_fini
+#define _nvkm_falcon_context_rd32 _nvkm_engctx_rd32
+#define _nvkm_falcon_context_wr32 _nvkm_engctx_wr32
-struct nouveau_falcon_data {
+struct nvkm_falcon_data {
bool external;
};
-struct nouveau_falcon {
- struct nouveau_engine base;
+#include <core/engine.h>
+
+struct nvkm_falcon {
+ struct nvkm_engine base;
u32 addr;
u8 version;
u8 secret;
- struct nouveau_gpuobj *core;
+ struct nvkm_gpuobj *core;
bool external;
struct {
@@ -54,30 +53,29 @@ struct nouveau_falcon {
#define nv_falcon(priv) (&(priv)->base)
-#define nouveau_falcon_create(p,e,c,b,d,i,f,r) \
- nouveau_falcon_create_((p), (e), (c), (b), (d), (i), (f), \
+#define nvkm_falcon_create(p,e,c,b,d,i,f,r) \
+ nvkm_falcon_create_((p), (e), (c), (b), (d), (i), (f), \
sizeof(**r),(void **)r)
-#define nouveau_falcon_destroy(p) \
- nouveau_engine_destroy(&(p)->base)
-#define nouveau_falcon_init(p) ({ \
- struct nouveau_falcon *falcon = (p); \
- _nouveau_falcon_init(nv_object(falcon)); \
+#define nvkm_falcon_destroy(p) \
+ nvkm_engine_destroy(&(p)->base)
+#define nvkm_falcon_init(p) ({ \
+ struct nvkm_falcon *falcon = (p); \
+ _nvkm_falcon_init(nv_object(falcon)); \
})
-#define nouveau_falcon_fini(p,s) ({ \
- struct nouveau_falcon *falcon = (p); \
- _nouveau_falcon_fini(nv_object(falcon), (s)); \
+#define nvkm_falcon_fini(p,s) ({ \
+ struct nvkm_falcon *falcon = (p); \
+ _nvkm_falcon_fini(nv_object(falcon), (s)); \
})
-int nouveau_falcon_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, u32, bool, const char *,
+int nvkm_falcon_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, u32, bool, const char *,
const char *, int, void **);
-void nouveau_falcon_intr(struct nouveau_subdev *subdev);
-
-#define _nouveau_falcon_dtor _nouveau_engine_dtor
-int _nouveau_falcon_init(struct nouveau_object *);
-int _nouveau_falcon_fini(struct nouveau_object *, bool);
-u32 _nouveau_falcon_rd32(struct nouveau_object *, u64);
-void _nouveau_falcon_wr32(struct nouveau_object *, u64, u32);
+void nvkm_falcon_intr(struct nvkm_subdev *subdev);
+#define _nvkm_falcon_dtor _nvkm_engine_dtor
+int _nvkm_falcon_init(struct nvkm_object *);
+int _nvkm_falcon_fini(struct nvkm_object *, bool);
+u32 _nvkm_falcon_rd32(struct nvkm_object *, u64);
+void _nvkm_falcon_wr32(struct nvkm_object *, u64, u32);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h
index 306100f31f02..7a216cca2865 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h
@@ -1,38 +1,35 @@
-#ifndef __NOUVEAU_XTENSA_H__
-#define __NOUVEAU_XTENSA_H__
-
+#ifndef __NVKM_XTENSA_H__
+#define __NVKM_XTENSA_H__
#include <core/engine.h>
-#include <core/engctx.h>
-#include <core/gpuobj.h>
+struct nvkm_gpuobj;
-struct nouveau_xtensa {
- struct nouveau_engine base;
+struct nvkm_xtensa {
+ struct nvkm_engine base;
u32 addr;
- struct nouveau_gpuobj *gpu_fw;
+ struct nvkm_gpuobj *gpu_fw;
u32 fifo_val;
u32 unkd28;
};
-#define nouveau_xtensa_create(p,e,c,b,d,i,f,r) \
- nouveau_xtensa_create_((p), (e), (c), (b), (d), (i), (f), \
+#define nvkm_xtensa_create(p,e,c,b,d,i,f,r) \
+ nvkm_xtensa_create_((p), (e), (c), (b), (d), (i), (f), \
sizeof(**r),(void **)r)
-int _nouveau_xtensa_engctx_ctor(struct nouveau_object *,
- struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
+int _nvkm_xtensa_engctx_ctor(struct nvkm_object *,
+ struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
-void _nouveau_xtensa_intr(struct nouveau_subdev *);
-int nouveau_xtensa_create_(struct nouveau_object *,
- struct nouveau_object *,
- struct nouveau_oclass *, u32, bool,
+void _nvkm_xtensa_intr(struct nvkm_subdev *);
+int nvkm_xtensa_create_(struct nvkm_object *,
+ struct nvkm_object *,
+ struct nvkm_oclass *, u32, bool,
const char *, const char *,
int, void **);
-#define _nouveau_xtensa_dtor _nouveau_engine_dtor
-int _nouveau_xtensa_init(struct nouveau_object *);
-int _nouveau_xtensa_fini(struct nouveau_object *, bool);
-u32 _nouveau_xtensa_rd32(struct nouveau_object *, u64);
-void _nouveau_xtensa_wr32(struct nouveau_object *, u64, u32);
-
+#define _nvkm_xtensa_dtor _nvkm_engine_dtor
+int _nvkm_xtensa_init(struct nvkm_object *);
+int _nvkm_xtensa_fini(struct nvkm_object *, bool);
+u32 _nvkm_xtensa_rd32(struct nvkm_object *, u64);
+void _nvkm_xtensa_wr32(struct nvkm_object *, u64, u32);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
index 4524d4eea2f1..d42a08837d4f 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
@@ -2,6 +2,7 @@
#define __NOUVEAU_CLK_H__
#include <core/device.h>
+#include <core/notify.h>
#include <core/subdev.h>
struct nouveau_pll_vals;
diff --git a/drivers/gpu/drm/nouveau/nouveau_nvif.c b/drivers/gpu/drm/nouveau/nouveau_nvif.c
index 6544b84f0303..7f7bd329425e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_nvif.c
+++ b/drivers/gpu/drm/nouveau/nouveau_nvif.c
@@ -70,7 +70,7 @@ nvkm_client_suspend(void *priv)
}
static void
-nvkm_client_fini(void *priv)
+nvkm_client_driver_fini(void *priv)
{
struct nouveau_object *client = priv;
nouveau_client_fini(nv_client(client), false);
@@ -107,8 +107,8 @@ nvkm_client_ntfy(const void *header, u32 length, const void *data, u32 size)
}
static int
-nvkm_client_init(const char *name, u64 device, const char *cfg,
- const char *dbg, void **ppriv)
+nvkm_client_driver_init(const char *name, u64 device, const char *cfg,
+ const char *dbg, void **ppriv)
{
struct nouveau_client *client;
int ret;
@@ -125,8 +125,8 @@ nvkm_client_init(const char *name, u64 device, const char *cfg,
const struct nvif_driver
nvif_driver_nvkm = {
.name = "nvkm",
- .init = nvkm_client_init,
- .fini = nvkm_client_fini,
+ .init = nvkm_client_driver_init,
+ .fini = nvkm_client_driver_fini,
.suspend = nvkm_client_suspend,
.resume = nvkm_client_resume,
.ioctl = nvkm_client_ioctl,
diff --git a/drivers/gpu/drm/nouveau/nvif/notify.c b/drivers/gpu/drm/nouveau/nvif/notify.c
index 0898c3155292..8e34748709a0 100644
--- a/drivers/gpu/drm/nouveau/nvif/notify.c
+++ b/drivers/gpu/drm/nouveau/nvif/notify.c
@@ -92,7 +92,7 @@ nvif_notify_func(struct nvif_notify *notify, bool keep)
{
int ret = notify->func(notify);
if (ret == NVIF_NOTIFY_KEEP ||
- !test_and_clear_bit(NVKM_NOTIFY_USER, ¬ify->flags)) {
+ !test_and_clear_bit(NVIF_NOTIFY_USER, ¬ify->flags)) {
if (!keep)
atomic_dec(¬ify->putcnt);
else
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/client.c b/drivers/gpu/drm/nouveau/nvkm/core/client.c
index acff10387846..878a82f8f295 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/client.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/client.c
@@ -21,21 +21,18 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/object.h>
#include <core/client.h>
+#include <core/device.h>
#include <core/handle.h>
+#include <core/notify.h>
#include <core/option.h>
-#include <nvif/unpack.h>
+
#include <nvif/class.h>
-
-#include <nvif/unpack.h>
#include <nvif/event.h>
-
-#include <engine/device.h>
+#include <nvif/unpack.h>
struct nvkm_client_notify {
- struct nouveau_client *client;
+ struct nvkm_client *client;
struct nvkm_notify n;
u8 version;
u8 size;
@@ -48,12 +45,12 @@ static int
nvkm_client_notify(struct nvkm_notify *n)
{
struct nvkm_client_notify *notify = container_of(n, typeof(*notify), n);
- struct nouveau_client *client = notify->client;
+ struct nvkm_client *client = notify->client;
return client->ntfy(¬ify->rep, notify->size, n->data, n->size);
}
int
-nvkm_client_notify_put(struct nouveau_client *client, int index)
+nvkm_client_notify_put(struct nvkm_client *client, int index)
{
if (index < ARRAY_SIZE(client->notify)) {
if (client->notify[index]) {
@@ -65,7 +62,7 @@ nvkm_client_notify_put(struct nouveau_client *client, int index)
}
int
-nvkm_client_notify_get(struct nouveau_client *client, int index)
+nvkm_client_notify_get(struct nvkm_client *client, int index)
{
if (index < ARRAY_SIZE(client->notify)) {
if (client->notify[index]) {
@@ -77,7 +74,7 @@ nvkm_client_notify_get(struct nouveau_client *client, int index)
}
int
-nvkm_client_notify_del(struct nouveau_client *client, int index)
+nvkm_client_notify_del(struct nvkm_client *client, int index)
{
if (index < ARRAY_SIZE(client->notify)) {
if (client->notify[index]) {
@@ -91,10 +88,10 @@ nvkm_client_notify_del(struct nouveau_client *client, int index)
}
int
-nvkm_client_notify_new(struct nouveau_object *object,
+nvkm_client_notify_new(struct nvkm_object *object,
struct nvkm_event *event, void *data, u32 size)
{
- struct nouveau_client *client = nouveau_client(object);
+ struct nvkm_client *client = nvkm_client(object);
struct nvkm_client_notify *notify;
union {
struct nvif_notify_req_v0 v0;
@@ -142,7 +139,7 @@ nvkm_client_notify_new(struct nouveau_object *object,
}
static int
-nouveau_client_devlist(struct nouveau_object *object, void *data, u32 size)
+nvkm_client_mthd_devlist(struct nvkm_object *object, void *data, u32 size)
{
union {
struct nv_client_devlist_v0 v0;
@@ -154,8 +151,7 @@ nouveau_client_devlist(struct nouveau_object *object, void *data, u32 size)
nv_ioctl(object, "client devlist vers %d count %d\n",
args->v0.version, args->v0.count);
if (size == sizeof(args->v0.device[0]) * args->v0.count) {
- ret = nouveau_device_list(args->v0.device,
- args->v0.count);
+ ret = nvkm_device_list(args->v0.device, args->v0.count);
if (ret >= 0) {
args->v0.count = ret;
ret = 0;
@@ -169,12 +165,11 @@ nouveau_client_devlist(struct nouveau_object *object, void *data, u32 size)
}
static int
-nouveau_client_mthd(struct nouveau_object *object, u32 mthd,
- void *data, u32 size)
+nvkm_client_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
switch (mthd) {
case NV_CLIENT_DEVLIST:
- return nouveau_client_devlist(object, data, size);
+ return nvkm_client_mthd_devlist(object, data, size);
default:
break;
}
@@ -182,71 +177,71 @@ nouveau_client_mthd(struct nouveau_object *object, u32 mthd,
}
static void
-nouveau_client_dtor(struct nouveau_object *object)
+nvkm_client_dtor(struct nvkm_object *object)
{
- struct nouveau_client *client = (void *)object;
+ struct nvkm_client *client = (void *)object;
int i;
for (i = 0; i < ARRAY_SIZE(client->notify); i++)
nvkm_client_notify_del(client, i);
- nouveau_object_ref(NULL, &client->device);
- nouveau_handle_destroy(client->root);
- nouveau_namedb_destroy(&client->namedb);
+ nvkm_object_ref(NULL, &client->device);
+ nvkm_handle_destroy(client->root);
+ nvkm_namedb_destroy(&client->namedb);
}
-static struct nouveau_oclass
-nouveau_client_oclass = {
- .ofuncs = &(struct nouveau_ofuncs) {
- .dtor = nouveau_client_dtor,
- .mthd = nouveau_client_mthd,
+static struct nvkm_oclass
+nvkm_client_oclass = {
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .dtor = nvkm_client_dtor,
+ .mthd = nvkm_client_mthd,
},
};
int
-nouveau_client_create_(const char *name, u64 devname, const char *cfg,
- const char *dbg, int length, void **pobject)
+nvkm_client_create_(const char *name, u64 devname, const char *cfg,
+ const char *dbg, int length, void **pobject)
{
- struct nouveau_object *device;
- struct nouveau_client *client;
+ struct nvkm_object *device;
+ struct nvkm_client *client;
int ret;
- device = (void *)nouveau_device_find(devname);
+ device = (void *)nvkm_device_find(devname);
if (!device)
return -ENODEV;
- ret = nouveau_namedb_create_(NULL, NULL, &nouveau_client_oclass,
- NV_CLIENT_CLASS, NULL,
- (1ULL << NVDEV_ENGINE_DEVICE),
- length, pobject);
+ ret = nvkm_namedb_create_(NULL, NULL, &nvkm_client_oclass,
+ NV_CLIENT_CLASS, NULL,
+ (1ULL << NVDEV_ENGINE_DEVICE),
+ length, pobject);
client = *pobject;
if (ret)
return ret;
- ret = nouveau_handle_create(nv_object(client), ~0, ~0,
- nv_object(client), &client->root);
+ ret = nvkm_handle_create(nv_object(client), ~0, ~0, nv_object(client),
+ &client->root);
if (ret)
return ret;
/* prevent init/fini being called, os in in charge of this */
atomic_set(&nv_object(client)->usecount, 2);
- nouveau_object_ref(device, &client->device);
+ nvkm_object_ref(device, &client->device);
snprintf(client->name, sizeof(client->name), "%s", name);
- client->debug = nouveau_dbgopt(dbg, "CLIENT");
+ client->debug = nvkm_dbgopt(dbg, "CLIENT");
return 0;
}
int
-nouveau_client_init(struct nouveau_client *client)
+nvkm_client_init(struct nvkm_client *client)
{
int ret;
nv_debug(client, "init running\n");
- ret = nouveau_handle_init(client->root);
+ ret = nvkm_handle_init(client->root);
nv_debug(client, "init completed with %d\n", ret);
return ret;
}
int
-nouveau_client_fini(struct nouveau_client *client, bool suspend)
+nvkm_client_fini(struct nvkm_client *client, bool suspend)
{
const char *name[2] = { "fini", "suspend" };
int ret, i;
@@ -255,16 +250,16 @@ nouveau_client_fini(struct nouveau_client *client, bool suspend)
for (i = 0; i < ARRAY_SIZE(client->notify); i++)
nvkm_client_notify_put(client, i);
nv_debug(client, "%s object\n", name[suspend]);
- ret = nouveau_handle_fini(client->root, suspend);
+ ret = nvkm_handle_fini(client->root, suspend);
nv_debug(client, "%s completed with %d\n", name[suspend], ret);
return ret;
}
const char *
-nouveau_client_name(void *obj)
+nvkm_client_name(void *obj)
{
const char *client_name = "unknown";
- struct nouveau_client *client = nouveau_client(obj);
+ struct nvkm_client *client = nvkm_client(obj);
if (client)
client_name = client->name;
return client_name;
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
index 892baa461575..a9df07a90f9b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
@@ -21,21 +21,15 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/object.h>
-#include <core/namedb.h>
-#include <core/handle.h>
-#include <core/client.h>
#include <core/engctx.h>
-
-#include <subdev/mmu.h>
+#include <core/client.h>
static inline int
-nouveau_engctx_exists(struct nouveau_object *parent,
- struct nouveau_engine *engine, void **pobject)
+nvkm_engctx_exists(struct nvkm_object *parent,
+ struct nvkm_engine *engine, void **pobject)
{
- struct nouveau_engctx *engctx;
- struct nouveau_object *parctx;
+ struct nvkm_engctx *engctx;
+ struct nvkm_object *parctx;
list_for_each_entry(engctx, &engine->contexts, head) {
parctx = nv_pclass(nv_object(engctx), NV_PARENT_CLASS);
@@ -50,16 +44,13 @@ nouveau_engctx_exists(struct nouveau_object *parent,
}
int
-nouveau_engctx_create_(struct nouveau_object *parent,
- struct nouveau_object *engobj,
- struct nouveau_oclass *oclass,
- struct nouveau_object *pargpu,
- u32 size, u32 align, u32 flags,
- int length, void **pobject)
+nvkm_engctx_create_(struct nvkm_object *parent, struct nvkm_object *engobj,
+ struct nvkm_oclass *oclass, struct nvkm_object *pargpu,
+ u32 size, u32 align, u32 flags, int length, void **pobject)
{
- struct nouveau_client *client = nouveau_client(parent);
- struct nouveau_engine *engine = nv_engine(engobj);
- struct nouveau_object *engctx;
+ struct nvkm_client *client = nvkm_client(parent);
+ struct nvkm_engine *engine = nv_engine(engobj);
+ struct nvkm_object *engctx;
unsigned long save;
int ret;
@@ -67,7 +58,7 @@ nouveau_engctx_create_(struct nouveau_object *parent,
* and reference it instead of creating a new one
*/
spin_lock_irqsave(&engine->lock, save);
- ret = nouveau_engctx_exists(parent, engine, pobject);
+ ret = nvkm_engctx_exists(parent, engine, pobject);
spin_unlock_irqrestore(&engine->lock, save);
if (ret)
return ret;
@@ -76,13 +67,12 @@ nouveau_engctx_create_(struct nouveau_object *parent,
* objects backed by instance memory
*/
if (size) {
- ret = nouveau_gpuobj_create_(parent, engobj, oclass,
- NV_ENGCTX_CLASS,
- pargpu, size, align, flags,
- length, pobject);
+ ret = nvkm_gpuobj_create_(parent, engobj, oclass,
+ NV_ENGCTX_CLASS, pargpu, size,
+ align, flags, length, pobject);
} else {
- ret = nouveau_object_create_(parent, engobj, oclass,
- NV_ENGCTX_CLASS, length, pobject);
+ ret = nvkm_object_create_(parent, engobj, oclass,
+ NV_ENGCTX_CLASS, length, pobject);
}
engctx = *pobject;
@@ -94,10 +84,10 @@ nouveau_engctx_create_(struct nouveau_object *parent,
* it's not possible to allocate the object with it held.
*/
spin_lock_irqsave(&engine->lock, save);
- ret = nouveau_engctx_exists(parent, engine, pobject);
+ ret = nvkm_engctx_exists(parent, engine, pobject);
if (ret) {
spin_unlock_irqrestore(&engine->lock, save);
- nouveau_object_ref(NULL, &engctx);
+ nvkm_object_ref(NULL, &engctx);
return ret;
}
@@ -110,13 +100,13 @@ nouveau_engctx_create_(struct nouveau_object *parent,
}
void
-nouveau_engctx_destroy(struct nouveau_engctx *engctx)
+nvkm_engctx_destroy(struct nvkm_engctx *engctx)
{
- struct nouveau_engine *engine = engctx->gpuobj.object.engine;
- struct nouveau_client *client = nouveau_client(engctx);
+ struct nvkm_engine *engine = engctx->gpuobj.object.engine;
+ struct nvkm_client *client = nvkm_client(engctx);
unsigned long save;
- nouveau_gpuobj_unmap(&engctx->vma);
+ nvkm_gpuobj_unmap(&engctx->vma);
spin_lock_irqsave(&engine->lock, save);
list_del(&engctx->head);
spin_unlock_irqrestore(&engine->lock, save);
@@ -125,21 +115,21 @@ nouveau_engctx_destroy(struct nouveau_engctx *engctx)
atomic_dec(&client->vm->engref[nv_engidx(engine)]);
if (engctx->gpuobj.size)
- nouveau_gpuobj_destroy(&engctx->gpuobj);
+ nvkm_gpuobj_destroy(&engctx->gpuobj);
else
- nouveau_object_destroy(&engctx->gpuobj.object);
+ nvkm_object_destroy(&engctx->gpuobj.object);
}
int
-nouveau_engctx_init(struct nouveau_engctx *engctx)
+nvkm_engctx_init(struct nvkm_engctx *engctx)
{
- struct nouveau_object *object = nv_object(engctx);
- struct nouveau_subdev *subdev = nv_subdev(object->engine);
- struct nouveau_object *parent;
- struct nouveau_subdev *pardev;
+ struct nvkm_object *object = nv_object(engctx);
+ struct nvkm_subdev *subdev = nv_subdev(object->engine);
+ struct nvkm_object *parent;
+ struct nvkm_subdev *pardev;
int ret;
- ret = nouveau_gpuobj_init(&engctx->gpuobj);
+ ret = nvkm_gpuobj_init(&engctx->gpuobj);
if (ret)
return ret;
@@ -162,12 +152,12 @@ nouveau_engctx_init(struct nouveau_engctx *engctx)
}
int
-nouveau_engctx_fini(struct nouveau_engctx *engctx, bool suspend)
+nvkm_engctx_fini(struct nvkm_engctx *engctx, bool suspend)
{
- struct nouveau_object *object = nv_object(engctx);
- struct nouveau_subdev *subdev = nv_subdev(object->engine);
- struct nouveau_object *parent;
- struct nouveau_subdev *pardev;
+ struct nvkm_object *object = nv_object(engctx);
+ struct nvkm_subdev *subdev = nv_subdev(object->engine);
+ struct nvkm_object *parent;
+ struct nvkm_subdev *pardev;
int ret = 0;
parent = nv_pclass(object->parent, NV_PARENT_CLASS);
@@ -185,47 +175,45 @@ nouveau_engctx_fini(struct nouveau_engctx *engctx, bool suspend)
}
nv_debug(parent, "detached %s context\n", subdev->name);
- return nouveau_gpuobj_fini(&engctx->gpuobj, suspend);
+ return nvkm_gpuobj_fini(&engctx->gpuobj, suspend);
}
int
-_nouveau_engctx_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+_nvkm_engctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_engctx *engctx;
+ struct nvkm_engctx *engctx;
int ret;
- ret = nouveau_engctx_create(parent, engine, oclass, NULL, 256, 256,
- NVOBJ_FLAG_ZERO_ALLOC, &engctx);
+ ret = nvkm_engctx_create(parent, engine, oclass, NULL, 256, 256,
+ NVOBJ_FLAG_ZERO_ALLOC, &engctx);
*pobject = nv_object(engctx);
return ret;
}
void
-_nouveau_engctx_dtor(struct nouveau_object *object)
+_nvkm_engctx_dtor(struct nvkm_object *object)
{
- nouveau_engctx_destroy(nv_engctx(object));
+ nvkm_engctx_destroy(nv_engctx(object));
}
int
-_nouveau_engctx_init(struct nouveau_object *object)
+_nvkm_engctx_init(struct nvkm_object *object)
{
- return nouveau_engctx_init(nv_engctx(object));
+ return nvkm_engctx_init(nv_engctx(object));
}
-
int
-_nouveau_engctx_fini(struct nouveau_object *object, bool suspend)
+_nvkm_engctx_fini(struct nvkm_object *object, bool suspend)
{
- return nouveau_engctx_fini(nv_engctx(object), suspend);
+ return nvkm_engctx_fini(nv_engctx(object), suspend);
}
-struct nouveau_object *
-nouveau_engctx_get(struct nouveau_engine *engine, u64 addr)
+struct nvkm_object *
+nvkm_engctx_get(struct nvkm_engine *engine, u64 addr)
{
- struct nouveau_engctx *engctx;
+ struct nvkm_engctx *engctx;
unsigned long flags;
spin_lock_irqsave(&engine->lock, flags);
@@ -240,11 +228,11 @@ nouveau_engctx_get(struct nouveau_engine *engine, u64 addr)
}
void
-nouveau_engctx_put(struct nouveau_object *object)
+nvkm_engctx_put(struct nvkm_object *object)
{
if (object) {
- struct nouveau_engine *engine = nv_engine(object->engine);
- struct nouveau_engctx *engctx = nv_engctx(object);
+ struct nvkm_engine *engine = nv_engine(object->engine);
+ struct nvkm_engctx *engctx = nv_engctx(object);
spin_unlock_irqrestore(&engine->lock, engctx->save);
}
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engine.c b/drivers/gpu/drm/nouveau/nvkm/core/engine.c
index c9414b1532ff..60820173c6aa 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/engine.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/engine.c
@@ -21,42 +21,40 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/device.h>
#include <core/engine.h>
+#include <core/device.h>
#include <core/option.h>
-struct nouveau_engine *
-nouveau_engine(void *obj, int idx)
+struct nvkm_engine *
+nvkm_engine(void *obj, int idx)
{
- obj = nouveau_subdev(obj, idx);
+ obj = nvkm_subdev(obj, idx);
if (obj && nv_iclass(obj, NV_ENGINE_CLASS))
return nv_engine(obj);
return NULL;
}
int
-nouveau_engine_create_(struct nouveau_object *parent,
- struct nouveau_object *engobj,
- struct nouveau_oclass *oclass, bool enable,
- const char *iname, const char *fname,
- int length, void **pobject)
+nvkm_engine_create_(struct nvkm_object *parent, struct nvkm_object *engobj,
+ struct nvkm_oclass *oclass, bool enable,
+ const char *iname, const char *fname,
+ int length, void **pobject)
{
- struct nouveau_engine *engine;
+ struct nvkm_engine *engine;
int ret;
- ret = nouveau_subdev_create_(parent, engobj, oclass, NV_ENGINE_CLASS,
- iname, fname, length, pobject);
+ ret = nvkm_subdev_create_(parent, engobj, oclass, NV_ENGINE_CLASS,
+ iname, fname, length, pobject);
engine = *pobject;
if (ret)
return ret;
if (parent) {
- struct nouveau_device *device = nv_device(parent);
+ struct nvkm_device *device = nv_device(parent);
int engidx = nv_engidx(engine);
if (device->disable_mask & (1ULL << engidx)) {
- if (!nouveau_boolopt(device->cfgopt, iname, false)) {
+ if (!nvkm_boolopt(device->cfgopt, iname, false)) {
nv_debug(engine, "engine disabled by hw/fw\n");
return -ENODEV;
}
@@ -64,7 +62,7 @@ nouveau_engine_create_(struct nouveau_object *parent,
nv_warn(engine, "ignoring hw/fw engine disable\n");
}
- if (!nouveau_boolopt(device->cfgopt, iname, enable)) {
+ if (!nvkm_boolopt(device->cfgopt, iname, enable)) {
if (!enable)
nv_warn(engine, "disabled, %s=1 to enable\n", iname);
return -ENODEV;
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/enum.c b/drivers/gpu/drm/nouveau/nvkm/core/enum.c
index dd434790ccc4..4f92bfc13d6b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/enum.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/enum.c
@@ -24,12 +24,10 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
-#include <core/os.h>
#include <core/enum.h>
-const struct nouveau_enum *
-nouveau_enum_find(const struct nouveau_enum *en, u32 value)
+const struct nvkm_enum *
+nvkm_enum_find(const struct nvkm_enum *en, u32 value)
{
while (en->name) {
if (en->value == value)
@@ -40,10 +38,10 @@ nouveau_enum_find(const struct nouveau_enum *en, u32 value)
return NULL;
}
-const struct nouveau_enum *
-nouveau_enum_print(const struct nouveau_enum *en, u32 value)
+const struct nvkm_enum *
+nvkm_enum_print(const struct nvkm_enum *en, u32 value)
{
- en = nouveau_enum_find(en, value);
+ en = nvkm_enum_find(en, value);
if (en)
pr_cont("%s", en->name);
else
@@ -52,7 +50,7 @@ nouveau_enum_print(const struct nouveau_enum *en, u32 value)
}
void
-nouveau_bitfield_print(const struct nouveau_bitfield *bf, u32 value)
+nvkm_bitfield_print(const struct nvkm_bitfield *bf, u32 value)
{
while (bf->name) {
if (value & bf->mask) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/event.c b/drivers/gpu/drm/nouveau/nvkm/core/event.c
index 760947e380c9..4e8d3fa042df 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/event.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/event.c
@@ -19,9 +19,8 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
-
-#include <core/object.h>
#include <core/event.h>
+#include <core/notify.h>
void
nvkm_event_put(struct nvkm_event *event, u32 types, int index)
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
index 68a4232d35cc..0c5cb55fc617 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
@@ -21,8 +21,6 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/object.h>
#include <core/gpuobj.h>
#include <subdev/instmem.h>
@@ -30,7 +28,7 @@
#include <subdev/mmu.h>
void
-nouveau_gpuobj_destroy(struct nouveau_gpuobj *gpuobj)
+nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj)
{
int i;
@@ -39,29 +37,25 @@ nouveau_gpuobj_destroy(struct nouveau_gpuobj *gpuobj)
nv_wo32(gpuobj, i, 0x00000000);
}
- if (gpuobj->node) {
- nouveau_mm_free(&nv_gpuobj(gpuobj->parent)->heap,
- &gpuobj->node);
- }
+ if (gpuobj->node)
+ nvkm_mm_free(&nv_gpuobj(gpuobj->parent)->heap, &gpuobj->node);
if (gpuobj->heap.block_size)
- nouveau_mm_fini(&gpuobj->heap);
+ nvkm_mm_fini(&gpuobj->heap);
- nouveau_object_destroy(&gpuobj->object);
+ nvkm_object_destroy(&gpuobj->object);
}
int
-nouveau_gpuobj_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, u32 pclass,
- struct nouveau_object *pargpu,
- u32 size, u32 align, u32 flags,
- int length, void **pobject)
+nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, u32 pclass,
+ struct nvkm_object *pargpu, u32 size, u32 align, u32 flags,
+ int length, void **pobject)
{
- struct nouveau_instmem *imem = nouveau_instmem(parent);
- struct nouveau_bar *bar = nouveau_bar(parent);
- struct nouveau_gpuobj *gpuobj;
- struct nouveau_mm *heap = NULL;
+ struct nvkm_instmem *imem = nvkm_instmem(parent);
+ struct nvkm_bar *bar = nvkm_bar(parent);
+ struct nvkm_gpuobj *gpuobj;
+ struct nvkm_mm *heap = NULL;
int ret, i;
u64 addr;
@@ -92,19 +86,19 @@ nouveau_gpuobj_create_(struct nouveau_object *parent,
size = nv_memobj(pargpu)->size;
if (bar && bar->alloc) {
- struct nouveau_instobj *iobj = (void *)parent;
- struct nouveau_mem **mem = (void *)(iobj + 1);
- struct nouveau_mem *node = *mem;
+ struct nvkm_instobj *iobj = (void *)parent;
+ struct nvkm_mem **mem = (void *)(iobj + 1);
+ struct nvkm_mem *node = *mem;
if (!bar->alloc(bar, parent, node, &pargpu)) {
- nouveau_object_ref(NULL, &parent);
+ nvkm_object_ref(NULL, &parent);
parent = pargpu;
}
}
}
- ret = nouveau_object_create_(parent, engine, oclass, pclass |
- NV_GPUOBJ_CLASS, length, pobject);
- nouveau_object_ref(NULL, &parent);
+ ret = nvkm_object_create_(parent, engine, oclass, pclass |
+ NV_GPUOBJ_CLASS, length, pobject);
+ nvkm_object_ref(NULL, &parent);
gpuobj = *pobject;
if (ret)
return ret;
@@ -115,8 +109,8 @@ nouveau_gpuobj_create_(struct nouveau_object *parent,
gpuobj->size = size;
if (heap) {
- ret = nouveau_mm_head(heap, 0, 1, size, size,
- max(align, (u32)1), &gpuobj->node);
+ ret = nvkm_mm_head(heap, 0, 1, size, size, max(align, (u32)1),
+ &gpuobj->node);
if (ret)
return ret;
@@ -124,7 +118,7 @@ nouveau_gpuobj_create_(struct nouveau_object *parent,
}
if (gpuobj->flags & NVOBJ_FLAG_HEAP) {
- ret = nouveau_mm_init(&gpuobj->heap, 0, gpuobj->size, 1);
+ ret = nvkm_mm_init(&gpuobj->heap, 0, gpuobj->size, 1);
if (ret)
return ret;
}
@@ -137,26 +131,25 @@ nouveau_gpuobj_create_(struct nouveau_object *parent,
return ret;
}
-struct nouveau_gpuobj_class {
- struct nouveau_object *pargpu;
+struct nvkm_gpuobj_class {
+ struct nvkm_object *pargpu;
u64 size;
u32 align;
u32 flags;
};
static int
-_nouveau_gpuobj_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+_nvkm_gpuobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_gpuobj_class *args = data;
- struct nouveau_gpuobj *object;
+ struct nvkm_gpuobj_class *args = data;
+ struct nvkm_gpuobj *object;
int ret;
- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, args->pargpu,
- args->size, args->align, args->flags,
- &object);
+ ret = nvkm_gpuobj_create(parent, engine, oclass, 0, args->pargpu,
+ args->size, args->align, args->flags,
+ &object);
*pobject = nv_object(object);
if (ret)
return ret;
@@ -165,63 +158,63 @@ _nouveau_gpuobj_ctor(struct nouveau_object *parent,
}
void
-_nouveau_gpuobj_dtor(struct nouveau_object *object)
+_nvkm_gpuobj_dtor(struct nvkm_object *object)
{
- nouveau_gpuobj_destroy(nv_gpuobj(object));
+ nvkm_gpuobj_destroy(nv_gpuobj(object));
}
int
-_nouveau_gpuobj_init(struct nouveau_object *object)
+_nvkm_gpuobj_init(struct nvkm_object *object)
{
- return nouveau_gpuobj_init(nv_gpuobj(object));
+ return nvkm_gpuobj_init(nv_gpuobj(object));
}
int
-_nouveau_gpuobj_fini(struct nouveau_object *object, bool suspend)
+_nvkm_gpuobj_fini(struct nvkm_object *object, bool suspend)
{
- return nouveau_gpuobj_fini(nv_gpuobj(object), suspend);
+ return nvkm_gpuobj_fini(nv_gpuobj(object), suspend);
}
u32
-_nouveau_gpuobj_rd32(struct nouveau_object *object, u64 addr)
+_nvkm_gpuobj_rd32(struct nvkm_object *object, u64 addr)
{
- struct nouveau_gpuobj *gpuobj = nv_gpuobj(object);
- struct nouveau_ofuncs *pfuncs = nv_ofuncs(gpuobj->parent);
+ struct nvkm_gpuobj *gpuobj = nv_gpuobj(object);
+ struct nvkm_ofuncs *pfuncs = nv_ofuncs(gpuobj->parent);
if (gpuobj->node)
addr += gpuobj->node->offset;
return pfuncs->rd32(gpuobj->parent, addr);
}
void
-_nouveau_gpuobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
+_nvkm_gpuobj_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
- struct nouveau_gpuobj *gpuobj = nv_gpuobj(object);
- struct nouveau_ofuncs *pfuncs = nv_ofuncs(gpuobj->parent);
+ struct nvkm_gpuobj *gpuobj = nv_gpuobj(object);
+ struct nvkm_ofuncs *pfuncs = nv_ofuncs(gpuobj->parent);
if (gpuobj->node)
addr += gpuobj->node->offset;
pfuncs->wr32(gpuobj->parent, addr, data);
}
-static struct nouveau_oclass
-_nouveau_gpuobj_oclass = {
+static struct nvkm_oclass
+_nvkm_gpuobj_oclass = {
.handle = 0x00000000,
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_gpuobj_ctor,
- .dtor = _nouveau_gpuobj_dtor,
- .init = _nouveau_gpuobj_init,
- .fini = _nouveau_gpuobj_fini,
- .rd32 = _nouveau_gpuobj_rd32,
- .wr32 = _nouveau_gpuobj_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_gpuobj_ctor,
+ .dtor = _nvkm_gpuobj_dtor,
+ .init = _nvkm_gpuobj_init,
+ .fini = _nvkm_gpuobj_fini,
+ .rd32 = _nvkm_gpuobj_rd32,
+ .wr32 = _nvkm_gpuobj_wr32,
},
};
int
-nouveau_gpuobj_new(struct nouveau_object *parent, struct nouveau_object *pargpu,
- u32 size, u32 align, u32 flags,
- struct nouveau_gpuobj **pgpuobj)
+nvkm_gpuobj_new(struct nvkm_object *parent, struct nvkm_object *pargpu,
+ u32 size, u32 align, u32 flags,
+ struct nvkm_gpuobj **pgpuobj)
{
- struct nouveau_object *engine = parent;
- struct nouveau_gpuobj_class args = {
+ struct nvkm_object *engine = parent;
+ struct nvkm_gpuobj_class args = {
.pargpu = pargpu,
.size = size,
.align = align,
@@ -232,22 +225,21 @@ nouveau_gpuobj_new(struct nouveau_object *parent, struct nouveau_object *pargpu,
engine = &engine->engine->subdev.object;
BUG_ON(engine == NULL);
- return nouveau_object_ctor(parent, engine, &_nouveau_gpuobj_oclass,
- &args, sizeof(args),
- (struct nouveau_object **)pgpuobj);
+ return nvkm_object_ctor(parent, engine, &_nvkm_gpuobj_oclass,
+ &args, sizeof(args),
+ (struct nvkm_object **)pgpuobj);
}
int
-nouveau_gpuobj_map(struct nouveau_gpuobj *gpuobj, u32 access,
- struct nouveau_vma *vma)
+nvkm_gpuobj_map(struct nvkm_gpuobj *gpuobj, u32 access, struct nvkm_vma *vma)
{
- struct nouveau_bar *bar = nouveau_bar(gpuobj);
+ struct nvkm_bar *bar = nvkm_bar(gpuobj);
int ret = -EINVAL;
if (bar && bar->umap) {
- struct nouveau_instobj *iobj = (void *)
+ struct nvkm_instobj *iobj = (void *)
nv_pclass(nv_object(gpuobj), NV_MEMOBJ_CLASS);
- struct nouveau_mem **mem = (void *)(iobj + 1);
+ struct nvkm_mem **mem = (void *)(iobj + 1);
ret = bar->umap(bar, *mem, access, vma);
}
@@ -255,28 +247,28 @@ nouveau_gpuobj_map(struct nouveau_gpuobj *gpuobj, u32 access,
}
int
-nouveau_gpuobj_map_vm(struct nouveau_gpuobj *gpuobj, struct nouveau_vm *vm,
- u32 access, struct nouveau_vma *vma)
+nvkm_gpuobj_map_vm(struct nvkm_gpuobj *gpuobj, struct nvkm_vm *vm,
+ u32 access, struct nvkm_vma *vma)
{
- struct nouveau_instobj *iobj = (void *)
+ struct nvkm_instobj *iobj = (void *)
nv_pclass(nv_object(gpuobj), NV_MEMOBJ_CLASS);
- struct nouveau_mem **mem = (void *)(iobj + 1);
+ struct nvkm_mem **mem = (void *)(iobj + 1);
int ret;
- ret = nouveau_vm_get(vm, gpuobj->size, 12, access, vma);
+ ret = nvkm_vm_get(vm, gpuobj->size, 12, access, vma);
if (ret)
return ret;
- nouveau_vm_map(vma, *mem);
+ nvkm_vm_map(vma, *mem);
return 0;
}
void
-nouveau_gpuobj_unmap(struct nouveau_vma *vma)
+nvkm_gpuobj_unmap(struct nvkm_vma *vma)
{
if (vma->node) {
- nouveau_vm_unmap(vma);
- nouveau_vm_put(vma);
+ nvkm_vm_unmap(vma);
+ nvkm_vm_put(vma);
}
}
@@ -286,37 +278,37 @@ nouveau_gpuobj_unmap(struct nouveau_vma *vma)
*/
static void
-nouveau_gpudup_dtor(struct nouveau_object *object)
+nvkm_gpudup_dtor(struct nvkm_object *object)
{
- struct nouveau_gpuobj *gpuobj = (void *)object;
- nouveau_object_ref(NULL, &gpuobj->parent);
- nouveau_object_destroy(&gpuobj->object);
+ struct nvkm_gpuobj *gpuobj = (void *)object;
+ nvkm_object_ref(NULL, &gpuobj->parent);
+ nvkm_object_destroy(&gpuobj->object);
}
-static struct nouveau_oclass
-nouveau_gpudup_oclass = {
+static struct nvkm_oclass
+nvkm_gpudup_oclass = {
.handle = NV_GPUOBJ_CLASS,
- .ofuncs = &(struct nouveau_ofuncs) {
- .dtor = nouveau_gpudup_dtor,
- .init = nouveau_object_init,
- .fini = nouveau_object_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .dtor = nvkm_gpudup_dtor,
+ .init = nvkm_object_init,
+ .fini = nvkm_object_fini,
},
};
int
-nouveau_gpuobj_dup(struct nouveau_object *parent, struct nouveau_gpuobj *base,
- struct nouveau_gpuobj **pgpuobj)
+nvkm_gpuobj_dup(struct nvkm_object *parent, struct nvkm_gpuobj *base,
+ struct nvkm_gpuobj **pgpuobj)
{
- struct nouveau_gpuobj *gpuobj;
+ struct nvkm_gpuobj *gpuobj;
int ret;
- ret = nouveau_object_create(parent, &parent->engine->subdev.object,
- &nouveau_gpudup_oclass, 0, &gpuobj);
+ ret = nvkm_object_create(parent, &parent->engine->subdev.object,
+ &nvkm_gpudup_oclass, 0, &gpuobj);
*pgpuobj = gpuobj;
if (ret)
return ret;
- nouveau_object_ref(nv_object(base), &gpuobj->parent);
+ nvkm_object_ref(nv_object(base), &gpuobj->parent);
gpuobj->addr = base->addr;
gpuobj->size = base->size;
return 0;
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/handle.c b/drivers/gpu/drm/nouveau/nvkm/core/handle.c
index 13f816cb08bd..dc7ff10ebe7b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/handle.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/handle.c
@@ -21,31 +21,29 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/object.h>
#include <core/handle.h>
#include <core/client.h>
#define hprintk(h,l,f,a...) do { \
- struct nouveau_client *c = nouveau_client((h)->object); \
- struct nouveau_handle *p = (h)->parent; u32 n = p ? p->name : ~0; \
+ struct nvkm_client *c = nvkm_client((h)->object); \
+ struct nvkm_handle *p = (h)->parent; u32 n = p ? p->name : ~0; \
nv_printk((c), l, "0x%08x:0x%08x "f, n, (h)->name, ##a); \
} while(0)
int
-nouveau_handle_init(struct nouveau_handle *handle)
+nvkm_handle_init(struct nvkm_handle *handle)
{
- struct nouveau_handle *item;
+ struct nvkm_handle *item;
int ret;
hprintk(handle, TRACE, "init running\n");
- ret = nouveau_object_inc(handle->object);
+ ret = nvkm_object_inc(handle->object);
if (ret)
return ret;
hprintk(handle, TRACE, "init children\n");
list_for_each_entry(item, &handle->tree, head) {
- ret = nouveau_handle_init(item);
+ ret = nvkm_handle_init(item);
if (ret)
goto fail;
}
@@ -55,30 +53,30 @@ nouveau_handle_init(struct nouveau_handle *handle)
fail:
hprintk(handle, ERROR, "init failed with %d\n", ret);
list_for_each_entry_continue_reverse(item, &handle->tree, head) {
- nouveau_handle_fini(item, false);
+ nvkm_handle_fini(item, false);
}
- nouveau_object_dec(handle->object, false);
+ nvkm_object_dec(handle->object, false);
return ret;
}
int
-nouveau_handle_fini(struct nouveau_handle *handle, bool suspend)
+nvkm_handle_fini(struct nvkm_handle *handle, bool suspend)
{
static char *name[2] = { "fini", "suspend" };
- struct nouveau_handle *item;
+ struct nvkm_handle *item;
int ret;
hprintk(handle, TRACE, "%s children\n", name[suspend]);
list_for_each_entry(item, &handle->tree, head) {
- ret = nouveau_handle_fini(item, suspend);
+ ret = nvkm_handle_fini(item, suspend);
if (ret && suspend)
goto fail;
}
hprintk(handle, TRACE, "%s running\n", name[suspend]);
if (handle->object) {
- ret = nouveau_object_dec(handle->object, suspend);
+ ret = nvkm_object_dec(handle->object, suspend);
if (ret && suspend)
goto fail;
}
@@ -88,7 +86,7 @@ nouveau_handle_fini(struct nouveau_handle *handle, bool suspend)
fail:
hprintk(handle, ERROR, "%s failed with %d\n", name[suspend], ret);
list_for_each_entry_continue_reverse(item, &handle->tree, head) {
- int rret = nouveau_handle_init(item);
+ int rret = nvkm_handle_init(item);
if (rret)
hprintk(handle, FATAL, "failed to restart, %d\n", rret);
}
@@ -97,12 +95,11 @@ fail:
}
int
-nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle,
- struct nouveau_object *object,
- struct nouveau_handle **phandle)
+nvkm_handle_create(struct nvkm_object *parent, u32 _parent, u32 _handle,
+ struct nvkm_object *object, struct nvkm_handle **phandle)
{
- struct nouveau_object *namedb;
- struct nouveau_handle *handle;
+ struct nvkm_object *namedb;
+ struct nvkm_handle *handle;
int ret;
namedb = parent;
@@ -118,7 +115,7 @@ nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle,
handle->name = _handle;
handle->priv = ~0;
- ret = nouveau_namedb_insert(nv_namedb(namedb), _handle, object, handle);
+ ret = nvkm_namedb_insert(nv_namedb(namedb), _handle, object, handle);
if (ret) {
kfree(handle);
return ret;
@@ -127,7 +124,7 @@ nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle,
if (nv_parent(parent)->object_attach) {
ret = nv_parent(parent)->object_attach(parent, object, _handle);
if (ret < 0) {
- nouveau_handle_destroy(handle);
+ nvkm_handle_destroy(handle);
return ret;
}
@@ -138,10 +135,10 @@ nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle,
while (!nv_iclass(namedb, NV_CLIENT_CLASS))
namedb = namedb->parent;
- handle->parent = nouveau_namedb_get(nv_namedb(namedb), _parent);
+ handle->parent = nvkm_namedb_get(nv_namedb(namedb), _parent);
if (handle->parent) {
list_add(&handle->head, &handle->parent->tree);
- nouveau_namedb_put(handle->parent);
+ nvkm_namedb_put(handle->parent);
}
}
@@ -151,74 +148,74 @@ nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle,
}
void
-nouveau_handle_destroy(struct nouveau_handle *handle)
+nvkm_handle_destroy(struct nvkm_handle *handle)
{
- struct nouveau_handle *item, *temp;
+ struct nvkm_handle *item, *temp;
hprintk(handle, TRACE, "destroy running\n");
list_for_each_entry_safe(item, temp, &handle->tree, head) {
- nouveau_handle_destroy(item);
+ nvkm_handle_destroy(item);
}
list_del(&handle->head);
if (handle->priv != ~0) {
- struct nouveau_object *parent = handle->parent->object;
+ struct nvkm_object *parent = handle->parent->object;
nv_parent(parent)->object_detach(parent, handle->priv);
}
hprintk(handle, TRACE, "destroy completed\n");
- nouveau_namedb_remove(handle);
+ nvkm_namedb_remove(handle);
kfree(handle);
}
-struct nouveau_object *
-nouveau_handle_ref(struct nouveau_object *parent, u32 name)
+struct nvkm_object *
+nvkm_handle_ref(struct nvkm_object *parent, u32 name)
{
- struct nouveau_object *object = NULL;
- struct nouveau_handle *handle;
+ struct nvkm_object *object = NULL;
+ struct nvkm_handle *handle;
while (!nv_iclass(parent, NV_NAMEDB_CLASS))
parent = parent->parent;
- handle = nouveau_namedb_get(nv_namedb(parent), name);
+ handle = nvkm_namedb_get(nv_namedb(parent), name);
if (handle) {
- nouveau_object_ref(handle->object, &object);
- nouveau_namedb_put(handle);
+ nvkm_object_ref(handle->object, &object);
+ nvkm_namedb_put(handle);
}
return object;
}
-struct nouveau_handle *
-nouveau_handle_get_class(struct nouveau_object *engctx, u16 oclass)
+struct nvkm_handle *
+nvkm_handle_get_class(struct nvkm_object *engctx, u16 oclass)
{
- struct nouveau_namedb *namedb;
+ struct nvkm_namedb *namedb;
if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS)))
- return nouveau_namedb_get_class(namedb, oclass);
+ return nvkm_namedb_get_class(namedb, oclass);
return NULL;
}
-struct nouveau_handle *
-nouveau_handle_get_vinst(struct nouveau_object *engctx, u64 vinst)
+struct nvkm_handle *
+nvkm_handle_get_vinst(struct nvkm_object *engctx, u64 vinst)
{
- struct nouveau_namedb *namedb;
+ struct nvkm_namedb *namedb;
if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS)))
- return nouveau_namedb_get_vinst(namedb, vinst);
+ return nvkm_namedb_get_vinst(namedb, vinst);
return NULL;
}
-struct nouveau_handle *
-nouveau_handle_get_cinst(struct nouveau_object *engctx, u32 cinst)
+struct nvkm_handle *
+nvkm_handle_get_cinst(struct nvkm_object *engctx, u32 cinst)
{
- struct nouveau_namedb *namedb;
+ struct nvkm_namedb *namedb;
if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS)))
- return nouveau_namedb_get_cinst(namedb, cinst);
+ return nvkm_namedb_get_cinst(namedb, cinst);
return NULL;
}
void
-nouveau_handle_put(struct nouveau_handle *handle)
+nvkm_handle_put(struct nvkm_handle *handle)
{
if (handle)
- nouveau_namedb_put(handle);
+ nvkm_namedb_put(handle);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
index bdfabb4a8dc9..4459ff5f4cb8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
@@ -21,23 +21,19 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include <core/object.h>
-#include <core/parent.h>
+#include <core/ioctl.h>
+#include <core/client.h>
+#include <core/engine.h>
#include <core/handle.h>
#include <core/namedb.h>
-#include <core/client.h>
-#include <core/device.h>
-#include <core/ioctl.h>
-#include <core/event.h>
#include <nvif/unpack.h>
#include <nvif/ioctl.h>
static int
-nvkm_ioctl_nop(struct nouveau_handle *handle, void *data, u32 size)
+nvkm_ioctl_nop(struct nvkm_handle *handle, void *data, u32 size)
{
- struct nouveau_object *object = handle->object;
+ struct nvkm_object *object = handle->object;
union {
struct nvif_ioctl_nop none;
} *args = data;
@@ -52,9 +48,9 @@ nvkm_ioctl_nop(struct nouveau_handle *handle, void *data, u32 size)
}
static int
-nvkm_ioctl_sclass(struct nouveau_handle *handle, void *data, u32 size)
+nvkm_ioctl_sclass(struct nvkm_handle *handle, void *data, u32 size)
{
- struct nouveau_object *object = handle->object;
+ struct nvkm_object *object = handle->object;
union {
struct nvif_ioctl_sclass_v0 v0;
} *args = data;
@@ -70,8 +66,8 @@ nvkm_ioctl_sclass(struct nouveau_handle *handle, void *data, u32 size)
nv_ioctl(object, "sclass vers %d count %d\n",
args->v0.version, args->v0.count);
if (size == args->v0.count * sizeof(args->v0.oclass[0])) {
- ret = nouveau_parent_lclass(object, args->v0.oclass,
- args->v0.count);
+ ret = nvkm_parent_lclass(object, args->v0.oclass,
+ args->v0.count);
if (ret >= 0) {
args->v0.count = ret;
ret = 0;
@@ -85,17 +81,17 @@ nvkm_ioctl_sclass(struct nouveau_handle *handle, void *data, u32 size)
}
static int
-nvkm_ioctl_new(struct nouveau_handle *handle, void *data, u32 size)
+nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size)
{
union {
struct nvif_ioctl_new_v0 v0;
} *args = data;
- struct nouveau_client *client = nouveau_client(handle->object);
- struct nouveau_object *engctx = NULL;
- struct nouveau_object *object = NULL;
- struct nouveau_parent *parent;
- struct nouveau_object *engine;
- struct nouveau_oclass *oclass;
+ struct nvkm_client *client = nvkm_client(handle->object);
+ struct nvkm_object *engctx = NULL;
+ struct nvkm_object *object = NULL;
+ struct nvkm_parent *parent;
+ struct nvkm_object *engine;
+ struct nvkm_oclass *oclass;
u32 _handle, _oclass;
int ret;
@@ -108,8 +104,8 @@ nvkm_ioctl_new(struct nouveau_handle *handle, void *data, u32 size)
nv_ioctl(client, "new vers %d handle %08x class %08x "
"route %02x token %llx\n",
- args->v0.version, _handle, _oclass,
- args->v0.route, args->v0.token);
+ args->v0.version, _handle, _oclass,
+ args->v0.route, args->v0.token);
if (!nv_iclass(handle->object, NV_PARENT_CLASS)) {
nv_debug(handle->object, "cannot have children (ctor)\n");
@@ -120,7 +116,7 @@ nvkm_ioctl_new(struct nouveau_handle *handle, void *data, u32 size)
parent = nv_parent(handle->object);
/* check that parent supports the requested subclass */
- ret = nouveau_parent_sclass(&parent->object, _oclass, &engine, &oclass);
+ ret = nvkm_parent_sclass(&parent->object, _oclass, &engine, &oclass);
if (ret) {
nv_debug(parent, "illegal class 0x%04x\n", _oclass);
goto fail_class;
@@ -131,7 +127,7 @@ nvkm_ioctl_new(struct nouveau_handle *handle, void *data, u32 size)
* state calculated at init (ie. default context construction)
*/
if (engine) {
- ret = nouveau_object_inc(engine);
+ ret = nvkm_object_inc(engine);
if (ret)
goto fail_class;
}
@@ -140,53 +136,53 @@ nvkm_ioctl_new(struct nouveau_handle *handle, void *data, u32 size)
* between the parent and its children (eg. PGRAPH context)
*/
if (engine && nv_engine(engine)->cclass) {
- ret = nouveau_object_ctor(&parent->object, engine,
- nv_engine(engine)->cclass,
- data, size, &engctx);
+ ret = nvkm_object_ctor(&parent->object, engine,
+ nv_engine(engine)->cclass,
+ data, size, &engctx);
if (ret)
goto fail_engctx;
} else {
- nouveau_object_ref(&parent->object, &engctx);
+ nvkm_object_ref(&parent->object, &engctx);
}
/* finally, create new object and bind it to its handle */
- ret = nouveau_object_ctor(engctx, engine, oclass, data, size, &object);
+ ret = nvkm_object_ctor(engctx, engine, oclass, data, size, &object);
client->data = object;
if (ret)
goto fail_ctor;
- ret = nouveau_object_inc(object);
+ ret = nvkm_object_inc(object);
if (ret)
goto fail_init;
- ret = nouveau_handle_create(&parent->object, handle->name,
- _handle, object, &handle);
+ ret = nvkm_handle_create(&parent->object, handle->name,
+ _handle, object, &handle);
if (ret)
goto fail_handle;
- ret = nouveau_handle_init(handle);
+ ret = nvkm_handle_init(handle);
handle->route = args->v0.route;
handle->token = args->v0.token;
if (ret)
- nouveau_handle_destroy(handle);
+ nvkm_handle_destroy(handle);
fail_handle:
- nouveau_object_dec(object, false);
+ nvkm_object_dec(object, false);
fail_init:
- nouveau_object_ref(NULL, &object);
+ nvkm_object_ref(NULL, &object);
fail_ctor:
- nouveau_object_ref(NULL, &engctx);
+ nvkm_object_ref(NULL, &engctx);
fail_engctx:
if (engine)
- nouveau_object_dec(engine, false);
+ nvkm_object_dec(engine, false);
fail_class:
return ret;
}
static int
-nvkm_ioctl_del(struct nouveau_handle *handle, void *data, u32 size)
+nvkm_ioctl_del(struct nvkm_handle *handle, void *data, u32 size)
{
- struct nouveau_object *object = handle->object;
+ struct nvkm_object *object = handle->object;
union {
struct nvif_ioctl_del none;
} *args = data;
@@ -195,18 +191,18 @@ nvkm_ioctl_del(struct nouveau_handle *handle, void *data, u32 size)
nv_ioctl(object, "delete size %d\n", size);
if (nvif_unvers(args->none)) {
nv_ioctl(object, "delete\n");
- nouveau_handle_fini(handle, false);
- nouveau_handle_destroy(handle);
+ nvkm_handle_fini(handle, false);
+ nvkm_handle_destroy(handle);
}
return ret;
}
static int
-nvkm_ioctl_mthd(struct nouveau_handle *handle, void *data, u32 size)
+nvkm_ioctl_mthd(struct nvkm_handle *handle, void *data, u32 size)
{
- struct nouveau_object *object = handle->object;
- struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs;
+ struct nvkm_object *object = handle->object;
+ struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs;
union {
struct nvif_ioctl_mthd_v0 v0;
} *args = data;
@@ -225,10 +221,10 @@ nvkm_ioctl_mthd(struct nouveau_handle *handle, void *data, u32 size)
static int
-nvkm_ioctl_rd(struct nouveau_handle *handle, void *data, u32 size)
+nvkm_ioctl_rd(struct nvkm_handle *handle, void *data, u32 size)
{
- struct nouveau_object *object = handle->object;
- struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs;
+ struct nvkm_object *object = handle->object;
+ struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs;
union {
struct nvif_ioctl_rd_v0 v0;
} *args = data;
@@ -237,7 +233,7 @@ nvkm_ioctl_rd(struct nouveau_handle *handle, void *data, u32 size)
nv_ioctl(object, "rd size %d\n", size);
if (nvif_unpack(args->v0, 0, 0, false)) {
nv_ioctl(object, "rd vers %d size %d addr %016llx\n",
- args->v0.version, args->v0.size, args->v0.addr);
+ args->v0.version, args->v0.size, args->v0.addr);
switch (args->v0.size) {
case 1:
if (ret = -ENODEV, ofuncs->rd08) {
@@ -267,10 +263,10 @@ nvkm_ioctl_rd(struct nouveau_handle *handle, void *data, u32 size)
}
static int
-nvkm_ioctl_wr(struct nouveau_handle *handle, void *data, u32 size)
+nvkm_ioctl_wr(struct nvkm_handle *handle, void *data, u32 size)
{
- struct nouveau_object *object = handle->object;
- struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs;
+ struct nvkm_object *object = handle->object;
+ struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs;
union {
struct nvif_ioctl_wr_v0 v0;
} *args = data;
@@ -310,10 +306,10 @@ nvkm_ioctl_wr(struct nouveau_handle *handle, void *data, u32 size)
}
static int
-nvkm_ioctl_map(struct nouveau_handle *handle, void *data, u32 size)
+nvkm_ioctl_map(struct nvkm_handle *handle, void *data, u32 size)
{
- struct nouveau_object *object = handle->object;
- struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs;
+ struct nvkm_object *object = handle->object;
+ struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs;
union {
struct nvif_ioctl_map_v0 v0;
} *args = data;
@@ -332,9 +328,9 @@ nvkm_ioctl_map(struct nouveau_handle *handle, void *data, u32 size)
}
static int
-nvkm_ioctl_unmap(struct nouveau_handle *handle, void *data, u32 size)
+nvkm_ioctl_unmap(struct nvkm_handle *handle, void *data, u32 size)
{
- struct nouveau_object *object = handle->object;
+ struct nvkm_object *object = handle->object;
union {
struct nvif_ioctl_unmap none;
} *args = data;
@@ -349,10 +345,10 @@ nvkm_ioctl_unmap(struct nouveau_handle *handle, void *data, u32 size)
}
static int
-nvkm_ioctl_ntfy_new(struct nouveau_handle *handle, void *data, u32 size)
+nvkm_ioctl_ntfy_new(struct nvkm_handle *handle, void *data, u32 size)
{
- struct nouveau_object *object = handle->object;
- struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs;
+ struct nvkm_object *object = handle->object;
+ struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs;
union {
struct nvif_ioctl_ntfy_new_v0 v0;
} *args = data;
@@ -378,10 +374,10 @@ nvkm_ioctl_ntfy_new(struct nouveau_handle *handle, void *data, u32 size)
}
static int
-nvkm_ioctl_ntfy_del(struct nouveau_handle *handle, void *data, u32 size)
+nvkm_ioctl_ntfy_del(struct nvkm_handle *handle, void *data, u32 size)
{
- struct nouveau_client *client = nouveau_client(handle->object);
- struct nouveau_object *object = handle->object;
+ struct nvkm_client *client = nvkm_client(handle->object);
+ struct nvkm_object *object = handle->object;
union {
struct nvif_ioctl_ntfy_del_v0 v0;
} *args = data;
@@ -398,10 +394,10 @@ nvkm_ioctl_ntfy_del(struct nouveau_handle *handle, void *data, u32 size)
}
static int
-nvkm_ioctl_ntfy_get(struct nouveau_handle *handle, void *data, u32 size)
+nvkm_ioctl_ntfy_get(struct nvkm_handle *handle, void *data, u32 size)
{
- struct nouveau_client *client = nouveau_client(handle->object);
- struct nouveau_object *object = handle->object;
+ struct nvkm_client *client = nvkm_client(handle->object);
+ struct nvkm_object *object = handle->object;
union {
struct nvif_ioctl_ntfy_get_v0 v0;
} *args = data;
@@ -418,10 +414,10 @@ nvkm_ioctl_ntfy_get(struct nouveau_handle *handle, void *data, u32 size)
}
static int
-nvkm_ioctl_ntfy_put(struct nouveau_handle *handle, void *data, u32 size)
+nvkm_ioctl_ntfy_put(struct nvkm_handle *handle, void *data, u32 size)
{
- struct nouveau_client *client = nouveau_client(handle->object);
- struct nouveau_object *object = handle->object;
+ struct nvkm_client *client = nvkm_client(handle->object);
+ struct nvkm_object *object = handle->object;
union {
struct nvif_ioctl_ntfy_put_v0 v0;
} *args = data;
@@ -439,7 +435,7 @@ nvkm_ioctl_ntfy_put(struct nouveau_handle *handle, void *data, u32 size)
static struct {
int version;
- int (*func)(struct nouveau_handle *, void *, u32);
+ int (*func)(struct nvkm_handle *, void *, u32);
}
nvkm_ioctl_v0[] = {
{ 0x00, nvkm_ioctl_nop },
@@ -458,13 +454,12 @@ nvkm_ioctl_v0[] = {
};
static int
-nvkm_ioctl_path(struct nouveau_handle *parent, u32 type, u32 nr,
- u32 *path, void *data, u32 size,
- u8 owner, u8 *route, u64 *token)
+nvkm_ioctl_path(struct nvkm_handle *parent, u32 type, u32 nr, u32 *path,
+ void *data, u32 size, u8 owner, u8 *route, u64 *token)
{
- struct nouveau_handle *handle = parent;
- struct nouveau_namedb *namedb;
- struct nouveau_object *object;
+ struct nvkm_handle *handle = parent;
+ struct nvkm_namedb *namedb;
+ struct nvkm_object *object;
int ret;
while ((object = parent->object), nr--) {
@@ -475,16 +470,15 @@ nvkm_ioctl_path(struct nouveau_handle *parent, u32 type, u32 nr,
}
if (!(namedb = (void *)nv_pclass(object, NV_NAMEDB_CLASS)) ||
- !(handle = nouveau_namedb_get(namedb, path[nr]))) {
+ !(handle = nvkm_namedb_get(namedb, path[nr]))) {
nv_debug(object, "handle 0x%08x not found\n", path[nr]);
return -ENOENT;
}
- nouveau_namedb_put(handle);
+ nvkm_namedb_put(handle);
parent = handle;
}
- if (owner != NVIF_IOCTL_V0_OWNER_ANY &&
- owner != handle->route) {
+ if (owner != NVIF_IOCTL_V0_OWNER_ANY && owner != handle->route) {
nv_ioctl(object, "object route != owner\n");
return -EACCES;
}
@@ -492,16 +486,15 @@ nvkm_ioctl_path(struct nouveau_handle *parent, u32 type, u32 nr,
*token = handle->token;
if (ret = -EINVAL, type < ARRAY_SIZE(nvkm_ioctl_v0)) {
- if (nvkm_ioctl_v0[type].version == 0) {
+ if (nvkm_ioctl_v0[type].version == 0)
ret = nvkm_ioctl_v0[type].func(handle, data, size);
- }
}
return ret;
}
int
-nvkm_ioctl(struct nouveau_client *client, bool supervisor,
+nvkm_ioctl(struct nvkm_client *client, bool supervisor,
void *data, u32 size, void **hack)
{
union {
@@ -519,7 +512,7 @@ nvkm_ioctl(struct nouveau_client *client, bool supervisor,
ret = nvkm_ioctl_path(client->root, args->v0.type,
args->v0.path_nr, args->v0.path,
data, size, args->v0.owner,
- &args->v0.route, &args->v0.token);
+ &args->v0.route, &args->v0.token);
}
nv_ioctl(client, "return %d\n", ret);
@@ -527,6 +520,7 @@ nvkm_ioctl(struct nouveau_client *client, bool supervisor,
*hack = client->data;
client->data = NULL;
}
+
client->super = false;
return ret;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/mm.c b/drivers/gpu/drm/nouveau/nvkm/core/mm.c
index b4f5db66d5b5..7f458dfd5608 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/mm.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/mm.c
@@ -21,39 +21,37 @@
*
* Authors: Ben Skeggs
*/
+#include <core/mm.h>
-#include "core/os.h"
-#include "core/mm.h"
-
-#define node(root, dir) ((root)->nl_entry.dir == &mm->nodes) ? NULL : \
- list_entry((root)->nl_entry.dir, struct nouveau_mm_node, nl_entry)
+#define node(root, dir) ((root)->nl_entry.dir == &mm->nodes) ? NULL : \
+ list_entry((root)->nl_entry.dir, struct nvkm_mm_node, nl_entry)
static void
-nouveau_mm_dump(struct nouveau_mm *mm, const char *header)
+nvkm_mm_dump(struct nvkm_mm *mm, const char *header)
{
- struct nouveau_mm_node *node;
+ struct nvkm_mm_node *node;
- printk(KERN_ERR "nouveau: %s\n", header);
- printk(KERN_ERR "nouveau: node list:\n");
+ printk(KERN_ERR "nvkm: %s\n", header);
+ printk(KERN_ERR "nvkm: node list:\n");
list_for_each_entry(node, &mm->nodes, nl_entry) {
- printk(KERN_ERR "nouveau: \t%08x %08x %d\n",
+ printk(KERN_ERR "nvkm: \t%08x %08x %d\n",
node->offset, node->length, node->type);
}
- printk(KERN_ERR "nouveau: free list:\n");
+ printk(KERN_ERR "nvkm: free list:\n");
list_for_each_entry(node, &mm->free, fl_entry) {
- printk(KERN_ERR "nouveau: \t%08x %08x %d\n",
+ printk(KERN_ERR "nvkm: \t%08x %08x %d\n",
node->offset, node->length, node->type);
}
}
void
-nouveau_mm_free(struct nouveau_mm *mm, struct nouveau_mm_node **pthis)
+nvkm_mm_free(struct nvkm_mm *mm, struct nvkm_mm_node **pthis)
{
- struct nouveau_mm_node *this = *pthis;
+ struct nvkm_mm_node *this = *pthis;
if (this) {
- struct nouveau_mm_node *prev = node(this, prev);
- struct nouveau_mm_node *next = node(this, next);
+ struct nvkm_mm_node *prev = node(this, prev);
+ struct nvkm_mm_node *next = node(this, next);
if (prev && prev->type == NVKM_MM_TYPE_NONE) {
prev->length += this->length;
@@ -84,10 +82,10 @@ nouveau_mm_free(struct nouveau_mm *mm, struct nouveau_mm_node **pthis)
*pthis = NULL;
}
-static struct nouveau_mm_node *
-region_head(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size)
+static struct nvkm_mm_node *
+region_head(struct nvkm_mm *mm, struct nvkm_mm_node *a, u32 size)
{
- struct nouveau_mm_node *b;
+ struct nvkm_mm_node *b;
if (a->length == size)
return a;
@@ -105,14 +103,15 @@ region_head(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size)
list_add_tail(&b->nl_entry, &a->nl_entry);
if (b->type == NVKM_MM_TYPE_NONE)
list_add_tail(&b->fl_entry, &a->fl_entry);
+
return b;
}
int
-nouveau_mm_head(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max,
- u32 size_min, u32 align, struct nouveau_mm_node **pnode)
+nvkm_mm_head(struct nvkm_mm *mm, u8 heap, u8 type, u32 size_max, u32 size_min,
+ u32 align, struct nvkm_mm_node **pnode)
{
- struct nouveau_mm_node *prev, *this, *next;
+ struct nvkm_mm_node *prev, *this, *next;
u32 mask = align - 1;
u32 splitoff;
u32 s, e;
@@ -157,10 +156,10 @@ nouveau_mm_head(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max,
return -ENOSPC;
}
-static struct nouveau_mm_node *
-region_tail(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size)
+static struct nvkm_mm_node *
+region_tail(struct nvkm_mm *mm, struct nvkm_mm_node *a, u32 size)
{
- struct nouveau_mm_node *b;
+ struct nvkm_mm_node *b;
if (a->length == size)
return a;
@@ -178,14 +177,15 @@ region_tail(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size)
list_add(&b->nl_entry, &a->nl_entry);
if (b->type == NVKM_MM_TYPE_NONE)
list_add(&b->fl_entry, &a->fl_entry);
+
return b;
}
int
-nouveau_mm_tail(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max,
- u32 size_min, u32 align, struct nouveau_mm_node **pnode)
+nvkm_mm_tail(struct nvkm_mm *mm, u8 heap, u8 type, u32 size_max, u32 size_min,
+ u32 align, struct nvkm_mm_node **pnode)
{
- struct nouveau_mm_node *prev, *this, *next;
+ struct nvkm_mm_node *prev, *this, *next;
u32 mask = align - 1;
BUG_ON(type == NVKM_MM_TYPE_NONE || type == NVKM_MM_TYPE_HOLE);
@@ -235,12 +235,12 @@ nouveau_mm_tail(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max,
}
int
-nouveau_mm_init(struct nouveau_mm *mm, u32 offset, u32 length, u32 block)
+nvkm_mm_init(struct nvkm_mm *mm, u32 offset, u32 length, u32 block)
{
- struct nouveau_mm_node *node, *prev;
+ struct nvkm_mm_node *node, *prev;
u32 next;
- if (nouveau_mm_initialised(mm)) {
+ if (nvkm_mm_initialised(mm)) {
prev = list_last_entry(&mm->nodes, typeof(*node), nl_entry);
next = prev->offset + prev->length;
if (next != offset) {
@@ -277,18 +277,18 @@ nouveau_mm_init(struct nouveau_mm *mm, u32 offset, u32 length, u32 block)
}
int
-nouveau_mm_fini(struct nouveau_mm *mm)
+nvkm_mm_fini(struct nvkm_mm *mm)
{
- struct nouveau_mm_node *node, *temp;
+ struct nvkm_mm_node *node, *temp;
int nodes = 0;
- if (!nouveau_mm_initialised(mm))
+ if (!nvkm_mm_initialised(mm))
return 0;
list_for_each_entry(node, &mm->nodes, nl_entry) {
if (node->type != NVKM_MM_TYPE_HOLE) {
if (++nodes > mm->heap_nodes) {
- nouveau_mm_dump(mm, "mm not clean!");
+ nvkm_mm_dump(mm, "mm not clean!");
return -EBUSY;
}
}
@@ -298,6 +298,7 @@ nouveau_mm_fini(struct nouveau_mm *mm)
list_del(&node->nl_entry);
kfree(node);
}
+
mm->heap_nodes = 0;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/namedb.c b/drivers/gpu/drm/nouveau/nvkm/core/namedb.c
index 0594a599f6fb..6400767c5dba 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/namedb.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/namedb.c
@@ -21,16 +21,14 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/object.h>
#include <core/namedb.h>
-#include <core/handle.h>
#include <core/gpuobj.h>
+#include <core/handle.h>
-static struct nouveau_handle *
-nouveau_namedb_lookup(struct nouveau_namedb *namedb, u32 name)
+static struct nvkm_handle *
+nvkm_namedb_lookup(struct nvkm_namedb *namedb, u32 name)
{
- struct nouveau_handle *handle;
+ struct nvkm_handle *handle;
list_for_each_entry(handle, &namedb->list, node) {
if (handle->name == name)
@@ -40,10 +38,10 @@ nouveau_namedb_lookup(struct nouveau_namedb *namedb, u32 name)
return NULL;
}
-static struct nouveau_handle *
-nouveau_namedb_lookup_class(struct nouveau_namedb *namedb, u16 oclass)
+static struct nvkm_handle *
+nvkm_namedb_lookup_class(struct nvkm_namedb *namedb, u16 oclass)
{
- struct nouveau_handle *handle;
+ struct nvkm_handle *handle;
list_for_each_entry(handle, &namedb->list, node) {
if (nv_mclass(handle->object) == oclass)
@@ -53,10 +51,10 @@ nouveau_namedb_lookup_class(struct nouveau_namedb *namedb, u16 oclass)
return NULL;
}
-static struct nouveau_handle *
-nouveau_namedb_lookup_vinst(struct nouveau_namedb *namedb, u64 vinst)
+static struct nvkm_handle *
+nvkm_namedb_lookup_vinst(struct nvkm_namedb *namedb, u64 vinst)
{
- struct nouveau_handle *handle;
+ struct nvkm_handle *handle;
list_for_each_entry(handle, &namedb->list, node) {
if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
@@ -68,10 +66,10 @@ nouveau_namedb_lookup_vinst(struct nouveau_namedb *namedb, u64 vinst)
return NULL;
}
-static struct nouveau_handle *
-nouveau_namedb_lookup_cinst(struct nouveau_namedb *namedb, u32 cinst)
+static struct nvkm_handle *
+nvkm_namedb_lookup_cinst(struct nvkm_namedb *namedb, u32 cinst)
{
- struct nouveau_handle *handle;
+ struct nvkm_handle *handle;
list_for_each_entry(handle, &namedb->list, node) {
if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
@@ -85,14 +83,14 @@ nouveau_namedb_lookup_cinst(struct nouveau_namedb *namedb, u32 cinst)
}
int
-nouveau_namedb_insert(struct nouveau_namedb *namedb, u32 name,
- struct nouveau_object *object,
- struct nouveau_handle *handle)
+nvkm_namedb_insert(struct nvkm_namedb *namedb, u32 name,
+ struct nvkm_object *object,
+ struct nvkm_handle *handle)
{
int ret = -EEXIST;
write_lock_irq(&namedb->lock);
- if (!nouveau_namedb_lookup(namedb, name)) {
- nouveau_object_ref(object, &handle->object);
+ if (!nvkm_namedb_lookup(namedb, name)) {
+ nvkm_object_ref(object, &handle->object);
handle->namedb = namedb;
list_add(&handle->node, &namedb->list);
ret = 0;
@@ -102,80 +100,79 @@ nouveau_namedb_insert(struct nouveau_namedb *namedb, u32 name,
}
void
-nouveau_namedb_remove(struct nouveau_handle *handle)
+nvkm_namedb_remove(struct nvkm_handle *handle)
{
- struct nouveau_namedb *namedb = handle->namedb;
- struct nouveau_object *object = handle->object;
+ struct nvkm_namedb *namedb = handle->namedb;
+ struct nvkm_object *object = handle->object;
write_lock_irq(&namedb->lock);
list_del(&handle->node);
write_unlock_irq(&namedb->lock);
- nouveau_object_ref(NULL, &object);
+ nvkm_object_ref(NULL, &object);
}
-struct nouveau_handle *
-nouveau_namedb_get(struct nouveau_namedb *namedb, u32 name)
+struct nvkm_handle *
+nvkm_namedb_get(struct nvkm_namedb *namedb, u32 name)
{
- struct nouveau_handle *handle;
+ struct nvkm_handle *handle;
read_lock(&namedb->lock);
- handle = nouveau_namedb_lookup(namedb, name);
+ handle = nvkm_namedb_lookup(namedb, name);
if (handle == NULL)
read_unlock(&namedb->lock);
return handle;
}
-struct nouveau_handle *
-nouveau_namedb_get_class(struct nouveau_namedb *namedb, u16 oclass)
+struct nvkm_handle *
+nvkm_namedb_get_class(struct nvkm_namedb *namedb, u16 oclass)
{
- struct nouveau_handle *handle;
+ struct nvkm_handle *handle;
read_lock(&namedb->lock);
- handle = nouveau_namedb_lookup_class(namedb, oclass);
+ handle = nvkm_namedb_lookup_class(namedb, oclass);
if (handle == NULL)
read_unlock(&namedb->lock);
return handle;
}
-struct nouveau_handle *
-nouveau_namedb_get_vinst(struct nouveau_namedb *namedb, u64 vinst)
+struct nvkm_handle *
+nvkm_namedb_get_vinst(struct nvkm_namedb *namedb, u64 vinst)
{
- struct nouveau_handle *handle;
+ struct nvkm_handle *handle;
read_lock(&namedb->lock);
- handle = nouveau_namedb_lookup_vinst(namedb, vinst);
+ handle = nvkm_namedb_lookup_vinst(namedb, vinst);
if (handle == NULL)
read_unlock(&namedb->lock);
return handle;
}
-struct nouveau_handle *
-nouveau_namedb_get_cinst(struct nouveau_namedb *namedb, u32 cinst)
+struct nvkm_handle *
+nvkm_namedb_get_cinst(struct nvkm_namedb *namedb, u32 cinst)
{
- struct nouveau_handle *handle;
+ struct nvkm_handle *handle;
read_lock(&namedb->lock);
- handle = nouveau_namedb_lookup_cinst(namedb, cinst);
+ handle = nvkm_namedb_lookup_cinst(namedb, cinst);
if (handle == NULL)
read_unlock(&namedb->lock);
return handle;
}
void
-nouveau_namedb_put(struct nouveau_handle *handle)
+nvkm_namedb_put(struct nvkm_handle *handle)
{
if (handle)
read_unlock(&handle->namedb->lock);
}
int
-nouveau_namedb_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, u32 pclass,
- struct nouveau_oclass *sclass, u64 engcls,
- int length, void **pobject)
+nvkm_namedb_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, u32 pclass,
+ struct nvkm_oclass *sclass, u64 engcls,
+ int length, void **pobject)
{
- struct nouveau_namedb *namedb;
+ struct nvkm_namedb *namedb;
int ret;
- ret = nouveau_parent_create_(parent, engine, oclass, pclass |
- NV_NAMEDB_CLASS, sclass, engcls,
- length, pobject);
+ ret = nvkm_parent_create_(parent, engine, oclass, pclass |
+ NV_NAMEDB_CLASS, sclass, engcls,
+ length, pobject);
namedb = *pobject;
if (ret)
return ret;
@@ -186,15 +183,14 @@ nouveau_namedb_create_(struct nouveau_object *parent,
}
int
-_nouveau_namedb_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+_nvkm_namedb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_namedb *object;
+ struct nvkm_namedb *object;
int ret;
- ret = nouveau_namedb_create(parent, engine, oclass, 0, NULL, 0, &object);
+ ret = nvkm_namedb_create(parent, engine, oclass, 0, NULL, 0, &object);
*pobject = nv_object(object);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/notify.c b/drivers/gpu/drm/nouveau/nvkm/core/notify.c
index 839a32577680..023610d01458 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/notify.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/notify.c
@@ -21,13 +21,8 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include <core/client.h>
-#include <core/event.h>
#include <core/notify.h>
-
-#include <nvif/unpack.h>
-#include <nvif/event.h>
+#include <core/event.h>
static inline void
nvkm_notify_put_locked(struct nvkm_notify *notify)
@@ -134,7 +129,7 @@ nvkm_notify_fini(struct nvkm_notify *notify)
}
int
-nvkm_notify_init(struct nouveau_object *object, struct nvkm_event *event,
+nvkm_notify_init(struct nvkm_object *object, struct nvkm_event *event,
int (*func)(struct nvkm_notify *), bool work,
void *data, u32 size, u32 reply,
struct nvkm_notify *notify)
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/object.c b/drivers/gpu/drm/nouveau/nvkm/core/object.c
index b160860edf54..979f3627d395 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/object.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/object.c
@@ -21,36 +21,34 @@
*
* Authors: Ben Skeggs
*/
-
#include <core/object.h>
#include <core/engine.h>
-#ifdef NOUVEAU_OBJECT_MAGIC
+#ifdef NVKM_OBJECT_MAGIC
static struct list_head _objlist = LIST_HEAD_INIT(_objlist);
static DEFINE_SPINLOCK(_objlist_lock);
#endif
int
-nouveau_object_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, u32 pclass,
- int size, void **pobject)
+nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, u32 pclass,
+ int size, void **pobject)
{
- struct nouveau_object *object;
+ struct nvkm_object *object;
object = *pobject = kzalloc(size, GFP_KERNEL);
if (!object)
return -ENOMEM;
- nouveau_object_ref(parent, &object->parent);
- nouveau_object_ref(engine, (struct nouveau_object **)&object->engine);
+ nvkm_object_ref(parent, &object->parent);
+ nvkm_object_ref(engine, (struct nvkm_object **)&object->engine);
object->oclass = oclass;
object->oclass->handle |= pclass;
atomic_set(&object->refcount, 1);
atomic_set(&object->usecount, 0);
-#ifdef NOUVEAU_OBJECT_MAGIC
- object->_magic = NOUVEAU_OBJECT_MAGIC;
+#ifdef NVKM_OBJECT_MAGIC
+ object->_magic = NVKM_OBJECT_MAGIC;
spin_lock(&_objlist_lock);
list_add(&object->list, &_objlist);
spin_unlock(&_objlist_lock);
@@ -59,57 +57,55 @@ nouveau_object_create_(struct nouveau_object *parent,
}
int
-_nouveau_object_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+_nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
if (size != 0)
return -ENOSYS;
- return nouveau_object_create(parent, engine, oclass, 0, pobject);
+ return nvkm_object_create(parent, engine, oclass, 0, pobject);
}
void
-nouveau_object_destroy(struct nouveau_object *object)
+nvkm_object_destroy(struct nvkm_object *object)
{
-#ifdef NOUVEAU_OBJECT_MAGIC
+#ifdef NVKM_OBJECT_MAGIC
spin_lock(&_objlist_lock);
list_del(&object->list);
spin_unlock(&_objlist_lock);
#endif
- nouveau_object_ref(NULL, (struct nouveau_object **)&object->engine);
- nouveau_object_ref(NULL, &object->parent);
+ nvkm_object_ref(NULL, (struct nvkm_object **)&object->engine);
+ nvkm_object_ref(NULL, &object->parent);
kfree(object);
}
int
-nouveau_object_init(struct nouveau_object *object)
+nvkm_object_init(struct nvkm_object *object)
{
return 0;
}
int
-nouveau_object_fini(struct nouveau_object *object, bool suspend)
+nvkm_object_fini(struct nvkm_object *object, bool suspend)
{
return 0;
}
-struct nouveau_ofuncs
-nouveau_object_ofuncs = {
- .ctor = _nouveau_object_ctor,
- .dtor = nouveau_object_destroy,
- .init = nouveau_object_init,
- .fini = nouveau_object_fini,
+struct nvkm_ofuncs
+nvkm_object_ofuncs = {
+ .ctor = _nvkm_object_ctor,
+ .dtor = nvkm_object_destroy,
+ .init = nvkm_object_init,
+ .fini = nvkm_object_fini,
};
int
-nouveau_object_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_ofuncs *ofuncs = oclass->ofuncs;
- struct nouveau_object *object = NULL;
+ struct nvkm_ofuncs *ofuncs = oclass->ofuncs;
+ struct nvkm_object *object = NULL;
int ret;
ret = ofuncs->ctor(parent, engine, oclass, data, size, &object);
@@ -137,14 +133,14 @@ nouveau_object_ctor(struct nouveau_object *parent,
}
static void
-nouveau_object_dtor(struct nouveau_object *object)
+nvkm_object_dtor(struct nvkm_object *object)
{
nv_trace(object, "destroying\n");
nv_ofuncs(object)->dtor(object);
}
void
-nouveau_object_ref(struct nouveau_object *obj, struct nouveau_object **ref)
+nvkm_object_ref(struct nvkm_object *obj, struct nvkm_object **ref)
{
if (obj) {
atomic_inc(&obj->refcount);
@@ -155,14 +151,14 @@ nouveau_object_ref(struct nouveau_object *obj, struct nouveau_object **ref)
int dead = atomic_dec_and_test(&(*ref)->refcount);
nv_trace(*ref, "dec() == %d\n", atomic_read(&(*ref)->refcount));
if (dead)
- nouveau_object_dtor(*ref);
+ nvkm_object_dtor(*ref);
}
*ref = obj;
}
int
-nouveau_object_inc(struct nouveau_object *object)
+nvkm_object_inc(struct nvkm_object *object)
{
int ref = atomic_add_return(1, &object->usecount);
int ret;
@@ -173,7 +169,7 @@ nouveau_object_inc(struct nouveau_object *object)
nv_trace(object, "initialising...\n");
if (object->parent) {
- ret = nouveau_object_inc(object->parent);
+ ret = nvkm_object_inc(object->parent);
if (ret) {
nv_error(object, "parent failed, %d\n", ret);
goto fail_parent;
@@ -182,7 +178,7 @@ nouveau_object_inc(struct nouveau_object *object)
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
- ret = nouveau_object_inc(&object->engine->subdev.object);
+ ret = nvkm_object_inc(&object->engine->subdev.object);
mutex_unlock(&nv_subdev(object->engine)->mutex);
if (ret) {
nv_error(object, "engine failed, %d\n", ret);
@@ -203,19 +199,19 @@ nouveau_object_inc(struct nouveau_object *object)
fail_self:
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
- nouveau_object_dec(&object->engine->subdev.object, false);
+ nvkm_object_dec(&object->engine->subdev.object, false);
mutex_unlock(&nv_subdev(object->engine)->mutex);
}
fail_engine:
if (object->parent)
- nouveau_object_dec(object->parent, false);
+ nvkm_object_dec(object->parent, false);
fail_parent:
atomic_dec(&object->usecount);
return ret;
}
static int
-nouveau_object_decf(struct nouveau_object *object)
+nvkm_object_decf(struct nvkm_object *object)
{
int ret;
@@ -228,19 +224,19 @@ nouveau_object_decf(struct nouveau_object *object)
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
- nouveau_object_dec(&object->engine->subdev.object, false);
+ nvkm_object_dec(&object->engine->subdev.object, false);
mutex_unlock(&nv_subdev(object->engine)->mutex);
}
if (object->parent)
- nouveau_object_dec(object->parent, false);
+ nvkm_object_dec(object->parent, false);
nv_trace(object, "stopped\n");
return 0;
}
static int
-nouveau_object_decs(struct nouveau_object *object)
+nvkm_object_decs(struct nvkm_object *object)
{
int ret, rret;
@@ -255,7 +251,7 @@ nouveau_object_decs(struct nouveau_object *object)
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
- ret = nouveau_object_dec(&object->engine->subdev.object, true);
+ ret = nvkm_object_dec(&object->engine->subdev.object, true);
mutex_unlock(&nv_subdev(object->engine)->mutex);
if (ret) {
nv_warn(object, "engine failed suspend, %d\n", ret);
@@ -264,7 +260,7 @@ nouveau_object_decs(struct nouveau_object *object)
}
if (object->parent) {
- ret = nouveau_object_dec(object->parent, true);
+ ret = nvkm_object_dec(object->parent, true);
if (ret) {
nv_warn(object, "parent failed suspend, %d\n", ret);
goto fail_parent;
@@ -277,7 +273,7 @@ nouveau_object_decs(struct nouveau_object *object)
fail_parent:
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
- rret = nouveau_object_inc(&object->engine->subdev.object);
+ rret = nvkm_object_inc(&object->engine->subdev.object);
mutex_unlock(&nv_subdev(object->engine)->mutex);
if (rret)
nv_fatal(object, "engine failed to reinit, %d\n", rret);
@@ -292,7 +288,7 @@ fail_engine:
}
int
-nouveau_object_dec(struct nouveau_object *object, bool suspend)
+nvkm_object_dec(struct nvkm_object *object, bool suspend)
{
int ref = atomic_add_return(-1, &object->usecount);
int ret;
@@ -301,9 +297,9 @@ nouveau_object_dec(struct nouveau_object *object, bool suspend)
if (ref == 0) {
if (suspend)
- ret = nouveau_object_decs(object);
+ ret = nvkm_object_decs(object);
else
- ret = nouveau_object_decf(object);
+ ret = nvkm_object_decf(object);
if (ret) {
atomic_inc(&object->usecount);
@@ -315,10 +311,10 @@ nouveau_object_dec(struct nouveau_object *object, bool suspend)
}
void
-nouveau_object_debug(void)
+nvkm_object_debug(void)
{
-#ifdef NOUVEAU_OBJECT_MAGIC
- struct nouveau_object *object;
+#ifdef NVKM_OBJECT_MAGIC
+ struct nvkm_object *object;
if (!list_empty(&_objlist)) {
nv_fatal(NULL, "*******************************************\n");
nv_fatal(NULL, "* AIIIII! object(s) still exist!!!\n");
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/option.c b/drivers/gpu/drm/nouveau/nvkm/core/option.c
index 9f6fcc5f66c2..19d153f8c8fd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/option.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/option.c
@@ -21,12 +21,11 @@
*
* Authors: Ben Skeggs
*/
-
#include <core/option.h>
#include <core/debug.h>
const char *
-nouveau_stropt(const char *optstr, const char *opt, int *arglen)
+nvkm_stropt(const char *optstr, const char *opt, int *arglen)
{
while (optstr && *optstr != '\0') {
int len = strcspn(optstr, ",=");
@@ -52,11 +51,11 @@ nouveau_stropt(const char *optstr, const char *opt, int *arglen)
}
bool
-nouveau_boolopt(const char *optstr, const char *opt, bool value)
+nvkm_boolopt(const char *optstr, const char *opt, bool value)
{
int arglen;
- optstr = nouveau_stropt(optstr, opt, &arglen);
+ optstr = nvkm_stropt(optstr, opt, &arglen);
if (optstr) {
if (!strncasecmpz(optstr, "0", arglen) ||
!strncasecmpz(optstr, "no", arglen) ||
@@ -75,7 +74,7 @@ nouveau_boolopt(const char *optstr, const char *opt, bool value)
}
int
-nouveau_dbgopt(const char *optstr, const char *sub)
+nvkm_dbgopt(const char *optstr, const char *sub)
{
int mode = 1, level = CONFIG_NOUVEAU_DEBUG_DEFAULT;
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/parent.c b/drivers/gpu/drm/nouveau/nvkm/core/parent.c
index 1f28fa12e98f..dd56cd1eeb38 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/parent.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/parent.c
@@ -21,19 +21,18 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/object.h>
#include <core/parent.h>
#include <core/client.h>
+#include <core/engine.h>
int
-nouveau_parent_sclass(struct nouveau_object *parent, u16 handle,
- struct nouveau_object **pengine,
- struct nouveau_oclass **poclass)
+nvkm_parent_sclass(struct nvkm_object *parent, u16 handle,
+ struct nvkm_object **pengine,
+ struct nvkm_oclass **poclass)
{
- struct nouveau_sclass *sclass;
- struct nouveau_engine *engine;
- struct nouveau_oclass *oclass;
+ struct nvkm_sclass *sclass;
+ struct nvkm_engine *engine;
+ struct nvkm_oclass *oclass;
u64 mask;
sclass = nv_parent(parent)->sclass;
@@ -54,7 +53,7 @@ nouveau_parent_sclass(struct nouveau_object *parent, u16 handle,
if (nv_iclass(parent, NV_CLIENT_CLASS))
engine = nv_engine(nv_client(parent)->device);
else
- engine = nouveau_engine(parent, i);
+ engine = nvkm_engine(parent, i);
if (engine) {
oclass = engine->sclass;
@@ -75,11 +74,11 @@ nouveau_parent_sclass(struct nouveau_object *parent, u16 handle,
}
int
-nouveau_parent_lclass(struct nouveau_object *parent, u32 *lclass, int size)
+nvkm_parent_lclass(struct nvkm_object *parent, u32 *lclass, int size)
{
- struct nouveau_sclass *sclass;
- struct nouveau_engine *engine;
- struct nouveau_oclass *oclass;
+ struct nvkm_sclass *sclass;
+ struct nvkm_engine *engine;
+ struct nvkm_oclass *oclass;
int nr = -1, i;
u64 mask;
@@ -92,7 +91,7 @@ nouveau_parent_lclass(struct nouveau_object *parent, u32 *lclass, int size)
mask = nv_parent(parent)->engine;
while (i = __ffs64(mask), mask) {
- engine = nouveau_engine(parent, i);
+ engine = nvkm_engine(parent, i);
if (engine && (oclass = engine->sclass)) {
while (oclass->ofuncs) {
if (++nr < size)
@@ -108,18 +107,17 @@ nouveau_parent_lclass(struct nouveau_object *parent, u32 *lclass, int size)
}
int
-nouveau_parent_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, u32 pclass,
- struct nouveau_oclass *sclass, u64 engcls,
- int size, void **pobject)
+nvkm_parent_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, u32 pclass,
+ struct nvkm_oclass *sclass, u64 engcls,
+ int size, void **pobject)
{
- struct nouveau_parent *object;
- struct nouveau_sclass *nclass;
+ struct nvkm_parent *object;
+ struct nvkm_sclass *nclass;
int ret;
- ret = nouveau_object_create_(parent, engine, oclass, pclass |
- NV_PARENT_CLASS, size, pobject);
+ ret = nvkm_object_create_(parent, engine, oclass, pclass |
+ NV_PARENT_CLASS, size, pobject);
object = *pobject;
if (ret)
return ret;
@@ -141,21 +139,21 @@ nouveau_parent_create_(struct nouveau_object *parent,
}
void
-nouveau_parent_destroy(struct nouveau_parent *parent)
+nvkm_parent_destroy(struct nvkm_parent *parent)
{
- struct nouveau_sclass *sclass;
+ struct nvkm_sclass *sclass;
while ((sclass = parent->sclass)) {
parent->sclass = sclass->sclass;
kfree(sclass);
}
- nouveau_object_destroy(&parent->object);
+ nvkm_object_destroy(&parent->object);
}
void
-_nouveau_parent_dtor(struct nouveau_object *object)
+_nvkm_parent_dtor(struct nvkm_object *object)
{
- nouveau_parent_destroy(nv_parent(object));
+ nvkm_parent_destroy(nv_parent(object));
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/printk.c b/drivers/gpu/drm/nouveau/nvkm/core/printk.c
index ed424f99f383..4a220eb91660 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/printk.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/printk.c
@@ -21,16 +21,14 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/object.h>
-#include <core/client.h>
-#include <core/subdev.h>
#include <core/printk.h>
+#include <core/client.h>
+#include <core/device.h>
int nv_info_debug_level = NV_DBG_INFO_NORMAL;
void
-nv_printk_(struct nouveau_object *object, int level, const char *fmt, ...)
+nv_printk_(struct nvkm_object *object, int level, const char *fmt, ...)
{
static const char name[] = { '!', 'E', 'W', ' ', 'D', 'T', 'P', 'S' };
const char *pfx;
@@ -60,8 +58,8 @@ nv_printk_(struct nouveau_object *object, int level, const char *fmt, ...)
}
if (object && !nv_iclass(object, NV_CLIENT_CLASS)) {
- struct nouveau_object *device;
- struct nouveau_object *subdev;
+ struct nvkm_object *device;
+ struct nvkm_object *subdev;
char obuf[64], *ofmt = "";
if (object->engine == NULL) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ramht.c b/drivers/gpu/drm/nouveau/nvkm/core/ramht.c
index 25cd6f29072b..0a382d0975b0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/ramht.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/ramht.c
@@ -19,14 +19,12 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
-
-#include <core/object.h>
#include <core/ramht.h>
#include <subdev/bar.h>
static u32
-nouveau_ramht_hash(struct nouveau_ramht *ramht, int chid, u32 handle)
+nvkm_ramht_hash(struct nvkm_ramht *ramht, int chid, u32 handle)
{
u32 hash = 0;
@@ -41,13 +39,12 @@ nouveau_ramht_hash(struct nouveau_ramht *ramht, int chid, u32 handle)
}
int
-nouveau_ramht_insert(struct nouveau_ramht *ramht, int chid,
- u32 handle, u32 context)
+nvkm_ramht_insert(struct nvkm_ramht *ramht, int chid, u32 handle, u32 context)
{
- struct nouveau_bar *bar = nouveau_bar(ramht);
+ struct nvkm_bar *bar = nvkm_bar(ramht);
u32 co, ho;
- co = ho = nouveau_ramht_hash(ramht, chid, handle);
+ co = ho = nvkm_ramht_hash(ramht, chid, handle);
do {
if (!nv_ro32(ramht, co + 4)) {
nv_wo32(ramht, co + 0, handle);
@@ -66,39 +63,39 @@ nouveau_ramht_insert(struct nouveau_ramht *ramht, int chid,
}
void
-nouveau_ramht_remove(struct nouveau_ramht *ramht, int cookie)
+nvkm_ramht_remove(struct nvkm_ramht *ramht, int cookie)
{
- struct nouveau_bar *bar = nouveau_bar(ramht);
+ struct nvkm_bar *bar = nvkm_bar(ramht);
nv_wo32(ramht, cookie + 0, 0x00000000);
nv_wo32(ramht, cookie + 4, 0x00000000);
if (bar)
bar->flush(bar);
}
-static struct nouveau_oclass
-nouveau_ramht_oclass = {
+static struct nvkm_oclass
+nvkm_ramht_oclass = {
.handle = 0x0000abcd,
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = NULL,
- .dtor = _nouveau_gpuobj_dtor,
- .init = _nouveau_gpuobj_init,
- .fini = _nouveau_gpuobj_fini,
- .rd32 = _nouveau_gpuobj_rd32,
- .wr32 = _nouveau_gpuobj_wr32,
+ .dtor = _nvkm_gpuobj_dtor,
+ .init = _nvkm_gpuobj_init,
+ .fini = _nvkm_gpuobj_fini,
+ .rd32 = _nvkm_gpuobj_rd32,
+ .wr32 = _nvkm_gpuobj_wr32,
},
};
int
-nouveau_ramht_new(struct nouveau_object *parent, struct nouveau_object *pargpu,
- u32 size, u32 align, struct nouveau_ramht **pramht)
+nvkm_ramht_new(struct nvkm_object *parent, struct nvkm_object *pargpu,
+ u32 size, u32 align, struct nvkm_ramht **pramht)
{
- struct nouveau_ramht *ramht;
+ struct nvkm_ramht *ramht;
int ret;
- ret = nouveau_gpuobj_create(parent, parent->engine ?
- &parent->engine->subdev.object : parent, /* <nv50 ramht */
- &nouveau_ramht_oclass, 0, pargpu, size,
- align, NVOBJ_FLAG_ZERO_ALLOC, &ramht);
+ ret = nvkm_gpuobj_create(parent, parent->engine ?
+ &parent->engine->subdev.object : parent, /* <nv50 ramht */
+ &nvkm_ramht_oclass, 0, pargpu, size,
+ align, NVOBJ_FLAG_ZERO_ALLOC, &ramht);
*pramht = ramht;
if (ret)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c
index cb1c49c2e9d6..c5fb3a793174 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c
@@ -21,16 +21,14 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/object.h>
#include <core/subdev.h>
#include <core/device.h>
#include <core/option.h>
-struct nouveau_subdev *
-nouveau_subdev(void *obj, int idx)
+struct nvkm_subdev *
+nvkm_subdev(void *obj, int idx)
{
- struct nouveau_object *object = nv_object(obj);
+ struct nvkm_object *object = nv_object(obj);
while (object && !nv_iclass(object, NV_SUBDEV_CLASS))
object = object->parent;
if (object == NULL || nv_subidx(nv_subdev(object)) != idx)
@@ -39,7 +37,7 @@ nouveau_subdev(void *obj, int idx)
}
void
-nouveau_subdev_reset(struct nouveau_object *subdev)
+nvkm_subdev_reset(struct nvkm_object *subdev)
{
nv_trace(subdev, "resetting...\n");
nv_ofuncs(subdev)->fini(subdev, false);
@@ -47,65 +45,64 @@ nouveau_subdev_reset(struct nouveau_object *subdev)
}
int
-nouveau_subdev_init(struct nouveau_subdev *subdev)
+nvkm_subdev_init(struct nvkm_subdev *subdev)
{
- int ret = nouveau_object_init(&subdev->object);
+ int ret = nvkm_object_init(&subdev->object);
if (ret)
return ret;
- nouveau_subdev_reset(&subdev->object);
+ nvkm_subdev_reset(&subdev->object);
return 0;
}
int
-_nouveau_subdev_init(struct nouveau_object *object)
+_nvkm_subdev_init(struct nvkm_object *object)
{
- return nouveau_subdev_init(nv_subdev(object));
+ return nvkm_subdev_init(nv_subdev(object));
}
int
-nouveau_subdev_fini(struct nouveau_subdev *subdev, bool suspend)
+nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend)
{
if (subdev->unit) {
nv_mask(subdev, 0x000200, subdev->unit, 0x00000000);
nv_mask(subdev, 0x000200, subdev->unit, subdev->unit);
}
- return nouveau_object_fini(&subdev->object, suspend);
+ return nvkm_object_fini(&subdev->object, suspend);
}
int
-_nouveau_subdev_fini(struct nouveau_object *object, bool suspend)
+_nvkm_subdev_fini(struct nvkm_object *object, bool suspend)
{
- return nouveau_subdev_fini(nv_subdev(object), suspend);
+ return nvkm_subdev_fini(nv_subdev(object), suspend);
}
void
-nouveau_subdev_destroy(struct nouveau_subdev *subdev)
+nvkm_subdev_destroy(struct nvkm_subdev *subdev)
{
int subidx = nv_hclass(subdev) & 0xff;
nv_device(subdev)->subdev[subidx] = NULL;
- nouveau_object_destroy(&subdev->object);
+ nvkm_object_destroy(&subdev->object);
}
void
-_nouveau_subdev_dtor(struct nouveau_object *object)
+_nvkm_subdev_dtor(struct nvkm_object *object)
{
- nouveau_subdev_destroy(nv_subdev(object));
+ nvkm_subdev_destroy(nv_subdev(object));
}
int
-nouveau_subdev_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, u32 pclass,
- const char *subname, const char *sysname,
- int size, void **pobject)
+nvkm_subdev_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, u32 pclass,
+ const char *subname, const char *sysname,
+ int size, void **pobject)
{
- struct nouveau_subdev *subdev;
+ struct nvkm_subdev *subdev;
int ret;
- ret = nouveau_object_create_(parent, engine, oclass, pclass |
- NV_SUBDEV_CLASS, size, pobject);
+ ret = nvkm_object_create_(parent, engine, oclass, pclass |
+ NV_SUBDEV_CLASS, size, pobject);
subdev = *pobject;
if (ret)
return ret;
@@ -114,8 +111,8 @@ nouveau_subdev_create_(struct nouveau_object *parent,
subdev->name = subname;
if (parent) {
- struct nouveau_device *device = nv_device(parent);
- subdev->debug = nouveau_dbgopt(device->dbgopt, subname);
+ struct nvkm_device *device = nv_device(parent);
+ subdev->debug = nvkm_dbgopt(device->dbgopt, subname);
subdev->mmio = nv_subdev(device)->mmio;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv84.c
index 1e8e75c0684a..649922d983ac 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv84.c
@@ -25,6 +25,8 @@
#include <engine/xtensa.h>
#include <engine/bsp.h>
+#include <core/engctx.h>
+
/*******************************************************************************
* BSP object classes
******************************************************************************/
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 60f538976f3b..ae2ad8b4e5df 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -22,6 +22,7 @@
* Authors: Ben Skeggs
*/
+#include <core/notify.h>
#include <core/object.h>
#include <core/device.h>
#include <core/client.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h
index a1bf359e53bd..4a92d9fa1d78 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h
@@ -1,8 +1,9 @@
#ifndef __NVKM_DISP_CONN_H__
#define __NVKM_DISP_CONN_H__
-
#include "priv.h"
+#include <core/notify.h>
+
struct nvkm_connector {
struct nouveau_object base;
struct list_head head;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h
index 1fac367cc867..74ef058ff051 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h
@@ -1,6 +1,7 @@
#ifndef __NVKM_DISP_OUTP_DP_H__
#define __NVKM_DISP_OUTP_DP_H__
+#include <core/notify.h>
#include <subdev/bios.h>
#include <subdev/bios/dp.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
index 2914646c8709..f6e9ae95c822 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
@@ -19,14 +19,14 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
-
#include <engine/falcon.h>
+
#include <subdev/timer.h>
void
-nouveau_falcon_intr(struct nouveau_subdev *subdev)
+nvkm_falcon_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_falcon *falcon = (void *)subdev;
+ struct nvkm_falcon *falcon = (void *)subdev;
u32 dispatch = nv_ro32(falcon, 0x01c);
u32 intr = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16);
@@ -43,16 +43,16 @@ nouveau_falcon_intr(struct nouveau_subdev *subdev)
}
u32
-_nouveau_falcon_rd32(struct nouveau_object *object, u64 addr)
+_nvkm_falcon_rd32(struct nvkm_object *object, u64 addr)
{
- struct nouveau_falcon *falcon = (void *)object;
+ struct nvkm_falcon *falcon = (void *)object;
return nv_rd32(falcon, falcon->addr + addr);
}
void
-_nouveau_falcon_wr32(struct nouveau_object *object, u64 addr, u32 data)
+_nvkm_falcon_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
- struct nouveau_falcon *falcon = (void *)object;
+ struct nvkm_falcon *falcon = (void *)object;
nv_wr32(falcon, falcon->addr + addr, data);
}
@@ -67,17 +67,17 @@ vmemdup(const void *src, size_t len)
}
int
-_nouveau_falcon_init(struct nouveau_object *object)
+_nvkm_falcon_init(struct nvkm_object *object)
{
- struct nouveau_device *device = nv_device(object);
- struct nouveau_falcon *falcon = (void *)object;
+ struct nvkm_device *device = nv_device(object);
+ struct nvkm_falcon *falcon = (void *)object;
const struct firmware *fw;
char name[32] = "internal";
int ret, i;
u32 caps;
/* enable engine, and determine its capabilities */
- ret = nouveau_engine_init(&falcon->base);
+ ret = nvkm_engine_init(&falcon->base);
if (ret)
return ret;
@@ -171,9 +171,8 @@ _nouveau_falcon_init(struct nouveau_object *object)
/* ensure any "self-bootstrapping" firmware image is in vram */
if (!falcon->data.data && !falcon->core) {
- ret = nouveau_gpuobj_new(object->parent, NULL,
- falcon->code.size, 256, 0,
- &falcon->core);
+ ret = nvkm_gpuobj_new(object->parent, NULL, falcon->code.size,
+ 256, 0, &falcon->core);
if (ret) {
nv_error(falcon, "core allocation failed, %d\n", ret);
return ret;
@@ -238,12 +237,12 @@ _nouveau_falcon_init(struct nouveau_object *object)
}
int
-_nouveau_falcon_fini(struct nouveau_object *object, bool suspend)
+_nvkm_falcon_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_falcon *falcon = (void *)object;
+ struct nvkm_falcon *falcon = (void *)object;
if (!suspend) {
- nouveau_gpuobj_ref(NULL, &falcon->core);
+ nvkm_gpuobj_ref(NULL, &falcon->core);
if (falcon->external) {
vfree(falcon->data.data);
vfree(falcon->code.data);
@@ -254,21 +253,20 @@ _nouveau_falcon_fini(struct nouveau_object *object, bool suspend)
nv_mo32(falcon, 0x048, 0x00000003, 0x00000000);
nv_wo32(falcon, 0x014, 0xffffffff);
- return nouveau_engine_fini(&falcon->base, suspend);
+ return nvkm_engine_fini(&falcon->base, suspend);
}
int
-nouveau_falcon_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, u32 addr, bool enable,
- const char *iname, const char *fname,
- int length, void **pobject)
+nvkm_falcon_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, u32 addr, bool enable,
+ const char *iname, const char *fname,
+ int length, void **pobject)
{
- struct nouveau_falcon *falcon;
+ struct nvkm_falcon *falcon;
int ret;
- ret = nouveau_engine_create_(parent, engine, oclass, enable, iname,
- fname, length, pobject);
+ ret = nvkm_engine_create_(parent, engine, oclass, enable, iname,
+ fname, length, pobject);
falcon = *pobject;
if (ret)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
index 836c6d32e82e..7e54a521bc05 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
@@ -23,6 +23,8 @@
*/
#include <core/client.h>
+#include <core/device.h>
+#include <core/notify.h>
#include <core/object.h>
#include <core/handle.h>
#include <core/event.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
index eb39af055bbb..a5cdb43524cb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
@@ -1,7 +1,7 @@
#ifndef __NV50_GR_H__
#define __NV50_GR_H__
+struct nvkm_device;
int nv50_grctx_init(struct nouveau_device *, u32 *size);
void nv50_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
index 618e41fa36d0..fa0a236004d6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
@@ -1,7 +1,7 @@
#ifndef __NVKM_SW_NV50_H__
#define __NVKM_SW_NV50_H__
-
#include <engine/sw.h>
+#include <core/notify.h>
struct nv50_sw_oclass {
struct nouveau_oclass base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/vp/nv84.c
index fd6272b8cdb2..9caa037b7a6b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/nv84.c
@@ -25,6 +25,8 @@
#include <engine/xtensa.h>
#include <engine/vp.h>
+#include <core/engctx.h>
+
/*******************************************************************************
* VP object classes
******************************************************************************/
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
index 92384759d2f5..3995d2cf0668 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
@@ -19,43 +19,42 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
-
#include <engine/xtensa.h>
+#include <core/engctx.h>
+
u32
-_nouveau_xtensa_rd32(struct nouveau_object *object, u64 addr)
+_nvkm_xtensa_rd32(struct nvkm_object *object, u64 addr)
{
- struct nouveau_xtensa *xtensa = (void *)object;
+ struct nvkm_xtensa *xtensa = (void *)object;
return nv_rd32(xtensa, xtensa->addr + addr);
}
void
-_nouveau_xtensa_wr32(struct nouveau_object *object, u64 addr, u32 data)
+_nvkm_xtensa_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
- struct nouveau_xtensa *xtensa = (void *)object;
+ struct nvkm_xtensa *xtensa = (void *)object;
nv_wr32(xtensa, xtensa->addr + addr, data);
}
int
-_nouveau_xtensa_engctx_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+_nvkm_xtensa_engctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_engctx *engctx;
+ struct nvkm_engctx *engctx;
int ret;
- ret = nouveau_engctx_create(parent, engine, oclass, NULL,
- 0x10000, 0x1000,
- NVOBJ_FLAG_ZERO_ALLOC, &engctx);
+ ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000, 0x1000,
+ NVOBJ_FLAG_ZERO_ALLOC, &engctx);
*pobject = nv_object(engctx);
return ret;
}
void
-_nouveau_xtensa_intr(struct nouveau_subdev *subdev)
+_nvkm_xtensa_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_xtensa *xtensa = (void *)subdev;
+ struct nvkm_xtensa *xtensa = (void *)subdev;
u32 unk104 = nv_ro32(xtensa, 0xd04);
u32 intr = nv_ro32(xtensa, 0xc20);
u32 chan = nv_ro32(xtensa, 0xc28);
@@ -72,39 +71,36 @@ _nouveau_xtensa_intr(struct nouveau_subdev *subdev)
}
int
-nouveau_xtensa_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, u32 addr, bool enable,
- const char *iname, const char *fname,
- int length, void **pobject)
+nvkm_xtensa_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, u32 addr, bool enable,
+ const char *iname, const char *fname,
+ int length, void **pobject)
{
- struct nouveau_xtensa *xtensa;
+ struct nvkm_xtensa *xtensa;
int ret;
- ret = nouveau_engine_create_(parent, engine, oclass, enable, iname,
- fname, length, pobject);
+ ret = nvkm_engine_create_(parent, engine, oclass, enable, iname,
+ fname, length, pobject);
xtensa = *pobject;
if (ret)
return ret;
- nv_subdev(xtensa)->intr = _nouveau_xtensa_intr;
-
+ nv_subdev(xtensa)->intr = _nvkm_xtensa_intr;
xtensa->addr = addr;
-
return 0;
}
int
-_nouveau_xtensa_init(struct nouveau_object *object)
+_nvkm_xtensa_init(struct nvkm_object *object)
{
- struct nouveau_device *device = nv_device(object);
- struct nouveau_xtensa *xtensa = (void *)object;
+ struct nvkm_device *device = nv_device(object);
+ struct nvkm_xtensa *xtensa = (void *)object;
const struct firmware *fw;
char name[32];
int i, ret;
u32 tmp;
- ret = nouveau_engine_init(&xtensa->base);
+ ret = nvkm_engine_init(&xtensa->base);
if (ret)
return ret;
@@ -124,8 +120,8 @@ _nouveau_xtensa_init(struct nouveau_object *object)
return -EINVAL;
}
- ret = nouveau_gpuobj_new(object, NULL, 0x40000, 0x1000, 0,
- &xtensa->gpu_fw);
+ ret = nvkm_gpuobj_new(object, NULL, 0x40000, 0x1000, 0,
+ &xtensa->gpu_fw);
if (ret) {
release_firmware(fw);
return ret;
@@ -157,20 +153,19 @@ _nouveau_xtensa_init(struct nouveau_object *object)
nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */
nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */
-
return 0;
}
int
-_nouveau_xtensa_fini(struct nouveau_object *object, bool suspend)
+_nvkm_xtensa_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_xtensa *xtensa = (void *)object;
+ struct nvkm_xtensa *xtensa = (void *)object;
nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */
nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */
if (!suspend)
- nouveau_gpuobj_ref(NULL, &xtensa->gpu_fw);
+ nvkm_gpuobj_ref(NULL, &xtensa->gpu_fw);
- return nouveau_engine_fini(&xtensa->base, suspend);
+ return nvkm_engine_fini(&xtensa->base, suspend);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
index 7ad99b763f4c..98d79298cb07 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
@@ -22,6 +22,7 @@
* Authors: Ben Skeggs
*/
+#include <core/notify.h>
#include <subdev/bios.h>
#include <subdev/bios/gpio.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
index d1f06e9aaca2..bd477cd8a919 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
@@ -22,6 +22,7 @@
* Authors: Ben Skeggs
*/
+#include <core/notify.h>
#include <core/option.h>
#include <core/object.h>
#include <core/event.h>
From 245dcfe96f6900dbf64e48a350badf4c90fabc2e Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 14:35:35 +1000
Subject: [PATCH 52/86] drm/nouveau/bar: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 2 +
.../gpu/drm/nouveau/include/nvkm/subdev/bar.h | 44 ++--
drivers/gpu/drm/nouveau/nvkm/core/ramht.c | 1 +
.../drm/nouveau/nvkm/engine/device/gm100.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 +-
.../gpu/drm/nouveau/nvkm/subdev/bar/Kbuild | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/bar/base.c | 95 ++++----
.../gpu/drm/nouveau/nvkm/subdev/bar/gf100.c | 218 +++++++++++++++++
.../gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c | 26 +-
.../gpu/drm/nouveau/nvkm/subdev/bar/nv50.c | 139 ++++++-----
.../gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c | 222 ------------------
.../gpu/drm/nouveau/nvkm/subdev/bar/priv.h | 42 ++--
13 files changed, 404 insertions(+), 423 deletions(-)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 0b5a1e4dff48..18e5edde08bd 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -137,6 +137,8 @@
#define nouveau_vm_put nvkm_vm_put
#define nouveau_vm_map nvkm_vm_map
#define nouveau_vm_unmap nvkm_vm_unmap
+#define nouveau_vm_new nvkm_vm_new
+#define nouveau_vm_ref nvkm_vm_ref
#define nouveau_instmem nvkm_instmem
#define nouveau_instobj nvkm_instobj
#define nouveau_mem nvkm_mem
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
index 960e33a30819..c7a007b8bc10 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
@@ -1,37 +1,33 @@
-#ifndef __NOUVEAU_BAR_H__
-#define __NOUVEAU_BAR_H__
-
+#ifndef __NVKM_BAR_H__
+#define __NVKM_BAR_H__
#include <core/subdev.h>
-#include <core/device.h>
+struct nvkm_mem;
+struct nvkm_vma;
-struct nouveau_mem;
-struct nouveau_vma;
+struct nvkm_bar {
+ struct nvkm_subdev base;
-struct nouveau_bar {
- struct nouveau_subdev base;
+ int (*alloc)(struct nvkm_bar *, struct nvkm_object *,
+ struct nvkm_mem *, struct nvkm_object **);
- int (*alloc)(struct nouveau_bar *, struct nouveau_object *,
- struct nouveau_mem *, struct nouveau_object **);
-
- int (*kmap)(struct nouveau_bar *, struct nouveau_mem *,
- u32 flags, struct nouveau_vma *);
- int (*umap)(struct nouveau_bar *, struct nouveau_mem *,
- u32 flags, struct nouveau_vma *);
- void (*unmap)(struct nouveau_bar *, struct nouveau_vma *);
- void (*flush)(struct nouveau_bar *);
+ int (*kmap)(struct nvkm_bar *, struct nvkm_mem *, u32 flags,
+ struct nvkm_vma *);
+ int (*umap)(struct nvkm_bar *, struct nvkm_mem *, u32 flags,
+ struct nvkm_vma *);
+ void (*unmap)(struct nvkm_bar *, struct nvkm_vma *);
+ void (*flush)(struct nvkm_bar *);
/* whether the BAR supports to be ioremapped WC or should be uncached */
bool iomap_uncached;
};
-static inline struct nouveau_bar *
-nouveau_bar(void *obj)
+static inline struct nvkm_bar *
+nvkm_bar(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_BAR);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BAR);
}
-extern struct nouveau_oclass nv50_bar_oclass;
-extern struct nouveau_oclass nvc0_bar_oclass;
-extern struct nouveau_oclass gk20a_bar_oclass;
-
+extern struct nvkm_oclass nv50_bar_oclass;
+extern struct nvkm_oclass gf100_bar_oclass;
+extern struct nvkm_oclass gk20a_bar_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ramht.c b/drivers/gpu/drm/nouveau/nvkm/core/ramht.c
index 0a382d0975b0..ebd4d15479bd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/ramht.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/ramht.c
@@ -20,6 +20,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <core/ramht.h>
+#include <core/engine.h>
#include <subdev/bar.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 915ba957f075..29dbe1693480 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -77,7 +77,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
#if 0
@@ -121,7 +121,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 2a6fc7f6fd85..5e4608fba660 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -77,7 +77,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
@@ -110,7 +110,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
@@ -143,7 +143,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
@@ -175,7 +175,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
@@ -208,7 +208,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
@@ -240,7 +240,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
@@ -272,7 +272,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
@@ -305,7 +305,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
@@ -337,7 +337,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index b2225ec499b1..a488b30304cf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -77,7 +77,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
@@ -111,7 +111,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
@@ -145,7 +145,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
@@ -201,7 +201,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
@@ -235,7 +235,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
@@ -269,7 +269,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
@@ -302,7 +302,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
+ device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild
index 922454f97de2..1ab554a0b5e0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild
@@ -1,4 +1,4 @@
nvkm-y += nvkm/subdev/bar/base.o
nvkm-y += nvkm/subdev/bar/nv50.o
-nvkm-y += nvkm/subdev/bar/nvc0.o
+nvkm-y += nvkm/subdev/bar/gf100.o
nvkm-y += nvkm/subdev/bar/gk20a.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
index 1b37afe4a4ea..3502d00122ef 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
@@ -21,33 +21,30 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
-#include <core/object.h>
-
+#include <core/device.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>
-#include "priv.h"
-
-struct nouveau_barobj {
- struct nouveau_object base;
- struct nouveau_vma vma;
+struct nvkm_barobj {
+ struct nvkm_object base;
+ struct nvkm_vma vma;
void __iomem *iomem;
};
static int
-nouveau_barobj_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nvkm_barobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_device *device = nv_device(parent);
- struct nouveau_bar *bar = nouveau_bar(device);
- struct nouveau_mem *mem = data;
- struct nouveau_barobj *barobj;
+ struct nvkm_device *device = nv_device(parent);
+ struct nvkm_bar *bar = nvkm_bar(device);
+ struct nvkm_mem *mem = data;
+ struct nvkm_barobj *barobj;
int ret;
- ret = nouveau_object_create(parent, engine, oclass, 0, &barobj);
+ ret = nvkm_object_create(parent, engine, oclass, 0, &barobj);
*pobject = nv_object(barobj);
if (ret)
return ret;
@@ -67,67 +64,65 @@ nouveau_barobj_ctor(struct nouveau_object *parent,
}
static void
-nouveau_barobj_dtor(struct nouveau_object *object)
+nvkm_barobj_dtor(struct nvkm_object *object)
{
- struct nouveau_bar *bar = nouveau_bar(object);
- struct nouveau_barobj *barobj = (void *)object;
+ struct nvkm_bar *bar = nvkm_bar(object);
+ struct nvkm_barobj *barobj = (void *)object;
if (barobj->vma.node) {
if (barobj->iomem)
iounmap(barobj->iomem);
bar->unmap(bar, &barobj->vma);
}
- nouveau_object_destroy(&barobj->base);
+ nvkm_object_destroy(&barobj->base);
}
static u32
-nouveau_barobj_rd32(struct nouveau_object *object, u64 addr)
+nvkm_barobj_rd32(struct nvkm_object *object, u64 addr)
{
- struct nouveau_barobj *barobj = (void *)object;
+ struct nvkm_barobj *barobj = (void *)object;
return ioread32_native(barobj->iomem + addr);
}
static void
-nouveau_barobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
+nvkm_barobj_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
- struct nouveau_barobj *barobj = (void *)object;
+ struct nvkm_barobj *barobj = (void *)object;
iowrite32_native(data, barobj->iomem + addr);
}
-static struct nouveau_oclass
-nouveau_barobj_oclass = {
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nouveau_barobj_ctor,
- .dtor = nouveau_barobj_dtor,
- .init = nouveau_object_init,
- .fini = nouveau_object_fini,
- .rd32 = nouveau_barobj_rd32,
- .wr32 = nouveau_barobj_wr32,
+static struct nvkm_oclass
+nvkm_barobj_oclass = {
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = nvkm_barobj_ctor,
+ .dtor = nvkm_barobj_dtor,
+ .init = nvkm_object_init,
+ .fini = nvkm_object_fini,
+ .rd32 = nvkm_barobj_rd32,
+ .wr32 = nvkm_barobj_wr32,
},
};
int
-nouveau_bar_alloc(struct nouveau_bar *bar, struct nouveau_object *parent,
- struct nouveau_mem *mem, struct nouveau_object **pobject)
+nvkm_bar_alloc(struct nvkm_bar *bar, struct nvkm_object *parent,
+ struct nvkm_mem *mem, struct nvkm_object **pobject)
{
- struct nouveau_object *gpuobj;
- int ret = nouveau_object_ctor(parent, &parent->engine->subdev.object,
- &nouveau_barobj_oclass,
- mem, 0, &gpuobj);
+ struct nvkm_object *gpuobj;
+ int ret = nvkm_object_ctor(parent, &parent->engine->subdev.object,
+ &nvkm_barobj_oclass, mem, 0, &gpuobj);
if (ret == 0)
*pobject = gpuobj;
return ret;
}
int
-nouveau_bar_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int length, void **pobject)
+nvkm_bar_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
- struct nouveau_bar *bar;
+ struct nvkm_bar *bar;
int ret;
- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "BARCTL",
- "bar", length, pobject);
+ ret = nvkm_subdev_create_(parent, engine, oclass, 0, "BARCTL",
+ "bar", length, pobject);
bar = *pobject;
if (ret)
return ret;
@@ -136,14 +131,14 @@ nouveau_bar_create_(struct nouveau_object *parent,
}
void
-nouveau_bar_destroy(struct nouveau_bar *bar)
+nvkm_bar_destroy(struct nvkm_bar *bar)
{
- nouveau_subdev_destroy(&bar->base);
+ nvkm_subdev_destroy(&bar->base);
}
void
-_nouveau_bar_dtor(struct nouveau_object *object)
+_nvkm_bar_dtor(struct nvkm_object *object)
{
- struct nouveau_bar *bar = (void *)object;
- nouveau_bar_destroy(bar);
+ struct nvkm_bar *bar = (void *)object;
+ nvkm_bar_destroy(bar);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
new file mode 100644
index 000000000000..4c6d238dd3da
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+#include "priv.h"
+
+#include <core/gpuobj.h>
+#include <subdev/fb.h>
+#include <subdev/mmu.h>
+
+struct gf100_bar_priv_vm {
+ struct nvkm_gpuobj *mem;
+ struct nvkm_gpuobj *pgd;
+ struct nvkm_vm *vm;
+};
+
+struct gf100_bar_priv {
+ struct nvkm_bar base;
+ spinlock_t lock;
+ struct gf100_bar_priv_vm bar[2];
+};
+
+static int
+gf100_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
+ struct nvkm_vma *vma)
+{
+ struct gf100_bar_priv *priv = (void *)bar;
+ int ret;
+
+ ret = nvkm_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma);
+ if (ret)
+ return ret;
+
+ nvkm_vm_map(vma, mem);
+ return 0;
+}
+
+static int
+gf100_bar_umap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
+ struct nvkm_vma *vma)
+{
+ struct gf100_bar_priv *priv = (void *)bar;
+ int ret;
+
+ ret = nvkm_vm_get(priv->bar[1].vm, mem->size << 12,
+ mem->page_shift, flags, vma);
+ if (ret)
+ return ret;
+
+ nvkm_vm_map(vma, mem);
+ return 0;
+}
+
+static void
+gf100_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma)
+{
+ nvkm_vm_unmap(vma);
+ nvkm_vm_put(vma);
+}
+
+static int
+gf100_bar_ctor_vm(struct gf100_bar_priv *priv, struct gf100_bar_priv_vm *bar_vm,
+ int bar_nr)
+{
+ struct nvkm_device *device = nv_device(&priv->base);
+ struct nvkm_vm *vm;
+ resource_size_t bar_len;
+ int ret;
+
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
+ &bar_vm->mem);
+ if (ret)
+ return ret;
+
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
+ &bar_vm->pgd);
+ if (ret)
+ return ret;
+
+ bar_len = nv_device_resource_len(device, bar_nr);
+
+ ret = nvkm_vm_new(device, 0, bar_len, 0, &vm);
+ if (ret)
+ return ret;
+
+ atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
+
+ /*
+ * Bootstrap page table lookup.
+ */
+ if (bar_nr == 3) {
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL,
+ (bar_len >> 12) * 8, 0x1000,
+ NVOBJ_FLAG_ZERO_ALLOC,
+ &vm->pgt[0].obj[0]);
+ vm->pgt[0].refcount[0] = 1;
+ if (ret)
+ return ret;
+ }
+
+ ret = nvkm_vm_ref(vm, &bar_vm->vm, bar_vm->pgd);
+ nvkm_vm_ref(NULL, &vm, NULL);
+ if (ret)
+ return ret;
+
+ nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr));
+ nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr));
+ nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1));
+ nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1));
+ return 0;
+}
+
+int
+gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
+{
+ struct nvkm_device *device = nv_device(parent);
+ struct gf100_bar_priv *priv;
+ bool has_bar3 = nv_device_resource_len(device, 3) != 0;
+ int ret;
+
+ ret = nvkm_bar_create(parent, engine, oclass, &priv);
+ *pobject = nv_object(priv);
+ if (ret)
+ return ret;
+
+ /* BAR3 */
+ if (has_bar3) {
+ ret = gf100_bar_ctor_vm(priv, &priv->bar[0], 3);
+ if (ret)
+ return ret;
+ }
+
+ /* BAR1 */
+ ret = gf100_bar_ctor_vm(priv, &priv->bar[1], 1);
+ if (ret)
+ return ret;
+
+ if (has_bar3) {
+ priv->base.alloc = nvkm_bar_alloc;
+ priv->base.kmap = gf100_bar_kmap;
+ }
+ priv->base.umap = gf100_bar_umap;
+ priv->base.unmap = gf100_bar_unmap;
+ priv->base.flush = g84_bar_flush;
+ spin_lock_init(&priv->lock);
+ return 0;
+}
+
+void
+gf100_bar_dtor(struct nvkm_object *object)
+{
+ struct gf100_bar_priv *priv = (void *)object;
+
+ nvkm_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd);
+ nvkm_gpuobj_ref(NULL, &priv->bar[1].pgd);
+ nvkm_gpuobj_ref(NULL, &priv->bar[1].mem);
+
+ if (priv->bar[0].vm) {
+ nvkm_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
+ nvkm_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd);
+ }
+ nvkm_gpuobj_ref(NULL, &priv->bar[0].pgd);
+ nvkm_gpuobj_ref(NULL, &priv->bar[0].mem);
+
+ nvkm_bar_destroy(&priv->base);
+}
+
+int
+gf100_bar_init(struct nvkm_object *object)
+{
+ struct gf100_bar_priv *priv = (void *)object;
+ int ret;
+
+ ret = nvkm_bar_init(&priv->base);
+ if (ret)
+ return ret;
+
+ nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
+ nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
+
+ nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12);
+ if (priv->bar[0].mem)
+ nv_wr32(priv, 0x001714,
+ 0xc0000000 | priv->bar[0].mem->addr >> 12);
+ return 0;
+}
+
+struct nvkm_oclass
+gf100_bar_oclass = {
+ .handle = NV_SUBDEV(BAR, 0xc0),
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_bar_ctor,
+ .dtor = gf100_bar_dtor,
+ .init = gf100_bar_init,
+ .fini = _nvkm_bar_fini,
+ },
+};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c
index bf877af9d3bd..148f739a276e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c
@@ -19,36 +19,32 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
-
-#include <subdev/bar.h>
-
#include "priv.h"
int
-gk20a_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk20a_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_bar *bar;
+ struct nvkm_bar *bar;
int ret;
- ret = nvc0_bar_ctor(parent, engine, oclass, data, size, pobject);
+ ret = gf100_bar_ctor(parent, engine, oclass, data, size, pobject);
if (ret)
return ret;
- bar = (struct nouveau_bar *)*pobject;
+ bar = (struct nvkm_bar *)*pobject;
bar->iomap_uncached = true;
-
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
gk20a_bar_oclass = {
.handle = NV_SUBDEV(BAR, 0xea),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_bar_ctor,
- .dtor = nvc0_bar_dtor,
- .init = nvc0_bar_init,
- .fini = _nouveau_bar_fini,
+ .dtor = gf100_bar_dtor,
+ .init = gf100_bar_init,
+ .fini = _nvkm_bar_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
index 6d0dd6a01e64..36c5c083c1e9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
@@ -21,66 +21,64 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/gpuobj.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/mmu.h>
-
#include "priv.h"
+#include <core/gpuobj.h>
+#include <subdev/fb.h>
+#include <subdev/mmu.h>
+#include <subdev/timer.h>
+
struct nv50_bar_priv {
- struct nouveau_bar base;
+ struct nvkm_bar base;
spinlock_t lock;
- struct nouveau_gpuobj *mem;
- struct nouveau_gpuobj *pad;
- struct nouveau_gpuobj *pgd;
- struct nouveau_vm *bar1_vm;
- struct nouveau_gpuobj *bar1;
- struct nouveau_vm *bar3_vm;
- struct nouveau_gpuobj *bar3;
+ struct nvkm_gpuobj *mem;
+ struct nvkm_gpuobj *pad;
+ struct nvkm_gpuobj *pgd;
+ struct nvkm_vm *bar1_vm;
+ struct nvkm_gpuobj *bar1;
+ struct nvkm_vm *bar3_vm;
+ struct nvkm_gpuobj *bar3;
};
static int
-nv50_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
- u32 flags, struct nouveau_vma *vma)
+nv50_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
+ struct nvkm_vma *vma)
{
struct nv50_bar_priv *priv = (void *)bar;
int ret;
- ret = nouveau_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma);
+ ret = nvkm_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma);
if (ret)
return ret;
- nouveau_vm_map(vma, mem);
+ nvkm_vm_map(vma, mem);
return 0;
}
static int
-nv50_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
- u32 flags, struct nouveau_vma *vma)
+nv50_bar_umap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
+ struct nvkm_vma *vma)
{
struct nv50_bar_priv *priv = (void *)bar;
int ret;
- ret = nouveau_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma);
+ ret = nvkm_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma);
if (ret)
return ret;
- nouveau_vm_map(vma, mem);
+ nvkm_vm_map(vma, mem);
return 0;
}
static void
-nv50_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
+nv50_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma)
{
- nouveau_vm_unmap(vma);
- nouveau_vm_put(vma);
+ nvkm_vm_unmap(vma);
+ nvkm_vm_put(vma);
}
static void
-nv50_bar_flush(struct nouveau_bar *bar)
+nv50_bar_flush(struct nvkm_bar *bar)
{
struct nv50_bar_priv *priv = (void *)bar;
unsigned long flags;
@@ -92,7 +90,7 @@ nv50_bar_flush(struct nouveau_bar *bar)
}
void
-nv84_bar_flush(struct nouveau_bar *bar)
+g84_bar_flush(struct nvkm_bar *bar)
{
struct nv50_bar_priv *priv = (void *)bar;
unsigned long flags;
@@ -104,36 +102,35 @@ nv84_bar_flush(struct nouveau_bar *bar)
}
static int
-nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_device *device = nv_device(parent);
- struct nouveau_object *heap;
- struct nouveau_vm *vm;
+ struct nvkm_device *device = nv_device(parent);
+ struct nvkm_object *heap;
+ struct nvkm_vm *vm;
struct nv50_bar_priv *priv;
u64 start, limit;
int ret;
- ret = nouveau_bar_create(parent, engine, oclass, &priv);
+ ret = nvkm_bar_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x20000, 0,
- NVOBJ_FLAG_HEAP, &priv->mem);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x20000, 0,
+ NVOBJ_FLAG_HEAP, &priv->mem);
heap = nv_object(priv->mem);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), heap,
- (device->chipset == 0x50) ? 0x1400 : 0x0200,
- 0, 0, &priv->pad);
+ ret = nvkm_gpuobj_new(nv_object(priv), heap,
+ (device->chipset == 0x50) ? 0x1400 : 0x0200,
+ 0, 0, &priv->pad);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), heap, 0x4000, 0,
- 0, &priv->pgd);
+ ret = nvkm_gpuobj_new(nv_object(priv), heap, 0x4000, 0, 0, &priv->pgd);
if (ret)
return ret;
@@ -141,25 +138,25 @@ nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
start = 0x0100000000ULL;
limit = start + nv_device_resource_len(device, 3);
- ret = nouveau_vm_new(device, start, limit, start, &vm);
+ ret = nvkm_vm_new(device, start, limit, start, &vm);
if (ret)
return ret;
atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
- ret = nouveau_gpuobj_new(nv_object(priv), heap,
- ((limit-- - start) >> 12) * 8, 0x1000,
- NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]);
+ ret = nvkm_gpuobj_new(nv_object(priv), heap,
+ ((limit-- - start) >> 12) * 8, 0x1000,
+ NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]);
vm->pgt[0].refcount[0] = 1;
if (ret)
return ret;
- ret = nouveau_vm_ref(vm, &priv->bar3_vm, priv->pgd);
- nouveau_vm_ref(NULL, &vm, NULL);
+ ret = nvkm_vm_ref(vm, &priv->bar3_vm, priv->pgd);
+ nvkm_vm_ref(NULL, &vm, NULL);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3);
+ ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3);
if (ret)
return ret;
@@ -175,18 +172,18 @@ nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
start = 0x0000000000ULL;
limit = start + nv_device_resource_len(device, 1);
- ret = nouveau_vm_new(device, start, limit--, start, &vm);
+ ret = nvkm_vm_new(device, start, limit--, start, &vm);
if (ret)
return ret;
atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
- ret = nouveau_vm_ref(vm, &priv->bar1_vm, priv->pgd);
- nouveau_vm_ref(NULL, &vm, NULL);
+ ret = nvkm_vm_ref(vm, &priv->bar1_vm, priv->pgd);
+ nvkm_vm_ref(NULL, &vm, NULL);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1);
+ ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1);
if (ret)
return ret;
@@ -198,42 +195,42 @@ nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
nv_wo32(priv->bar1, 0x10, 0x00000000);
nv_wo32(priv->bar1, 0x14, 0x00000000);
- priv->base.alloc = nouveau_bar_alloc;
+ priv->base.alloc = nvkm_bar_alloc;
priv->base.kmap = nv50_bar_kmap;
priv->base.umap = nv50_bar_umap;
priv->base.unmap = nv50_bar_unmap;
if (device->chipset == 0x50)
priv->base.flush = nv50_bar_flush;
else
- priv->base.flush = nv84_bar_flush;
+ priv->base.flush = g84_bar_flush;
spin_lock_init(&priv->lock);
return 0;
}
static void
-nv50_bar_dtor(struct nouveau_object *object)
+nv50_bar_dtor(struct nvkm_object *object)
{
struct nv50_bar_priv *priv = (void *)object;
- nouveau_gpuobj_ref(NULL, &priv->bar1);
- nouveau_vm_ref(NULL, &priv->bar1_vm, priv->pgd);
- nouveau_gpuobj_ref(NULL, &priv->bar3);
+ nvkm_gpuobj_ref(NULL, &priv->bar1);
+ nvkm_vm_ref(NULL, &priv->bar1_vm, priv->pgd);
+ nvkm_gpuobj_ref(NULL, &priv->bar3);
if (priv->bar3_vm) {
- nouveau_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]);
- nouveau_vm_ref(NULL, &priv->bar3_vm, priv->pgd);
+ nvkm_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]);
+ nvkm_vm_ref(NULL, &priv->bar3_vm, priv->pgd);
}
- nouveau_gpuobj_ref(NULL, &priv->pgd);
- nouveau_gpuobj_ref(NULL, &priv->pad);
- nouveau_gpuobj_ref(NULL, &priv->mem);
- nouveau_bar_destroy(&priv->base);
+ nvkm_gpuobj_ref(NULL, &priv->pgd);
+ nvkm_gpuobj_ref(NULL, &priv->pad);
+ nvkm_gpuobj_ref(NULL, &priv->mem);
+ nvkm_bar_destroy(&priv->base);
}
static int
-nv50_bar_init(struct nouveau_object *object)
+nv50_bar_init(struct nvkm_object *object)
{
struct nv50_bar_priv *priv = (void *)object;
int ret, i;
- ret = nouveau_bar_init(&priv->base);
+ ret = nvkm_bar_init(&priv->base);
if (ret)
return ret;
@@ -255,16 +252,16 @@ nv50_bar_init(struct nouveau_object *object)
}
static int
-nv50_bar_fini(struct nouveau_object *object, bool suspend)
+nv50_bar_fini(struct nvkm_object *object, bool suspend)
{
struct nv50_bar_priv *priv = (void *)object;
- return nouveau_bar_fini(&priv->base, suspend);
+ return nvkm_bar_fini(&priv->base, suspend);
}
-struct nouveau_oclass
+struct nvkm_oclass
nv50_bar_oclass = {
.handle = NV_SUBDEV(BAR, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_bar_ctor,
.dtor = nv50_bar_dtor,
.init = nv50_bar_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c
deleted file mode 100644
index c7ac57ba8e35..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/gpuobj.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/mmu.h>
-
-#include "priv.h"
-
-struct nvc0_bar_priv_vm {
- struct nouveau_gpuobj *mem;
- struct nouveau_gpuobj *pgd;
- struct nouveau_vm *vm;
-};
-
-struct nvc0_bar_priv {
- struct nouveau_bar base;
- spinlock_t lock;
- struct nvc0_bar_priv_vm bar[2];
-};
-
-static int
-nvc0_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
- u32 flags, struct nouveau_vma *vma)
-{
- struct nvc0_bar_priv *priv = (void *)bar;
- int ret;
-
- ret = nouveau_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma);
- if (ret)
- return ret;
-
- nouveau_vm_map(vma, mem);
- return 0;
-}
-
-static int
-nvc0_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
- u32 flags, struct nouveau_vma *vma)
-{
- struct nvc0_bar_priv *priv = (void *)bar;
- int ret;
-
- ret = nouveau_vm_get(priv->bar[1].vm, mem->size << 12,
- mem->page_shift, flags, vma);
- if (ret)
- return ret;
-
- nouveau_vm_map(vma, mem);
- return 0;
-}
-
-static void
-nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
-{
- nouveau_vm_unmap(vma);
- nouveau_vm_put(vma);
-}
-
-static int
-nvc0_bar_init_vm(struct nvc0_bar_priv *priv, struct nvc0_bar_priv_vm *bar_vm,
- int bar_nr)
-{
- struct nouveau_device *device = nv_device(&priv->base);
- struct nouveau_vm *vm;
- resource_size_t bar_len;
- int ret;
-
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
- &bar_vm->mem);
- if (ret)
- return ret;
-
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
- &bar_vm->pgd);
- if (ret)
- return ret;
-
- bar_len = nv_device_resource_len(device, bar_nr);
-
- ret = nouveau_vm_new(device, 0, bar_len, 0, &vm);
- if (ret)
- return ret;
-
- atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
-
- /*
- * Bootstrap page table lookup.
- */
- if (bar_nr == 3) {
- ret = nouveau_gpuobj_new(nv_object(priv), NULL,
- (bar_len >> 12) * 8, 0x1000,
- NVOBJ_FLAG_ZERO_ALLOC,
- &vm->pgt[0].obj[0]);
- vm->pgt[0].refcount[0] = 1;
- if (ret)
- return ret;
- }
-
- ret = nouveau_vm_ref(vm, &bar_vm->vm, bar_vm->pgd);
- nouveau_vm_ref(NULL, &vm, NULL);
- if (ret)
- return ret;
-
- nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr));
- nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr));
- nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1));
- nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1));
-
- return 0;
-}
-
-int
-nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
-{
- struct nouveau_device *device = nv_device(parent);
- struct nvc0_bar_priv *priv;
- bool has_bar3 = nv_device_resource_len(device, 3) != 0;
- int ret;
-
- ret = nouveau_bar_create(parent, engine, oclass, &priv);
- *pobject = nv_object(priv);
- if (ret)
- return ret;
-
- /* BAR3 */
- if (has_bar3) {
- ret = nvc0_bar_init_vm(priv, &priv->bar[0], 3);
- if (ret)
- return ret;
- }
-
- /* BAR1 */
- ret = nvc0_bar_init_vm(priv, &priv->bar[1], 1);
- if (ret)
- return ret;
-
- if (has_bar3) {
- priv->base.alloc = nouveau_bar_alloc;
- priv->base.kmap = nvc0_bar_kmap;
- }
- priv->base.umap = nvc0_bar_umap;
- priv->base.unmap = nvc0_bar_unmap;
- priv->base.flush = nv84_bar_flush;
- spin_lock_init(&priv->lock);
- return 0;
-}
-
-void
-nvc0_bar_dtor(struct nouveau_object *object)
-{
- struct nvc0_bar_priv *priv = (void *)object;
-
- nouveau_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd);
- nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd);
- nouveau_gpuobj_ref(NULL, &priv->bar[1].mem);
-
- if (priv->bar[0].vm) {
- nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
- nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd);
- }
- nouveau_gpuobj_ref(NULL, &priv->bar[0].pgd);
- nouveau_gpuobj_ref(NULL, &priv->bar[0].mem);
-
- nouveau_bar_destroy(&priv->base);
-}
-
-int
-nvc0_bar_init(struct nouveau_object *object)
-{
- struct nvc0_bar_priv *priv = (void *)object;
- int ret;
-
- ret = nouveau_bar_init(&priv->base);
- if (ret)
- return ret;
-
- nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
- nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
-
- nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12);
- if (priv->bar[0].mem)
- nv_wr32(priv, 0x001714,
- 0xc0000000 | priv->bar[0].mem->addr >> 12);
- return 0;
-}
-
-struct nouveau_oclass
-nvc0_bar_oclass = {
- .handle = NV_SUBDEV(BAR, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_bar_ctor,
- .dtor = nvc0_bar_dtor,
- .init = nvc0_bar_init,
- .fini = _nouveau_bar_fini,
- },
-};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h
index 3ee8b1476d00..aa85f61b48c2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h
@@ -1,32 +1,30 @@
#ifndef __NVKM_BAR_PRIV_H__
#define __NVKM_BAR_PRIV_H__
-
#include <subdev/bar.h>
-#define nouveau_bar_create(p,e,o,d) \
- nouveau_bar_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_bar_init(p) \
- nouveau_subdev_init(&(p)->base)
-#define nouveau_bar_fini(p,s) \
- nouveau_subdev_fini(&(p)->base, (s))
+#define nvkm_bar_create(p,e,o,d) \
+ nvkm_bar_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_bar_init(p) \
+ nvkm_subdev_init(&(p)->base)
+#define nvkm_bar_fini(p,s) \
+ nvkm_subdev_fini(&(p)->base, (s))
-int nouveau_bar_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-void nouveau_bar_destroy(struct nouveau_bar *);
+int nvkm_bar_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+void nvkm_bar_destroy(struct nvkm_bar *);
-void _nouveau_bar_dtor(struct nouveau_object *);
-#define _nouveau_bar_init _nouveau_subdev_init
-#define _nouveau_bar_fini _nouveau_subdev_fini
+void _nvkm_bar_dtor(struct nvkm_object *);
+#define _nvkm_bar_init _nvkm_subdev_init
+#define _nvkm_bar_fini _nvkm_subdev_fini
-int nouveau_bar_alloc(struct nouveau_bar *, struct nouveau_object *,
- struct nouveau_mem *, struct nouveau_object **);
+int nvkm_bar_alloc(struct nvkm_bar *, struct nvkm_object *,
+ struct nvkm_mem *, struct nvkm_object **);
-void nv84_bar_flush(struct nouveau_bar *);
-
-int nvc0_bar_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nvc0_bar_dtor(struct nouveau_object *);
-int nvc0_bar_init(struct nouveau_object *);
+void g84_bar_flush(struct nvkm_bar *);
+int gf100_bar_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void gf100_bar_dtor(struct nvkm_object *);
+int gf100_bar_init(struct nvkm_object *);
#endif
From d390b48027f886c9b8c60a4578044958f517047d Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 14:40:03 +1000
Subject: [PATCH 53/86] drm/nouveau/bios: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 8 +
.../drm/nouveau/include/nvkm/subdev/bios.h | 19 +-
.../nouveau/include/nvkm/subdev/bios/M0203.h | 12 +-
.../nouveau/include/nvkm/subdev/bios/M0205.h | 17 +-
.../nouveau/include/nvkm/subdev/bios/M0209.h | 15 +-
.../nouveau/include/nvkm/subdev/bios/P0260.h | 12 +-
.../nouveau/include/nvkm/subdev/bios/bit.h | 4 +-
.../nouveau/include/nvkm/subdev/bios/bmp.h | 10 +-
.../nouveau/include/nvkm/subdev/bios/boost.h | 14 +-
.../nouveau/include/nvkm/subdev/bios/conn.h | 10 +-
.../nouveau/include/nvkm/subdev/bios/cstep.h | 14 +-
.../nouveau/include/nvkm/subdev/bios/dcb.h | 16 +-
.../nouveau/include/nvkm/subdev/bios/disp.h | 37 ++--
.../drm/nouveau/include/nvkm/subdev/bios/dp.h | 16 +-
.../nouveau/include/nvkm/subdev/bios/extdev.h | 9 +-
.../nouveau/include/nvkm/subdev/bios/fan.h | 4 +-
.../nouveau/include/nvkm/subdev/bios/gpio.h | 10 +-
.../nouveau/include/nvkm/subdev/bios/i2c.h | 10 +-
.../nouveau/include/nvkm/subdev/bios/image.h | 4 +-
.../nouveau/include/nvkm/subdev/bios/init.h | 8 +-
.../nouveau/include/nvkm/subdev/bios/mxm.h | 9 +-
.../nouveau/include/nvkm/subdev/bios/npde.h | 6 +-
.../nouveau/include/nvkm/subdev/bios/pcir.h | 6 +-
.../nouveau/include/nvkm/subdev/bios/perf.h | 18 +-
.../nouveau/include/nvkm/subdev/bios/pll.h | 10 +-
.../nouveau/include/nvkm/subdev/bios/pmu.h | 12 +-
.../nouveau/include/nvkm/subdev/bios/ramcfg.h | 8 +-
.../nouveau/include/nvkm/subdev/bios/rammap.h | 25 +--
.../nouveau/include/nvkm/subdev/bios/therm.h | 15 +-
.../nouveau/include/nvkm/subdev/bios/timing.h | 13 +-
.../nouveau/include/nvkm/subdev/bios/vmap.h | 12 +-
.../nouveau/include/nvkm/subdev/bios/volt.h | 12 +-
.../nouveau/include/nvkm/subdev/bios/xpio.h | 5 +-
.../gpu/drm/nouveau/include/nvkm/subdev/fb.h | 1 +
.../gpu/drm/nouveau/nvkm/subdev/bios/M0203.c | 11 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/M0205.c | 13 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/M0209.c | 14 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/P0260.c | 12 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/base.c | 91 ++++-----
.../gpu/drm/nouveau/nvkm/subdev/bios/bit.c | 9 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/boost.c | 13 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/conn.c | 11 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/cstep.c | 13 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/dcb.c | 21 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/disp.c | 35 ++--
drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c | 22 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/extdev.c | 15 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/fan.c | 8 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/gpio.c | 10 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/i2c.c | 14 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/image.c | 5 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/init.c | 192 ++++++++++--------
.../gpu/drm/nouveau/nvkm/subdev/bios/mxm.c | 23 +--
.../gpu/drm/nouveau/nvkm/subdev/bios/npde.c | 5 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/pcir.c | 5 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/perf.c | 18 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/pll.c | 19 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/pmu.c | 13 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/priv.h | 10 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.c | 9 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/rammap.c | 23 +--
.../gpu/drm/nouveau/nvkm/subdev/bios/shadow.c | 40 ++--
.../drm/nouveau/nvkm/subdev/bios/shadowacpi.c | 9 +-
.../drm/nouveau/nvkm/subdev/bios/shadowof.c | 7 +-
.../drm/nouveau/nvkm/subdev/bios/shadowpci.c | 9 +-
.../nouveau/nvkm/subdev/bios/shadowramin.c | 9 +-
.../drm/nouveau/nvkm/subdev/bios/shadowrom.c | 9 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/therm.c | 15 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/timing.c | 11 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/vmap.c | 9 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/volt.c | 9 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/xpio.c | 10 +-
.../gpu/drm/nouveau/nvkm/subdev/therm/base.c | 6 +-
.../gpu/drm/nouveau/nvkm/subdev/therm/priv.h | 3 +-
74 files changed, 529 insertions(+), 652 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 18e5edde08bd..af07bbba9faf 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -193,5 +193,13 @@
#define _nouveau_xtensa_context_rd32 _nvkm_xtensa_context_rd32
#define _nouveau_xtensa_context_wr32 _nvkm_xtensa_context_wr32
#define nouveau_xtensa_intr nvkm_xtensa_intr
+#define nouveau_gpio nvkm_gpio
+#define nouveau_i2c nvkm_i2c
+#define nouveau_i2c_port nvkm_i2c_port
+#define nouveau_devinit nvkm_devinit
+#define nouveau_bios nvkm_bios
+#define nouveau_bios_oclass nvkm_bios_oclass
+#define nouveau_pll_vals nvkm_pll_vals
+#define nouveau_therm_trip_point nvkm_therm_trip_point
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h
index 39528a9f3c20..cef287e0bbf2 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h
@@ -1,11 +1,9 @@
-#ifndef __NOUVEAU_BIOS_H__
-#define __NOUVEAU_BIOS_H__
-
+#ifndef __NVKM_BIOS_H__
+#define __NVKM_BIOS_H__
#include <core/subdev.h>
-#include <core/device.h>
-struct nouveau_bios {
- struct nouveau_subdev base;
+struct nvkm_bios {
+ struct nvkm_subdev base;
u32 size;
u8 *data;
@@ -21,15 +19,14 @@ struct nouveau_bios {
} version;
};
-static inline struct nouveau_bios *
-nouveau_bios(void *obj)
+static inline struct nvkm_bios *
+nvkm_bios(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_VBIOS);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_VBIOS);
}
u8 nvbios_checksum(const u8 *data, int size);
u16 nvbios_findstr(const u8 *data, int size, const char *str, int len);
-extern struct nouveau_oclass nouveau_bios_oclass;
-
+extern struct nvkm_oclass nvkm_bios_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h
index 1f84d3612dd8..cf202c793a1d 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h
@@ -1,14 +1,13 @@
#ifndef __NVBIOS_M0203_H__
#define __NVBIOS_M0203_H__
-
struct nvbios_M0203T {
#define M0203T_TYPE_RAMCFG 0x00
u8 type;
u16 pointer;
};
-u32 nvbios_M0203Te(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u32 nvbios_M0203Tp(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+u32 nvbios_M0203Te(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
+u32 nvbios_M0203Tp(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_M0203T *);
struct nvbios_M0203E {
@@ -22,10 +21,9 @@ struct nvbios_M0203E {
u8 group;
};
-u32 nvbios_M0203Ee(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
-u32 nvbios_M0203Ep(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
+u32 nvbios_M0203Ee(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
+u32 nvbios_M0203Ep(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_M0203E *);
-u32 nvbios_M0203Em(struct nouveau_bios *, u8 ramcfg, u8 *ver, u8 *hdr,
+u32 nvbios_M0203Em(struct nvkm_bios *, u8 ramcfg, u8 *ver, u8 *hdr,
struct nvbios_M0203E *);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h
index e171120cec81..d34608ff241e 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h
@@ -1,13 +1,12 @@
#ifndef __NVBIOS_M0205_H__
#define __NVBIOS_M0205_H__
-
struct nvbios_M0205T {
u16 freq;
};
-u32 nvbios_M0205Te(struct nouveau_bios *,
+u32 nvbios_M0205Te(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
-u32 nvbios_M0205Tp(struct nouveau_bios *,
+u32 nvbios_M0205Tp(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz,
struct nvbios_M0205T *);
@@ -15,18 +14,16 @@ struct nvbios_M0205E {
u8 type;
};
-u32 nvbios_M0205Ee(struct nouveau_bios *, int idx,
+u32 nvbios_M0205Ee(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u32 nvbios_M0205Ep(struct nouveau_bios *, int idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_M0205E *);
+u32 nvbios_M0205Ep(struct nvkm_bios *, int idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_M0205E *);
struct nvbios_M0205S {
u8 data;
};
-u32 nvbios_M0205Se(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr);
-u32 nvbios_M0205Sp(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr,
+u32 nvbios_M0205Se(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr);
+u32 nvbios_M0205Sp(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr,
struct nvbios_M0205S *);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h
index 67dc50d837bc..c7ff8d9526e7 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h
@@ -1,7 +1,6 @@
#ifndef __NVBIOS_M0209_H__
#define __NVBIOS_M0209_H__
-
-u32 nvbios_M0209Te(struct nouveau_bios *,
+u32 nvbios_M0209Te(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
struct nvbios_M0209E {
@@ -13,18 +12,16 @@ struct nvbios_M0209E {
u8 v03;
};
-u32 nvbios_M0209Ee(struct nouveau_bios *, int idx,
+u32 nvbios_M0209Ee(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u32 nvbios_M0209Ep(struct nouveau_bios *, int idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_M0209E *);
+u32 nvbios_M0209Ep(struct nvkm_bios *, int idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_M0209E *);
struct nvbios_M0209S {
u32 data[0x200];
};
-u32 nvbios_M0209Se(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr);
-u32 nvbios_M0209Sp(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr,
+u32 nvbios_M0209Se(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr);
+u32 nvbios_M0209Sp(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr,
struct nvbios_M0209S *);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h
index bba01ab1e049..1c1c52eac97d 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h
@@ -1,23 +1,21 @@
#ifndef __NVBIOS_P0260_H__
#define __NVBIOS_P0260_H__
-
-u32 nvbios_P0260Te(struct nouveau_bios *,
+u32 nvbios_P0260Te(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz);
struct nvbios_P0260E {
u32 data;
};
-u32 nvbios_P0260Ee(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
-u32 nvbios_P0260Ep(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
+u32 nvbios_P0260Ee(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
+u32 nvbios_P0260Ep(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_P0260E *);
struct nvbios_P0260X {
u32 data;
};
-u32 nvbios_P0260Xe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
-u32 nvbios_P0260Xp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
+u32 nvbios_P0260Xe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
+u32 nvbios_P0260Xp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_P0260X *);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h
index 73f060b07981..6711732b7cb1 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h
@@ -1,6 +1,5 @@
#ifndef __NVBIOS_BIT_H__
#define __NVBIOS_BIT_H__
-
struct bit_entry {
u8 id;
u8 version;
@@ -8,6 +7,5 @@ struct bit_entry {
u16 offset;
};
-int bit_entry(struct nouveau_bios *, u8 id, struct bit_entry *);
-
+int bit_entry(struct nvkm_bios *, u8 id, struct bit_entry *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h
index 10e4dbca649a..4107aa546a21 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h
@@ -1,8 +1,7 @@
#ifndef __NVBIOS_BMP_H__
#define __NVBIOS_BMP_H__
-
static inline u16
-bmp_version(struct nouveau_bios *bios)
+bmp_version(struct nvkm_bios *bios)
{
if (bios->bmp_offset) {
return nv_ro08(bios, bios->bmp_offset + 5) << 8 |
@@ -13,7 +12,7 @@ bmp_version(struct nouveau_bios *bios)
}
static inline u16
-bmp_mem_init_table(struct nouveau_bios *bios)
+bmp_mem_init_table(struct nvkm_bios *bios)
{
if (bmp_version(bios) >= 0x0300)
return nv_ro16(bios, bios->bmp_offset + 24);
@@ -21,7 +20,7 @@ bmp_mem_init_table(struct nouveau_bios *bios)
}
static inline u16
-bmp_sdr_seq_table(struct nouveau_bios *bios)
+bmp_sdr_seq_table(struct nvkm_bios *bios)
{
if (bmp_version(bios) >= 0x0300)
return nv_ro16(bios, bios->bmp_offset + 26);
@@ -29,11 +28,10 @@ bmp_sdr_seq_table(struct nouveau_bios *bios)
}
static inline u16
-bmp_ddr_seq_table(struct nouveau_bios *bios)
+bmp_ddr_seq_table(struct nvkm_bios *bios)
{
if (bmp_version(bios) >= 0x0300)
return nv_ro16(bios, bios->bmp_offset + 28);
return 0x0000;
}
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h
index 662b20726851..934b0ae5521d 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h
@@ -1,7 +1,6 @@
#ifndef __NVBIOS_BOOST_H__
#define __NVBIOS_BOOST_H__
-
-u16 nvbios_boostTe(struct nouveau_bios *, u8 *, u8 *, u8 *, u8 *, u8 *, u8 *);
+u16 nvbios_boostTe(struct nvkm_bios *, u8 *, u8 *, u8 *, u8 *, u8 *, u8 *);
struct nvbios_boostE {
u8 pstate;
@@ -9,10 +8,10 @@ struct nvbios_boostE {
u32 max;
};
-u16 nvbios_boostEe(struct nouveau_bios *, int idx, u8 *, u8 *, u8 *, u8 *);
-u16 nvbios_boostEp(struct nouveau_bios *, int idx, u8 *, u8 *, u8 *, u8 *,
+u16 nvbios_boostEe(struct nvkm_bios *, int idx, u8 *, u8 *, u8 *, u8 *);
+u16 nvbios_boostEp(struct nvkm_bios *, int idx, u8 *, u8 *, u8 *, u8 *,
struct nvbios_boostE *);
-u16 nvbios_boostEm(struct nouveau_bios *, u8, u8 *, u8 *, u8 *, u8 *,
+u16 nvbios_boostEm(struct nvkm_bios *, u8, u8 *, u8 *, u8 *, u8 *,
struct nvbios_boostE *);
struct nvbios_boostS {
@@ -22,8 +21,7 @@ struct nvbios_boostS {
u32 max;
};
-u16 nvbios_boostSe(struct nouveau_bios *, int, u16, u8 *, u8 *, u8, u8);
-u16 nvbios_boostSp(struct nouveau_bios *, int, u16, u8 *, u8 *, u8, u8,
+u16 nvbios_boostSe(struct nvkm_bios *, int, u16, u8 *, u8 *, u8, u8);
+u16 nvbios_boostSp(struct nvkm_bios *, int, u16, u8 *, u8 *, u8, u8,
struct nvbios_boostS *);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h
index f3930c27cb7a..e8e77ee24776 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h
@@ -1,6 +1,5 @@
#ifndef __NVBIOS_CONN_H__
#define __NVBIOS_CONN_H__
-
enum dcb_connector_type {
DCB_CONNECTOR_VGA = 0x00,
DCB_CONNECTOR_TV_0 = 0x10,
@@ -25,8 +24,8 @@ enum dcb_connector_type {
struct nvbios_connT {
};
-u32 nvbios_connTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u32 nvbios_connTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+u32 nvbios_connTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
+u32 nvbios_connTp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_connT *info);
struct nvbios_connE {
@@ -39,8 +38,7 @@ struct nvbios_connE {
u8 lcdid;
};
-u32 nvbios_connEe(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *hdr);
-u32 nvbios_connEp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *hdr,
+u32 nvbios_connEe(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr);
+u32 nvbios_connEp(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr,
struct nvbios_connE *info);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h
index a80a43809883..2f0e0c8e83be 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h
@@ -1,7 +1,6 @@
#ifndef __NVBIOS_CSTEP_H__
#define __NVBIOS_CSTEP_H__
-
-u16 nvbios_cstepTe(struct nouveau_bios *,
+u16 nvbios_cstepTe(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz);
struct nvbios_cstepE {
@@ -9,10 +8,10 @@ struct nvbios_cstepE {
u8 index;
};
-u16 nvbios_cstepEe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
-u16 nvbios_cstepEp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
+u16 nvbios_cstepEe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
+u16 nvbios_cstepEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_cstepE *);
-u16 nvbios_cstepEm(struct nouveau_bios *, u8 pstate, u8 *ver, u8 *hdr,
+u16 nvbios_cstepEm(struct nvkm_bios *, u8 pstate, u8 *ver, u8 *hdr,
struct nvbios_cstepE *);
struct nvbios_cstepX {
@@ -21,8 +20,7 @@ struct nvbios_cstepX {
u8 voltage;
};
-u16 nvbios_cstepXe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
-u16 nvbios_cstepXp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
+u16 nvbios_cstepXe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
+u16 nvbios_cstepXp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_cstepX *);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h
index 123270e9813a..4892a65ddd48 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h
@@ -1,8 +1,5 @@
#ifndef __NVBIOS_DCB_H__
#define __NVBIOS_DCB_H__
-
-struct nouveau_bios;
-
enum dcb_output_type {
DCB_OUTPUT_ANALOG = 0x0,
DCB_OUTPUT_TV = 0x1,
@@ -57,13 +54,12 @@ struct dcb_output {
bool i2c_upper_default;
};
-u16 dcb_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *ent, u8 *len);
-u16 dcb_outp(struct nouveau_bios *, u8 idx, u8 *ver, u8 *len);
-u16 dcb_outp_parse(struct nouveau_bios *, u8 idx, u8 *, u8 *,
+u16 dcb_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *ent, u8 *len);
+u16 dcb_outp(struct nvkm_bios *, u8 idx, u8 *ver, u8 *len);
+u16 dcb_outp_parse(struct nvkm_bios *, u8 idx, u8 *, u8 *,
struct dcb_output *);
-u16 dcb_outp_match(struct nouveau_bios *, u16 type, u16 mask, u8 *, u8 *,
+u16 dcb_outp_match(struct nvkm_bios *, u16 type, u16 mask, u8 *, u8 *,
struct dcb_output *);
-int dcb_outp_foreach(struct nouveau_bios *, void *data, int (*exec)
- (struct nouveau_bios *, void *, int index, u16 entry));
-
+int dcb_outp_foreach(struct nvkm_bios *, void *data, int (*exec)
+ (struct nvkm_bios *, void *, int index, u16 entry));
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h
index c35937e2f6a4..db10c11f0595 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h
@@ -1,17 +1,14 @@
#ifndef __NVBIOS_DISP_H__
#define __NVBIOS_DISP_H__
-
-u16 nvbios_disp_table(struct nouveau_bios *,
+u16 nvbios_disp_table(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *sub);
struct nvbios_disp {
u16 data;
};
-u16 nvbios_disp_entry(struct nouveau_bios *, u8 idx,
- u8 *ver, u8 *hdr__, u8 *sub);
-u16 nvbios_disp_parse(struct nouveau_bios *, u8 idx,
- u8 *ver, u8 *hdr__, u8 *sub,
+u16 nvbios_disp_entry(struct nvkm_bios *, u8 idx, u8 *ver, u8 *hdr, u8 *sub);
+u16 nvbios_disp_parse(struct nvkm_bios *, u8 idx, u8 *ver, u8 *hdr, u8 *sub,
struct nvbios_disp *);
struct nvbios_outp {
@@ -20,29 +17,23 @@ struct nvbios_outp {
u16 script[3];
};
-u16 nvbios_outp_entry(struct nouveau_bios *, u8 idx,
+u16 nvbios_outp_entry(struct nvkm_bios *, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 nvbios_outp_parse(struct nouveau_bios *, u8 idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_outp *);
-u16 nvbios_outp_match(struct nouveau_bios *, u16 type, u16 mask,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_outp *);
-
+u16 nvbios_outp_parse(struct nvkm_bios *, u8 idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *);
+u16 nvbios_outp_match(struct nvkm_bios *, u16 type, u16 mask,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *);
struct nvbios_ocfg {
u16 match;
u16 clkcmp[2];
};
-u16 nvbios_ocfg_entry(struct nouveau_bios *, u16 outp, u8 idx,
+u16 nvbios_ocfg_entry(struct nvkm_bios *, u16 outp, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 nvbios_ocfg_parse(struct nouveau_bios *, u16 outp, u8 idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_ocfg *);
-u16 nvbios_ocfg_match(struct nouveau_bios *, u16 outp, u16 type,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_ocfg *);
-u16 nvbios_oclk_match(struct nouveau_bios *, u16 cmp, u32 khz);
-
+u16 nvbios_ocfg_parse(struct nvkm_bios *, u16 outp, u8 idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *);
+u16 nvbios_ocfg_match(struct nvkm_bios *, u16 outp, u16 type,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *);
+u16 nvbios_oclk_match(struct nvkm_bios *, u16 cmp, u32 khz);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h
index 728206e21777..b4d39df70d4e 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h
@@ -1,6 +1,5 @@
#ifndef __NVBIOS_DP_H__
#define __NVBIOS_DP_H__
-
struct nvbios_dpout {
u16 type;
u16 mask;
@@ -9,10 +8,10 @@ struct nvbios_dpout {
u32 lnkcmp;
};
-u16 nvbios_dpout_parse(struct nouveau_bios *, u8 idx,
+u16 nvbios_dpout_parse(struct nvkm_bios *, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_dpout *);
-u16 nvbios_dpout_match(struct nouveau_bios *, u16 type, u16 mask,
+u16 nvbios_dpout_match(struct nvkm_bios *, u16 type, u16 mask,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_dpout *);
@@ -24,12 +23,9 @@ struct nvbios_dpcfg {
};
u16
-nvbios_dpcfg_parse(struct nouveau_bios *, u16 outp, u8 idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_dpcfg *);
+nvbios_dpcfg_parse(struct nvkm_bios *, u16 outp, u8 idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_dpcfg *);
u16
-nvbios_dpcfg_match(struct nouveau_bios *, u16 outp, u8 pc, u8 vs, u8 pe,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_dpcfg *);
-
+nvbios_dpcfg_match(struct nvkm_bios *, u16 outp, u8 pc, u8 vs, u8 pe,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_dpcfg *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h
index 949fee3af8fb..6d3bedc633b3 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h
@@ -1,8 +1,5 @@
#ifndef __NVBIOS_EXTDEV_H__
#define __NVBIOS_EXTDEV_H__
-
-struct nouveau_bios;
-
enum nvbios_extdev_type {
NVBIOS_EXTDEV_LM89 = 0x02,
NVBIOS_EXTDEV_VT1103M = 0x40,
@@ -20,11 +17,9 @@ struct nvbios_extdev_func {
};
int
-nvbios_extdev_parse(struct nouveau_bios *, int, struct nvbios_extdev_func *);
+nvbios_extdev_parse(struct nvkm_bios *, int, struct nvbios_extdev_func *);
int
-nvbios_extdev_find(struct nouveau_bios *, enum nvbios_extdev_type,
+nvbios_extdev_find(struct nvkm_bios *, enum nvbios_extdev_type,
struct nvbios_extdev_func *);
-
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h
index 119d0874e041..693ea7d9ec43 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h
@@ -1,8 +1,6 @@
#ifndef __NVBIOS_FAN_H__
#define __NVBIOS_FAN_H__
-
#include <subdev/bios/therm.h>
-u16 nvbios_fan_parse(struct nouveau_bios *bios, struct nvbios_therm_fan *fan);
-
+u16 nvbios_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h
index c7b2e586be0b..33be260ddd38 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h
@@ -1,6 +1,5 @@
#ifndef __NVBIOS_GPIO_H__
#define __NVBIOS_GPIO_H__
-
enum dcb_gpio_func_name {
DCB_GPIO_PANEL_POWER = 0x01,
DCB_GPIO_TVDAC0 = 0x0c,
@@ -38,11 +37,10 @@ struct dcb_gpio_func {
u8 param;
};
-u16 dcb_gpio_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 dcb_gpio_entry(struct nouveau_bios *, int idx, int ent, u8 *ver, u8 *len);
-u16 dcb_gpio_parse(struct nouveau_bios *, int idx, int ent, u8 *ver, u8 *len,
+u16 dcb_gpio_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
+u16 dcb_gpio_entry(struct nvkm_bios *, int idx, int ent, u8 *ver, u8 *len);
+u16 dcb_gpio_parse(struct nvkm_bios *, int idx, int ent, u8 *ver, u8 *len,
struct dcb_gpio_func *);
-u16 dcb_gpio_match(struct nouveau_bios *, int idx, u8 func, u8 line,
+u16 dcb_gpio_match(struct nvkm_bios *, int idx, u8 func, u8 line,
u8 *ver, u8 *len, struct dcb_gpio_func *);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h
index c9bb112895af..85c529ecf9b1 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h
@@ -1,8 +1,5 @@
#ifndef __NVBIOS_I2C_H__
#define __NVBIOS_I2C_H__
-
-struct nouveau_bios;
-
enum dcb_i2c_type {
/* matches bios type field prior to ccb 4.1 */
DCB_I2C_NV04_BIT = 0x00,
@@ -22,8 +19,7 @@ struct dcb_i2c_entry {
u8 auxch;
};
-u16 dcb_i2c_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 dcb_i2c_entry(struct nouveau_bios *, u8 index, u8 *ver, u8 *len);
-int dcb_i2c_parse(struct nouveau_bios *, u8 index, struct dcb_i2c_entry *);
-
+u16 dcb_i2c_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
+u16 dcb_i2c_entry(struct nvkm_bios *, u8 index, u8 *ver, u8 *len);
+int dcb_i2c_parse(struct nvkm_bios *, u8 index, struct dcb_i2c_entry *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h
index 3348b4580843..e15d63b9a5eb 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h
@@ -1,6 +1,5 @@
#ifndef __NVBIOS_IMAGE_H__
#define __NVBIOS_IMAGE_H__
-
struct nvbios_image {
u32 base;
u32 size;
@@ -8,6 +7,5 @@ struct nvbios_image {
bool last;
};
-bool nvbios_image(struct nouveau_bios *, int, struct nvbios_image *);
-
+bool nvbios_image(struct nvkm_bios *, int, struct nvbios_image *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
index ca2f6bf37f46..578a667eed3b 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
@@ -1,9 +1,8 @@
#ifndef __NVBIOS_INIT_H__
#define __NVBIOS_INIT_H__
-
struct nvbios_init {
- struct nouveau_subdev *subdev;
- struct nouveau_bios *bios;
+ struct nvkm_subdev *subdev;
+ struct nvkm_bios *bios;
u16 offset;
struct dcb_output *outp;
int crtc;
@@ -17,6 +16,5 @@ struct nvbios_init {
};
int nvbios_exec(struct nvbios_init *);
-int nvbios_init(struct nouveau_subdev *, bool execute);
-
+int nvbios_init(struct nvkm_subdev *, bool execute);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h
index 5572e60414e8..4e31b64c5edf 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h
@@ -1,9 +1,6 @@
#ifndef __NVBIOS_MXM_H__
#define __NVBIOS_MXM_H__
-
-u16 mxm_table(struct nouveau_bios *, u8 *ver, u8 *hdr);
-
-u8 mxm_sor_map(struct nouveau_bios *, u8 conn);
-u8 mxm_ddc_map(struct nouveau_bios *, u8 port);
-
+u16 mxm_table(struct nvkm_bios *, u8 *ver, u8 *hdr);
+u8 mxm_sor_map(struct nvkm_bios *, u8 conn);
+u8 mxm_ddc_map(struct nvkm_bios *, u8 port);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h
index b18413d951e5..64a59549b7ea 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h
@@ -1,12 +1,10 @@
#ifndef __NVBIOS_NPDE_H__
#define __NVBIOS_NPDE_H__
-
struct nvbios_npdeT {
u32 image_size;
bool last;
};
-u32 nvbios_npdeTe(struct nouveau_bios *, u32);
-u32 nvbios_npdeTp(struct nouveau_bios *, u32, struct nvbios_npdeT *);
-
+u32 nvbios_npdeTe(struct nvkm_bios *, u32);
+u32 nvbios_npdeTp(struct nvkm_bios *, u32, struct nvbios_npdeT *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h
index 3d634a06dca1..e85931541f4f 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h
@@ -1,6 +1,5 @@
#ifndef __NVBIOS_PCIR_H__
#define __NVBIOS_PCIR_H__
-
struct nvbios_pcirT {
u16 vendor_id;
u16 device_id;
@@ -11,8 +10,7 @@ struct nvbios_pcirT {
bool last;
};
-u32 nvbios_pcirTe(struct nouveau_bios *, u32, u8 *ver, u16 *hdr);
-u32 nvbios_pcirTp(struct nouveau_bios *, u32, u8 *ver, u16 *hdr,
+u32 nvbios_pcirTe(struct nvkm_bios *, u32, u8 *ver, u16 *hdr);
+u32 nvbios_pcirTp(struct nvkm_bios *, u32, u8 *ver, u16 *hdr,
struct nvbios_pcirT *);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h
index 16ff06ec2a88..7cc2becabc69 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h
@@ -1,9 +1,6 @@
#ifndef __NVBIOS_PERF_H__
#define __NVBIOS_PERF_H__
-
-struct nouveau_bios;
-
-u16 nvbios_perf_table(struct nouveau_bios *, u8 *ver, u8 *hdr,
+u16 nvbios_perf_table(struct nvkm_bios *, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
struct nvbios_perfE {
@@ -18,9 +15,9 @@ struct nvbios_perfE {
u32 script;
};
-u16 nvbios_perf_entry(struct nouveau_bios *, int idx,
+u16 nvbios_perf_entry(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 nvbios_perfEp(struct nouveau_bios *, int idx,
+u16 nvbios_perfEp(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *);
struct nvbios_perfS {
@@ -31,17 +28,14 @@ struct nvbios_perfS {
};
};
-u32 nvbios_perfSe(struct nouveau_bios *, u32 data, int idx,
+u32 nvbios_perfSe(struct nvkm_bios *, u32 data, int idx,
u8 *ver, u8 *hdr, u8 cnt, u8 len);
-u32 nvbios_perfSp(struct nouveau_bios *, u32 data, int idx,
+u32 nvbios_perfSp(struct nvkm_bios *, u32 data, int idx,
u8 *ver, u8 *hdr, u8 cnt, u8 len, struct nvbios_perfS *);
struct nvbios_perf_fan {
u32 pwm_divisor;
};
-int
-nvbios_perf_fan_parse(struct nouveau_bios *, struct nvbios_perf_fan *);
-
-
+int nvbios_perf_fan_parse(struct nvkm_bios *, struct nvbios_perf_fan *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h
index b2f3d4d0aa49..5a69978d1e3b 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h
@@ -1,8 +1,7 @@
#ifndef __NVBIOS_PLL_H__
#define __NVBIOS_PLL_H__
-
/*XXX: kill me */
-struct nouveau_pll_vals {
+struct nvkm_pll_vals {
union {
struct {
#ifdef __BIG_ENDIAN
@@ -20,10 +19,8 @@ struct nouveau_pll_vals {
int refclk;
};
-struct nouveau_bios;
-
/* these match types in pll limits table version 0x40,
- * nouveau uses them on all chipsets internally where a
+ * nvkm uses them on all chipsets internally where a
* specific pll needs to be referenced, but the exact
* register isn't known.
*/
@@ -74,6 +71,5 @@ struct nvbios_pll {
} vco1, vco2;
};
-int nvbios_pll_parse(struct nouveau_bios *, u32 type, struct nvbios_pll *);
-
+int nvbios_pll_parse(struct nvkm_bios *, u32 type, struct nvbios_pll *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h
index 9de593deaea8..d606875c125a 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h
@@ -1,11 +1,10 @@
#ifndef __NVBIOS_PMU_H__
#define __NVBIOS_PMU_H__
-
struct nvbios_pmuT {
};
-u32 nvbios_pmuTe(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u32 nvbios_pmuTp(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+u32 nvbios_pmuTe(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
+u32 nvbios_pmuTp(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_pmuT *);
struct nvbios_pmuE {
@@ -13,8 +12,8 @@ struct nvbios_pmuE {
u32 data;
};
-u32 nvbios_pmuEe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
-u32 nvbios_pmuEp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
+u32 nvbios_pmuEe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
+u32 nvbios_pmuEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_pmuE *);
struct nvbios_pmuR {
@@ -32,6 +31,5 @@ struct nvbios_pmuR {
u32 args_addr_pmu;
};
-bool nvbios_pmuRm(struct nouveau_bios *, u8 type, struct nvbios_pmuR *);
-
+bool nvbios_pmuRm(struct nvkm_bios *, u8 type, struct nvbios_pmuR *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h
index 4a0e0ceb41ba..420426793880 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h
@@ -1,8 +1,5 @@
#ifndef __NVBIOS_RAMCFG_H__
#define __NVBIOS_RAMCFG_H__
-
-struct nouveau_bios;
-
struct nvbios_ramcfg {
unsigned rammap_ver;
unsigned rammap_hdr;
@@ -139,7 +136,6 @@ struct nvbios_ramcfg {
};
};
-u8 nvbios_ramcfg_count(struct nouveau_bios *);
-u8 nvbios_ramcfg_index(struct nouveau_subdev *);
-
+u8 nvbios_ramcfg_count(struct nvkm_bios *);
+u8 nvbios_ramcfg_index(struct nvkm_subdev *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h
index 47e021d3e20d..609a905ec780 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h
@@ -1,26 +1,21 @@
#ifndef __NVBIOS_RAMMAP_H__
#define __NVBIOS_RAMMAP_H__
+#include <subdev/bios/ramcfg.h>
-struct nvbios_ramcfg;
-
-u32 nvbios_rammapTe(struct nouveau_bios *, u8 *ver, u8 *hdr,
+u32 nvbios_rammapTe(struct nvkm_bios *, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
-u32 nvbios_rammapEe(struct nouveau_bios *, int idx,
+u32 nvbios_rammapEe(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u32 nvbios_rammapEp(struct nouveau_bios *, int idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_ramcfg *);
-u32 nvbios_rammapEm(struct nouveau_bios *, u16 mhz,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_ramcfg *);
+u32 nvbios_rammapEp(struct nvkm_bios *, int idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *);
+u32 nvbios_rammapEm(struct nvkm_bios *, u16 mhz,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *);
-u32 nvbios_rammapSe(struct nouveau_bios *, u32 data,
+u32 nvbios_rammapSe(struct nvkm_bios *, u32 data,
u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
u8 *ver, u8 *hdr);
-u32 nvbios_rammapSp(struct nouveau_bios *, u32 data,
+u32 nvbios_rammapSp(struct nvkm_bios *, u32 data,
u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
- u8 *ver, u8 *hdr,
- struct nvbios_ramcfg *);
-
+ u8 *ver, u8 *hdr, struct nvbios_ramcfg *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h
index 295d093f3b30..dd3ba960e75d 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h
@@ -1,8 +1,5 @@
#ifndef __NVBIOS_THERM_H__
#define __NVBIOS_THERM_H__
-
-struct nouveau_bios;
-
struct nvbios_therm_threshold {
u8 temp;
u8 hysteresis;
@@ -30,8 +27,8 @@ enum nvbios_therm_fan_type {
};
/* no vbios have more than 6 */
-#define NOUVEAU_TEMP_FAN_TRIP_MAX 10
-struct nouveau_therm_trip_point {
+#define NVKM_TEMP_FAN_TRIP_MAX 10
+struct nvbios_therm_trip_point {
int fan_duty;
int temp;
int hysteresis;
@@ -55,7 +52,7 @@ struct nvbios_therm_fan {
u16 slow_down_period;
enum nvbios_therm_fan_mode fan_mode;
- struct nouveau_therm_trip_point trip[NOUVEAU_TEMP_FAN_TRIP_MAX];
+ struct nvbios_therm_trip_point trip[NVKM_TEMP_FAN_TRIP_MAX];
u8 nr_fan_trip;
u8 linear_min_temp;
u8 linear_max_temp;
@@ -67,11 +64,9 @@ enum nvbios_therm_domain {
};
int
-nvbios_therm_sensor_parse(struct nouveau_bios *, enum nvbios_therm_domain,
+nvbios_therm_sensor_parse(struct nvkm_bios *, enum nvbios_therm_domain,
struct nvbios_therm_sensor *);
int
-nvbios_therm_fan_parse(struct nouveau_bios *, struct nvbios_therm_fan *);
-
-
+nvbios_therm_fan_parse(struct nvkm_bios *, struct nvbios_therm_fan *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h
index 76d914b67ab5..339a826aa176 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h
@@ -1,14 +1,11 @@
#ifndef __NVBIOS_TIMING_H__
#define __NVBIOS_TIMING_H__
+#include <subdev/bios/ramcfg.h>
-struct nvbios_ramcfg;
-
-u16 nvbios_timingTe(struct nouveau_bios *,
+u16 nvbios_timingTe(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
-u16 nvbios_timingEe(struct nouveau_bios *, int idx,
+u16 nvbios_timingEe(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 nvbios_timingEp(struct nouveau_bios *, int idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_ramcfg *);
-
+u16 nvbios_timingEp(struct nvkm_bios *, int idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h
index ad5a8f20e113..6633c6db9281 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h
@@ -1,13 +1,10 @@
#ifndef __NVBIOS_VMAP_H__
#define __NVBIOS_VMAP_H__
-
-struct nouveau_bios;
-
struct nvbios_vmap {
};
-u16 nvbios_vmap_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 nvbios_vmap_parse(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+u16 nvbios_vmap_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
+u16 nvbios_vmap_parse(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_vmap *);
struct nvbios_vmap_entry {
@@ -18,8 +15,7 @@ struct nvbios_vmap_entry {
s32 arg[6];
};
-u16 nvbios_vmap_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *len);
-u16 nvbios_vmap_entry_parse(struct nouveau_bios *, int idx, u8 *ver, u8 *len,
+u16 nvbios_vmap_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *len);
+u16 nvbios_vmap_entry_parse(struct nvkm_bios *, int idx, u8 *ver, u8 *len,
struct nvbios_vmap_entry *);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h
index 6a11dcd59770..eb2de4b85bbd 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h
@@ -1,8 +1,5 @@
#ifndef __NVBIOS_VOLT_H__
#define __NVBIOS_VOLT_H__
-
-struct nouveau_bios;
-
struct nvbios_volt {
u8 vidmask;
u32 min;
@@ -11,8 +8,8 @@ struct nvbios_volt {
s16 step;
};
-u16 nvbios_volt_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 nvbios_volt_parse(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+u16 nvbios_volt_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
+u16 nvbios_volt_parse(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_volt *);
struct nvbios_volt_entry {
@@ -20,8 +17,7 @@ struct nvbios_volt_entry {
u8 vid;
};
-u16 nvbios_volt_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *len);
-u16 nvbios_volt_entry_parse(struct nouveau_bios *, int idx, u8 *ver, u8 *len,
+u16 nvbios_volt_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *len);
+u16 nvbios_volt_entry_parse(struct nvkm_bios *, int idx, u8 *ver, u8 *len,
struct nvbios_volt_entry *);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h
index 360baab52e4c..0c0fe234ff12 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h
@@ -11,9 +11,8 @@ struct nvbios_xpio {
u8 flags;
};
-u16 dcb_xpio_table(struct nouveau_bios *, u8 idx,
+u16 dcb_xpio_table(struct nvkm_bios *, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
-u16 dcb_xpio_parse(struct nouveau_bios *, u8 idx,
+u16 dcb_xpio_parse(struct nvkm_bios *, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_xpio *);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
index 0277585c9067..b6a210071b22 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
@@ -108,6 +108,7 @@ extern struct nouveau_oclass *nve0_fb_oclass;
extern struct nouveau_oclass *gk20a_fb_oclass;
extern struct nouveau_oclass *gm107_fb_oclass;
+#include <subdev/bios.h>
#include <subdev/bios/ramcfg.h>
struct nouveau_ram_data {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.c
index 28906b16d4e5..08eb03fbc203 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/M0203.h>
u32
-nvbios_M0203Te(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+nvbios_M0203Te(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry bit_M;
u32 data = 0x00000000;
@@ -53,7 +52,7 @@ nvbios_M0203Te(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
u32
-nvbios_M0203Tp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+nvbios_M0203Tp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_M0203T *info)
{
u32 data = nvbios_M0203Te(bios, ver, hdr, cnt, len);
@@ -70,7 +69,7 @@ nvbios_M0203Tp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
}
u32
-nvbios_M0203Ee(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
+nvbios_M0203Ee(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr)
{
u8 cnt, len;
u32 data = nvbios_M0203Te(bios, ver, hdr, &cnt, &len);
@@ -83,7 +82,7 @@ nvbios_M0203Ee(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
}
u32
-nvbios_M0203Ep(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
+nvbios_M0203Ep(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr,
struct nvbios_M0203E *info)
{
u32 data = nvbios_M0203Ee(bios, idx, ver, hdr);
@@ -101,7 +100,7 @@ nvbios_M0203Ep(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
}
u32
-nvbios_M0203Em(struct nouveau_bios *bios, u8 ramcfg, u8 *ver, u8 *hdr,
+nvbios_M0203Em(struct nvkm_bios *bios, u8 ramcfg, u8 *ver, u8 *hdr,
struct nvbios_M0203E *info)
{
struct nvbios_M0203T M0203T;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.c
index ac9617c5fc2a..e1a8ad5f3066 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/M0205.h>
u32
-nvbios_M0205Te(struct nouveau_bios *bios,
+nvbios_M0205Te(struct nvkm_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_M;
@@ -56,7 +55,7 @@ nvbios_M0205Te(struct nouveau_bios *bios,
}
u32
-nvbios_M0205Tp(struct nouveau_bios *bios,
+nvbios_M0205Tp(struct nvkm_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz,
struct nvbios_M0205T *info)
{
@@ -73,7 +72,7 @@ nvbios_M0205Tp(struct nouveau_bios *bios,
}
u32
-nvbios_M0205Ee(struct nouveau_bios *bios, int idx,
+nvbios_M0205Ee(struct nvkm_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 snr, ssz;
@@ -89,7 +88,7 @@ nvbios_M0205Ee(struct nouveau_bios *bios, int idx,
}
u32
-nvbios_M0205Ep(struct nouveau_bios *bios, int idx,
+nvbios_M0205Ep(struct nvkm_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_M0205E *info)
{
@@ -106,7 +105,7 @@ nvbios_M0205Ep(struct nouveau_bios *bios, int idx,
}
u32
-nvbios_M0205Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr)
+nvbios_M0205Se(struct nvkm_bios *bios, int ent, int idx, u8 *ver, u8 *hdr)
{
u8 cnt, len;
@@ -120,7 +119,7 @@ nvbios_M0205Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr)
}
u32
-nvbios_M0205Sp(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr,
+nvbios_M0205Sp(struct nvkm_bios *bios, int ent, int idx, u8 *ver, u8 *hdr,
struct nvbios_M0205S *info)
{
u32 data = nvbios_M0205Se(bios, ent, idx, ver, hdr);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.c
index b142a510e89f..3026920c3358 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/M0209.h>
u32
-nvbios_M0209Te(struct nouveau_bios *bios,
+nvbios_M0209Te(struct nvkm_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_M;
@@ -56,7 +55,7 @@ nvbios_M0209Te(struct nouveau_bios *bios,
}
u32
-nvbios_M0209Ee(struct nouveau_bios *bios, int idx,
+nvbios_M0209Ee(struct nvkm_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 snr, ssz;
@@ -72,9 +71,8 @@ nvbios_M0209Ee(struct nouveau_bios *bios, int idx,
}
u32
-nvbios_M0209Ep(struct nouveau_bios *bios, int idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_M0209E *info)
+nvbios_M0209Ep(struct nvkm_bios *bios, int idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_M0209E *info)
{
u32 data = nvbios_M0209Ee(bios, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
@@ -94,7 +92,7 @@ nvbios_M0209Ep(struct nouveau_bios *bios, int idx,
}
u32
-nvbios_M0209Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr)
+nvbios_M0209Se(struct nvkm_bios *bios, int ent, int idx, u8 *ver, u8 *hdr)
{
u8 cnt, len;
@@ -108,7 +106,7 @@ nvbios_M0209Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr)
}
u32
-nvbios_M0209Sp(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr,
+nvbios_M0209Sp(struct nvkm_bios *bios, int ent, int idx, u8 *ver, u8 *hdr,
struct nvbios_M0209S *info)
{
struct nvbios_M0209E M0209E;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.c
index 199f4e5f7488..b72edcf849b6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.c
@@ -21,14 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
-#include <subdev/bios/ramcfg.h>
#include <subdev/bios/P0260.h>
u32
-nvbios_P0260Te(struct nouveau_bios *bios,
+nvbios_P0260Te(struct nvkm_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz)
{
struct bit_entry bit_P;
@@ -57,7 +55,7 @@ nvbios_P0260Te(struct nouveau_bios *bios,
}
u32
-nvbios_P0260Ee(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
+nvbios_P0260Ee(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len)
{
u8 hdr, cnt, xnr, xsz;
u32 data = nvbios_P0260Te(bios, ver, &hdr, &cnt, len, &xnr, &xsz);
@@ -67,7 +65,7 @@ nvbios_P0260Ee(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
}
u32
-nvbios_P0260Ep(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len,
+nvbios_P0260Ep(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len,
struct nvbios_P0260E *info)
{
u32 data = nvbios_P0260Ee(bios, idx, ver, len);
@@ -83,7 +81,7 @@ nvbios_P0260Ep(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len,
}
u32
-nvbios_P0260Xe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *xsz)
+nvbios_P0260Xe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *xsz)
{
u8 hdr, cnt, len, xnr;
u32 data = nvbios_P0260Te(bios, ver, &hdr, &cnt, &len, &xnr, xsz);
@@ -93,7 +91,7 @@ nvbios_P0260Xe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *xsz)
}
u32
-nvbios_P0260Xp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
+nvbios_P0260Xp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr,
struct nvbios_P0260X *info)
{
u32 data = nvbios_P0260Xe(bios, idx, ver, hdr);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c
index 7df3a273553d..8db204f92ed3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c
@@ -21,18 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/object.h>
-#include <core/device.h>
-#include <core/subdev.h>
-#include <core/option.h>
+#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bios/bmp.h>
#include <subdev/bios/bit.h>
-#include "priv.h"
-
u8
nvbios_checksum(const u8 *data, int size)
{
@@ -59,7 +53,7 @@ nvbios_findstr(const u8 *data, int size, const char *str, int len)
}
int
-nvbios_extend(struct nouveau_bios *bios, u32 length)
+nvbios_extend(struct nvkm_bios *bios, u32 length)
{
if (bios->size < length) {
u8 *prev = bios->data;
@@ -76,59 +70,58 @@ nvbios_extend(struct nouveau_bios *bios, u32 length)
}
static u8
-nouveau_bios_rd08(struct nouveau_object *object, u64 addr)
+nvkm_bios_rd08(struct nvkm_object *object, u64 addr)
{
- struct nouveau_bios *bios = (void *)object;
+ struct nvkm_bios *bios = (void *)object;
return bios->data[addr];
}
static u16
-nouveau_bios_rd16(struct nouveau_object *object, u64 addr)
+nvkm_bios_rd16(struct nvkm_object *object, u64 addr)
{
- struct nouveau_bios *bios = (void *)object;
+ struct nvkm_bios *bios = (void *)object;
return get_unaligned_le16(&bios->data[addr]);
}
static u32
-nouveau_bios_rd32(struct nouveau_object *object, u64 addr)
+nvkm_bios_rd32(struct nvkm_object *object, u64 addr)
{
- struct nouveau_bios *bios = (void *)object;
+ struct nvkm_bios *bios = (void *)object;
return get_unaligned_le32(&bios->data[addr]);
}
static void
-nouveau_bios_wr08(struct nouveau_object *object, u64 addr, u8 data)
+nvkm_bios_wr08(struct nvkm_object *object, u64 addr, u8 data)
{
- struct nouveau_bios *bios = (void *)object;
+ struct nvkm_bios *bios = (void *)object;
bios->data[addr] = data;
}
static void
-nouveau_bios_wr16(struct nouveau_object *object, u64 addr, u16 data)
+nvkm_bios_wr16(struct nvkm_object *object, u64 addr, u16 data)
{
- struct nouveau_bios *bios = (void *)object;
+ struct nvkm_bios *bios = (void *)object;
put_unaligned_le16(data, &bios->data[addr]);
}
static void
-nouveau_bios_wr32(struct nouveau_object *object, u64 addr, u32 data)
+nvkm_bios_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
- struct nouveau_bios *bios = (void *)object;
+ struct nvkm_bios *bios = (void *)object;
put_unaligned_le32(data, &bios->data[addr]);
}
static int
-nouveau_bios_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nvkm_bios_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_bios *bios;
+ struct nvkm_bios *bios;
struct bit_entry bit_i;
int ret;
- ret = nouveau_subdev_create(parent, engine, oclass, 0,
- "VBIOS", "bios", &bios);
+ ret = nvkm_subdev_create(parent, engine, oclass, 0,
+ "VBIOS", "bios", &bios);
*pobject = nv_object(bios);
if (ret)
return ret;
@@ -174,40 +167,40 @@ nouveau_bios_ctor(struct nouveau_object *parent,
}
static void
-nouveau_bios_dtor(struct nouveau_object *object)
+nvkm_bios_dtor(struct nvkm_object *object)
{
- struct nouveau_bios *bios = (void *)object;
+ struct nvkm_bios *bios = (void *)object;
kfree(bios->data);
- nouveau_subdev_destroy(&bios->base);
+ nvkm_subdev_destroy(&bios->base);
}
static int
-nouveau_bios_init(struct nouveau_object *object)
+nvkm_bios_init(struct nvkm_object *object)
{
- struct nouveau_bios *bios = (void *)object;
- return nouveau_subdev_init(&bios->base);
+ struct nvkm_bios *bios = (void *)object;
+ return nvkm_subdev_init(&bios->base);
}
static int
-nouveau_bios_fini(struct nouveau_object *object, bool suspend)
+nvkm_bios_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_bios *bios = (void *)object;
- return nouveau_subdev_fini(&bios->base, suspend);
+ struct nvkm_bios *bios = (void *)object;
+ return nvkm_subdev_fini(&bios->base, suspend);
}
-struct nouveau_oclass
-nouveau_bios_oclass = {
+struct nvkm_oclass
+nvkm_bios_oclass = {
.handle = NV_SUBDEV(VBIOS, 0x00),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nouveau_bios_ctor,
- .dtor = nouveau_bios_dtor,
- .init = nouveau_bios_init,
- .fini = nouveau_bios_fini,
- .rd08 = nouveau_bios_rd08,
- .rd16 = nouveau_bios_rd16,
- .rd32 = nouveau_bios_rd32,
- .wr08 = nouveau_bios_wr08,
- .wr16 = nouveau_bios_wr16,
- .wr32 = nouveau_bios_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = nvkm_bios_ctor,
+ .dtor = nvkm_bios_dtor,
+ .init = nvkm_bios_init,
+ .fini = nvkm_bios_fini,
+ .rd08 = nvkm_bios_rd08,
+ .rd16 = nvkm_bios_rd16,
+ .rd32 = nvkm_bios_rd32,
+ .wr08 = nvkm_bios_wr08,
+ .wr16 = nvkm_bios_wr16,
+ .wr32 = nvkm_bios_wr32,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.c
index 1d03a3f2b2d2..eab540496cdf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.c
@@ -21,14 +21,11 @@
*
* Authors: Ben Skeggs
*/
-
-#include "core/object.h"
-
-#include "subdev/bios.h"
-#include "subdev/bios/bit.h"
+#include <subdev/bios.h>
+#include <subdev/bios/bit.h>
int
-bit_entry(struct nouveau_bios *bios, u8 id, struct bit_entry *bit)
+bit_entry(struct nvkm_bios *bios, u8 id, struct bit_entry *bit)
{
if (likely(bios->bit_offset)) {
u8 entries = nv_ro08(bios, bios->bit_offset + 10);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c
index c1835e591c44..12e958533f46 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/boost.h>
u16
-nvbios_boostTe(struct nouveau_bios *bios,
+nvbios_boostTe(struct nvkm_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_P;
@@ -57,7 +56,7 @@ nvbios_boostTe(struct nouveau_bios *bios,
}
u16
-nvbios_boostEe(struct nouveau_bios *bios, int idx,
+nvbios_boostEe(struct nvkm_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 snr, ssz;
@@ -73,7 +72,7 @@ nvbios_boostEe(struct nouveau_bios *bios, int idx,
}
u16
-nvbios_boostEp(struct nouveau_bios *bios, int idx,
+nvbios_boostEp(struct nvkm_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info)
{
u16 data = nvbios_boostEe(bios, idx, ver, hdr, cnt, len);
@@ -87,7 +86,7 @@ nvbios_boostEp(struct nouveau_bios *bios, int idx,
}
u16
-nvbios_boostEm(struct nouveau_bios *bios, u8 pstate,
+nvbios_boostEm(struct nvkm_bios *bios, u8 pstate,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info)
{
u32 data, idx = 0;
@@ -99,7 +98,7 @@ nvbios_boostEm(struct nouveau_bios *bios, u8 pstate,
}
u16
-nvbios_boostSe(struct nouveau_bios *bios, int idx,
+nvbios_boostSe(struct nvkm_bios *bios, int idx,
u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len)
{
if (data && idx < cnt) {
@@ -111,7 +110,7 @@ nvbios_boostSe(struct nouveau_bios *bios, int idx,
}
u16
-nvbios_boostSp(struct nouveau_bios *bios, int idx,
+nvbios_boostSp(struct nvkm_bios *bios, int idx,
u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len,
struct nvbios_boostS *info)
{
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.c
index 2ede3bcd96a1..706a1650a4f2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.c
@@ -21,15 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/device.h>
-
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/conn.h>
u32
-nvbios_connTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+nvbios_connTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u32 dcb = dcb_table(bios, ver, hdr, cnt, len);
if (dcb && *ver >= 0x30 && *hdr >= 0x16) {
@@ -46,7 +43,7 @@ nvbios_connTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
u32
-nvbios_connTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+nvbios_connTp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_connT *info)
{
u32 data = nvbios_connTe(bios, ver, hdr, cnt, len);
@@ -62,7 +59,7 @@ nvbios_connTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
}
u32
-nvbios_connEe(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len)
+nvbios_connEe(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u32 data = nvbios_connTe(bios, ver, &hdr, &cnt, len);
@@ -72,7 +69,7 @@ nvbios_connEe(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len)
}
u32
-nvbios_connEp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len,
+nvbios_connEp(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len,
struct nvbios_connE *info)
{
u32 data = nvbios_connEe(bios, idx, ver, len);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c
index d3b15327fbfd..16f7ad8a4f80 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/cstep.h>
u16
-nvbios_cstepTe(struct nouveau_bios *bios,
+nvbios_cstepTe(struct nvkm_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz)
{
struct bit_entry bit_P;
@@ -57,7 +56,7 @@ nvbios_cstepTe(struct nouveau_bios *bios,
}
u16
-nvbios_cstepEe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
+nvbios_cstepEe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr)
{
u8 cnt, len, xnr, xsz;
u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz);
@@ -70,7 +69,7 @@ nvbios_cstepEe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
}
u16
-nvbios_cstepEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
+nvbios_cstepEp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr,
struct nvbios_cstepE *info)
{
u16 data = nvbios_cstepEe(bios, idx, ver, hdr);
@@ -83,7 +82,7 @@ nvbios_cstepEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
}
u16
-nvbios_cstepEm(struct nouveau_bios *bios, u8 pstate, u8 *ver, u8 *hdr,
+nvbios_cstepEm(struct nvkm_bios *bios, u8 pstate, u8 *ver, u8 *hdr,
struct nvbios_cstepE *info)
{
u32 data, idx = 0;
@@ -95,7 +94,7 @@ nvbios_cstepEm(struct nouveau_bios *bios, u8 pstate, u8 *ver, u8 *hdr,
}
u16
-nvbios_cstepXe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
+nvbios_cstepXe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr)
{
u8 cnt, len, xnr, xsz;
u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz);
@@ -108,7 +107,7 @@ nvbios_cstepXe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
}
u16
-nvbios_cstepXp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
+nvbios_cstepXp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr,
struct nvbios_cstepX *info)
{
u16 data = nvbios_cstepXe(bios, idx, ver, hdr);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c
index 96099aff8b41..8d78140f9401 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c
@@ -21,16 +21,15 @@
*
* Authors: Ben Skeggs
*/
+#include <subdev/bios.h>
+#include <subdev/bios/dcb.h>
-#include "core/device.h"
-
-#include "subdev/bios.h"
-#include "subdev/bios/dcb.h"
+#include <core/device.h>
u16
-dcb_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+dcb_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
- struct nouveau_device *device = nv_device(bios);
+ struct nvkm_device *device = nv_device(bios);
u16 dcb = 0x0000;
if (device->card_type > NV_04)
@@ -98,7 +97,7 @@ dcb_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
u16
-dcb_outp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len)
+dcb_outp(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 dcb = dcb_table(bios, ver, &hdr, &cnt, len);
@@ -120,7 +119,7 @@ dcb_outp_hashm(struct dcb_output *outp)
}
u16
-dcb_outp_parse(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len,
+dcb_outp_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len,
struct dcb_output *outp)
{
u16 dcb = dcb_outp(bios, idx, ver, len);
@@ -194,7 +193,7 @@ dcb_outp_parse(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len,
}
u16
-dcb_outp_match(struct nouveau_bios *bios, u16 type, u16 mask,
+dcb_outp_match(struct nvkm_bios *bios, u16 type, u16 mask,
u8 *ver, u8 *len, struct dcb_output *outp)
{
u16 dcb, idx = 0;
@@ -208,8 +207,8 @@ dcb_outp_match(struct nouveau_bios *bios, u16 type, u16 mask,
}
int
-dcb_outp_foreach(struct nouveau_bios *bios, void *data,
- int (*exec)(struct nouveau_bios *, void *, int, u16))
+dcb_outp_foreach(struct nvkm_bios *bios, void *data,
+ int (*exec)(struct nvkm_bios *, void *, int, u16))
{
int ret, idx = -1;
u8 ver, len;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c
index 51f355599694..262c410b7ee2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/disp.h>
u16
-nvbios_disp_table(struct nouveau_bios *bios,
+nvbios_disp_table(struct nvkm_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *sub)
{
struct bit_entry U;
@@ -57,8 +56,7 @@ nvbios_disp_table(struct nouveau_bios *bios,
}
u16
-nvbios_disp_entry(struct nouveau_bios *bios, u8 idx,
- u8 *ver, u8 *len, u8 *sub)
+nvbios_disp_entry(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len, u8 *sub)
{
u8 hdr, cnt;
u16 data = nvbios_disp_table(bios, ver, &hdr, &cnt, len, sub);
@@ -69,8 +67,7 @@ nvbios_disp_entry(struct nouveau_bios *bios, u8 idx,
}
u16
-nvbios_disp_parse(struct nouveau_bios *bios, u8 idx,
- u8 *ver, u8 *len, u8 *sub,
+nvbios_disp_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len, u8 *sub,
struct nvbios_disp *info)
{
u16 data = nvbios_disp_entry(bios, idx, ver, len, sub);
@@ -82,7 +79,7 @@ nvbios_disp_parse(struct nouveau_bios *bios, u8 idx,
}
u16
-nvbios_outp_entry(struct nouveau_bios *bios, u8 idx,
+nvbios_outp_entry(struct nvkm_bios *bios, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct nvbios_disp info;
@@ -96,9 +93,8 @@ nvbios_outp_entry(struct nouveau_bios *bios, u8 idx,
}
u16
-nvbios_outp_parse(struct nouveau_bios *bios, u8 idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_outp *info)
+nvbios_outp_parse(struct nvkm_bios *bios, u8 idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *info)
{
u16 data = nvbios_outp_entry(bios, idx, ver, hdr, cnt, len);
if (data && *hdr >= 0x0a) {
@@ -117,9 +113,8 @@ nvbios_outp_parse(struct nouveau_bios *bios, u8 idx,
}
u16
-nvbios_outp_match(struct nouveau_bios *bios, u16 type, u16 mask,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_outp *info)
+nvbios_outp_match(struct nvkm_bios *bios, u16 type, u16 mask,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *info)
{
u16 data, idx = 0;
while ((data = nvbios_outp_parse(bios, idx++, ver, hdr, cnt, len, info)) || *ver) {
@@ -132,7 +127,7 @@ nvbios_outp_match(struct nouveau_bios *bios, u16 type, u16 mask,
}
u16
-nvbios_ocfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx,
+nvbios_ocfg_entry(struct nvkm_bios *bios, u16 outp, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
if (idx < *cnt)
@@ -141,9 +136,8 @@ nvbios_ocfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx,
}
u16
-nvbios_ocfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_ocfg *info)
+nvbios_ocfg_parse(struct nvkm_bios *bios, u16 outp, u8 idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *info)
{
u16 data = nvbios_ocfg_entry(bios, outp, idx, ver, hdr, cnt, len);
if (data) {
@@ -155,9 +149,8 @@ nvbios_ocfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx,
}
u16
-nvbios_ocfg_match(struct nouveau_bios *bios, u16 outp, u16 type,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_ocfg *info)
+nvbios_ocfg_match(struct nvkm_bios *bios, u16 outp, u16 type,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *info)
{
u16 data, idx = 0;
while ((data = nvbios_ocfg_parse(bios, outp, idx++, ver, hdr, cnt, len, info))) {
@@ -168,7 +161,7 @@ nvbios_ocfg_match(struct nouveau_bios *bios, u16 outp, u16 type,
}
u16
-nvbios_oclk_match(struct nouveau_bios *bios, u16 cmp, u32 khz)
+nvbios_oclk_match(struct nvkm_bios *bios, u16 cmp, u32 khz)
{
while (cmp) {
if (khz / 10 >= nv_ro16(bios, cmp + 0x00))
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c
index cef53f81f12b..95970faae6c8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c
@@ -21,14 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
-
-#include "subdev/bios.h"
-#include "subdev/bios/bit.h"
-#include "subdev/bios/dp.h"
+#include <subdev/bios.h>
+#include <subdev/bios/bit.h>
+#include <subdev/bios/dp.h>
static u16
-nvbios_dp_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+nvbios_dp_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry d;
@@ -57,7 +55,7 @@ nvbios_dp_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
static u16
-nvbios_dpout_entry(struct nouveau_bios *bios, u8 idx,
+nvbios_dpout_entry(struct nvkm_bios *bios, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u16 data = nvbios_dp_table(bios, ver, hdr, cnt, len);
@@ -86,7 +84,7 @@ nvbios_dpout_entry(struct nouveau_bios *bios, u8 idx,
}
u16
-nvbios_dpout_parse(struct nouveau_bios *bios, u8 idx,
+nvbios_dpout_parse(struct nvkm_bios *bios, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_dpout *info)
{
@@ -128,7 +126,7 @@ nvbios_dpout_parse(struct nouveau_bios *bios, u8 idx,
}
u16
-nvbios_dpout_match(struct nouveau_bios *bios, u16 type, u16 mask,
+nvbios_dpout_match(struct nvkm_bios *bios, u16 type, u16 mask,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_dpout *info)
{
@@ -143,7 +141,7 @@ nvbios_dpout_match(struct nouveau_bios *bios, u16 type, u16 mask,
}
static u16
-nvbios_dpcfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx,
+nvbios_dpcfg_entry(struct nvkm_bios *bios, u16 outp, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
if (*ver >= 0x40) {
@@ -160,7 +158,7 @@ nvbios_dpcfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx,
}
u16
-nvbios_dpcfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx,
+nvbios_dpcfg_parse(struct nvkm_bios *bios, u16 outp, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_dpcfg *info)
{
@@ -190,7 +188,7 @@ nvbios_dpcfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx,
}
u16
-nvbios_dpcfg_match(struct nouveau_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe,
+nvbios_dpcfg_match(struct nvkm_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_dpcfg *info)
{
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c
index 49285d4f7ca5..a8503a1854c4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c
@@ -21,13 +21,12 @@
*
* Authors: Martin Peres
*/
-
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/extdev.h>
static u16
-extdev_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
+extdev_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
{
u8 dcb_ver, dcb_hdr, dcb_cnt, dcb_len;
u16 dcb, extdev = 0;
@@ -44,12 +43,11 @@ extdev_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
*hdr = nv_ro08(bios, extdev + 1);
*cnt = nv_ro08(bios, extdev + 2);
*len = nv_ro08(bios, extdev + 3);
-
return extdev + *hdr;
}
static u16
-nvbios_extdev_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
+nvbios_extdev_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 extdev = extdev_table(bios, ver, &hdr, len, &cnt);
@@ -59,8 +57,8 @@ nvbios_extdev_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
}
static void
-extdev_parse_entry(struct nouveau_bios *bios, u16 offset,
- struct nvbios_extdev_func *entry)
+extdev_parse_entry(struct nvkm_bios *bios, u16 offset,
+ struct nvbios_extdev_func *entry)
{
entry->type = nv_ro08(bios, offset + 0);
entry->addr = nv_ro08(bios, offset + 1);
@@ -68,7 +66,7 @@ extdev_parse_entry(struct nouveau_bios *bios, u16 offset,
}
int
-nvbios_extdev_parse(struct nouveau_bios *bios, int idx,
+nvbios_extdev_parse(struct nvkm_bios *bios, int idx,
struct nvbios_extdev_func *func)
{
u8 ver, len;
@@ -78,12 +76,11 @@ nvbios_extdev_parse(struct nouveau_bios *bios, int idx,
return -EINVAL;
extdev_parse_entry(bios, entry, func);
-
return 0;
}
int
-nvbios_extdev_find(struct nouveau_bios *bios, enum nvbios_extdev_type type,
+nvbios_extdev_find(struct nvkm_bios *bios, enum nvbios_extdev_type type,
struct nvbios_extdev_func *func)
{
u8 ver, len, i;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c
index e419892240f5..8dba70d9d9a9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c
@@ -21,13 +21,12 @@
*
* Authors: Martin Peres
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/fan.h>
u16
-nvbios_fan_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+nvbios_fan_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry bit_P;
u16 fan = 0x0000;
@@ -54,7 +53,7 @@ nvbios_fan_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
u16
-nvbios_fan_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
+nvbios_fan_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len)
{
u16 data = nvbios_fan_table(bios, ver, hdr, cnt, len);
@@ -64,7 +63,7 @@ nvbios_fan_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
}
u16
-nvbios_fan_parse(struct nouveau_bios *bios, struct nvbios_therm_fan *fan)
+nvbios_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan)
{
u8 ver, hdr, cnt, len;
@@ -89,5 +88,6 @@ nvbios_fan_parse(struct nouveau_bios *bios, struct nvbios_therm_fan *fan)
fan->pwm_freq = nv_ro32(bios, data + 0x0b) & 0xffffff;
}
+
return data;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.c
index 172a4f999990..8ce154d88f51 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.c
@@ -21,14 +21,13 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/gpio.h>
#include <subdev/bios/xpio.h>
u16
-dcb_gpio_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+dcb_gpio_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u16 data = 0x0000;
u16 dcb = dcb_table(bios, ver, hdr, cnt, len);
@@ -59,7 +58,7 @@ dcb_gpio_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
u16
-dcb_gpio_entry(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len)
+dcb_gpio_entry(struct nvkm_bios *bios, int idx, int ent, u8 *ver, u8 *len)
{
u8 hdr, cnt, xver; /* use gpio version for xpio entry parsing */
u16 gpio;
@@ -71,11 +70,12 @@ dcb_gpio_entry(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len)
if (gpio && ent < cnt)
return gpio + hdr + (ent * *len);
+
return 0x0000;
}
u16
-dcb_gpio_parse(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len,
+dcb_gpio_parse(struct nvkm_bios *bios, int idx, int ent, u8 *ver, u8 *len,
struct dcb_gpio_func *gpio)
{
u16 data = dcb_gpio_entry(bios, idx, ent, ver, len);
@@ -116,7 +116,7 @@ dcb_gpio_parse(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len,
}
u16
-dcb_gpio_match(struct nouveau_bios *bios, int idx, u8 func, u8 line,
+dcb_gpio_match(struct nvkm_bios *bios, int idx, u8 func, u8 line,
u8 *ver, u8 *len, struct dcb_gpio_func *gpio)
{
u8 hdr, cnt, i = 0;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c
index 282320ba9264..d1a89b2bd5c1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c
@@ -21,14 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
-
-#include "subdev/bios.h"
-#include "subdev/bios/dcb.h"
-#include "subdev/bios/i2c.h"
+#include <subdev/bios.h>
+#include <subdev/bios/dcb.h>
+#include <subdev/bios/i2c.h>
u16
-dcb_i2c_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+dcb_i2c_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u16 i2c = 0x0000;
u16 dcb = dcb_table(bios, ver, hdr, cnt, len);
@@ -60,7 +58,7 @@ dcb_i2c_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
u16
-dcb_i2c_entry(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len)
+dcb_i2c_entry(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 i2c = dcb_i2c_table(bios, ver, &hdr, &cnt, len);
@@ -70,7 +68,7 @@ dcb_i2c_entry(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len)
}
int
-dcb_i2c_parse(struct nouveau_bios *bios, u8 idx, struct dcb_i2c_entry *info)
+dcb_i2c_parse(struct nvkm_bios *bios, u8 idx, struct dcb_i2c_entry *info)
{
u8 ver, len;
u16 ent = dcb_i2c_entry(bios, idx, &ver, &len);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c
index 373f9a564ac9..1815540a0e8b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c
@@ -21,14 +21,13 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
#include <subdev/bios.h>
#include <subdev/bios/image.h>
#include <subdev/bios/pcir.h>
#include <subdev/bios/npde.h>
static bool
-nvbios_imagen(struct nouveau_bios *bios, struct nvbios_image *image)
+nvbios_imagen(struct nvkm_bios *bios, struct nvbios_image *image)
{
struct nvbios_pcirT pcir;
struct nvbios_npdeT npde;
@@ -66,7 +65,7 @@ nvbios_imagen(struct nouveau_bios *bios, struct nvbios_image *image)
}
bool
-nvbios_image(struct nouveau_bios *bios, int idx, struct nvbios_image *image)
+nvbios_image(struct nvkm_bios *bios, int idx, struct nvbios_image *image)
{
memset(image, 0x00, sizeof(*image));
do {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
index c6579ef32cd1..63c9607a0116 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
@@ -1,9 +1,29 @@
-#include <core/engine.h>
-#include <core/device.h>
-
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
#include <subdev/bios.h>
-#include <subdev/bios/bmp.h>
#include <subdev/bios/bit.h>
+#include <subdev/bios/bmp.h>
#include <subdev/bios/conn.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/dp.h>
@@ -11,9 +31,9 @@
#include <subdev/bios/init.h>
#include <subdev/bios/ramcfg.h>
#include <subdev/devinit.h>
+#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/vga.h>
-#include <subdev/gpio.h>
#define bioslog(lvl, fmt, args...) do { \
nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
@@ -97,7 +117,7 @@ init_crtc(struct nvbios_init *init)
static u8
init_conn(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
struct nvbios_connE connE;
u8 ver, hdr;
u32 conn;
@@ -119,7 +139,7 @@ init_conn(struct nvbios_init *init)
static inline u32
init_nvreg(struct nvbios_init *init, u32 reg)
{
- struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
+ struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
/* C51 (at least) sometimes has the lower bits set which the VBIOS
* interprets to mean that access needs to go through certain IO
@@ -203,7 +223,7 @@ init_wrport(struct nvbios_init *init, u16 port, u8 value)
static u8
init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
{
- struct nouveau_subdev *subdev = init->subdev;
+ struct nvkm_subdev *subdev = init->subdev;
if (init_exec(init)) {
int head = init->crtc < 0 ? 0 : init->crtc;
return nv_rdvgai(subdev, head, port, index);
@@ -232,10 +252,10 @@ init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
}
}
-static struct nouveau_i2c_port *
+static struct nvkm_i2c_port *
init_i2c(struct nvbios_init *init, int index)
{
- struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
+ struct nvkm_i2c *i2c = nvkm_i2c(init->bios);
if (index == 0xff) {
index = NV_I2C_DEFAULT(0);
@@ -265,7 +285,7 @@ init_i2c(struct nvbios_init *init, int index)
static int
init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
{
- struct nouveau_i2c_port *port = init_i2c(init, index);
+ struct nvkm_i2c_port *port = init_i2c(init, index);
if (port && init_exec(init))
return nv_rdi2cr(port, addr, reg);
return -ENODEV;
@@ -274,7 +294,7 @@ init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
static int
init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
{
- struct nouveau_i2c_port *port = init_i2c(init, index);
+ struct nvkm_i2c_port *port = init_i2c(init, index);
if (port && init_exec(init))
return nv_wri2cr(port, addr, reg, val);
return -ENODEV;
@@ -283,7 +303,7 @@ init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
static u8
init_rdauxr(struct nvbios_init *init, u32 addr)
{
- struct nouveau_i2c_port *port = init_i2c(init, -2);
+ struct nvkm_i2c_port *port = init_i2c(init, -2);
u8 data;
if (port && init_exec(init)) {
@@ -299,7 +319,7 @@ init_rdauxr(struct nvbios_init *init, u32 addr)
static int
init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
{
- struct nouveau_i2c_port *port = init_i2c(init, -2);
+ struct nvkm_i2c_port *port = init_i2c(init, -2);
if (port && init_exec(init)) {
int ret = nv_wraux(port, addr, &data, 1);
if (ret)
@@ -312,7 +332,7 @@ init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
static void
init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
{
- struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
+ struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
if (devinit->pll_set && init_exec(init)) {
int ret = devinit->pll_set(devinit, id, freq);
if (ret)
@@ -325,7 +345,7 @@ init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
*****************************************************************************/
static u16
-init_table(struct nouveau_bios *bios, u16 *len)
+init_table(struct nvkm_bios *bios, u16 *len)
{
struct bit_entry bit_I;
@@ -345,7 +365,7 @@ init_table(struct nouveau_bios *bios, u16 *len)
static u16
init_table_(struct nvbios_init *init, u16 offset, const char *name)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 len, data = init_table(bios, &len);
if (data) {
if (len >= offset + 2) {
@@ -375,7 +395,7 @@ init_table_(struct nvbios_init *init, u16 offset, const char *name)
#define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
static u16
-init_script(struct nouveau_bios *bios, int index)
+init_script(struct nvkm_bios *bios, int index)
{
struct nvbios_init init = { .bios = bios };
u16 bmp_ver = bmp_version(bios), data;
@@ -396,7 +416,7 @@ init_script(struct nouveau_bios *bios, int index)
}
static u16
-init_unknown_script(struct nouveau_bios *bios)
+init_unknown_script(struct nvkm_bios *bios)
{
u16 len, data = init_table(bios, &len);
if (data && len >= 16)
@@ -429,7 +449,7 @@ init_ram_restrict(struct nvbios_init *init)
static u8
init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 table = init_xlat_table(init);
if (table) {
u16 data = nv_ro16(bios, table + (index * 2));
@@ -447,7 +467,7 @@ init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
static bool
init_condition_met(struct nvbios_init *init, u8 cond)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 table = init_condition_table(init);
if (table) {
u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
@@ -463,7 +483,7 @@ init_condition_met(struct nvbios_init *init, u8 cond)
static bool
init_io_condition_met(struct nvbios_init *init, u8 cond)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 table = init_io_condition_table(init);
if (table) {
u16 port = nv_ro16(bios, table + (cond * 5) + 0);
@@ -480,7 +500,7 @@ init_io_condition_met(struct nvbios_init *init, u8 cond)
static bool
init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 table = init_io_flag_condition_table(init);
if (table) {
u16 port = nv_ro16(bios, table + (cond * 9) + 0);
@@ -515,7 +535,6 @@ init_tmds_reg(struct nvbios_init *init, u8 tmds)
* CR58 for CR57 = 0 to index a table of offsets to the basic
* 0x6808b0 address, and then flip the offset by 8.
*/
-
const int pramdac_offset[13] = {
0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
const u32 pramdac_table[4] = {
@@ -589,7 +608,7 @@ init_done(struct nvbios_init *init)
static void
init_io_restrict_prog(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 port = nv_ro16(bios, init->offset + 1);
u8 index = nv_ro08(bios, init->offset + 3);
u8 mask = nv_ro08(bios, init->offset + 4);
@@ -626,7 +645,7 @@ init_io_restrict_prog(struct nvbios_init *init)
static void
init_repeat(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 count = nv_ro08(bios, init->offset + 1);
u16 repeat = init->repeat;
@@ -652,7 +671,7 @@ init_repeat(struct nvbios_init *init)
static void
init_io_restrict_pll(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 port = nv_ro16(bios, init->offset + 1);
u8 index = nv_ro08(bios, init->offset + 3);
u8 mask = nv_ro08(bios, init->offset + 4);
@@ -708,7 +727,7 @@ init_end_repeat(struct nvbios_init *init)
static void
init_copy(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 reg = nv_ro32(bios, init->offset + 1);
u8 shift = nv_ro08(bios, init->offset + 5);
u8 smask = nv_ro08(bios, init->offset + 6);
@@ -747,7 +766,7 @@ init_not(struct nvbios_init *init)
static void
init_io_flag_condition(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 cond = nv_ro08(bios, init->offset + 1);
trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
@@ -764,7 +783,7 @@ init_io_flag_condition(struct nvbios_init *init)
static void
init_dp_condition(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
struct nvbios_dpout info;
u8 cond = nv_ro08(bios, init->offset + 1);
u8 unkn = nv_ro08(bios, init->offset + 2);
@@ -812,7 +831,7 @@ init_dp_condition(struct nvbios_init *init)
static void
init_io_mask_or(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 index = nv_ro08(bios, init->offset + 1);
u8 or = init_or(init);
u8 data;
@@ -831,7 +850,7 @@ init_io_mask_or(struct nvbios_init *init)
static void
init_io_or(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 index = nv_ro08(bios, init->offset + 1);
u8 or = init_or(init);
u8 data;
@@ -850,7 +869,7 @@ init_io_or(struct nvbios_init *init)
static void
init_andn_reg(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 reg = nv_ro32(bios, init->offset + 1);
u32 mask = nv_ro32(bios, init->offset + 5);
@@ -867,7 +886,7 @@ init_andn_reg(struct nvbios_init *init)
static void
init_or_reg(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 reg = nv_ro32(bios, init->offset + 1);
u32 mask = nv_ro32(bios, init->offset + 5);
@@ -884,7 +903,7 @@ init_or_reg(struct nvbios_init *init)
static void
init_idx_addr_latched(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 creg = nv_ro32(bios, init->offset + 1);
u32 dreg = nv_ro32(bios, init->offset + 5);
u32 mask = nv_ro32(bios, init->offset + 9);
@@ -914,7 +933,7 @@ init_idx_addr_latched(struct nvbios_init *init)
static void
init_io_restrict_pll2(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 port = nv_ro16(bios, init->offset + 1);
u8 index = nv_ro08(bios, init->offset + 3);
u8 mask = nv_ro08(bios, init->offset + 4);
@@ -949,7 +968,7 @@ init_io_restrict_pll2(struct nvbios_init *init)
static void
init_pll2(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 reg = nv_ro32(bios, init->offset + 1);
u32 freq = nv_ro32(bios, init->offset + 5);
@@ -966,7 +985,7 @@ init_pll2(struct nvbios_init *init)
static void
init_i2c_byte(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 index = nv_ro08(bios, init->offset + 1);
u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
u8 count = nv_ro08(bios, init->offset + 3);
@@ -997,7 +1016,7 @@ init_i2c_byte(struct nvbios_init *init)
static void
init_zm_i2c_byte(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 index = nv_ro08(bios, init->offset + 1);
u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
u8 count = nv_ro08(bios, init->offset + 3);
@@ -1014,7 +1033,6 @@ init_zm_i2c_byte(struct nvbios_init *init)
init_wri2cr(init, index, addr, reg, data);
}
-
}
/**
@@ -1024,7 +1042,7 @@ init_zm_i2c_byte(struct nvbios_init *init)
static void
init_zm_i2c(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 index = nv_ro08(bios, init->offset + 1);
u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
u8 count = nv_ro08(bios, init->offset + 3);
@@ -1040,7 +1058,7 @@ init_zm_i2c(struct nvbios_init *init)
}
if (init_exec(init)) {
- struct nouveau_i2c_port *port = init_i2c(init, index);
+ struct nvkm_i2c_port *port = init_i2c(init, index);
struct i2c_msg msg = {
.addr = addr, .flags = 0, .len = count, .buf = data,
};
@@ -1058,7 +1076,7 @@ init_zm_i2c(struct nvbios_init *init)
static void
init_tmds(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 tmds = nv_ro08(bios, init->offset + 1);
u8 addr = nv_ro08(bios, init->offset + 2);
u8 mask = nv_ro08(bios, init->offset + 3);
@@ -1084,7 +1102,7 @@ init_tmds(struct nvbios_init *init)
static void
init_zm_tmds_group(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 tmds = nv_ro08(bios, init->offset + 1);
u8 count = nv_ro08(bios, init->offset + 2);
u32 reg = init_tmds_reg(init, tmds);
@@ -1111,7 +1129,7 @@ init_zm_tmds_group(struct nvbios_init *init)
static void
init_cr_idx_adr_latch(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 addr0 = nv_ro08(bios, init->offset + 1);
u8 addr1 = nv_ro08(bios, init->offset + 2);
u8 base = nv_ro08(bios, init->offset + 3);
@@ -1141,7 +1159,7 @@ init_cr_idx_adr_latch(struct nvbios_init *init)
static void
init_cr(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 addr = nv_ro08(bios, init->offset + 1);
u8 mask = nv_ro08(bios, init->offset + 2);
u8 data = nv_ro08(bios, init->offset + 3);
@@ -1161,7 +1179,7 @@ init_cr(struct nvbios_init *init)
static void
init_zm_cr(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 addr = nv_ro08(bios, init->offset + 1);
u8 data = nv_ro08(bios, init->offset + 2);
@@ -1178,7 +1196,7 @@ init_zm_cr(struct nvbios_init *init)
static void
init_zm_cr_group(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 count = nv_ro08(bios, init->offset + 1);
trace("ZM_CR_GROUP\n");
@@ -1202,7 +1220,7 @@ init_zm_cr_group(struct nvbios_init *init)
static void
init_condition_time(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 cond = nv_ro08(bios, init->offset + 1);
u8 retry = nv_ro08(bios, init->offset + 2);
u8 wait = min((u16)retry * 50, 100);
@@ -1229,7 +1247,7 @@ init_condition_time(struct nvbios_init *init)
static void
init_ltime(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 msec = nv_ro16(bios, init->offset + 1);
trace("LTIME\t0x%04x\n", msec);
@@ -1246,7 +1264,7 @@ init_ltime(struct nvbios_init *init)
static void
init_zm_reg_sequence(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 base = nv_ro32(bios, init->offset + 1);
u8 count = nv_ro08(bios, init->offset + 5);
@@ -1271,7 +1289,7 @@ init_zm_reg_sequence(struct nvbios_init *init)
static void
init_sub_direct(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 addr = nv_ro16(bios, init->offset + 1);
u16 save;
@@ -1297,7 +1315,7 @@ init_sub_direct(struct nvbios_init *init)
static void
init_jump(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 offset = nv_ro16(bios, init->offset + 1);
trace("JUMP\t0x%04x\n", offset);
@@ -1315,7 +1333,7 @@ init_jump(struct nvbios_init *init)
static void
init_i2c_if(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 index = nv_ro08(bios, init->offset + 1);
u8 addr = nv_ro08(bios, init->offset + 2);
u8 reg = nv_ro08(bios, init->offset + 3);
@@ -1342,7 +1360,7 @@ init_i2c_if(struct nvbios_init *init)
static void
init_copy_nv_reg(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 sreg = nv_ro32(bios, init->offset + 1);
u8 shift = nv_ro08(bios, init->offset + 5);
u32 smask = nv_ro32(bios, init->offset + 6);
@@ -1368,7 +1386,7 @@ init_copy_nv_reg(struct nvbios_init *init)
static void
init_zm_index_io(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 port = nv_ro16(bios, init->offset + 1);
u8 index = nv_ro08(bios, init->offset + 3);
u8 data = nv_ro08(bios, init->offset + 4);
@@ -1386,7 +1404,7 @@ init_zm_index_io(struct nvbios_init *init)
static void
init_compute_mem(struct nvbios_init *init)
{
- struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
+ struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
trace("COMPUTE_MEM\n");
init->offset += 1;
@@ -1404,7 +1422,7 @@ init_compute_mem(struct nvbios_init *init)
static void
init_reset(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 reg = nv_ro32(bios, init->offset + 1);
u32 data1 = nv_ro32(bios, init->offset + 5);
u32 data2 = nv_ro32(bios, init->offset + 9);
@@ -1440,7 +1458,7 @@ init_configure_mem_clk(struct nvbios_init *init)
static void
init_configure_mem(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 mdata, sdata;
u32 addr, data;
@@ -1490,7 +1508,7 @@ init_configure_mem(struct nvbios_init *init)
static void
init_configure_clk(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 mdata, clock;
trace("CONFIGURE_CLK\n");
@@ -1524,7 +1542,7 @@ init_configure_clk(struct nvbios_init *init)
static void
init_configure_preinit(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 strap;
trace("CONFIGURE_PREINIT\n");
@@ -1550,7 +1568,7 @@ init_configure_preinit(struct nvbios_init *init)
static void
init_io(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 port = nv_ro16(bios, init->offset + 1);
u8 mask = nv_ro16(bios, init->offset + 3);
u8 data = nv_ro16(bios, init->offset + 4);
@@ -1590,7 +1608,7 @@ init_io(struct nvbios_init *init)
static void
init_sub(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 index = nv_ro08(bios, init->offset + 1);
u16 addr, save;
@@ -1617,7 +1635,7 @@ init_sub(struct nvbios_init *init)
static void
init_ram_condition(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 mask = nv_ro08(bios, init->offset + 1);
u8 value = nv_ro08(bios, init->offset + 2);
@@ -1636,7 +1654,7 @@ init_ram_condition(struct nvbios_init *init)
static void
init_nv_reg(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 reg = nv_ro32(bios, init->offset + 1);
u32 mask = nv_ro32(bios, init->offset + 5);
u32 data = nv_ro32(bios, init->offset + 9);
@@ -1654,7 +1672,7 @@ init_nv_reg(struct nvbios_init *init)
static void
init_macro(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 macro = nv_ro08(bios, init->offset + 1);
u16 table;
@@ -1690,7 +1708,7 @@ init_resume(struct nvbios_init *init)
static void
init_time(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 usec = nv_ro16(bios, init->offset + 1);
trace("TIME\t0x%04x\n", usec);
@@ -1711,7 +1729,7 @@ init_time(struct nvbios_init *init)
static void
init_condition(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 cond = nv_ro08(bios, init->offset + 1);
trace("CONDITION\t0x%02x\n", cond);
@@ -1728,7 +1746,7 @@ init_condition(struct nvbios_init *init)
static void
init_io_condition(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 cond = nv_ro08(bios, init->offset + 1);
trace("IO_CONDITION\t0x%02x\n", cond);
@@ -1745,7 +1763,7 @@ init_io_condition(struct nvbios_init *init)
static void
init_index_io(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u16 port = nv_ro16(bios, init->offset + 1);
u8 index = nv_ro16(bios, init->offset + 3);
u8 mask = nv_ro08(bios, init->offset + 4);
@@ -1767,7 +1785,7 @@ init_index_io(struct nvbios_init *init)
static void
init_pll(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 reg = nv_ro32(bios, init->offset + 1);
u32 freq = nv_ro16(bios, init->offset + 5) * 10;
@@ -1784,7 +1802,7 @@ init_pll(struct nvbios_init *init)
static void
init_zm_reg(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 addr = nv_ro32(bios, init->offset + 1);
u32 data = nv_ro32(bios, init->offset + 5);
@@ -1804,7 +1822,7 @@ init_zm_reg(struct nvbios_init *init)
static void
init_ram_restrict_pll(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 type = nv_ro08(bios, init->offset + 1);
u8 count = init_ram_restrict_group_count(init);
u8 strap = init_ram_restrict(init);
@@ -1834,7 +1852,7 @@ init_ram_restrict_pll(struct nvbios_init *init)
static void
init_gpio(struct nvbios_init *init)
{
- struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
+ struct nvkm_gpio *gpio = nvkm_gpio(init->bios);
trace("GPIO\n");
init->offset += 1;
@@ -1850,7 +1868,7 @@ init_gpio(struct nvbios_init *init)
static void
init_ram_restrict_zm_reg_group(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 addr = nv_ro32(bios, init->offset + 1);
u8 incr = nv_ro08(bios, init->offset + 5);
u8 num = nv_ro08(bios, init->offset + 6);
@@ -1888,7 +1906,7 @@ init_ram_restrict_zm_reg_group(struct nvbios_init *init)
static void
init_copy_zm_reg(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 sreg = nv_ro32(bios, init->offset + 1);
u32 dreg = nv_ro32(bios, init->offset + 5);
@@ -1905,7 +1923,7 @@ init_copy_zm_reg(struct nvbios_init *init)
static void
init_zm_reg_group(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 addr = nv_ro32(bios, init->offset + 1);
u8 count = nv_ro08(bios, init->offset + 5);
@@ -1927,7 +1945,7 @@ init_zm_reg_group(struct nvbios_init *init)
static void
init_xlat(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 saddr = nv_ro32(bios, init->offset + 1);
u8 sshift = nv_ro08(bios, init->offset + 5);
u8 smask = nv_ro08(bios, init->offset + 6);
@@ -1955,7 +1973,7 @@ init_xlat(struct nvbios_init *init)
static void
init_zm_mask_add(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 addr = nv_ro32(bios, init->offset + 1);
u32 mask = nv_ro32(bios, init->offset + 5);
u32 add = nv_ro32(bios, init->offset + 9);
@@ -1976,7 +1994,7 @@ init_zm_mask_add(struct nvbios_init *init)
static void
init_auxch(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 addr = nv_ro32(bios, init->offset + 1);
u8 count = nv_ro08(bios, init->offset + 5);
@@ -2000,7 +2018,7 @@ init_auxch(struct nvbios_init *init)
static void
init_zm_auxch(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u32 addr = nv_ro32(bios, init->offset + 1);
u8 count = nv_ro08(bios, init->offset + 5);
@@ -2022,14 +2040,14 @@ init_zm_auxch(struct nvbios_init *init)
static void
init_i2c_long_if(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
+ struct nvkm_bios *bios = init->bios;
u8 index = nv_ro08(bios, init->offset + 1);
u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
u8 reglo = nv_ro08(bios, init->offset + 3);
u8 reghi = nv_ro08(bios, init->offset + 4);
u8 mask = nv_ro08(bios, init->offset + 5);
u8 data = nv_ro08(bios, init->offset + 6);
- struct nouveau_i2c_port *port;
+ struct nvkm_i2c_port *port;
trace("I2C_LONG_IF\t"
"I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
@@ -2061,8 +2079,8 @@ init_i2c_long_if(struct nvbios_init *init)
static void
init_gpio_ne(struct nvbios_init *init)
{
- struct nouveau_bios *bios = init->bios;
- struct nouveau_gpio *gpio = nouveau_gpio(bios);
+ struct nvkm_bios *bios = init->bios;
+ struct nvkm_gpio *gpio = nvkm_gpio(bios);
struct dcb_gpio_func func;
u8 count = nv_ro08(bios, init->offset + 1);
u8 idx = 0, ver, len;
@@ -2185,9 +2203,9 @@ nvbios_exec(struct nvbios_init *init)
}
int
-nvbios_init(struct nouveau_subdev *subdev, bool execute)
+nvbios_init(struct nvkm_subdev *subdev, bool execute)
{
- struct nouveau_bios *bios = nouveau_bios(subdev);
+ struct nvkm_bios *bios = nvkm_bios(subdev);
int ret = 0;
int i = -1;
u16 data;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c
index 2610b11a99b3..c4087df4f85e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/mxm.h>
u16
-mxm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr)
+mxm_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr)
{
struct bit_entry x;
@@ -51,28 +50,28 @@ mxm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr)
*
* MXM v3.x VBIOS are nicer and provide pointers to these tables.
*/
-static u8 nv84_sor_map[16] = {
+static u8 g84_sor_map[16] = {
0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
-static u8 nv92_sor_map[16] = {
+static u8 g92_sor_map[16] = {
0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31,
0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
-static u8 nv94_sor_map[16] = {
+static u8 g94_sor_map[16] = {
0x00, 0x14, 0x24, 0x11, 0x34, 0x31, 0x11, 0x31,
0x11, 0x31, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00
};
-static u8 nv98_sor_map[16] = {
+static u8 g98_sor_map[16] = {
0x00, 0x14, 0x12, 0x11, 0x00, 0x31, 0x11, 0x31,
0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
u8
-mxm_sor_map(struct nouveau_bios *bios, u8 conn)
+mxm_sor_map(struct nvkm_bios *bios, u8 conn)
{
u8 ver, hdr;
u16 mxm = mxm_table(bios, &ver, &hdr);
@@ -95,20 +94,20 @@ mxm_sor_map(struct nouveau_bios *bios, u8 conn)
}
if (bios->version.chip == 0x84 || bios->version.chip == 0x86)
- return nv84_sor_map[conn];
+ return g84_sor_map[conn];
if (bios->version.chip == 0x92)
- return nv92_sor_map[conn];
+ return g92_sor_map[conn];
if (bios->version.chip == 0x94 || bios->version.chip == 0x96)
- return nv94_sor_map[conn];
+ return g94_sor_map[conn];
if (bios->version.chip == 0x98)
- return nv98_sor_map[conn];
+ return g98_sor_map[conn];
nv_warn(bios, "missing sor map\n");
return 0x00;
}
u8
-mxm_ddc_map(struct nouveau_bios *bios, u8 port)
+mxm_ddc_map(struct nvkm_bios *bios, u8 port)
{
u8 ver, hdr;
u16 mxm = mxm_table(bios, &ver, &hdr);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c
index d694716a166c..fd7dd718b2bf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
#include <subdev/bios.h>
#include <subdev/bios/npde.h>
#include <subdev/bios/pcir.h>
u32
-nvbios_npdeTe(struct nouveau_bios *bios, u32 base)
+nvbios_npdeTe(struct nvkm_bios *bios, u32 base)
{
struct nvbios_pcirT pcir;
u8 ver; u16 hdr;
@@ -47,7 +46,7 @@ nvbios_npdeTe(struct nouveau_bios *bios, u32 base)
}
u32
-nvbios_npdeTp(struct nouveau_bios *bios, u32 base, struct nvbios_npdeT *info)
+nvbios_npdeTp(struct nvkm_bios *bios, u32 base, struct nvbios_npdeT *info)
{
u32 data = nvbios_npdeTe(bios, base);
memset(info, 0x00, sizeof(*info));
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c
index 91dae26bc50f..df5978753ae8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c
@@ -21,12 +21,11 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
#include <subdev/bios.h>
#include <subdev/bios/pcir.h>
u32
-nvbios_pcirTe(struct nouveau_bios *bios, u32 base, u8 *ver, u16 *hdr)
+nvbios_pcirTe(struct nvkm_bios *bios, u32 base, u8 *ver, u16 *hdr)
{
u32 data = nv_ro16(bios, base + 0x18);
if (data) {
@@ -49,7 +48,7 @@ nvbios_pcirTe(struct nouveau_bios *bios, u32 base, u8 *ver, u16 *hdr)
}
u32
-nvbios_pcirTp(struct nouveau_bios *bios, u32 base, u8 *ver, u16 *hdr,
+nvbios_pcirTp(struct nvkm_bios *bios, u32 base, u8 *ver, u16 *hdr,
struct nvbios_pcirT *info)
{
u32 data = nvbios_pcirTe(bios, base, ver, hdr);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c
index 675e221680aa..382ae9cdbf58 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c
@@ -21,13 +21,14 @@
*
* Authors: Martin Peres
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/perf.h>
+#include <core/device.h>
+
u16
-nvbios_perf_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr,
+nvbios_perf_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_P;
@@ -76,7 +77,7 @@ nvbios_perf_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr,
}
u16
-nvbios_perf_entry(struct nouveau_bios *bios, int idx,
+nvbios_perf_entry(struct nvkm_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 snr, ssz;
@@ -92,9 +93,8 @@ nvbios_perf_entry(struct nouveau_bios *bios, int idx,
}
u16
-nvbios_perfEp(struct nouveau_bios *bios, int idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_perfE *info)
+nvbios_perfEp(struct nvkm_bios *bios, int idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *info)
{
u16 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
@@ -155,7 +155,7 @@ nvbios_perfEp(struct nouveau_bios *bios, int idx,
}
u32
-nvbios_perfSe(struct nouveau_bios *bios, u32 perfE, int idx,
+nvbios_perfSe(struct nvkm_bios *bios, u32 perfE, int idx,
u8 *ver, u8 *hdr, u8 cnt, u8 len)
{
u32 data = 0x00000000;
@@ -167,7 +167,7 @@ nvbios_perfSe(struct nouveau_bios *bios, u32 perfE, int idx,
}
u32
-nvbios_perfSp(struct nouveau_bios *bios, u32 perfE, int idx,
+nvbios_perfSp(struct nvkm_bios *bios, u32 perfE, int idx,
u8 *ver, u8 *hdr, u8 cnt, u8 len,
struct nvbios_perfS *info)
{
@@ -184,7 +184,7 @@ nvbios_perfSp(struct nouveau_bios *bios, u32 perfE, int idx,
}
int
-nvbios_perf_fan_parse(struct nouveau_bios *bios,
+nvbios_perf_fan_parse(struct nvkm_bios *bios,
struct nvbios_perf_fan *fan)
{
u8 ver, hdr, cnt, len, snr, ssz;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c
index 1f76de597d4b..ebd402e19dbf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c
@@ -21,12 +21,13 @@
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
-
-#include <subdev/vga.h>
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/bmp.h>
#include <subdev/bios/pll.h>
+#include <subdev/vga.h>
+
+#include <core/device.h>
struct pll_mapping {
u8 type;
@@ -66,7 +67,7 @@ nv50_pll_mapping[] = {
};
static struct pll_mapping
-nv84_pll_mapping[] = {
+g84_pll_mapping[] = {
{ PLL_CORE , 0x004028 },
{ PLL_SHADER, 0x004020 },
{ PLL_MEMORY, 0x004008 },
@@ -78,7 +79,7 @@ nv84_pll_mapping[] = {
};
static u16
-pll_limits_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+pll_limits_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry bit_C;
@@ -109,7 +110,7 @@ pll_limits_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
static struct pll_mapping *
-pll_map(struct nouveau_bios *bios)
+pll_map(struct nvkm_bios *bios)
{
switch (nv_device(bios)->card_type) {
case NV_04:
@@ -128,14 +129,14 @@ pll_map(struct nouveau_bios *bios)
if (nv_device(bios)->chipset < 0xa3 ||
nv_device(bios)->chipset == 0xaa ||
nv_device(bios)->chipset == 0xac)
- return nv84_pll_mapping;
+ return g84_pll_mapping;
default:
return NULL;
}
}
static u16
-pll_map_reg(struct nouveau_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len)
+pll_map_reg(struct nvkm_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len)
{
struct pll_mapping *map;
u8 hdr, cnt;
@@ -177,7 +178,7 @@ pll_map_reg(struct nouveau_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len)
}
static u16
-pll_map_type(struct nouveau_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len)
+pll_map_type(struct nvkm_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len)
{
struct pll_mapping *map;
u8 hdr, cnt;
@@ -219,7 +220,7 @@ pll_map_type(struct nouveau_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len)
}
int
-nvbios_pll_parse(struct nouveau_bios *bios, u32 type, struct nvbios_pll *info)
+nvbios_pll_parse(struct nvkm_bios *bios, u32 type, struct nvbios_pll *info)
{
u8 ver, len;
u32 reg = type;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c
index 66c56ba07d1b..20c5ce0cd573 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c
@@ -21,14 +21,13 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/image.h>
#include <subdev/bios/pmu.h>
static u32
-weirdo_pointer(struct nouveau_bios *bios, u32 data)
+weirdo_pointer(struct nvkm_bios *bios, u32 data)
{
struct nvbios_image image;
int idx = 0;
@@ -43,7 +42,7 @@ weirdo_pointer(struct nouveau_bios *bios, u32 data)
}
u32
-nvbios_pmuTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+nvbios_pmuTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry bit_p;
u32 data = 0;
@@ -63,7 +62,7 @@ nvbios_pmuTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
u32
-nvbios_pmuTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+nvbios_pmuTp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_pmuT *info)
{
u32 data = nvbios_pmuTe(bios, ver, hdr, cnt, len);
@@ -76,7 +75,7 @@ nvbios_pmuTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
}
u32
-nvbios_pmuEe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
+nvbios_pmuEe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr)
{
u8 cnt, len;
u32 data = nvbios_pmuTe(bios, ver, hdr, &cnt, &len);
@@ -89,7 +88,7 @@ nvbios_pmuEe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
}
u32
-nvbios_pmuEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
+nvbios_pmuEp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr,
struct nvbios_pmuE *info)
{
u32 data = nvbios_pmuEe(bios, idx, ver, hdr);
@@ -104,7 +103,7 @@ nvbios_pmuEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
}
bool
-nvbios_pmuRm(struct nouveau_bios *bios, u8 type, struct nvbios_pmuR *info)
+nvbios_pmuRm(struct nvkm_bios *bios, u8 type, struct nvbios_pmuR *info)
{
struct nvbios_pmuE pmuE;
u8 ver, hdr, idx = 0;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h
index 187d225bd1e9..95e4fa1531d6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h
@@ -1,18 +1,17 @@
#ifndef __NVKM_BIOS_PRIV_H__
#define __NVKM_BIOS_PRIV_H__
-
#include <subdev/bios.h>
struct nvbios_source {
const char *name;
- void *(*init)(struct nouveau_bios *, const char *);
+ void *(*init)(struct nvkm_bios *, const char *);
void (*fini)(void *);
- u32 (*read)(void *, u32 offset, u32 length, struct nouveau_bios *);
+ u32 (*read)(void *, u32 offset, u32 length, struct nvkm_bios *);
bool rw;
};
-int nvbios_extend(struct nouveau_bios *, u32 length);
-int nvbios_shadow(struct nouveau_bios *);
+int nvbios_extend(struct nvkm_bios *, u32 length);
+int nvbios_shadow(struct nvkm_bios *);
extern const struct nvbios_source nvbios_rom;
extern const struct nvbios_source nvbios_ramin;
@@ -21,5 +20,4 @@ extern const struct nvbios_source nvbios_acpi_slow;
extern const struct nvbios_source nvbios_pcirom;
extern const struct nvbios_source nvbios_platform;
extern const struct nvbios_source nvbios_of;
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.c
index 1623c8dfe797..a17b221119b2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.c
@@ -21,20 +21,19 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/ramcfg.h>
#include <subdev/bios/M0203.h>
static u8
-nvbios_ramcfg_strap(struct nouveau_subdev *subdev)
+nvbios_ramcfg_strap(struct nvkm_subdev *subdev)
{
return (nv_rd32(subdev, 0x101000) & 0x0000003c) >> 2;
}
u8
-nvbios_ramcfg_count(struct nouveau_bios *bios)
+nvbios_ramcfg_count(struct nvkm_bios *bios)
{
struct bit_entry bit_M;
@@ -49,9 +48,9 @@ nvbios_ramcfg_count(struct nouveau_bios *bios)
}
u8
-nvbios_ramcfg_index(struct nouveau_subdev *subdev)
+nvbios_ramcfg_index(struct nvkm_subdev *subdev)
{
- struct nouveau_bios *bios = nouveau_bios(subdev);
+ struct nvkm_bios *bios = nvkm_bios(subdev);
u8 strap = nvbios_ramcfg_strap(subdev);
u32 xlat = 0x00000000;
struct bit_entry bit_M;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c
index c5685228c322..8b17bb4b220c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c
@@ -21,14 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
-#include <subdev/bios/ramcfg.h>
#include <subdev/bios/rammap.h>
u32
-nvbios_rammapTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr,
+nvbios_rammapTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_P;
@@ -59,7 +57,7 @@ nvbios_rammapTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr,
}
u32
-nvbios_rammapEe(struct nouveau_bios *bios, int idx,
+nvbios_rammapEe(struct nvkm_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 snr, ssz;
@@ -75,9 +73,8 @@ nvbios_rammapEe(struct nouveau_bios *bios, int idx,
}
u32
-nvbios_rammapEp(struct nouveau_bios *bios, int idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_ramcfg *p)
+nvbios_rammapEp(struct nvkm_bios *bios, int idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p)
{
u32 data = nvbios_rammapEe(bios, idx, ver, hdr, cnt, len), temp;
memset(p, 0x00, sizeof(*p));
@@ -118,9 +115,8 @@ nvbios_rammapEp(struct nouveau_bios *bios, int idx,
}
u32
-nvbios_rammapEm(struct nouveau_bios *bios, u16 mhz,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_ramcfg *info)
+nvbios_rammapEm(struct nvkm_bios *bios, u16 mhz,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *info)
{
int idx = 0;
u32 data;
@@ -132,9 +128,8 @@ nvbios_rammapEm(struct nouveau_bios *bios, u16 mhz,
}
u32
-nvbios_rammapSe(struct nouveau_bios *bios, u32 data,
- u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
- u8 *ver, u8 *hdr)
+nvbios_rammapSe(struct nvkm_bios *bios, u32 data,
+ u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, u8 *ver, u8 *hdr)
{
if (idx < ecnt) {
data = data + ehdr + (idx * elen);
@@ -146,7 +141,7 @@ nvbios_rammapSe(struct nouveau_bios *bios, u32 data,
}
u32
-nvbios_rammapSp(struct nouveau_bios *bios, u32 data,
+nvbios_rammapSp(struct nvkm_bios *bios, u32 data,
u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
u8 *ver, u8 *hdr, struct nvbios_ramcfg *p)
{
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
index bb9e0018d936..8c2b7cba5cff 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
@@ -21,13 +21,15 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
#include "priv.h"
+
+#include <core/device.h>
#include <core/option.h>
+#include <subdev/bios.h>
#include <subdev/bios/image.h>
struct shadow {
- struct nouveau_oclass base;
+ struct nvkm_oclass base;
u32 skip;
const struct nvbios_source *func;
void *data;
@@ -36,7 +38,7 @@ struct shadow {
};
static bool
-shadow_fetch(struct nouveau_bios *bios, u32 upto)
+shadow_fetch(struct nvkm_bios *bios, u32 upto)
{
struct shadow *mthd = (void *)nv_object(bios)->oclass;
const u32 limit = (upto + 3) & ~3;
@@ -50,36 +52,36 @@ shadow_fetch(struct nouveau_bios *bios, u32 upto)
}
static u8
-shadow_rd08(struct nouveau_object *object, u64 addr)
+shadow_rd08(struct nvkm_object *object, u64 addr)
{
- struct nouveau_bios *bios = (void *)object;
+ struct nvkm_bios *bios = (void *)object;
if (shadow_fetch(bios, addr + 1))
return bios->data[addr];
return 0x00;
}
static u16
-shadow_rd16(struct nouveau_object *object, u64 addr)
+shadow_rd16(struct nvkm_object *object, u64 addr)
{
- struct nouveau_bios *bios = (void *)object;
+ struct nvkm_bios *bios = (void *)object;
if (shadow_fetch(bios, addr + 2))
return get_unaligned_le16(&bios->data[addr]);
return 0x0000;
}
static u32
-shadow_rd32(struct nouveau_object *object, u64 addr)
+shadow_rd32(struct nvkm_object *object, u64 addr)
{
- struct nouveau_bios *bios = (void *)object;
+ struct nvkm_bios *bios = (void *)object;
if (shadow_fetch(bios, addr + 4))
return get_unaligned_le32(&bios->data[addr]);
return 0x00000000;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
shadow_class = {
.handle = NV_SUBDEV(VBIOS, 0x00),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.rd08 = shadow_rd08,
.rd16 = shadow_rd16,
.rd32 = shadow_rd32,
@@ -87,7 +89,7 @@ shadow_class = {
};
static int
-shadow_image(struct nouveau_bios *bios, int idx, struct shadow *mthd)
+shadow_image(struct nvkm_bios *bios, int idx, struct shadow *mthd)
{
struct nvbios_image image;
int score = 1;
@@ -126,9 +128,9 @@ shadow_image(struct nouveau_bios *bios, int idx, struct shadow *mthd)
}
static int
-shadow_score(struct nouveau_bios *bios, struct shadow *mthd)
+shadow_score(struct nvkm_bios *bios, struct shadow *mthd)
{
- struct nouveau_oclass *oclass = nv_object(bios)->oclass;
+ struct nvkm_oclass *oclass = nv_object(bios)->oclass;
int score;
nv_object(bios)->oclass = &mthd->base;
score = shadow_image(bios, 0, mthd);
@@ -138,7 +140,7 @@ shadow_score(struct nouveau_bios *bios, struct shadow *mthd)
}
static int
-shadow_method(struct nouveau_bios *bios, struct shadow *mthd, const char *name)
+shadow_method(struct nvkm_bios *bios, struct shadow *mthd, const char *name)
{
const struct nvbios_source *func = mthd->func;
if (func->name) {
@@ -163,7 +165,7 @@ shadow_method(struct nouveau_bios *bios, struct shadow *mthd, const char *name)
}
static u32
-shadow_fw_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
+shadow_fw_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
{
const struct firmware *fw = data;
if (offset + length <= fw->size) {
@@ -174,7 +176,7 @@ shadow_fw_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
}
static void *
-shadow_fw_init(struct nouveau_bios *bios, const char *name)
+shadow_fw_init(struct nvkm_bios *bios, const char *name)
{
struct device *dev = &nv_device(bios)->pdev->dev;
const struct firmware *fw;
@@ -194,7 +196,7 @@ shadow_fw = {
};
int
-nvbios_shadow(struct nouveau_bios *bios)
+nvbios_shadow(struct nvkm_bios *bios)
{
struct shadow mthds[] = {
{ shadow_class, 0, &nvbios_of },
@@ -211,7 +213,7 @@ nvbios_shadow(struct nouveau_bios *bios)
int optlen;
/* handle user-specified bios source */
- optarg = nouveau_stropt(nv_device(bios)->cfgopt, "NvBios", &optlen);
+ optarg = nvkm_stropt(nv_device(bios)->cfgopt, "NvBios", &optlen);
source = optarg ? kstrndup(optarg, optlen, GFP_KERNEL) : NULL;
if (source) {
/* try to match one of the built-in methods */
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c
index bc130c12ec06..1fbd93bbb561 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c
@@ -20,9 +20,10 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "priv.h"
+#include <core/device.h>
+
#if defined(CONFIG_ACPI) && defined(CONFIG_X86)
int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
@@ -45,7 +46,7 @@ nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len)
* on some systems, such as Lenovo W530.
*/
static u32
-acpi_read_fast(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
+acpi_read_fast(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
{
u32 limit = (offset + length + 0xfff) & ~0xfff;
u32 start = offset & ~0x00000fff;
@@ -66,7 +67,7 @@ acpi_read_fast(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
* function.
*/
static u32
-acpi_read_slow(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
+acpi_read_slow(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
{
u32 limit = (offset + length + 0xfff) & ~0xfff;
u32 start = offset & ~0xfff;
@@ -87,7 +88,7 @@ acpi_read_slow(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
}
static void *
-acpi_init(struct nouveau_bios *bios, const char *name)
+acpi_init(struct nvkm_bios *bios, const char *name)
{
if (!nouveau_acpi_rom_supported(nv_device(bios)->pdev))
return ERR_PTR(-ENODEV);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c
index 3abe487a6025..4c19a7dba803 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c
@@ -20,9 +20,10 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "priv.h"
+#include <core/device.h>
+
#if defined(__powerpc__)
struct priv {
const void __iomem *data;
@@ -30,7 +31,7 @@ struct priv {
};
static u32
-of_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
+of_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
{
struct priv *priv = data;
if (offset + length <= priv->size) {
@@ -41,7 +42,7 @@ of_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
}
static void *
-of_init(struct nouveau_bios *bios, const char *name)
+of_init(struct nvkm_bios *bios, const char *name)
{
struct pci_dev *pdev = nv_device(bios)->pdev;
struct device_node *dn;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c
index 1d0389c0abef..1b045483dc87 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c
@@ -20,9 +20,10 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "priv.h"
+#include <core/device.h>
+
struct priv {
struct pci_dev *pdev;
void __iomem *rom;
@@ -30,7 +31,7 @@ struct priv {
};
static u32
-pcirom_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
+pcirom_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
{
struct priv *priv = data;
if (offset + length <= priv->size) {
@@ -50,7 +51,7 @@ pcirom_fini(void *data)
}
static void *
-pcirom_init(struct nouveau_bios *bios, const char *name)
+pcirom_init(struct nvkm_bios *bios, const char *name)
{
struct pci_dev *pdev = nv_device(bios)->pdev;
struct priv *priv = NULL;
@@ -82,7 +83,7 @@ nvbios_pcirom = {
};
static void *
-platform_init(struct nouveau_bios *bios, const char *name)
+platform_init(struct nvkm_bios *bios, const char *name)
{
struct pci_dev *pdev = nv_device(bios)->pdev;
struct priv *priv;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
index a7a890fad1e5..abe8ae4d3a9f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
@@ -20,16 +20,17 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "priv.h"
+#include <core/device.h>
+
struct priv {
- struct nouveau_bios *bios;
+ struct nvkm_bios *bios;
u32 bar0;
};
static u32
-pramin_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
+pramin_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
{
u32 i;
if (offset + length <= 0x00100000) {
@@ -51,7 +52,7 @@ pramin_fini(void *data)
}
static void *
-pramin_init(struct nouveau_bios *bios, const char *name)
+pramin_init(struct nvkm_bios *bios, const char *name)
{
struct priv *priv = NULL;
u64 addr = 0;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c
index b7992bc3ffa5..6ec3b237925e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c
@@ -20,11 +20,12 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "priv.h"
+#include <core/device.h>
+
static u32
-prom_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
+prom_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
{
u32 i;
if (offset + length <= 0x00100000) {
@@ -38,7 +39,7 @@ prom_read(void *data, u32 offset, u32 length, struct nouveau_bios *bios)
static void
prom_fini(void *data)
{
- struct nouveau_bios *bios = data;
+ struct nvkm_bios *bios = data;
if (nv_device(bios)->card_type < NV_50)
nv_mask(bios, 0x001850, 0x00000001, 0x00000001);
else
@@ -46,7 +47,7 @@ prom_fini(void *data)
}
static void *
-prom_init(struct nouveau_bios *bios, const char *name)
+prom_init(struct nvkm_bios *bios, const char *name)
{
if (nv_device(bios)->card_type < NV_50) {
if (nv_device(bios)->card_type == NV_40 &&
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c
index d15854094078..249ff6d583df 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c
@@ -21,13 +21,14 @@
*
* Authors: Martin Peres
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/therm.h>
+#include <core/device.h>
+
static u16
-therm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
+therm_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
{
struct bit_entry bit_P;
u16 therm = 0;
@@ -51,12 +52,11 @@ therm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
*hdr = nv_ro08(bios, therm + 1);
*len = nv_ro08(bios, therm + 2);
*cnt = nv_ro08(bios, therm + 3);
-
return therm + nv_ro08(bios, therm + 1);
}
static u16
-nvbios_therm_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
+nvbios_therm_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 therm = therm_table(bios, ver, &hdr, len, &cnt);
@@ -66,7 +66,7 @@ nvbios_therm_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
}
int
-nvbios_therm_sensor_parse(struct nouveau_bios *bios,
+nvbios_therm_sensor_parse(struct nvkm_bios *bios,
enum nvbios_therm_domain domain,
struct nvbios_therm_sensor *sensor)
{
@@ -152,10 +152,9 @@ nvbios_therm_sensor_parse(struct nouveau_bios *bios,
}
int
-nvbios_therm_fan_parse(struct nouveau_bios *bios,
- struct nvbios_therm_fan *fan)
+nvbios_therm_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan)
{
- struct nouveau_therm_trip_point *cur_trip = NULL;
+ struct nvbios_therm_trip_point *cur_trip = NULL;
u8 ver, len, i;
u16 entry;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
index 8521eca1ed9c..763fd29a58f2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
@@ -21,14 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
-#include <subdev/bios/ramcfg.h>
#include <subdev/bios/timing.h>
u16
-nvbios_timingTe(struct nouveau_bios *bios,
+nvbios_timingTe(struct nvkm_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_P;
@@ -68,7 +66,7 @@ nvbios_timingTe(struct nouveau_bios *bios,
}
u16
-nvbios_timingEe(struct nouveau_bios *bios, int idx,
+nvbios_timingEe(struct nvkm_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 snr, ssz;
@@ -84,9 +82,8 @@ nvbios_timingEe(struct nouveau_bios *bios, int idx,
}
u16
-nvbios_timingEp(struct nouveau_bios *bios, int idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_ramcfg *p)
+nvbios_timingEp(struct nvkm_bios *bios, int idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p)
{
u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp;
p->timing_ver = *ver;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.c
index f343a1b060e8..e95b69faa82e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.c
@@ -21,13 +21,12 @@
*
* Authors: Martin Peres
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/vmap.h>
u16
-nvbios_vmap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+nvbios_vmap_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry bit_P;
u16 vmap = 0x0000;
@@ -55,7 +54,7 @@ nvbios_vmap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
u16
-nvbios_vmap_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+nvbios_vmap_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_vmap *info)
{
u16 vmap = nvbios_vmap_table(bios, ver, hdr, cnt, len);
@@ -69,7 +68,7 @@ nvbios_vmap_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
}
u16
-nvbios_vmap_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
+nvbios_vmap_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 vmap = nvbios_vmap_table(bios, ver, &hdr, &cnt, len);
@@ -81,7 +80,7 @@ nvbios_vmap_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
}
u16
-nvbios_vmap_entry_parse(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len,
+nvbios_vmap_entry_parse(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len,
struct nvbios_vmap_entry *info)
{
u16 vmap = nvbios_vmap_entry(bios, idx, ver, len);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c
index bb590de4ecb2..8454ab7c4a3d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c
@@ -21,13 +21,12 @@
*
* Authors: Martin Peres
*/
-
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/volt.h>
u16
-nvbios_volt_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+nvbios_volt_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry bit_P;
u16 volt = 0x0000;
@@ -67,7 +66,7 @@ nvbios_volt_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
u16
-nvbios_volt_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
+nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_volt *info)
{
u16 volt = nvbios_volt_table(bios, ver, hdr, cnt, len);
@@ -102,7 +101,7 @@ nvbios_volt_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
}
u16
-nvbios_volt_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
+nvbios_volt_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 volt = nvbios_volt_table(bios, ver, &hdr, &cnt, len);
@@ -114,7 +113,7 @@ nvbios_volt_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
}
u16
-nvbios_volt_entry_parse(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len,
+nvbios_volt_entry_parse(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len,
struct nvbios_volt_entry *info)
{
u16 volt = nvbios_volt_entry(bios, idx, ver, len);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.c
index e9b8e5d30a7a..63a5e1b5cb3c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/bios.h>
#include <subdev/bios/gpio.h>
#include <subdev/bios/xpio.h>
static u16
-dcb_xpiod_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
+dcb_xpiod_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u16 data = dcb_gpio_table(bios, ver, hdr, cnt, len);
if (data && *ver >= 0x40 && *hdr >= 0x06) {
@@ -44,7 +43,7 @@ dcb_xpiod_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
u16
-dcb_xpio_table(struct nouveau_bios *bios, u8 idx,
+dcb_xpio_table(struct nvkm_bios *bios, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u16 data = dcb_xpiod_table(bios, ver, hdr, cnt, len);
@@ -62,9 +61,8 @@ dcb_xpio_table(struct nouveau_bios *bios, u8 idx,
}
u16
-dcb_xpio_parse(struct nouveau_bios *bios, u8 idx,
- u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
- struct nvbios_xpio *info)
+dcb_xpio_parse(struct nvkm_bios *bios, u8 idx,
+ u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_xpio *info)
{
u16 data = dcb_xpio_table(bios, idx, ver, hdr, cnt, len);
if (data && *len >= 6) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
index 7d4bfd8d5b93..67ad8ea468a9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
@@ -33,9 +33,9 @@ static int
nouveau_therm_update_trip(struct nouveau_therm *therm)
{
struct nouveau_therm_priv *priv = (void *)therm;
- struct nouveau_therm_trip_point *trip = priv->fan->bios.trip,
- *cur_trip = NULL,
- *last_trip = priv->last_trip;
+ struct nvbios_therm_trip_point *trip = priv->fan->bios.trip,
+ *cur_trip = NULL,
+ *last_trip = priv->last_trip;
u8 temp = therm->temp_get(therm);
u16 duty, i;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h
index 7dba8c281a0b..8db630818793 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h
@@ -27,6 +27,7 @@
#include <subdev/therm.h>
+#include <subdev/bios.h>
#include <subdev/bios/extdev.h>
#include <subdev/bios/gpio.h>
#include <subdev/bios/perf.h>
@@ -74,7 +75,7 @@ struct nouveau_therm_priv {
/* automatic thermal management */
struct nouveau_alarm alarm;
spinlock_t lock;
- struct nouveau_therm_trip_point *last_trip;
+ struct nvbios_therm_trip_point *last_trip;
int mode;
int cstate;
int suspend;
From 5f8824de8a50150c7c2e514e6d51ed7bcb5f4faa Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 14:40:22 +1000
Subject: [PATCH 54/86] drm/nouveau/bus: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/subdev/bus.h | 67 +++++++++----------
.../drm/nouveau/nvkm/engine/device/gm100.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 20 +++---
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 ++---
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 16 ++---
.../gpu/drm/nouveau/nvkm/subdev/bus/Kbuild | 4 +-
.../nouveau/nvkm/subdev/bus/{nv94.c => g94.c} | 17 +++--
.../nvkm/subdev/bus/{nvc0.c => gf100.c} | 23 +++----
.../gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c | 26 ++++---
.../gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h | 24 +++----
.../gpu/drm/nouveau/nvkm/subdev/bus/nv04.c | 27 ++++----
.../gpu/drm/nouveau/nvkm/subdev/bus/nv04.h | 20 +++---
.../gpu/drm/nouveau/nvkm/subdev/bus/nv31.c | 21 +++---
.../gpu/drm/nouveau/nvkm/subdev/bus/nv50.c | 23 +++----
14 files changed, 148 insertions(+), 162 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/subdev/bus/{nv94.c => g94.c} (87%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/bus/{nvc0.c => gf100.c} (84%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
index 2d40f0c2fdfc..fba83c04849e 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
@@ -1,53 +1,50 @@
-#ifndef __NOUVEAU_BUS_H__
-#define __NOUVEAU_BUS_H__
-
+#ifndef __NVKM_BUS_H__
+#define __NVKM_BUS_H__
#include <core/subdev.h>
-#include <core/device.h>
-struct nouveau_bus_intr {
+struct nvkm_bus_intr {
u32 stat;
u32 unit;
};
-struct nouveau_bus {
- struct nouveau_subdev base;
- int (*hwsq_exec)(struct nouveau_bus *, u32 *, u32);
+struct nvkm_bus {
+ struct nvkm_subdev base;
+ int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32);
u32 hwsq_size;
};
-static inline struct nouveau_bus *
-nouveau_bus(void *obj)
+static inline struct nvkm_bus *
+nvkm_bus(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_BUS);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BUS);
}
-#define nouveau_bus_create(p, e, o, d) \
- nouveau_subdev_create_((p), (e), (o), 0, "PBUS", "master", \
+#define nvkm_bus_create(p, e, o, d) \
+ nvkm_subdev_create_((p), (e), (o), 0, "PBUS", "master", \
sizeof(**d), (void **)d)
-#define nouveau_bus_destroy(p) \
- nouveau_subdev_destroy(&(p)->base)
-#define nouveau_bus_init(p) \
- nouveau_subdev_init(&(p)->base)
-#define nouveau_bus_fini(p, s) \
- nouveau_subdev_fini(&(p)->base, (s))
+#define nvkm_bus_destroy(p) \
+ nvkm_subdev_destroy(&(p)->base)
+#define nvkm_bus_init(p) \
+ nvkm_subdev_init(&(p)->base)
+#define nvkm_bus_fini(p, s) \
+ nvkm_subdev_fini(&(p)->base, (s))
-#define _nouveau_bus_dtor _nouveau_subdev_dtor
-#define _nouveau_bus_init _nouveau_subdev_init
-#define _nouveau_bus_fini _nouveau_subdev_fini
+#define _nvkm_bus_dtor _nvkm_subdev_dtor
+#define _nvkm_bus_init _nvkm_subdev_init
+#define _nvkm_bus_fini _nvkm_subdev_fini
-extern struct nouveau_oclass *nv04_bus_oclass;
-extern struct nouveau_oclass *nv31_bus_oclass;
-extern struct nouveau_oclass *nv50_bus_oclass;
-extern struct nouveau_oclass *nv94_bus_oclass;
-extern struct nouveau_oclass *nvc0_bus_oclass;
+extern struct nvkm_oclass *nv04_bus_oclass;
+extern struct nvkm_oclass *nv31_bus_oclass;
+extern struct nvkm_oclass *nv50_bus_oclass;
+extern struct nvkm_oclass *g94_bus_oclass;
+extern struct nvkm_oclass *gf100_bus_oclass;
/* interface to sequencer */
-struct nouveau_hwsq;
-int nouveau_hwsq_init(struct nouveau_bus *, struct nouveau_hwsq **);
-int nouveau_hwsq_fini(struct nouveau_hwsq **, bool exec);
-void nouveau_hwsq_wr32(struct nouveau_hwsq *, u32 addr, u32 data);
-void nouveau_hwsq_setf(struct nouveau_hwsq *, u8 flag, int data);
-void nouveau_hwsq_wait(struct nouveau_hwsq *, u8 flag, u8 data);
-void nouveau_hwsq_nsec(struct nouveau_hwsq *, u32 nsec);
-
+struct nvkm_hwsq;
+int nvkm_hwsq_init(struct nvkm_bus *, struct nvkm_hwsq **);
+int nvkm_hwsq_fini(struct nvkm_hwsq **, bool exec);
+void nvkm_hwsq_wr32(struct nvkm_hwsq *, u32 addr, u32 data);
+void nvkm_hwsq_setf(struct nvkm_hwsq *, u8 flag, int data);
+void nvkm_hwsq_wait(struct nvkm_hwsq *, u8 flag, u8 data);
+void nvkm_hwsq_nsec(struct nvkm_hwsq *, u32 nsec);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 29dbe1693480..f6004cc543c0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -70,7 +70,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
@@ -114,7 +114,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 4f100b261f28..e60deaee4d2f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -185,7 +185,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -214,7 +214,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -243,7 +243,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -272,7 +272,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -301,7 +301,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -330,7 +330,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -359,7 +359,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -390,7 +390,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -420,7 +420,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -450,7 +450,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 5e4608fba660..89ff7d0d630b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -70,7 +70,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@@ -103,7 +103,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@@ -136,7 +136,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@@ -168,7 +168,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@@ -201,7 +201,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@@ -233,7 +233,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@@ -265,7 +265,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@@ -298,7 +298,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@@ -330,7 +330,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index a488b30304cf..11805f72f4e9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -70,7 +70,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
@@ -104,7 +104,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
@@ -138,7 +138,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
@@ -165,7 +165,7 @@ nve0_identify(struct nouveau_device *device)
device->cname = "GK20A";
device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;
@@ -194,7 +194,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
@@ -228,7 +228,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
@@ -262,7 +262,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
@@ -295,7 +295,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
+ device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild
index 633e9b4b6a3a..83d80b13f149 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild
@@ -2,5 +2,5 @@ nvkm-y += nvkm/subdev/bus/hwsq.o
nvkm-y += nvkm/subdev/bus/nv04.o
nvkm-y += nvkm/subdev/bus/nv31.o
nvkm-y += nvkm/subdev/bus/nv50.o
-nvkm-y += nvkm/subdev/bus/nv94.o
-nvkm-y += nvkm/subdev/bus/nvc0.o
+nvkm-y += nvkm/subdev/bus/g94.o
+nvkm-y += nvkm/subdev/bus/gf100.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c
similarity index 87%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv94.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c
index d3659055fa4b..cbe699e82593 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv94.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c
@@ -22,13 +22,12 @@
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
+#include "nv04.h"
#include <subdev/timer.h>
-#include "nv04.h"
-
static int
-nv94_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
+g94_bus_hwsq_exec(struct nvkm_bus *pbus, u32 *data, u32 size)
{
struct nv50_bus_priv *priv = (void *)pbus;
int i;
@@ -44,16 +43,16 @@ nv94_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
}
-struct nouveau_oclass *
-nv94_bus_oclass = &(struct nv04_bus_impl) {
+struct nvkm_oclass *
+g94_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x94),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_bus_ctor,
- .dtor = _nouveau_bus_dtor,
+ .dtor = _nvkm_bus_dtor,
.init = nv50_bus_init,
- .fini = _nouveau_bus_fini,
+ .fini = _nvkm_bus_fini,
},
.intr = nv50_bus_intr,
- .hwsq_exec = nv94_bus_hwsq_exec,
+ .hwsq_exec = g94_bus_hwsq_exec,
.hwsq_size = 128,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c
similarity index 84%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/bus/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c
index 73839d7151a7..ebc63ba968d4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c
@@ -22,13 +22,12 @@
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
-
#include "nv04.h"
static void
-nvc0_bus_intr(struct nouveau_subdev *subdev)
+gf100_bus_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_bus *pbus = nouveau_bus(subdev);
+ struct nvkm_bus *pbus = nvkm_bus(subdev);
u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
if (stat & 0x0000000e) {
@@ -54,12 +53,12 @@ nvc0_bus_intr(struct nouveau_subdev *subdev)
}
static int
-nvc0_bus_init(struct nouveau_object *object)
+gf100_bus_init(struct nvkm_object *object)
{
struct nv04_bus_priv *priv = (void *)object;
int ret;
- ret = nouveau_bus_init(&priv->base);
+ ret = nvkm_bus_init(&priv->base);
if (ret)
return ret;
@@ -68,14 +67,14 @@ nvc0_bus_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
-nvc0_bus_oclass = &(struct nv04_bus_impl) {
+struct nvkm_oclass *
+gf100_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_bus_ctor,
- .dtor = _nouveau_bus_dtor,
- .init = nvc0_bus_init,
- .fini = _nouveau_bus_fini,
+ .dtor = _nvkm_bus_dtor,
+ .init = gf100_bus_init,
+ .fini = _nvkm_bus_fini,
},
- .intr = nvc0_bus_intr,
+ .intr = gf100_bus_intr,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
index f757470e2284..b8853bf16b23 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
@@ -21,12 +21,10 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include <subdev/timer.h>
#include <subdev/bus.h>
-struct nouveau_hwsq {
- struct nouveau_bus *pbus;
+struct nvkm_hwsq {
+ struct nvkm_bus *pbus;
u32 addr;
u32 data;
struct {
@@ -36,16 +34,16 @@ struct nouveau_hwsq {
};
static void
-hwsq_cmd(struct nouveau_hwsq *hwsq, int size, u8 data[])
+hwsq_cmd(struct nvkm_hwsq *hwsq, int size, u8 data[])
{
memcpy(&hwsq->c.data[hwsq->c.size], data, size * sizeof(data[0]));
hwsq->c.size += size;
}
int
-nouveau_hwsq_init(struct nouveau_bus *pbus, struct nouveau_hwsq **phwsq)
+nvkm_hwsq_init(struct nvkm_bus *pbus, struct nvkm_hwsq **phwsq)
{
- struct nouveau_hwsq *hwsq;
+ struct nvkm_hwsq *hwsq;
hwsq = *phwsq = kmalloc(sizeof(*hwsq), GFP_KERNEL);
if (hwsq) {
@@ -60,12 +58,12 @@ nouveau_hwsq_init(struct nouveau_bus *pbus, struct nouveau_hwsq **phwsq)
}
int
-nouveau_hwsq_fini(struct nouveau_hwsq **phwsq, bool exec)
+nvkm_hwsq_fini(struct nvkm_hwsq **phwsq, bool exec)
{
- struct nouveau_hwsq *hwsq = *phwsq;
+ struct nvkm_hwsq *hwsq = *phwsq;
int ret = 0, i;
if (hwsq) {
- struct nouveau_bus *pbus = hwsq->pbus;
+ struct nvkm_bus *pbus = hwsq->pbus;
hwsq->c.size = (hwsq->c.size + 4) / 4;
if (hwsq->c.size <= pbus->hwsq_size) {
if (exec)
@@ -88,7 +86,7 @@ nouveau_hwsq_fini(struct nouveau_hwsq **phwsq, bool exec)
}
void
-nouveau_hwsq_wr32(struct nouveau_hwsq *hwsq, u32 addr, u32 data)
+nvkm_hwsq_wr32(struct nvkm_hwsq *hwsq, u32 addr, u32 data)
{
nv_debug(hwsq->pbus, "R[%06x] = 0x%08x\n", addr, data);
@@ -113,7 +111,7 @@ nouveau_hwsq_wr32(struct nouveau_hwsq *hwsq, u32 addr, u32 data)
}
void
-nouveau_hwsq_setf(struct nouveau_hwsq *hwsq, u8 flag, int data)
+nvkm_hwsq_setf(struct nvkm_hwsq *hwsq, u8 flag, int data)
{
nv_debug(hwsq->pbus, " FLAG[%02x] = %d\n", flag, data);
flag += 0x80;
@@ -125,14 +123,14 @@ nouveau_hwsq_setf(struct nouveau_hwsq *hwsq, u8 flag, int data)
}
void
-nouveau_hwsq_wait(struct nouveau_hwsq *hwsq, u8 flag, u8 data)
+nvkm_hwsq_wait(struct nvkm_hwsq *hwsq, u8 flag, u8 data)
{
nv_debug(hwsq->pbus, " WAIT[%02x] = %d\n", flag, data);
hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data });
}
void
-nouveau_hwsq_nsec(struct nouveau_hwsq *hwsq, u32 nsec)
+nvkm_hwsq_nsec(struct nvkm_hwsq *hwsq, u32 nsec)
{
u8 shift = 0, usec = nsec / 1000;
while (usec & ~3) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h
index 12176f9c1bc6..3394a5ea8a9f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h
@@ -1,11 +1,10 @@
#ifndef __NVKM_BUS_HWSQ_H__
#define __NVKM_BUS_HWSQ_H__
-
#include <subdev/bus.h>
struct hwsq {
- struct nouveau_subdev *subdev;
- struct nouveau_hwsq *hwsq;
+ struct nvkm_subdev *subdev;
+ struct nvkm_hwsq *hwsq;
int sequence;
};
@@ -34,12 +33,12 @@ hwsq_reg(u32 addr)
}
static inline int
-hwsq_init(struct hwsq *ram, struct nouveau_subdev *subdev)
+hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev)
{
- struct nouveau_bus *pbus = nouveau_bus(subdev);
+ struct nvkm_bus *pbus = nvkm_bus(subdev);
int ret;
- ret = nouveau_hwsq_init(pbus, &ram->hwsq);
+ ret = nvkm_hwsq_init(pbus, &ram->hwsq);
if (ret)
return ret;
@@ -53,7 +52,7 @@ hwsq_exec(struct hwsq *ram, bool exec)
{
int ret = 0;
if (ram->subdev) {
- ret = nouveau_hwsq_fini(&ram->hwsq, exec);
+ ret = nvkm_hwsq_fini(&ram->hwsq, exec);
ram->subdev = NULL;
}
return ret;
@@ -73,8 +72,8 @@ hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data)
reg->sequence = ram->sequence;
reg->data = data;
if (reg->addr[0] != reg->addr[1])
- nouveau_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data);
- nouveau_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data);
+ nvkm_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data);
+ nvkm_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data);
}
static inline void
@@ -95,19 +94,18 @@ hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data)
static inline void
hwsq_setf(struct hwsq *ram, u8 flag, int data)
{
- nouveau_hwsq_setf(ram->hwsq, flag, data);
+ nvkm_hwsq_setf(ram->hwsq, flag, data);
}
static inline void
hwsq_wait(struct hwsq *ram, u8 flag, u8 data)
{
- nouveau_hwsq_wait(ram->hwsq, flag, data);
+ nvkm_hwsq_wait(ram->hwsq, flag, data);
}
static inline void
hwsq_nsec(struct hwsq *ram, u32 nsec)
{
- nouveau_hwsq_nsec(ram->hwsq, nsec);
+ nvkm_hwsq_nsec(ram->hwsq, nsec);
}
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
index 23921b5351db..19c8e50eeff7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
@@ -22,13 +22,12 @@
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
-
#include "nv04.h"
static void
-nv04_bus_intr(struct nouveau_subdev *subdev)
+nv04_bus_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_bus *pbus = nouveau_bus(subdev);
+ struct nvkm_bus *pbus = nvkm_bus(subdev);
u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
if (stat & 0x00000001) {
@@ -38,7 +37,7 @@ nv04_bus_intr(struct nouveau_subdev *subdev)
}
if (stat & 0x00000110) {
- subdev = nouveau_subdev(subdev, NVDEV_SUBDEV_GPIO);
+ subdev = nvkm_subdev(subdev, NVDEV_SUBDEV_GPIO);
if (subdev && subdev->intr)
subdev->intr(subdev);
stat &= ~0x00000110;
@@ -52,26 +51,26 @@ nv04_bus_intr(struct nouveau_subdev *subdev)
}
static int
-nv04_bus_init(struct nouveau_object *object)
+nv04_bus_init(struct nvkm_object *object)
{
struct nv04_bus_priv *priv = (void *)object;
nv_wr32(priv, 0x001100, 0xffffffff);
nv_wr32(priv, 0x001140, 0x00000111);
- return nouveau_bus_init(&priv->base);
+ return nvkm_bus_init(&priv->base);
}
int
-nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_bus_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_bus_impl *impl = (void *)oclass;
struct nv04_bus_priv *priv;
int ret;
- ret = nouveau_bus_create(parent, engine, oclass, &priv);
+ ret = nvkm_bus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -82,14 +81,14 @@ nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv04_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x04),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_bus_ctor,
- .dtor = _nouveau_bus_dtor,
+ .dtor = _nvkm_bus_dtor,
.init = nv04_bus_init,
- .fini = _nouveau_bus_fini,
+ .fini = _nvkm_bus_fini,
},
.intr = nv04_bus_intr,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h
index 4d7602450a20..3ddc8f91b1e3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h
@@ -1,23 +1,21 @@
#ifndef __NVKM_BUS_NV04_H__
#define __NVKM_BUS_NV04_H__
-
#include <subdev/bus.h>
struct nv04_bus_priv {
- struct nouveau_bus base;
+ struct nvkm_bus base;
};
-int nv04_bus_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-int nv50_bus_init(struct nouveau_object *);
-void nv50_bus_intr(struct nouveau_subdev *);
+int nv04_bus_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+int nv50_bus_init(struct nvkm_object *);
+void nv50_bus_intr(struct nvkm_subdev *);
struct nv04_bus_impl {
- struct nouveau_oclass base;
- void (*intr)(struct nouveau_subdev *);
- int (*hwsq_exec)(struct nouveau_bus *, u32 *, u32);
+ struct nvkm_oclass base;
+ void (*intr)(struct nvkm_subdev *);
+ int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32);
u32 hwsq_size;
};
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
index 94da46f61627..c5739bce8052 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
@@ -22,18 +22,17 @@
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
-
#include "nv04.h"
static void
-nv31_bus_intr(struct nouveau_subdev *subdev)
+nv31_bus_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_bus *pbus = nouveau_bus(subdev);
+ struct nvkm_bus *pbus = nvkm_bus(subdev);
u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
u32 gpio = nv_rd32(pbus, 0x001104) & nv_rd32(pbus, 0x001144);
if (gpio) {
- subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_GPIO);
+ subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_GPIO);
if (subdev && subdev->intr)
subdev->intr(subdev);
}
@@ -51,7 +50,7 @@ nv31_bus_intr(struct nouveau_subdev *subdev)
}
if (stat & 0x00070000) {
- subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM);
+ subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_THERM);
if (subdev && subdev->intr)
subdev->intr(subdev);
stat &= ~0x00070000;
@@ -65,12 +64,12 @@ nv31_bus_intr(struct nouveau_subdev *subdev)
}
static int
-nv31_bus_init(struct nouveau_object *object)
+nv31_bus_init(struct nvkm_object *object)
{
struct nv04_bus_priv *priv = (void *)object;
int ret;
- ret = nouveau_bus_init(&priv->base);
+ ret = nvkm_bus_init(&priv->base);
if (ret)
return ret;
@@ -79,14 +78,14 @@ nv31_bus_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv31_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x31),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_bus_ctor,
- .dtor = _nouveau_bus_dtor,
+ .dtor = _nvkm_bus_dtor,
.init = nv31_bus_init,
- .fini = _nouveau_bus_fini,
+ .fini = _nvkm_bus_fini,
},
.intr = nv31_bus_intr,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
index 11918f7e2aca..1987863d71ee 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
@@ -22,13 +22,12 @@
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
+#include "nv04.h"
#include <subdev/timer.h>
-#include "nv04.h"
-
static int
-nv50_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
+nv50_bus_hwsq_exec(struct nvkm_bus *pbus, u32 *data, u32 size)
{
struct nv50_bus_priv *priv = (void *)pbus;
int i;
@@ -44,9 +43,9 @@ nv50_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
}
void
-nv50_bus_intr(struct nouveau_subdev *subdev)
+nv50_bus_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_bus *pbus = nouveau_bus(subdev);
+ struct nvkm_bus *pbus = nvkm_bus(subdev);
u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
if (stat & 0x00000008) {
@@ -62,7 +61,7 @@ nv50_bus_intr(struct nouveau_subdev *subdev)
}
if (stat & 0x00010000) {
- subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM);
+ subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_THERM);
if (subdev && subdev->intr)
subdev->intr(subdev);
stat &= ~0x00010000;
@@ -76,12 +75,12 @@ nv50_bus_intr(struct nouveau_subdev *subdev)
}
int
-nv50_bus_init(struct nouveau_object *object)
+nv50_bus_init(struct nvkm_object *object)
{
struct nv04_bus_priv *priv = (void *)object;
int ret;
- ret = nouveau_bus_init(&priv->base);
+ ret = nvkm_bus_init(&priv->base);
if (ret)
return ret;
@@ -90,14 +89,14 @@ nv50_bus_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv50_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x50),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_bus_ctor,
- .dtor = _nouveau_bus_dtor,
+ .dtor = _nvkm_bus_dtor,
.init = nv50_bus_init,
- .fini = _nouveau_bus_fini,
+ .fini = _nvkm_bus_fini,
},
.intr = nv50_bus_intr,
.hwsq_exec = nv50_bus_hwsq_exec,
From 7632b30e4b8be39270b098948c5b2f05fae8b691 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 14:47:24 +1000
Subject: [PATCH 55/86] drm/nouveau/clk: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 18 ++
.../gpu/drm/nouveau/include/nvkm/subdev/clk.h | 140 ++++++-------
.../drm/nouveau/nvkm/engine/device/gm100.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 26 +--
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 +-
.../gpu/drm/nouveau/nvkm/subdev/clk/Kbuild | 12 +-
.../gpu/drm/nouveau/nvkm/subdev/clk/base.c | 198 +++++++++---------
.../nouveau/nvkm/subdev/clk/{nv84.c => g84.c} | 19 +-
.../nvkm/subdev/clk/{nvc0.c => gf100.c} | 129 ++++++------
.../nvkm/subdev/clk/{nve0.c => gk104.c} | 139 ++++++------
.../gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c | 58 +++--
.../nvkm/subdev/clk/{nva3.c => gt215.c} | 150 +++++++------
.../gpu/drm/nouveau/nvkm/subdev/clk/gt215.h | 18 ++
.../nvkm/subdev/clk/{nvaa.c => mcp77.c} | 87 ++++----
.../gpu/drm/nouveau/nvkm/subdev/clk/nv04.c | 40 ++--
.../gpu/drm/nouveau/nvkm/subdev/clk/nv40.c | 47 +++--
.../gpu/drm/nouveau/nvkm/subdev/clk/nv50.c | 50 ++---
.../gpu/drm/nouveau/nvkm/subdev/clk/nv50.h | 15 +-
.../gpu/drm/nouveau/nvkm/subdev/clk/nva3.h | 20 --
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h | 12 +-
.../nvkm/subdev/clk/{pllnva3.c => pllgt215.c} | 8 +-
.../gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c | 13 +-
drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h | 3 -
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c | 2 +-
25 files changed, 610 insertions(+), 630 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/subdev/clk/{nv84.c => g84.c} (84%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/clk/{nvc0.c => gf100.c} (75%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/clk/{nve0.c => gk104.c} (75%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/clk/{nva3.c => gt215.c} (75%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h
rename drivers/gpu/drm/nouveau/nvkm/subdev/clk/{nvaa.c => mcp77.c} (85%)
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h
rename drivers/gpu/drm/nouveau/nvkm/subdev/clk/{pllnva3.c => pllgt215.c} (94%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index af07bbba9faf..70ad99dd01e6 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -201,5 +201,23 @@
#define nouveau_bios_oclass nvkm_bios_oclass
#define nouveau_pll_vals nvkm_pll_vals
#define nouveau_therm_trip_point nvkm_therm_trip_point
+#define nouveau_fb nvkm_fb
+#define nouveau_fifo nvkm_fifo
+#define nouveau_therm nvkm_therm
+#define nouveau_therm_cstate nvkm_therm_cstate
+#define nouveau_volt nvkm_volt
+#define nouveau_timer nvkm_timer
+#define nouveau_timer_wait_eq nvkm_timer_wait_eq
+#define nva3_pll_calc gt215_pll_calc
+#define nouveau_clk nvkm_clk
+#define nouveau_domain nvkm_domain
+#define nouveau_cstate nvkm_cstate
+#define nouveau_pstate nvkm_pstate
+#define nouveau_clk_astate nvkm_clk_astate
+#define nouveau_clk_ustate nvkm_clk_ustate
+#define nva3_clk_pre gt215_clk_pre
+#define nva3_clk_post gt215_clk_post
+#define nva3_clk_info gt215_clk_info
+#define nva3_pll_info gt215_pll_info
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
index d42a08837d4f..f5d303850d8c 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
@@ -1,12 +1,9 @@
-#ifndef __NOUVEAU_CLK_H__
-#define __NOUVEAU_CLK_H__
-
-#include <core/device.h>
-#include <core/notify.h>
+#ifndef __NVKM_CLK_H__
+#define __NVKM_CLK_H__
#include <core/subdev.h>
-
-struct nouveau_pll_vals;
+#include <core/notify.h>
struct nvbios_pll;
+struct nvkm_pll_vals;
enum nv_clk_src {
nv_clk_src_crystal,
@@ -50,25 +47,34 @@ enum nv_clk_src {
nv_clk_src_max,
};
-struct nouveau_cstate {
+struct nvkm_cstate {
struct list_head head;
u8 voltage;
u32 domain[nv_clk_src_max];
};
-struct nouveau_pstate {
+struct nvkm_pstate {
struct list_head head;
struct list_head list; /* c-states */
- struct nouveau_cstate base;
+ struct nvkm_cstate base;
u8 pstate;
u8 fanspeed;
};
-struct nouveau_clk {
- struct nouveau_subdev base;
+struct nvkm_domain {
+ enum nv_clk_src name;
+ u8 bios; /* 0xff for none */
+#define NVKM_CLK_DOM_FLAG_CORE 0x01
+ u8 flags;
+ const char *mname;
+ int mdiv;
+};
- struct nouveau_domain *domains;
- struct nouveau_pstate bstate;
+struct nvkm_clk {
+ struct nvkm_subdev base;
+
+ struct nvkm_domain *domains;
+ struct nvkm_pstate bstate;
struct list_head states;
int state_nr;
@@ -88,80 +94,68 @@ struct nouveau_clk {
bool allow_reclock;
- int (*read)(struct nouveau_clk *, enum nv_clk_src);
- int (*calc)(struct nouveau_clk *, struct nouveau_cstate *);
- int (*prog)(struct nouveau_clk *);
- void (*tidy)(struct nouveau_clk *);
+ int (*read)(struct nvkm_clk *, enum nv_clk_src);
+ int (*calc)(struct nvkm_clk *, struct nvkm_cstate *);
+ int (*prog)(struct nvkm_clk *);
+ void (*tidy)(struct nvkm_clk *);
/*XXX: die, these are here *only* to support the completely
- * bat-shit insane what-was-nouveau_hw.c code
+ * bat-shit insane what-was-nvkm_hw.c code
*/
- int (*pll_calc)(struct nouveau_clk *, struct nvbios_pll *,
- int clk, struct nouveau_pll_vals *pv);
- int (*pll_prog)(struct nouveau_clk *, u32 reg1,
- struct nouveau_pll_vals *pv);
+ int (*pll_calc)(struct nvkm_clk *, struct nvbios_pll *, int clk,
+ struct nvkm_pll_vals *pv);
+ int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv);
};
-static inline struct nouveau_clk *
-nouveau_clk(void *obj)
+static inline struct nvkm_clk *
+nvkm_clk(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_CLK);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_CLK);
}
-struct nouveau_domain {
- enum nv_clk_src name;
- u8 bios; /* 0xff for none */
-#define NVKM_CLK_DOM_FLAG_CORE 0x01
- u8 flags;
- const char *mname;
- int mdiv;
-};
-
-#define nouveau_clk_create(p,e,o,i,r,s,n,d) \
- nouveau_clk_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \
+#define nvkm_clk_create(p,e,o,i,r,s,n,d) \
+ nvkm_clk_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \
(void **)d)
-#define nouveau_clk_destroy(p) ({ \
- struct nouveau_clk *clk = (p); \
- _nouveau_clk_dtor(nv_object(clk)); \
+#define nvkm_clk_destroy(p) ({ \
+ struct nvkm_clk *clk = (p); \
+ _nvkm_clk_dtor(nv_object(clk)); \
})
-#define nouveau_clk_init(p) ({ \
- struct nouveau_clk *clk = (p); \
- _nouveau_clk_init(nv_object(clk)); \
+#define nvkm_clk_init(p) ({ \
+ struct nvkm_clk *clk = (p); \
+ _nvkm_clk_init(nv_object(clk)); \
})
-#define nouveau_clk_fini(p,s) ({ \
- struct nouveau_clk *clk = (p); \
- _nouveau_clk_fini(nv_object(clk), (s)); \
+#define nvkm_clk_fini(p,s) ({ \
+ struct nvkm_clk *clk = (p); \
+ _nvkm_clk_fini(nv_object(clk), (s)); \
})
-int nouveau_clk_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *,
- struct nouveau_domain *, struct nouveau_pstate *,
+int nvkm_clk_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *,
+ struct nvkm_domain *, struct nvkm_pstate *,
int, bool, int, void **);
-void _nouveau_clk_dtor(struct nouveau_object *);
-int _nouveau_clk_init(struct nouveau_object *);
-int _nouveau_clk_fini(struct nouveau_object *, bool);
+void _nvkm_clk_dtor(struct nvkm_object *);
+int _nvkm_clk_init(struct nvkm_object *);
+int _nvkm_clk_fini(struct nvkm_object *, bool);
-extern struct nouveau_oclass nv04_clk_oclass;
-extern struct nouveau_oclass nv40_clk_oclass;
-extern struct nouveau_oclass *nv50_clk_oclass;
-extern struct nouveau_oclass *nv84_clk_oclass;
-extern struct nouveau_oclass *nvaa_clk_oclass;
-extern struct nouveau_oclass nva3_clk_oclass;
-extern struct nouveau_oclass nvc0_clk_oclass;
-extern struct nouveau_oclass nve0_clk_oclass;
-extern struct nouveau_oclass gk20a_clk_oclass;
+extern struct nvkm_oclass nv04_clk_oclass;
+extern struct nvkm_oclass nv40_clk_oclass;
+extern struct nvkm_oclass *nv50_clk_oclass;
+extern struct nvkm_oclass *g84_clk_oclass;
+extern struct nvkm_oclass *mcp77_clk_oclass;
+extern struct nvkm_oclass gt215_clk_oclass;
+extern struct nvkm_oclass gf100_clk_oclass;
+extern struct nvkm_oclass gk104_clk_oclass;
+extern struct nvkm_oclass gk20a_clk_oclass;
-int nv04_clk_pll_set(struct nouveau_clk *, u32 type, u32 freq);
-int nv04_clk_pll_calc(struct nouveau_clk *, struct nvbios_pll *,
- int clk, struct nouveau_pll_vals *);
-int nv04_clk_pll_prog(struct nouveau_clk *, u32 reg1,
- struct nouveau_pll_vals *);
-int nva3_clk_pll_calc(struct nouveau_clk *, struct nvbios_pll *,
- int clk, struct nouveau_pll_vals *);
-
-int nouveau_clk_ustate(struct nouveau_clk *, int req, int pwr);
-int nouveau_clk_astate(struct nouveau_clk *, int req, int rel, bool wait);
-int nouveau_clk_dstate(struct nouveau_clk *, int req, int rel);
-int nouveau_clk_tstate(struct nouveau_clk *, int req, int rel);
+int nv04_clk_pll_set(struct nvkm_clk *, u32 type, u32 freq);
+int nv04_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, int clk,
+ struct nvkm_pll_vals *);
+int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *);
+int gt215_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *,
+ int clk, struct nvkm_pll_vals *);
+int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr);
+int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait);
+int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel);
+int nvkm_clk_tstate(struct nvkm_clk *, int req, int rel);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index f6004cc543c0..6dc59ffee68a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -65,7 +65,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
@@ -107,7 +107,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
#if 0
/* looks to be some non-trivial changes */
- device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
/* priv ring says no to 0x10eb14 writes */
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index e60deaee4d2f..9df93c5b7489 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -93,7 +93,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -122,7 +122,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -151,7 +151,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -180,7 +180,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -209,7 +209,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -238,7 +238,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
@@ -267,7 +267,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -296,7 +296,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
@@ -325,7 +325,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
@@ -354,7 +354,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
@@ -385,7 +385,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
@@ -415,7 +415,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
@@ -445,7 +445,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 89ff7d0d630b..8d0304f5de73 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -65,7 +65,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -98,7 +98,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -131,7 +131,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -163,7 +163,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -196,7 +196,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -228,7 +228,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -260,7 +260,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -293,7 +293,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -325,7 +325,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 11805f72f4e9..9f0efb1d5349 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -65,7 +65,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -99,7 +99,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -133,7 +133,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -189,7 +189,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -223,7 +223,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -257,7 +257,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -290,7 +290,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
index 94d10a9e637a..9c2f688c9602 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
@@ -2,11 +2,11 @@ nvkm-y += nvkm/subdev/clk/base.o
nvkm-y += nvkm/subdev/clk/nv04.o
nvkm-y += nvkm/subdev/clk/nv40.o
nvkm-y += nvkm/subdev/clk/nv50.o
-nvkm-y += nvkm/subdev/clk/nv84.o
-nvkm-y += nvkm/subdev/clk/nva3.o
-nvkm-y += nvkm/subdev/clk/nvaa.o
-nvkm-y += nvkm/subdev/clk/nvc0.o
-nvkm-y += nvkm/subdev/clk/nve0.o
+nvkm-y += nvkm/subdev/clk/g84.o
+nvkm-y += nvkm/subdev/clk/gt215.o
+nvkm-y += nvkm/subdev/clk/mcp77.o
+nvkm-y += nvkm/subdev/clk/gf100.o
+nvkm-y += nvkm/subdev/clk/gk104.o
nvkm-y += nvkm/subdev/clk/gk20a.o
nvkm-y += nvkm/subdev/clk/pllnv04.o
-nvkm-y += nvkm/subdev/clk/pllnva3.o
+nvkm-y += nvkm/subdev/clk/pllgt215.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
index a0c21ec3f61d..adfd3d93e066 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
@@ -21,27 +21,25 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/option.h>
-
#include <subdev/clk.h>
-#include <subdev/therm.h>
-#include <subdev/volt.h>
-#include <subdev/fb.h>
-
#include <subdev/bios.h>
#include <subdev/bios/boost.h>
#include <subdev/bios/cstep.h>
#include <subdev/bios/perf.h>
+#include <subdev/fb.h>
+#include <subdev/therm.h>
+#include <subdev/volt.h>
+
+#include <core/option.h>
/******************************************************************************
* misc
*****************************************************************************/
static u32
-nouveau_clk_adjust(struct nouveau_clk *clk, bool adjust,
- u8 pstate, u8 domain, u32 input)
+nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust,
+ u8 pstate, u8 domain, u32 input)
{
- struct nouveau_bios *bios = nouveau_bios(clk);
+ struct nvkm_bios *bios = nvkm_bios(clk);
struct nvbios_boostE boostE;
u8 ver, hdr, cnt, len;
u16 data;
@@ -76,12 +74,11 @@ nouveau_clk_adjust(struct nouveau_clk *clk, bool adjust,
* C-States
*****************************************************************************/
static int
-nouveau_cstate_prog(struct nouveau_clk *clk,
- struct nouveau_pstate *pstate, int cstatei)
+nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
{
- struct nouveau_therm *ptherm = nouveau_therm(clk);
- struct nouveau_volt *volt = nouveau_volt(clk);
- struct nouveau_cstate *cstate;
+ struct nvkm_therm *ptherm = nvkm_therm(clk);
+ struct nvkm_volt *volt = nvkm_volt(clk);
+ struct nvkm_cstate *cstate;
int ret;
if (!list_empty(&pstate->list)) {
@@ -91,7 +88,7 @@ nouveau_cstate_prog(struct nouveau_clk *clk,
}
if (ptherm) {
- ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1);
+ ret = nvkm_therm_cstate(ptherm, pstate->fanspeed, +1);
if (ret && ret != -ENODEV) {
nv_error(clk, "failed to raise fan speed: %d\n", ret);
return ret;
@@ -119,7 +116,7 @@ nouveau_cstate_prog(struct nouveau_clk *clk,
}
if (ptherm) {
- ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1);
+ ret = nvkm_therm_cstate(ptherm, pstate->fanspeed, -1);
if (ret && ret != -ENODEV)
nv_error(clk, "failed to lower fan speed: %d\n", ret);
}
@@ -128,19 +125,18 @@ nouveau_cstate_prog(struct nouveau_clk *clk,
}
static void
-nouveau_cstate_del(struct nouveau_cstate *cstate)
+nvkm_cstate_del(struct nvkm_cstate *cstate)
{
list_del(&cstate->head);
kfree(cstate);
}
static int
-nouveau_cstate_new(struct nouveau_clk *clk, int idx,
- struct nouveau_pstate *pstate)
+nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate)
{
- struct nouveau_bios *bios = nouveau_bios(clk);
- struct nouveau_domain *domain = clk->domains;
- struct nouveau_cstate *cstate = NULL;
+ struct nvkm_bios *bios = nvkm_bios(clk);
+ struct nvkm_domain *domain = clk->domains;
+ struct nvkm_cstate *cstate = NULL;
struct nvbios_cstepX cstepX;
u8 ver, hdr;
u16 data;
@@ -158,10 +154,8 @@ nouveau_cstate_new(struct nouveau_clk *clk, int idx,
while (domain && domain->name != nv_clk_src_max) {
if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
- u32 freq = nouveau_clk_adjust(clk, true,
- pstate->pstate,
- domain->bios,
- cstepX.freq);
+ u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate,
+ domain->bios, cstepX.freq);
cstate->domain[domain->name] = freq;
}
domain++;
@@ -175,10 +169,10 @@ nouveau_cstate_new(struct nouveau_clk *clk, int idx,
* P-States
*****************************************************************************/
static int
-nouveau_pstate_prog(struct nouveau_clk *clk, int pstatei)
+nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
{
- struct nouveau_fb *pfb = nouveau_fb(clk);
- struct nouveau_pstate *pstate;
+ struct nvkm_fb *pfb = nvkm_fb(clk);
+ struct nvkm_pstate *pstate;
int ret, idx = 0;
list_for_each_entry(pstate, &clk->states, head) {
@@ -199,13 +193,13 @@ nouveau_pstate_prog(struct nouveau_clk *clk, int pstatei)
pfb->ram->tidy(pfb);
}
- return nouveau_cstate_prog(clk, pstate, 0);
+ return nvkm_cstate_prog(clk, pstate, 0);
}
static void
-nouveau_pstate_work(struct work_struct *work)
+nvkm_pstate_work(struct work_struct *work)
{
- struct nouveau_clk *clk = container_of(work, typeof(*clk), work);
+ struct nvkm_clk *clk = container_of(work, typeof(*clk), work);
int pstate;
if (!atomic_xchg(&clk->waiting, 0))
@@ -227,7 +221,7 @@ nouveau_pstate_work(struct work_struct *work)
nv_trace(clk, "-> %d\n", pstate);
if (pstate != clk->pstate) {
- int ret = nouveau_pstate_prog(clk, pstate);
+ int ret = nvkm_pstate_prog(clk, pstate);
if (ret) {
nv_error(clk, "error setting pstate %d: %d\n",
pstate, ret);
@@ -239,7 +233,7 @@ nouveau_pstate_work(struct work_struct *work)
}
static int
-nouveau_pstate_calc(struct nouveau_clk *clk, bool wait)
+nvkm_pstate_calc(struct nvkm_clk *clk, bool wait)
{
atomic_set(&clk->waiting, 1);
schedule_work(&clk->work);
@@ -249,10 +243,10 @@ nouveau_pstate_calc(struct nouveau_clk *clk, bool wait)
}
static void
-nouveau_pstate_info(struct nouveau_clk *clk, struct nouveau_pstate *pstate)
+nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)
{
- struct nouveau_domain *clock = clk->domains - 1;
- struct nouveau_cstate *cstate;
+ struct nvkm_domain *clock = clk->domains - 1;
+ struct nvkm_cstate *cstate;
char info[3][32] = { "", "", "" };
char name[4] = "--";
int i = -1;
@@ -291,12 +285,12 @@ nouveau_pstate_info(struct nouveau_clk *clk, struct nouveau_pstate *pstate)
}
static void
-nouveau_pstate_del(struct nouveau_pstate *pstate)
+nvkm_pstate_del(struct nvkm_pstate *pstate)
{
- struct nouveau_cstate *cstate, *temp;
+ struct nvkm_cstate *cstate, *temp;
list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
- nouveau_cstate_del(cstate);
+ nvkm_cstate_del(cstate);
}
list_del(&pstate->head);
@@ -304,12 +298,12 @@ nouveau_pstate_del(struct nouveau_pstate *pstate)
}
static int
-nouveau_pstate_new(struct nouveau_clk *clk, int idx)
+nvkm_pstate_new(struct nvkm_clk *clk, int idx)
{
- struct nouveau_bios *bios = nouveau_bios(clk);
- struct nouveau_domain *domain = clk->domains - 1;
- struct nouveau_pstate *pstate;
- struct nouveau_cstate *cstate;
+ struct nvkm_bios *bios = nvkm_bios(clk);
+ struct nvkm_domain *domain = clk->domains - 1;
+ struct nvkm_pstate *pstate;
+ struct nvkm_cstate *cstate;
struct nvbios_cstepE cstepE;
struct nvbios_perfE perfE;
u8 ver, hdr, cnt, len;
@@ -346,10 +340,10 @@ nouveau_pstate_new(struct nouveau_clk *clk, int idx)
continue;
if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
- perfS.v40.freq = nouveau_clk_adjust(clk, false,
- pstate->pstate,
- domain->bios,
- perfS.v40.freq);
+ perfS.v40.freq = nvkm_clk_adjust(clk, false,
+ pstate->pstate,
+ domain->bios,
+ perfS.v40.freq);
}
cstate->domain[domain->name] = perfS.v40.freq;
@@ -359,11 +353,11 @@ nouveau_pstate_new(struct nouveau_clk *clk, int idx)
if (data) {
int idx = cstepE.index;
do {
- nouveau_cstate_new(clk, idx, pstate);
+ nvkm_cstate_new(clk, idx, pstate);
} while(idx--);
}
- nouveau_pstate_info(clk, pstate);
+ nvkm_pstate_info(clk, pstate);
list_add_tail(&pstate->head, &clk->states);
clk->state_nr++;
return 0;
@@ -373,9 +367,9 @@ nouveau_pstate_new(struct nouveau_clk *clk, int idx)
* Adjustment triggers
*****************************************************************************/
static int
-nouveau_clk_ustate_update(struct nouveau_clk *clk, int req)
+nvkm_clk_ustate_update(struct nvkm_clk *clk, int req)
{
- struct nouveau_pstate *pstate;
+ struct nvkm_pstate *pstate;
int i = 0;
if (!clk->allow_reclock)
@@ -397,7 +391,7 @@ nouveau_clk_ustate_update(struct nouveau_clk *clk, int req)
}
static int
-nouveau_clk_nstate(struct nouveau_clk *clk, const char *mode, int arglen)
+nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen)
{
int ret = 1;
@@ -410,7 +404,7 @@ nouveau_clk_nstate(struct nouveau_clk *clk, const char *mode, int arglen)
((char *)mode)[arglen] = '\0';
if (!kstrtol(mode, 0, &v)) {
- ret = nouveau_clk_ustate_update(clk, v);
+ ret = nvkm_clk_ustate_update(clk, v);
if (ret < 0)
ret = 1;
}
@@ -421,53 +415,53 @@ nouveau_clk_nstate(struct nouveau_clk *clk, const char *mode, int arglen)
}
int
-nouveau_clk_ustate(struct nouveau_clk *clk, int req, int pwr)
+nvkm_clk_ustate(struct nvkm_clk *clk, int req, int pwr)
{
- int ret = nouveau_clk_ustate_update(clk, req);
+ int ret = nvkm_clk_ustate_update(clk, req);
if (ret >= 0) {
if (ret -= 2, pwr) clk->ustate_ac = ret;
else clk->ustate_dc = ret;
- return nouveau_pstate_calc(clk, true);
+ return nvkm_pstate_calc(clk, true);
}
return ret;
}
int
-nouveau_clk_astate(struct nouveau_clk *clk, int req, int rel, bool wait)
+nvkm_clk_astate(struct nvkm_clk *clk, int req, int rel, bool wait)
{
if (!rel) clk->astate = req;
if ( rel) clk->astate += rel;
clk->astate = min(clk->astate, clk->state_nr - 1);
clk->astate = max(clk->astate, 0);
- return nouveau_pstate_calc(clk, wait);
+ return nvkm_pstate_calc(clk, wait);
}
int
-nouveau_clk_tstate(struct nouveau_clk *clk, int req, int rel)
+nvkm_clk_tstate(struct nvkm_clk *clk, int req, int rel)
{
if (!rel) clk->tstate = req;
if ( rel) clk->tstate += rel;
clk->tstate = min(clk->tstate, 0);
clk->tstate = max(clk->tstate, -(clk->state_nr - 1));
- return nouveau_pstate_calc(clk, true);
+ return nvkm_pstate_calc(clk, true);
}
int
-nouveau_clk_dstate(struct nouveau_clk *clk, int req, int rel)
+nvkm_clk_dstate(struct nvkm_clk *clk, int req, int rel)
{
if (!rel) clk->dstate = req;
if ( rel) clk->dstate += rel;
clk->dstate = min(clk->dstate, clk->state_nr - 1);
clk->dstate = max(clk->dstate, 0);
- return nouveau_pstate_calc(clk, true);
+ return nvkm_pstate_calc(clk, true);
}
static int
-nouveau_clk_pwrsrc(struct nvkm_notify *notify)
+nvkm_clk_pwrsrc(struct nvkm_notify *notify)
{
- struct nouveau_clk *clk =
+ struct nvkm_clk *clk =
container_of(notify, typeof(*clk), pwrsrc_ntfy);
- nouveau_pstate_calc(clk, false);
+ nvkm_pstate_calc(clk, false);
return NVKM_NOTIFY_DROP;
}
@@ -476,21 +470,21 @@ nouveau_clk_pwrsrc(struct nvkm_notify *notify)
*****************************************************************************/
int
-_nouveau_clk_fini(struct nouveau_object *object, bool suspend)
+_nvkm_clk_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_clk *clk = (void *)object;
+ struct nvkm_clk *clk = (void *)object;
nvkm_notify_put(&clk->pwrsrc_ntfy);
- return nouveau_subdev_fini(&clk->base, suspend);
+ return nvkm_subdev_fini(&clk->base, suspend);
}
int
-_nouveau_clk_init(struct nouveau_object *object)
+_nvkm_clk_init(struct nvkm_object *object)
{
- struct nouveau_clk *clk = (void *)object;
- struct nouveau_domain *clock = clk->domains;
+ struct nvkm_clk *clk = (void *)object;
+ struct nvkm_domain *clock = clk->domains;
int ret;
- ret = nouveau_subdev_init(&clk->base);
+ ret = nvkm_subdev_init(&clk->base);
if (ret)
return ret;
@@ -508,47 +502,44 @@ _nouveau_clk_init(struct nouveau_object *object)
clock++;
}
- nouveau_pstate_info(clk, &clk->bstate);
+ nvkm_pstate_info(clk, &clk->bstate);
clk->astate = clk->state_nr - 1;
clk->tstate = 0;
clk->dstate = 0;
clk->pstate = -1;
- nouveau_pstate_calc(clk, true);
+ nvkm_pstate_calc(clk, true);
return 0;
}
void
-_nouveau_clk_dtor(struct nouveau_object *object)
+_nvkm_clk_dtor(struct nvkm_object *object)
{
- struct nouveau_clk *clk = (void *)object;
- struct nouveau_pstate *pstate, *temp;
+ struct nvkm_clk *clk = (void *)object;
+ struct nvkm_pstate *pstate, *temp;
nvkm_notify_fini(&clk->pwrsrc_ntfy);
list_for_each_entry_safe(pstate, temp, &clk->states, head) {
- nouveau_pstate_del(pstate);
+ nvkm_pstate_del(pstate);
}
- nouveau_subdev_destroy(&clk->base);
+ nvkm_subdev_destroy(&clk->base);
}
int
-nouveau_clk_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass,
- struct nouveau_domain *clocks,
- struct nouveau_pstate *pstates, int nb_pstates,
- bool allow_reclock,
- int length, void **object)
+nvkm_clk_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, struct nvkm_domain *clocks,
+ struct nvkm_pstate *pstates, int nb_pstates,
+ bool allow_reclock, int length, void **object)
{
- struct nouveau_device *device = nv_device(parent);
- struct nouveau_clk *clk;
+ struct nvkm_device *device = nv_device(parent);
+ struct nvkm_clk *clk;
int ret, idx, arglen;
const char *mode;
- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "CLK",
- "clock", length, object);
+ ret = nvkm_subdev_create_(parent, engine, oclass, 0, "CLK",
+ "clock", length, object);
clk = *object;
if (ret)
return ret;
@@ -558,7 +549,7 @@ nouveau_clk_create_(struct nouveau_object *parent,
clk->ustate_ac = -1;
clk->ustate_dc = -1;
- INIT_WORK(&clk->work, nouveau_pstate_work);
+ INIT_WORK(&clk->work, nvkm_pstate_work);
init_waitqueue_head(&clk->wait);
atomic_set(&clk->waiting, 0);
@@ -566,7 +557,7 @@ nouveau_clk_create_(struct nouveau_object *parent,
if (!pstates) {
idx = 0;
do {
- ret = nouveau_pstate_new(clk, idx++);
+ ret = nvkm_pstate_new(clk, idx++);
} while (ret == 0);
} else {
for (idx = 0; idx < nb_pstates; idx++)
@@ -576,25 +567,24 @@ nouveau_clk_create_(struct nouveau_object *parent,
clk->allow_reclock = allow_reclock;
- ret = nvkm_notify_init(NULL, &device->event, nouveau_clk_pwrsrc, true,
+ ret = nvkm_notify_init(NULL, &device->event, nvkm_clk_pwrsrc, true,
NULL, 0, 0, &clk->pwrsrc_ntfy);
if (ret)
return ret;
- mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen);
+ mode = nvkm_stropt(device->cfgopt, "NvClkMode", &arglen);
if (mode) {
- clk->ustate_ac = nouveau_clk_nstate(clk, mode, arglen);
- clk->ustate_dc = nouveau_clk_nstate(clk, mode, arglen);
+ clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen);
+ clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen);
}
- mode = nouveau_stropt(device->cfgopt, "NvClkModeAC", &arglen);
+ mode = nvkm_stropt(device->cfgopt, "NvClkModeAC", &arglen);
if (mode)
- clk->ustate_ac = nouveau_clk_nstate(clk, mode, arglen);
+ clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen);
- mode = nouveau_stropt(device->cfgopt, "NvClkModeDC", &arglen);
+ mode = nvkm_stropt(device->cfgopt, "NvClkModeDC", &arglen);
if (mode)
- clk->ustate_dc = nouveau_clk_nstate(clk, mode, arglen);
-
+ clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen);
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c
similarity index 84%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c
index b5b00b3df6c4..4c90b9769d64 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c
@@ -21,11 +21,10 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
#include "nv50.h"
-static struct nouveau_domain
-nv84_domains[] = {
+static struct nvkm_domain
+g84_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
@@ -35,14 +34,14 @@ nv84_domains[] = {
{ nv_clk_src_max }
};
-struct nouveau_oclass *
-nv84_clk_oclass = &(struct nv50_clk_oclass) {
+struct nvkm_oclass *
+g84_clk_oclass = &(struct nv50_clk_oclass) {
.base.handle = NV_SUBDEV(CLK, 0x84),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_clk_ctor,
- .dtor = _nouveau_clk_dtor,
- .init = _nouveau_clk_init,
- .fini = _nouveau_clk_fini,
+ .dtor = _nvkm_clk_dtor,
+ .init = _nvkm_clk_init,
+ .fini = _nvkm_clk_fini,
},
- .domains = nv84_domains,
+ .domains = g84_domains,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
similarity index 75%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
index 791a9f5198eb..e8125b5199a4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/clk.h>
+#include "pll.h"
+
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
-#include "pll.h"
-
-struct nvc0_clk_info {
+struct gf100_clk_info {
u32 freq;
u32 ssel;
u32 mdiv;
@@ -38,17 +37,17 @@ struct nvc0_clk_info {
u32 coef;
};
-struct nvc0_clk_priv {
- struct nouveau_clk base;
- struct nvc0_clk_info eng[16];
+struct gf100_clk_priv {
+ struct nvkm_clk base;
+ struct gf100_clk_info eng[16];
};
-static u32 read_div(struct nvc0_clk_priv *, int, u32, u32);
+static u32 read_div(struct gf100_clk_priv *, int, u32, u32);
static u32
-read_vco(struct nvc0_clk_priv *priv, u32 dsrc)
+read_vco(struct gf100_clk_priv *priv, u32 dsrc)
{
- struct nouveau_clk *clk = &priv->base;
+ struct nvkm_clk *clk = &priv->base;
u32 ssrc = nv_rd32(priv, dsrc);
if (!(ssrc & 0x00000100))
return clk->read(clk, nv_clk_src_sppll0);
@@ -56,9 +55,9 @@ read_vco(struct nvc0_clk_priv *priv, u32 dsrc)
}
static u32
-read_pll(struct nvc0_clk_priv *priv, u32 pll)
+read_pll(struct gf100_clk_priv *priv, u32 pll)
{
- struct nouveau_clk *clk = &priv->base;
+ struct nvkm_clk *clk = &priv->base;
u32 ctrl = nv_rd32(priv, pll + 0x00);
u32 coef = nv_rd32(priv, pll + 0x04);
u32 P = (coef & 0x003f0000) >> 16;
@@ -95,7 +94,7 @@ read_pll(struct nvc0_clk_priv *priv, u32 pll)
}
static u32
-read_div(struct nvc0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
+read_div(struct gf100_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
{
u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
u32 sctl = nv_rd32(priv, dctl + (doff * 4));
@@ -121,7 +120,7 @@ read_div(struct nvc0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
}
static u32
-read_clk(struct nvc0_clk_priv *priv, int clk)
+read_clk(struct gf100_clk_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
u32 ssel = nv_rd32(priv, 0x137100);
@@ -145,10 +144,10 @@ read_clk(struct nvc0_clk_priv *priv, int clk)
}
static int
-nvc0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
+gf100_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
- struct nouveau_device *device = nv_device(clk);
- struct nvc0_clk_priv *priv = (void *)clk;
+ struct nvkm_device *device = nv_device(clk);
+ struct gf100_clk_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
@@ -196,7 +195,7 @@ nvc0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
}
static u32
-calc_div(struct nvc0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
+calc_div(struct gf100_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
{
u32 div = min((ref * 2) / freq, (u32)65);
if (div < 2)
@@ -207,7 +206,7 @@ calc_div(struct nvc0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
}
static u32
-calc_src(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
+calc_src(struct gf100_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
{
u32 sclk;
@@ -236,9 +235,9 @@ calc_src(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
}
static u32
-calc_pll(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *coef)
+calc_pll(struct gf100_clk_priv *priv, int clk, u32 freq, u32 *coef)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_pll limits;
int N, M, P, ret;
@@ -250,7 +249,7 @@ calc_pll(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *coef)
if (!limits.refclk)
return 0;
- ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
+ ret = gt215_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
if (ret <= 0)
return 0;
@@ -259,10 +258,10 @@ calc_pll(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *coef)
}
static int
-calc_clk(struct nvc0_clk_priv *priv,
- struct nouveau_cstate *cstate, int clk, int dom)
+calc_clk(struct gf100_clk_priv *priv,
+ struct nvkm_cstate *cstate, int clk, int dom)
{
- struct nvc0_clk_info *info = &priv->eng[clk];
+ struct gf100_clk_info *info = &priv->eng[clk];
u32 freq = cstate->domain[dom];
u32 src0, div0, div1D, div1P = 0;
u32 clk0, clk1 = 0;
@@ -311,9 +310,9 @@ calc_clk(struct nvc0_clk_priv *priv,
}
static int
-nvc0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
+gf100_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
- struct nvc0_clk_priv *priv = (void *)clk;
+ struct gf100_clk_priv *priv = (void *)clk;
int ret;
if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
@@ -330,9 +329,9 @@ nvc0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
}
static void
-nvc0_clk_prog_0(struct nvc0_clk_priv *priv, int clk)
+gf100_clk_prog_0(struct gf100_clk_priv *priv, int clk)
{
- struct nvc0_clk_info *info = &priv->eng[clk];
+ struct gf100_clk_info *info = &priv->eng[clk];
if (clk < 7 && !info->ssel) {
nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
@@ -340,16 +339,16 @@ nvc0_clk_prog_0(struct nvc0_clk_priv *priv, int clk)
}
static void
-nvc0_clk_prog_1(struct nvc0_clk_priv *priv, int clk)
+gf100_clk_prog_1(struct gf100_clk_priv *priv, int clk)
{
nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
}
static void
-nvc0_clk_prog_2(struct nvc0_clk_priv *priv, int clk)
+gf100_clk_prog_2(struct gf100_clk_priv *priv, int clk)
{
- struct nvc0_clk_info *info = &priv->eng[clk];
+ struct gf100_clk_info *info = &priv->eng[clk];
const u32 addr = 0x137000 + (clk * 0x20);
if (clk <= 7) {
nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
@@ -364,9 +363,9 @@ nvc0_clk_prog_2(struct nvc0_clk_priv *priv, int clk)
}
static void
-nvc0_clk_prog_3(struct nvc0_clk_priv *priv, int clk)
+gf100_clk_prog_3(struct gf100_clk_priv *priv, int clk)
{
- struct nvc0_clk_info *info = &priv->eng[clk];
+ struct gf100_clk_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137100, (1 << clk), info->ssel);
nv_wait(priv, 0x137100, (1 << clk), info->ssel);
@@ -374,24 +373,24 @@ nvc0_clk_prog_3(struct nvc0_clk_priv *priv, int clk)
}
static void
-nvc0_clk_prog_4(struct nvc0_clk_priv *priv, int clk)
+gf100_clk_prog_4(struct gf100_clk_priv *priv, int clk)
{
- struct nvc0_clk_info *info = &priv->eng[clk];
+ struct gf100_clk_info *info = &priv->eng[clk];
nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
}
static int
-nvc0_clk_prog(struct nouveau_clk *clk)
+gf100_clk_prog(struct nvkm_clk *clk)
{
- struct nvc0_clk_priv *priv = (void *)clk;
+ struct gf100_clk_priv *priv = (void *)clk;
struct {
- void (*exec)(struct nvc0_clk_priv *, int);
+ void (*exec)(struct gf100_clk_priv *, int);
} stage[] = {
- { nvc0_clk_prog_0 }, /* div programming */
- { nvc0_clk_prog_1 }, /* select div mode */
- { nvc0_clk_prog_2 }, /* (maybe) program pll */
- { nvc0_clk_prog_3 }, /* (maybe) select pll mode */
- { nvc0_clk_prog_4 }, /* final divider */
+ { gf100_clk_prog_0 }, /* div programming */
+ { gf100_clk_prog_1 }, /* select div mode */
+ { gf100_clk_prog_2 }, /* (maybe) program pll */
+ { gf100_clk_prog_3 }, /* (maybe) select pll mode */
+ { gf100_clk_prog_4 }, /* final divider */
};
int i, j;
@@ -407,14 +406,14 @@ nvc0_clk_prog(struct nouveau_clk *clk)
}
static void
-nvc0_clk_tidy(struct nouveau_clk *clk)
+gf100_clk_tidy(struct nvkm_clk *clk)
{
- struct nvc0_clk_priv *priv = (void *)clk;
+ struct gf100_clk_priv *priv = (void *)clk;
memset(priv->eng, 0x00, sizeof(priv->eng));
}
-static struct nouveau_domain
-nvc0_domain[] = {
+static struct nvkm_domain
+gf100_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_hubk06 , 0x00 },
@@ -430,33 +429,33 @@ nvc0_domain[] = {
};
static int
-nvc0_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvc0_clk_priv *priv;
+ struct gf100_clk_priv *priv;
int ret;
- ret = nouveau_clk_create(parent, engine, oclass, nvc0_domain, NULL, 0,
- false, &priv);
+ ret = nvkm_clk_create(parent, engine, oclass, gf100_domain,
+ NULL, 0, false, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.read = nvc0_clk_read;
- priv->base.calc = nvc0_clk_calc;
- priv->base.prog = nvc0_clk_prog;
- priv->base.tidy = nvc0_clk_tidy;
+ priv->base.read = gf100_clk_read;
+ priv->base.calc = gf100_clk_calc;
+ priv->base.prog = gf100_clk_prog;
+ priv->base.tidy = gf100_clk_tidy;
return 0;
}
-struct nouveau_oclass
-nvc0_clk_oclass = {
+struct nvkm_oclass
+gf100_clk_oclass = {
.handle = NV_SUBDEV(CLK, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_clk_ctor,
- .dtor = _nouveau_clk_dtor,
- .init = _nouveau_clk_init,
- .fini = _nouveau_clk_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_clk_ctor,
+ .dtor = _nvkm_clk_dtor,
+ .init = _nvkm_clk_init,
+ .fini = _nvkm_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
similarity index 75%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
index ffd2139e0a49..e380d62df232 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/clk.h>
+#include "pll.h"
+
#include <subdev/timer.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
-#include "pll.h"
-
-struct nve0_clk_info {
+struct gk104_clk_info {
u32 freq;
u32 ssel;
u32 mdiv;
@@ -38,16 +37,16 @@ struct nve0_clk_info {
u32 coef;
};
-struct nve0_clk_priv {
- struct nouveau_clk base;
- struct nve0_clk_info eng[16];
+struct gk104_clk_priv {
+ struct nvkm_clk base;
+ struct gk104_clk_info eng[16];
};
-static u32 read_div(struct nve0_clk_priv *, int, u32, u32);
-static u32 read_pll(struct nve0_clk_priv *, u32);
+static u32 read_div(struct gk104_clk_priv *, int, u32, u32);
+static u32 read_pll(struct gk104_clk_priv *, u32);
static u32
-read_vco(struct nve0_clk_priv *priv, u32 dsrc)
+read_vco(struct gk104_clk_priv *priv, u32 dsrc)
{
u32 ssrc = nv_rd32(priv, dsrc);
if (!(ssrc & 0x00000100))
@@ -56,7 +55,7 @@ read_vco(struct nve0_clk_priv *priv, u32 dsrc)
}
static u32
-read_pll(struct nve0_clk_priv *priv, u32 pll)
+read_pll(struct gk104_clk_priv *priv, u32 pll)
{
u32 ctrl = nv_rd32(priv, pll + 0x00);
u32 coef = nv_rd32(priv, pll + 0x04);
@@ -101,7 +100,7 @@ read_pll(struct nve0_clk_priv *priv, u32 pll)
}
static u32
-read_div(struct nve0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
+read_div(struct gk104_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
{
u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
u32 sctl = nv_rd32(priv, dctl + (doff * 4));
@@ -127,7 +126,7 @@ read_div(struct nve0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
}
static u32
-read_mem(struct nve0_clk_priv *priv)
+read_mem(struct gk104_clk_priv *priv)
{
switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) {
case 1: return read_pll(priv, 0x132020);
@@ -138,7 +137,7 @@ read_mem(struct nve0_clk_priv *priv)
}
static u32
-read_clk(struct nve0_clk_priv *priv, int clk)
+read_clk(struct gk104_clk_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
u32 sclk, sdiv;
@@ -181,10 +180,10 @@ read_clk(struct nve0_clk_priv *priv, int clk)
}
static int
-nve0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
+gk104_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
- struct nouveau_device *device = nv_device(clk);
- struct nve0_clk_priv *priv = (void *)clk;
+ struct nvkm_device *device = nv_device(clk);
+ struct gk104_clk_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
@@ -214,7 +213,7 @@ nve0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
}
static u32
-calc_div(struct nve0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
+calc_div(struct gk104_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
{
u32 div = min((ref * 2) / freq, (u32)65);
if (div < 2)
@@ -225,7 +224,7 @@ calc_div(struct nve0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
}
static u32
-calc_src(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
+calc_src(struct gk104_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
{
u32 sclk;
@@ -254,9 +253,9 @@ calc_src(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
}
static u32
-calc_pll(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *coef)
+calc_pll(struct gk104_clk_priv *priv, int clk, u32 freq, u32 *coef)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_pll limits;
int N, M, P, ret;
@@ -268,7 +267,7 @@ calc_pll(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *coef)
if (!limits.refclk)
return 0;
- ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
+ ret = gt215_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
if (ret <= 0)
return 0;
@@ -277,10 +276,10 @@ calc_pll(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *coef)
}
static int
-calc_clk(struct nve0_clk_priv *priv,
- struct nouveau_cstate *cstate, int clk, int dom)
+calc_clk(struct gk104_clk_priv *priv,
+ struct nvkm_cstate *cstate, int clk, int dom)
{
- struct nve0_clk_info *info = &priv->eng[clk];
+ struct gk104_clk_info *info = &priv->eng[clk];
u32 freq = cstate->domain[dom];
u32 src0, div0, div1D, div1P = 0;
u32 clk0, clk1 = 0;
@@ -329,9 +328,9 @@ calc_clk(struct nve0_clk_priv *priv,
}
static int
-nve0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
+gk104_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
- struct nve0_clk_priv *priv = (void *)clk;
+ struct gk104_clk_priv *priv = (void *)clk;
int ret;
if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
@@ -347,9 +346,9 @@ nve0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
}
static void
-nve0_clk_prog_0(struct nve0_clk_priv *priv, int clk)
+gk104_clk_prog_0(struct gk104_clk_priv *priv, int clk)
{
- struct nve0_clk_info *info = &priv->eng[clk];
+ struct gk104_clk_info *info = &priv->eng[clk];
if (!info->ssel) {
nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv);
nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
@@ -357,22 +356,22 @@ nve0_clk_prog_0(struct nve0_clk_priv *priv, int clk)
}
static void
-nve0_clk_prog_1_0(struct nve0_clk_priv *priv, int clk)
+gk104_clk_prog_1_0(struct gk104_clk_priv *priv, int clk)
{
nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
}
static void
-nve0_clk_prog_1_1(struct nve0_clk_priv *priv, int clk)
+gk104_clk_prog_1_1(struct gk104_clk_priv *priv, int clk)
{
nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000);
}
static void
-nve0_clk_prog_2(struct nve0_clk_priv *priv, int clk)
+gk104_clk_prog_2(struct gk104_clk_priv *priv, int clk)
{
- struct nve0_clk_info *info = &priv->eng[clk];
+ struct gk104_clk_info *info = &priv->eng[clk];
const u32 addr = 0x137000 + (clk * 0x20);
nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
@@ -385,9 +384,9 @@ nve0_clk_prog_2(struct nve0_clk_priv *priv, int clk)
}
static void
-nve0_clk_prog_3(struct nve0_clk_priv *priv, int clk)
+gk104_clk_prog_3(struct gk104_clk_priv *priv, int clk)
{
- struct nve0_clk_info *info = &priv->eng[clk];
+ struct gk104_clk_info *info = &priv->eng[clk];
if (info->ssel)
nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv);
else
@@ -395,9 +394,9 @@ nve0_clk_prog_3(struct nve0_clk_priv *priv, int clk)
}
static void
-nve0_clk_prog_4_0(struct nve0_clk_priv *priv, int clk)
+gk104_clk_prog_4_0(struct gk104_clk_priv *priv, int clk)
{
- struct nve0_clk_info *info = &priv->eng[clk];
+ struct gk104_clk_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137100, (1 << clk), info->ssel);
nv_wait(priv, 0x137100, (1 << clk), info->ssel);
@@ -405,9 +404,9 @@ nve0_clk_prog_4_0(struct nve0_clk_priv *priv, int clk)
}
static void
-nve0_clk_prog_4_1(struct nve0_clk_priv *priv, int clk)
+gk104_clk_prog_4_1(struct gk104_clk_priv *priv, int clk)
{
- struct nve0_clk_info *info = &priv->eng[clk];
+ struct gk104_clk_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000);
nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100);
@@ -415,20 +414,20 @@ nve0_clk_prog_4_1(struct nve0_clk_priv *priv, int clk)
}
static int
-nve0_clk_prog(struct nouveau_clk *clk)
+gk104_clk_prog(struct nvkm_clk *clk)
{
- struct nve0_clk_priv *priv = (void *)clk;
+ struct gk104_clk_priv *priv = (void *)clk;
struct {
u32 mask;
- void (*exec)(struct nve0_clk_priv *, int);
+ void (*exec)(struct gk104_clk_priv *, int);
} stage[] = {
- { 0x007f, nve0_clk_prog_0 }, /* div programming */
- { 0x007f, nve0_clk_prog_1_0 }, /* select div mode */
- { 0xff80, nve0_clk_prog_1_1 },
- { 0x00ff, nve0_clk_prog_2 }, /* (maybe) program pll */
- { 0xff80, nve0_clk_prog_3 }, /* final divider */
- { 0x007f, nve0_clk_prog_4_0 }, /* (maybe) select pll mode */
- { 0xff80, nve0_clk_prog_4_1 },
+ { 0x007f, gk104_clk_prog_0 }, /* div programming */
+ { 0x007f, gk104_clk_prog_1_0 }, /* select div mode */
+ { 0xff80, gk104_clk_prog_1_1 },
+ { 0x00ff, gk104_clk_prog_2 }, /* (maybe) program pll */
+ { 0xff80, gk104_clk_prog_3 }, /* final divider */
+ { 0x007f, gk104_clk_prog_4_0 }, /* (maybe) select pll mode */
+ { 0xff80, gk104_clk_prog_4_1 },
};
int i, j;
@@ -446,14 +445,14 @@ nve0_clk_prog(struct nouveau_clk *clk)
}
static void
-nve0_clk_tidy(struct nouveau_clk *clk)
+gk104_clk_tidy(struct nvkm_clk *clk)
{
- struct nve0_clk_priv *priv = (void *)clk;
+ struct gk104_clk_priv *priv = (void *)clk;
memset(priv->eng, 0x00, sizeof(priv->eng));
}
-static struct nouveau_domain
-nve0_domain[] = {
+static struct nvkm_domain
+gk104_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 },
@@ -468,33 +467,33 @@ nve0_domain[] = {
};
static int
-nve0_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk104_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nve0_clk_priv *priv;
+ struct gk104_clk_priv *priv;
int ret;
- ret = nouveau_clk_create(parent, engine, oclass, nve0_domain, NULL, 0,
- true, &priv);
+ ret = nvkm_clk_create(parent, engine, oclass, gk104_domain,
+ NULL, 0, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.read = nve0_clk_read;
- priv->base.calc = nve0_clk_calc;
- priv->base.prog = nve0_clk_prog;
- priv->base.tidy = nve0_clk_tidy;
+ priv->base.read = gk104_clk_read;
+ priv->base.calc = gk104_clk_calc;
+ priv->base.prog = gk104_clk_prog;
+ priv->base.tidy = gk104_clk_tidy;
return 0;
}
-struct nouveau_oclass
-nve0_clk_oclass = {
+struct nvkm_oclass
+gk104_clk_oclass = {
.handle = NV_SUBDEV(CLK, 0xe0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_clk_ctor,
- .dtor = _nouveau_clk_dtor,
- .init = _nouveau_clk_init,
- .fini = _nouveau_clk_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_clk_ctor,
+ .dtor = _nvkm_clk_dtor,
+ .init = _nvkm_clk_init,
+ .fini = _nvkm_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
index 4529ba20af5e..94d3839fd444 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
@@ -22,6 +22,12 @@
* Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c
*
*/
+#include <subdev/clk.h>
+#include <subdev/timer.h>
+
+#ifdef __KERNEL__
+#include <nouveau_platform.h>
+#endif
#define MHZ (1000 * 1000)
@@ -87,13 +93,6 @@
#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \
(0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT)
-#include <subdev/clk.h>
-#include <subdev/timer.h>
-
-#ifdef __KERNEL__
-#include <nouveau_platform.h>
-#endif
-
static const u8 pl_to_div[] = {
/* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32,
@@ -117,7 +116,7 @@ static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
};
struct gk20a_clk_priv {
- struct nouveau_clk base;
+ struct nvkm_clk base;
const struct gk20a_clk_pllg_params *params;
u32 m, n, pl;
u32 parent_rate;
@@ -260,7 +259,6 @@ found_match:
nv_debug(priv, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n",
target_freq, priv->m, priv->n, priv->pl, pl_to_div[priv->pl]);
-
return 0;
}
@@ -402,8 +400,8 @@ _gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv, bool allow_slide)
nv_wr32(priv, GPCPLL_CFG, val);
}
- if (!nouveau_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK,
- GPCPLL_CFG_LOCK)) {
+ if (!nvkm_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK,
+ GPCPLL_CFG_LOCK)) {
nv_error(priv, "%s: timeout waiting for pllg lock\n", __func__);
return -ETIMEDOUT;
}
@@ -458,14 +456,14 @@ gk20a_pllg_disable(struct gk20a_clk_priv *priv)
#define GK20A_CLK_GPC_MDIV 1000
-static struct nouveau_domain
+static struct nvkm_domain
gk20a_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
{ nv_clk_src_max }
};
-static struct nouveau_pstate
+static struct nvkm_pstate
gk20a_pstates[] = {
{
.base = {
@@ -560,7 +558,7 @@ gk20a_pstates[] = {
};
static int
-gk20a_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
+gk20a_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
struct gk20a_clk_priv *priv = (void *)clk;
@@ -577,7 +575,7 @@ gk20a_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
}
static int
-gk20a_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
+gk20a_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
struct gk20a_clk_priv *priv = (void *)clk;
@@ -586,7 +584,7 @@ gk20a_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
}
static int
-gk20a_clk_prog(struct nouveau_clk *clk)
+gk20a_clk_prog(struct nvkm_clk *clk)
{
struct gk20a_clk_priv *priv = (void *)clk;
@@ -594,17 +592,17 @@ gk20a_clk_prog(struct nouveau_clk *clk)
}
static void
-gk20a_clk_tidy(struct nouveau_clk *clk)
+gk20a_clk_tidy(struct nvkm_clk *clk)
{
}
static int
-gk20a_clk_fini(struct nouveau_object *object, bool suspend)
+gk20a_clk_fini(struct nvkm_object *object, bool suspend)
{
struct gk20a_clk_priv *priv = (void *)object;
int ret;
- ret = nouveau_clk_fini(&priv->base, false);
+ ret = nvkm_clk_fini(&priv->base, false);
gk20a_pllg_disable(priv);
@@ -612,14 +610,14 @@ gk20a_clk_fini(struct nouveau_object *object, bool suspend)
}
static int
-gk20a_clk_init(struct nouveau_object *object)
+gk20a_clk_init(struct nvkm_object *object)
{
struct gk20a_clk_priv *priv = (void *)object;
int ret;
nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL);
- ret = nouveau_clk_init(&priv->base);
+ ret = nvkm_clk_init(&priv->base);
if (ret)
return ret;
@@ -633,9 +631,9 @@ gk20a_clk_init(struct nouveau_object *object)
}
static int
-gk20a_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk20a_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct gk20a_clk_priv *priv;
struct nouveau_platform_device *plat;
@@ -648,8 +646,9 @@ gk20a_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
gk20a_pstates[i].pstate = i + 1;
}
- ret = nouveau_clk_create(parent, engine, oclass, gk20a_domains,
- gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv);
+ ret = nvkm_clk_create(parent, engine, oclass, gk20a_domains,
+ gk20a_pstates, ARRAY_SIZE(gk20a_pstates),
+ true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -664,16 +663,15 @@ gk20a_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.calc = gk20a_clk_calc;
priv->base.prog = gk20a_clk_prog;
priv->base.tidy = gk20a_clk_tidy;
-
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
gk20a_clk_oclass = {
.handle = NV_SUBDEV(CLK, 0xea),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_clk_ctor,
- .dtor = _nouveau_subdev_dtor,
+ .dtor = _nvkm_subdev_dtor,
.init = gk20a_clk_init,
.fini = gk20a_clk_fini,
},
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
similarity index 75%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
index 3002c60a3993..99e3ca3b0890 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
@@ -22,26 +22,24 @@
* Authors: Ben Skeggs
* Roy Spliet
*/
+#include "gt215.h"
+#include "pll.h"
#include <engine/fifo.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
-#include "pll.h"
-
-#include "nva3.h"
-
-struct nva3_clk_priv {
- struct nouveau_clk base;
- struct nva3_clk_info eng[nv_clk_src_max];
+struct gt215_clk_priv {
+ struct nvkm_clk base;
+ struct gt215_clk_info eng[nv_clk_src_max];
};
-static u32 read_clk(struct nva3_clk_priv *, int, bool);
-static u32 read_pll(struct nva3_clk_priv *, int, u32);
+static u32 read_clk(struct gt215_clk_priv *, int, bool);
+static u32 read_pll(struct gt215_clk_priv *, int, u32);
static u32
-read_vco(struct nva3_clk_priv *priv, int clk)
+read_vco(struct gt215_clk_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
@@ -58,7 +56,7 @@ read_vco(struct nva3_clk_priv *priv, int clk)
}
static u32
-read_clk(struct nva3_clk_priv *priv, int clk, bool ignore_en)
+read_clk(struct gt215_clk_priv *priv, int clk, bool ignore_en)
{
u32 sctl, sdiv, sclk;
@@ -104,7 +102,7 @@ read_clk(struct nva3_clk_priv *priv, int clk, bool ignore_en)
}
static u32
-read_pll(struct nva3_clk_priv *priv, int clk, u32 pll)
+read_pll(struct gt215_clk_priv *priv, int clk, u32 pll)
{
u32 ctrl = nv_rd32(priv, pll + 0);
u32 sclk = 0, P = 1, N = 1, M = 1;
@@ -130,13 +128,14 @@ read_pll(struct nva3_clk_priv *priv, int clk, u32 pll)
if (M * P)
return sclk * N / (M * P);
+
return 0;
}
static int
-nva3_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
+gt215_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
- struct nva3_clk_priv *priv = (void *)clk;
+ struct gt215_clk_priv *priv = (void *)clk;
u32 hsrc;
switch (src) {
@@ -176,10 +175,10 @@ nva3_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
}
int
-nva3_clk_info(struct nouveau_clk *clock, int clk, u32 khz,
- struct nva3_clk_info *info)
+gt215_clk_info(struct nvkm_clk *clock, int clk, u32 khz,
+ struct gt215_clk_info *info)
{
- struct nva3_clk_priv *priv = (void *)clock;
+ struct gt215_clk_priv *priv = (void *)clock;
u32 oclk, sclk, sdiv, diff;
info->clk = 0;
@@ -223,11 +222,11 @@ nva3_clk_info(struct nouveau_clk *clock, int clk, u32 khz,
}
int
-nva3_pll_info(struct nouveau_clk *clock, int clk, u32 pll, u32 khz,
- struct nva3_clk_info *info)
+gt215_pll_info(struct nvkm_clk *clock, int clk, u32 pll, u32 khz,
+ struct gt215_clk_info *info)
{
- struct nouveau_bios *bios = nouveau_bios(clock);
- struct nva3_clk_priv *priv = (void *)clock;
+ struct nvkm_bios *bios = nvkm_bios(clock);
+ struct gt215_clk_priv *priv = (void *)clock;
struct nvbios_pll limits;
int P, N, M, diff;
int ret;
@@ -236,7 +235,7 @@ nva3_pll_info(struct nouveau_clk *clock, int clk, u32 pll, u32 khz,
/* If we can get a within [-2, 3) MHz of a divider, we'll disable the
* PLL and use the divider instead. */
- ret = nva3_clk_info(clock, clk, khz, info);
+ ret = gt215_clk_info(clock, clk, khz, info);
diff = khz - ret;
if (!pll || (diff >= -2000 && diff < 3000)) {
goto out;
@@ -247,38 +246,37 @@ nva3_pll_info(struct nouveau_clk *clock, int clk, u32 pll, u32 khz,
if (ret)
return ret;
- ret = nva3_clk_info(clock, clk - 0x10, limits.refclk, info);
+ ret = gt215_clk_info(clock, clk - 0x10, limits.refclk, info);
if (ret != limits.refclk)
return -EINVAL;
- ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
+ ret = gt215_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
if (ret >= 0) {
info->pll = (P << 16) | (N << 8) | M;
}
out:
info->fb_delay = max(((khz + 7566) / 15133), (u32) 18);
-
return ret ? ret : -ERANGE;
}
static int
-calc_clk(struct nva3_clk_priv *priv, struct nouveau_cstate *cstate,
+calc_clk(struct gt215_clk_priv *priv, struct nvkm_cstate *cstate,
int clk, u32 pll, int idx)
{
- int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx],
- &priv->eng[idx]);
+ int ret = gt215_pll_info(&priv->base, clk, pll, cstate->domain[idx],
+ &priv->eng[idx]);
if (ret >= 0)
return 0;
return ret;
}
static int
-calc_host(struct nva3_clk_priv *priv, struct nouveau_cstate *cstate)
+calc_host(struct gt215_clk_priv *priv, struct nvkm_cstate *cstate)
{
int ret = 0;
u32 kHz = cstate->domain[nv_clk_src_host];
- struct nva3_clk_info *info = &priv->eng[nv_clk_src_host];
+ struct gt215_clk_info *info = &priv->eng[nv_clk_src_host];
if (kHz == 277000) {
info->clk = 0;
@@ -288,16 +286,17 @@ calc_host(struct nva3_clk_priv *priv, struct nouveau_cstate *cstate)
info->host_out = NVA3_HOST_CLK;
- ret = nva3_clk_info(&priv->base, 0x1d, kHz, info);
+ ret = gt215_clk_info(&priv->base, 0x1d, kHz, info);
if (ret >= 0)
return 0;
+
return ret;
}
int
-nva3_clk_pre(struct nouveau_clk *clk, unsigned long *flags)
+gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags)
{
- struct nouveau_fifo *pfifo = nouveau_fifo(clk);
+ struct nvkm_fifo *pfifo = nvkm_fifo(clk);
/* halt and idle execution engines */
nv_mask(clk, 0x020060, 0x00070000, 0x00000000);
@@ -318,9 +317,9 @@ nva3_clk_pre(struct nouveau_clk *clk, unsigned long *flags)
}
void
-nva3_clk_post(struct nouveau_clk *clk, unsigned long *flags)
+gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags)
{
- struct nouveau_fifo *pfifo = nouveau_fifo(clk);
+ struct nvkm_fifo *pfifo = nvkm_fifo(clk);
if (pfifo && flags)
pfifo->start(pfifo, flags);
@@ -330,16 +329,16 @@ nva3_clk_post(struct nouveau_clk *clk, unsigned long *flags)
}
static void
-disable_clk_src(struct nva3_clk_priv *priv, u32 src)
+disable_clk_src(struct gt215_clk_priv *priv, u32 src)
{
nv_mask(priv, src, 0x00000100, 0x00000000);
nv_mask(priv, src, 0x00000001, 0x00000000);
}
static void
-prog_pll(struct nva3_clk_priv *priv, int clk, u32 pll, int idx)
+prog_pll(struct gt215_clk_priv *priv, int clk, u32 pll, int idx)
{
- struct nva3_clk_info *info = &priv->eng[idx];
+ struct gt215_clk_info *info = &priv->eng[idx];
const u32 src0 = 0x004120 + (clk * 4);
const u32 src1 = 0x004160 + (clk * 4);
const u32 ctrl = pll + 0;
@@ -377,16 +376,16 @@ prog_pll(struct nva3_clk_priv *priv, int clk, u32 pll, int idx)
}
static void
-prog_clk(struct nva3_clk_priv *priv, int clk, int idx)
+prog_clk(struct gt215_clk_priv *priv, int clk, int idx)
{
- struct nva3_clk_info *info = &priv->eng[idx];
+ struct gt215_clk_info *info = &priv->eng[idx];
nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
}
static void
-prog_host(struct nva3_clk_priv *priv)
+prog_host(struct gt215_clk_priv *priv)
{
- struct nva3_clk_info *info = &priv->eng[nv_clk_src_host];
+ struct gt215_clk_info *info = &priv->eng[nv_clk_src_host];
u32 hsrc = (nv_rd32(priv, 0xc040));
switch (info->host_out) {
@@ -411,9 +410,9 @@ prog_host(struct nva3_clk_priv *priv)
}
static void
-prog_core(struct nva3_clk_priv *priv, int idx)
+prog_core(struct gt215_clk_priv *priv, int idx)
{
- struct nva3_clk_info *info = &priv->eng[idx];
+ struct gt215_clk_info *info = &priv->eng[idx];
u32 fb_delay = nv_rd32(priv, 0x10002c);
if (fb_delay < info->fb_delay)
@@ -426,10 +425,10 @@ prog_core(struct nva3_clk_priv *priv, int idx)
}
static int
-nva3_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
+gt215_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
- struct nva3_clk_priv *priv = (void *)clk;
- struct nva3_clk_info *core = &priv->eng[nv_clk_src_core];
+ struct gt215_clk_priv *priv = (void *)clk;
+ struct gt215_clk_info *core = &priv->eng[nv_clk_src_core];
int ret;
if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
@@ -442,9 +441,9 @@ nva3_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
/* XXX: Should be reading the highest bit in the VBIOS clock to decide
* whether to use a PLL or not... but using a PLL defeats the purpose */
if (core->pll) {
- ret = nva3_clk_info(clk, 0x10,
- cstate->domain[nv_clk_src_core_intm],
- &priv->eng[nv_clk_src_core_intm]);
+ ret = gt215_clk_info(clk, 0x10,
+ cstate->domain[nv_clk_src_core_intm],
+ &priv->eng[nv_clk_src_core_intm]);
if (ret < 0)
return ret;
}
@@ -453,15 +452,15 @@ nva3_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
}
static int
-nva3_clk_prog(struct nouveau_clk *clk)
+gt215_clk_prog(struct nvkm_clk *clk)
{
- struct nva3_clk_priv *priv = (void *)clk;
- struct nva3_clk_info *core = &priv->eng[nv_clk_src_core];
+ struct gt215_clk_priv *priv = (void *)clk;
+ struct gt215_clk_info *core = &priv->eng[nv_clk_src_core];
int ret = 0;
unsigned long flags;
unsigned long *f = &flags;
- ret = nva3_clk_pre(clk, f);
+ ret = gt215_clk_pre(clk, f);
if (ret)
goto out;
@@ -478,18 +477,17 @@ out:
if (ret == -EBUSY)
f = NULL;
- nva3_clk_post(clk, f);
-
+ gt215_clk_post(clk, f);
return ret;
}
static void
-nva3_clk_tidy(struct nouveau_clk *clk)
+gt215_clk_tidy(struct nvkm_clk *clk)
{
}
-static struct nouveau_domain
-nva3_domain[] = {
+static struct nvkm_domain
+gt215_domain[] = {
{ nv_clk_src_crystal , 0xff },
{ nv_clk_src_core , 0x00, 0, "core", 1000 },
{ nv_clk_src_shader , 0x01, 0, "shader", 1000 },
@@ -502,33 +500,33 @@ nva3_domain[] = {
};
static int
-nva3_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gt215_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nva3_clk_priv *priv;
+ struct gt215_clk_priv *priv;
int ret;
- ret = nouveau_clk_create(parent, engine, oclass, nva3_domain, NULL, 0,
- true, &priv);
+ ret = nvkm_clk_create(parent, engine, oclass, gt215_domain,
+ NULL, 0, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.read = nva3_clk_read;
- priv->base.calc = nva3_clk_calc;
- priv->base.prog = nva3_clk_prog;
- priv->base.tidy = nva3_clk_tidy;
+ priv->base.read = gt215_clk_read;
+ priv->base.calc = gt215_clk_calc;
+ priv->base.prog = gt215_clk_prog;
+ priv->base.tidy = gt215_clk_tidy;
return 0;
}
-struct nouveau_oclass
-nva3_clk_oclass = {
+struct nvkm_oclass
+gt215_clk_oclass = {
.handle = NV_SUBDEV(CLK, 0xa3),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nva3_clk_ctor,
- .dtor = _nouveau_clk_dtor,
- .init = _nouveau_clk_init,
- .fini = _nouveau_clk_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gt215_clk_ctor,
+ .dtor = _nvkm_clk_dtor,
+ .init = _nvkm_clk_init,
+ .fini = _nvkm_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h
new file mode 100644
index 000000000000..b447d9cd4d37
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h
@@ -0,0 +1,18 @@
+#ifndef __NVKM_CLK_NVA3_H__
+#define __NVKM_CLK_NVA3_H__
+#include <subdev/clk.h>
+
+struct gt215_clk_info {
+ u32 clk;
+ u32 pll;
+ enum {
+ NVA3_HOST_277,
+ NVA3_HOST_CLK,
+ } host_out;
+ u32 fb_delay;
+};
+
+int gt215_pll_info(struct nvkm_clk *, int, u32, u32, struct gt215_clk_info *);
+int gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags);
+void gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags);
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
similarity index 85%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
index d6d2bd190144..d735de2dbd74 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
@@ -21,18 +21,15 @@
*
* Authors: Ben Skeggs
*/
+#include "gt215.h"
+#include "pll.h"
-#include <engine/fifo.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
-#include <subdev/clk.h>
-#include "nva3.h"
-#include "pll.h"
-
-struct nvaa_clk_priv {
- struct nouveau_clk base;
+struct mcp77_clk_priv {
+ struct nvkm_clk base;
enum nv_clk_src csrc, ssrc, vsrc;
u32 cctrl, sctrl;
u32 ccoef, scoef;
@@ -41,13 +38,13 @@ struct nvaa_clk_priv {
};
static u32
-read_div(struct nouveau_clk *clk)
+read_div(struct nvkm_clk *clk)
{
return nv_rd32(clk, 0x004600);
}
static u32
-read_pll(struct nouveau_clk *clk, u32 base)
+read_pll(struct nvkm_clk *clk, u32 base)
{
u32 ctrl = nv_rd32(clk, base + 0);
u32 coef = nv_rd32(clk, base + 4);
@@ -78,9 +75,9 @@ read_pll(struct nouveau_clk *clk, u32 base)
}
static int
-nvaa_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
+mcp77_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
- struct nvaa_clk_priv *priv = (void *)clk;
+ struct mcp77_clk_priv *priv = (void *)clk;
u32 mast = nv_rd32(clk, 0x00c054);
u32 P = 0;
@@ -160,12 +157,12 @@ nvaa_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
}
static u32
-calc_pll(struct nvaa_clk_priv *priv, u32 reg,
+calc_pll(struct mcp77_clk_priv *priv, u32 reg,
u32 clock, int *N, int *M, int *P)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_pll pll;
- struct nouveau_clk *clk = &priv->base;
+ struct nvkm_clk *clk = &priv->base;
int ret;
ret = nvbios_pll_parse(bios, reg, &pll);
@@ -199,9 +196,9 @@ calc_P(u32 src, u32 target, int *div)
}
static int
-nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
+mcp77_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
- struct nvaa_clk_priv *priv = (void *)clk;
+ struct mcp77_clk_priv *priv = (void *)clk;
const int shader = cstate->domain[nv_clk_src_shader];
const int core = cstate->domain[nv_clk_src_core];
const int vdec = cstate->domain[nv_clk_src_vdec];
@@ -216,8 +213,7 @@ nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
/* Calculate clock * 2, so shader clock can use it too */
clock = calc_pll(priv, 0x4028, (core << 1), &N, &M, &P1);
- if (abs(core - out) <=
- abs(core - (clock >> 1))) {
+ if (abs(core - out) <= abs(core - (clock >> 1))) {
priv->csrc = nv_clk_src_hclkm4;
priv->cctrl = divs << 16;
} else {
@@ -242,9 +238,8 @@ nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
priv->ssrc = nv_clk_src_href;
} else {
clock = calc_pll(priv, 0x4020, shader, &N, &M, &P1);
- if (priv->csrc == nv_clk_src_core) {
+ if (priv->csrc == nv_clk_src_core)
out = calc_P((core << 1), shader, &divs);
- }
if (abs(shader - out) <=
abs(shader - clock) &&
@@ -261,8 +256,7 @@ nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
/* vclk */
out = calc_P(core, vdec, &divs);
clock = calc_P(500000, vdec, &P1);
- if(abs(vdec - out) <=
- abs(vdec - clock)) {
+ if(abs(vdec - out) <= abs(vdec - clock)) {
priv->vsrc = nv_clk_src_cclk;
priv->vdiv = divs << 16;
} else {
@@ -297,15 +291,15 @@ nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
}
static int
-nvaa_clk_prog(struct nouveau_clk *clk)
+mcp77_clk_prog(struct nvkm_clk *clk)
{
- struct nvaa_clk_priv *priv = (void *)clk;
+ struct mcp77_clk_priv *priv = (void *)clk;
u32 pllmask = 0, mast;
unsigned long flags;
unsigned long *f = &flags;
int ret = 0;
- ret = nva3_clk_pre(clk, f);
+ ret = gt215_clk_pre(clk, f);
if (ret)
goto out;
@@ -382,18 +376,17 @@ out:
if (ret == -EBUSY)
f = NULL;
- nva3_clk_post(clk, f);
-
+ gt215_clk_post(clk, f);
return ret;
}
static void
-nvaa_clk_tidy(struct nouveau_clk *clk)
+mcp77_clk_tidy(struct nvkm_clk *clk)
{
}
-static struct nouveau_domain
-nvaa_domains[] = {
+static struct nvkm_domain
+mcp77_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
@@ -403,33 +396,33 @@ nvaa_domains[] = {
};
static int
-nvaa_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+mcp77_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvaa_clk_priv *priv;
+ struct mcp77_clk_priv *priv;
int ret;
- ret = nouveau_clk_create(parent, engine, oclass, nvaa_domains, NULL,
- 0, true, &priv);
+ ret = nvkm_clk_create(parent, engine, oclass, mcp77_domains,
+ NULL, 0, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.read = nvaa_clk_read;
- priv->base.calc = nvaa_clk_calc;
- priv->base.prog = nvaa_clk_prog;
- priv->base.tidy = nvaa_clk_tidy;
+ priv->base.read = mcp77_clk_read;
+ priv->base.calc = mcp77_clk_calc;
+ priv->base.prog = mcp77_clk_prog;
+ priv->base.tidy = mcp77_clk_tidy;
return 0;
}
-struct nouveau_oclass *
-nvaa_clk_oclass = &(struct nouveau_oclass) {
+struct nvkm_oclass *
+mcp77_clk_oclass = &(struct nvkm_oclass) {
.handle = NV_SUBDEV(CLK, 0xaa),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvaa_clk_ctor,
- .dtor = _nouveau_clk_dtor,
- .init = _nouveau_clk_init,
- .fini = _nouveau_clk_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = mcp77_clk_ctor,
+ .dtor = _nvkm_clk_dtor,
+ .init = _nvkm_clk_init,
+ .fini = _nvkm_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
index de68f2f53204..63dbbb575228 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
@@ -21,21 +21,20 @@
*
* Authors: Ben Skeggs
*/
+#include <subdev/clk.h>
+#include "pll.h"
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
-#include <subdev/clk.h>
#include <subdev/devinit/nv04.h>
-#include "pll.h"
-
struct nv04_clk_priv {
- struct nouveau_clk base;
+ struct nvkm_clk base;
};
int
-nv04_clk_pll_calc(struct nouveau_clk *clock, struct nvbios_pll *info,
- int clk, struct nouveau_pll_vals *pv)
+nv04_clk_pll_calc(struct nvkm_clk *clock, struct nvbios_pll *info,
+ int clk, struct nvkm_pll_vals *pv)
{
int N1, M1, N2, M2, P;
int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P);
@@ -51,11 +50,10 @@ nv04_clk_pll_calc(struct nouveau_clk *clock, struct nvbios_pll *info,
}
int
-nv04_clk_pll_prog(struct nouveau_clk *clk, u32 reg1,
- struct nouveau_pll_vals *pv)
+nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv)
{
- struct nouveau_devinit *devinit = nouveau_devinit(clk);
- int cv = nouveau_bios(clk)->version.chip;
+ struct nvkm_devinit *devinit = nvkm_devinit(clk);
+ int cv = nvkm_bios(clk)->version.chip;
if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
cv >= 0x40) {
@@ -69,21 +67,21 @@ nv04_clk_pll_prog(struct nouveau_clk *clk, u32 reg1,
return 0;
}
-static struct nouveau_domain
+static struct nvkm_domain
nv04_domain[] = {
{ nv_clk_src_max }
};
static int
-nv04_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_clk_priv *priv;
int ret;
- ret = nouveau_clk_create(parent, engine, oclass, nv04_domain, NULL, 0,
- false, &priv);
+ ret = nvkm_clk_create(parent, engine, oclass, nv04_domain,
+ NULL, 0, false, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -93,13 +91,13 @@ nv04_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv04_clk_oclass = {
.handle = NV_SUBDEV(CLK, 0x04),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_clk_ctor,
- .dtor = _nouveau_clk_dtor,
- .init = _nouveau_clk_init,
- .fini = _nouveau_clk_fini,
+ .dtor = _nvkm_clk_dtor,
+ .init = _nvkm_clk_init,
+ .fini = _nvkm_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
index 460ca4ab603b..ed838130c89d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
@@ -21,22 +21,22 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/clk.h>
+#include "pll.h"
+
+#include <core/device.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
-#include "pll.h"
-
struct nv40_clk_priv {
- struct nouveau_clk base;
+ struct nvkm_clk base;
u32 ctrl;
u32 npll_ctrl;
u32 npll_coef;
u32 spll;
};
-static struct nouveau_domain
+static struct nvkm_domain
nv40_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -102,7 +102,7 @@ read_clk(struct nv40_clk_priv *priv, u32 src)
}
static int
-nv40_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
+nv40_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
struct nv40_clk_priv *priv = (void *)clk;
u32 mast = nv_rd32(priv, 0x00c040);
@@ -128,9 +128,9 @@ nv40_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
static int
nv40_clk_calc_pll(struct nv40_clk_priv *priv, u32 reg, u32 clk,
- int *N1, int *M1, int *N2, int *M2, int *log2P)
+ int *N1, int *M1, int *N2, int *M2, int *log2P)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_pll pll;
int ret;
@@ -144,11 +144,12 @@ nv40_clk_calc_pll(struct nv40_clk_priv *priv, u32 reg, u32 clk,
ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P);
if (ret == 0)
return -ERANGE;
+
return ret;
}
static int
-nv40_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
+nv40_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
struct nv40_clk_priv *priv = (void *)clk;
int gclk = cstate->domain[nv_clk_src_core];
@@ -158,7 +159,7 @@ nv40_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
/* core/geometric clock */
ret = nv40_clk_calc_pll(priv, 0x004000, gclk,
- &N1, &M1, &N2, &M2, &log2P);
+ &N1, &M1, &N2, &M2, &log2P);
if (ret < 0)
return ret;
@@ -173,7 +174,7 @@ nv40_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
/* use the second pll for shader/rop clock, if it differs from core */
if (sclk && sclk != gclk) {
ret = nv40_clk_calc_pll(priv, 0x004008, sclk,
- &N1, &M1, NULL, NULL, &log2P);
+ &N1, &M1, NULL, NULL, &log2P);
if (ret < 0)
return ret;
@@ -188,7 +189,7 @@ nv40_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
}
static int
-nv40_clk_prog(struct nouveau_clk *clk)
+nv40_clk_prog(struct nvkm_clk *clk)
{
struct nv40_clk_priv *priv = (void *)clk;
nv_mask(priv, 0x00c040, 0x00000333, 0x00000000);
@@ -201,20 +202,20 @@ nv40_clk_prog(struct nouveau_clk *clk)
}
static void
-nv40_clk_tidy(struct nouveau_clk *clk)
+nv40_clk_tidy(struct nvkm_clk *clk)
{
}
static int
-nv40_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv40_clk_priv *priv;
int ret;
- ret = nouveau_clk_create(parent, engine, oclass, nv40_domain, NULL, 0,
- true, &priv);
+ ret = nvkm_clk_create(parent, engine, oclass, nv40_domain,
+ NULL, 0, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -228,13 +229,13 @@ nv40_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv40_clk_oclass = {
.handle = NV_SUBDEV(CLK, 0x40),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_clk_ctor,
- .dtor = _nouveau_clk_dtor,
- .init = _nouveau_clk_init,
- .fini = _nouveau_clk_fini,
+ .dtor = _nvkm_clk_dtor,
+ .init = _nvkm_clk_init,
+ .fini = _nvkm_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
index 3c462a24922c..9b4ffd6347ce 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
@@ -21,14 +21,14 @@
*
* Authors: Ben Skeggs
*/
-
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-
#include "nv50.h"
#include "pll.h"
#include "seq.h"
+#include <core/device.h>
+#include <subdev/bios.h>
+#include <subdev/bios/pll.h>
+
static u32
read_div(struct nv50_clk_priv *priv)
{
@@ -51,7 +51,7 @@ read_div(struct nv50_clk_priv *priv)
static u32
read_pll_src(struct nv50_clk_priv *priv, u32 base)
{
- struct nouveau_clk *clk = &priv->base;
+ struct nvkm_clk *clk = &priv->base;
u32 coef, ref = clk->read(clk, nv_clk_src_crystal);
u32 rsel = nv_rd32(priv, 0x00e18c);
int P, N, M, id;
@@ -116,13 +116,14 @@ read_pll_src(struct nv50_clk_priv *priv, u32 base)
if (M)
return (ref * N / M) >> P;
+
return 0;
}
static u32
read_pll_ref(struct nv50_clk_priv *priv, u32 base)
{
- struct nouveau_clk *clk = &priv->base;
+ struct nvkm_clk *clk = &priv->base;
u32 src, mast = nv_rd32(priv, 0x00c040);
switch (base) {
@@ -147,13 +148,14 @@ read_pll_ref(struct nv50_clk_priv *priv, u32 base)
if (src)
return clk->read(clk, nv_clk_src_href);
+
return read_pll_src(priv, base);
}
static u32
read_pll(struct nv50_clk_priv *priv, u32 base)
{
- struct nouveau_clk *clk = &priv->base;
+ struct nvkm_clk *clk = &priv->base;
u32 mast = nv_rd32(priv, 0x00c040);
u32 ctrl = nv_rd32(priv, base + 0);
u32 coef = nv_rd32(priv, base + 4);
@@ -162,7 +164,7 @@ read_pll(struct nv50_clk_priv *priv, u32 base)
int N1, N2, M1, M2;
if (base == 0x004028 && (mast & 0x00100000)) {
- /* wtf, appears to only disable post-divider on nva0 */
+ /* wtf, appears to only disable post-divider on gt200 */
if (nv_device(priv)->chipset != 0xa0)
return clk->read(clk, nv_clk_src_dom6);
}
@@ -185,7 +187,7 @@ read_pll(struct nv50_clk_priv *priv, u32 base)
}
static int
-nv50_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
+nv50_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
struct nv50_clk_priv *priv = (void *)clk;
u32 mast = nv_rd32(priv, 0x00c040);
@@ -318,7 +320,7 @@ nv50_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
static u32
calc_pll(struct nv50_clk_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_pll pll;
int ret;
@@ -359,7 +361,7 @@ clk_same(u32 a, u32 b)
}
static int
-nv50_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
+nv50_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
struct nv50_clk_priv *priv = (void *)clk;
struct nv50_clk_hwsq *hwsq = &priv->hwsq;
@@ -484,30 +486,30 @@ nv50_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
}
static int
-nv50_clk_prog(struct nouveau_clk *clk)
+nv50_clk_prog(struct nvkm_clk *clk)
{
struct nv50_clk_priv *priv = (void *)clk;
return clk_exec(&priv->hwsq, true);
}
static void
-nv50_clk_tidy(struct nouveau_clk *clk)
+nv50_clk_tidy(struct nvkm_clk *clk)
{
struct nv50_clk_priv *priv = (void *)clk;
clk_exec(&priv->hwsq, false);
}
int
-nv50_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_clk_oclass *pclass = (void *)oclass;
struct nv50_clk_priv *priv;
int ret;
- ret = nouveau_clk_create(parent, engine, oclass, pclass->domains,
- NULL, 0, false, &priv);
+ ret = nvkm_clk_create(parent, engine, oclass, pclass->domains,
+ NULL, 0, false, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -536,7 +538,7 @@ nv50_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-static struct nouveau_domain
+static struct nvkm_domain
nv50_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -546,14 +548,14 @@ nv50_domains[] = {
{ nv_clk_src_max }
};
-struct nouveau_oclass *
+struct nvkm_oclass *
nv50_clk_oclass = &(struct nv50_clk_oclass) {
.base.handle = NV_SUBDEV(CLK, 0x50),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_clk_ctor,
- .dtor = _nouveau_clk_dtor,
- .init = _nouveau_clk_init,
- .fini = _nouveau_clk_fini,
+ .dtor = _nvkm_clk_dtor,
+ .init = _nvkm_clk_init,
+ .fini = _nvkm_clk_fini,
},
.domains = nv50_domains,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
index ae6421fd28f4..0ead76a32f10 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
@@ -1,7 +1,5 @@
#ifndef __NVKM_CLK_NV50_H__
#define __NVKM_CLK_NV50_H__
-
-#include <subdev/bus.h>
#include <subdev/bus/hwsq.h>
#include <subdev/clk.h>
@@ -15,17 +13,16 @@ struct nv50_clk_hwsq {
};
struct nv50_clk_priv {
- struct nouveau_clk base;
+ struct nvkm_clk base;
struct nv50_clk_hwsq hwsq;
};
-int nv50_clk_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
+int nv50_clk_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
struct nv50_clk_oclass {
- struct nouveau_oclass base;
- struct nouveau_domain *domains;
+ struct nvkm_oclass base;
+ struct nvkm_domain *domains;
};
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h
deleted file mode 100644
index ce0fc83345e3..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __NVKM_CLK_NVA3_H__
-#define __NVKM_CLK_NVA3_H__
-
-#include <subdev/clk.h>
-
-struct nva3_clk_info {
- u32 clk;
- u32 pll;
- enum {
- NVA3_HOST_277,
- NVA3_HOST_CLK,
- } host_out;
- u32 fb_delay;
-};
-
-int nva3_pll_info(struct nouveau_clk *, int, u32, u32,
- struct nva3_clk_info *);
-int nva3_clk_pre(struct nouveau_clk *clk, unsigned long *flags);
-void nva3_clk_post(struct nouveau_clk *clk, unsigned long *flags);
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h
index 445b14c33a98..44020a30dee8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h
@@ -1,9 +1,11 @@
-#ifndef __NOUVEAU_PLL_H__
-#define __NOUVEAU_PLL_H__
+#ifndef __NVKM_PLL_H__
+#define __NVKM_PLL_H__
+#include <core/os.h>
+struct nvkm_subdev;
+struct nvbios_pll;
-int nv04_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq,
+int nv04_pll_calc(struct nvkm_subdev *, struct nvbios_pll *, u32 freq,
int *N1, int *M1, int *N2, int *M2, int *P);
-int nva3_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq,
+int gt215_pll_calc(struct nvkm_subdev *, struct nvbios_pll *, u32 freq,
int *N, int *fN, int *M, int *P);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.c
similarity index 94%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.c
index bc17fcc83bfe..783a3e78d632 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.c
@@ -21,16 +21,14 @@
*
* Authors: Ben Skeggs
*/
+#include "pll.h"
-#include <subdev/clk.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
-#include "pll.h"
-
int
-nva3_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info,
- u32 freq, int *pN, int *pfN, int *pM, int *P)
+gt215_pll_calc(struct nvkm_subdev *subdev, struct nvbios_pll *info,
+ u32 freq, int *pN, int *pfN, int *pM, int *P)
{
u32 best_err = ~0, err;
int M, lM, hM, N, fN;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
index b47d543ab2e3..f2292895a1a8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
@@ -20,14 +20,13 @@
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
+#include "pll.h"
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
-#include "pll.h"
-
static int
-getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
+getMNP_single(struct nvkm_subdev *subdev, struct nvbios_pll *info, int clk,
int *pN, int *pM, int *pP)
{
/* Find M, N and P for a single stage PLL
@@ -38,7 +37,7 @@ getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
* "clk" parameter in kHz
* returns calculated clock
*/
- struct nouveau_bios *bios = nouveau_bios(subdev);
+ struct nvkm_bios *bios = nvkm_bios(subdev);
int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq;
int minM = info->vco1.min_m, maxM = info->vco1.max_m;
int minN = info->vco1.min_n, maxN = info->vco1.max_n;
@@ -126,7 +125,7 @@ getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
}
static int
-getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
+getMNP_double(struct nvkm_subdev *subdev, struct nvbios_pll *info, int clk,
int *pN1, int *pM1, int *pN2, int *pM2, int *pP)
{
/* Find M, N and P for a two stage PLL
@@ -137,7 +136,7 @@ getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
* "clk" parameter in kHz
* returns calculated clock
*/
- int chip_version = nouveau_bios(subdev)->version.chip;
+ int chip_version = nvkm_bios(subdev)->version.chip;
int minvco1 = info->vco1.min_freq, maxvco1 = info->vco1.max_freq;
int minvco2 = info->vco2.min_freq, maxvco2 = info->vco2.max_freq;
int minU1 = info->vco1.min_inputfreq, minU2 = info->vco2.min_inputfreq;
@@ -225,7 +224,7 @@ getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
}
int
-nv04_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, u32 freq,
+nv04_pll_calc(struct nvkm_subdev *subdev, struct nvbios_pll *info, u32 freq,
int *N1, int *M1, int *N2, int *M2, int *P)
{
int ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h
index fb33f06ebd59..d717e8b8f679 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h
@@ -1,7 +1,5 @@
#ifndef __NVKM_CLK_SEQ_H__
#define __NVKM_CLK_SEQ_H__
-
-#include <subdev/bus.h>
#include <subdev/bus/hwsq.h>
#define clk_init(s,p) hwsq_init(&(s)->base, (p))
@@ -13,5 +11,4 @@
#define clk_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d))
#define clk_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d))
#define clk_nsec(s,n) hwsq_nsec(&(s)->base, (n))
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
index 50e8dee513cc..f3cc7a19f931 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
@@ -30,7 +30,7 @@
#include <subdev/bios/M0205.h>
#include <subdev/bios/timing.h>
-#include <subdev/clk/nva3.h>
+#include <subdev/clk/gt215.h>
#include <subdev/clk/pll.h>
#include <subdev/gpio.h>
From a8c4362bad2218484870678f5d0c221968883f13 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 14:48:16 +1000
Subject: [PATCH 56/86] drm/nouveau/devinit: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 1 +
.../drm/nouveau/include/nvkm/subdev/devinit.h | 49 +++++++-------
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 26 ++++----
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +++---
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 ++--
.../drm/nouveau/nvkm/subdev/devinit/Kbuild | 10 +--
.../drm/nouveau/nvkm/subdev/devinit/base.c | 47 +++++++-------
.../drm/nouveau/nvkm/subdev/devinit/fbmem.h | 4 +-
.../nvkm/subdev/devinit/{nv84.c => g84.c} | 18 +++---
.../nvkm/subdev/devinit/{nv98.c => g98.c} | 18 +++---
.../nvkm/subdev/devinit/{nvc0.c => gf100.c} | 39 ++++++-----
.../drm/nouveau/nvkm/subdev/devinit/gm107.c | 18 +++---
.../drm/nouveau/nvkm/subdev/devinit/gm204.c | 27 ++++----
.../nvkm/subdev/devinit/{nva3.c => gt215.c} | 36 ++++++-----
.../nvkm/subdev/devinit/{nvaf.c => mcp89.c} | 20 +++---
.../drm/nouveau/nvkm/subdev/devinit/nv04.c | 64 ++++++++++---------
.../drm/nouveau/nvkm/subdev/devinit/nv04.h | 25 ++++----
.../drm/nouveau/nvkm/subdev/devinit/nv05.c | 16 ++---
.../drm/nouveau/nvkm/subdev/devinit/nv10.c | 16 ++---
.../drm/nouveau/nvkm/subdev/devinit/nv1a.c | 10 +--
.../drm/nouveau/nvkm/subdev/devinit/nv20.c | 14 ++--
.../drm/nouveau/nvkm/subdev/devinit/nv50.c | 39 +++++------
.../drm/nouveau/nvkm/subdev/devinit/nv50.h | 20 +++---
.../drm/nouveau/nvkm/subdev/devinit/priv.h | 52 +++++++--------
24 files changed, 304 insertions(+), 297 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/subdev/devinit/{nv84.c => g84.c} (86%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/devinit/{nv98.c => g98.c} (85%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/devinit/{nvc0.c => gf100.c} (75%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/devinit/{nva3.c => gt215.c} (82%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/devinit/{nvaf.c => mcp89.c} (84%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 70ad99dd01e6..2b0fe0e7da8c 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -219,5 +219,6 @@
#define nva3_clk_post gt215_clk_post
#define nva3_clk_info gt215_clk_info
#define nva3_pll_info gt215_pll_info
+#define nouveau_ibus nvkm_ibus
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h
index b627d5329543..d1bbe0d62b35 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h
@@ -1,35 +1,32 @@
-#ifndef __NOUVEAU_DEVINIT_H__
-#define __NOUVEAU_DEVINIT_H__
-
+#ifndef __NVKM_DEVINIT_H__
+#define __NVKM_DEVINIT_H__
#include <core/subdev.h>
-#include <core/device.h>
-struct nouveau_devinit {
- struct nouveau_subdev base;
+struct nvkm_devinit {
+ struct nvkm_subdev base;
bool post;
- void (*meminit)(struct nouveau_devinit *);
- int (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq);
- u32 (*mmio)(struct nouveau_devinit *, u32 addr);
+ void (*meminit)(struct nvkm_devinit *);
+ int (*pll_set)(struct nvkm_devinit *, u32 type, u32 freq);
+ u32 (*mmio)(struct nvkm_devinit *, u32 addr);
};
-static inline struct nouveau_devinit *
-nouveau_devinit(void *obj)
+static inline struct nvkm_devinit *
+nvkm_devinit(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_DEVINIT);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_DEVINIT);
}
-extern struct nouveau_oclass *nv04_devinit_oclass;
-extern struct nouveau_oclass *nv05_devinit_oclass;
-extern struct nouveau_oclass *nv10_devinit_oclass;
-extern struct nouveau_oclass *nv1a_devinit_oclass;
-extern struct nouveau_oclass *nv20_devinit_oclass;
-extern struct nouveau_oclass *nv50_devinit_oclass;
-extern struct nouveau_oclass *nv84_devinit_oclass;
-extern struct nouveau_oclass *nv98_devinit_oclass;
-extern struct nouveau_oclass *nva3_devinit_oclass;
-extern struct nouveau_oclass *nvaf_devinit_oclass;
-extern struct nouveau_oclass *nvc0_devinit_oclass;
-extern struct nouveau_oclass *gm107_devinit_oclass;
-extern struct nouveau_oclass *gm204_devinit_oclass;
-
+extern struct nvkm_oclass *nv04_devinit_oclass;
+extern struct nvkm_oclass *nv05_devinit_oclass;
+extern struct nvkm_oclass *nv10_devinit_oclass;
+extern struct nvkm_oclass *nv1a_devinit_oclass;
+extern struct nvkm_oclass *nv20_devinit_oclass;
+extern struct nvkm_oclass *nv50_devinit_oclass;
+extern struct nvkm_oclass *g84_devinit_oclass;
+extern struct nvkm_oclass *g98_devinit_oclass;
+extern struct nvkm_oclass *gt215_devinit_oclass;
+extern struct nvkm_oclass *mcp89_devinit_oclass;
+extern struct nvkm_oclass *gf100_devinit_oclass;
+extern struct nvkm_oclass *gm107_devinit_oclass;
+extern struct nvkm_oclass *gm204_devinit_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 9df93c5b7489..ead391480479 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -96,7 +96,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -125,7 +125,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -154,7 +154,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -183,7 +183,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -212,7 +212,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -241,7 +241,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -270,7 +270,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -299,7 +299,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -328,7 +328,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -357,7 +357,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -388,7 +388,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -418,7 +418,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -448,7 +448,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 8d0304f5de73..56843b0cdfb0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -68,7 +68,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -101,7 +101,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -134,7 +134,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -166,7 +166,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -199,7 +199,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -231,7 +231,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -263,7 +263,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -296,7 +296,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -328,7 +328,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 9f0efb1d5349..2abd532e2b09 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -68,7 +68,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -102,7 +102,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -136,7 +136,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -192,7 +192,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -226,7 +226,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -260,7 +260,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -293,7 +293,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
+ device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild
index 4321e285c51c..793e73d16dac 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild
@@ -5,10 +5,10 @@ nvkm-y += nvkm/subdev/devinit/nv10.o
nvkm-y += nvkm/subdev/devinit/nv1a.o
nvkm-y += nvkm/subdev/devinit/nv20.o
nvkm-y += nvkm/subdev/devinit/nv50.o
-nvkm-y += nvkm/subdev/devinit/nv84.o
-nvkm-y += nvkm/subdev/devinit/nv98.o
-nvkm-y += nvkm/subdev/devinit/nva3.o
-nvkm-y += nvkm/subdev/devinit/nvaf.o
-nvkm-y += nvkm/subdev/devinit/nvc0.o
+nvkm-y += nvkm/subdev/devinit/g84.o
+nvkm-y += nvkm/subdev/devinit/g98.o
+nvkm-y += nvkm/subdev/devinit/gt215.o
+nvkm-y += nvkm/subdev/devinit/mcp89.o
+nvkm-y += nvkm/subdev/devinit/gf100.o
nvkm-y += nvkm/subdev/devinit/gm107.o
nvkm-y += nvkm/subdev/devinit/gm204.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c
index 0e45cee82463..b0d7c5f40db1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c
@@ -21,17 +21,16 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/option.h>
-
-#include <subdev/vga.h>
-
#include "priv.h"
+#include <core/device.h>
+#include <core/option.h>
+#include <subdev/vga.h>
+
int
-_nouveau_devinit_fini(struct nouveau_object *object, bool suspend)
+_nvkm_devinit_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_devinit *devinit = (void *)object;
+ struct nvkm_devinit *devinit = (void *)object;
/* force full reinit on resume */
if (suspend)
@@ -40,17 +39,17 @@ _nouveau_devinit_fini(struct nouveau_object *object, bool suspend)
/* unlock the extended vga crtc regs */
nv_lockvgac(devinit, false);
- return nouveau_subdev_fini(&devinit->base, suspend);
+ return nvkm_subdev_fini(&devinit->base, suspend);
}
int
-_nouveau_devinit_init(struct nouveau_object *object)
+_nvkm_devinit_init(struct nvkm_object *object)
{
- struct nouveau_devinit_impl *impl = (void *)object->oclass;
- struct nouveau_devinit *devinit = (void *)object;
+ struct nvkm_devinit_impl *impl = (void *)object->oclass;
+ struct nvkm_devinit *devinit = (void *)object;
int ret;
- ret = nouveau_subdev_init(&devinit->base);
+ ret = nvkm_subdev_init(&devinit->base);
if (ret)
return ret;
@@ -64,34 +63,32 @@ _nouveau_devinit_init(struct nouveau_object *object)
}
void
-_nouveau_devinit_dtor(struct nouveau_object *object)
+_nvkm_devinit_dtor(struct nvkm_object *object)
{
- struct nouveau_devinit *devinit = (void *)object;
+ struct nvkm_devinit *devinit = (void *)object;
/* lock crtc regs */
nv_lockvgac(devinit, true);
- nouveau_subdev_destroy(&devinit->base);
+ nvkm_subdev_destroy(&devinit->base);
}
int
-nouveau_devinit_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass,
- int size, void **pobject)
+nvkm_devinit_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int size, void **pobject)
{
- struct nouveau_devinit_impl *impl = (void *)oclass;
- struct nouveau_device *device = nv_device(parent);
- struct nouveau_devinit *devinit;
+ struct nvkm_devinit_impl *impl = (void *)oclass;
+ struct nvkm_device *device = nv_device(parent);
+ struct nvkm_devinit *devinit;
int ret;
- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "DEVINIT",
- "init", size, pobject);
+ ret = nvkm_subdev_create_(parent, engine, oclass, 0, "DEVINIT",
+ "init", size, pobject);
devinit = *pobject;
if (ret)
return ret;
- devinit->post = nouveau_boolopt(device->cfgopt, "NvForcePost", false);
+ devinit->post = nvkm_boolopt(device->cfgopt, "NvForcePost", false);
devinit->meminit = impl->meminit;
devinit->pll_set = impl->pll_set;
devinit->mmio = impl->mmio;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h
index 6103484fea72..36684c3f9e9c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h
@@ -23,9 +23,7 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include <core/device.h>
-
#include <subdev/fb/regsnv04.h>
#define NV04_PFB_DEBUG_0 0x00100080
@@ -48,7 +46,7 @@
# define NV10_PFB_REFCTRL_VALID_1 (1 << 31)
static inline struct io_mapping *
-fbmem_init(struct nouveau_device *dev)
+fbmem_init(struct nvkm_device *dev)
{
return io_mapping_create_wc(nv_device_resource_start(dev, 1),
nv_device_resource_len(dev, 1));
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
similarity index 86%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
index c4f4c158dc1b..ca776ce75f4f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
@@ -21,11 +21,13 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
+#include <subdev/bios.h>
+#include <subdev/bios/init.h>
+
static u64
-nv84_devinit_disable(struct nouveau_devinit *devinit)
+g84_devinit_disable(struct nvkm_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r001540 = nv_rd32(priv, 0x001540);
@@ -49,16 +51,16 @@ nv84_devinit_disable(struct nouveau_devinit *devinit)
return disable;
}
-struct nouveau_oclass *
-nv84_devinit_oclass = &(struct nouveau_devinit_impl) {
+struct nvkm_oclass *
+g84_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x84),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_devinit_ctor,
- .dtor = _nouveau_devinit_dtor,
+ .dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
- .fini = _nouveau_devinit_fini,
+ .fini = _nvkm_devinit_fini,
},
.pll_set = nv50_devinit_pll_set,
- .disable = nv84_devinit_disable,
+ .disable = g84_devinit_disable,
.post = nvbios_init,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
similarity index 85%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
index 3a629e02622f..d29bacee65ee 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
@@ -21,11 +21,13 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
+#include <subdev/bios.h>
+#include <subdev/bios/init.h>
+
static u64
-nv98_devinit_disable(struct nouveau_devinit *devinit)
+g98_devinit_disable(struct nvkm_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r001540 = nv_rd32(priv, 0x001540);
@@ -48,16 +50,16 @@ nv98_devinit_disable(struct nouveau_devinit *devinit)
return disable;
}
-struct nouveau_oclass *
-nv98_devinit_oclass = &(struct nouveau_devinit_impl) {
+struct nvkm_oclass *
+g98_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x98),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_devinit_ctor,
- .dtor = _nouveau_devinit_dtor,
+ .dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
- .fini = _nouveau_devinit_fini,
+ .fini = _nvkm_devinit_fini,
},
.pll_set = nv50_devinit_pll_set,
- .disable = nv98_devinit_disable,
+ .disable = g98_devinit_disable,
.post = nvbios_init,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
similarity index 75%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
index 672aaf347efe..e8778c67578e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
@@ -21,14 +21,18 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
+#include <subdev/bios.h>
+#include <subdev/bios/init.h>
+#include <subdev/bios/pll.h>
+#include <subdev/clk/pll.h>
+
int
-nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
+gf100_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
{
struct nv50_devinit_priv *priv = (void *)devinit;
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_pll info;
int N, fN, M, P;
int ret;
@@ -37,7 +41,7 @@ nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
if (ret)
return ret;
- ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P);
+ ret = gt215_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P);
if (ret < 0)
return ret;
@@ -60,7 +64,7 @@ nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
}
static u64
-nvc0_devinit_disable(struct nouveau_devinit *devinit)
+gf100_devinit_disable(struct nvkm_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r022500 = nv_rd32(priv, 0x022500);
@@ -87,33 +91,34 @@ nvc0_devinit_disable(struct nouveau_devinit *devinit)
}
static int
-nvc0_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_devinit_priv *priv;
int ret;
- ret = nouveau_devinit_create(parent, engine, oclass, &priv);
+ ret = nvkm_devinit_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
if (nv_rd32(priv, 0x022500) & 0x00000001)
priv->base.post = true;
+
return 0;
}
-struct nouveau_oclass *
-nvc0_devinit_oclass = &(struct nouveau_devinit_impl) {
+struct nvkm_oclass *
+gf100_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_devinit_ctor,
- .dtor = _nouveau_devinit_dtor,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_devinit_ctor,
+ .dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
- .fini = _nouveau_devinit_fini,
+ .fini = _nvkm_devinit_fini,
},
- .pll_set = nvc0_devinit_pll_set,
- .disable = nvc0_devinit_disable,
+ .pll_set = gf100_devinit_pll_set,
+ .disable = gf100_devinit_disable,
.post = nvbios_init,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
index 04c04efcc8c4..b345a53e881d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
@@ -21,11 +21,13 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
+#include <subdev/bios.h>
+#include <subdev/bios/init.h>
+
u64
-gm107_devinit_disable(struct nouveau_devinit *devinit)
+gm107_devinit_disable(struct nvkm_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r021c00 = nv_rd32(priv, 0x021c00);
@@ -42,16 +44,16 @@ gm107_devinit_disable(struct nouveau_devinit *devinit)
return disable;
}
-struct nouveau_oclass *
-gm107_devinit_oclass = &(struct nouveau_devinit_impl) {
+struct nvkm_oclass *
+gm107_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x07),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_devinit_ctor,
- .dtor = _nouveau_devinit_dtor,
+ .dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
- .fini = _nouveau_devinit_fini,
+ .fini = _nvkm_devinit_fini,
},
- .pll_set = nvc0_devinit_pll_set,
+ .pll_set = gf100_devinit_pll_set,
.disable = gm107_devinit_disable,
.post = nvbios_init,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c
index e44a86662a2a..535172c5f1ad 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c
@@ -21,17 +21,16 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/pmu.h>
-#include "nv50.h"
-
static void
pmu_code(struct nv50_devinit_priv *priv, u32 pmu, u32 img, u32 len, bool sec)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
int i;
nv_wr32(priv, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu);
@@ -50,7 +49,7 @@ pmu_code(struct nv50_devinit_priv *priv, u32 pmu, u32 img, u32 len, bool sec)
static void
pmu_data(struct nv50_devinit_priv *priv, u32 pmu, u32 img, u32 len)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
int i;
nv_wr32(priv, 0x10a1c0, 0x01000000 | pmu);
@@ -78,7 +77,7 @@ static int
pmu_load(struct nv50_devinit_priv *priv, u8 type, bool post,
u32 *init_addr_pmu, u32 *args_addr_pmu)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_pmuR pmu;
if (!nvbios_pmuRm(bios, type, &pmu)) {
@@ -103,10 +102,10 @@ pmu_load(struct nv50_devinit_priv *priv, u8 type, bool post,
}
static int
-gm204_devinit_post(struct nouveau_subdev *subdev, bool post)
+gm204_devinit_post(struct nvkm_subdev *subdev, bool post)
{
- struct nv50_devinit_priv *priv = (void *)nouveau_devinit(subdev);
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nv50_devinit_priv *priv = (void *)nvkm_devinit(subdev);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct bit_entry bit_I;
u32 init, args;
int ret;
@@ -158,16 +157,16 @@ gm204_devinit_post(struct nouveau_subdev *subdev, bool post)
return pmu_load(priv, 0x01, post, NULL, NULL);
}
-struct nouveau_oclass *
-gm204_devinit_oclass = &(struct nouveau_devinit_impl) {
+struct nvkm_oclass *
+gm204_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x07),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_devinit_ctor,
- .dtor = _nouveau_devinit_dtor,
+ .dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
- .fini = _nouveau_devinit_fini,
+ .fini = _nvkm_devinit_fini,
},
- .pll_set = nvc0_devinit_pll_set,
+ .pll_set = gf100_devinit_pll_set,
.disable = gm107_devinit_disable,
.post = gm204_devinit_post,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
similarity index 82%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
index 830fdffa9644..6a3e8d4efed7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
@@ -21,14 +21,18 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
+#include <subdev/bios.h>
+#include <subdev/bios/init.h>
+#include <subdev/bios/pll.h>
+#include <subdev/clk/pll.h>
+
int
-nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
+gt215_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
{
struct nv50_devinit_priv *priv = (void *)devinit;
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_pll info;
int N, fN, M, P;
int ret;
@@ -37,7 +41,7 @@ nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
if (ret)
return ret;
- ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P);
+ ret = gt215_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P);
if (ret < 0)
return ret;
@@ -59,7 +63,7 @@ nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
}
static u64
-nva3_devinit_disable(struct nouveau_devinit *devinit)
+gt215_devinit_disable(struct nvkm_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r001540 = nv_rd32(priv, 0x001540);
@@ -82,7 +86,7 @@ nva3_devinit_disable(struct nouveau_devinit *devinit)
}
static u32
-nva3_devinit_mmio_part[] = {
+gt215_devinit_mmio_part[] = {
0x100720, 0x1008bc, 4,
0x100a20, 0x100adc, 4,
0x100d80, 0x100ddc, 4,
@@ -95,10 +99,10 @@ nva3_devinit_mmio_part[] = {
};
static u32
-nva3_devinit_mmio(struct nouveau_devinit *devinit, u32 addr)
+gt215_devinit_mmio(struct nvkm_devinit *devinit, u32 addr)
{
struct nv50_devinit_priv *priv = (void *)devinit;
- u32 *mmio = nva3_devinit_mmio_part;
+ u32 *mmio = gt215_devinit_mmio_part;
/* the init tables on some boards have INIT_RAM_RESTRICT_ZM_REG_GROUP
* instructions which touch registers that may not even exist on
@@ -130,17 +134,17 @@ nva3_devinit_mmio(struct nouveau_devinit *devinit, u32 addr)
return addr;
}
-struct nouveau_oclass *
-nva3_devinit_oclass = &(struct nouveau_devinit_impl) {
+struct nvkm_oclass *
+gt215_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0xa3),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_devinit_ctor,
- .dtor = _nouveau_devinit_dtor,
+ .dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
- .fini = _nouveau_devinit_fini,
+ .fini = _nvkm_devinit_fini,
},
- .pll_set = nva3_devinit_pll_set,
- .disable = nva3_devinit_disable,
- .mmio = nva3_devinit_mmio,
+ .pll_set = gt215_devinit_pll_set,
+ .disable = gt215_devinit_disable,
+ .mmio = gt215_devinit_mmio,
.post = nvbios_init,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
similarity index 84%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
index f70b9542ad03..55cf48bbca1c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
@@ -21,11 +21,13 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
+#include <subdev/bios.h>
+#include <subdev/bios/init.h>
+
static u64
-nvaf_devinit_disable(struct nouveau_devinit *devinit)
+mcp89_devinit_disable(struct nvkm_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r001540 = nv_rd32(priv, 0x001540);
@@ -49,16 +51,16 @@ nvaf_devinit_disable(struct nouveau_devinit *devinit)
return disable;
}
-struct nouveau_oclass *
-nvaf_devinit_oclass = &(struct nouveau_devinit_impl) {
+struct nvkm_oclass *
+mcp89_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0xaf),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_devinit_ctor,
- .dtor = _nouveau_devinit_dtor,
+ .dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
- .fini = _nouveau_devinit_fini,
+ .fini = _nvkm_devinit_fini,
},
- .pll_set = nva3_devinit_pll_set,
- .disable = nvaf_devinit_disable,
+ .pll_set = gt215_devinit_pll_set,
+ .disable = mcp89_devinit_disable,
.post = nvbios_init,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
index 65651c50f6ea..03a0da834244 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
@@ -23,14 +23,17 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
+#include "nv04.h"
+#include "fbmem.h"
+#include <subdev/bios.h>
+#include <subdev/bios/init.h>
+#include <subdev/bios/pll.h>
+#include <subdev/clk/pll.h>
#include <subdev/vga.h>
-#include "fbmem.h"
-#include "nv04.h"
-
static void
-nv04_devinit_meminit(struct nouveau_devinit *devinit)
+nv04_devinit_meminit(struct nvkm_devinit *devinit)
{
struct nv04_devinit_priv *priv = (void *)devinit;
u32 patt = 0xdeadbeef;
@@ -136,10 +139,10 @@ powerctrl_1_shift(int chip_version, int reg)
}
void
-setPLL_single(struct nouveau_devinit *devinit, u32 reg,
- struct nouveau_pll_vals *pv)
+setPLL_single(struct nvkm_devinit *devinit, u32 reg,
+ struct nvkm_pll_vals *pv)
{
- int chip_version = nouveau_bios(devinit)->version.chip;
+ int chip_version = nvkm_bios(devinit)->version.chip;
uint32_t oldpll = nv_rd32(devinit, reg);
int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
@@ -190,10 +193,10 @@ new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
}
void
-setPLL_double_highregs(struct nouveau_devinit *devinit, u32 reg1,
- struct nouveau_pll_vals *pv)
+setPLL_double_highregs(struct nvkm_devinit *devinit, u32 reg1,
+ struct nvkm_pll_vals *pv)
{
- int chip_version = nouveau_bios(devinit)->version.chip;
+ int chip_version = nvkm_bios(devinit)->version.chip;
bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
uint32_t oldpll1 = nv_rd32(devinit, reg1);
@@ -267,8 +270,8 @@ setPLL_double_highregs(struct nouveau_devinit *devinit, u32 reg1,
}
void
-setPLL_double_lowregs(struct nouveau_devinit *devinit, u32 NMNMreg,
- struct nouveau_pll_vals *pv)
+setPLL_double_lowregs(struct nvkm_devinit *devinit, u32 NMNMreg,
+ struct nvkm_pll_vals *pv)
{
/* When setting PLLs, there is a merry game of disabling and enabling
* various bits of hardware during the process. This function is a
@@ -301,7 +304,7 @@ setPLL_double_lowregs(struct nouveau_devinit *devinit, u32 NMNMreg,
struct nvbios_pll info;
uint8_t Pval2;
- if (nvbios_pll_parse(nouveau_bios(devinit), Preg, &info))
+ if (nvbios_pll_parse(nvkm_bios(devinit), Preg, &info))
return;
Pval2 = pv->log2P + info.bias_p;
@@ -347,10 +350,10 @@ setPLL_double_lowregs(struct nouveau_devinit *devinit, u32 NMNMreg,
}
int
-nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
+nv04_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
{
- struct nouveau_bios *bios = nouveau_bios(devinit);
- struct nouveau_pll_vals pv;
+ struct nvkm_bios *bios = nvkm_bios(devinit);
+ struct nvkm_pll_vals pv;
struct nvbios_pll info;
int cv = bios->version.chip;
int N1, M1, N2, M2, P;
@@ -361,7 +364,7 @@ nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
return ret;
ret = nv04_pll_calc(nv_subdev(devinit), &info, freq,
- &N1, &M1, &N2, &M2, &P);
+ &N1, &M1, &N2, &M2, &P);
if (!ret)
return -EINVAL;
@@ -385,7 +388,7 @@ nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
}
int
-nv04_devinit_fini(struct nouveau_object *object, bool suspend)
+nv04_devinit_fini(struct nvkm_object *object, bool suspend)
{
struct nv04_devinit_priv *priv = (void *)object;
int ret;
@@ -393,7 +396,7 @@ nv04_devinit_fini(struct nouveau_object *object, bool suspend)
/* make i2c busses accessible */
nv_mask(priv, 0x000200, 0x00000001, 0x00000001);
- ret = nouveau_devinit_fini(&priv->base, suspend);
+ ret = nvkm_devinit_fini(&priv->base, suspend);
if (ret)
return ret;
@@ -401,12 +404,11 @@ nv04_devinit_fini(struct nouveau_object *object, bool suspend)
if (priv->owner < 0)
priv->owner = nv_rdvgaowner(priv);
nv_wrvgaowner(priv, 0);
-
return 0;
}
int
-nv04_devinit_init(struct nouveau_object *object)
+nv04_devinit_init(struct nvkm_object *object)
{
struct nv04_devinit_priv *priv = (void *)object;
@@ -422,29 +424,29 @@ nv04_devinit_init(struct nouveau_object *object)
}
}
- return nouveau_devinit_init(&priv->base);
+ return nvkm_devinit_init(&priv->base);
}
void
-nv04_devinit_dtor(struct nouveau_object *object)
+nv04_devinit_dtor(struct nvkm_object *object)
{
struct nv04_devinit_priv *priv = (void *)object;
/* restore vga owner saved at first init */
nv_wrvgaowner(priv, priv->owner);
- nouveau_devinit_destroy(&priv->base);
+ nvkm_devinit_destroy(&priv->base);
}
int
-nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_devinit_priv *priv;
int ret;
- ret = nouveau_devinit_create(parent, engine, oclass, &priv);
+ ret = nvkm_devinit_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -453,10 +455,10 @@ nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
-nv04_devinit_oclass = &(struct nouveau_devinit_impl) {
+struct nvkm_oclass *
+nv04_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x04),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h
index 23470a57510c..14a51a9ff7d0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h
@@ -1,23 +1,22 @@
#ifndef __NVKM_DEVINIT_NV04_H__
#define __NVKM_DEVINIT_NV04_H__
-
#include "priv.h"
+struct nvkm_pll_vals;
struct nv04_devinit_priv {
- struct nouveau_devinit base;
+ struct nvkm_devinit base;
u8 owner;
};
-int nv04_devinit_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nv04_devinit_dtor(struct nouveau_object *);
-int nv04_devinit_init(struct nouveau_object *);
-int nv04_devinit_fini(struct nouveau_object *, bool);
-int nv04_devinit_pll_set(struct nouveau_devinit *, u32, u32);
-
-void setPLL_single(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
-void setPLL_double_highregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
-void setPLL_double_lowregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
+int nv04_devinit_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void nv04_devinit_dtor(struct nvkm_object *);
+int nv04_devinit_init(struct nvkm_object *);
+int nv04_devinit_fini(struct nvkm_object *, bool);
+int nv04_devinit_pll_set(struct nvkm_devinit *, u32, u32);
+void setPLL_single(struct nvkm_devinit *, u32, struct nvkm_pll_vals *);
+void setPLL_double_highregs(struct nvkm_devinit *, u32, struct nvkm_pll_vals *);
+void setPLL_double_lowregs(struct nvkm_devinit *, u32, struct nvkm_pll_vals *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
index a2007a3efc4d..def8649216c2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
@@ -23,16 +23,16 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
+#include "nv04.h"
+#include "fbmem.h"
#include <subdev/bios.h>
#include <subdev/bios/bmp.h>
+#include <subdev/bios/init.h>
#include <subdev/vga.h>
-#include "fbmem.h"
-#include "nv04.h"
-
static void
-nv05_devinit_meminit(struct nouveau_devinit *devinit)
+nv05_devinit_meminit(struct nvkm_devinit *devinit)
{
static const u8 default_config_tab[][2] = {
{ 0x24, 0x00 },
@@ -45,7 +45,7 @@ nv05_devinit_meminit(struct nouveau_devinit *devinit)
{ 0x00, 0x00 }
};
struct nv04_devinit_priv *priv = (void *)devinit;
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct io_mapping *fb;
u32 patt = 0xdeadbeef;
u16 data;
@@ -125,10 +125,10 @@ out:
fbmem_fini(fb);
}
-struct nouveau_oclass *
-nv05_devinit_oclass = &(struct nouveau_devinit_impl) {
+struct nvkm_oclass *
+nv05_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x05),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
index 178b46f79b50..7aabc1bf0640 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
@@ -23,14 +23,14 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
-#include <subdev/vga.h>
-
-#include "fbmem.h"
#include "nv04.h"
+#include "fbmem.h"
+
+#include <subdev/bios.h>
+#include <subdev/bios/init.h>
static void
-nv10_devinit_meminit(struct nouveau_devinit *devinit)
+nv10_devinit_meminit(struct nvkm_devinit *devinit)
{
struct nv04_devinit_priv *priv = (void *)devinit;
static const int mem_width[] = { 0x10, 0x00, 0x20 };
@@ -96,10 +96,10 @@ amount_found:
fbmem_fini(fb);
}
-struct nouveau_oclass *
-nv10_devinit_oclass = &(struct nouveau_devinit_impl) {
+struct nvkm_oclass *
+nv10_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x10),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c
index 995dd97af3e9..9f36fff5a1c3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c
@@ -21,13 +21,15 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
-struct nouveau_oclass *
-nv1a_devinit_oclass = &(struct nouveau_devinit_impl) {
+#include <subdev/bios.h>
+#include <subdev/bios/init.h>
+
+struct nvkm_oclass *
+nv1a_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x1a),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c
index 915089fb46f7..02fcfd921c42 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c
@@ -23,15 +23,17 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
#include "fbmem.h"
+#include <subdev/bios.h>
+#include <subdev/bios/init.h>
+
static void
-nv20_devinit_meminit(struct nouveau_devinit *devinit)
+nv20_devinit_meminit(struct nvkm_devinit *devinit)
{
struct nv04_devinit_priv *priv = (void *)devinit;
- struct nouveau_device *device = nv_device(priv);
+ struct nvkm_device *device = nv_device(priv);
uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900);
uint32_t amount, off;
struct io_mapping *fb;
@@ -60,10 +62,10 @@ nv20_devinit_meminit(struct nouveau_devinit *devinit)
fbmem_fini(fb);
}
-struct nouveau_oclass *
-nv20_devinit_oclass = &(struct nouveau_devinit_impl) {
+struct nvkm_oclass *
+nv20_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x20),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
index 968334d1dca4..26b7cb13e167 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
@@ -21,21 +21,22 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/disp.h>
#include <subdev/bios/init.h>
+#include <subdev/bios/pll.h>
+#include <subdev/clk/pll.h>
#include <subdev/ibus.h>
#include <subdev/vga.h>
-#include "nv50.h"
-
int
-nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
+nv50_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
{
struct nv50_devinit_priv *priv = (void *)devinit;
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_pll info;
int N1, M1, N2, M2, P;
int ret;
@@ -76,7 +77,7 @@ nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
}
static u64
-nv50_devinit_disable(struct nouveau_devinit *devinit)
+nv50_devinit_disable(struct nvkm_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r001540 = nv_rd32(priv, 0x001540);
@@ -89,10 +90,10 @@ nv50_devinit_disable(struct nouveau_devinit *devinit)
}
int
-nv50_devinit_init(struct nouveau_object *object)
+nv50_devinit_init(struct nvkm_object *object)
{
- struct nouveau_bios *bios = nouveau_bios(object);
- struct nouveau_ibus *ibus = nouveau_ibus(object);
+ struct nvkm_bios *bios = nvkm_bios(object);
+ struct nvkm_ibus *ibus = nvkm_ibus(object);
struct nv50_devinit_priv *priv = (void *)object;
struct nvbios_outp info;
struct dcb_output outp;
@@ -114,7 +115,7 @@ nv50_devinit_init(struct nouveau_object *object)
if (priv->base.post && ibus)
nv_ofuncs(ibus)->init(nv_object(ibus));
- ret = nouveau_devinit_init(&priv->base);
+ ret = nvkm_devinit_init(&priv->base);
if (ret)
return ret;
@@ -124,7 +125,7 @@ nv50_devinit_init(struct nouveau_object *object)
*/
while (priv->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) {
if (nvbios_outp_match(bios, outp.hasht, outp.hashm,
- &ver, &hdr, &cnt, &len, &info)) {
+ &ver, &hdr, &cnt, &len, &info)) {
struct nvbios_init init = {
.subdev = nv_subdev(priv),
.bios = bios,
@@ -143,14 +144,14 @@ nv50_devinit_init(struct nouveau_object *object)
}
int
-nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_devinit_priv *priv;
int ret;
- ret = nouveau_devinit_create(parent, engine, oclass, &priv);
+ ret = nvkm_devinit_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -158,14 +159,14 @@ nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
-nv50_devinit_oclass = &(struct nouveau_devinit_impl) {
+struct nvkm_oclass *
+nv50_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x50),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_devinit_ctor,
- .dtor = _nouveau_devinit_dtor,
+ .dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
- .fini = _nouveau_devinit_fini,
+ .fini = _nvkm_devinit_fini,
},
.pll_set = nv50_devinit_pll_set,
.disable = nv50_devinit_disable,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h
index f412bb7f780e..b882b65ff3cd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h
@@ -1,23 +1,21 @@
#ifndef __NVKM_DEVINIT_NV50_H__
#define __NVKM_DEVINIT_NV50_H__
-
#include "priv.h"
struct nv50_devinit_priv {
- struct nouveau_devinit base;
+ struct nvkm_devinit base;
u32 r001540;
};
-int nv50_devinit_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-int nv50_devinit_init(struct nouveau_object *);
-int nv50_devinit_pll_set(struct nouveau_devinit *, u32, u32);
+int nv50_devinit_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+int nv50_devinit_init(struct nvkm_object *);
+int nv50_devinit_pll_set(struct nvkm_devinit *, u32, u32);
-int nva3_devinit_pll_set(struct nouveau_devinit *, u32, u32);
+int gt215_devinit_pll_set(struct nvkm_devinit *, u32, u32);
-int nvc0_devinit_pll_set(struct nouveau_devinit *, u32, u32);
-
-u64 gm107_devinit_disable(struct nouveau_devinit *);
+int gf100_devinit_pll_set(struct nvkm_devinit *, u32, u32);
+u64 gm107_devinit_disable(struct nvkm_devinit *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
index 7a768afba813..bb51a95d8012 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
@@ -1,40 +1,34 @@
#ifndef __NVKM_DEVINIT_PRIV_H__
#define __NVKM_DEVINIT_PRIV_H__
-
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-#include <subdev/bios/init.h>
-#include <subdev/clk/pll.h>
#include <subdev/devinit.h>
-struct nouveau_devinit_impl {
- struct nouveau_oclass base;
- void (*meminit)(struct nouveau_devinit *);
- int (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq);
- u64 (*disable)(struct nouveau_devinit *);
- u32 (*mmio)(struct nouveau_devinit *, u32);
- int (*post)(struct nouveau_subdev *, bool);
+struct nvkm_devinit_impl {
+ struct nvkm_oclass base;
+ void (*meminit)(struct nvkm_devinit *);
+ int (*pll_set)(struct nvkm_devinit *, u32 type, u32 freq);
+ u64 (*disable)(struct nvkm_devinit *);
+ u32 (*mmio)(struct nvkm_devinit *, u32);
+ int (*post)(struct nvkm_subdev *, bool);
};
-#define nouveau_devinit_create(p,e,o,d) \
- nouveau_devinit_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_devinit_destroy(p) ({ \
- struct nouveau_devinit *d = (p); \
- _nouveau_devinit_dtor(nv_object(d)); \
+#define nvkm_devinit_create(p,e,o,d) \
+ nvkm_devinit_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_devinit_destroy(p) ({ \
+ struct nvkm_devinit *d = (p); \
+ _nvkm_devinit_dtor(nv_object(d)); \
})
-#define nouveau_devinit_init(p) ({ \
- struct nouveau_devinit *d = (p); \
- _nouveau_devinit_init(nv_object(d)); \
+#define nvkm_devinit_init(p) ({ \
+ struct nvkm_devinit *d = (p); \
+ _nvkm_devinit_init(nv_object(d)); \
})
-#define nouveau_devinit_fini(p,s) ({ \
- struct nouveau_devinit *d = (p); \
- _nouveau_devinit_fini(nv_object(d), (s)); \
+#define nvkm_devinit_fini(p,s) ({ \
+ struct nvkm_devinit *d = (p); \
+ _nvkm_devinit_fini(nv_object(d), (s)); \
})
-int nouveau_devinit_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-void _nouveau_devinit_dtor(struct nouveau_object *);
-int _nouveau_devinit_init(struct nouveau_object *);
-int _nouveau_devinit_fini(struct nouveau_object *, bool suspend);
-
+int nvkm_devinit_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+void _nvkm_devinit_dtor(struct nvkm_object *);
+int _nvkm_devinit_init(struct nvkm_object *);
+int _nvkm_devinit_fini(struct nvkm_object *, bool suspend);
#endif
From 639c308effb945732feb26fe416a6f00f3147ae4 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 14:52:58 +1000
Subject: [PATCH 57/86] drm/nouveau/fb: namespace + nvidia gpu names (no binary
change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 17 ++
.../gpu/drm/nouveau/include/nvkm/subdev/fb.h | 128 +++++----
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 26 +-
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild | 20 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c | 56 ++--
.../nouveau/nvkm/subdev/fb/{nv84.c => g84.c} | 9 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c | 4 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c | 4 +-
.../nvkm/subdev/fb/{nvc0.c => gf100.c} | 60 ++---
.../gpu/drm/nouveau/nvkm/subdev/fb/gf100.h | 28 ++
.../nvkm/subdev/fb/{nve0.c => gk104.c} | 21 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c | 29 +--
.../gpu/drm/nouveau/nvkm/subdev/fb/gm107.c | 19 +-
.../nvkm/subdev/fb/{nva3.c => gt215.c} | 11 +-
.../nvkm/subdev/fb/{nvaa.c => mcp77.c} | 11 +-
.../nvkm/subdev/fb/{nvaf.c => mcp89.c} | 11 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c | 26 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h | 66 +++--
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c | 19 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c | 11 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c | 27 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c | 17 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c | 27 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c | 15 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c | 15 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c | 19 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h | 11 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c | 15 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c | 19 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c | 13 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c | 9 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c | 9 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c | 9 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 88 +++----
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h | 28 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.h | 31 ---
drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h | 116 ++++-----
.../gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h | 38 ++-
.../nvkm/subdev/fb/{ramnvc0.c => ramgf100.c} | 175 ++++++-------
.../nvkm/subdev/fb/{ramnve0.c => ramgk104.c} | 246 +++++++++---------
.../gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c | 33 +--
.../gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c | 23 +-
.../nvkm/subdev/fb/{ramnva3.c => ramgt215.c} | 205 +++++++--------
.../nvkm/subdev/fb/{ramnvaa.c => rammcp77.c} | 46 ++--
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c | 27 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c | 24 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c | 23 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c | 23 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c | 38 ++-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c | 21 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c | 21 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c | 21 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c | 23 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c | 114 ++++----
.../gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h | 3 -
.../gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h | 5 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c | 3 +-
.../gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c | 3 +-
60 files changed, 1049 insertions(+), 1142 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/subdev/fb/{nv84.c => g84.c} (90%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/fb/{nvc0.c => gf100.c} (64%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h
rename drivers/gpu/drm/nouveau/nvkm/subdev/fb/{nve0.c => gk104.c} (80%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/fb/{nva3.c => gt215.c} (88%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/fb/{nvaa.c => mcp77.c} (88%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/fb/{nvaf.c => mcp89.c} (88%)
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.h
rename drivers/gpu/drm/nouveau/nvkm/subdev/fb/{ramnvc0.c => ramgf100.c} (83%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/fb/{ramnve0.c => ramgk104.c} (90%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/fb/{ramnva3.c => ramgt215.c} (86%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/fb/{ramnvaa.c => rammcp77.c} (73%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 2b0fe0e7da8c..9571710e637c 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -220,5 +220,22 @@
#define nva3_clk_info gt215_clk_info
#define nva3_pll_info gt215_pll_info
#define nouveau_ibus nvkm_ibus
+#define nouveau_memx nvkm_memx
+#define nouveau_memx_block nvkm_memx_block
+#define nouveau_memx_unblock nvkm_memx_unblock
+#define nouveau_memx_train nvkm_memx_train
+#define nouveau_memx_train_result nvkm_memx_train_result
+#define nouveau_memx_wait_vblank nvkm_memx_wait_vblank
+#define nouveau_memx_rd32 nvkm_memx_rd32
+#define nouveau_memx_wr32 nvkm_memx_wr32
+#define nouveau_memx_wait nvkm_memx_wait
+#define nouveau_memx_init nvkm_memx_init
+#define nouveau_memx_fini nvkm_memx_fini
+#define nouveau_memx_nsec nvkm_memx_nsec
+#define nouveau_ltc nvkm_ltc
+#define nouveau_pmu nvkm_pmu
+#define nouveau_fb nvkm_fb
+#define nouveau_fb_tile nvkm_fb_tile
+#define nvc0_pte_storage_type_map gf100_pte_storage_type_map
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
index b6a210071b22..16da56cf43b0 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
@@ -1,9 +1,6 @@
-#ifndef __NOUVEAU_FB_H__
-#define __NOUVEAU_FB_H__
-
+#ifndef __NVKM_FB_H__
+#define __NVKM_FB_H__
#include <core/subdev.h>
-#include <core/device.h>
-#include <core/mm.h>
#include <subdev/mmu.h>
@@ -24,14 +21,14 @@
#define NV_MEM_TYPE_VM 0x7f
#define NV_MEM_COMP_VM 0x03
-struct nouveau_mem {
+struct nvkm_mem {
struct drm_device *dev;
- struct nouveau_vma bar_vma;
- struct nouveau_vma vma[2];
+ struct nvkm_vma bar_vma;
+ struct nvkm_vma vma[2];
u8 page_shift;
- struct nouveau_mm_node *tag;
+ struct nvkm_mm_node *tag;
struct list_head regions;
dma_addr_t *pages;
u32 memtype;
@@ -40,85 +37,83 @@ struct nouveau_mem {
struct sg_table *sg;
};
-struct nouveau_fb_tile {
- struct nouveau_mm_node *tag;
+struct nvkm_fb_tile {
+ struct nvkm_mm_node *tag;
u32 addr;
u32 limit;
u32 pitch;
u32 zcomp;
};
-struct nouveau_fb {
- struct nouveau_subdev base;
+struct nvkm_fb {
+ struct nvkm_subdev base;
- bool (*memtype_valid)(struct nouveau_fb *, u32 memtype);
+ bool (*memtype_valid)(struct nvkm_fb *, u32 memtype);
- struct nouveau_ram *ram;
+ struct nvkm_ram *ram;
- struct nouveau_mm vram;
- struct nouveau_mm tags;
+ struct nvkm_mm vram;
+ struct nvkm_mm tags;
struct {
- struct nouveau_fb_tile region[16];
+ struct nvkm_fb_tile region[16];
int regions;
- void (*init)(struct nouveau_fb *, int i, u32 addr, u32 size,
- u32 pitch, u32 flags, struct nouveau_fb_tile *);
- void (*comp)(struct nouveau_fb *, int i, u32 size, u32 flags,
- struct nouveau_fb_tile *);
- void (*fini)(struct nouveau_fb *, int i,
- struct nouveau_fb_tile *);
- void (*prog)(struct nouveau_fb *, int i,
- struct nouveau_fb_tile *);
+ void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size,
+ u32 pitch, u32 flags, struct nvkm_fb_tile *);
+ void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags,
+ struct nvkm_fb_tile *);
+ void (*fini)(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
+ void (*prog)(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
} tile;
};
-static inline struct nouveau_fb *
-nouveau_fb(void *obj)
+static inline struct nvkm_fb *
+nvkm_fb(void *obj)
{
/* fbram uses this before device subdev pointer is valid */
if (nv_iclass(obj, NV_SUBDEV_CLASS) &&
nv_subidx(obj) == NVDEV_SUBDEV_FB)
return obj;
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_FB);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_FB);
}
-extern struct nouveau_oclass *nv04_fb_oclass;
-extern struct nouveau_oclass *nv10_fb_oclass;
-extern struct nouveau_oclass *nv1a_fb_oclass;
-extern struct nouveau_oclass *nv20_fb_oclass;
-extern struct nouveau_oclass *nv25_fb_oclass;
-extern struct nouveau_oclass *nv30_fb_oclass;
-extern struct nouveau_oclass *nv35_fb_oclass;
-extern struct nouveau_oclass *nv36_fb_oclass;
-extern struct nouveau_oclass *nv40_fb_oclass;
-extern struct nouveau_oclass *nv41_fb_oclass;
-extern struct nouveau_oclass *nv44_fb_oclass;
-extern struct nouveau_oclass *nv46_fb_oclass;
-extern struct nouveau_oclass *nv47_fb_oclass;
-extern struct nouveau_oclass *nv49_fb_oclass;
-extern struct nouveau_oclass *nv4e_fb_oclass;
-extern struct nouveau_oclass *nv50_fb_oclass;
-extern struct nouveau_oclass *nv84_fb_oclass;
-extern struct nouveau_oclass *nva3_fb_oclass;
-extern struct nouveau_oclass *nvaa_fb_oclass;
-extern struct nouveau_oclass *nvaf_fb_oclass;
-extern struct nouveau_oclass *nvc0_fb_oclass;
-extern struct nouveau_oclass *nve0_fb_oclass;
-extern struct nouveau_oclass *gk20a_fb_oclass;
-extern struct nouveau_oclass *gm107_fb_oclass;
+extern struct nvkm_oclass *nv04_fb_oclass;
+extern struct nvkm_oclass *nv10_fb_oclass;
+extern struct nvkm_oclass *nv1a_fb_oclass;
+extern struct nvkm_oclass *nv20_fb_oclass;
+extern struct nvkm_oclass *nv25_fb_oclass;
+extern struct nvkm_oclass *nv30_fb_oclass;
+extern struct nvkm_oclass *nv35_fb_oclass;
+extern struct nvkm_oclass *nv36_fb_oclass;
+extern struct nvkm_oclass *nv40_fb_oclass;
+extern struct nvkm_oclass *nv41_fb_oclass;
+extern struct nvkm_oclass *nv44_fb_oclass;
+extern struct nvkm_oclass *nv46_fb_oclass;
+extern struct nvkm_oclass *nv47_fb_oclass;
+extern struct nvkm_oclass *nv49_fb_oclass;
+extern struct nvkm_oclass *nv4e_fb_oclass;
+extern struct nvkm_oclass *nv50_fb_oclass;
+extern struct nvkm_oclass *g84_fb_oclass;
+extern struct nvkm_oclass *gt215_fb_oclass;
+extern struct nvkm_oclass *mcp77_fb_oclass;
+extern struct nvkm_oclass *mcp89_fb_oclass;
+extern struct nvkm_oclass *gf100_fb_oclass;
+extern struct nvkm_oclass *gk104_fb_oclass;
+extern struct nvkm_oclass *gk20a_fb_oclass;
+extern struct nvkm_oclass *gm107_fb_oclass;
#include <subdev/bios.h>
#include <subdev/bios/ramcfg.h>
-struct nouveau_ram_data {
+struct nvkm_ram_data {
struct list_head head;
struct nvbios_ramcfg bios;
u32 freq;
};
-struct nouveau_ram {
- struct nouveau_object base;
+struct nvkm_ram {
+ struct nvkm_object base;
enum {
NV_MEM_TYPE_UNKNOWN = 0,
NV_MEM_TYPE_STOLEN,
@@ -140,21 +135,20 @@ struct nouveau_ram {
int parts;
int part_mask;
- int (*get)(struct nouveau_fb *, u64 size, u32 align,
- u32 size_nc, u32 type, struct nouveau_mem **);
- void (*put)(struct nouveau_fb *, struct nouveau_mem **);
+ int (*get)(struct nvkm_fb *, u64 size, u32 align, u32 size_nc,
+ u32 type, struct nvkm_mem **);
+ void (*put)(struct nvkm_fb *, struct nvkm_mem **);
- int (*calc)(struct nouveau_fb *, u32 freq);
- int (*prog)(struct nouveau_fb *);
- void (*tidy)(struct nouveau_fb *);
+ int (*calc)(struct nvkm_fb *, u32 freq);
+ int (*prog)(struct nvkm_fb *);
+ void (*tidy)(struct nvkm_fb *);
u32 freq;
u32 mr[16];
u32 mr1_nuts;
- struct nouveau_ram_data *next;
- struct nouveau_ram_data former;
- struct nouveau_ram_data xition;
- struct nouveau_ram_data target;
+ struct nvkm_ram_data *next;
+ struct nvkm_ram_data former;
+ struct nvkm_ram_data xition;
+ struct nvkm_ram_data target;
};
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index ead391480479..393b14cfddfa 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -100,7 +100,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
@@ -129,7 +129,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
@@ -158,7 +158,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
@@ -187,7 +187,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
@@ -216,7 +216,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
@@ -245,7 +245,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
@@ -274,7 +274,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
@@ -303,7 +303,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
@@ -332,7 +332,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
@@ -361,7 +361,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
@@ -392,7 +392,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
@@ -422,7 +422,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
@@ -452,7 +452,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 56843b0cdfb0..fc71b6705083 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -72,7 +72,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -105,7 +105,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -138,7 +138,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -170,7 +170,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -203,7 +203,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -235,7 +235,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -267,7 +267,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -300,7 +300,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -332,7 +332,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 2abd532e2b09..ca6b2a6f124c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -72,7 +72,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -106,7 +106,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -140,7 +140,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -196,7 +196,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -230,7 +230,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -264,7 +264,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@@ -297,7 +297,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
+ device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild
index bfd0166d3e1b..904d601e8a50 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild
@@ -15,12 +15,12 @@ nvkm-y += nvkm/subdev/fb/nv47.o
nvkm-y += nvkm/subdev/fb/nv49.o
nvkm-y += nvkm/subdev/fb/nv4e.o
nvkm-y += nvkm/subdev/fb/nv50.o
-nvkm-y += nvkm/subdev/fb/nv84.o
-nvkm-y += nvkm/subdev/fb/nva3.o
-nvkm-y += nvkm/subdev/fb/nvaa.o
-nvkm-y += nvkm/subdev/fb/nvaf.o
-nvkm-y += nvkm/subdev/fb/nvc0.o
-nvkm-y += nvkm/subdev/fb/nve0.o
+nvkm-y += nvkm/subdev/fb/g84.o
+nvkm-y += nvkm/subdev/fb/gt215.o
+nvkm-y += nvkm/subdev/fb/mcp77.o
+nvkm-y += nvkm/subdev/fb/mcp89.o
+nvkm-y += nvkm/subdev/fb/gf100.o
+nvkm-y += nvkm/subdev/fb/gk104.o
nvkm-y += nvkm/subdev/fb/gk20a.o
nvkm-y += nvkm/subdev/fb/gm107.o
nvkm-y += nvkm/subdev/fb/ramnv04.o
@@ -33,10 +33,10 @@ nvkm-y += nvkm/subdev/fb/ramnv44.o
nvkm-y += nvkm/subdev/fb/ramnv49.o
nvkm-y += nvkm/subdev/fb/ramnv4e.o
nvkm-y += nvkm/subdev/fb/ramnv50.o
-nvkm-y += nvkm/subdev/fb/ramnva3.o
-nvkm-y += nvkm/subdev/fb/ramnvaa.o
-nvkm-y += nvkm/subdev/fb/ramnvc0.o
-nvkm-y += nvkm/subdev/fb/ramnve0.o
+nvkm-y += nvkm/subdev/fb/ramgt215.o
+nvkm-y += nvkm/subdev/fb/rammcp77.o
+nvkm-y += nvkm/subdev/fb/ramgf100.o
+nvkm-y += nvkm/subdev/fb/ramgk104.o
nvkm-y += nvkm/subdev/fb/ramgk20a.o
nvkm-y += nvkm/subdev/fb/ramgm107.o
nvkm-y += nvkm/subdev/fb/sddr2.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
index 090a7f2ac9b3..16589fa613cd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
@@ -21,14 +21,13 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bios/M0203.h>
-#include "priv.h"
-
int
-nouveau_fb_bios_memtype(struct nouveau_bios *bios)
+nvkm_fb_bios_memtype(struct nvkm_bios *bios)
{
const u8 ramcfg = (nv_rd32(bios, 0x101000) & 0x0000003c) >> 2;
struct nvbios_M0203E M0203E;
@@ -51,25 +50,25 @@ nouveau_fb_bios_memtype(struct nouveau_bios *bios)
}
int
-_nouveau_fb_fini(struct nouveau_object *object, bool suspend)
+_nvkm_fb_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_fb *pfb = (void *)object;
+ struct nvkm_fb *pfb = (void *)object;
int ret;
ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend);
if (ret && suspend)
return ret;
- return nouveau_subdev_fini(&pfb->base, suspend);
+ return nvkm_subdev_fini(&pfb->base, suspend);
}
int
-_nouveau_fb_init(struct nouveau_object *object)
+_nvkm_fb_init(struct nvkm_object *object)
{
- struct nouveau_fb *pfb = (void *)object;
+ struct nvkm_fb *pfb = (void *)object;
int ret, i;
- ret = nouveau_subdev_init(&pfb->base);
+ ret = nvkm_subdev_init(&pfb->base);
if (ret)
return ret;
@@ -84,25 +83,25 @@ _nouveau_fb_init(struct nouveau_object *object)
}
void
-_nouveau_fb_dtor(struct nouveau_object *object)
+_nvkm_fb_dtor(struct nvkm_object *object)
{
- struct nouveau_fb *pfb = (void *)object;
+ struct nvkm_fb *pfb = (void *)object;
int i;
for (i = 0; i < pfb->tile.regions; i++)
pfb->tile.fini(pfb, i, &pfb->tile.region[i]);
- nouveau_mm_fini(&pfb->tags);
- nouveau_mm_fini(&pfb->vram);
+ nvkm_mm_fini(&pfb->tags);
+ nvkm_mm_fini(&pfb->vram);
- nouveau_object_ref(NULL, (struct nouveau_object **)&pfb->ram);
- nouveau_subdev_destroy(&pfb->base);
+ nvkm_object_ref(NULL, (struct nvkm_object **)&pfb->ram);
+ nvkm_subdev_destroy(&pfb->base);
}
int
-nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int length, void **pobject)
+nvkm_fb_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
- struct nouveau_fb_impl *impl = (void *)oclass;
+ struct nvkm_fb_impl *impl = (void *)oclass;
static const char *name[] = {
[NV_MEM_TYPE_UNKNOWN] = "unknown",
[NV_MEM_TYPE_STOLEN ] = "stolen system memory",
@@ -116,20 +115,19 @@ nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine,
[NV_MEM_TYPE_GDDR4 ] = "GDDR4",
[NV_MEM_TYPE_GDDR5 ] = "GDDR5",
};
- struct nouveau_object *ram;
- struct nouveau_fb *pfb;
+ struct nvkm_object *ram;
+ struct nvkm_fb *pfb;
int ret;
- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PFB", "fb",
- length, pobject);
+ ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PFB", "fb",
+ length, pobject);
pfb = *pobject;
if (ret)
return ret;
pfb->memtype_valid = impl->memtype;
- ret = nouveau_object_ctor(nv_object(pfb), NULL,
- impl->ram, NULL, 0, &ram);
+ ret = nvkm_object_ctor(nv_object(pfb), NULL, impl->ram, NULL, 0, &ram);
if (ret) {
nv_fatal(pfb, "error detecting memory configuration!!\n");
return ret;
@@ -137,15 +135,15 @@ nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine,
pfb->ram = (void *)ram;
- if (!nouveau_mm_initialised(&pfb->vram)) {
- ret = nouveau_mm_init(&pfb->vram, 0, pfb->ram->size >> 12, 1);
+ if (!nvkm_mm_initialised(&pfb->vram)) {
+ ret = nvkm_mm_init(&pfb->vram, 0, pfb->ram->size >> 12, 1);
if (ret)
return ret;
}
- if (!nouveau_mm_initialised(&pfb->tags)) {
- ret = nouveau_mm_init(&pfb->tags, 0, pfb->ram->tags ?
- ++pfb->ram->tags : 0, 1);
+ if (!nvkm_mm_initialised(&pfb->tags)) {
+ ret = nvkm_mm_init(&pfb->tags, 0, pfb->ram->tags ?
+ ++pfb->ram->tags : 0, 1);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c
similarity index 90%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c
index cf0e767d3833..6c968d1e98b3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c
@@ -21,17 +21,16 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
-struct nouveau_oclass *
-nv84_fb_oclass = &(struct nv50_fb_impl) {
+struct nvkm_oclass *
+g84_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x84),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
.base.ram = &nv50_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
index d85a25d027ee..15b462ae33cb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
@@ -22,8 +22,6 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
* Roy Spliet <rspliet@eclipso.eu>
*/
-
-#include <subdev/bios.h>
#include "priv.h"
struct ramxlat {
@@ -70,7 +68,7 @@ ramgddr3_wr_lo[] = {
};
int
-nouveau_gddr3_calc(struct nouveau_ram *ram)
+nvkm_gddr3_calc(struct nvkm_ram *ram)
{
int CL, WR, CWL, DLL = 0, ODT = 0, hi;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c
index 7fbbe05d5c60..f6f9eee1dcd0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c
@@ -21,8 +21,6 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include <subdev/bios.h>
#include "priv.h"
/* binary driver only executes this path if the condition (a) is true
@@ -34,7 +32,7 @@
#define NOTE00(a) 1
int
-nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts)
+nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts)
{
int pd, lf, xd, vh, vr, vo, l3;
int WL, CL, WR, at[2], dt, ds;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
similarity index 64%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
index 32f28dc73ef2..5a6c2b7a6ef1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
@@ -21,22 +21,21 @@
*
* Authors: Ben Skeggs
*/
+#include "gf100.h"
-#include "nvc0.h"
-
-extern const u8 nvc0_pte_storage_type_map[256];
+extern const u8 gf100_pte_storage_type_map[256];
bool
-nvc0_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags)
+gf100_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags)
{
u8 memtype = (tile_flags & 0x0000ff00) >> 8;
- return likely((nvc0_pte_storage_type_map[memtype] != 0xff));
+ return likely((gf100_pte_storage_type_map[memtype] != 0xff));
}
static void
-nvc0_fb_intr(struct nouveau_subdev *subdev)
+gf100_fb_intr(struct nvkm_subdev *subdev)
{
- struct nvc0_fb_priv *priv = (void *)subdev;
+ struct gf100_fb_priv *priv = (void *)subdev;
u32 intr = nv_rd32(priv, 0x000100);
if (intr & 0x08000000) {
nv_debug(priv, "PFFB intr\n");
@@ -49,26 +48,27 @@ nvc0_fb_intr(struct nouveau_subdev *subdev)
}
int
-nvc0_fb_init(struct nouveau_object *object)
+gf100_fb_init(struct nvkm_object *object)
{
- struct nvc0_fb_priv *priv = (void *)object;
+ struct gf100_fb_priv *priv = (void *)object;
int ret;
- ret = nouveau_fb_init(&priv->base);
+ ret = nvkm_fb_init(&priv->base);
if (ret)
return ret;
if (priv->r100c10_page)
nv_wr32(priv, 0x100c10, priv->r100c10 >> 8);
+
nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
return 0;
}
void
-nvc0_fb_dtor(struct nouveau_object *object)
+gf100_fb_dtor(struct nvkm_object *object)
{
- struct nouveau_device *device = nv_device(object);
- struct nvc0_fb_priv *priv = (void *)object;
+ struct nvkm_device *device = nv_device(object);
+ struct gf100_fb_priv *priv = (void *)object;
if (priv->r100c10_page) {
dma_unmap_page(nv_device_base(device), priv->r100c10, PAGE_SIZE,
@@ -76,19 +76,19 @@ nvc0_fb_dtor(struct nouveau_object *object)
__free_page(priv->r100c10_page);
}
- nouveau_fb_destroy(&priv->base);
+ nvkm_fb_destroy(&priv->base);
}
int
-nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_device *device = nv_device(parent);
- struct nvc0_fb_priv *priv;
+ struct nvkm_device *device = nv_device(parent);
+ struct gf100_fb_priv *priv;
int ret;
- ret = nouveau_fb_create(parent, engine, oclass, &priv);
+ ret = nvkm_fb_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -102,19 +102,19 @@ nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return -EFAULT;
}
- nv_subdev(priv)->intr = nvc0_fb_intr;
+ nv_subdev(priv)->intr = gf100_fb_intr;
return 0;
}
-struct nouveau_oclass *
-nvc0_fb_oclass = &(struct nouveau_fb_impl) {
+struct nvkm_oclass *
+gf100_fb_oclass = &(struct nvkm_fb_impl) {
.base.handle = NV_SUBDEV(FB, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_fb_ctor,
- .dtor = nvc0_fb_dtor,
- .init = nvc0_fb_init,
- .fini = _nouveau_fb_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_fb_ctor,
+ .dtor = gf100_fb_dtor,
+ .init = gf100_fb_init,
+ .fini = _nvkm_fb_fini,
},
- .memtype = nvc0_fb_memtype_valid,
- .ram = &nvc0_ram_oclass,
+ .memtype = gf100_fb_memtype_valid,
+ .ram = &gf100_ram_oclass,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h
new file mode 100644
index 000000000000..0af4da259471
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h
@@ -0,0 +1,28 @@
+#ifndef __NVKM_RAM_NVC0_H__
+#define __NVKM_RAM_NVC0_H__
+#include "priv.h"
+#include "nv50.h"
+
+struct gf100_fb_priv {
+ struct nvkm_fb base;
+ struct page *r100c10_page;
+ dma_addr_t r100c10;
+};
+
+int gf100_fb_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void gf100_fb_dtor(struct nvkm_object *);
+int gf100_fb_init(struct nvkm_object *);
+bool gf100_fb_memtype_valid(struct nvkm_fb *, u32);
+
+#define gf100_ram_create(p,e,o,m,d) \
+ gf100_ram_create_((p), (e), (o), (m), sizeof(**d), (void **)d)
+int gf100_ram_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, u32, int, void **);
+int gf100_ram_get(struct nvkm_fb *, u64, u32, u32, u32,
+ struct nvkm_mem **);
+void gf100_ram_put(struct nvkm_fb *, struct nvkm_mem **);
+
+int gk104_ram_init(struct nvkm_object*);
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c
similarity index 80%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/fb/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c
index 595db50cfef3..1c08317665bb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c
@@ -21,18 +21,17 @@
*
* Authors: Ben Skeggs
*/
+#include "gf100.h"
-#include "nvc0.h"
-
-struct nouveau_oclass *
-nve0_fb_oclass = &(struct nouveau_fb_impl) {
+struct nvkm_oclass *
+gk104_fb_oclass = &(struct nvkm_fb_impl) {
.base.handle = NV_SUBDEV(FB, 0xe0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_fb_ctor,
- .dtor = nvc0_fb_dtor,
- .init = nvc0_fb_init,
- .fini = _nouveau_fb_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_fb_ctor,
+ .dtor = gf100_fb_dtor,
+ .init = gf100_fb_init,
+ .fini = _nvkm_fb_fini,
},
- .memtype = nvc0_fb_memtype_valid,
- .ram = &nve0_ram_oclass,
+ .memtype = gf100_fb_memtype_valid,
+ .ram = &gk104_ram_oclass,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c
index fde42e4d1b56..6762847c05e8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c
@@ -19,20 +19,19 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
-
-#include "nvc0.h"
+#include "gf100.h"
struct gk20a_fb_priv {
- struct nouveau_fb base;
+ struct nvkm_fb base;
};
static int
-gk20a_fb_init(struct nouveau_object *object)
+gk20a_fb_init(struct nvkm_object *object)
{
struct gk20a_fb_priv *priv = (void *)object;
int ret;
- ret = nouveau_fb_init(&priv->base);
+ ret = nvkm_fb_init(&priv->base);
if (ret)
return ret;
@@ -41,14 +40,14 @@ gk20a_fb_init(struct nouveau_object *object)
}
static int
-gk20a_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk20a_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct gk20a_fb_priv *priv;
int ret;
- ret = nouveau_fb_create(parent, engine, oclass, &priv);
+ ret = nvkm_fb_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -56,15 +55,15 @@ gk20a_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
-gk20a_fb_oclass = &(struct nouveau_fb_impl) {
+struct nvkm_oclass *
+gk20a_fb_oclass = &(struct nvkm_fb_impl) {
.base.handle = NV_SUBDEV(FB, 0xea),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_fb_ctor,
- .dtor = _nouveau_fb_dtor,
+ .dtor = _nvkm_fb_dtor,
.init = gk20a_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
- .memtype = nvc0_fb_memtype_valid,
+ .memtype = gf100_fb_memtype_valid,
.ram = &gk20a_ram_oclass,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c
index c4840aedc2dc..843f9356b360 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c
@@ -21,18 +21,17 @@
*
* Authors: Ben Skeggs
*/
+#include "gf100.h"
-#include "nvc0.h"
-
-struct nouveau_oclass *
-gm107_fb_oclass = &(struct nouveau_fb_impl) {
+struct nvkm_oclass *
+gm107_fb_oclass = &(struct nvkm_fb_impl) {
.base.handle = NV_SUBDEV(FB, 0x07),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_fb_ctor,
- .dtor = nvc0_fb_dtor,
- .init = nvc0_fb_init,
- .fini = _nouveau_fb_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_fb_ctor,
+ .dtor = gf100_fb_dtor,
+ .init = gf100_fb_init,
+ .fini = _nvkm_fb_fini,
},
- .memtype = nvc0_fb_memtype_valid,
+ .memtype = gf100_fb_memtype_valid,
.ram = &gm107_ram_oclass,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c
similarity index 88%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/fb/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c
index dab6e1c63d48..dd9b8a0a3c8e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c
@@ -21,19 +21,18 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
-struct nouveau_oclass *
-nva3_fb_oclass = &(struct nv50_fb_impl) {
+struct nvkm_oclass *
+gt215_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0xa3),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
- .base.ram = &nva3_ram_oclass,
+ .base.ram = >215_ram_oclass,
.trap = 0x000d0fff,
}.base.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c
similarity index 88%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaa.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c
index cba8e6818035..7be4a47ef4ad 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaa.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c
@@ -21,19 +21,18 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
-struct nouveau_oclass *
-nvaa_fb_oclass = &(struct nv50_fb_impl) {
+struct nvkm_oclass *
+mcp77_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0xaa),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
- .base.ram = &nvaa_ram_oclass,
+ .base.ram = &mcp77_ram_oclass,
.trap = 0x001d07ff,
}.base.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c
similarity index 88%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaf.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c
index 5423faa2c09b..2d00656faef5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaf.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c
@@ -21,19 +21,18 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
-struct nouveau_oclass *
-nvaf_fb_oclass = &(struct nv50_fb_impl) {
+struct nvkm_oclass *
+mcp89_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0xaf),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
- .base.ram = &nvaa_ram_oclass,
+ .base.ram = &mcp77_ram_oclass,
.trap = 0x089d1fff,
}.base.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c
index 8309fe33fe84..c063dec7d03a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c
@@ -21,13 +21,11 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
-
-#define NV04_PFB_CFG0 0x00100200
+#include "regsnv04.h"
bool
-nv04_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags)
+nv04_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags)
{
if (!(tile_flags & 0xff00))
return true;
@@ -36,12 +34,12 @@ nv04_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags)
}
static int
-nv04_fb_init(struct nouveau_object *object)
+nv04_fb_init(struct nvkm_object *object)
{
struct nv04_fb_priv *priv = (void *)object;
int ret;
- ret = nouveau_fb_init(&priv->base);
+ ret = nvkm_fb_init(&priv->base);
if (ret)
return ret;
@@ -54,15 +52,15 @@ nv04_fb_init(struct nouveau_object *object)
}
int
-nv04_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_fb_impl *impl = (void *)oclass;
struct nv04_fb_priv *priv;
int ret;
- ret = nouveau_fb_create(parent, engine, oclass, &priv);
+ ret = nvkm_fb_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -75,14 +73,14 @@ nv04_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv04_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x04),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
+ .dtor = _nvkm_fb_dtor,
.init = nv04_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv04_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h
index 06ce71f87a74..caa0d03aaacc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h
@@ -1,55 +1,53 @@
#ifndef __NVKM_FB_NV04_H__
#define __NVKM_FB_NV04_H__
-
#include "priv.h"
struct nv04_fb_priv {
- struct nouveau_fb base;
+ struct nvkm_fb base;
};
-int nv04_fb_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
+int nv04_fb_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
struct nv04_fb_impl {
- struct nouveau_fb_impl base;
+ struct nvkm_fb_impl base;
struct {
int regions;
- void (*init)(struct nouveau_fb *, int i, u32 addr, u32 size,
- u32 pitch, u32 flags, struct nouveau_fb_tile *);
- void (*comp)(struct nouveau_fb *, int i, u32 size, u32 flags,
- struct nouveau_fb_tile *);
- void (*fini)(struct nouveau_fb *, int i,
- struct nouveau_fb_tile *);
- void (*prog)(struct nouveau_fb *, int i,
- struct nouveau_fb_tile *);
+ void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size,
+ u32 pitch, u32 flags, struct nvkm_fb_tile *);
+ void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags,
+ struct nvkm_fb_tile *);
+ void (*fini)(struct nvkm_fb *, int i,
+ struct nvkm_fb_tile *);
+ void (*prog)(struct nvkm_fb *, int i,
+ struct nvkm_fb_tile *);
} tile;
};
-void nv10_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
- u32 pitch, u32 flags, struct nouveau_fb_tile *);
-void nv10_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *);
-void nv10_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
+void nv10_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
+ u32 pitch, u32 flags, struct nvkm_fb_tile *);
+void nv10_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
+void nv10_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
-void nv20_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
- u32 pitch, u32 flags, struct nouveau_fb_tile *);
-void nv20_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *);
-void nv20_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
+void nv20_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
+ u32 pitch, u32 flags, struct nvkm_fb_tile *);
+void nv20_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
+void nv20_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
-int nv30_fb_init(struct nouveau_object *);
-void nv30_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
- u32 pitch, u32 flags, struct nouveau_fb_tile *);
+int nv30_fb_init(struct nvkm_object *);
+void nv30_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
+ u32 pitch, u32 flags, struct nvkm_fb_tile *);
-void nv40_fb_tile_comp(struct nouveau_fb *, int i, u32 size, u32 flags,
- struct nouveau_fb_tile *);
+void nv40_fb_tile_comp(struct nvkm_fb *, int i, u32 size, u32 flags,
+ struct nvkm_fb_tile *);
-int nv41_fb_init(struct nouveau_object *);
-void nv41_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
+int nv41_fb_init(struct nvkm_object *);
+void nv41_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
-int nv44_fb_init(struct nouveau_object *);
-void nv44_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
-
-void nv46_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
- u32 pitch, u32 flags, struct nouveau_fb_tile *);
+int nv44_fb_init(struct nvkm_object *);
+void nv44_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
+void nv46_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
+ u32 pitch, u32 flags, struct nvkm_fb_tile *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c
index ffb7ec6d97aa..f3530e4a6760 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c
@@ -23,12 +23,11 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
void
-nv10_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
- u32 flags, struct nouveau_fb_tile *tile)
+nv10_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
+ u32 flags, struct nvkm_fb_tile *tile)
{
tile->addr = 0x80000000 | addr;
tile->limit = max(1u, addr + size) - 1;
@@ -36,7 +35,7 @@ nv10_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
}
void
-nv10_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
+nv10_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
{
tile->addr = 0;
tile->limit = 0;
@@ -45,7 +44,7 @@ nv10_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
}
void
-nv10_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
+nv10_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
{
nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
@@ -53,14 +52,14 @@ nv10_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
nv_rd32(pfb, 0x100240 + (i * 0x10));
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv10_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x10),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
- .init = _nouveau_fb_init,
- .fini = _nouveau_fb_fini,
+ .dtor = _nvkm_fb_dtor,
+ .init = _nvkm_fb_init,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv10_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c
index 265d1253624a..83bcb73caf0a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c
@@ -23,17 +23,16 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
-struct nouveau_oclass *
+struct nvkm_oclass *
nv1a_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x1a),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
- .init = _nouveau_fb_init,
- .fini = _nouveau_fb_fini,
+ .dtor = _nvkm_fb_dtor,
+ .init = _nvkm_fb_init,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv1a_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c
index 2209ade63339..e37084b8d05e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c
@@ -23,12 +23,11 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
void
-nv20_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
- u32 flags, struct nouveau_fb_tile *tile)
+nv20_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
+ u32 flags, struct nvkm_fb_tile *tile)
{
tile->addr = 0x00000001 | addr;
tile->limit = max(1u, addr + size) - 1;
@@ -40,12 +39,12 @@ nv20_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
}
static void
-nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
- struct nouveau_fb_tile *tile)
+nv20_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
+ struct nvkm_fb_tile *tile)
{
u32 tiles = DIV_ROUND_UP(size, 0x40);
u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
- if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
+ if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */
else tile->zcomp = 0x04000000; /* Z24S8 */
tile->zcomp |= tile->tag->offset;
@@ -57,17 +56,17 @@ nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
}
void
-nv20_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
+nv20_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
{
tile->addr = 0;
tile->limit = 0;
tile->pitch = 0;
tile->zcomp = 0;
- nouveau_mm_free(&pfb->tags, &tile->tag);
+ nvkm_mm_free(&pfb->tags, &tile->tag);
}
void
-nv20_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
+nv20_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
{
nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
@@ -76,14 +75,14 @@ nv20_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
nv_wr32(pfb, 0x100300 + (i * 0x04), tile->zcomp);
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv20_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x20),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
- .init = _nouveau_fb_init,
- .fini = _nouveau_fb_fini,
+ .dtor = _nvkm_fb_dtor,
+ .init = _nvkm_fb_init,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv20_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c
index e2a66c355c50..bc9f54f38fba 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c
@@ -23,16 +23,15 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
static void
-nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
- struct nouveau_fb_tile *tile)
+nv25_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
+ struct nvkm_fb_tile *tile)
{
u32 tiles = DIV_ROUND_UP(size, 0x40);
u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
- if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
+ if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */
else tile->zcomp = 0x00200000; /* Z24S8 */
tile->zcomp |= tile->tag->offset;
@@ -42,14 +41,14 @@ nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
}
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv25_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x25),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
- .init = _nouveau_fb_init,
- .fini = _nouveau_fb_fini,
+ .dtor = _nvkm_fb_dtor,
+ .init = _nvkm_fb_init,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv20_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
index cbec402ba5b9..6c0b82f35d94 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
@@ -23,12 +23,11 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
void
-nv30_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
- u32 flags, struct nouveau_fb_tile *tile)
+nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
+ u32 flags, struct nvkm_fb_tile *tile)
{
/* for performance, select alternate bank offset for zeta */
if (!(flags & 4)) {
@@ -46,12 +45,12 @@ nv30_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
}
static void
-nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
- struct nouveau_fb_tile *tile)
+nv30_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
+ struct nvkm_fb_tile *tile)
{
u32 tiles = DIV_ROUND_UP(size, 0x40);
u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
- if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
+ if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */
else tile->zcomp |= 0x02000000; /* Z24S8 */
tile->zcomp |= ((tile->tag->offset ) >> 6);
@@ -65,7 +64,7 @@ nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
static int
calc_bias(struct nv04_fb_priv *priv, int k, int i, int j)
{
- struct nouveau_device *device = nv_device(priv);
+ struct nvkm_device *device = nv_device(priv);
int b = (device->chipset > 0x30 ?
nv_rd32(priv, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) :
0) & 0xf;
@@ -88,13 +87,13 @@ calc_ref(struct nv04_fb_priv *priv, int l, int k, int i)
}
int
-nv30_fb_init(struct nouveau_object *object)
+nv30_fb_init(struct nvkm_object *object)
{
- struct nouveau_device *device = nv_device(object);
+ struct nvkm_device *device = nv_device(object);
struct nv04_fb_priv *priv = (void *)object;
int ret, i, j;
- ret = nouveau_fb_init(&priv->base);
+ ret = nvkm_fb_init(&priv->base);
if (ret)
return ret;
@@ -120,14 +119,14 @@ nv30_fb_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv30_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x30),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
+ .dtor = _nvkm_fb_dtor,
.init = nv30_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv20_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c
index b2cf8c69fb2e..c01dc1839ea4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c
@@ -23,16 +23,15 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
static void
-nv35_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
- struct nouveau_fb_tile *tile)
+nv35_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
+ struct nvkm_fb_tile *tile)
{
u32 tiles = DIV_ROUND_UP(size, 0x40);
u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
- if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
+ if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */
else tile->zcomp |= 0x08000000; /* Z24S8 */
tile->zcomp |= ((tile->tag->offset ) >> 6);
@@ -43,14 +42,14 @@ nv35_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
}
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv35_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x35),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
+ .dtor = _nvkm_fb_dtor,
.init = nv30_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv20_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c
index b4cdae2a3b2f..cad75a1cef22 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c
@@ -23,16 +23,15 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
static void
-nv36_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
- struct nouveau_fb_tile *tile)
+nv36_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
+ struct nvkm_fb_tile *tile)
{
u32 tiles = DIV_ROUND_UP(size, 0x40);
u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
- if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
+ if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */
else tile->zcomp |= 0x20000000; /* Z24S8 */
tile->zcomp |= ((tile->tag->offset ) >> 6);
@@ -43,14 +42,14 @@ nv36_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
}
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv36_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x36),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
+ .dtor = _nvkm_fb_dtor,
.init = nv30_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv20_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c
index 52814258c212..dbe5c1910c2c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c
@@ -23,17 +23,16 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
void
-nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
- struct nouveau_fb_tile *tile)
+nv40_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
+ struct nvkm_fb_tile *tile)
{
u32 tiles = DIV_ROUND_UP(size, 0x80);
u32 tags = round_up(tiles / pfb->ram->parts, 0x100);
if ( (flags & 2) &&
- !nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
+ !nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */
tile->zcomp |= ((tile->tag->offset ) >> 8);
tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13;
@@ -44,12 +43,12 @@ nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
}
static int
-nv40_fb_init(struct nouveau_object *object)
+nv40_fb_init(struct nvkm_object *object)
{
struct nv04_fb_priv *priv = (void *)object;
int ret;
- ret = nouveau_fb_init(&priv->base);
+ ret = nvkm_fb_init(&priv->base);
if (ret)
return ret;
@@ -57,14 +56,14 @@ nv40_fb_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv40_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x40),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
+ .dtor = _nvkm_fb_dtor,
.init = nv40_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv40_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h
index 581f808527f2..602182661820 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h
@@ -1,17 +1,14 @@
#ifndef __NVKM_FB_NV40_H__
#define __NVKM_FB_NV40_H__
-
#include "priv.h"
struct nv40_ram {
- struct nouveau_ram base;
+ struct nvkm_ram base;
u32 ctrl;
u32 coef;
};
-
-int nv40_ram_calc(struct nouveau_fb *, u32);
-int nv40_ram_prog(struct nouveau_fb *);
-void nv40_ram_tidy(struct nouveau_fb *);
-
+int nv40_ram_calc(struct nvkm_fb *, u32);
+int nv40_ram_prog(struct nvkm_fb *);
+void nv40_ram_tidy(struct nvkm_fb *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c
index b239a8615599..d9e1a40a2955 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c
@@ -23,11 +23,10 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
void
-nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
+nv41_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
{
nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
@@ -37,12 +36,12 @@ nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
}
int
-nv41_fb_init(struct nouveau_object *object)
+nv41_fb_init(struct nvkm_object *object)
{
struct nv04_fb_priv *priv = (void *)object;
int ret;
- ret = nouveau_fb_init(&priv->base);
+ ret = nvkm_fb_init(&priv->base);
if (ret)
return ret;
@@ -50,14 +49,14 @@ nv41_fb_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv41_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x41),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
+ .dtor = _nvkm_fb_dtor,
.init = nv41_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv41_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c
index d8478208a681..20b97c83c4af 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c
@@ -23,12 +23,11 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
static void
-nv44_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
- u32 flags, struct nouveau_fb_tile *tile)
+nv44_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
+ u32 flags, struct nvkm_fb_tile *tile)
{
tile->addr = 0x00000001; /* mode = vram */
tile->addr |= addr;
@@ -37,7 +36,7 @@ nv44_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
}
void
-nv44_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
+nv44_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
{
nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
@@ -46,12 +45,12 @@ nv44_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
}
int
-nv44_fb_init(struct nouveau_object *object)
+nv44_fb_init(struct nvkm_object *object)
{
struct nv04_fb_priv *priv = (void *)object;
int ret;
- ret = nouveau_fb_init(&priv->base);
+ ret = nvkm_fb_init(&priv->base);
if (ret)
return ret;
@@ -60,14 +59,14 @@ nv44_fb_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv44_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x44),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
+ .dtor = _nvkm_fb_dtor,
.init = nv44_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv44_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c
index a5b77514d35b..5bfac38cdf24 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c
@@ -23,12 +23,11 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
void
-nv46_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
- u32 flags, struct nouveau_fb_tile *tile)
+nv46_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
+ u32 flags, struct nvkm_fb_tile *tile)
{
/* for performance, select alternate bank offset for zeta */
if (!(flags & 4)) tile->addr = (0 << 3);
@@ -40,14 +39,14 @@ nv46_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
tile->pitch = pitch;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv46_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x46),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
+ .dtor = _nvkm_fb_dtor,
.init = nv44_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv44_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c
index 3bea142376bc..d3b3988d1d49 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c
@@ -23,17 +23,16 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
-struct nouveau_oclass *
+struct nvkm_oclass *
nv47_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x47),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
+ .dtor = _nvkm_fb_dtor,
.init = nv41_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv41_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c
index 666cbd5d47f5..236e36c5054e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c
@@ -23,17 +23,16 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
-struct nouveau_oclass *
+struct nvkm_oclass *
nv49_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x49),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
+ .dtor = _nvkm_fb_dtor,
.init = nv41_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv49_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c
index 42e64f364ec1..1352b6a73fb0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c
@@ -23,17 +23,16 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "nv04.h"
-struct nouveau_oclass *
+struct nvkm_oclass *
nv4e_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x4e),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
- .dtor = _nouveau_fb_dtor,
+ .dtor = _nvkm_fb_dtor,
.init = nv44_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv4e_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
index 962273e3e008..48fd5a5bcd3c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
@@ -21,15 +21,11 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
#include <core/client.h>
-#include <core/enum.h>
#include <core/engctx.h>
-#include <core/object.h>
-
-#include <subdev/bios.h>
-
-#include "nv50.h"
+#include <core/enum.h>
int
nv50_fb_memtype[0x80] = {
@@ -44,12 +40,12 @@ nv50_fb_memtype[0x80] = {
};
bool
-nv50_fb_memtype_valid(struct nouveau_fb *pfb, u32 memtype)
+nv50_fb_memtype_valid(struct nvkm_fb *pfb, u32 memtype)
{
return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0;
}
-static const struct nouveau_enum vm_dispatch_subclients[] = {
+static const struct nvkm_enum vm_dispatch_subclients[] = {
{ 0x00000000, "GRCTX", NULL },
{ 0x00000001, "NOTIFY", NULL },
{ 0x00000002, "QUERY", NULL },
@@ -60,14 +56,14 @@ static const struct nouveau_enum vm_dispatch_subclients[] = {
{}
};
-static const struct nouveau_enum vm_ccache_subclients[] = {
+static const struct nvkm_enum vm_ccache_subclients[] = {
{ 0x00000000, "CB", NULL },
{ 0x00000001, "TIC", NULL },
{ 0x00000002, "TSC", NULL },
{}
};
-static const struct nouveau_enum vm_prop_subclients[] = {
+static const struct nvkm_enum vm_prop_subclients[] = {
{ 0x00000000, "RT0", NULL },
{ 0x00000001, "RT1", NULL },
{ 0x00000002, "RT2", NULL },
@@ -84,19 +80,19 @@ static const struct nouveau_enum vm_prop_subclients[] = {
{}
};
-static const struct nouveau_enum vm_pfifo_subclients[] = {
+static const struct nvkm_enum vm_pfifo_subclients[] = {
{ 0x00000000, "PUSHBUF", NULL },
{ 0x00000001, "SEMAPHORE", NULL },
{}
};
-static const struct nouveau_enum vm_bar_subclients[] = {
+static const struct nvkm_enum vm_bar_subclients[] = {
{ 0x00000000, "FB", NULL },
{ 0x00000001, "IN", NULL },
{}
};
-static const struct nouveau_enum vm_client[] = {
+static const struct nvkm_enum vm_client[] = {
{ 0x00000000, "STRMOUT", NULL },
{ 0x00000003, "DISPATCH", vm_dispatch_subclients },
{ 0x00000004, "PFIFO_WRITE", NULL },
@@ -115,7 +111,7 @@ static const struct nouveau_enum vm_client[] = {
{}
};
-static const struct nouveau_enum vm_engine[] = {
+static const struct nvkm_enum vm_engine[] = {
{ 0x00000000, "PGRAPH", NULL, NVDEV_ENGINE_GR },
{ 0x00000001, "PVP", NULL, NVDEV_ENGINE_VP },
{ 0x00000004, "PEEPHOLE", NULL },
@@ -132,7 +128,7 @@ static const struct nouveau_enum vm_engine[] = {
{}
};
-static const struct nouveau_enum vm_fault[] = {
+static const struct nvkm_enum vm_fault[] = {
{ 0x00000000, "PT_NOT_PRESENT", NULL },
{ 0x00000001, "PT_TOO_SHORT", NULL },
{ 0x00000002, "PAGE_NOT_PRESENT", NULL },
@@ -146,13 +142,13 @@ static const struct nouveau_enum vm_fault[] = {
};
static void
-nv50_fb_intr(struct nouveau_subdev *subdev)
+nv50_fb_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_device *device = nv_device(subdev);
- struct nouveau_engine *engine;
+ struct nvkm_device *device = nv_device(subdev);
+ struct nvkm_engine *engine;
struct nv50_fb_priv *priv = (void *)subdev;
- const struct nouveau_enum *en, *cl;
- struct nouveau_object *engctx = NULL;
+ const struct nvkm_enum *en, *cl;
+ struct nvkm_object *engctx = NULL;
u32 trap[6], idx, chan;
u8 st0, st1, st2, st3;
int i;
@@ -183,21 +179,21 @@ nv50_fb_intr(struct nouveau_subdev *subdev)
}
chan = (trap[2] << 16) | trap[1];
- en = nouveau_enum_find(vm_engine, st0);
+ en = nvkm_enum_find(vm_engine, st0);
if (en && en->data2) {
- const struct nouveau_enum *orig_en = en;
+ const struct nvkm_enum *orig_en = en;
while (en->name && en->value == st0 && en->data2) {
- engine = nouveau_engine(subdev, en->data2);
+ engine = nvkm_engine(subdev, en->data2);
/*XXX: clean this up */
if (!engine && en->data2 == NVDEV_ENGINE_BSP)
- engine = nouveau_engine(subdev, NVDEV_ENGINE_MSVLD);
+ engine = nvkm_engine(subdev, NVDEV_ENGINE_MSVLD);
if (!engine && en->data2 == NVDEV_ENGINE_CIPHER)
- engine = nouveau_engine(subdev, NVDEV_ENGINE_SEC);
+ engine = nvkm_engine(subdev, NVDEV_ENGINE_SEC);
if (!engine && en->data2 == NVDEV_ENGINE_VP)
- engine = nouveau_engine(subdev, NVDEV_ENGINE_MSPDEC);
+ engine = nvkm_engine(subdev, NVDEV_ENGINE_MSPDEC);
if (engine) {
- engctx = nouveau_engctx_get(engine, chan);
+ engctx = nvkm_engctx_get(engine, chan);
if (engctx)
break;
}
@@ -210,23 +206,23 @@ nv50_fb_intr(struct nouveau_subdev *subdev)
nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ",
(trap[5] & 0x00000100) ? "read" : "write",
trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan,
- nouveau_client_name(engctx));
+ nvkm_client_name(engctx));
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
if (en)
pr_cont("%s/", en->name);
else
pr_cont("%02x/", st0);
- cl = nouveau_enum_find(vm_client, st2);
+ cl = nvkm_enum_find(vm_client, st2);
if (cl)
pr_cont("%s/", cl->name);
else
pr_cont("%02x/", st2);
- if (cl && cl->data) cl = nouveau_enum_find(cl->data, st3);
- else if (en && en->data) cl = nouveau_enum_find(en->data, st3);
+ if (cl && cl->data) cl = nvkm_enum_find(cl->data, st3);
+ else if (en && en->data) cl = nvkm_enum_find(en->data, st3);
else cl = NULL;
if (cl)
pr_cont("%s", cl->name);
@@ -234,7 +230,7 @@ nv50_fb_intr(struct nouveau_subdev *subdev)
pr_cont("%02x", st3);
pr_cont(" reason: ");
- en = nouveau_enum_find(vm_fault, st1);
+ en = nvkm_enum_find(vm_fault, st1);
if (en)
pr_cont("%s\n", en->name);
else
@@ -242,15 +238,15 @@ nv50_fb_intr(struct nouveau_subdev *subdev)
}
int
-nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_device *device = nv_device(parent);
+ struct nvkm_device *device = nv_device(parent);
struct nv50_fb_priv *priv;
int ret;
- ret = nouveau_fb_create(parent, engine, oclass, &priv);
+ ret = nvkm_fb_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -271,9 +267,9 @@ nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
void
-nv50_fb_dtor(struct nouveau_object *object)
+nv50_fb_dtor(struct nvkm_object *object)
{
- struct nouveau_device *device = nv_device(object);
+ struct nvkm_device *device = nv_device(object);
struct nv50_fb_priv *priv = (void *)object;
if (priv->r100c08_page) {
@@ -282,17 +278,17 @@ nv50_fb_dtor(struct nouveau_object *object)
__free_page(priv->r100c08_page);
}
- nouveau_fb_destroy(&priv->base);
+ nvkm_fb_destroy(&priv->base);
}
int
-nv50_fb_init(struct nouveau_object *object)
+nv50_fb_init(struct nvkm_object *object)
{
struct nv50_fb_impl *impl = (void *)object->oclass;
struct nv50_fb_priv *priv = (void *)object;
int ret;
- ret = nouveau_fb_init(&priv->base);
+ ret = nvkm_fb_init(&priv->base);
if (ret)
return ret;
@@ -308,14 +304,14 @@ nv50_fb_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv50_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x50),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
- .fini = _nouveau_fb_fini,
+ .fini = _nvkm_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
.base.ram = &nv50_ram_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h
index c5e5a888c607..f3cde3f1f511 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h
@@ -1,33 +1,31 @@
#ifndef __NVKM_FB_NV50_H__
#define __NVKM_FB_NV50_H__
-
#include "priv.h"
struct nv50_fb_priv {
- struct nouveau_fb base;
+ struct nvkm_fb base;
struct page *r100c08_page;
dma_addr_t r100c08;
};
-int nv50_fb_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nv50_fb_dtor(struct nouveau_object *);
-int nv50_fb_init(struct nouveau_object *);
+int nv50_fb_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void nv50_fb_dtor(struct nvkm_object *);
+int nv50_fb_init(struct nvkm_object *);
struct nv50_fb_impl {
- struct nouveau_fb_impl base;
+ struct nvkm_fb_impl base;
u32 trap;
};
#define nv50_ram_create(p,e,o,d) \
nv50_ram_create_((p), (e), (o), sizeof(**d), (void **)d)
-int nv50_ram_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-int nv50_ram_get(struct nouveau_fb *, u64 size, u32 align, u32 ncmin,
- u32 memtype, struct nouveau_mem **);
-void nv50_ram_put(struct nouveau_fb *, struct nouveau_mem **);
-void __nv50_ram_put(struct nouveau_fb *, struct nouveau_mem *);
+int nv50_ram_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+int nv50_ram_get(struct nvkm_fb *, u64 size, u32 align, u32 ncmin,
+ u32 memtype, struct nvkm_mem **);
+void nv50_ram_put(struct nvkm_fb *, struct nvkm_mem **);
+void __nv50_ram_put(struct nvkm_fb *, struct nvkm_mem *);
extern int nv50_fb_memtype[0x80];
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.h
deleted file mode 100644
index 705a06d755ad..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __NVKM_RAM_NVC0_H__
-#define __NVKM_RAM_NVC0_H__
-
-#include "priv.h"
-#include "nv50.h"
-
-struct nvc0_fb_priv {
- struct nouveau_fb base;
- struct page *r100c10_page;
- dma_addr_t r100c10;
-};
-
-int nvc0_fb_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nvc0_fb_dtor(struct nouveau_object *);
-int nvc0_fb_init(struct nouveau_object *);
-bool nvc0_fb_memtype_valid(struct nouveau_fb *, u32);
-
-
-#define nvc0_ram_create(p,e,o,m,d) \
- nvc0_ram_create_((p), (e), (o), (m), sizeof(**d), (void **)d)
-int nvc0_ram_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, u32, int, void **);
-int nvc0_ram_get(struct nouveau_fb *, u64, u32, u32, u32,
- struct nouveau_mem **);
-void nvc0_ram_put(struct nouveau_fb *, struct nouveau_mem **);
-
-int nve0_ram_init(struct nouveau_object*);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
index 283863f7aa9b..d82da02daa1f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
@@ -1,76 +1,74 @@
#ifndef __NVKM_FB_PRIV_H__
#define __NVKM_FB_PRIV_H__
-
#include <subdev/fb.h>
+struct nvkm_bios;
-#define nouveau_ram_create(p,e,o,d) \
- nouveau_object_create_((p), (e), (o), 0, sizeof(**d), (void **)d)
-#define nouveau_ram_destroy(p) \
- nouveau_object_destroy(&(p)->base)
-#define nouveau_ram_init(p) \
- nouveau_object_init(&(p)->base)
-#define nouveau_ram_fini(p,s) \
- nouveau_object_fini(&(p)->base, (s))
+#define nvkm_ram_create(p,e,o,d) \
+ nvkm_object_create_((p), (e), (o), 0, sizeof(**d), (void **)d)
+#define nvkm_ram_destroy(p) \
+ nvkm_object_destroy(&(p)->base)
+#define nvkm_ram_init(p) \
+ nvkm_object_init(&(p)->base)
+#define nvkm_ram_fini(p,s) \
+ nvkm_object_fini(&(p)->base, (s))
-#define nouveau_ram_create_(p,e,o,s,d) \
- nouveau_object_create_((p), (e), (o), 0, (s), (void **)d)
-#define _nouveau_ram_dtor nouveau_object_destroy
-#define _nouveau_ram_init nouveau_object_init
-#define _nouveau_ram_fini nouveau_object_fini
+#define nvkm_ram_create_(p,e,o,s,d) \
+ nvkm_object_create_((p), (e), (o), 0, (s), (void **)d)
+#define _nvkm_ram_dtor nvkm_object_destroy
+#define _nvkm_ram_init nvkm_object_init
+#define _nvkm_ram_fini nvkm_object_fini
-extern struct nouveau_oclass nv04_ram_oclass;
-extern struct nouveau_oclass nv10_ram_oclass;
-extern struct nouveau_oclass nv1a_ram_oclass;
-extern struct nouveau_oclass nv20_ram_oclass;
-extern struct nouveau_oclass nv40_ram_oclass;
-extern struct nouveau_oclass nv41_ram_oclass;
-extern struct nouveau_oclass nv44_ram_oclass;
-extern struct nouveau_oclass nv49_ram_oclass;
-extern struct nouveau_oclass nv4e_ram_oclass;
-extern struct nouveau_oclass nv50_ram_oclass;
-extern struct nouveau_oclass nva3_ram_oclass;
-extern struct nouveau_oclass nvaa_ram_oclass;
-extern struct nouveau_oclass nvc0_ram_oclass;
-extern struct nouveau_oclass nve0_ram_oclass;
-extern struct nouveau_oclass gk20a_ram_oclass;
-extern struct nouveau_oclass gm107_ram_oclass;
+extern struct nvkm_oclass nv04_ram_oclass;
+extern struct nvkm_oclass nv10_ram_oclass;
+extern struct nvkm_oclass nv1a_ram_oclass;
+extern struct nvkm_oclass nv20_ram_oclass;
+extern struct nvkm_oclass nv40_ram_oclass;
+extern struct nvkm_oclass nv41_ram_oclass;
+extern struct nvkm_oclass nv44_ram_oclass;
+extern struct nvkm_oclass nv49_ram_oclass;
+extern struct nvkm_oclass nv4e_ram_oclass;
+extern struct nvkm_oclass nv50_ram_oclass;
+extern struct nvkm_oclass gt215_ram_oclass;
+extern struct nvkm_oclass mcp77_ram_oclass;
+extern struct nvkm_oclass gf100_ram_oclass;
+extern struct nvkm_oclass gk104_ram_oclass;
+extern struct nvkm_oclass gk20a_ram_oclass;
+extern struct nvkm_oclass gm107_ram_oclass;
-int nouveau_sddr2_calc(struct nouveau_ram *ram);
-int nouveau_sddr3_calc(struct nouveau_ram *ram);
-int nouveau_gddr3_calc(struct nouveau_ram *ram);
-int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts);
+int nvkm_sddr2_calc(struct nvkm_ram *ram);
+int nvkm_sddr3_calc(struct nvkm_ram *ram);
+int nvkm_gddr3_calc(struct nvkm_ram *ram);
+int nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts);
-#define nouveau_fb_create(p,e,c,d) \
- nouveau_fb_create_((p), (e), (c), sizeof(**d), (void **)d)
-#define nouveau_fb_destroy(p) ({ \
- struct nouveau_fb *pfb = (p); \
- _nouveau_fb_dtor(nv_object(pfb)); \
+#define nvkm_fb_create(p,e,c,d) \
+ nvkm_fb_create_((p), (e), (c), sizeof(**d), (void **)d)
+#define nvkm_fb_destroy(p) ({ \
+ struct nvkm_fb *pfb = (p); \
+ _nvkm_fb_dtor(nv_object(pfb)); \
})
-#define nouveau_fb_init(p) ({ \
- struct nouveau_fb *pfb = (p); \
- _nouveau_fb_init(nv_object(pfb)); \
+#define nvkm_fb_init(p) ({ \
+ struct nvkm_fb *pfb = (p); \
+ _nvkm_fb_init(nv_object(pfb)); \
})
-#define nouveau_fb_fini(p,s) ({ \
- struct nouveau_fb *pfb = (p); \
- _nouveau_fb_fini(nv_object(pfb), (s)); \
+#define nvkm_fb_fini(p,s) ({ \
+ struct nvkm_fb *pfb = (p); \
+ _nvkm_fb_fini(nv_object(pfb), (s)); \
})
-int nouveau_fb_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-void _nouveau_fb_dtor(struct nouveau_object *);
-int _nouveau_fb_init(struct nouveau_object *);
-int _nouveau_fb_fini(struct nouveau_object *, bool);
+int nvkm_fb_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+void _nvkm_fb_dtor(struct nvkm_object *);
+int _nvkm_fb_init(struct nvkm_object *);
+int _nvkm_fb_fini(struct nvkm_object *, bool);
-struct nouveau_fb_impl {
- struct nouveau_oclass base;
- struct nouveau_oclass *ram;
- bool (*memtype)(struct nouveau_fb *, u32);
+struct nvkm_fb_impl {
+ struct nvkm_oclass base;
+ struct nvkm_oclass *ram;
+ bool (*memtype)(struct nvkm_fb *, u32);
};
-bool nv04_fb_memtype_valid(struct nouveau_fb *, u32 memtype);
-bool nv50_fb_memtype_valid(struct nouveau_fb *, u32 memtype);
-
-struct nouveau_bios;
-int nouveau_fb_bios_memtype(struct nouveau_bios *);
+bool nv04_fb_memtype_valid(struct nvkm_fb *, u32 memtype);
+bool nv50_fb_memtype_valid(struct nvkm_fb *, u32 memtype);
+int nvkm_fb_bios_memtype(struct nvkm_bios *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h
index f641f3abd4f3..f343682b1387 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h
@@ -1,11 +1,10 @@
#ifndef __NVKM_FBRAM_FUC_H__
#define __NVKM_FBRAM_FUC_H__
-
#include <subdev/pmu.h>
struct ramfuc {
- struct nouveau_memx *memx;
- struct nouveau_fb *pfb;
+ struct nvkm_memx *memx;
+ struct nvkm_fb *pfb;
int sequence;
};
@@ -55,12 +54,12 @@ ramfuc_reg(u32 addr)
}
static inline int
-ramfuc_init(struct ramfuc *ram, struct nouveau_fb *pfb)
+ramfuc_init(struct ramfuc *ram, struct nvkm_fb *pfb)
{
- struct nouveau_pmu *pmu = nouveau_pmu(pfb);
+ struct nvkm_pmu *pmu = nvkm_pmu(pfb);
int ret;
- ret = nouveau_memx_init(pmu, &ram->memx);
+ ret = nvkm_memx_init(pmu, &ram->memx);
if (ret)
return ret;
@@ -74,7 +73,7 @@ ramfuc_exec(struct ramfuc *ram, bool exec)
{
int ret = 0;
if (ram->pfb) {
- ret = nouveau_memx_fini(&ram->memx, exec);
+ ret = nvkm_memx_fini(&ram->memx, exec);
ram->pfb = NULL;
}
return ret;
@@ -97,10 +96,8 @@ ramfuc_wr32(struct ramfuc *ram, struct ramfuc_reg *reg, u32 data)
reg->data = data;
for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) {
- if (mask & 1) {
- nouveau_memx_wr32(ram->memx, reg->addr+off, reg->data);
- }
-
+ if (mask & 1)
+ nvkm_memx_wr32(ram->memx, reg->addr+off, reg->data);
off += reg->stride;
}
}
@@ -125,45 +122,45 @@ ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data)
static inline void
ramfuc_wait(struct ramfuc *ram, u32 addr, u32 mask, u32 data, u32 nsec)
{
- nouveau_memx_wait(ram->memx, addr, mask, data, nsec);
+ nvkm_memx_wait(ram->memx, addr, mask, data, nsec);
}
static inline void
ramfuc_nsec(struct ramfuc *ram, u32 nsec)
{
- nouveau_memx_nsec(ram->memx, nsec);
+ nvkm_memx_nsec(ram->memx, nsec);
}
static inline void
ramfuc_wait_vblank(struct ramfuc *ram)
{
- nouveau_memx_wait_vblank(ram->memx);
+ nvkm_memx_wait_vblank(ram->memx);
}
static inline void
ramfuc_train(struct ramfuc *ram)
{
- nouveau_memx_train(ram->memx);
+ nvkm_memx_train(ram->memx);
}
static inline int
-ramfuc_train_result(struct nouveau_fb *pfb, u32 *result, u32 rsize)
+ramfuc_train_result(struct nvkm_fb *pfb, u32 *result, u32 rsize)
{
- struct nouveau_pmu *pmu = nouveau_pmu(pfb);
+ struct nvkm_pmu *pmu = nvkm_pmu(pfb);
- return nouveau_memx_train_result(pmu, result, rsize);
+ return nvkm_memx_train_result(pmu, result, rsize);
}
static inline void
ramfuc_block(struct ramfuc *ram)
{
- nouveau_memx_block(ram->memx);
+ nvkm_memx_block(ram->memx);
}
static inline void
ramfuc_unblock(struct ramfuc *ram)
{
- nouveau_memx_unblock(ram->memx);
+ nvkm_memx_unblock(ram->memx);
}
#define ram_init(s,p) ramfuc_init(&(s)->base, (p))
@@ -180,5 +177,4 @@ ramfuc_unblock(struct ramfuc *ram)
#define ram_train_result(s,r,l) ramfuc_train_result((s), (r), (l))
#define ram_block(s) ramfuc_block(&(s)->base)
#define ram_unblock(s) ramfuc_unblock(&(s)->base)
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
similarity index 83%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
index d08eacd580d4..dcb175bea84b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
@@ -21,23 +21,19 @@
*
* Authors: Ben Skeggs
*/
+#include "gf100.h"
+#include "ramfuc.h"
+#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/bios/rammap.h>
#include <subdev/bios/timing.h>
-#include <subdev/ltc.h>
-
#include <subdev/clk.h>
#include <subdev/clk/pll.h>
+#include <subdev/ltc.h>
-#include <core/option.h>
-
-#include "ramfuc.h"
-
-#include "nvc0.h"
-
-struct nvc0_ramfuc {
+struct gf100_ramfuc {
struct ramfuc base;
struct ramfuc_reg r_0x10fe20;
@@ -100,18 +96,18 @@ struct nvc0_ramfuc {
struct ramfuc_reg r_0x13d8f4;
};
-struct nvc0_ram {
- struct nouveau_ram base;
- struct nvc0_ramfuc fuc;
+struct gf100_ram {
+ struct nvkm_ram base;
+ struct gf100_ramfuc fuc;
struct nvbios_pll refpll;
struct nvbios_pll mempll;
};
static void
-nvc0_ram_train(struct nvc0_ramfuc *fuc, u32 magic)
+gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic)
{
- struct nvc0_ram *ram = container_of(fuc, typeof(*ram), fuc);
- struct nouveau_fb *pfb = nouveau_fb(ram);
+ struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc);
+ struct nvkm_fb *pfb = nvkm_fb(ram);
u32 part = nv_rd32(pfb, 0x022438), i;
u32 mask = nv_rd32(pfb, 0x022554);
u32 addr = 0x110974;
@@ -127,12 +123,12 @@ nvc0_ram_train(struct nvc0_ramfuc *fuc, u32 magic)
}
static int
-nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
+gf100_ram_calc(struct nvkm_fb *pfb, u32 freq)
{
- struct nouveau_clk *clk = nouveau_clk(pfb);
- struct nouveau_bios *bios = nouveau_bios(pfb);
- struct nvc0_ram *ram = (void *)pfb->ram;
- struct nvc0_ramfuc *fuc = &ram->fuc;
+ struct nvkm_clk *clk = nvkm_clk(pfb);
+ struct nvkm_bios *bios = nvkm_bios(pfb);
+ struct gf100_ram *ram = (void *)pfb->ram;
+ struct gf100_ramfuc *fuc = &ram->fuc;
struct nvbios_ramcfg cfg;
u8 ver, cnt, len, strap;
struct {
@@ -146,7 +142,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
/* lookup memory config data relevant to the target frequency */
rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
- &cnt, &ramcfg.size, &cfg);
+ &cnt, &ramcfg.size, &cfg);
if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
nv_error(pfb, "invalid/missing rammap entry\n");
return -EINVAL;
@@ -169,7 +165,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
strap = nv_ro08(bios, ramcfg.data + 0x01);
if (strap != 0xff) {
timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
- &cnt, &len);
+ &cnt, &len);
if (!timing.data || ver != 0x10 || timing.size < 0x19) {
nv_error(pfb, "invalid/missing timing entry\n");
return -EINVAL;
@@ -213,8 +209,8 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
if (mode == 1 && from == 0) {
/* calculate refpll */
- ret = nva3_pll_calc(nv_subdev(pfb), &ram->refpll,
- ram->mempll.refclk, &N1, NULL, &M1, &P);
+ ret = gt215_pll_calc(nv_subdev(pfb), &ram->refpll,
+ ram->mempll.refclk, &N1, NULL, &M1, &P);
if (ret <= 0) {
nv_error(pfb, "unable to calc refpll\n");
return ret ? ret : -ERANGE;
@@ -228,8 +224,8 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
/* calculate mempll */
- ret = nva3_pll_calc(nv_subdev(pfb), &ram->mempll, freq,
- &N1, NULL, &M1, &P);
+ ret = gt215_pll_calc(nv_subdev(pfb), &ram->mempll, freq,
+ &N1, NULL, &M1, &P);
if (ret <= 0) {
nv_error(pfb, "unable to calc refpll\n");
return ret ? ret : -ERANGE;
@@ -277,7 +273,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
ram_wr32(fuc, 0x10f210, 0x00000000);
ram_nsec(fuc, 1000);
if (mode == 0)
- nvc0_ram_train(fuc, 0x000c1001);
+ gf100_ram_train(fuc, 0x000c1001);
ram_wr32(fuc, 0x10f310, 0x00000001);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f090, 0x00000061);
@@ -325,8 +321,8 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
ram_wr32(fuc, 0x10f348, 0x00700008);
ram_wr32(fuc, 0x61c140, 0x19240000);
ram_wr32(fuc, 0x10f830, 0x00300017);
- nvc0_ram_train(fuc, 0x80021001);
- nvc0_ram_train(fuc, 0x80081001);
+ gf100_ram_train(fuc, 0x80021001);
+ gf100_ram_train(fuc, 0x80081001);
ram_wr32(fuc, 0x10f340, 0x00500004);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f830, 0x01300017);
@@ -379,7 +375,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
ram_wr32(fuc, 0x13d8f4, 0x00000000);
ram_wr32(fuc, 0x61c140, 0x09a40000);
- nvc0_ram_train(fuc, 0x800e1008);
+ gf100_ram_train(fuc, 0x800e1008);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f800, 0x00001804);
@@ -392,7 +388,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
ram_wr32(fuc, 0x10f9b0, 0x05313f41);
ram_wr32(fuc, 0x10f9b4, 0x00002f50);
- nvc0_ram_train(fuc, 0x010c1001);
+ gf100_ram_train(fuc, 0x010c1001);
}
ram_mask(fuc, 0x10f200, 0x00000800, 0x00000800);
@@ -400,34 +396,35 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
if (mode == 0)
ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
+
return 0;
}
static int
-nvc0_ram_prog(struct nouveau_fb *pfb)
+gf100_ram_prog(struct nvkm_fb *pfb)
{
- struct nouveau_device *device = nv_device(pfb);
- struct nvc0_ram *ram = (void *)pfb->ram;
- struct nvc0_ramfuc *fuc = &ram->fuc;
- ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", true));
+ struct nvkm_device *device = nv_device(pfb);
+ struct gf100_ram *ram = (void *)pfb->ram;
+ struct gf100_ramfuc *fuc = &ram->fuc;
+ ram_exec(fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", true));
return 0;
}
static void
-nvc0_ram_tidy(struct nouveau_fb *pfb)
+gf100_ram_tidy(struct nvkm_fb *pfb)
{
- struct nvc0_ram *ram = (void *)pfb->ram;
- struct nvc0_ramfuc *fuc = &ram->fuc;
+ struct gf100_ram *ram = (void *)pfb->ram;
+ struct gf100_ramfuc *fuc = &ram->fuc;
ram_exec(fuc, false);
}
-extern const u8 nvc0_pte_storage_type_map[256];
+extern const u8 gf100_pte_storage_type_map[256];
void
-nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
+gf100_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem)
{
- struct nouveau_ltc *ltc = nouveau_ltc(pfb);
- struct nouveau_mem *mem = *pmem;
+ struct nvkm_ltc *ltc = nvkm_ltc(pfb);
+ struct nvkm_mem *mem = *pmem;
*pmem = NULL;
if (unlikely(mem == NULL))
@@ -443,15 +440,15 @@ nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
}
int
-nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
- u32 memtype, struct nouveau_mem **pmem)
+gf100_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin,
+ u32 memtype, struct nvkm_mem **pmem)
{
- struct nouveau_mm *mm = &pfb->vram;
- struct nouveau_mm_node *r;
- struct nouveau_mem *mem;
+ struct nvkm_mm *mm = &pfb->vram;
+ struct nvkm_mm_node *r;
+ struct nvkm_mem *mem;
int type = (memtype & 0x0ff);
int back = (memtype & 0x800);
- const bool comp = nvc0_pte_storage_type_map[type] != type;
+ const bool comp = gf100_pte_storage_type_map[type] != type;
int ret;
size >>= 12;
@@ -469,7 +466,7 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
mutex_lock(&pfb->base.mutex);
if (comp) {
- struct nouveau_ltc *ltc = nouveau_ltc(pfb);
+ struct nvkm_ltc *ltc = nvkm_ltc(pfb);
/* compression only works with lpages */
if (align == (1 << (17 - 12))) {
@@ -478,15 +475,15 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
}
if (unlikely(!mem->tag))
- type = nvc0_pte_storage_type_map[type];
+ type = gf100_pte_storage_type_map[type];
}
mem->memtype = type;
do {
if (back)
- ret = nouveau_mm_tail(mm, 0, 1, size, ncmin, align, &r);
+ ret = nvkm_mm_tail(mm, 0, 1, size, ncmin, align, &r);
else
- ret = nouveau_mm_head(mm, 0, 1, size, ncmin, align, &r);
+ ret = nvkm_mm_head(mm, 0, 1, size, ncmin, align, &r);
if (ret) {
mutex_unlock(&pfb->base.mutex);
pfb->ram->put(pfb, &mem);
@@ -498,20 +495,20 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
} while (size);
mutex_unlock(&pfb->base.mutex);
- r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
+ r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry);
mem->offset = (u64)r->offset << 12;
*pmem = mem;
return 0;
}
int
-nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, u32 maskaddr, int size,
- void **pobject)
+gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, u32 maskaddr, int size,
+ void **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
- struct nouveau_bios *bios = nouveau_bios(pfb);
- struct nouveau_ram *ram;
+ struct nvkm_fb *pfb = nvkm_fb(parent);
+ struct nvkm_bios *bios = nvkm_bios(pfb);
+ struct nvkm_ram *ram;
const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
u32 parts = nv_rd32(pfb, 0x022438);
@@ -521,7 +518,7 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
bool uniform = true;
int ret, part;
- ret = nouveau_ram_create_(parent, engine, oclass, size, pobject);
+ ret = nvkm_ram_create_(parent, engine, oclass, size, pobject);
ram = *pobject;
if (ret)
return ret;
@@ -529,7 +526,7 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
nv_debug(pfb, "0x100800: 0x%08x\n", nv_rd32(pfb, 0x100800));
nv_debug(pfb, "parts 0x%08x mask 0x%08x\n", parts, pmask);
- ram->type = nouveau_fb_bios_memtype(bios);
+ ram->type = nvkm_fb_bios_memtype(bios);
ram->ranks = (nv_rd32(pfb, 0x10f200) & 0x00000004) ? 2 : 1;
/* read amount of vram attached to each memory controller */
@@ -551,11 +548,11 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
if (uniform) {
offset = rsvd_head;
length = (ram->size >> 12) - rsvd_head - rsvd_tail;
- ret = nouveau_mm_init(&pfb->vram, offset, length, 1);
+ ret = nvkm_mm_init(&pfb->vram, offset, length, 1);
} else {
/* otherwise, address lowest common amount from 0GiB */
- ret = nouveau_mm_init(&pfb->vram, rsvd_head,
- (bsize << 8) * parts - rsvd_head, 1);
+ ret = nvkm_mm_init(&pfb->vram, rsvd_head,
+ (bsize << 8) * parts - rsvd_head, 1);
if (ret)
return ret;
@@ -563,27 +560,27 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
offset = (0x0200000000ULL >> 12) + (bsize << 8);
length = (ram->size >> 12) - ((bsize * parts) << 8) - rsvd_tail;
- ret = nouveau_mm_init(&pfb->vram, offset, length, 1);
+ ret = nvkm_mm_init(&pfb->vram, offset, length, 1);
if (ret)
- nouveau_mm_fini(&pfb->vram);
+ nvkm_mm_fini(&pfb->vram);
}
if (ret)
return ret;
- ram->get = nvc0_ram_get;
- ram->put = nvc0_ram_put;
+ ram->get = gf100_ram_get;
+ ram->put = gf100_ram_put;
return 0;
}
static int
-nvc0_ram_init(struct nouveau_object *object)
+gf100_ram_init(struct nvkm_object *object)
{
- struct nouveau_fb *pfb = (void *)object->parent;
- struct nvc0_ram *ram = (void *)object;
+ struct nvkm_fb *pfb = (void *)object->parent;
+ struct gf100_ram *ram = (void *)object;
int ret, i;
- ret = nouveau_ram_init(&ram->base);
+ ret = nvkm_ram_init(&ram->base);
if (ret)
return ret;
@@ -624,15 +621,15 @@ nvc0_ram_init(struct nouveau_object *object)
}
static int
-nvc0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_bios *bios = nouveau_bios(parent);
- struct nvc0_ram *ram;
+ struct nvkm_bios *bios = nvkm_bios(parent);
+ struct gf100_ram *ram;
int ret;
- ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram);
+ ret = gf100_ram_create(parent, engine, oclass, 0x022554, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
@@ -651,9 +648,9 @@ nvc0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
switch (ram->base.type) {
case NV_MEM_TYPE_GDDR5:
- ram->base.calc = nvc0_ram_calc;
- ram->base.prog = nvc0_ram_prog;
- ram->base.tidy = nvc0_ram_tidy;
+ ram->base.calc = gf100_ram_calc;
+ ram->base.prog = gf100_ram_prog;
+ ram->base.tidy = gf100_ram_tidy;
break;
default:
nv_warn(ram, "reclocking of this ram type unsupported\n");
@@ -721,13 +718,13 @@ nvc0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
-nvc0_ram_oclass = {
+struct nvkm_oclass
+gf100_ram_oclass = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_ram_ctor,
- .dtor = _nouveau_ram_dtor,
- .init = nvc0_ram_init,
- .fini = _nouveau_ram_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_ram_ctor,
+ .dtor = _nvkm_ram_dtor,
+ .init = gf100_ram_init,
+ .fini = _nvkm_ram_fini,
}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
similarity index 90%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
index 60050aab84b8..97060ccfb80c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
@@ -21,29 +21,22 @@
*
* Authors: Ben Skeggs
*/
-
-#include <subdev/gpio.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/pll.h>
-#include <subdev/bios/init.h>
-#include <subdev/bios/rammap.h>
-#include <subdev/bios/timing.h>
-#include <subdev/bios/M0205.h>
-#include <subdev/bios/M0209.h>
-
-#include <subdev/clk.h>
-#include <subdev/clk/pll.h>
-
-#include <subdev/timer.h>
+#include "ramfuc.h"
+#include "gf100.h"
#include <core/option.h>
+#include <subdev/bios.h>
+#include <subdev/bios/init.h>
+#include <subdev/bios/M0205.h>
+#include <subdev/bios/M0209.h>
+#include <subdev/bios/pll.h>
+#include <subdev/bios/rammap.h>
+#include <subdev/bios/timing.h>
+#include <subdev/clk.h>
+#include <subdev/clk/pll.h>
+#include <subdev/gpio.h>
-#include "nvc0.h"
-
-#include "ramfuc.h"
-
-struct nve0_ramfuc {
+struct gk104_ramfuc {
struct ramfuc base;
struct nvbios_pll refpll;
@@ -124,9 +117,9 @@ struct nve0_ramfuc {
struct ramfuc_reg r_0x100750;
};
-struct nve0_ram {
- struct nouveau_ram base;
- struct nve0_ramfuc fuc;
+struct gk104_ram {
+ struct nvkm_ram base;
+ struct gk104_ramfuc fuc;
struct list_head cfg;
u32 parts;
@@ -144,9 +137,9 @@ struct nve0_ram {
* GDDR5
******************************************************************************/
static void
-nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data)
+gk104_ram_train(struct gk104_ramfuc *fuc, u32 mask, u32 data)
{
- struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
+ struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
u32 addr = 0x110974, i;
ram_mask(fuc, 0x10f910, mask, data);
@@ -160,9 +153,9 @@ nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data)
}
static void
-r1373f4_init(struct nve0_ramfuc *fuc)
+r1373f4_init(struct gk104_ramfuc *fuc)
{
- struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
+ struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
const u32 runk0 = ram->fN1 << 16;
@@ -210,10 +203,10 @@ r1373f4_init(struct nve0_ramfuc *fuc)
}
static void
-r1373f4_fini(struct nve0_ramfuc *fuc)
+r1373f4_fini(struct gk104_ramfuc *fuc)
{
- struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
- struct nouveau_ram_data *next = ram->base.next;
+ struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
+ struct nvkm_ram_data *next = ram->base.next;
u8 v0 = next->bios.ramcfg_11_03_c0;
u8 v1 = next->bios.ramcfg_11_03_30;
u32 tmp;
@@ -232,10 +225,10 @@ r1373f4_fini(struct nve0_ramfuc *fuc)
}
static void
-nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg,
- u32 _mask, u32 _data, u32 _copy)
+gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg,
+ u32 _mask, u32 _data, u32 _copy)
{
- struct nve0_fb_priv *priv = (void *)nouveau_fb(ram);
+ struct gk104_fb_priv *priv = (void *)nvkm_fb(ram);
struct ramfuc *fuc = &ram->fuc.base;
u32 addr = 0x110000 + (reg->addr & 0xfff);
u32 mask = _mask | _copy;
@@ -246,19 +239,19 @@ nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg,
if (ram->pnuts & (1 << i)) {
u32 prev = nv_rd32(priv, addr);
u32 next = (prev & ~mask) | data;
- nouveau_memx_wr32(fuc->memx, addr, next);
+ nvkm_memx_wr32(fuc->memx, addr, next);
}
}
}
#define ram_nuts(s,r,m,d,c) \
- nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
+ gk104_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
static int
-nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
+gk104_ram_calc_gddr5(struct nvkm_fb *pfb, u32 freq)
{
- struct nve0_ram *ram = (void *)pfb->ram;
- struct nve0_ramfuc *fuc = &ram->fuc;
- struct nouveau_ram_data *next = ram->base.next;
+ struct gk104_ram *ram = (void *)pfb->ram;
+ struct gk104_ramfuc *fuc = &ram->fuc;
+ struct nvkm_ram_data *next = ram->base.next;
int vc = !next->bios.ramcfg_11_02_08;
int mv = !next->bios.ramcfg_11_02_04;
u32 mask, data;
@@ -283,7 +276,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
- nve0_ram_train(fuc, 0x01020000, 0x000c0000);
+ gk104_ram_train(fuc, 0x01020000, 0x000c0000);
ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
ram_nsec(fuc, 1000);
@@ -588,7 +581,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) {
u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
- nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
+ gk104_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f294, temp);
}
@@ -643,7 +636,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
} else {
data = 0xa40e0000;
}
- nve0_ram_train(fuc, 0xbc0f0000, data);
+ gk104_ram_train(fuc, 0xbc0f0000, data);
if (1) /* XXX: not always? */
ram_nsec(fuc, 1000);
@@ -661,7 +654,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
}
if (next->bios.ramcfg_11_07_02)
- nve0_ram_train(fuc, 0x80020000, 0x01000000);
+ gk104_ram_train(fuc, 0x80020000, 0x01000000);
ram_unblock(fuc);
ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
@@ -680,14 +673,14 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
******************************************************************************/
static int
-nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
+gk104_ram_calc_sddr3(struct nvkm_fb *pfb, u32 freq)
{
- struct nve0_ram *ram = (void *)pfb->ram;
- struct nve0_ramfuc *fuc = &ram->fuc;
+ struct gk104_ram *ram = (void *)pfb->ram;
+ struct gk104_ramfuc *fuc = &ram->fuc;
const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
const u32 runk0 = ram->fN1 << 16;
const u32 runk1 = ram->fN1;
- struct nouveau_ram_data *next = ram->base.next;
+ struct nvkm_ram_data *next = ram->base.next;
int vc = !next->bios.ramcfg_11_02_08;
int mv = !next->bios.ramcfg_11_02_04;
u32 mask, data;
@@ -932,11 +925,10 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
******************************************************************************/
static int
-nve0_ram_calc_data(struct nouveau_fb *pfb, u32 khz,
- struct nouveau_ram_data *data)
+gk104_ram_calc_data(struct nvkm_fb *pfb, u32 khz, struct nvkm_ram_data *data)
{
- struct nve0_ram *ram = (void *)pfb->ram;
- struct nouveau_ram_data *cfg;
+ struct gk104_ram *ram = (void *)pfb->ram;
+ struct nvkm_ram_data *cfg;
u32 mhz = khz / 1000;
list_for_each_entry(cfg, &ram->cfg, head) {
@@ -953,10 +945,10 @@ nve0_ram_calc_data(struct nouveau_fb *pfb, u32 khz,
}
static int
-nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next)
+gk104_ram_calc_xits(struct nvkm_fb *pfb, struct nvkm_ram_data *next)
{
- struct nve0_ram *ram = (void *)pfb->ram;
- struct nve0_ramfuc *fuc = &ram->fuc;
+ struct gk104_ram *ram = (void *)pfb->ram;
+ struct gk104_ramfuc *fuc = &ram->fuc;
int refclk, i;
int ret;
@@ -980,8 +972,8 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next)
refclk = fuc->mempll.refclk;
/* calculate refpll coefficients */
- ret = nva3_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1,
- &ram->fN1, &ram->M1, &ram->P1);
+ ret = gt215_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1,
+ &ram->fN1, &ram->M1, &ram->P1);
fuc->mempll.refclk = ret;
if (ret <= 0) {
nv_error(pfb, "unable to calc refpll\n");
@@ -997,8 +989,8 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next)
fuc->mempll.min_p = 1;
fuc->mempll.max_p = 2;
- ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq,
- &ram->N2, NULL, &ram->M2, &ram->P2);
+ ret = gt215_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq,
+ &ram->N2, NULL, &ram->M2, &ram->P2);
if (ret <= 0) {
nv_error(pfb, "unable to calc mempll\n");
return -EINVAL;
@@ -1013,14 +1005,14 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next)
switch (ram->base.type) {
case NV_MEM_TYPE_DDR3:
- ret = nouveau_sddr3_calc(&ram->base);
+ ret = nvkm_sddr3_calc(&ram->base);
if (ret == 0)
- ret = nve0_ram_calc_sddr3(pfb, next->freq);
+ ret = gk104_ram_calc_sddr3(pfb, next->freq);
break;
case NV_MEM_TYPE_GDDR5:
- ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0);
+ ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0);
if (ret == 0)
- ret = nve0_ram_calc_gddr5(pfb, next->freq);
+ ret = gk104_ram_calc_gddr5(pfb, next->freq);
break;
default:
ret = -ENOSYS;
@@ -1031,21 +1023,21 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next)
}
static int
-nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
+gk104_ram_calc(struct nvkm_fb *pfb, u32 freq)
{
- struct nouveau_clk *clk = nouveau_clk(pfb);
- struct nve0_ram *ram = (void *)pfb->ram;
- struct nouveau_ram_data *xits = &ram->base.xition;
- struct nouveau_ram_data *copy;
+ struct nvkm_clk *clk = nvkm_clk(pfb);
+ struct gk104_ram *ram = (void *)pfb->ram;
+ struct nvkm_ram_data *xits = &ram->base.xition;
+ struct nvkm_ram_data *copy;
int ret;
if (ram->base.next == NULL) {
- ret = nve0_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem),
- &ram->base.former);
+ ret = gk104_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem),
+ &ram->base.former);
if (ret)
return ret;
- ret = nve0_ram_calc_data(pfb, freq, &ram->base.target);
+ ret = gk104_ram_calc_data(pfb, freq, &ram->base.target);
if (ret)
return ret;
@@ -1069,14 +1061,14 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
ram->base.next = &ram->base.target;
}
- return nve0_ram_calc_xits(pfb, ram->base.next);
+ return gk104_ram_calc_xits(pfb, ram->base.next);
}
static void
-nve0_ram_prog_0(struct nouveau_fb *pfb, u32 freq)
+gk104_ram_prog_0(struct nvkm_fb *pfb, u32 freq)
{
- struct nve0_ram *ram = (void *)pfb->ram;
- struct nouveau_ram_data *cfg;
+ struct gk104_ram *ram = (void *)pfb->ram;
+ struct nvkm_ram_data *cfg;
u32 mhz = freq / 1000;
u32 mask, data;
@@ -1149,35 +1141,35 @@ nve0_ram_prog_0(struct nouveau_fb *pfb, u32 freq)
}
static int
-nve0_ram_prog(struct nouveau_fb *pfb)
+gk104_ram_prog(struct nvkm_fb *pfb)
{
- struct nouveau_device *device = nv_device(pfb);
- struct nve0_ram *ram = (void *)pfb->ram;
- struct nve0_ramfuc *fuc = &ram->fuc;
- struct nouveau_ram_data *next = ram->base.next;
+ struct nvkm_device *device = nv_device(pfb);
+ struct gk104_ram *ram = (void *)pfb->ram;
+ struct gk104_ramfuc *fuc = &ram->fuc;
+ struct nvkm_ram_data *next = ram->base.next;
- if (!nouveau_boolopt(device->cfgopt, "NvMemExec", true)) {
+ if (!nvkm_boolopt(device->cfgopt, "NvMemExec", true)) {
ram_exec(fuc, false);
return (ram->base.next == &ram->base.xition);
}
- nve0_ram_prog_0(pfb, 1000);
+ gk104_ram_prog_0(pfb, 1000);
ram_exec(fuc, true);
- nve0_ram_prog_0(pfb, next->freq);
+ gk104_ram_prog_0(pfb, next->freq);
return (ram->base.next == &ram->base.xition);
}
static void
-nve0_ram_tidy(struct nouveau_fb *pfb)
+gk104_ram_tidy(struct nvkm_fb *pfb)
{
- struct nve0_ram *ram = (void *)pfb->ram;
- struct nve0_ramfuc *fuc = &ram->fuc;
+ struct gk104_ram *ram = (void *)pfb->ram;
+ struct gk104_ramfuc *fuc = &ram->fuc;
ram->base.next = NULL;
ram_exec(fuc, false);
}
-struct nve0_ram_train {
+struct gk104_ram_train {
u16 mask;
struct nvbios_M0209S remap;
struct nvbios_M0209S type00;
@@ -1190,10 +1182,10 @@ struct nve0_ram_train {
};
static int
-nve0_ram_train_type(struct nouveau_fb *pfb, int i, u8 ramcfg,
- struct nve0_ram_train *train)
+gk104_ram_train_type(struct nvkm_fb *pfb, int i, u8 ramcfg,
+ struct gk104_ram_train *train)
{
- struct nouveau_bios *bios = nouveau_bios(pfb);
+ struct nvkm_bios *bios = nvkm_bios(pfb);
struct nvbios_M0205E M0205E;
struct nvbios_M0205S M0205S;
struct nvbios_M0209E M0209E;
@@ -1251,7 +1243,7 @@ nve0_ram_train_type(struct nouveau_fb *pfb, int i, u8 ramcfg,
}
static int
-nve0_ram_train_init_0(struct nouveau_fb *pfb, struct nve0_ram_train *train)
+gk104_ram_train_init_0(struct nvkm_fb *pfb, struct gk104_ram_train *train)
{
int i, j;
@@ -1285,15 +1277,15 @@ nve0_ram_train_init_0(struct nouveau_fb *pfb, struct nve0_ram_train *train)
}
static int
-nve0_ram_train_init(struct nouveau_fb *pfb)
+gk104_ram_train_init(struct nvkm_fb *pfb)
{
u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb));
- struct nve0_ram_train *train;
+ struct gk104_ram_train *train;
int ret = -ENOMEM, i;
if ((train = kzalloc(sizeof(*train), GFP_KERNEL))) {
for (i = 0; i < 0x100; i++) {
- ret = nve0_ram_train_type(pfb, i, ramcfg, train);
+ ret = gk104_ram_train_type(pfb, i, ramcfg, train);
if (ret && ret != -ENOENT)
break;
}
@@ -1301,7 +1293,7 @@ nve0_ram_train_init(struct nouveau_fb *pfb)
switch (pfb->ram->type) {
case NV_MEM_TYPE_GDDR5:
- ret = nve0_ram_train_init_0(pfb, train);
+ ret = gk104_ram_train_init_0(pfb, train);
break;
default:
ret = 0;
@@ -1313,16 +1305,16 @@ nve0_ram_train_init(struct nouveau_fb *pfb)
}
int
-nve0_ram_init(struct nouveau_object *object)
+gk104_ram_init(struct nvkm_object *object)
{
- struct nouveau_fb *pfb = (void *)object->parent;
- struct nve0_ram *ram = (void *)object;
- struct nouveau_bios *bios = nouveau_bios(pfb);
+ struct nvkm_fb *pfb = (void *)object->parent;
+ struct gk104_ram *ram = (void *)object;
+ struct nvkm_bios *bios = nvkm_bios(pfb);
u8 ver, hdr, cnt, len, snr, ssz;
u32 data, save;
int ret, i;
- ret = nouveau_ram_init(&ram->base);
+ ret = nvkm_ram_init(&ram->base);
if (ret)
return ret;
@@ -1360,15 +1352,15 @@ nve0_ram_init(struct nouveau_object *object)
nv_wr32(pfb, 0x10ecc0, 0xffffffff);
nv_mask(pfb, 0x10f160, 0x00000010, 0x00000010);
- return nve0_ram_train_init(pfb);
+ return gk104_ram_train_init(pfb);
}
static int
-nve0_ram_ctor_data(struct nve0_ram *ram, u8 ramcfg, int i)
+gk104_ram_ctor_data(struct gk104_ram *ram, u8 ramcfg, int i)
{
- struct nouveau_fb *pfb = (void *)nv_object(ram)->parent;
- struct nouveau_bios *bios = nouveau_bios(pfb);
- struct nouveau_ram_data *cfg;
+ struct nvkm_fb *pfb = (void *)nv_object(ram)->parent;
+ struct nvkm_bios *bios = nvkm_bios(pfb);
+ struct nvkm_ram_data *cfg;
struct nvbios_ramcfg *d = &ram->diff;
struct nvbios_ramcfg *p, *n;
u8 ver, hdr, cnt, len;
@@ -1434,33 +1426,33 @@ done:
}
static void
-nve0_ram_dtor(struct nouveau_object *object)
+gk104_ram_dtor(struct nvkm_object *object)
{
- struct nve0_ram *ram = (void *)object;
- struct nouveau_ram_data *cfg, *tmp;
+ struct gk104_ram *ram = (void *)object;
+ struct nvkm_ram_data *cfg, *tmp;
list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) {
kfree(cfg);
}
- nouveau_ram_destroy(&ram->base);
+ nvkm_ram_destroy(&ram->base);
}
static int
-nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
- struct nouveau_bios *bios = nouveau_bios(pfb);
- struct nouveau_gpio *gpio = nouveau_gpio(pfb);
+ struct nvkm_fb *pfb = nvkm_fb(parent);
+ struct nvkm_bios *bios = nvkm_bios(pfb);
+ struct nvkm_gpio *gpio = nvkm_gpio(pfb);
struct dcb_gpio_func func;
- struct nve0_ram *ram;
+ struct gk104_ram *ram;
int ret, i;
u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb));
u32 tmp;
- ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram);
+ ret = gf100_ram_create(parent, engine, oclass, 0x022554, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
@@ -1470,9 +1462,9 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
switch (ram->base.type) {
case NV_MEM_TYPE_DDR3:
case NV_MEM_TYPE_GDDR5:
- ram->base.calc = nve0_ram_calc;
- ram->base.prog = nve0_ram_prog;
- ram->base.tidy = nve0_ram_tidy;
+ ram->base.calc = gk104_ram_calc;
+ ram->base.prog = gk104_ram_prog;
+ ram->base.tidy = gk104_ram_tidy;
break;
default:
nv_warn(pfb, "reclocking of this RAM type is unsupported\n");
@@ -1510,7 +1502,7 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
* need to treat this condition as a "don't touch" indicator.
*/
for (i = 0; !ret; i++) {
- ret = nve0_ram_ctor_data(ram, ramcfg, i);
+ ret = gk104_ram_ctor_data(ram, ramcfg, i);
if (ret && ret != -ENOENT) {
nv_error(pfb, "failed to parse ramcfg data\n");
return ret;
@@ -1634,13 +1626,13 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
-nve0_ram_oclass = {
+struct nvkm_oclass
+gk104_ram_oclass = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_ram_ctor,
- .dtor = nve0_ram_dtor,
- .init = nve0_ram_init,
- .fini = _nouveau_ram_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_ram_ctor,
+ .dtor = gk104_ram_dtor,
+ .init = gk104_ram_init,
+ .fini = _nvkm_ram_fini,
}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c
index 4d77d75e4673..6cf526b4a12f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c
@@ -19,20 +19,17 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
-
#include "priv.h"
-#include <subdev/fb.h>
-
struct gk20a_mem {
- struct nouveau_mem base;
+ struct nvkm_mem base;
void *cpuaddr;
dma_addr_t handle;
};
#define to_gk20a_mem(m) container_of(m, struct gk20a_mem, base)
static void
-gk20a_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
+gk20a_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem)
{
struct device *dev = nv_device_base(nv_device(pfb));
struct gk20a_mem *mem = to_gk20a_mem(*pmem);
@@ -50,8 +47,8 @@ gk20a_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
}
static int
-gk20a_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
- u32 memtype, struct nouveau_mem **pmem)
+gk20a_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin,
+ u32 memtype, struct nvkm_mem **pmem)
{
struct device *dev = nv_device_base(nv_device(pfb));
struct gk20a_mem *mem;
@@ -116,19 +113,18 @@ gk20a_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
mem->base.pages[i] = mem->handle + (PAGE_SIZE * i);
mem->base.offset = (u64)mem->base.pages[0];
-
return 0;
}
static int
-gk20a_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 datasize,
- struct nouveau_object **pobject)
+gk20a_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 datasize,
+ struct nvkm_object **pobject)
{
- struct nouveau_ram *ram;
+ struct nvkm_ram *ram;
int ret;
- ret = nouveau_ram_create(parent, engine, oclass, &ram);
+ ret = nvkm_ram_create(parent, engine, oclass, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
@@ -137,16 +133,15 @@ gk20a_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
ram->get = gk20a_ram_get;
ram->put = gk20a_ram_put;
-
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
gk20a_ram_oclass = {
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_ram_ctor,
- .dtor = _nouveau_ram_dtor,
- .init = _nouveau_ram_init,
- .fini = _nouveau_ram_fini,
+ .dtor = _nvkm_ram_dtor,
+ .init = _nvkm_ram_init,
+ .fini = _nvkm_ram_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c
index 4c6363595c79..a298b39f55c5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c
@@ -21,22 +21,21 @@
*
* Authors: Ben Skeggs
*/
-
-#include "nvc0.h"
+#include "gf100.h"
struct gm107_ram {
- struct nouveau_ram base;
+ struct nvkm_ram base;
};
static int
-gm107_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gm107_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct gm107_ram *ram;
int ret;
- ret = nvc0_ram_create(parent, engine, oclass, 0x021c14, &ram);
+ ret = gf100_ram_create(parent, engine, oclass, 0x021c14, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
@@ -44,13 +43,13 @@ gm107_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
gm107_ram_oclass = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm107_ram_ctor,
- .dtor = _nouveau_ram_dtor,
- .init = nve0_ram_init,
- .fini = _nouveau_ram_fini,
+ .dtor = _nvkm_ram_dtor,
+ .init = gk104_ram_init,
+ .fini = _nvkm_ram_fini,
}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
similarity index 86%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
index f3cc7a19f931..692a1cc6c957 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
@@ -23,32 +23,21 @@
* Roy Spliet <rspliet@eclipso.eu>
*/
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/pll.h>
-#include <subdev/bios/rammap.h>
-#include <subdev/bios/M0205.h>
-#include <subdev/bios/timing.h>
-
-#include <subdev/clk/gt215.h>
-#include <subdev/clk/pll.h>
-
-#include <subdev/gpio.h>
-
-#include <subdev/timer.h>
-
-#include <engine/fifo.h>
+#include "ramfuc.h"
+#include "nv50.h"
#include <core/option.h>
-
-#include "ramfuc.h"
-
-#include "nv50.h"
+#include <subdev/bios.h>
+#include <subdev/bios/M0205.h>
+#include <subdev/bios/rammap.h>
+#include <subdev/bios/timing.h>
+#include <subdev/clk/gt215.h>
+#include <subdev/gpio.h>
/* XXX: Remove when memx gains GPIO support */
extern int nv50_gpio_location(int line, u32 *reg, u32 *shift);
-struct nva3_ramfuc {
+struct gt215_ramfuc {
struct ramfuc base;
struct ramfuc_reg r_0x001610;
struct ramfuc_reg r_0x001700;
@@ -89,7 +78,7 @@ struct nva3_ramfuc {
struct ramfuc_reg r_gpioFBVREF;
};
-struct nva3_ltrain {
+struct gt215_ltrain {
enum {
NVA3_TRAIN_UNKNOWN,
NVA3_TRAIN_UNSUPPORTED,
@@ -100,17 +89,17 @@ struct nva3_ltrain {
u32 r_100720;
u32 r_1111e0;
u32 r_111400;
- struct nouveau_mem *mem;
+ struct nvkm_mem *mem;
};
-struct nva3_ram {
- struct nouveau_ram base;
- struct nva3_ramfuc fuc;
- struct nva3_ltrain ltrain;
+struct gt215_ram {
+ struct nvkm_ram base;
+ struct gt215_ramfuc fuc;
+ struct gt215_ltrain ltrain;
};
void
-nva3_link_train_calc(u32 *vals, struct nva3_ltrain *train)
+gt215_link_train_calc(u32 *vals, struct gt215_ltrain *train)
{
int i, lo, hi;
u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0;
@@ -164,14 +153,14 @@ nva3_link_train_calc(u32 *vals, struct nva3_ltrain *train)
* Link training for (at least) DDR3
*/
int
-nva3_link_train(struct nouveau_fb *pfb)
+gt215_link_train(struct nvkm_fb *pfb)
{
- struct nouveau_bios *bios = nouveau_bios(pfb);
- struct nva3_ram *ram = (void *)pfb->ram;
- struct nouveau_clk *clk = nouveau_clk(pfb);
- struct nva3_ltrain *train = &ram->ltrain;
- struct nouveau_device *device = nv_device(pfb);
- struct nva3_ramfuc *fuc = &ram->fuc;
+ struct nvkm_bios *bios = nvkm_bios(pfb);
+ struct gt215_ram *ram = (void *)pfb->ram;
+ struct nvkm_clk *clk = nvkm_clk(pfb);
+ struct gt215_ltrain *train = &ram->ltrain;
+ struct nvkm_device *device = nv_device(pfb);
+ struct gt215_ramfuc *fuc = &ram->fuc;
u32 *result, r1700;
int ret, i;
struct nvbios_M0205T M0205T = { 0 };
@@ -180,7 +169,7 @@ nva3_link_train(struct nouveau_fb *pfb)
unsigned long flags;
unsigned long *f = &flags;
- if (nouveau_boolopt(device->cfgopt, "NvMemExec", true) != true)
+ if (nvkm_boolopt(device->cfgopt, "NvMemExec", true) != true)
return -ENOSYS;
/* XXX: Multiple partitions? */
@@ -197,7 +186,7 @@ nva3_link_train(struct nouveau_fb *pfb)
clk_current = clk->read(clk, nv_clk_src_mem);
- ret = nva3_clk_pre(clk, f);
+ ret = gt215_clk_pre(clk, f);
if (ret)
goto out;
@@ -252,12 +241,12 @@ nva3_link_train(struct nouveau_fb *pfb)
nv_mask(pfb, 0x616308, 0x10, 0x10);
nv_mask(pfb, 0x616b08, 0x10, 0x10);
- nva3_clk_post(clk, f);
+ gt215_clk_post(clk, f);
ram_train_result(pfb, result, 64);
for (i = 0; i < 64; i++)
nv_debug(pfb, "Train: %08x", result[i]);
- nva3_link_train_calc(result, train);
+ gt215_link_train_calc(result, train);
nv_debug(pfb, "Train: %08x %08x %08x", train->r_100720,
train->r_1111e0, train->r_111400);
@@ -274,12 +263,12 @@ out:
train->state = NVA3_TRAIN_UNSUPPORTED;
- nva3_clk_post(clk, f);
+ gt215_clk_post(clk, f);
return ret;
}
int
-nva3_link_train_init(struct nouveau_fb *pfb)
+gt215_link_train_init(struct nvkm_fb *pfb)
{
static const u32 pattern[16] = {
0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee,
@@ -287,10 +276,10 @@ nva3_link_train_init(struct nouveau_fb *pfb)
0x33333333, 0x55555555, 0x77777777, 0x66666666,
0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb,
};
- struct nouveau_bios *bios = nouveau_bios(pfb);
- struct nva3_ram *ram = (void *)pfb->ram;
- struct nva3_ltrain *train = &ram->ltrain;
- struct nouveau_mem *mem;
+ struct nvkm_bios *bios = nvkm_bios(pfb);
+ struct gt215_ram *ram = (void *)pfb->ram;
+ struct gt215_ltrain *train = &ram->ltrain;
+ struct nvkm_mem *mem;
struct nvbios_M0205E M0205E;
u8 ver, hdr, cnt, len;
u32 r001700;
@@ -340,14 +329,13 @@ nva3_link_train_init(struct nouveau_fb *pfb)
train->r_100720 = nv_rd32(pfb, 0x100720);
train->r_1111e0 = nv_rd32(pfb, 0x1111e0);
train->r_111400 = nv_rd32(pfb, 0x111400);
-
return 0;
}
void
-nva3_link_train_fini(struct nouveau_fb *pfb)
+gt215_link_train_fini(struct nvkm_fb *pfb)
{
- struct nva3_ram *ram = (void *)pfb->ram;
+ struct gt215_ram *ram = (void *)pfb->ram;
if (ram->ltrain.mem)
pfb->ram->put(pfb, &ram->ltrain.mem);
@@ -358,9 +346,9 @@ nva3_link_train_fini(struct nouveau_fb *pfb)
*/
#define T(t) cfg->timing_10_##t
static int
-nva3_ram_timing_calc(struct nouveau_fb *pfb, u32 *timing)
+gt215_ram_timing_calc(struct nvkm_fb *pfb, u32 *timing)
{
- struct nva3_ram *ram = (void *)pfb->ram;
+ struct gt215_ram *ram = (void *)pfb->ram;
struct nvbios_ramcfg *cfg = &ram->base.target.bios;
int tUNK_base, tUNK_40_0, prevCL;
u32 cur2, cur3, cur7, cur8;
@@ -433,7 +421,7 @@ nva3_ram_timing_calc(struct nouveau_fb *pfb, u32 *timing)
#undef T
static void
-nouveau_sddr2_dll_reset(struct nva3_ramfuc *fuc)
+nvkm_sddr2_dll_reset(struct gt215_ramfuc *fuc)
{
ram_mask(fuc, mr[0], 0x100, 0x100);
ram_nsec(fuc, 1000);
@@ -442,7 +430,7 @@ nouveau_sddr2_dll_reset(struct nva3_ramfuc *fuc)
}
static void
-nouveau_sddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr)
+nvkm_sddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr)
{
u32 mr1_old = ram_rd32(fuc, mr[1]);
@@ -454,7 +442,7 @@ nouveau_sddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr)
}
static void
-nouveau_gddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr)
+nvkm_gddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr)
{
u32 mr1_old = ram_rd32(fuc, mr[1]);
@@ -465,7 +453,7 @@ nouveau_gddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr)
}
static void
-nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clk_info *mclk)
+gt215_ram_lock_pll(struct gt215_ramfuc *fuc, struct gt215_clk_info *mclk)
{
ram_wr32(fuc, 0x004004, mclk->pll);
ram_mask(fuc, 0x004000, 0x00000001, 0x00000001);
@@ -475,9 +463,9 @@ nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clk_info *mclk)
}
static void
-nva3_ram_fbvref(struct nva3_ramfuc *fuc, u32 val)
+gt215_ram_fbvref(struct gt215_ramfuc *fuc, u32 val)
{
- struct nouveau_gpio *gpio = nouveau_gpio(fuc->base.pfb);
+ struct nvkm_gpio *gpio = nvkm_gpio(fuc->base.pfb);
struct dcb_gpio_func func;
u32 reg, sh, gpio_val;
int ret;
@@ -498,14 +486,14 @@ nva3_ram_fbvref(struct nva3_ramfuc *fuc, u32 val)
}
static int
-nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
+gt215_ram_calc(struct nvkm_fb *pfb, u32 freq)
{
- struct nouveau_bios *bios = nouveau_bios(pfb);
- struct nva3_ram *ram = (void *)pfb->ram;
- struct nva3_ramfuc *fuc = &ram->fuc;
- struct nva3_ltrain *train = &ram->ltrain;
- struct nva3_clk_info mclk;
- struct nouveau_ram_data *next;
+ struct nvkm_bios *bios = nvkm_bios(pfb);
+ struct gt215_ram *ram = (void *)pfb->ram;
+ struct gt215_ramfuc *fuc = &ram->fuc;
+ struct gt215_ltrain *train = &ram->ltrain;
+ struct gt215_clk_info mclk;
+ struct nvkm_ram_data *next;
u8 ver, hdr, cnt, len, strap;
u32 data;
u32 r004018, r100760, r100da0, r111100, ctrl;
@@ -519,12 +507,12 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
ram->base.next = next;
if (ram->ltrain.state == NVA3_TRAIN_ONCE)
- nva3_link_train(pfb);
+ gt215_link_train(pfb);
/* lookup memory config data relevant to the target frequency */
i = 0;
data = nvbios_rammapEm(bios, freq / 1000, &ver, &hdr, &cnt, &len,
- &next->bios);
+ &next->bios);
if (!data || ver != 0x10 || hdr < 0x05) {
nv_error(pfb, "invalid/missing rammap entry\n");
return -EINVAL;
@@ -555,13 +543,13 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
}
}
- ret = nva3_pll_info(nouveau_clk(pfb), 0x12, 0x4000, freq, &mclk);
+ ret = gt215_pll_info(nvkm_clk(pfb), 0x12, 0x4000, freq, &mclk);
if (ret < 0) {
nv_error(pfb, "failed mclk calculation\n");
return ret;
}
- nva3_ram_timing_calc(pfb, timing);
+ gt215_ram_timing_calc(pfb, timing);
ret = ram_init(fuc, pfb);
if (ret)
@@ -574,13 +562,13 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
switch (ram->base.type) {
case NV_MEM_TYPE_DDR2:
- ret = nouveau_sddr2_calc(&ram->base);
+ ret = nvkm_sddr2_calc(&ram->base);
break;
case NV_MEM_TYPE_DDR3:
- ret = nouveau_sddr3_calc(&ram->base);
+ ret = nvkm_sddr3_calc(&ram->base);
break;
case NV_MEM_TYPE_GDDR3:
- ret = nouveau_gddr3_calc(&ram->base);
+ ret = nvkm_gddr3_calc(&ram->base);
break;
default:
ret = -ENOSYS;
@@ -621,7 +609,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
/* If switching from non-pll to pll, lock before disabling FB */
if (mclk.pll && !pll2pll) {
ram_mask(fuc, 0x004128, 0x003f3141, mclk.clk | 0x00000101);
- nva3_ram_lock_pll(fuc, &mclk);
+ gt215_ram_lock_pll(fuc, &mclk);
}
/* Start with disabling some CRTCs and PFIFO? */
@@ -643,15 +631,15 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
/* If we're disabling the DLL, do it now */
switch (next->bios.ramcfg_10_DLLoff * ram->base.type) {
case NV_MEM_TYPE_DDR3:
- nouveau_sddr3_dll_disable(fuc, ram->base.mr);
+ nvkm_sddr3_dll_disable(fuc, ram->base.mr);
break;
case NV_MEM_TYPE_GDDR3:
- nouveau_gddr3_dll_disable(fuc, ram->base.mr);
+ nvkm_gddr3_dll_disable(fuc, ram->base.mr);
break;
}
if (fuc->r_gpioFBVREF.addr && next->bios.timing_10_ODT)
- nva3_ram_fbvref(fuc, 0);
+ gt215_ram_fbvref(fuc, 0);
/* Brace RAM for impact */
ram_wr32(fuc, 0x1002d4, 0x00000001);
@@ -678,7 +666,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
ram_mask(fuc, 0x004000, 0x00000008, 0x00000008);
ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
ram_wr32(fuc, 0x004018, 0x00001000);
- nva3_ram_lock_pll(fuc, &mclk);
+ gt215_ram_lock_pll(fuc, &mclk);
}
if (mclk.pll) {
@@ -818,11 +806,11 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
ram_mask(fuc, 0x111100, 0xffffffff, r111100);
if (fuc->r_gpioFBVREF.addr && !next->bios.timing_10_ODT)
- nva3_ram_fbvref(fuc, 1);
+ gt215_ram_fbvref(fuc, 1);
/* Reset DLL */
if (!next->bios.ramcfg_10_DLLoff)
- nouveau_sddr2_dll_reset(fuc);
+ nvkm_sddr2_dll_reset(fuc);
if (ram->base.type == NV_MEM_TYPE_GDDR3) {
ram_nsec(fuc, 31000);
@@ -866,12 +854,12 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
}
static int
-nva3_ram_prog(struct nouveau_fb *pfb)
+gt215_ram_prog(struct nvkm_fb *pfb)
{
- struct nouveau_device *device = nv_device(pfb);
- struct nva3_ram *ram = (void *)pfb->ram;
- struct nva3_ramfuc *fuc = &ram->fuc;
- bool exec = nouveau_boolopt(device->cfgopt, "NvMemExec", true);
+ struct nvkm_device *device = nv_device(pfb);
+ struct gt215_ram *ram = (void *)pfb->ram;
+ struct gt215_ramfuc *fuc = &ram->fuc;
+ bool exec = nvkm_boolopt(device->cfgopt, "NvMemExec", true);
if (exec) {
nv_mask(pfb, 0x001534, 0x2, 0x2);
@@ -891,49 +879,48 @@ nva3_ram_prog(struct nouveau_fb *pfb)
}
static void
-nva3_ram_tidy(struct nouveau_fb *pfb)
+gt215_ram_tidy(struct nvkm_fb *pfb)
{
- struct nva3_ram *ram = (void *)pfb->ram;
- struct nva3_ramfuc *fuc = &ram->fuc;
+ struct gt215_ram *ram = (void *)pfb->ram;
+ struct gt215_ramfuc *fuc = &ram->fuc;
ram_exec(fuc, false);
}
static int
-nva3_ram_init(struct nouveau_object *object)
+gt215_ram_init(struct nvkm_object *object)
{
- struct nouveau_fb *pfb = (void *)object->parent;
- struct nva3_ram *ram = (void *)object;
+ struct nvkm_fb *pfb = (void *)object->parent;
+ struct gt215_ram *ram = (void *)object;
int ret;
- ret = nouveau_ram_init(&ram->base);
+ ret = nvkm_ram_init(&ram->base);
if (ret)
return ret;
- nva3_link_train_init(pfb);
-
+ gt215_link_train_init(pfb);
return 0;
}
static int
-nva3_ram_fini(struct nouveau_object *object, bool suspend)
+gt215_ram_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_fb *pfb = (void *)object->parent;
+ struct nvkm_fb *pfb = (void *)object->parent;
if (!suspend)
- nva3_link_train_fini(pfb);
+ gt215_link_train_fini(pfb);
return 0;
}
static int
-nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 datasize,
- struct nouveau_object **pobject)
+gt215_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 datasize,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
- struct nouveau_gpio *gpio = nouveau_gpio(pfb);
+ struct nvkm_fb *pfb = nvkm_fb(parent);
+ struct nvkm_gpio *gpio = nvkm_gpio(pfb);
struct dcb_gpio_func func;
- struct nva3_ram *ram;
+ struct gt215_ram *ram;
int ret, i;
u32 reg, shift;
@@ -946,9 +933,9 @@ nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
case NV_MEM_TYPE_DDR2:
case NV_MEM_TYPE_DDR3:
case NV_MEM_TYPE_GDDR3:
- ram->base.calc = nva3_ram_calc;
- ram->base.prog = nva3_ram_prog;
- ram->base.tidy = nva3_ram_tidy;
+ ram->base.calc = gt215_ram_calc;
+ ram->base.prog = gt215_ram_prog;
+ ram->base.tidy = gt215_ram_tidy;
break;
default:
nv_warn(ram, "reclocking of this ram type unsupported\n");
@@ -1013,12 +1000,12 @@ nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
-nva3_ram_oclass = {
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nva3_ram_ctor,
- .dtor = _nouveau_ram_dtor,
- .init = nva3_ram_init,
- .fini = nva3_ram_fini,
+struct nvkm_oclass
+gt215_ram_oclass = {
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gt215_ram_ctor,
+ .dtor = _nvkm_ram_dtor,
+ .init = gt215_ram_init,
+ .fini = gt215_ram_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c
similarity index 73%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvaa.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c
index 033a8e999497..abc18e89a97c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvaa.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c
@@ -21,26 +21,25 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
-struct nvaa_ram_priv {
- struct nouveau_ram base;
+struct mcp77_ram_priv {
+ struct nvkm_ram base;
u64 poller_base;
};
static int
-nvaa_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 datasize,
- struct nouveau_object **pobject)
+mcp77_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 datasize,
+ struct nvkm_object **pobject)
{
u32 rsvd_head = ( 256 * 1024); /* vga memory */
u32 rsvd_tail = (1024 * 1024); /* vbios etc */
- struct nouveau_fb *pfb = nouveau_fb(parent);
- struct nvaa_ram_priv *priv;
+ struct nvkm_fb *pfb = nvkm_fb(parent);
+ struct mcp77_ram_priv *priv;
int ret;
- ret = nouveau_ram_create(parent, engine, oclass, &priv);
+ ret = nvkm_ram_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -52,9 +51,9 @@ nvaa_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
rsvd_tail += 0x1000;
priv->poller_base = priv->base.size - rsvd_tail;
- ret = nouveau_mm_init(&pfb->vram, rsvd_head >> 12,
- (priv->base.size - (rsvd_head + rsvd_tail)) >> 12,
- 1);
+ ret = nvkm_mm_init(&pfb->vram, rsvd_head >> 12,
+ (priv->base.size - (rsvd_head + rsvd_tail)) >> 12,
+ 1);
if (ret)
return ret;
@@ -64,14 +63,14 @@ nvaa_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
static int
-nvaa_ram_init(struct nouveau_object *object)
+mcp77_ram_init(struct nvkm_object *object)
{
- struct nouveau_fb *pfb = nouveau_fb(object);
- struct nvaa_ram_priv *priv = (void *)object;
+ struct nvkm_fb *pfb = nvkm_fb(object);
+ struct mcp77_ram_priv *priv = (void *)object;
int ret;
u64 dniso, hostnb, flush;
- ret = nouveau_ram_init(&priv->base);
+ ret = nvkm_ram_init(&priv->base);
if (ret)
return ret;
@@ -88,16 +87,15 @@ nvaa_ram_init(struct nouveau_object *object)
nv_mask(pfb, 0x100c14, 0x00000000, 0x00000002);
nv_wr32(pfb, 0x100c24, flush);
nv_mask(pfb, 0x100c14, 0x00000000, 0x00010000);
-
return 0;
}
-struct nouveau_oclass
-nvaa_ram_oclass = {
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvaa_ram_ctor,
- .dtor = _nouveau_ram_dtor,
- .init = nvaa_ram_init,
- .fini = _nouveau_ram_fini,
+struct nvkm_oclass
+mcp77_ram_oclass = {
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = mcp77_ram_ctor,
+ .dtor = _nvkm_ram_dtor,
+ .init = mcp77_ram_init,
+ .fini = _nvkm_ram_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c
index 1972268d1410..855de1617229 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c
@@ -21,22 +21,20 @@
*
* Authors: Ben Skeggs
*/
-
-#include <subdev/fb/regsnv04.h>
-
#include "priv.h"
+#include "regsnv04.h"
static int
-nv04_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
- struct nouveau_ram *ram;
+ struct nvkm_fb *pfb = nvkm_fb(parent);
+ struct nvkm_ram *ram;
u32 boot0 = nv_rd32(pfb, NV04_PFB_BOOT_0);
int ret;
- ret = nouveau_ram_create(parent, engine, oclass, &ram);
+ ret = nvkm_ram_create(parent, engine, oclass, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
@@ -65,16 +63,17 @@ nv04_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
ram->type = NV_MEM_TYPE_SGRAM;
else
ram->type = NV_MEM_TYPE_SDRAM;
+
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv04_ram_oclass = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_ram_create,
- .dtor = _nouveau_ram_dtor,
- .init = _nouveau_ram_init,
- .fini = _nouveau_ram_fini,
+ .dtor = _nvkm_ram_dtor,
+ .init = _nvkm_ram_init,
+ .fini = _nvkm_ram_fini,
}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c
index 8311f3774edf..3b8a1eda5b64 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c
@@ -21,20 +21,19 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
static int
-nv10_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv10_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
- struct nouveau_ram *ram;
+ struct nvkm_fb *pfb = nvkm_fb(parent);
+ struct nvkm_ram *ram;
u32 cfg0 = nv_rd32(pfb, 0x100200);
int ret;
- ret = nouveau_ram_create(parent, engine, oclass, &ram);
+ ret = nvkm_ram_create(parent, engine, oclass, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
@@ -48,14 +47,13 @@ nv10_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-
-struct nouveau_oclass
+struct nvkm_oclass
nv10_ram_oclass = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv10_ram_create,
- .dtor = _nouveau_ram_dtor,
- .init = _nouveau_ram_init,
- .fini = _nouveau_ram_fini,
+ .dtor = _nvkm_ram_dtor,
+ .init = _nvkm_ram_init,
+ .fini = _nvkm_ram_fini,
}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
index d0caddfb9db0..8bb7e432ad04 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
@@ -21,16 +21,15 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
static int
-nv1a_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
- struct nouveau_ram *ram;
+ struct nvkm_fb *pfb = nvkm_fb(parent);
+ struct nvkm_ram *ram;
struct pci_dev *bridge;
u32 mem, mib;
int ret;
@@ -41,7 +40,7 @@ nv1a_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
return -ENODEV;
}
- ret = nouveau_ram_create(parent, engine, oclass, &ram);
+ ret = nvkm_ram_create(parent, engine, oclass, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
@@ -59,13 +58,13 @@ nv1a_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv1a_ram_oclass = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv1a_ram_create,
- .dtor = _nouveau_ram_dtor,
- .init = _nouveau_ram_init,
- .fini = _nouveau_ram_fini,
+ .dtor = _nvkm_ram_dtor,
+ .init = _nvkm_ram_init,
+ .fini = _nvkm_ram_fini,
}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c
index fdc11bba226d..d9e7187bd235 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c
@@ -21,20 +21,19 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
static int
-nv20_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv20_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
- struct nouveau_ram *ram;
+ struct nvkm_fb *pfb = nvkm_fb(parent);
+ struct nvkm_ram *ram;
u32 pbus1218 = nv_rd32(pfb, 0x001218);
int ret;
- ret = nouveau_ram_create(parent, engine, oclass, &ram);
+ ret = nvkm_ram_create(parent, engine, oclass, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
@@ -51,13 +50,13 @@ nv20_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv20_ram_oclass = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv20_ram_create,
- .dtor = _nouveau_ram_dtor,
- .init = _nouveau_ram_init,
- .fini = _nouveau_ram_fini,
+ .dtor = _nvkm_ram_dtor,
+ .init = _nvkm_ram_init,
+ .fini = _nvkm_ram_fini,
}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
index 50cbc3804eaf..a36a90c29ba9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
@@ -21,23 +21,19 @@
*
* Authors: Ben Skeggs
*/
+#include "nv40.h"
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
-#include <subdev/bios/pll.h>
#include <subdev/bios/init.h>
-#include <subdev/clk.h>
+#include <subdev/bios/pll.h>
#include <subdev/clk/pll.h>
#include <subdev/timer.h>
-#include <engine/fifo.h>
-
-#include "nv40.h"
-
int
-nv40_ram_calc(struct nouveau_fb *pfb, u32 freq)
+nv40_ram_calc(struct nvkm_fb *pfb, u32 freq)
{
- struct nouveau_bios *bios = nouveau_bios(pfb);
+ struct nvkm_bios *bios = nvkm_bios(pfb);
struct nv40_ram *ram = (void *)pfb->ram;
struct nvbios_pll pll;
int N1, M1, N2, M2;
@@ -68,9 +64,9 @@ nv40_ram_calc(struct nouveau_fb *pfb, u32 freq)
}
int
-nv40_ram_prog(struct nouveau_fb *pfb)
+nv40_ram_prog(struct nvkm_fb *pfb)
{
- struct nouveau_bios *bios = nouveau_bios(pfb);
+ struct nvkm_bios *bios = nvkm_bios(pfb);
struct nv40_ram *ram = (void *)pfb->ram;
struct bit_entry M;
u32 crtc_mask = 0;
@@ -167,21 +163,21 @@ nv40_ram_prog(struct nouveau_fb *pfb)
}
void
-nv40_ram_tidy(struct nouveau_fb *pfb)
+nv40_ram_tidy(struct nvkm_fb *pfb)
{
}
static int
-nv40_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
+ struct nvkm_fb *pfb = nvkm_fb(parent);
struct nv40_ram *ram;
u32 pbus1218 = nv_rd32(pfb, 0x001218);
int ret;
- ret = nouveau_ram_create(parent, engine, oclass, &ram);
+ ret = nvkm_ram_create(parent, engine, oclass, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
@@ -203,13 +199,13 @@ nv40_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
}
-struct nouveau_oclass
+struct nvkm_oclass
nv40_ram_oclass = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_ram_create,
- .dtor = _nouveau_ram_dtor,
- .init = _nouveau_ram_init,
- .fini = _nouveau_ram_fini,
+ .dtor = _nvkm_ram_dtor,
+ .init = _nvkm_ram_init,
+ .fini = _nvkm_ram_fini,
}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c
index d64498a4d9ee..33c612b1355f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c
@@ -21,20 +21,19 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv40.h"
static int
-nv41_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv41_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
+ struct nvkm_fb *pfb = nvkm_fb(parent);
struct nv40_ram *ram;
u32 pfb474 = nv_rd32(pfb, 0x100474);
int ret;
- ret = nouveau_ram_create(parent, engine, oclass, &ram);
+ ret = nvkm_ram_create(parent, engine, oclass, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
@@ -55,13 +54,13 @@ nv41_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv41_ram_oclass = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv41_ram_create,
- .dtor = _nouveau_ram_dtor,
- .init = _nouveau_ram_init,
- .fini = _nouveau_ram_fini,
+ .dtor = _nvkm_ram_dtor,
+ .init = _nvkm_ram_init,
+ .fini = _nvkm_ram_fini,
}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c
index 089acac810c5..f575a7246403 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c
@@ -21,20 +21,19 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv40.h"
static int
-nv44_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
+ struct nvkm_fb *pfb = nvkm_fb(parent);
struct nv40_ram *ram;
u32 pfb474 = nv_rd32(pfb, 0x100474);
int ret;
- ret = nouveau_ram_create(parent, engine, oclass, &ram);
+ ret = nvkm_ram_create(parent, engine, oclass, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
@@ -53,13 +52,13 @@ nv44_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv44_ram_oclass = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv44_ram_create,
- .dtor = _nouveau_ram_dtor,
- .init = _nouveau_ram_init,
- .fini = _nouveau_ram_fini,
+ .dtor = _nvkm_ram_dtor,
+ .init = _nvkm_ram_init,
+ .fini = _nvkm_ram_fini,
}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c
index baa013afa57b..51b44cdb2732 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c
@@ -21,20 +21,19 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv40.h"
static int
-nv49_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv49_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
+ struct nvkm_fb *pfb = nvkm_fb(parent);
struct nv40_ram *ram;
u32 pfb914 = nv_rd32(pfb, 0x100914);
int ret;
- ret = nouveau_ram_create(parent, engine, oclass, &ram);
+ ret = nvkm_ram_create(parent, engine, oclass, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
@@ -55,13 +54,13 @@ nv49_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv49_ram_oclass = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv49_ram_create,
- .dtor = _nouveau_ram_dtor,
- .init = _nouveau_ram_init,
- .fini = _nouveau_ram_fini,
+ .dtor = _nvkm_ram_dtor,
+ .init = _nvkm_ram_init,
+ .fini = _nvkm_ram_fini,
}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c
index 63a6aab86028..f3ed1c60d730 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c
@@ -21,19 +21,18 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
static int
-nv4e_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv4e_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
- struct nouveau_ram *ram;
+ struct nvkm_fb *pfb = nvkm_fb(parent);
+ struct nvkm_ram *ram;
int ret;
- ret = nouveau_ram_create(parent, engine, oclass, &ram);
+ ret = nvkm_ram_create(parent, engine, oclass, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
@@ -43,13 +42,13 @@ nv4e_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv4e_ram_oclass = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv4e_ram_create,
- .dtor = _nouveau_ram_dtor,
- .init = _nouveau_ram_init,
- .fini = _nouveau_ram_fini,
+ .dtor = _nvkm_ram_dtor,
+ .init = _nvkm_ram_init,
+ .fini = _nvkm_ram_fini,
}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
index 8d2970c27715..14f5ba5eefde 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
@@ -21,21 +21,15 @@
*
* Authors: Ben Skeggs
*/
-
-#include <subdev/bios.h>
-#include <subdev/bios/bit.h>
-#include <subdev/bios/pll.h>
-#include <subdev/bios/perf.h>
-#include <subdev/bios/timing.h>
-#include <subdev/clk/pll.h>
-#include <subdev/fb.h>
-
-#include <core/option.h>
-#include <core/mm.h>
-
+#include "nv50.h"
#include "ramseq.h"
-#include "nv50.h"
+#include <core/option.h>
+#include <subdev/bios.h>
+#include <subdev/bios/perf.h>
+#include <subdev/bios/pll.h>
+#include <subdev/bios/timing.h>
+#include <subdev/clk/pll.h>
struct nv50_ramseq {
struct hwsq base;
@@ -56,16 +50,16 @@ struct nv50_ramseq {
};
struct nv50_ram {
- struct nouveau_ram base;
+ struct nvkm_ram base;
struct nv50_ramseq hwsq;
};
#define QFX5800NVA0 1
static int
-nv50_ram_calc(struct nouveau_fb *pfb, u32 freq)
+nv50_ram_calc(struct nvkm_fb *pfb, u32 freq)
{
- struct nouveau_bios *bios = nouveau_bios(pfb);
+ struct nvkm_bios *bios = nvkm_bios(pfb);
struct nv50_ram *ram = (void *)pfb->ram;
struct nv50_ramseq *hwsq = &ram->hwsq;
struct nvbios_perfE perfE;
@@ -82,7 +76,7 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq)
i = 0;
do {
ramcfg.data = nvbios_perfEp(bios, i++, &ver, &hdr, &cnt,
- &ramcfg.size, &perfE);
+ &ramcfg.size, &perfE);
if (!ramcfg.data || (ver < 0x25 || ver >= 0x40) ||
(ramcfg.size < 2)) {
nv_error(pfb, "invalid/missing perftab entry\n");
@@ -103,7 +97,7 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq)
strap = nv_ro08(bios, ramcfg.data + 0x01);
if (strap != 0xff) {
timing.data = nvbios_timingEe(bios, strap, &ver, &hdr,
- &cnt, &len);
+ &cnt, &len);
if (!timing.data || ver != 0x10 || hdr < 0x12) {
nv_error(pfb, "invalid/missing timing entry "
"%02x %04x %02x %02x\n",
@@ -136,7 +130,7 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq)
mpll.vco2.max_freq = 0;
if (ret == 0) {
ret = nv04_pll_calc(nv_subdev(pfb), &mpll, freq,
- &N1, &M1, &N2, &M2, &P);
+ &N1, &M1, &N2, &M2, &P);
if (ret == 0)
ret = -EINVAL;
}
@@ -205,18 +199,18 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq)
}
static int
-nv50_ram_prog(struct nouveau_fb *pfb)
+nv50_ram_prog(struct nvkm_fb *pfb)
{
- struct nouveau_device *device = nv_device(pfb);
+ struct nvkm_device *device = nv_device(pfb);
struct nv50_ram *ram = (void *)pfb->ram;
struct nv50_ramseq *hwsq = &ram->hwsq;
- ram_exec(hwsq, nouveau_boolopt(device->cfgopt, "NvMemExec", true));
+ ram_exec(hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true));
return 0;
}
static void
-nv50_ram_tidy(struct nouveau_fb *pfb)
+nv50_ram_tidy(struct nvkm_fb *pfb)
{
struct nv50_ram *ram = (void *)pfb->ram;
struct nv50_ramseq *hwsq = &ram->hwsq;
@@ -224,24 +218,24 @@ nv50_ram_tidy(struct nouveau_fb *pfb)
}
void
-__nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem *mem)
+__nv50_ram_put(struct nvkm_fb *pfb, struct nvkm_mem *mem)
{
- struct nouveau_mm_node *this;
+ struct nvkm_mm_node *this;
while (!list_empty(&mem->regions)) {
this = list_first_entry(&mem->regions, typeof(*this), rl_entry);
list_del(&this->rl_entry);
- nouveau_mm_free(&pfb->vram, &this);
+ nvkm_mm_free(&pfb->vram, &this);
}
- nouveau_mm_free(&pfb->tags, &mem->tag);
+ nvkm_mm_free(&pfb->tags, &mem->tag);
}
void
-nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
+nv50_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem)
{
- struct nouveau_mem *mem = *pmem;
+ struct nvkm_mem *mem = *pmem;
*pmem = NULL;
if (unlikely(mem == NULL))
@@ -255,13 +249,13 @@ nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
}
int
-nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
- u32 memtype, struct nouveau_mem **pmem)
+nv50_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin,
+ u32 memtype, struct nvkm_mem **pmem)
{
- struct nouveau_mm *heap = &pfb->vram;
- struct nouveau_mm *tags = &pfb->tags;
- struct nouveau_mm_node *r;
- struct nouveau_mem *mem;
+ struct nvkm_mm *heap = &pfb->vram;
+ struct nvkm_mm *tags = &pfb->tags;
+ struct nvkm_mm_node *r;
+ struct nvkm_mem *mem;
int comp = (memtype & 0x300) >> 8;
int type = (memtype & 0x07f);
int back = (memtype & 0x800);
@@ -280,7 +274,7 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
if (align == 16) {
int n = (max >> 4) * comp;
- ret = nouveau_mm_head(tags, 0, 1, n, n, 1, &mem->tag);
+ ret = nvkm_mm_head(tags, 0, 1, n, n, 1, &mem->tag);
if (ret)
mem->tag = NULL;
}
@@ -296,9 +290,9 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
type = nv50_fb_memtype[type];
do {
if (back)
- ret = nouveau_mm_tail(heap, 0, type, max, min, align, &r);
+ ret = nvkm_mm_tail(heap, 0, type, max, min, align, &r);
else
- ret = nouveau_mm_head(heap, 0, type, max, min, align, &r);
+ ret = nvkm_mm_head(heap, 0, type, max, min, align, &r);
if (ret) {
mutex_unlock(&pfb->base.mutex);
pfb->ram->put(pfb, &mem);
@@ -310,14 +304,14 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
} while (max);
mutex_unlock(&pfb->base.mutex);
- r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
+ r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry);
mem->offset = (u64)r->offset << 12;
*pmem = mem;
return 0;
}
static u32
-nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram)
+nv50_fb_vram_rblock(struct nvkm_fb *pfb, struct nvkm_ram *ram)
{
int colbits, rowbitsa, rowbitsb, banks;
u64 rowsize, predicted;
@@ -326,8 +320,8 @@ nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram)
r0 = nv_rd32(pfb, 0x100200);
r4 = nv_rd32(pfb, 0x100204);
rt = nv_rd32(pfb, 0x100250);
- nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt,
- nv_rd32(pfb, 0x001540));
+ nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ r0, r4, rt, nv_rd32(pfb, 0x001540));
colbits = (r4 & 0x0000f000) >> 12;
rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
@@ -353,17 +347,17 @@ nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram)
}
int
-nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int length, void **pobject)
+nv50_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
- struct nouveau_bios *bios = nouveau_bios(parent);
- struct nouveau_fb *pfb = nouveau_fb(parent);
- struct nouveau_ram *ram;
+ struct nvkm_bios *bios = nvkm_bios(parent);
+ struct nvkm_fb *pfb = nvkm_fb(parent);
+ struct nvkm_ram *ram;
int ret;
- ret = nouveau_ram_create_(parent, engine, oclass, length, pobject);
+ ret = nvkm_ram_create_(parent, engine, oclass, length, pobject);
ram = *pobject;
if (ret)
return ret;
@@ -377,7 +371,7 @@ nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
switch (nv_rd32(pfb, 0x100714) & 0x00000007) {
case 0: ram->type = NV_MEM_TYPE_DDR1; break;
case 1:
- if (nouveau_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3)
+ if (nvkm_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3)
ram->type = NV_MEM_TYPE_DDR3;
else
ram->type = NV_MEM_TYPE_DDR2;
@@ -389,9 +383,9 @@ nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
break;
}
- ret = nouveau_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) -
- (rsvd_head + rsvd_tail),
- nv50_fb_vram_rblock(pfb, ram) >> 12);
+ ret = nvkm_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) -
+ (rsvd_head + rsvd_tail),
+ nv50_fb_vram_rblock(pfb, ram) >> 12);
if (ret)
return ret;
@@ -403,9 +397,9 @@ nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
}
static int
-nv50_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 datasize,
- struct nouveau_object **pobject)
+nv50_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 datasize,
+ struct nvkm_object **pobject)
{
struct nv50_ram *ram;
int ret, i;
@@ -459,12 +453,12 @@ nv50_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv50_ram_oclass = {
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_ram_ctor,
- .dtor = _nouveau_ram_dtor,
- .init = _nouveau_ram_init,
- .fini = _nouveau_ram_fini,
+ .dtor = _nvkm_ram_dtor,
+ .init = _nvkm_ram_init,
+ .fini = _nvkm_ram_fini,
}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h
index 571077e39071..0f1f97ccd5f6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h
@@ -1,7 +1,5 @@
#ifndef __NVKM_FBRAM_SEQ_H__
#define __NVKM_FBRAM_SEQ_H__
-
-#include <subdev/bus.h>
#include <subdev/bus/hwsq.h>
#define ram_init(s,p) hwsq_init(&(s)->base, (p))
@@ -14,5 +12,4 @@
#define ram_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d))
#define ram_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d))
#define ram_nsec(s,n) hwsq_nsec(&(s)->base, (n))
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h
index 0f7fc0c52ab2..1f865f61504e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h
@@ -1,5 +1,5 @@
-#ifndef __NOUVEAU_FB_REGS_04_H__
-#define __NOUVEAU_FB_REGS_04_H__
+#ifndef __NVKM_FB_REGS_04_H__
+#define __NVKM_FB_REGS_04_H__
#define NV04_PFB_BOOT_0 0x00100000
# define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
@@ -17,5 +17,6 @@
# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028
# define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100
# define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000
+#define NV04_PFB_CFG0 0x00100200
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c
index 252575f3aa29..afab42df28d4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c
@@ -22,7 +22,6 @@
* Authors: Roy Spliet <rspliet@eclipso.eu>
* Ben Skeggs
*/
-
#include "priv.h"
struct ramxlat {
@@ -58,7 +57,7 @@ ramddr2_wr[] = {
};
int
-nouveau_sddr2_calc(struct nouveau_ram *ram)
+nvkm_sddr2_calc(struct nvkm_ram *ram)
{
int CL, WR, DLL = 0, ODT = 0;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c
index a2dca4869e52..10844355c3f3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c
@@ -22,7 +22,6 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
* Roy Spliet <rspliet@eclipso.eu>
*/
-
#include "priv.h"
struct ramxlat {
@@ -67,7 +66,7 @@ ramddr3_cwl[] = {
};
int
-nouveau_sddr3_calc(struct nouveau_ram *ram)
+nvkm_sddr3_calc(struct nvkm_ram *ram)
{
int CWL, CL, WR, DLL = 0, ODT = 0;
From 630ec6c0d31e0d3b2d8aa641f252e83dfa4a9345 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 14:53:51 +1000
Subject: [PATCH 58/86] drm/nouveau/fuse: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 1 +
.../drm/nouveau/include/nvkm/subdev/fuse.h | 36 ++++++++--------
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 28 ++++++-------
.../gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/fuse/base.c | 25 +++++------
.../gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c | 29 ++++++-------
.../gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c | 24 +++++------
.../nvkm/subdev/fuse/{g80.c => nv50.c} | 41 ++++++++-----------
.../gpu/drm/nouveau/nvkm/subdev/fuse/priv.h | 6 +--
9 files changed, 87 insertions(+), 105 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/subdev/fuse/{g80.c => nv50.c} (70%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 9571710e637c..4c16deb1ab7d 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -237,5 +237,6 @@
#define nouveau_fb nvkm_fb
#define nouveau_fb_tile nvkm_fb_tile
#define nvc0_pte_storage_type_map gf100_pte_storage_type_map
+#define nouveau_fuse nvkm_fuse
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h
index cc6b02fec682..a1384786adc9 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h
@@ -1,30 +1,28 @@
-#ifndef __NOUVEAU_FUSE_H__
-#define __NOUVEAU_FUSE_H__
-
+#ifndef __NVKM_FUSE_H__
+#define __NVKM_FUSE_H__
#include <core/subdev.h>
#include <core/device.h>
-struct nouveau_fuse {
- struct nouveau_subdev base;
+struct nvkm_fuse {
+ struct nvkm_subdev base;
};
-static inline struct nouveau_fuse *
-nouveau_fuse(void *obj)
+static inline struct nvkm_fuse *
+nvkm_fuse(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_FUSE);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_FUSE);
}
-#define nouveau_fuse_create(p, e, o, d) \
- nouveau_fuse_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_fuse_create(p, e, o, d) \
+ nvkm_fuse_create_((p), (e), (o), sizeof(**d), (void **)d)
-int nouveau_fuse_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-void _nouveau_fuse_dtor(struct nouveau_object *);
-int _nouveau_fuse_init(struct nouveau_object *);
-#define _nouveau_fuse_fini _nouveau_subdev_fini
-
-extern struct nouveau_oclass g80_fuse_oclass;
-extern struct nouveau_oclass gf100_fuse_oclass;
-extern struct nouveau_oclass gm107_fuse_oclass;
+int nvkm_fuse_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+void _nvkm_fuse_dtor(struct nvkm_object *);
+int _nvkm_fuse_init(struct nvkm_object *);
+#define _nvkm_fuse_fini _nvkm_subdev_fini
+extern struct nvkm_oclass nv50_fuse_oclass;
+extern struct nvkm_oclass gf100_fuse_oclass;
+extern struct nvkm_oclass gm107_fuse_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 393b14cfddfa..aaa2e5bf38c2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -66,7 +66,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = nv50_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
@@ -92,7 +92,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
@@ -121,7 +121,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
@@ -150,7 +150,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
@@ -179,7 +179,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
@@ -208,7 +208,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
@@ -237,7 +237,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
@@ -266,7 +266,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
@@ -295,7 +295,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
@@ -324,7 +324,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
@@ -353,7 +353,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
@@ -384,7 +384,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
@@ -414,7 +414,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
@@ -444,7 +444,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
+ device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild
index 0458bce2ceeb..f3d4e6e131b6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild
@@ -1,4 +1,4 @@
nvkm-y += nvkm/subdev/fuse/base.o
-nvkm-y += nvkm/subdev/fuse/g80.o
+nvkm-y += nvkm/subdev/fuse/nv50.o
nvkm-y += nvkm/subdev/fuse/gf100.o
nvkm-y += nvkm/subdev/fuse/gm107.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c
index 9e8e92127715..b7b7193bbce7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c
@@ -21,34 +21,31 @@
*
* Authors: Martin Peres
*/
-
#include <subdev/fuse.h>
int
-_nouveau_fuse_init(struct nouveau_object *object)
+_nvkm_fuse_init(struct nvkm_object *object)
{
- struct nouveau_fuse *fuse = (void *)object;
- return nouveau_subdev_init(&fuse->base);
+ struct nvkm_fuse *fuse = (void *)object;
+ return nvkm_subdev_init(&fuse->base);
}
void
-_nouveau_fuse_dtor(struct nouveau_object *object)
+_nvkm_fuse_dtor(struct nvkm_object *object)
{
- struct nouveau_fuse *fuse = (void *)object;
- nouveau_subdev_destroy(&fuse->base);
+ struct nvkm_fuse *fuse = (void *)object;
+ nvkm_subdev_destroy(&fuse->base);
}
int
-nouveau_fuse_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int length, void **pobject)
+nvkm_fuse_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
- struct nouveau_fuse *fuse;
+ struct nvkm_fuse *fuse;
int ret;
- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "FUSE",
- "fuse", length, pobject);
+ ret = nvkm_subdev_create_(parent, engine, oclass, 0, "FUSE",
+ "fuse", length, pobject);
fuse = *pobject;
-
return ret;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c
index 5ed03f54b3d4..393ef3a0faaf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c
@@ -21,63 +21,58 @@
*
* Authors: Martin Peres
*/
-
#include "priv.h"
struct gf100_fuse_priv {
- struct nouveau_fuse base;
+ struct nvkm_fuse base;
spinlock_t fuse_enable_lock;
};
static u32
-gf100_fuse_rd32(struct nouveau_object *object, u64 addr)
+gf100_fuse_rd32(struct nvkm_object *object, u64 addr)
{
struct gf100_fuse_priv *priv = (void *)object;
unsigned long flags;
u32 fuse_enable, unk, val;
+ /* racy if another part of nvkm start writing to these regs */
spin_lock_irqsave(&priv->fuse_enable_lock, flags);
-
- /* racy if another part of nouveau start writing to these regs */
fuse_enable = nv_mask(priv, 0x22400, 0x800, 0x800);
unk = nv_mask(priv, 0x21000, 0x1, 0x1);
val = nv_rd32(priv, 0x21100 + addr);
nv_wr32(priv, 0x21000, unk);
nv_wr32(priv, 0x22400, fuse_enable);
-
spin_unlock_irqrestore(&priv->fuse_enable_lock, flags);
-
return val;
}
static int
-gf100_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct gf100_fuse_priv *priv;
int ret;
- ret = nouveau_fuse_create(parent, engine, oclass, &priv);
+ ret = nvkm_fuse_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
spin_lock_init(&priv->fuse_enable_lock);
-
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
gf100_fuse_oclass = {
.handle = NV_SUBDEV(FUSE, 0xC0),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_fuse_ctor,
- .dtor = _nouveau_fuse_dtor,
- .init = _nouveau_fuse_init,
- .fini = _nouveau_fuse_fini,
+ .dtor = _nvkm_fuse_dtor,
+ .init = _nvkm_fuse_init,
+ .fini = _nvkm_fuse_fini,
.rd32 = gf100_fuse_rd32,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c
index 4f1a636c6538..ba19158a5912 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c
@@ -21,31 +21,29 @@
*
* Authors: Martin Peres
*/
-
#include "priv.h"
struct gm107_fuse_priv {
- struct nouveau_fuse base;
+ struct nvkm_fuse base;
};
static u32
-gm107_fuse_rd32(struct nouveau_object *object, u64 addr)
+gm107_fuse_rd32(struct nvkm_object *object, u64 addr)
{
struct gf100_fuse_priv *priv = (void *)object;
-
return nv_rd32(priv, 0x21100 + addr);
}
static int
-gm107_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gm107_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct gm107_fuse_priv *priv;
int ret;
- ret = nouveau_fuse_create(parent, engine, oclass, &priv);
+ ret = nvkm_fuse_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -53,14 +51,14 @@ gm107_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
gm107_fuse_oclass = {
.handle = NV_SUBDEV(FUSE, 0x117),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm107_fuse_ctor,
- .dtor = _nouveau_fuse_dtor,
- .init = _nouveau_fuse_init,
- .fini = _nouveau_fuse_fini,
+ .dtor = _nvkm_fuse_dtor,
+ .init = _nvkm_fuse_init,
+ .fini = _nvkm_fuse_fini,
.rd32 = gm107_fuse_rd32,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/g80.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c
similarity index 70%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/fuse/g80.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c
index a374ade485be..0d2afc426100 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/g80.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c
@@ -21,61 +21,56 @@
*
* Authors: Martin Peres
*/
-
#include "priv.h"
-struct g80_fuse_priv {
- struct nouveau_fuse base;
+struct nv50_fuse_priv {
+ struct nvkm_fuse base;
spinlock_t fuse_enable_lock;
};
static u32
-g80_fuse_rd32(struct nouveau_object *object, u64 addr)
+nv50_fuse_rd32(struct nvkm_object *object, u64 addr)
{
- struct g80_fuse_priv *priv = (void *)object;
+ struct nv50_fuse_priv *priv = (void *)object;
unsigned long flags;
u32 fuse_enable, val;
+ /* racy if another part of nvkm start writing to this reg */
spin_lock_irqsave(&priv->fuse_enable_lock, flags);
-
- /* racy if another part of nouveau start writing to this reg */
fuse_enable = nv_mask(priv, 0x1084, 0x800, 0x800);
val = nv_rd32(priv, 0x21000 + addr);
nv_wr32(priv, 0x1084, fuse_enable);
-
spin_unlock_irqrestore(&priv->fuse_enable_lock, flags);
-
return val;
}
static int
-g80_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct g80_fuse_priv *priv;
+ struct nv50_fuse_priv *priv;
int ret;
- ret = nouveau_fuse_create(parent, engine, oclass, &priv);
+ ret = nvkm_fuse_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
spin_lock_init(&priv->fuse_enable_lock);
-
return 0;
}
-struct nouveau_oclass
-g80_fuse_oclass = {
+struct nvkm_oclass
+nv50_fuse_oclass = {
.handle = NV_SUBDEV(FUSE, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = g80_fuse_ctor,
- .dtor = _nouveau_fuse_dtor,
- .init = _nouveau_fuse_init,
- .fini = _nouveau_fuse_fini,
- .rd32 = g80_fuse_rd32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = nv50_fuse_ctor,
+ .dtor = _nvkm_fuse_dtor,
+ .init = _nvkm_fuse_init,
+ .fini = _nvkm_fuse_fini,
+ .rd32 = nv50_fuse_rd32,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h
index d2085411a5cb..7e050f789384 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h
@@ -1,9 +1,7 @@
#ifndef __NVKM_FUSE_PRIV_H__
#define __NVKM_FUSE_PRIV_H__
-
#include <subdev/fuse.h>
-int _nouveau_fuse_init(struct nouveau_object *object);
-void _nouveau_fuse_dtor(struct nouveau_object *object);
-
+int _nvkm_fuse_init(struct nvkm_object *object);
+void _nvkm_fuse_dtor(struct nvkm_object *object);
#endif
From 4e7659fc5b54925964142988a2f6888cd35c893e Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:02:59 +1000
Subject: [PATCH 59/86] drm/nouveau/gpio: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/subdev/gpio.h | 35 +++---
.../drm/nouveau/nvkm/engine/device/gm100.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 20 +--
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +--
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 +--
.../gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild | 6 +-
.../gpu/drm/nouveau/nvkm/subdev/gpio/base.c | 119 +++++++++---------
.../nvkm/subdev/gpio/{nv94.c => g94.c} | 23 ++--
.../nvkm/subdev/gpio/{nvd0.c => gf110.c} | 33 +++--
.../nvkm/subdev/gpio/{nve0.c => gk104.c} | 29 +++--
.../gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c | 23 ++--
.../gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c | 27 ++--
.../gpu/drm/nouveau/nvkm/subdev/gpio/priv.h | 75 ++++++-----
13 files changed, 205 insertions(+), 221 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/subdev/gpio/{nv94.c => g94.c} (82%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/gpio/{nvd0.c => gf110.c} (77%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/gpio/{nve0.c => gk104.c} (79%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
index 8b60c5de6cb9..ca5099a81b5a 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
@@ -1,8 +1,6 @@
-#ifndef __NOUVEAU_GPIO_H__
-#define __NOUVEAU_GPIO_H__
-
+#ifndef __NVKM_GPIO_H__
+#define __NVKM_GPIO_H__
#include <core/subdev.h>
-#include <core/device.h>
#include <core/event.h>
#include <subdev/bios.h>
@@ -20,28 +18,27 @@ struct nvkm_gpio_ntfy_rep {
u8 mask;
};
-struct nouveau_gpio {
- struct nouveau_subdev base;
+struct nvkm_gpio {
+ struct nvkm_subdev base;
struct nvkm_event event;
- void (*reset)(struct nouveau_gpio *, u8 func);
- int (*find)(struct nouveau_gpio *, int idx, u8 tag, u8 line,
+ void (*reset)(struct nvkm_gpio *, u8 func);
+ int (*find)(struct nvkm_gpio *, int idx, u8 tag, u8 line,
struct dcb_gpio_func *);
- int (*set)(struct nouveau_gpio *, int idx, u8 tag, u8 line, int state);
- int (*get)(struct nouveau_gpio *, int idx, u8 tag, u8 line);
+ int (*set)(struct nvkm_gpio *, int idx, u8 tag, u8 line, int state);
+ int (*get)(struct nvkm_gpio *, int idx, u8 tag, u8 line);
};
-static inline struct nouveau_gpio *
-nouveau_gpio(void *obj)
+static inline struct nvkm_gpio *
+nvkm_gpio(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_GPIO);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_GPIO);
}
-extern struct nouveau_oclass *nv10_gpio_oclass;
-extern struct nouveau_oclass *nv50_gpio_oclass;
-extern struct nouveau_oclass *nv94_gpio_oclass;
-extern struct nouveau_oclass *nvd0_gpio_oclass;
-extern struct nouveau_oclass *nve0_gpio_oclass;
-
+extern struct nvkm_oclass *nv10_gpio_oclass;
+extern struct nvkm_oclass *nv50_gpio_oclass;
+extern struct nvkm_oclass *g94_gpio_oclass;
+extern struct nvkm_oclass *gf110_gpio_oclass;
+extern struct nvkm_oclass *gk104_gpio_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 6dc59ffee68a..f27932ea6196 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -62,7 +62,7 @@ gm100_identify(struct nouveau_device *device)
case 0x117:
device->cname = "GM107";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
@@ -102,7 +102,7 @@ gm100_identify(struct nouveau_device *device)
case 0x124:
device->cname = "GM204";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
#if 0
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index aaa2e5bf38c2..747651747b16 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -177,7 +177,7 @@ nv50_identify(struct nouveau_device *device)
case 0x94:
device->cname = "G94";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
@@ -206,7 +206,7 @@ nv50_identify(struct nouveau_device *device)
case 0x96:
device->cname = "G96";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
@@ -235,7 +235,7 @@ nv50_identify(struct nouveau_device *device)
case 0x98:
device->cname = "G98";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
@@ -264,7 +264,7 @@ nv50_identify(struct nouveau_device *device)
case 0xa0:
device->cname = "G200";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
@@ -293,7 +293,7 @@ nv50_identify(struct nouveau_device *device)
case 0xaa:
device->cname = "MCP77/MCP78";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
@@ -322,7 +322,7 @@ nv50_identify(struct nouveau_device *device)
case 0xac:
device->cname = "MCP79/MCP7A";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
@@ -351,7 +351,7 @@ nv50_identify(struct nouveau_device *device)
case 0xa3:
device->cname = "GT215";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
@@ -382,7 +382,7 @@ nv50_identify(struct nouveau_device *device)
case 0xa5:
device->cname = "GT216";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
@@ -412,7 +412,7 @@ nv50_identify(struct nouveau_device *device)
case 0xa8:
device->cname = "GT218";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
@@ -442,7 +442,7 @@ nv50_identify(struct nouveau_device *device)
case 0xaf:
device->cname = "MCP89";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index fc71b6705083..5a67aad4f8f9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -62,7 +62,7 @@ nvc0_identify(struct nouveau_device *device)
case 0xc0:
device->cname = "GF100";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
@@ -95,7 +95,7 @@ nvc0_identify(struct nouveau_device *device)
case 0xc4:
device->cname = "GF104";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
@@ -128,7 +128,7 @@ nvc0_identify(struct nouveau_device *device)
case 0xc3:
device->cname = "GF106";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
@@ -160,7 +160,7 @@ nvc0_identify(struct nouveau_device *device)
case 0xce:
device->cname = "GF114";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
@@ -193,7 +193,7 @@ nvc0_identify(struct nouveau_device *device)
case 0xcf:
device->cname = "GF116";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
@@ -225,7 +225,7 @@ nvc0_identify(struct nouveau_device *device)
case 0xc1:
device->cname = "GF108";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
@@ -257,7 +257,7 @@ nvc0_identify(struct nouveau_device *device)
case 0xc8:
device->cname = "GF110";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
@@ -290,7 +290,7 @@ nvc0_identify(struct nouveau_device *device)
case 0xd9:
device->cname = "GF119";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
@@ -322,7 +322,7 @@ nvc0_identify(struct nouveau_device *device)
case 0xd7:
device->cname = "GF117";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index ca6b2a6f124c..024059aea4fd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -62,7 +62,7 @@ nve0_identify(struct nouveau_device *device)
case 0xe4:
device->cname = "GK104";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
@@ -96,7 +96,7 @@ nve0_identify(struct nouveau_device *device)
case 0xe7:
device->cname = "GK107";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
@@ -130,7 +130,7 @@ nve0_identify(struct nouveau_device *device)
case 0xe6:
device->cname = "GK106";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
@@ -186,7 +186,7 @@ nve0_identify(struct nouveau_device *device)
case 0xf0:
device->cname = "GK110";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
@@ -220,7 +220,7 @@ nve0_identify(struct nouveau_device *device)
case 0xf1:
device->cname = "GK110B";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
@@ -254,7 +254,7 @@ nve0_identify(struct nouveau_device *device)
case 0x106:
device->cname = "GK208B";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
@@ -287,7 +287,7 @@ nve0_identify(struct nouveau_device *device)
case 0x108:
device->cname = "GK208";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
+ device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild
index 77bc88672af6..ea42a9ed1821 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild
@@ -1,6 +1,6 @@
nvkm-y += nvkm/subdev/gpio/base.o
nvkm-y += nvkm/subdev/gpio/nv10.o
nvkm-y += nvkm/subdev/gpio/nv50.o
-nvkm-y += nvkm/subdev/gpio/nv94.o
-nvkm-y += nvkm/subdev/gpio/nvd0.o
-nvkm-y += nvkm/subdev/gpio/nve0.o
+nvkm-y += nvkm/subdev/gpio/g94.o
+nvkm-y += nvkm/subdev/gpio/gf110.o
+nvkm-y += nvkm/subdev/gpio/gk104.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
index 98d79298cb07..dea58161ba46 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
@@ -21,33 +21,30 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/notify.h>
-#include <subdev/bios.h>
-#include <subdev/bios/gpio.h>
-
#include "priv.h"
+#include <core/device.h>
+#include <core/notify.h>
+
static int
-nouveau_gpio_drive(struct nouveau_gpio *gpio,
- int idx, int line, int dir, int out)
+nvkm_gpio_drive(struct nvkm_gpio *gpio, int idx, int line, int dir, int out)
{
- const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
+ const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
return impl->drive ? impl->drive(gpio, line, dir, out) : -ENODEV;
}
static int
-nouveau_gpio_sense(struct nouveau_gpio *gpio, int idx, int line)
+nvkm_gpio_sense(struct nvkm_gpio *gpio, int idx, int line)
{
- const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
+ const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
return impl->sense ? impl->sense(gpio, line) : -ENODEV;
}
static int
-nouveau_gpio_find(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line,
- struct dcb_gpio_func *func)
+nvkm_gpio_find(struct nvkm_gpio *gpio, int idx, u8 tag, u8 line,
+ struct dcb_gpio_func *func)
{
- struct nouveau_bios *bios = nouveau_bios(gpio);
+ struct nvkm_bios *bios = nvkm_bios(gpio);
u8 ver, len;
u16 data;
@@ -75,30 +72,30 @@ nouveau_gpio_find(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line,
}
static int
-nouveau_gpio_set(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line, int state)
+nvkm_gpio_set(struct nvkm_gpio *gpio, int idx, u8 tag, u8 line, int state)
{
struct dcb_gpio_func func;
int ret;
- ret = nouveau_gpio_find(gpio, idx, tag, line, &func);
+ ret = nvkm_gpio_find(gpio, idx, tag, line, &func);
if (ret == 0) {
int dir = !!(func.log[state] & 0x02);
int out = !!(func.log[state] & 0x01);
- ret = nouveau_gpio_drive(gpio, idx, func.line, dir, out);
+ ret = nvkm_gpio_drive(gpio, idx, func.line, dir, out);
}
return ret;
}
static int
-nouveau_gpio_get(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line)
+nvkm_gpio_get(struct nvkm_gpio *gpio, int idx, u8 tag, u8 line)
{
struct dcb_gpio_func func;
int ret;
- ret = nouveau_gpio_find(gpio, idx, tag, line, &func);
+ ret = nvkm_gpio_find(gpio, idx, tag, line, &func);
if (ret == 0) {
- ret = nouveau_gpio_sense(gpio, idx, func.line);
+ ret = nvkm_gpio_sense(gpio, idx, func.line);
if (ret >= 0)
ret = (ret == (func.log[1] & 1));
}
@@ -107,24 +104,24 @@ nouveau_gpio_get(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line)
}
static void
-nouveau_gpio_intr_fini(struct nvkm_event *event, int type, int index)
+nvkm_gpio_intr_fini(struct nvkm_event *event, int type, int index)
{
- struct nouveau_gpio *gpio = container_of(event, typeof(*gpio), event);
- const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
+ struct nvkm_gpio *gpio = container_of(event, typeof(*gpio), event);
+ const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
impl->intr_mask(gpio, type, 1 << index, 0);
}
static void
-nouveau_gpio_intr_init(struct nvkm_event *event, int type, int index)
+nvkm_gpio_intr_init(struct nvkm_event *event, int type, int index)
{
- struct nouveau_gpio *gpio = container_of(event, typeof(*gpio), event);
- const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
+ struct nvkm_gpio *gpio = container_of(event, typeof(*gpio), event);
+ const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
impl->intr_mask(gpio, type, 1 << index, 1 << index);
}
static int
-nouveau_gpio_intr_ctor(struct nouveau_object *object, void *data, u32 size,
- struct nvkm_notify *notify)
+nvkm_gpio_intr_ctor(struct nvkm_object *object, void *data, u32 size,
+ struct nvkm_notify *notify)
{
struct nvkm_gpio_ntfy_req *req = data;
if (!WARN_ON(size != sizeof(*req))) {
@@ -137,10 +134,10 @@ nouveau_gpio_intr_ctor(struct nouveau_object *object, void *data, u32 size,
}
static void
-nouveau_gpio_intr(struct nouveau_subdev *subdev)
+nvkm_gpio_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_gpio *gpio = nouveau_gpio(subdev);
- const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
+ struct nvkm_gpio *gpio = nvkm_gpio(subdev);
+ const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass;
u32 hi, lo, i;
impl->intr_stat(gpio, &hi, &lo);
@@ -155,23 +152,23 @@ nouveau_gpio_intr(struct nouveau_subdev *subdev)
}
static const struct nvkm_event_func
-nouveau_gpio_intr_func = {
- .ctor = nouveau_gpio_intr_ctor,
- .init = nouveau_gpio_intr_init,
- .fini = nouveau_gpio_intr_fini,
+nvkm_gpio_intr_func = {
+ .ctor = nvkm_gpio_intr_ctor,
+ .init = nvkm_gpio_intr_init,
+ .fini = nvkm_gpio_intr_fini,
};
int
-_nouveau_gpio_fini(struct nouveau_object *object, bool suspend)
+_nvkm_gpio_fini(struct nvkm_object *object, bool suspend)
{
- const struct nouveau_gpio_impl *impl = (void *)object->oclass;
- struct nouveau_gpio *gpio = nouveau_gpio(object);
+ const struct nvkm_gpio_impl *impl = (void *)object->oclass;
+ struct nvkm_gpio *gpio = nvkm_gpio(object);
u32 mask = (1 << impl->lines) - 1;
impl->intr_mask(gpio, NVKM_GPIO_TOGGLED, mask, 0);
impl->intr_stat(gpio, &mask, &mask);
- return nouveau_subdev_fini(&gpio->base, suspend);
+ return nvkm_subdev_fini(&gpio->base, suspend);
}
static struct dmi_system_id gpio_reset_ids[] = {
@@ -186,12 +183,12 @@ static struct dmi_system_id gpio_reset_ids[] = {
};
int
-_nouveau_gpio_init(struct nouveau_object *object)
+_nvkm_gpio_init(struct nvkm_object *object)
{
- struct nouveau_gpio *gpio = nouveau_gpio(object);
+ struct nvkm_gpio *gpio = nvkm_gpio(object);
int ret;
- ret = nouveau_subdev_init(&gpio->base);
+ ret = nvkm_subdev_init(&gpio->base);
if (ret)
return ret;
@@ -202,52 +199,50 @@ _nouveau_gpio_init(struct nouveau_object *object)
}
void
-_nouveau_gpio_dtor(struct nouveau_object *object)
+_nvkm_gpio_dtor(struct nvkm_object *object)
{
- struct nouveau_gpio *gpio = (void *)object;
+ struct nvkm_gpio *gpio = (void *)object;
nvkm_event_fini(&gpio->event);
- nouveau_subdev_destroy(&gpio->base);
+ nvkm_subdev_destroy(&gpio->base);
}
int
-nouveau_gpio_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass,
- int length, void **pobject)
+nvkm_gpio_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
- const struct nouveau_gpio_impl *impl = (void *)oclass;
- struct nouveau_gpio *gpio;
+ const struct nvkm_gpio_impl *impl = (void *)oclass;
+ struct nvkm_gpio *gpio;
int ret;
- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "GPIO", "gpio",
- length, pobject);
+ ret = nvkm_subdev_create_(parent, engine, oclass, 0, "GPIO",
+ "gpio", length, pobject);
gpio = *pobject;
if (ret)
return ret;
- gpio->find = nouveau_gpio_find;
- gpio->set = nouveau_gpio_set;
- gpio->get = nouveau_gpio_get;
+ gpio->find = nvkm_gpio_find;
+ gpio->set = nvkm_gpio_set;
+ gpio->get = nvkm_gpio_get;
gpio->reset = impl->reset;
- ret = nvkm_event_init(&nouveau_gpio_intr_func, 2, impl->lines,
+ ret = nvkm_event_init(&nvkm_gpio_intr_func, 2, impl->lines,
&gpio->event);
if (ret)
return ret;
- nv_subdev(gpio)->intr = nouveau_gpio_intr;
+ nv_subdev(gpio)->intr = nvkm_gpio_intr;
return 0;
}
int
-_nouveau_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+_nvkm_gpio_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_gpio *gpio;
+ struct nvkm_gpio *gpio;
int ret;
- ret = nouveau_gpio_create(parent, engine, oclass, &gpio);
+ ret = nvkm_gpio_create(parent, engine, oclass, &gpio);
*pobject = nv_object(gpio);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c
similarity index 82%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv94.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c
index cae404ccadac..12b3e01fca8e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv94.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c
@@ -21,11 +21,10 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
void
-nv94_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
+g94_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
{
u32 intr0 = nv_rd32(gpio, 0x00e054);
u32 intr1 = nv_rd32(gpio, 0x00e074);
@@ -38,7 +37,7 @@ nv94_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
}
void
-nv94_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
+g94_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
{
u32 inte0 = nv_rd32(gpio, 0x00e050);
u32 inte1 = nv_rd32(gpio, 0x00e070);
@@ -56,18 +55,18 @@ nv94_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
nv_wr32(gpio, 0x00e070, inte1);
}
-struct nouveau_oclass *
-nv94_gpio_oclass = &(struct nouveau_gpio_impl) {
+struct nvkm_oclass *
+g94_gpio_oclass = &(struct nvkm_gpio_impl) {
.base.handle = NV_SUBDEV(GPIO, 0x94),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_gpio_ctor,
- .dtor = _nouveau_gpio_dtor,
- .init = _nouveau_gpio_init,
- .fini = _nouveau_gpio_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_gpio_ctor,
+ .dtor = _nvkm_gpio_dtor,
+ .init = _nvkm_gpio_init,
+ .fini = _nvkm_gpio_fini,
},
.lines = 32,
- .intr_stat = nv94_gpio_intr_stat,
- .intr_mask = nv94_gpio_intr_mask,
+ .intr_stat = g94_gpio_intr_stat,
+ .intr_mask = g94_gpio_intr_mask,
.drive = nv50_gpio_drive,
.sense = nv50_gpio_sense,
.reset = nv50_gpio_reset,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf110.c
similarity index 77%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf110.c
index 480d6d2af770..2c3bb255d1f8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nvd0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf110.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
void
-nvd0_gpio_reset(struct nouveau_gpio *gpio, u8 match)
+gf110_gpio_reset(struct nvkm_gpio *gpio, u8 match)
{
- struct nouveau_bios *bios = nouveau_bios(gpio);
+ struct nvkm_bios *bios = nvkm_bios(gpio);
u8 ver, len;
u16 entry;
int ent = -1;
@@ -53,7 +52,7 @@ nvd0_gpio_reset(struct nouveau_gpio *gpio, u8 match)
}
int
-nvd0_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
+gf110_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)
{
u32 data = ((dir ^ 1) << 13) | (out << 12);
nv_mask(gpio, 0x00d610 + (line * 4), 0x00003000, data);
@@ -62,24 +61,24 @@ nvd0_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
}
int
-nvd0_gpio_sense(struct nouveau_gpio *gpio, int line)
+gf110_gpio_sense(struct nvkm_gpio *gpio, int line)
{
return !!(nv_rd32(gpio, 0x00d610 + (line * 4)) & 0x00004000);
}
-struct nouveau_oclass *
-nvd0_gpio_oclass = &(struct nouveau_gpio_impl) {
+struct nvkm_oclass *
+gf110_gpio_oclass = &(struct nvkm_gpio_impl) {
.base.handle = NV_SUBDEV(GPIO, 0xd0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_gpio_ctor,
- .dtor = _nouveau_gpio_dtor,
- .init = _nouveau_gpio_init,
- .fini = _nouveau_gpio_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_gpio_ctor,
+ .dtor = _nvkm_gpio_dtor,
+ .init = _nvkm_gpio_init,
+ .fini = _nvkm_gpio_fini,
},
.lines = 32,
- .intr_stat = nv94_gpio_intr_stat,
- .intr_mask = nv94_gpio_intr_mask,
- .drive = nvd0_gpio_drive,
- .sense = nvd0_gpio_sense,
- .reset = nvd0_gpio_reset,
+ .intr_stat = g94_gpio_intr_stat,
+ .intr_mask = g94_gpio_intr_mask,
+ .drive = gf110_gpio_drive,
+ .sense = gf110_gpio_sense,
+ .reset = gf110_gpio_reset,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c
similarity index 79%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c
index e1145b48c76c..42fd2faaaa4f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c
@@ -21,11 +21,10 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
static void
-nve0_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
+gk104_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
{
u32 intr0 = nv_rd32(gpio, 0x00dc00);
u32 intr1 = nv_rd32(gpio, 0x00dc80);
@@ -38,7 +37,7 @@ nve0_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
}
void
-nve0_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
+gk104_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
{
u32 inte0 = nv_rd32(gpio, 0x00dc08);
u32 inte1 = nv_rd32(gpio, 0x00dc88);
@@ -56,19 +55,19 @@ nve0_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
nv_wr32(gpio, 0x00dc88, inte1);
}
-struct nouveau_oclass *
-nve0_gpio_oclass = &(struct nouveau_gpio_impl) {
+struct nvkm_oclass *
+gk104_gpio_oclass = &(struct nvkm_gpio_impl) {
.base.handle = NV_SUBDEV(GPIO, 0xe0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_gpio_ctor,
- .dtor = _nouveau_gpio_dtor,
- .init = _nouveau_gpio_init,
- .fini = _nouveau_gpio_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_gpio_ctor,
+ .dtor = _nvkm_gpio_dtor,
+ .init = _nvkm_gpio_init,
+ .fini = _nvkm_gpio_fini,
},
.lines = 32,
- .intr_stat = nve0_gpio_intr_stat,
- .intr_mask = nve0_gpio_intr_mask,
- .drive = nvd0_gpio_drive,
- .sense = nvd0_gpio_sense,
- .reset = nvd0_gpio_reset,
+ .intr_stat = gk104_gpio_intr_stat,
+ .intr_mask = gk104_gpio_intr_mask,
+ .drive = gf110_gpio_drive,
+ .sense = gf110_gpio_sense,
+ .reset = gf110_gpio_reset,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c
index 27ad23eaf185..2b295154247e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c
@@ -23,11 +23,10 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
-
#include "priv.h"
static int
-nv10_gpio_sense(struct nouveau_gpio *gpio, int line)
+nv10_gpio_sense(struct nvkm_gpio *gpio, int line)
{
if (line < 2) {
line = line * 16;
@@ -49,7 +48,7 @@ nv10_gpio_sense(struct nouveau_gpio *gpio, int line)
}
static int
-nv10_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
+nv10_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)
{
u32 reg, mask, data;
@@ -79,7 +78,7 @@ nv10_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
}
static void
-nv10_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
+nv10_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
{
u32 intr = nv_rd32(gpio, 0x001104);
u32 stat = nv_rd32(gpio, 0x001144) & intr;
@@ -89,7 +88,7 @@ nv10_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
}
static void
-nv10_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
+nv10_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
{
u32 inte = nv_rd32(gpio, 0x001144);
if (type & NVKM_GPIO_LO)
@@ -99,14 +98,14 @@ nv10_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
nv_wr32(gpio, 0x001144, inte);
}
-struct nouveau_oclass *
-nv10_gpio_oclass = &(struct nouveau_gpio_impl) {
+struct nvkm_oclass *
+nv10_gpio_oclass = &(struct nvkm_gpio_impl) {
.base.handle = NV_SUBDEV(GPIO, 0x10),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_gpio_ctor,
- .dtor = _nouveau_gpio_dtor,
- .init = _nouveau_gpio_init,
- .fini = _nouveau_gpio_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_gpio_ctor,
+ .dtor = _nvkm_gpio_dtor,
+ .init = _nvkm_gpio_init,
+ .fini = _nvkm_gpio_fini,
},
.lines = 16,
.intr_stat = nv10_gpio_intr_stat,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c
index 2e30d5a62d6e..6a031035bd27 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
void
-nv50_gpio_reset(struct nouveau_gpio *gpio, u8 match)
+nv50_gpio_reset(struct nvkm_gpio *gpio, u8 match)
{
- struct nouveau_bios *bios = nouveau_bios(gpio);
+ struct nvkm_bios *bios = nvkm_bios(gpio);
u8 ver, len;
u16 entry;
int ent = -1;
@@ -68,7 +67,7 @@ nv50_gpio_location(int line, u32 *reg, u32 *shift)
}
int
-nv50_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
+nv50_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)
{
u32 reg, shift;
@@ -80,7 +79,7 @@ nv50_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
}
int
-nv50_gpio_sense(struct nouveau_gpio *gpio, int line)
+nv50_gpio_sense(struct nvkm_gpio *gpio, int line)
{
u32 reg, shift;
@@ -91,7 +90,7 @@ nv50_gpio_sense(struct nouveau_gpio *gpio, int line)
}
static void
-nv50_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
+nv50_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
{
u32 intr = nv_rd32(gpio, 0x00e054);
u32 stat = nv_rd32(gpio, 0x00e050) & intr;
@@ -101,7 +100,7 @@ nv50_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
}
static void
-nv50_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
+nv50_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
{
u32 inte = nv_rd32(gpio, 0x00e050);
if (type & NVKM_GPIO_LO)
@@ -111,14 +110,14 @@ nv50_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
nv_wr32(gpio, 0x00e050, inte);
}
-struct nouveau_oclass *
-nv50_gpio_oclass = &(struct nouveau_gpio_impl) {
+struct nvkm_oclass *
+nv50_gpio_oclass = &(struct nvkm_gpio_impl) {
.base.handle = NV_SUBDEV(GPIO, 0x50),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_gpio_ctor,
- .dtor = _nouveau_gpio_dtor,
- .init = _nouveau_gpio_init,
- .fini = _nouveau_gpio_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_gpio_ctor,
+ .dtor = _nvkm_gpio_dtor,
+ .init = _nvkm_gpio_init,
+ .fini = _nvkm_gpio_fini,
},
.lines = 16,
.intr_stat = nv50_gpio_intr_stat,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h
index bff98b86e2b5..382f8d44e140 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h
@@ -1,67 +1,64 @@
-#ifndef __NVKM_GPIO_H__
-#define __NVKM_GPIO_H__
-
+#ifndef __NVKM_GPIO_PRIV_H__
+#define __NVKM_GPIO_PRIV_H__
#include <subdev/gpio.h>
-#define nouveau_gpio_create(p,e,o,d) \
- nouveau_gpio_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_gpio_destroy(p) ({ \
- struct nouveau_gpio *gpio = (p); \
- _nouveau_gpio_dtor(nv_object(gpio)); \
+#define nvkm_gpio_create(p,e,o,d) \
+ nvkm_gpio_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_gpio_destroy(p) ({ \
+ struct nvkm_gpio *gpio = (p); \
+ _nvkm_gpio_dtor(nv_object(gpio)); \
})
-#define nouveau_gpio_init(p) ({ \
- struct nouveau_gpio *gpio = (p); \
- _nouveau_gpio_init(nv_object(gpio)); \
+#define nvkm_gpio_init(p) ({ \
+ struct nvkm_gpio *gpio = (p); \
+ _nvkm_gpio_init(nv_object(gpio)); \
})
-#define nouveau_gpio_fini(p,s) ({ \
- struct nouveau_gpio *gpio = (p); \
- _nouveau_gpio_fini(nv_object(gpio), (s)); \
+#define nvkm_gpio_fini(p,s) ({ \
+ struct nvkm_gpio *gpio = (p); \
+ _nvkm_gpio_fini(nv_object(gpio), (s)); \
})
-int nouveau_gpio_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-int _nouveau_gpio_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void _nouveau_gpio_dtor(struct nouveau_object *);
-int _nouveau_gpio_init(struct nouveau_object *);
-int _nouveau_gpio_fini(struct nouveau_object *, bool);
+int nvkm_gpio_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+int _nvkm_gpio_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void _nvkm_gpio_dtor(struct nvkm_object *);
+int _nvkm_gpio_init(struct nvkm_object *);
+int _nvkm_gpio_fini(struct nvkm_object *, bool);
-struct nouveau_gpio_impl {
- struct nouveau_oclass base;
+struct nvkm_gpio_impl {
+ struct nvkm_oclass base;
int lines;
/* read and ack pending interrupts, returning only data
* for lines that have not been masked off, while still
* performing the ack for anything that was pending.
*/
- void (*intr_stat)(struct nouveau_gpio *, u32 *, u32 *);
+ void (*intr_stat)(struct nvkm_gpio *, u32 *, u32 *);
/* mask on/off interrupts for hi/lo transitions on a
* given set of gpio lines
*/
- void (*intr_mask)(struct nouveau_gpio *, u32, u32, u32);
+ void (*intr_mask)(struct nvkm_gpio *, u32, u32, u32);
/* configure gpio direction and output value */
- int (*drive)(struct nouveau_gpio *, int line, int dir, int out);
+ int (*drive)(struct nvkm_gpio *, int line, int dir, int out);
/* sense current state of given gpio line */
- int (*sense)(struct nouveau_gpio *, int line);
+ int (*sense)(struct nvkm_gpio *, int line);
/*XXX*/
- void (*reset)(struct nouveau_gpio *, u8);
+ void (*reset)(struct nvkm_gpio *, u8);
};
-void nv50_gpio_reset(struct nouveau_gpio *, u8);
-int nv50_gpio_drive(struct nouveau_gpio *, int, int, int);
-int nv50_gpio_sense(struct nouveau_gpio *, int);
-
-void nv94_gpio_intr_stat(struct nouveau_gpio *, u32 *, u32 *);
-void nv94_gpio_intr_mask(struct nouveau_gpio *, u32, u32, u32);
-
-void nvd0_gpio_reset(struct nouveau_gpio *, u8);
-int nvd0_gpio_drive(struct nouveau_gpio *, int, int, int);
-int nvd0_gpio_sense(struct nouveau_gpio *, int);
+void nv50_gpio_reset(struct nvkm_gpio *, u8);
+int nv50_gpio_drive(struct nvkm_gpio *, int, int, int);
+int nv50_gpio_sense(struct nvkm_gpio *, int);
+void g94_gpio_intr_stat(struct nvkm_gpio *, u32 *, u32 *);
+void g94_gpio_intr_mask(struct nvkm_gpio *, u32, u32, u32);
+void gf110_gpio_reset(struct nvkm_gpio *, u8);
+int gf110_gpio_drive(struct nvkm_gpio *, int, int, int);
+int gf110_gpio_sense(struct nvkm_gpio *, int);
#endif
From b9ec14246dc4260294ccfb25ec40b113d23e5b9a Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:04:16 +1000
Subject: [PATCH 60/86] drm/nouveau/i2c: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 1 +
.../gpu/drm/nouveau/include/nvkm/subdev/i2c.h | 91 +++---
.../drm/nouveau/nvkm/engine/device/gm100.c | 2 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 16 +-
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 +-
.../gpu/drm/nouveau/nvkm/subdev/bios/init.c | 2 +
.../gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild | 8 +-
.../gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c | 70 ++--
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c | 15 +-
.../gpu/drm/nouveau/nvkm/subdev/i2c/base.c | 307 +++++++++---------
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c | 37 +--
.../nouveau/nvkm/subdev/i2c/{nv94.c => g94.c} | 89 +++--
.../nvkm/subdev/i2c/{nvd0.c => gf110.c} | 72 ++--
.../gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c | 17 +-
.../nvkm/subdev/i2c/{nve0.c => gk104.c} | 27 +-
.../gpu/drm/nouveau/nvkm/subdev/i2c/gm204.c | 60 ++--
.../gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c | 60 ++--
.../gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c | 60 ++--
.../gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c | 58 ++--
.../gpu/drm/nouveau/nvkm/subdev/i2c/nv50.h | 32 +-
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.c | 27 +-
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h | 28 +-
.../nvkm/subdev/i2c/{padnv94.c => padg94.c} | 35 +-
.../drm/nouveau/nvkm/subdev/i2c/padgm204.c | 19 +-
.../gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.c | 5 +-
.../gpu/drm/nouveau/nvkm/subdev/i2c/port.h | 4 +-
.../gpu/drm/nouveau/nvkm/subdev/i2c/priv.h | 110 +++----
28 files changed, 622 insertions(+), 662 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/subdev/i2c/{nv94.c => g94.c} (76%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/i2c/{nvd0.c => gf110.c} (58%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/i2c/{nve0.c => gk104.c} (79%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/i2c/{padnv94.c => padg94.c} (73%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 4c16deb1ab7d..58f8d8bf2f8e 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -196,6 +196,7 @@
#define nouveau_gpio nvkm_gpio
#define nouveau_i2c nvkm_i2c
#define nouveau_i2c_port nvkm_i2c_port
+#define nouveau_i2c_board_info nvkm_i2c_board_info
#define nouveau_devinit nvkm_devinit
#define nouveau_bios nvkm_bios
#define nouveau_bios_oclass nvkm_bios_oclass
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
index a400e67f2d43..a2e33730f05e 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
@@ -1,8 +1,7 @@
-#ifndef __NOUVEAU_I2C_H__
-#define __NOUVEAU_I2C_H__
-
+#ifndef __NVKM_I2C_H__
+#define __NVKM_I2C_H__
#include <core/subdev.h>
-#include <core/device.h>
+#include <core/event.h>
#include <subdev/bios.h>
#include <subdev/bios/i2c.h>
@@ -30,8 +29,8 @@ struct nvkm_i2c_ntfy_rep {
u8 mask;
};
-struct nouveau_i2c_port {
- struct nouveau_object base;
+struct nvkm_i2c_port {
+ struct nvkm_object base;
struct i2c_adapter adapter;
struct mutex mutex;
@@ -39,62 +38,63 @@ struct nouveau_i2c_port {
u8 index;
int aux;
- const struct nouveau_i2c_func *func;
+ const struct nvkm_i2c_func *func;
};
-struct nouveau_i2c_func {
- void (*drive_scl)(struct nouveau_i2c_port *, int);
- void (*drive_sda)(struct nouveau_i2c_port *, int);
- int (*sense_scl)(struct nouveau_i2c_port *);
- int (*sense_sda)(struct nouveau_i2c_port *);
+struct nvkm_i2c_func {
+ void (*drive_scl)(struct nvkm_i2c_port *, int);
+ void (*drive_sda)(struct nvkm_i2c_port *, int);
+ int (*sense_scl)(struct nvkm_i2c_port *);
+ int (*sense_sda)(struct nvkm_i2c_port *);
- int (*aux)(struct nouveau_i2c_port *, bool, u8, u32, u8 *, u8);
- int (*pattern)(struct nouveau_i2c_port *, int pattern);
- int (*lnk_ctl)(struct nouveau_i2c_port *, int nr, int bw, bool enh);
- int (*drv_ctl)(struct nouveau_i2c_port *, int lane, int sw, int pe);
+ int (*aux)(struct nvkm_i2c_port *, bool, u8, u32, u8 *, u8);
+ int (*pattern)(struct nvkm_i2c_port *, int pattern);
+ int (*lnk_ctl)(struct nvkm_i2c_port *, int nr, int bw, bool enh);
+ int (*drv_ctl)(struct nvkm_i2c_port *, int lane, int sw, int pe);
};
-struct nouveau_i2c_board_info {
+struct nvkm_i2c_board_info {
struct i2c_board_info dev;
u8 udelay; /* set to 0 to use the standard delay */
};
-struct nouveau_i2c {
- struct nouveau_subdev base;
+struct nvkm_i2c {
+ struct nvkm_subdev base;
struct nvkm_event event;
- struct nouveau_i2c_port *(*find)(struct nouveau_i2c *, u8 index);
- struct nouveau_i2c_port *(*find_type)(struct nouveau_i2c *, u16 type);
- int (*acquire_pad)(struct nouveau_i2c_port *, unsigned long timeout);
- void (*release_pad)(struct nouveau_i2c_port *);
- int (*acquire)(struct nouveau_i2c_port *, unsigned long timeout);
- void (*release)(struct nouveau_i2c_port *);
- int (*identify)(struct nouveau_i2c *, int index,
- const char *what, struct nouveau_i2c_board_info *,
- bool (*match)(struct nouveau_i2c_port *,
- struct i2c_board_info *, void *), void *);
+ struct nvkm_i2c_port *(*find)(struct nvkm_i2c *, u8 index);
+ struct nvkm_i2c_port *(*find_type)(struct nvkm_i2c *, u16 type);
+ int (*acquire_pad)(struct nvkm_i2c_port *, unsigned long timeout);
+ void (*release_pad)(struct nvkm_i2c_port *);
+ int (*acquire)(struct nvkm_i2c_port *, unsigned long timeout);
+ void (*release)(struct nvkm_i2c_port *);
+ int (*identify)(struct nvkm_i2c *, int index,
+ const char *what, struct nvkm_i2c_board_info *,
+ bool (*match)(struct nvkm_i2c_port *,
+ struct i2c_board_info *, void *),
+ void *);
wait_queue_head_t wait;
struct list_head ports;
};
-static inline struct nouveau_i2c *
-nouveau_i2c(void *obj)
+static inline struct nvkm_i2c *
+nvkm_i2c(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_I2C);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_I2C);
}
-extern struct nouveau_oclass *nv04_i2c_oclass;
-extern struct nouveau_oclass *nv4e_i2c_oclass;
-extern struct nouveau_oclass *nv50_i2c_oclass;
-extern struct nouveau_oclass *nv94_i2c_oclass;
-extern struct nouveau_oclass *nvd0_i2c_oclass;
-extern struct nouveau_oclass *gf117_i2c_oclass;
-extern struct nouveau_oclass *nve0_i2c_oclass;
-extern struct nouveau_oclass *gm204_i2c_oclass;
+extern struct nvkm_oclass *nv04_i2c_oclass;
+extern struct nvkm_oclass *nv4e_i2c_oclass;
+extern struct nvkm_oclass *nv50_i2c_oclass;
+extern struct nvkm_oclass *g94_i2c_oclass;
+extern struct nvkm_oclass *gf110_i2c_oclass;
+extern struct nvkm_oclass *gf117_i2c_oclass;
+extern struct nvkm_oclass *gk104_i2c_oclass;
+extern struct nvkm_oclass *gm204_i2c_oclass;
static inline int
-nv_rdi2cr(struct nouveau_i2c_port *port, u8 addr, u8 reg)
+nv_rdi2cr(struct nvkm_i2c_port *port, u8 addr, u8 reg)
{
u8 val;
struct i2c_msg msgs[] = {
@@ -110,7 +110,7 @@ nv_rdi2cr(struct nouveau_i2c_port *port, u8 addr, u8 reg)
}
static inline int
-nv_wri2cr(struct nouveau_i2c_port *port, u8 addr, u8 reg, u8 val)
+nv_wri2cr(struct nvkm_i2c_port *port, u8 addr, u8 reg, u8 val)
{
u8 buf[2] = { reg, val };
struct i2c_msg msgs[] = {
@@ -125,12 +125,11 @@ nv_wri2cr(struct nouveau_i2c_port *port, u8 addr, u8 reg, u8 val)
}
static inline bool
-nv_probe_i2c(struct nouveau_i2c_port *port, u8 addr)
+nv_probe_i2c(struct nvkm_i2c_port *port, u8 addr)
{
return nv_rdi2cr(port, addr, 0) >= 0;
}
-int nv_rdaux(struct nouveau_i2c_port *, u32 addr, u8 *data, u8 size);
-int nv_wraux(struct nouveau_i2c_port *, u32 addr, u8 *data, u8 size);
-
+int nv_rdaux(struct nvkm_i2c_port *, u32 addr, u8 *data, u8 size);
+int nv_wraux(struct nvkm_i2c_port *, u32 addr, u8 *data, u8 size);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index f27932ea6196..e2581c408bd4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -63,7 +63,7 @@ gm100_identify(struct nouveau_device *device)
device->cname = "GM107";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 747651747b16..579829a39e25 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -178,7 +178,7 @@ nv50_identify(struct nouveau_device *device)
device->cname = "G94";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
@@ -207,7 +207,7 @@ nv50_identify(struct nouveau_device *device)
device->cname = "G96";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
@@ -236,7 +236,7 @@ nv50_identify(struct nouveau_device *device)
device->cname = "G98";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
@@ -294,7 +294,7 @@ nv50_identify(struct nouveau_device *device)
device->cname = "MCP77/MCP78";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
@@ -323,7 +323,7 @@ nv50_identify(struct nouveau_device *device)
device->cname = "MCP79/MCP7A";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
@@ -352,7 +352,7 @@ nv50_identify(struct nouveau_device *device)
device->cname = "GT215";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
@@ -383,7 +383,7 @@ nv50_identify(struct nouveau_device *device)
device->cname = "GT216";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
@@ -413,7 +413,7 @@ nv50_identify(struct nouveau_device *device)
device->cname = "GT218";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
@@ -443,7 +443,7 @@ nv50_identify(struct nouveau_device *device)
device->cname = "MCP89";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 5a67aad4f8f9..310fd4113e90 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -63,7 +63,7 @@ nvc0_identify(struct nouveau_device *device)
device->cname = "GF100";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
@@ -96,7 +96,7 @@ nvc0_identify(struct nouveau_device *device)
device->cname = "GF104";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
@@ -129,7 +129,7 @@ nvc0_identify(struct nouveau_device *device)
device->cname = "GF106";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
@@ -161,7 +161,7 @@ nvc0_identify(struct nouveau_device *device)
device->cname = "GF114";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
@@ -194,7 +194,7 @@ nvc0_identify(struct nouveau_device *device)
device->cname = "GF116";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
@@ -226,7 +226,7 @@ nvc0_identify(struct nouveau_device *device)
device->cname = "GF108";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
@@ -258,7 +258,7 @@ nvc0_identify(struct nouveau_device *device)
device->cname = "GF110";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
@@ -291,7 +291,7 @@ nvc0_identify(struct nouveau_device *device)
device->cname = "GF119";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 024059aea4fd..89ac2ca1f85f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -63,7 +63,7 @@ nve0_identify(struct nouveau_device *device)
device->cname = "GK104";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
@@ -97,7 +97,7 @@ nve0_identify(struct nouveau_device *device)
device->cname = "GK107";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
@@ -131,7 +131,7 @@ nve0_identify(struct nouveau_device *device)
device->cname = "GK106";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
@@ -187,7 +187,7 @@ nve0_identify(struct nouveau_device *device)
device->cname = "GK110";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
@@ -221,7 +221,7 @@ nve0_identify(struct nouveau_device *device)
device->cname = "GK110B";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
@@ -255,7 +255,7 @@ nve0_identify(struct nouveau_device *device)
device->cname = "GK208B";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
@@ -288,7 +288,7 @@ nve0_identify(struct nouveau_device *device)
device->cname = "GK208";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
- device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
+ device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
index 63c9607a0116..f67cdae1e90a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
@@ -30,6 +30,8 @@
#include <subdev/bios/gpio.h>
#include <subdev/bios/init.h>
#include <subdev/bios/ramcfg.h>
+
+#include <core/device.h>
#include <subdev/devinit.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild
index cc8bd8368358..d68307409980 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild
@@ -4,13 +4,13 @@ nvkm-y += nvkm/subdev/i2c/aux.o
nvkm-y += nvkm/subdev/i2c/bit.o
nvkm-y += nvkm/subdev/i2c/pad.o
nvkm-y += nvkm/subdev/i2c/padnv04.o
-nvkm-y += nvkm/subdev/i2c/padnv94.o
+nvkm-y += nvkm/subdev/i2c/padg94.o
nvkm-y += nvkm/subdev/i2c/padgm204.o
nvkm-y += nvkm/subdev/i2c/nv04.o
nvkm-y += nvkm/subdev/i2c/nv4e.o
nvkm-y += nvkm/subdev/i2c/nv50.o
-nvkm-y += nvkm/subdev/i2c/nv94.o
-nvkm-y += nvkm/subdev/i2c/nvd0.o
+nvkm-y += nvkm/subdev/i2c/g94.o
+nvkm-y += nvkm/subdev/i2c/gf110.o
nvkm-y += nvkm/subdev/i2c/gf117.o
-nvkm-y += nvkm/subdev/i2c/nve0.o
+nvkm-y += nvkm/subdev/i2c/gk104.o
nvkm-y += nvkm/subdev/i2c/gm204.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c
index 2c2731a6cf91..d17dd1cf3c34 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c
@@ -21,20 +21,19 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
#include "port.h"
struct anx9805_i2c_port {
- struct nouveau_i2c_port base;
+ struct nvkm_i2c_port base;
u32 addr;
u32 ctrl;
};
static int
-anx9805_train(struct nouveau_i2c_port *port, int link_nr, int link_bw, bool enh)
+anx9805_train(struct nvkm_i2c_port *port, int link_nr, int link_bw, bool enh)
{
struct anx9805_i2c_port *chan = (void *)port;
- struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent;
+ struct nvkm_i2c_port *mast = (void *)nv_object(chan)->parent;
u8 tmp, i;
DBG("ANX9805 train %d 0x%02x %d\n", link_nr, link_bw, enh);
@@ -62,11 +61,11 @@ anx9805_train(struct nouveau_i2c_port *port, int link_nr, int link_bw, bool enh)
}
static int
-anx9805_aux(struct nouveau_i2c_port *port, bool retry,
+anx9805_aux(struct nvkm_i2c_port *port, bool retry,
u8 type, u32 addr, u8 *data, u8 size)
{
struct anx9805_i2c_port *chan = (void *)port;
- struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent;
+ struct nvkm_i2c_port *mast = (void *)nv_object(chan)->parent;
int i, ret = -ETIMEDOUT;
u8 buf[16] = {};
u8 tmp;
@@ -116,25 +115,25 @@ done:
return ret;
}
-static const struct nouveau_i2c_func
+static const struct nvkm_i2c_func
anx9805_aux_func = {
.aux = anx9805_aux,
.lnk_ctl = anx9805_train,
};
static int
-anx9805_aux_chan_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 index,
- struct nouveau_object **pobject)
+anx9805_aux_chan_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 index,
+ struct nvkm_object **pobject)
{
- struct nouveau_i2c_port *mast = (void *)parent;
+ struct nvkm_i2c_port *mast = (void *)parent;
struct anx9805_i2c_port *chan;
int ret;
- ret = nouveau_i2c_port_create(parent, engine, oclass, index,
- &nouveau_i2c_aux_algo, &anx9805_aux_func,
- &chan);
+ ret = nvkm_i2c_port_create(parent, engine, oclass, index,
+ &nvkm_i2c_aux_algo, &anx9805_aux_func,
+ &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -156,22 +155,23 @@ anx9805_aux_chan_ctor(struct nouveau_object *parent,
struct i2c_algo_bit_data *algo = mast->adapter.algo_data;
algo->udelay = max(algo->udelay, 40);
}
+
return 0;
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
anx9805_aux_ofuncs = {
.ctor = anx9805_aux_chan_ctor,
- .dtor = _nouveau_i2c_port_dtor,
- .init = _nouveau_i2c_port_init,
- .fini = _nouveau_i2c_port_fini,
+ .dtor = _nvkm_i2c_port_dtor,
+ .init = _nvkm_i2c_port_init,
+ .fini = _nvkm_i2c_port_fini,
};
static int
anx9805_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
struct anx9805_i2c_port *port = adap->algo_data;
- struct nouveau_i2c_port *mast = (void *)nv_object(port)->parent;
+ struct nvkm_i2c_port *mast = (void *)nv_object(port)->parent;
struct i2c_msg *msg = msgs;
int ret = -ETIMEDOUT;
int i, j, cnt = num;
@@ -233,23 +233,22 @@ anx9805_i2c_algo = {
.functionality = anx9805_func
};
-static const struct nouveau_i2c_func
+static const struct nvkm_i2c_func
anx9805_i2c_func = {
};
static int
-anx9805_ddc_port_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 index,
- struct nouveau_object **pobject)
+anx9805_ddc_port_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 index,
+ struct nvkm_object **pobject)
{
- struct nouveau_i2c_port *mast = (void *)parent;
+ struct nvkm_i2c_port *mast = (void *)parent;
struct anx9805_i2c_port *port;
int ret;
- ret = nouveau_i2c_port_create(parent, engine, oclass, index,
- &anx9805_i2c_algo, &anx9805_i2c_func,
- &port);
+ ret = nvkm_i2c_port_create(parent, engine, oclass, index,
+ &anx9805_i2c_algo, &anx9805_i2c_func, &port);
*pobject = nv_object(port);
if (ret)
return ret;
@@ -271,19 +270,20 @@ anx9805_ddc_port_ctor(struct nouveau_object *parent,
struct i2c_algo_bit_data *algo = mast->adapter.algo_data;
algo->udelay = max(algo->udelay, 40);
}
+
return 0;
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
anx9805_ddc_ofuncs = {
.ctor = anx9805_ddc_port_ctor,
- .dtor = _nouveau_i2c_port_dtor,
- .init = _nouveau_i2c_port_init,
- .fini = _nouveau_i2c_port_fini,
+ .dtor = _nvkm_i2c_port_dtor,
+ .init = _nvkm_i2c_port_init,
+ .fini = _nvkm_i2c_port_fini,
};
-struct nouveau_oclass
-nouveau_anx9805_sclass[] = {
+struct nvkm_oclass
+nvkm_anx9805_sclass[] = {
{ .handle = NV_I2C_TYPE_EXTDDC(0x0d), .ofuncs = &anx9805_ddc_ofuncs },
{ .handle = NV_I2C_TYPE_EXTAUX(0x0d), .ofuncs = &anx9805_aux_ofuncs },
{ .handle = NV_I2C_TYPE_EXTDDC(0x0e), .ofuncs = &anx9805_ddc_ofuncs },
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c
index 02eb42be2e9e..1c18860f80d1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
int
-nv_rdaux(struct nouveau_i2c_port *port, u32 addr, u8 *data, u8 size)
+nv_rdaux(struct nvkm_i2c_port *port, u32 addr, u8 *data, u8 size)
{
- struct nouveau_i2c *i2c = nouveau_i2c(port);
+ struct nvkm_i2c *i2c = nvkm_i2c(port);
if (port->func->aux) {
int ret = i2c->acquire(port, 0);
if (ret == 0) {
@@ -40,9 +39,9 @@ nv_rdaux(struct nouveau_i2c_port *port, u32 addr, u8 *data, u8 size)
}
int
-nv_wraux(struct nouveau_i2c_port *port, u32 addr, u8 *data, u8 size)
+nv_wraux(struct nvkm_i2c_port *port, u32 addr, u8 *data, u8 size)
{
- struct nouveau_i2c *i2c = nouveau_i2c(port);
+ struct nvkm_i2c *i2c = nvkm_i2c(port);
if (port->func->aux) {
int ret = i2c->acquire(port, 0);
if (ret == 0) {
@@ -57,8 +56,8 @@ nv_wraux(struct nouveau_i2c_port *port, u32 addr, u8 *data, u8 size)
static int
aux_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
- struct nouveau_i2c_port *port = adap->algo_data;
- struct nouveau_i2c *i2c = nouveau_i2c(port);
+ struct nvkm_i2c_port *port = adap->algo_data;
+ struct nvkm_i2c *i2c = nvkm_i2c(port);
struct i2c_msg *msg = msgs;
int ret, mcnt = num;
@@ -108,7 +107,7 @@ aux_func(struct i2c_adapter *adap)
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
-const struct i2c_algorithm nouveau_i2c_aux_algo = {
+const struct i2c_algorithm nvkm_i2c_aux_algo = {
.master_xfer = aux_xfer,
.functionality = aux_func
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
index bd477cd8a919..bfb0388f8d5b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
@@ -21,71 +21,66 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/notify.h>
-#include <core/option.h>
-#include <core/object.h>
-#include <core/event.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/i2c.h>
-#include <subdev/vga.h>
-
#include "priv.h"
#include "pad.h"
+#include <core/device.h>
+#include <core/notify.h>
+#include <core/option.h>
+#include <subdev/bios.h>
+#include <subdev/bios/dcb.h>
+
/******************************************************************************
* interface to linux i2c bit-banging algorithm
*****************************************************************************/
-#ifdef CONFIG_NOUVEAU_I2C_INTERNAL_DEFAULT
+#ifdef CONFIG_NVKM_I2C_INTERNAL_DEFAULT
#define CSTMSEL true
#else
#define CSTMSEL false
#endif
static int
-nouveau_i2c_pre_xfer(struct i2c_adapter *adap)
+nvkm_i2c_pre_xfer(struct i2c_adapter *adap)
{
struct i2c_algo_bit_data *bit = adap->algo_data;
- struct nouveau_i2c_port *port = bit->data;
- return nouveau_i2c(port)->acquire(port, bit->timeout);
+ struct nvkm_i2c_port *port = bit->data;
+ return nvkm_i2c(port)->acquire(port, bit->timeout);
}
static void
-nouveau_i2c_post_xfer(struct i2c_adapter *adap)
+nvkm_i2c_post_xfer(struct i2c_adapter *adap)
{
struct i2c_algo_bit_data *bit = adap->algo_data;
- struct nouveau_i2c_port *port = bit->data;
- return nouveau_i2c(port)->release(port);
+ struct nvkm_i2c_port *port = bit->data;
+ return nvkm_i2c(port)->release(port);
}
static void
-nouveau_i2c_setscl(void *data, int state)
+nvkm_i2c_setscl(void *data, int state)
{
- struct nouveau_i2c_port *port = data;
+ struct nvkm_i2c_port *port = data;
port->func->drive_scl(port, state);
}
static void
-nouveau_i2c_setsda(void *data, int state)
+nvkm_i2c_setsda(void *data, int state)
{
- struct nouveau_i2c_port *port = data;
+ struct nvkm_i2c_port *port = data;
port->func->drive_sda(port, state);
}
static int
-nouveau_i2c_getscl(void *data)
+nvkm_i2c_getscl(void *data)
{
- struct nouveau_i2c_port *port = data;
+ struct nvkm_i2c_port *port = data;
return port->func->sense_scl(port);
}
static int
-nouveau_i2c_getsda(void *data)
+nvkm_i2c_getsda(void *data)
{
- struct nouveau_i2c_port *port = data;
+ struct nvkm_i2c_port *port = data;
return port->func->sense_sda(port);
}
@@ -94,42 +89,41 @@ nouveau_i2c_getsda(void *data)
*****************************************************************************/
int
-_nouveau_i2c_port_fini(struct nouveau_object *object, bool suspend)
+_nvkm_i2c_port_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_i2c_port *port = (void *)object;
+ struct nvkm_i2c_port *port = (void *)object;
struct nvkm_i2c_pad *pad = nvkm_i2c_pad(port);
nv_ofuncs(pad)->fini(nv_object(pad), suspend);
- return nouveau_object_fini(&port->base, suspend);
+ return nvkm_object_fini(&port->base, suspend);
}
void
-_nouveau_i2c_port_dtor(struct nouveau_object *object)
+_nvkm_i2c_port_dtor(struct nvkm_object *object)
{
- struct nouveau_i2c_port *port = (void *)object;
+ struct nvkm_i2c_port *port = (void *)object;
i2c_del_adapter(&port->adapter);
- nouveau_object_destroy(&port->base);
+ nvkm_object_destroy(&port->base);
}
int
-nouveau_i2c_port_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, u8 index,
- const struct i2c_algorithm *algo,
- const struct nouveau_i2c_func *func,
- int size, void **pobject)
+nvkm_i2c_port_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, u8 index,
+ const struct i2c_algorithm *algo,
+ const struct nvkm_i2c_func *func,
+ int size, void **pobject)
{
- struct nouveau_device *device = nv_device(parent);
- struct nouveau_i2c *i2c = nouveau_i2c(parent);
- struct nouveau_i2c_port *port;
+ struct nvkm_device *device = nv_device(parent);
+ struct nvkm_i2c *i2c = nvkm_i2c(parent);
+ struct nvkm_i2c_port *port;
int ret;
- ret = nouveau_object_create_(parent, engine, oclass, 0, size, pobject);
+ ret = nvkm_object_create_(parent, engine, oclass, 0, size, pobject);
port = *pobject;
if (ret)
return ret;
snprintf(port->adapter.name, sizeof(port->adapter.name),
- "nouveau-%s-%d", device->name, index);
+ "nvkm-%s-%d", device->name, index);
port->adapter.owner = THIS_MODULE;
port->adapter.dev.parent = nv_device_base(device);
port->index = index;
@@ -137,8 +131,8 @@ nouveau_i2c_port_create_(struct nouveau_object *parent,
port->func = func;
mutex_init(&port->mutex);
- if ( algo == &nouveau_i2c_bit_algo &&
- !nouveau_boolopt(device->cfgopt, "NvI2C", CSTMSEL)) {
+ if ( algo == &nvkm_i2c_bit_algo &&
+ !nvkm_boolopt(device->cfgopt, "NvI2C", CSTMSEL)) {
struct i2c_algo_bit_data *bit;
bit = kzalloc(sizeof(*bit), GFP_KERNEL);
@@ -148,12 +142,12 @@ nouveau_i2c_port_create_(struct nouveau_object *parent,
bit->udelay = 10;
bit->timeout = usecs_to_jiffies(2200);
bit->data = port;
- bit->pre_xfer = nouveau_i2c_pre_xfer;
- bit->post_xfer = nouveau_i2c_post_xfer;
- bit->setsda = nouveau_i2c_setsda;
- bit->setscl = nouveau_i2c_setscl;
- bit->getsda = nouveau_i2c_getsda;
- bit->getscl = nouveau_i2c_getscl;
+ bit->pre_xfer = nvkm_i2c_pre_xfer;
+ bit->post_xfer = nvkm_i2c_post_xfer;
+ bit->setsda = nvkm_i2c_setsda;
+ bit->setscl = nvkm_i2c_setscl;
+ bit->getsda = nvkm_i2c_getsda;
+ bit->getscl = nvkm_i2c_getscl;
port->adapter.algo_data = bit;
ret = i2c_bit_add_bus(&port->adapter);
@@ -172,11 +166,11 @@ nouveau_i2c_port_create_(struct nouveau_object *parent,
* base i2c subdev class implementation
*****************************************************************************/
-static struct nouveau_i2c_port *
-nouveau_i2c_find(struct nouveau_i2c *i2c, u8 index)
+static struct nvkm_i2c_port *
+nvkm_i2c_find(struct nvkm_i2c *i2c, u8 index)
{
- struct nouveau_bios *bios = nouveau_bios(i2c);
- struct nouveau_i2c_port *port;
+ struct nvkm_bios *bios = nvkm_bios(i2c);
+ struct nvkm_i2c_port *port;
if (index == NV_I2C_DEFAULT(0) ||
index == NV_I2C_DEFAULT(1)) {
@@ -201,10 +195,10 @@ nouveau_i2c_find(struct nouveau_i2c *i2c, u8 index)
return NULL;
}
-static struct nouveau_i2c_port *
-nouveau_i2c_find_type(struct nouveau_i2c *i2c, u16 type)
+static struct nvkm_i2c_port *
+nvkm_i2c_find_type(struct nvkm_i2c *i2c, u16 type)
{
- struct nouveau_i2c_port *port;
+ struct nvkm_i2c_port *port;
list_for_each_entry(port, &i2c->ports, head) {
if (nv_hclass(port) == type)
@@ -215,10 +209,10 @@ nouveau_i2c_find_type(struct nouveau_i2c *i2c, u16 type)
}
static void
-nouveau_i2c_release_pad(struct nouveau_i2c_port *port)
+nvkm_i2c_release_pad(struct nvkm_i2c_port *port)
{
struct nvkm_i2c_pad *pad = nvkm_i2c_pad(port);
- struct nouveau_i2c *i2c = nouveau_i2c(port);
+ struct nvkm_i2c *i2c = nvkm_i2c(port);
if (atomic_dec_and_test(&nv_object(pad)->usecount)) {
nv_ofuncs(pad)->fini(nv_object(pad), false);
@@ -227,18 +221,18 @@ nouveau_i2c_release_pad(struct nouveau_i2c_port *port)
}
static int
-nouveau_i2c_try_acquire_pad(struct nouveau_i2c_port *port)
+nvkm_i2c_try_acquire_pad(struct nvkm_i2c_port *port)
{
struct nvkm_i2c_pad *pad = nvkm_i2c_pad(port);
if (atomic_add_return(1, &nv_object(pad)->usecount) != 1) {
- struct nouveau_object *owner = (void *)pad->port;
+ struct nvkm_object *owner = (void *)pad->port;
do {
if (owner == (void *)port)
return 0;
owner = owner->parent;
} while(owner);
- nouveau_i2c_release_pad(port);
+ nvkm_i2c_release_pad(port);
return -EBUSY;
}
@@ -248,48 +242,48 @@ nouveau_i2c_try_acquire_pad(struct nouveau_i2c_port *port)
}
static int
-nouveau_i2c_acquire_pad(struct nouveau_i2c_port *port, unsigned long timeout)
+nvkm_i2c_acquire_pad(struct nvkm_i2c_port *port, unsigned long timeout)
{
- struct nouveau_i2c *i2c = nouveau_i2c(port);
+ struct nvkm_i2c *i2c = nvkm_i2c(port);
if (timeout) {
if (wait_event_timeout(i2c->wait,
- nouveau_i2c_try_acquire_pad(port) == 0,
+ nvkm_i2c_try_acquire_pad(port) == 0,
timeout) == 0)
return -EBUSY;
} else {
- wait_event(i2c->wait, nouveau_i2c_try_acquire_pad(port) == 0);
+ wait_event(i2c->wait, nvkm_i2c_try_acquire_pad(port) == 0);
}
return 0;
}
static void
-nouveau_i2c_release(struct nouveau_i2c_port *port)
+nvkm_i2c_release(struct nvkm_i2c_port *port)
__releases(pad->mutex)
{
- nouveau_i2c(port)->release_pad(port);
+ nvkm_i2c(port)->release_pad(port);
mutex_unlock(&port->mutex);
}
static int
-nouveau_i2c_acquire(struct nouveau_i2c_port *port, unsigned long timeout)
+nvkm_i2c_acquire(struct nvkm_i2c_port *port, unsigned long timeout)
__acquires(pad->mutex)
{
int ret;
mutex_lock(&port->mutex);
- if ((ret = nouveau_i2c(port)->acquire_pad(port, timeout)))
+ if ((ret = nvkm_i2c(port)->acquire_pad(port, timeout)))
mutex_unlock(&port->mutex);
return ret;
}
static int
-nouveau_i2c_identify(struct nouveau_i2c *i2c, int index, const char *what,
- struct nouveau_i2c_board_info *info,
- bool (*match)(struct nouveau_i2c_port *,
- struct i2c_board_info *, void *), void *data)
+nvkm_i2c_identify(struct nvkm_i2c *i2c, int index, const char *what,
+ struct nvkm_i2c_board_info *info,
+ bool (*match)(struct nvkm_i2c_port *,
+ struct i2c_board_info *, void *), void *data)
{
- struct nouveau_i2c_port *port = nouveau_i2c_find(i2c, index);
+ struct nvkm_i2c_port *port = nvkm_i2c_find(i2c, index);
int i;
if (!port) {
@@ -328,27 +322,27 @@ nouveau_i2c_identify(struct nouveau_i2c *i2c, int index, const char *what,
}
static void
-nouveau_i2c_intr_fini(struct nvkm_event *event, int type, int index)
+nvkm_i2c_intr_fini(struct nvkm_event *event, int type, int index)
{
- struct nouveau_i2c *i2c = container_of(event, typeof(*i2c), event);
- struct nouveau_i2c_port *port = i2c->find(i2c, index);
- const struct nouveau_i2c_impl *impl = (void *)nv_object(i2c)->oclass;
+ struct nvkm_i2c *i2c = container_of(event, typeof(*i2c), event);
+ struct nvkm_i2c_port *port = i2c->find(i2c, index);
+ const struct nvkm_i2c_impl *impl = (void *)nv_object(i2c)->oclass;
if (port && port->aux >= 0)
impl->aux_mask(i2c, type, 1 << port->aux, 0);
}
static void
-nouveau_i2c_intr_init(struct nvkm_event *event, int type, int index)
+nvkm_i2c_intr_init(struct nvkm_event *event, int type, int index)
{
- struct nouveau_i2c *i2c = container_of(event, typeof(*i2c), event);
- struct nouveau_i2c_port *port = i2c->find(i2c, index);
- const struct nouveau_i2c_impl *impl = (void *)nv_object(i2c)->oclass;
+ struct nvkm_i2c *i2c = container_of(event, typeof(*i2c), event);
+ struct nvkm_i2c_port *port = i2c->find(i2c, index);
+ const struct nvkm_i2c_impl *impl = (void *)nv_object(i2c)->oclass;
if (port && port->aux >= 0)
impl->aux_mask(i2c, type, 1 << port->aux, 1 << port->aux);
}
static int
-nouveau_i2c_intr_ctor(struct nouveau_object *object, void *data, u32 size,
+nvkm_i2c_intr_ctor(struct nvkm_object *object, void *data, u32 size,
struct nvkm_notify *notify)
{
struct nvkm_i2c_ntfy_req *req = data;
@@ -362,11 +356,11 @@ nouveau_i2c_intr_ctor(struct nouveau_object *object, void *data, u32 size,
}
static void
-nouveau_i2c_intr(struct nouveau_subdev *subdev)
+nvkm_i2c_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_i2c_impl *impl = (void *)nv_oclass(subdev);
- struct nouveau_i2c *i2c = nouveau_i2c(subdev);
- struct nouveau_i2c_port *port;
+ struct nvkm_i2c_impl *impl = (void *)nv_oclass(subdev);
+ struct nvkm_i2c *i2c = nvkm_i2c(subdev);
+ struct nvkm_i2c_port *port;
u32 hi, lo, rq, tx, e;
if (impl->aux_stat) {
@@ -394,18 +388,18 @@ nouveau_i2c_intr(struct nouveau_subdev *subdev)
}
static const struct nvkm_event_func
-nouveau_i2c_intr_func = {
- .ctor = nouveau_i2c_intr_ctor,
- .init = nouveau_i2c_intr_init,
- .fini = nouveau_i2c_intr_fini,
+nvkm_i2c_intr_func = {
+ .ctor = nvkm_i2c_intr_ctor,
+ .init = nvkm_i2c_intr_init,
+ .fini = nvkm_i2c_intr_fini,
};
int
-_nouveau_i2c_fini(struct nouveau_object *object, bool suspend)
+_nvkm_i2c_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_i2c_impl *impl = (void *)nv_oclass(object);
- struct nouveau_i2c *i2c = (void *)object;
- struct nouveau_i2c_port *port;
+ struct nvkm_i2c_impl *impl = (void *)nv_oclass(object);
+ struct nvkm_i2c *i2c = (void *)object;
+ struct nvkm_i2c_port *port;
u32 mask;
int ret;
@@ -420,7 +414,7 @@ _nouveau_i2c_fini(struct nouveau_object *object, bool suspend)
impl->aux_stat(i2c, &mask, &mask, &mask, &mask);
}
- return nouveau_subdev_fini(&i2c->base, suspend);
+ return nvkm_subdev_fini(&i2c->base, suspend);
fail:
list_for_each_entry_continue_reverse(port, &i2c->ports, head) {
nv_ofuncs(port)->init(nv_object(port));
@@ -430,13 +424,13 @@ fail:
}
int
-_nouveau_i2c_init(struct nouveau_object *object)
+_nvkm_i2c_init(struct nvkm_object *object)
{
- struct nouveau_i2c *i2c = (void *)object;
- struct nouveau_i2c_port *port;
+ struct nvkm_i2c *i2c = (void *)object;
+ struct nvkm_i2c_port *port;
int ret;
- ret = nouveau_subdev_init(&i2c->base);
+ ret = nvkm_subdev_init(&i2c->base);
if (ret == 0) {
list_for_each_entry(port, &i2c->ports, head) {
ret = nv_ofuncs(port)->init(nv_object(port));
@@ -455,33 +449,33 @@ fail:
}
void
-_nouveau_i2c_dtor(struct nouveau_object *object)
+_nvkm_i2c_dtor(struct nvkm_object *object)
{
- struct nouveau_i2c *i2c = (void *)object;
- struct nouveau_i2c_port *port, *temp;
+ struct nvkm_i2c *i2c = (void *)object;
+ struct nvkm_i2c_port *port, *temp;
nvkm_event_fini(&i2c->event);
list_for_each_entry_safe(port, temp, &i2c->ports, head) {
- nouveau_object_ref(NULL, (struct nouveau_object **)&port);
+ nvkm_object_ref(NULL, (struct nvkm_object **)&port);
}
- nouveau_subdev_destroy(&i2c->base);
+ nvkm_subdev_destroy(&i2c->base);
}
-static struct nouveau_oclass *
-nouveau_i2c_extdev_sclass[] = {
- nouveau_anx9805_sclass,
+static struct nvkm_oclass *
+nvkm_i2c_extdev_sclass[] = {
+ nvkm_anx9805_sclass,
};
static void
-nouveau_i2c_create_port(struct nouveau_i2c *i2c, int index, u8 type,
- struct dcb_i2c_entry *info)
+nvkm_i2c_create_port(struct nvkm_i2c *i2c, int index, u8 type,
+ struct dcb_i2c_entry *info)
{
- const struct nouveau_i2c_impl *impl = (void *)nv_oclass(i2c);
- struct nouveau_oclass *oclass;
- struct nouveau_object *parent;
- struct nouveau_object *object;
+ const struct nvkm_i2c_impl *impl = (void *)nv_oclass(i2c);
+ struct nvkm_oclass *oclass;
+ struct nvkm_object *parent;
+ struct nvkm_object *object;
int ret, pad;
if (info->share != DCB_I2C_UNUSED) {
@@ -495,8 +489,8 @@ nouveau_i2c_create_port(struct nouveau_i2c *i2c, int index, u8 type,
oclass = impl->pad_x;
}
- ret = nouveau_object_ctor(nv_object(i2c), NULL, oclass,
- NULL, pad, &parent);
+ ret = nvkm_object_ctor(nv_object(i2c), NULL, oclass,
+ NULL, pad, &parent);
if (ret < 0)
return;
@@ -504,44 +498,40 @@ nouveau_i2c_create_port(struct nouveau_i2c *i2c, int index, u8 type,
do {
ret = -EINVAL;
if (oclass->handle == type) {
- ret = nouveau_object_ctor(parent, NULL,
- oclass, info, index,
- &object);
+ ret = nvkm_object_ctor(parent, NULL, oclass,
+ info, index, &object);
}
} while (ret && (++oclass)->handle);
- nouveau_object_ref(NULL, &parent);
+ nvkm_object_ref(NULL, &parent);
}
int
-nouveau_i2c_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass,
- int length, void **pobject)
+nvkm_i2c_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
- struct nouveau_bios *bios = nouveau_bios(parent);
- struct nouveau_i2c *i2c;
- struct nouveau_object *object;
+ struct nvkm_bios *bios = nvkm_bios(parent);
+ struct nvkm_i2c *i2c;
+ struct nvkm_object *object;
struct dcb_i2c_entry info;
int ret, i, j, index = -1;
struct dcb_output outp;
u8 ver, hdr;
u32 data;
- ret = nouveau_subdev_create(parent, engine, oclass, 0,
- "I2C", "i2c", &i2c);
+ ret = nvkm_subdev_create(parent, engine, oclass, 0, "I2C", "i2c", &i2c);
*pobject = nv_object(i2c);
if (ret)
return ret;
- nv_subdev(i2c)->intr = nouveau_i2c_intr;
- i2c->find = nouveau_i2c_find;
- i2c->find_type = nouveau_i2c_find_type;
- i2c->acquire_pad = nouveau_i2c_acquire_pad;
- i2c->release_pad = nouveau_i2c_release_pad;
- i2c->acquire = nouveau_i2c_acquire;
- i2c->release = nouveau_i2c_release;
- i2c->identify = nouveau_i2c_identify;
+ nv_subdev(i2c)->intr = nvkm_i2c_intr;
+ i2c->find = nvkm_i2c_find;
+ i2c->find_type = nvkm_i2c_find_type;
+ i2c->acquire_pad = nvkm_i2c_acquire_pad;
+ i2c->release_pad = nvkm_i2c_release_pad;
+ i2c->acquire = nvkm_i2c_acquire;
+ i2c->release = nvkm_i2c_release;
+ i2c->identify = nvkm_i2c_identify;
init_waitqueue_head(&i2c->wait);
INIT_LIST_HEAD(&i2c->ports);
@@ -550,23 +540,21 @@ nouveau_i2c_create_(struct nouveau_object *parent,
case DCB_I2C_NV04_BIT:
case DCB_I2C_NV4E_BIT:
case DCB_I2C_NVIO_BIT:
- nouveau_i2c_create_port(i2c, NV_I2C_PORT(index),
- info.type, &info);
+ nvkm_i2c_create_port(i2c, NV_I2C_PORT(index),
+ info.type, &info);
break;
case DCB_I2C_NVIO_AUX:
- nouveau_i2c_create_port(i2c, NV_I2C_AUX(index),
- info.type, &info);
+ nvkm_i2c_create_port(i2c, NV_I2C_AUX(index),
+ info.type, &info);
break;
case DCB_I2C_PMGR:
if (info.drive != DCB_I2C_UNUSED) {
- nouveau_i2c_create_port(i2c, NV_I2C_PORT(index),
- DCB_I2C_NVIO_BIT,
- &info);
+ nvkm_i2c_create_port(i2c, NV_I2C_PORT(index),
+ DCB_I2C_NVIO_BIT, &info);
}
if (info.auxch != DCB_I2C_UNUSED) {
- nouveau_i2c_create_port(i2c, NV_I2C_AUX(index),
- DCB_I2C_NVIO_AUX,
- &info);
+ nvkm_i2c_create_port(i2c, NV_I2C_AUX(index),
+ DCB_I2C_NVIO_AUX, &info);
}
break;
case DCB_I2C_UNUSED:
@@ -598,20 +586,19 @@ nouveau_i2c_create_(struct nouveau_object *parent,
ret = -ENODEV;
j = -1;
- while (ret && ++j < ARRAY_SIZE(nouveau_i2c_extdev_sclass)) {
+ while (ret && ++j < ARRAY_SIZE(nvkm_i2c_extdev_sclass)) {
parent = nv_object(i2c->find(i2c, outp.i2c_index));
- oclass = nouveau_i2c_extdev_sclass[j];
+ oclass = nvkm_i2c_extdev_sclass[j];
do {
if (oclass->handle != info.type)
continue;
- ret = nouveau_object_ctor(parent, NULL,
- oclass, NULL,
- index++, &object);
+ ret = nvkm_object_ctor(parent, NULL, oclass,
+ NULL, index++, &object);
} while (ret && (++oclass)->handle);
}
}
- ret = nvkm_event_init(&nouveau_i2c_intr_func, 4, index, &i2c->event);
+ ret = nvkm_event_init(&nvkm_i2c_intr_func, 4, index, &i2c->event);
if (ret)
return ret;
@@ -619,14 +606,14 @@ nouveau_i2c_create_(struct nouveau_object *parent,
}
int
-_nouveau_i2c_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+_nvkm_i2c_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_i2c *i2c;
+ struct nvkm_i2c *i2c;
int ret;
- ret = nouveau_i2c_create(parent, engine, oclass, &i2c);
+ ret = nvkm_i2c_create(parent, engine, oclass, &i2c);
*pobject = nv_object(i2c);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c
index 813ffc96e864..35132badaa8f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c
@@ -21,46 +21,45 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
-#ifdef CONFIG_NOUVEAU_I2C_INTERNAL
+#ifdef CONFIG_NVKM_I2C_INTERNAL
#define T_TIMEOUT 2200000
#define T_RISEFALL 1000
#define T_HOLD 5000
static inline void
-i2c_drive_scl(struct nouveau_i2c_port *port, int state)
+i2c_drive_scl(struct nvkm_i2c_port *port, int state)
{
port->func->drive_scl(port, state);
}
static inline void
-i2c_drive_sda(struct nouveau_i2c_port *port, int state)
+i2c_drive_sda(struct nvkm_i2c_port *port, int state)
{
port->func->drive_sda(port, state);
}
static inline int
-i2c_sense_scl(struct nouveau_i2c_port *port)
+i2c_sense_scl(struct nvkm_i2c_port *port)
{
return port->func->sense_scl(port);
}
static inline int
-i2c_sense_sda(struct nouveau_i2c_port *port)
+i2c_sense_sda(struct nvkm_i2c_port *port)
{
return port->func->sense_sda(port);
}
static void
-i2c_delay(struct nouveau_i2c_port *port, u32 nsec)
+i2c_delay(struct nvkm_i2c_port *port, u32 nsec)
{
udelay((nsec + 500) / 1000);
}
static bool
-i2c_raise_scl(struct nouveau_i2c_port *port)
+i2c_raise_scl(struct nvkm_i2c_port *port)
{
u32 timeout = T_TIMEOUT / T_RISEFALL;
@@ -73,7 +72,7 @@ i2c_raise_scl(struct nouveau_i2c_port *port)
}
static int
-i2c_start(struct nouveau_i2c_port *port)
+i2c_start(struct nvkm_i2c_port *port)
{
int ret = 0;
@@ -93,7 +92,7 @@ i2c_start(struct nouveau_i2c_port *port)
}
static void
-i2c_stop(struct nouveau_i2c_port *port)
+i2c_stop(struct nvkm_i2c_port *port)
{
i2c_drive_scl(port, 0);
i2c_drive_sda(port, 0);
@@ -106,7 +105,7 @@ i2c_stop(struct nouveau_i2c_port *port)
}
static int
-i2c_bitw(struct nouveau_i2c_port *port, int sda)
+i2c_bitw(struct nvkm_i2c_port *port, int sda)
{
i2c_drive_sda(port, sda);
i2c_delay(port, T_RISEFALL);
@@ -121,7 +120,7 @@ i2c_bitw(struct nouveau_i2c_port *port, int sda)
}
static int
-i2c_bitr(struct nouveau_i2c_port *port)
+i2c_bitr(struct nvkm_i2c_port *port)
{
int sda;
@@ -140,7 +139,7 @@ i2c_bitr(struct nouveau_i2c_port *port)
}
static int
-i2c_get_byte(struct nouveau_i2c_port *port, u8 *byte, bool last)
+i2c_get_byte(struct nvkm_i2c_port *port, u8 *byte, bool last)
{
int i, bit;
@@ -156,7 +155,7 @@ i2c_get_byte(struct nouveau_i2c_port *port, u8 *byte, bool last)
}
static int
-i2c_put_byte(struct nouveau_i2c_port *port, u8 byte)
+i2c_put_byte(struct nvkm_i2c_port *port, u8 byte)
{
int i, ret;
for (i = 7; i >= 0; i--) {
@@ -172,7 +171,7 @@ i2c_put_byte(struct nouveau_i2c_port *port, u8 byte)
}
static int
-i2c_addr(struct nouveau_i2c_port *port, struct i2c_msg *msg)
+i2c_addr(struct nvkm_i2c_port *port, struct i2c_msg *msg)
{
u32 addr = msg->addr << 1;
if (msg->flags & I2C_M_RD)
@@ -183,11 +182,11 @@ i2c_addr(struct nouveau_i2c_port *port, struct i2c_msg *msg)
static int
i2c_bit_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
- struct nouveau_i2c_port *port = adap->algo_data;
+ struct nvkm_i2c_port *port = adap->algo_data;
struct i2c_msg *msg = msgs;
int ret = 0, mcnt = num;
- ret = nouveau_i2c(port)->acquire(port, nsecs_to_jiffies(T_TIMEOUT));
+ ret = nvkm_i2c(port)->acquire(port, nsecs_to_jiffies(T_TIMEOUT));
if (ret)
return ret;
@@ -211,7 +210,7 @@ i2c_bit_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
}
i2c_stop(port);
- nouveau_i2c(port)->release(port);
+ nvkm_i2c(port)->release(port);
return (ret < 0) ? ret : num;
}
#else
@@ -228,7 +227,7 @@ i2c_bit_func(struct i2c_adapter *adap)
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
-const struct i2c_algorithm nouveau_i2c_bit_algo = {
+const struct i2c_algorithm nvkm_i2c_bit_algo = {
.master_xfer = i2c_bit_xfer,
.functionality = i2c_bit_func
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c
similarity index 76%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv94.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c
index e383ee81f4d2..2a2dd47b9835 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv94.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c
@@ -21,11 +21,10 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
void
-nv94_aux_stat(struct nouveau_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx)
+g94_aux_stat(struct nvkm_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx)
{
u32 intr = nv_rd32(i2c, 0x00e06c);
u32 stat = nv_rd32(i2c, 0x00e068) & intr, i;
@@ -39,7 +38,7 @@ nv94_aux_stat(struct nouveau_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx)
}
void
-nv94_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data)
+g94_aux_mask(struct nvkm_i2c *i2c, u32 type, u32 mask, u32 data)
{
u32 temp = nv_rd32(i2c, 0x00e068), i;
for (i = 0; i < 8; i++) {
@@ -58,13 +57,13 @@ nv94_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data)
#define AUX_ERR(fmt, args...) nv_error(aux, "AUXCH(%d): " fmt, ch, ##args)
static void
-auxch_fini(struct nouveau_i2c *aux, int ch)
+auxch_fini(struct nvkm_i2c *aux, int ch)
{
nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
}
static int
-auxch_init(struct nouveau_i2c *aux, int ch)
+auxch_init(struct nvkm_i2c *aux, int ch)
{
const u32 unksel = 1; /* nfi which to use, or if it matters.. */
const u32 ureq = unksel ? 0x00100000 : 0x00200000;
@@ -99,10 +98,10 @@ auxch_init(struct nouveau_i2c *aux, int ch)
}
int
-nv94_aux(struct nouveau_i2c_port *base, bool retry,
+g94_aux(struct nvkm_i2c_port *base, bool retry,
u8 type, u32 addr, u8 *data, u8 size)
{
- struct nouveau_i2c *aux = nouveau_i2c(base);
+ struct nvkm_i2c *aux = nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
u32 ctrl, stat, timeout, retries;
u32 xbuf[4] = {};
@@ -185,8 +184,8 @@ out:
return ret < 0 ? ret : (stat & 0x000f0000) >> 16;
}
-static const struct nouveau_i2c_func
-nv94_i2c_func = {
+static const struct nvkm_i2c_func
+g94_i2c_func = {
.drive_scl = nv50_i2c_drive_scl,
.drive_sda = nv50_i2c_drive_sda,
.sense_scl = nv50_i2c_sense_scl,
@@ -194,17 +193,16 @@ nv94_i2c_func = {
};
static int
-nv94_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 index,
- struct nouveau_object **pobject)
+g94_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 index,
+ struct nvkm_object **pobject)
{
struct dcb_i2c_entry *info = data;
struct nv50_i2c_port *port;
int ret;
- ret = nouveau_i2c_port_create(parent, engine, oclass, index,
- &nouveau_i2c_bit_algo, &nv94_i2c_func,
- &port);
+ ret = nvkm_i2c_port_create(parent, engine, oclass, index,
+ &nvkm_i2c_bit_algo, &g94_i2c_func, &port);
*pobject = nv_object(port);
if (ret)
return ret;
@@ -217,23 +215,22 @@ nv94_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-static const struct nouveau_i2c_func
-nv94_aux_func = {
- .aux = nv94_aux,
+static const struct nvkm_i2c_func
+g94_aux_func = {
+ .aux = g94_aux,
};
int
-nv94_aux_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 index,
- struct nouveau_object **pobject)
+g94_aux_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 index,
+ struct nvkm_object **pobject)
{
struct dcb_i2c_entry *info = data;
struct nv50_i2c_port *port;
int ret;
- ret = nouveau_i2c_port_create(parent, engine, oclass, index,
- &nouveau_i2c_aux_algo, &nv94_aux_func,
- &port);
+ ret = nvkm_i2c_port_create(parent, engine, oclass, index,
+ &nvkm_i2c_aux_algo, &g94_aux_func, &port);
*pobject = nv_object(port);
if (ret)
return ret;
@@ -243,40 +240,40 @@ nv94_aux_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-static struct nouveau_oclass
-nv94_i2c_sclass[] = {
+static struct nvkm_oclass
+g94_i2c_sclass[] = {
{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv94_i2c_port_ctor,
- .dtor = _nouveau_i2c_port_dtor,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g94_i2c_port_ctor,
+ .dtor = _nvkm_i2c_port_dtor,
.init = nv50_i2c_port_init,
- .fini = _nouveau_i2c_port_fini,
+ .fini = _nvkm_i2c_port_fini,
},
},
{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv94_aux_port_ctor,
- .dtor = _nouveau_i2c_port_dtor,
- .init = _nouveau_i2c_port_init,
- .fini = _nouveau_i2c_port_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g94_aux_port_ctor,
+ .dtor = _nvkm_i2c_port_dtor,
+ .init = _nvkm_i2c_port_init,
+ .fini = _nvkm_i2c_port_fini,
},
},
{}
};
-struct nouveau_oclass *
-nv94_i2c_oclass = &(struct nouveau_i2c_impl) {
+struct nvkm_oclass *
+g94_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0x94),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_i2c_ctor,
- .dtor = _nouveau_i2c_dtor,
- .init = _nouveau_i2c_init,
- .fini = _nouveau_i2c_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_i2c_ctor,
+ .dtor = _nvkm_i2c_dtor,
+ .init = _nvkm_i2c_init,
+ .fini = _nvkm_i2c_fini,
},
- .sclass = nv94_i2c_sclass,
+ .sclass = g94_i2c_sclass,
.pad_x = &nv04_i2c_pad_oclass,
- .pad_s = &nv94_i2c_pad_oclass,
+ .pad_s = &g94_i2c_pad_oclass,
.aux = 4,
- .aux_stat = nv94_aux_stat,
- .aux_mask = nv94_aux_mask,
+ .aux_stat = g94_aux_stat,
+ .aux_mask = g94_aux_mask,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf110.c
similarity index 58%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf110.c
index 62dde9b09007..4d4ac6638140 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nvd0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf110.c
@@ -21,45 +21,43 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
static int
-nvd0_i2c_sense_scl(struct nouveau_i2c_port *base)
+gf110_i2c_sense_scl(struct nvkm_i2c_port *base)
{
- struct nv50_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00000010);
}
static int
-nvd0_i2c_sense_sda(struct nouveau_i2c_port *base)
+gf110_i2c_sense_sda(struct nvkm_i2c_port *base)
{
- struct nv50_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00000020);
}
-static const struct nouveau_i2c_func
-nvd0_i2c_func = {
+static const struct nvkm_i2c_func
+gf110_i2c_func = {
.drive_scl = nv50_i2c_drive_scl,
.drive_sda = nv50_i2c_drive_sda,
- .sense_scl = nvd0_i2c_sense_scl,
- .sense_sda = nvd0_i2c_sense_sda,
+ .sense_scl = gf110_i2c_sense_scl,
+ .sense_sda = gf110_i2c_sense_sda,
};
int
-nvd0_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 index,
- struct nouveau_object **pobject)
+gf110_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 index,
+ struct nvkm_object **pobject)
{
struct dcb_i2c_entry *info = data;
struct nv50_i2c_port *port;
int ret;
- ret = nouveau_i2c_port_create(parent, engine, oclass, index,
- &nouveau_i2c_bit_algo, &nvd0_i2c_func,
- &port);
+ ret = nvkm_i2c_port_create(parent, engine, oclass, index,
+ &nvkm_i2c_bit_algo, &gf110_i2c_func, &port);
*pobject = nv_object(port);
if (ret)
return ret;
@@ -69,40 +67,40 @@ nvd0_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
-nvd0_i2c_sclass[] = {
+struct nvkm_oclass
+gf110_i2c_sclass[] = {
{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvd0_i2c_port_ctor,
- .dtor = _nouveau_i2c_port_dtor,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf110_i2c_port_ctor,
+ .dtor = _nvkm_i2c_port_dtor,
.init = nv50_i2c_port_init,
- .fini = _nouveau_i2c_port_fini,
+ .fini = _nvkm_i2c_port_fini,
},
},
{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv94_aux_port_ctor,
- .dtor = _nouveau_i2c_port_dtor,
- .init = _nouveau_i2c_port_init,
- .fini = _nouveau_i2c_port_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g94_aux_port_ctor,
+ .dtor = _nvkm_i2c_port_dtor,
+ .init = _nvkm_i2c_port_init,
+ .fini = _nvkm_i2c_port_fini,
},
},
{}
};
-struct nouveau_oclass *
-nvd0_i2c_oclass = &(struct nouveau_i2c_impl) {
+struct nvkm_oclass *
+gf110_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0xd0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_i2c_ctor,
- .dtor = _nouveau_i2c_dtor,
- .init = _nouveau_i2c_init,
- .fini = _nouveau_i2c_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_i2c_ctor,
+ .dtor = _nvkm_i2c_dtor,
+ .init = _nvkm_i2c_init,
+ .fini = _nvkm_i2c_fini,
},
- .sclass = nvd0_i2c_sclass,
+ .sclass = gf110_i2c_sclass,
.pad_x = &nv04_i2c_pad_oclass,
- .pad_s = &nv94_i2c_pad_oclass,
+ .pad_s = &g94_i2c_pad_oclass,
.aux = 4,
- .aux_stat = nv94_aux_stat,
- .aux_mask = nv94_aux_mask,
+ .aux_stat = g94_aux_stat,
+ .aux_mask = g94_aux_mask,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c
index fa891c39866b..e290b40f2d13 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c
@@ -21,19 +21,18 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
-struct nouveau_oclass *
-gf117_i2c_oclass = &(struct nouveau_i2c_impl) {
+struct nvkm_oclass *
+gf117_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0xd7),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_i2c_ctor,
- .dtor = _nouveau_i2c_dtor,
- .init = _nouveau_i2c_init,
- .fini = _nouveau_i2c_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_i2c_ctor,
+ .dtor = _nvkm_i2c_dtor,
+ .init = _nvkm_i2c_init,
+ .fini = _nvkm_i2c_fini,
},
- .sclass = nvd0_i2c_sclass,
+ .sclass = gf110_i2c_sclass,
.pad_x = &nv04_i2c_pad_oclass,
.pad_s = &nv04_i2c_pad_oclass,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c
similarity index 79%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c
index 25fe5c2d110e..1a464903a992 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c
@@ -21,11 +21,10 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
void
-nve0_aux_stat(struct nouveau_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx)
+gk104_aux_stat(struct nvkm_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx)
{
u32 intr = nv_rd32(i2c, 0x00dc60);
u32 stat = nv_rd32(i2c, 0x00dc68) & intr, i;
@@ -39,7 +38,7 @@ nve0_aux_stat(struct nouveau_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx)
}
void
-nve0_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data)
+gk104_aux_mask(struct nvkm_i2c *i2c, u32 type, u32 mask, u32 data)
{
u32 temp = nv_rd32(i2c, 0x00dc68), i;
for (i = 0; i < 8; i++) {
@@ -54,19 +53,19 @@ nve0_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data)
nv_wr32(i2c, 0x00dc68, temp);
}
-struct nouveau_oclass *
-nve0_i2c_oclass = &(struct nouveau_i2c_impl) {
+struct nvkm_oclass *
+gk104_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0xe0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_i2c_ctor,
- .dtor = _nouveau_i2c_dtor,
- .init = _nouveau_i2c_init,
- .fini = _nouveau_i2c_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_i2c_ctor,
+ .dtor = _nvkm_i2c_dtor,
+ .init = _nvkm_i2c_init,
+ .fini = _nvkm_i2c_fini,
},
- .sclass = nvd0_i2c_sclass,
+ .sclass = gf110_i2c_sclass,
.pad_x = &nv04_i2c_pad_oclass,
- .pad_s = &nv94_i2c_pad_oclass,
+ .pad_s = &g94_i2c_pad_oclass,
.aux = 4,
- .aux_stat = nve0_aux_stat,
- .aux_mask = nve0_aux_mask,
+ .aux_stat = gk104_aux_stat,
+ .aux_mask = gk104_aux_mask,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm204.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm204.c
index 06a2b87ccbf1..ab64237b3842 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm204.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm204.c
@@ -21,20 +21,19 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
#define AUX_DBG(fmt, args...) nv_debug(aux, "AUXCH(%d): " fmt, ch, ##args)
#define AUX_ERR(fmt, args...) nv_error(aux, "AUXCH(%d): " fmt, ch, ##args)
static void
-auxch_fini(struct nouveau_i2c *aux, int ch)
+auxch_fini(struct nvkm_i2c *aux, int ch)
{
nv_mask(aux, 0x00d954 + (ch * 0x50), 0x00310000, 0x00000000);
}
static int
-auxch_init(struct nouveau_i2c *aux, int ch)
+auxch_init(struct nvkm_i2c *aux, int ch)
{
const u32 unksel = 1; /* nfi which to use, or if it matters.. */
const u32 ureq = unksel ? 0x00100000 : 0x00200000;
@@ -69,10 +68,10 @@ auxch_init(struct nouveau_i2c *aux, int ch)
}
int
-gm204_aux(struct nouveau_i2c_port *base, bool retry,
+gm204_aux(struct nvkm_i2c_port *base, bool retry,
u8 type, u32 addr, u8 *data, u8 size)
{
- struct nouveau_i2c *aux = nouveau_i2c(base);
+ struct nvkm_i2c *aux = nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
u32 ctrl, stat, timeout, retries;
u32 xbuf[4] = {};
@@ -155,24 +154,23 @@ out:
return ret < 0 ? ret : (stat & 0x000f0000) >> 16;
}
-static const struct nouveau_i2c_func
+static const struct nvkm_i2c_func
gm204_aux_func = {
.aux = gm204_aux,
};
int
-gm204_aux_port_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 index,
- struct nouveau_object **pobject)
+gm204_aux_port_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 index,
+ struct nvkm_object **pobject)
{
struct dcb_i2c_entry *info = data;
struct nv50_i2c_port *port;
int ret;
- ret = nouveau_i2c_port_create(parent, engine, oclass, index,
- &nouveau_i2c_aux_algo, &gm204_aux_func,
- &port);
+ ret = nvkm_i2c_port_create(parent, engine, oclass, index,
+ &nvkm_i2c_aux_algo, &gm204_aux_func, &port);
*pobject = nv_object(port);
if (ret)
return ret;
@@ -182,40 +180,40 @@ gm204_aux_port_ctor(struct nouveau_object *parent,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
gm204_i2c_sclass[] = {
{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvd0_i2c_port_ctor,
- .dtor = _nouveau_i2c_port_dtor,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf110_i2c_port_ctor,
+ .dtor = _nvkm_i2c_port_dtor,
.init = nv50_i2c_port_init,
- .fini = _nouveau_i2c_port_fini,
+ .fini = _nvkm_i2c_port_fini,
},
},
{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm204_aux_port_ctor,
- .dtor = _nouveau_i2c_port_dtor,
- .init = _nouveau_i2c_port_init,
- .fini = _nouveau_i2c_port_fini,
+ .dtor = _nvkm_i2c_port_dtor,
+ .init = _nvkm_i2c_port_init,
+ .fini = _nvkm_i2c_port_fini,
},
},
{}
};
-struct nouveau_oclass *
-gm204_i2c_oclass = &(struct nouveau_i2c_impl) {
+struct nvkm_oclass *
+gm204_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0x24),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_i2c_ctor,
- .dtor = _nouveau_i2c_dtor,
- .init = _nouveau_i2c_init,
- .fini = _nouveau_i2c_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_i2c_ctor,
+ .dtor = _nvkm_i2c_dtor,
+ .init = _nvkm_i2c_init,
+ .fini = _nvkm_i2c_fini,
},
.sclass = gm204_i2c_sclass,
.pad_x = &nv04_i2c_pad_oclass,
.pad_s = &gm204_i2c_pad_oclass,
.aux = 8,
- .aux_stat = nve0_aux_stat,
- .aux_mask = nve0_aux_mask,
+ .aux_stat = gk104_aux_stat,
+ .aux_mask = gk104_aux_mask,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c
index 0db5de6a27fd..4cdf1c489353 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c
@@ -21,25 +21,24 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/vga.h>
-#include "priv.h"
-
struct nv04_i2c_priv {
- struct nouveau_i2c base;
+ struct nvkm_i2c base;
};
struct nv04_i2c_port {
- struct nouveau_i2c_port base;
+ struct nvkm_i2c_port base;
u8 drive;
u8 sense;
};
static void
-nv04_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
+nv04_i2c_drive_scl(struct nvkm_i2c_port *base, int state)
{
- struct nv04_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv04_i2c_port *port = (void *)base;
u8 val = nv_rdvgac(priv, 0, port->drive);
if (state) val |= 0x20;
@@ -48,9 +47,9 @@ nv04_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
}
static void
-nv04_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
+nv04_i2c_drive_sda(struct nvkm_i2c_port *base, int state)
{
- struct nv04_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv04_i2c_port *port = (void *)base;
u8 val = nv_rdvgac(priv, 0, port->drive);
if (state) val |= 0x10;
@@ -59,22 +58,22 @@ nv04_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
}
static int
-nv04_i2c_sense_scl(struct nouveau_i2c_port *base)
+nv04_i2c_sense_scl(struct nvkm_i2c_port *base)
{
- struct nv04_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv04_i2c_port *port = (void *)base;
return !!(nv_rdvgac(priv, 0, port->sense) & 0x04);
}
static int
-nv04_i2c_sense_sda(struct nouveau_i2c_port *base)
+nv04_i2c_sense_sda(struct nvkm_i2c_port *base)
{
- struct nv04_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv04_i2c_port *port = (void *)base;
return !!(nv_rdvgac(priv, 0, port->sense) & 0x08);
}
-static const struct nouveau_i2c_func
+static const struct nvkm_i2c_func
nv04_i2c_func = {
.drive_scl = nv04_i2c_drive_scl,
.drive_sda = nv04_i2c_drive_sda,
@@ -83,17 +82,16 @@ nv04_i2c_func = {
};
static int
-nv04_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 index,
- struct nouveau_object **pobject)
+nv04_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 index,
+ struct nvkm_object **pobject)
{
struct dcb_i2c_entry *info = data;
struct nv04_i2c_port *port;
int ret;
- ret = nouveau_i2c_port_create(parent, engine, oclass, index,
- &nouveau_i2c_bit_algo, &nv04_i2c_func,
- &port);
+ ret = nvkm_i2c_port_create(parent, engine, oclass, index,
+ &nvkm_i2c_bit_algo, &nv04_i2c_func, &port);
*pobject = nv_object(port);
if (ret)
return ret;
@@ -103,27 +101,27 @@ nv04_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv04_i2c_sclass[] = {
{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NV04_BIT),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_i2c_port_ctor,
- .dtor = _nouveau_i2c_port_dtor,
- .init = _nouveau_i2c_port_init,
- .fini = _nouveau_i2c_port_fini,
+ .dtor = _nvkm_i2c_port_dtor,
+ .init = _nvkm_i2c_port_init,
+ .fini = _nvkm_i2c_port_fini,
},
},
{}
};
-struct nouveau_oclass *
-nv04_i2c_oclass = &(struct nouveau_i2c_impl) {
+struct nvkm_oclass *
+nv04_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0x04),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_i2c_ctor,
- .dtor = _nouveau_i2c_dtor,
- .init = _nouveau_i2c_init,
- .fini = _nouveau_i2c_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_i2c_ctor,
+ .dtor = _nvkm_i2c_dtor,
+ .init = _nvkm_i2c_init,
+ .fini = _nvkm_i2c_fini,
},
.sclass = nv04_i2c_sclass,
.pad_x = &nv04_i2c_pad_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c
index 0d783890f267..046fe5e2ea19 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c
@@ -21,53 +21,52 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/vga.h>
-#include "priv.h"
-
struct nv4e_i2c_priv {
- struct nouveau_i2c base;
+ struct nvkm_i2c base;
};
struct nv4e_i2c_port {
- struct nouveau_i2c_port base;
+ struct nvkm_i2c_port base;
u32 addr;
};
static void
-nv4e_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
+nv4e_i2c_drive_scl(struct nvkm_i2c_port *base, int state)
{
- struct nv4e_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv4e_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv4e_i2c_port *port = (void *)base;
nv_mask(priv, port->addr, 0x2f, state ? 0x21 : 0x01);
}
static void
-nv4e_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
+nv4e_i2c_drive_sda(struct nvkm_i2c_port *base, int state)
{
- struct nv4e_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv4e_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv4e_i2c_port *port = (void *)base;
nv_mask(priv, port->addr, 0x1f, state ? 0x11 : 0x01);
}
static int
-nv4e_i2c_sense_scl(struct nouveau_i2c_port *base)
+nv4e_i2c_sense_scl(struct nvkm_i2c_port *base)
{
- struct nv4e_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv4e_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv4e_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00040000);
}
static int
-nv4e_i2c_sense_sda(struct nouveau_i2c_port *base)
+nv4e_i2c_sense_sda(struct nvkm_i2c_port *base)
{
- struct nv4e_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv4e_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv4e_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00080000);
}
-static const struct nouveau_i2c_func
+static const struct nvkm_i2c_func
nv4e_i2c_func = {
.drive_scl = nv4e_i2c_drive_scl,
.drive_sda = nv4e_i2c_drive_sda,
@@ -76,17 +75,16 @@ nv4e_i2c_func = {
};
static int
-nv4e_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 index,
- struct nouveau_object **pobject)
+nv4e_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 index,
+ struct nvkm_object **pobject)
{
struct dcb_i2c_entry *info = data;
struct nv4e_i2c_port *port;
int ret;
- ret = nouveau_i2c_port_create(parent, engine, oclass, index,
- &nouveau_i2c_bit_algo, &nv4e_i2c_func,
- &port);
+ ret = nvkm_i2c_port_create(parent, engine, oclass, index,
+ &nvkm_i2c_bit_algo, &nv4e_i2c_func, &port);
*pobject = nv_object(port);
if (ret)
return ret;
@@ -95,27 +93,27 @@ nv4e_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv4e_i2c_sclass[] = {
{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NV4E_BIT),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv4e_i2c_port_ctor,
- .dtor = _nouveau_i2c_port_dtor,
- .init = _nouveau_i2c_port_init,
- .fini = _nouveau_i2c_port_fini,
+ .dtor = _nvkm_i2c_port_dtor,
+ .init = _nvkm_i2c_port_init,
+ .fini = _nvkm_i2c_port_fini,
},
},
{}
};
-struct nouveau_oclass *
-nv4e_i2c_oclass = &(struct nouveau_i2c_impl) {
+struct nvkm_oclass *
+nv4e_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0x4e),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_i2c_ctor,
- .dtor = _nouveau_i2c_dtor,
- .init = _nouveau_i2c_init,
- .fini = _nouveau_i2c_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_i2c_ctor,
+ .dtor = _nvkm_i2c_dtor,
+ .init = _nvkm_i2c_init,
+ .fini = _nvkm_i2c_fini,
},
.sclass = nv4e_i2c_sclass,
.pad_x = &nv04_i2c_pad_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c
index 33dd89f5cfc4..fba5b26a5682 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv50.h"
void
-nv50_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
+nv50_i2c_drive_scl(struct nvkm_i2c_port *base, int state)
{
- struct nv50_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
if (state) port->state |= 0x01;
else port->state &= 0xfe;
@@ -35,9 +34,9 @@ nv50_i2c_drive_scl(struct nouveau_i2c_port *base, int state)
}
void
-nv50_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
+nv50_i2c_drive_sda(struct nvkm_i2c_port *base, int state)
{
- struct nv50_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
if (state) port->state |= 0x02;
else port->state &= 0xfd;
@@ -45,22 +44,22 @@ nv50_i2c_drive_sda(struct nouveau_i2c_port *base, int state)
}
int
-nv50_i2c_sense_scl(struct nouveau_i2c_port *base)
+nv50_i2c_sense_scl(struct nvkm_i2c_port *base)
{
- struct nv50_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00000001);
}
int
-nv50_i2c_sense_sda(struct nouveau_i2c_port *base)
+nv50_i2c_sense_sda(struct nvkm_i2c_port *base)
{
- struct nv50_i2c_priv *priv = (void *)nouveau_i2c(base);
+ struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00000002);
}
-static const struct nouveau_i2c_func
+static const struct nvkm_i2c_func
nv50_i2c_func = {
.drive_scl = nv50_i2c_drive_scl,
.drive_sda = nv50_i2c_drive_sda,
@@ -76,17 +75,16 @@ const u32 nv50_i2c_addr[] = {
const int nv50_i2c_addr_nr = ARRAY_SIZE(nv50_i2c_addr);
static int
-nv50_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 index,
- struct nouveau_object **pobject)
+nv50_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 index,
+ struct nvkm_object **pobject)
{
struct dcb_i2c_entry *info = data;
struct nv50_i2c_port *port;
int ret;
- ret = nouveau_i2c_port_create(parent, engine, oclass, index,
- &nouveau_i2c_bit_algo, &nv50_i2c_func,
- &port);
+ ret = nvkm_i2c_port_create(parent, engine, oclass, index,
+ &nvkm_i2c_bit_algo, &nv50_i2c_func, &port);
*pobject = nv_object(port);
if (ret)
return ret;
@@ -100,35 +98,35 @@ nv50_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
int
-nv50_i2c_port_init(struct nouveau_object *object)
+nv50_i2c_port_init(struct nvkm_object *object)
{
- struct nv50_i2c_priv *priv = (void *)nouveau_i2c(object);
+ struct nv50_i2c_priv *priv = (void *)nvkm_i2c(object);
struct nv50_i2c_port *port = (void *)object;
nv_wr32(priv, port->addr, port->state);
- return nouveau_i2c_port_init(&port->base);
+ return nvkm_i2c_port_init(&port->base);
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv50_i2c_sclass[] = {
{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_i2c_port_ctor,
- .dtor = _nouveau_i2c_port_dtor,
+ .dtor = _nvkm_i2c_port_dtor,
.init = nv50_i2c_port_init,
- .fini = _nouveau_i2c_port_fini,
+ .fini = _nvkm_i2c_port_fini,
},
},
{}
};
-struct nouveau_oclass *
-nv50_i2c_oclass = &(struct nouveau_i2c_impl) {
+struct nvkm_oclass *
+nv50_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0x50),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_i2c_ctor,
- .dtor = _nouveau_i2c_dtor,
- .init = _nouveau_i2c_init,
- .fini = _nouveau_i2c_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_i2c_ctor,
+ .dtor = _nvkm_i2c_dtor,
+ .init = _nvkm_i2c_init,
+ .fini = _nvkm_i2c_fini,
},
.sclass = nv50_i2c_sclass,
.pad_x = &nv04_i2c_pad_oclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.h
index 9ef965692fb1..b3139e721b02 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.h
@@ -1,34 +1,32 @@
#ifndef __NV50_I2C_H__
#define __NV50_I2C_H__
-
#include "priv.h"
struct nv50_i2c_priv {
- struct nouveau_i2c base;
+ struct nvkm_i2c base;
};
struct nv50_i2c_port {
- struct nouveau_i2c_port base;
+ struct nvkm_i2c_port base;
u32 addr;
u32 state;
};
extern const u32 nv50_i2c_addr[];
extern const int nv50_i2c_addr_nr;
-int nv50_i2c_port_init(struct nouveau_object *);
-int nv50_i2c_sense_scl(struct nouveau_i2c_port *);
-int nv50_i2c_sense_sda(struct nouveau_i2c_port *);
-void nv50_i2c_drive_scl(struct nouveau_i2c_port *, int state);
-void nv50_i2c_drive_sda(struct nouveau_i2c_port *, int state);
+int nv50_i2c_port_init(struct nvkm_object *);
+int nv50_i2c_sense_scl(struct nvkm_i2c_port *);
+int nv50_i2c_sense_sda(struct nvkm_i2c_port *);
+void nv50_i2c_drive_scl(struct nvkm_i2c_port *, int state);
+void nv50_i2c_drive_sda(struct nvkm_i2c_port *, int state);
-int nv94_aux_port_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nv94_i2c_acquire(struct nouveau_i2c_port *);
-void nv94_i2c_release(struct nouveau_i2c_port *);
-
-int nvd0_i2c_port_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
+int g94_aux_port_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void g94_i2c_acquire(struct nvkm_i2c_port *);
+void g94_i2c_release(struct nvkm_i2c_port *);
+int gf110_i2c_port_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.c
index a3d0d82ff6f5..a242eeb67829 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.c
@@ -21,35 +21,34 @@
*
* Authors: Ben Skeggs
*/
-
#include "pad.h"
int
-_nvkm_i2c_pad_fini(struct nouveau_object *object, bool suspend)
+_nvkm_i2c_pad_fini(struct nvkm_object *object, bool suspend)
{
struct nvkm_i2c_pad *pad = (void *)object;
DBG("-> NULL\n");
pad->port = NULL;
- return nouveau_object_fini(&pad->base, suspend);
+ return nvkm_object_fini(&pad->base, suspend);
}
int
-_nvkm_i2c_pad_init(struct nouveau_object *object)
+_nvkm_i2c_pad_init(struct nvkm_object *object)
{
struct nvkm_i2c_pad *pad = (void *)object;
DBG("-> PORT:%02x\n", pad->next->index);
pad->port = pad->next;
- return nouveau_object_init(&pad->base);
+ return nvkm_object_init(&pad->base);
}
int
-nvkm_i2c_pad_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int index,
+nvkm_i2c_pad_create_(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int index,
int size, void **pobject)
{
- struct nouveau_i2c *i2c = nouveau_i2c(parent);
- struct nouveau_i2c_port *port;
+ struct nvkm_i2c *i2c = nvkm_i2c(parent);
+ struct nvkm_i2c_port *port;
struct nvkm_i2c_pad *pad;
int ret;
@@ -62,7 +61,7 @@ nvkm_i2c_pad_create_(struct nouveau_object *parent,
}
}
- ret = nouveau_object_create_(parent, engine, oclass, 0, size, pobject);
+ ret = nvkm_object_create_(parent, engine, oclass, 0, size, pobject);
pad = *pobject;
if (ret)
return ret;
@@ -72,9 +71,9 @@ nvkm_i2c_pad_create_(struct nouveau_object *parent,
}
int
-_nvkm_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 index,
- struct nouveau_object **pobject)
+_nvkm_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 index,
+ struct nvkm_object **pobject)
{
struct nvkm_i2c_pad *pad;
int ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h
index f03138b2e42c..f3422cc6f8db 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h
@@ -1,19 +1,18 @@
#ifndef __NVKM_I2C_PAD_H__
#define __NVKM_I2C_PAD_H__
-
#include "priv.h"
struct nvkm_i2c_pad {
- struct nouveau_object base;
+ struct nvkm_object base;
int index;
- struct nouveau_i2c_port *port;
- struct nouveau_i2c_port *next;
+ struct nvkm_i2c_port *port;
+ struct nvkm_i2c_port *next;
};
static inline struct nvkm_i2c_pad *
-nvkm_i2c_pad(struct nouveau_i2c_port *port)
+nvkm_i2c_pad(struct nvkm_i2c_port *port)
{
- struct nouveau_object *pad = nv_object(port);
+ struct nvkm_object *pad = nv_object(port);
while (!nv_iclass(pad->parent, NV_SUBDEV_CLASS))
pad = pad->parent;
return (void *)pad;
@@ -34,15 +33,15 @@ nvkm_i2c_pad(struct nouveau_i2c_port *port)
_nvkm_i2c_pad_fini(nv_object(_p), (s)); \
})
-int nvkm_i2c_pad_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int index, int, void **);
+int nvkm_i2c_pad_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int index, int, void **);
-int _nvkm_i2c_pad_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-#define _nvkm_i2c_pad_dtor nouveau_object_destroy
-int _nvkm_i2c_pad_init(struct nouveau_object *);
-int _nvkm_i2c_pad_fini(struct nouveau_object *, bool);
+int _nvkm_i2c_pad_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+#define _nvkm_i2c_pad_dtor nvkm_object_destroy
+int _nvkm_i2c_pad_init(struct nvkm_object *);
+int _nvkm_i2c_pad_fini(struct nvkm_object *, bool);
#ifndef MSG
#define MSG(l,f,a...) do { \
@@ -54,5 +53,4 @@ int _nvkm_i2c_pad_fini(struct nouveau_object *, bool);
#define DBG(f,a...) MSG(debug, f, ##a)
#define ERR(f,a...) MSG(error, f, ##a)
#endif
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.c
similarity index 73%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv94.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.c
index afe79892f3be..e9832f7a7e38 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv94.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.c
@@ -21,28 +21,27 @@
*
* Authors: Ben Skeggs
*/
-
#include "pad.h"
-struct nv94_i2c_pad {
+struct g94_i2c_pad {
struct nvkm_i2c_pad base;
int addr;
};
static int
-nv94_i2c_pad_fini(struct nouveau_object *object, bool suspend)
+g94_i2c_pad_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_i2c *i2c = (void *)nouveau_i2c(object);
- struct nv94_i2c_pad *pad = (void *)object;
+ struct nvkm_i2c *i2c = (void *)nvkm_i2c(object);
+ struct g94_i2c_pad *pad = (void *)object;
nv_mask(i2c, 0x00e50c + pad->addr, 0x00000001, 0x00000001);
return nvkm_i2c_pad_fini(&pad->base, suspend);
}
static int
-nv94_i2c_pad_init(struct nouveau_object *object)
+g94_i2c_pad_init(struct nvkm_object *object)
{
- struct nouveau_i2c *i2c = (void *)nouveau_i2c(object);
- struct nv94_i2c_pad *pad = (void *)object;
+ struct nvkm_i2c *i2c = (void *)nvkm_i2c(object);
+ struct g94_i2c_pad *pad = (void *)object;
switch (nv_oclass(pad->base.next)->handle) {
case NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX):
@@ -59,11 +58,11 @@ nv94_i2c_pad_init(struct nouveau_object *object)
}
static int
-nv94_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 index,
- struct nouveau_object **pobject)
+g94_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 index,
+ struct nvkm_object **pobject)
{
- struct nv94_i2c_pad *pad;
+ struct g94_i2c_pad *pad;
int ret;
ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad);
@@ -75,12 +74,12 @@ nv94_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
-nv94_i2c_pad_oclass = {
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv94_i2c_pad_ctor,
+struct nvkm_oclass
+g94_i2c_pad_oclass = {
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g94_i2c_pad_ctor,
.dtor = _nvkm_i2c_pad_dtor,
- .init = nv94_i2c_pad_init,
- .fini = nv94_i2c_pad_fini,
+ .init = g94_i2c_pad_init,
+ .fini = g94_i2c_pad_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm204.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm204.c
index 1630a934bece..be590405444d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm204.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm204.c
@@ -21,7 +21,6 @@
*
* Authors: Ben Skeggs
*/
-
#include "pad.h"
struct gm204_i2c_pad {
@@ -30,18 +29,18 @@ struct gm204_i2c_pad {
};
static int
-gm204_i2c_pad_fini(struct nouveau_object *object, bool suspend)
+gm204_i2c_pad_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_i2c *i2c = (void *)nouveau_i2c(object);
+ struct nvkm_i2c *i2c = (void *)nvkm_i2c(object);
struct gm204_i2c_pad *pad = (void *)object;
nv_mask(i2c, 0x00d97c + pad->addr, 0x00000001, 0x00000001);
return nvkm_i2c_pad_fini(&pad->base, suspend);
}
static int
-gm204_i2c_pad_init(struct nouveau_object *object)
+gm204_i2c_pad_init(struct nvkm_object *object)
{
- struct nouveau_i2c *i2c = (void *)nouveau_i2c(object);
+ struct nvkm_i2c *i2c = (void *)nvkm_i2c(object);
struct gm204_i2c_pad *pad = (void *)object;
switch (nv_oclass(pad->base.next)->handle) {
@@ -59,9 +58,9 @@ gm204_i2c_pad_init(struct nouveau_object *object)
}
static int
-gm204_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 index,
- struct nouveau_object **pobject)
+gm204_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 index,
+ struct nvkm_object **pobject)
{
struct gm204_i2c_pad *pad;
int ret;
@@ -75,9 +74,9 @@ gm204_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
gm204_i2c_pad_oclass = {
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm204_i2c_pad_ctor,
.dtor = _nvkm_i2c_pad_dtor,
.init = gm204_i2c_pad_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.c
index 2c4b61296dd1..22c7daaad3a0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.c
@@ -21,12 +21,11 @@
*
* Authors: Ben Skeggs
*/
-
#include "pad.h"
-struct nouveau_oclass
+struct nvkm_oclass
nv04_i2c_pad_oclass = {
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_i2c_pad_ctor,
.dtor = _nvkm_i2c_pad_dtor,
.init = _nvkm_i2c_pad_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/port.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/port.h
index b9acf788e960..586f53dad813 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/port.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/port.h
@@ -1,15 +1,13 @@
#ifndef __NVKM_I2C_PORT_H__
#define __NVKM_I2C_PORT_H__
-
#include "priv.h"
#ifndef MSG
#define MSG(l,f,a...) do { \
- struct nouveau_i2c_port *_port = (void *)port; \
+ struct nvkm_i2c_port *_port = (void *)port; \
nv_##l(_port, "PORT:%02x: "f, _port->index, ##a); \
} while(0)
#define DBG(f,a...) MSG(debug, f, ##a)
#define ERR(f,a...) MSG(error, f, ##a)
#endif
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h
index 4fe7ae3fde4e..6586e1567fcf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h
@@ -1,70 +1,69 @@
-#ifndef __NVKM_I2C_H__
-#define __NVKM_I2C_H__
-
+#ifndef __NVKM_I2C_PRIV_H__
+#define __NVKM_I2C_PRIV_H__
#include <subdev/i2c.h>
-extern struct nouveau_oclass nv04_i2c_pad_oclass;
-extern struct nouveau_oclass nv94_i2c_pad_oclass;
-extern struct nouveau_oclass gm204_i2c_pad_oclass;
+extern struct nvkm_oclass nv04_i2c_pad_oclass;
+extern struct nvkm_oclass g94_i2c_pad_oclass;
+extern struct nvkm_oclass gm204_i2c_pad_oclass;
-#define nouveau_i2c_port_create(p,e,o,i,a,f,d) \
- nouveau_i2c_port_create_((p), (e), (o), (i), (a), (f), \
+#define nvkm_i2c_port_create(p,e,o,i,a,f,d) \
+ nvkm_i2c_port_create_((p), (e), (o), (i), (a), (f), \
sizeof(**d), (void **)d)
-#define nouveau_i2c_port_destroy(p) ({ \
- struct nouveau_i2c_port *port = (p); \
- _nouveau_i2c_port_dtor(nv_object(i2c)); \
+#define nvkm_i2c_port_destroy(p) ({ \
+ struct nvkm_i2c_port *port = (p); \
+ _nvkm_i2c_port_dtor(nv_object(i2c)); \
})
-#define nouveau_i2c_port_init(p) \
- nouveau_object_init(&(p)->base)
-#define nouveau_i2c_port_fini(p,s) \
- nouveau_object_fini(&(p)->base, (s))
+#define nvkm_i2c_port_init(p) \
+ nvkm_object_init(&(p)->base)
+#define nvkm_i2c_port_fini(p,s) \
+ nvkm_object_fini(&(p)->base, (s))
-int nouveau_i2c_port_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, u8,
+int nvkm_i2c_port_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, u8,
const struct i2c_algorithm *,
- const struct nouveau_i2c_func *,
+ const struct nvkm_i2c_func *,
int, void **);
-void _nouveau_i2c_port_dtor(struct nouveau_object *);
-#define _nouveau_i2c_port_init nouveau_object_init
-int _nouveau_i2c_port_fini(struct nouveau_object *, bool);
+void _nvkm_i2c_port_dtor(struct nvkm_object *);
+#define _nvkm_i2c_port_init nvkm_object_init
+int _nvkm_i2c_port_fini(struct nvkm_object *, bool);
-#define nouveau_i2c_create(p,e,o,d) \
- nouveau_i2c_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_i2c_destroy(p) ({ \
- struct nouveau_i2c *i2c = (p); \
- _nouveau_i2c_dtor(nv_object(i2c)); \
+#define nvkm_i2c_create(p,e,o,d) \
+ nvkm_i2c_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_i2c_destroy(p) ({ \
+ struct nvkm_i2c *i2c = (p); \
+ _nvkm_i2c_dtor(nv_object(i2c)); \
})
-#define nouveau_i2c_init(p) ({ \
- struct nouveau_i2c *i2c = (p); \
- _nouveau_i2c_init(nv_object(i2c)); \
+#define nvkm_i2c_init(p) ({ \
+ struct nvkm_i2c *i2c = (p); \
+ _nvkm_i2c_init(nv_object(i2c)); \
})
-#define nouveau_i2c_fini(p,s) ({ \
- struct nouveau_i2c *i2c = (p); \
- _nouveau_i2c_fini(nv_object(i2c), (s)); \
+#define nvkm_i2c_fini(p,s) ({ \
+ struct nvkm_i2c *i2c = (p); \
+ _nvkm_i2c_fini(nv_object(i2c), (s)); \
})
-int nouveau_i2c_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-int _nouveau_i2c_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void _nouveau_i2c_dtor(struct nouveau_object *);
-int _nouveau_i2c_init(struct nouveau_object *);
-int _nouveau_i2c_fini(struct nouveau_object *, bool);
+int nvkm_i2c_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+int _nvkm_i2c_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void _nvkm_i2c_dtor(struct nvkm_object *);
+int _nvkm_i2c_init(struct nvkm_object *);
+int _nvkm_i2c_fini(struct nvkm_object *, bool);
-extern struct nouveau_oclass nouveau_anx9805_sclass[];
-extern struct nouveau_oclass nvd0_i2c_sclass[];
+extern struct nvkm_oclass nvkm_anx9805_sclass[];
+extern struct nvkm_oclass gf110_i2c_sclass[];
-extern const struct i2c_algorithm nouveau_i2c_bit_algo;
-extern const struct i2c_algorithm nouveau_i2c_aux_algo;
+extern const struct i2c_algorithm nvkm_i2c_bit_algo;
+extern const struct i2c_algorithm nvkm_i2c_aux_algo;
-struct nouveau_i2c_impl {
- struct nouveau_oclass base;
+struct nvkm_i2c_impl {
+ struct nvkm_oclass base;
/* supported i2c port classes */
- struct nouveau_oclass *sclass;
- struct nouveau_oclass *pad_x;
- struct nouveau_oclass *pad_s;
+ struct nvkm_oclass *sclass;
+ struct nvkm_oclass *pad_x;
+ struct nvkm_oclass *pad_s;
/* number of native dp aux channels present */
int aux;
@@ -73,17 +72,16 @@ struct nouveau_i2c_impl {
* for ports that have not been masked off, while still
* performing the ack for anything that was pending.
*/
- void (*aux_stat)(struct nouveau_i2c *, u32 *, u32 *, u32 *, u32 *);
+ void (*aux_stat)(struct nvkm_i2c *, u32 *, u32 *, u32 *, u32 *);
/* mask on/off interrupt types for a given set of auxch
*/
- void (*aux_mask)(struct nouveau_i2c *, u32, u32, u32);
+ void (*aux_mask)(struct nvkm_i2c *, u32, u32, u32);
};
-void nv94_aux_stat(struct nouveau_i2c *, u32 *, u32 *, u32 *, u32 *);
-void nv94_aux_mask(struct nouveau_i2c *, u32, u32, u32);
-
-void nve0_aux_stat(struct nouveau_i2c *, u32 *, u32 *, u32 *, u32 *);
-void nve0_aux_mask(struct nouveau_i2c *, u32, u32, u32);
+void g94_aux_stat(struct nvkm_i2c *, u32 *, u32 *, u32 *, u32 *);
+void g94_aux_mask(struct nvkm_i2c *, u32, u32, u32);
+void gk104_aux_stat(struct nvkm_i2c *, u32 *, u32 *, u32 *, u32 *);
+void gk104_aux_mask(struct nvkm_i2c *, u32, u32, u32);
#endif
From 5ecfadeb89a63b414bfd26ad469b39037930485e Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:04:31 +1000
Subject: [PATCH 61/86] drm/nouveau/ibus: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/subdev/ibus.h | 45 ++++++++--------
.../drm/nouveau/nvkm/engine/device/gm100.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +++----
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 ++---
.../gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild | 4 +-
.../nvkm/subdev/ibus/{nvc0.c => gf100.c} | 47 ++++++++--------
.../nvkm/subdev/ibus/{nve0.c => gk104.c} | 53 +++++++++----------
.../gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c | 25 +++++----
8 files changed, 102 insertions(+), 108 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/subdev/ibus/{nvc0.c => gf100.c} (75%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/ibus/{nve0.c => gk104.c} (75%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h
index b6387d27ea0c..2150d8af0040 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h
@@ -1,35 +1,32 @@
-#ifndef __NOUVEAU_IBUS_H__
-#define __NOUVEAU_IBUS_H__
-
+#ifndef __NVKM_IBUS_H__
+#define __NVKM_IBUS_H__
#include <core/subdev.h>
-#include <core/device.h>
-struct nouveau_ibus {
- struct nouveau_subdev base;
+struct nvkm_ibus {
+ struct nvkm_subdev base;
};
-static inline struct nouveau_ibus *
-nouveau_ibus(void *obj)
+static inline struct nvkm_ibus *
+nvkm_ibus(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_IBUS);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_IBUS);
}
-#define nouveau_ibus_create(p,e,o,d) \
- nouveau_subdev_create_((p), (e), (o), 0, "PIBUS", "ibus", \
+#define nvkm_ibus_create(p,e,o,d) \
+ nvkm_subdev_create_((p), (e), (o), 0, "PIBUS", "ibus", \
sizeof(**d), (void **)d)
-#define nouveau_ibus_destroy(p) \
- nouveau_subdev_destroy(&(p)->base)
-#define nouveau_ibus_init(p) \
- nouveau_subdev_init(&(p)->base)
-#define nouveau_ibus_fini(p,s) \
- nouveau_subdev_fini(&(p)->base, (s))
+#define nvkm_ibus_destroy(p) \
+ nvkm_subdev_destroy(&(p)->base)
+#define nvkm_ibus_init(p) \
+ nvkm_subdev_init(&(p)->base)
+#define nvkm_ibus_fini(p,s) \
+ nvkm_subdev_fini(&(p)->base, (s))
-#define _nouveau_ibus_dtor _nouveau_subdev_dtor
-#define _nouveau_ibus_init _nouveau_subdev_init
-#define _nouveau_ibus_fini _nouveau_subdev_fini
-
-extern struct nouveau_oclass nvc0_ibus_oclass;
-extern struct nouveau_oclass nve0_ibus_oclass;
-extern struct nouveau_oclass gk20a_ibus_oclass;
+#define _nvkm_ibus_dtor _nvkm_subdev_dtor
+#define _nvkm_ibus_init _nvkm_subdev_init
+#define _nvkm_ibus_fini _nvkm_subdev_fini
+extern struct nvkm_oclass gf100_ibus_oclass;
+extern struct nvkm_oclass gk104_ibus_oclass;
+extern struct nvkm_oclass gk20a_ibus_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index e2581c408bd4..165271cf9959 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -74,7 +74,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -118,7 +118,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 310fd4113e90..fbe552e825b8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -74,7 +74,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -107,7 +107,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -140,7 +140,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -172,7 +172,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -205,7 +205,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -237,7 +237,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -269,7 +269,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -302,7 +302,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -334,7 +334,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 89ac2ca1f85f..a9b5aa3d9ed1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -74,7 +74,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -108,7 +108,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -142,7 +142,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -198,7 +198,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -232,7 +232,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -266,7 +266,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@@ -299,7 +299,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
+ device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild
index a006e535e450..a0b12d27284a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild
@@ -1,3 +1,3 @@
-nvkm-y += nvkm/subdev/ibus/nvc0.o
-nvkm-y += nvkm/subdev/ibus/nve0.o
+nvkm-y += nvkm/subdev/ibus/gf100.o
+nvkm-y += nvkm/subdev/ibus/gk104.o
nvkm-y += nvkm/subdev/ibus/gk20a.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c
similarity index 75%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/ibus/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c
index 4e977ff27e44..8e578f802f66 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/ibus.h>
-struct nvc0_ibus_priv {
- struct nouveau_ibus base;
+struct gf100_ibus_priv {
+ struct nvkm_ibus base;
};
static void
-nvc0_ibus_intr_hub(struct nvc0_ibus_priv *priv, int i)
+gf100_ibus_intr_hub(struct gf100_ibus_priv *priv, int i)
{
u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0400));
u32 data = nv_rd32(priv, 0x122124 + (i * 0x0400));
@@ -39,7 +38,7 @@ nvc0_ibus_intr_hub(struct nvc0_ibus_priv *priv, int i)
}
static void
-nvc0_ibus_intr_rop(struct nvc0_ibus_priv *priv, int i)
+gf100_ibus_intr_rop(struct gf100_ibus_priv *priv, int i)
{
u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0400));
u32 data = nv_rd32(priv, 0x124124 + (i * 0x0400));
@@ -49,7 +48,7 @@ nvc0_ibus_intr_rop(struct nvc0_ibus_priv *priv, int i)
}
static void
-nvc0_ibus_intr_gpc(struct nvc0_ibus_priv *priv, int i)
+gf100_ibus_intr_gpc(struct gf100_ibus_priv *priv, int i)
{
u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0400));
u32 data = nv_rd32(priv, 0x128124 + (i * 0x0400));
@@ -59,9 +58,9 @@ nvc0_ibus_intr_gpc(struct nvc0_ibus_priv *priv, int i)
}
static void
-nvc0_ibus_intr(struct nouveau_subdev *subdev)
+gf100_ibus_intr(struct nvkm_subdev *subdev)
{
- struct nvc0_ibus_priv *priv = (void *)subdev;
+ struct gf100_ibus_priv *priv = (void *)subdev;
u32 intr0 = nv_rd32(priv, 0x121c58);
u32 intr1 = nv_rd32(priv, 0x121c5c);
u32 hubnr = nv_rd32(priv, 0x121c70);
@@ -72,7 +71,7 @@ nvc0_ibus_intr(struct nouveau_subdev *subdev)
for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) {
u32 stat = 0x00000100 << i;
if (intr0 & stat) {
- nvc0_ibus_intr_hub(priv, i);
+ gf100_ibus_intr_hub(priv, i);
intr0 &= ~stat;
}
}
@@ -80,7 +79,7 @@ nvc0_ibus_intr(struct nouveau_subdev *subdev)
for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) {
u32 stat = 0x00010000 << i;
if (intr0 & stat) {
- nvc0_ibus_intr_rop(priv, i);
+ gf100_ibus_intr_rop(priv, i);
intr0 &= ~stat;
}
}
@@ -88,36 +87,36 @@ nvc0_ibus_intr(struct nouveau_subdev *subdev)
for (i = 0; intr1 && i < gpcnr; i++) {
u32 stat = 0x00000001 << i;
if (intr1 & stat) {
- nvc0_ibus_intr_gpc(priv, i);
+ gf100_ibus_intr_gpc(priv, i);
intr1 &= ~stat;
}
}
}
static int
-nvc0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvc0_ibus_priv *priv;
+ struct gf100_ibus_priv *priv;
int ret;
- ret = nouveau_ibus_create(parent, engine, oclass, &priv);
+ ret = nvkm_ibus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- nv_subdev(priv)->intr = nvc0_ibus_intr;
+ nv_subdev(priv)->intr = gf100_ibus_intr;
return 0;
}
-struct nouveau_oclass
-nvc0_ibus_oclass = {
+struct nvkm_oclass
+gf100_ibus_oclass = {
.handle = NV_SUBDEV(IBUS, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_ibus_ctor,
- .dtor = _nouveau_ibus_dtor,
- .init = _nouveau_ibus_init,
- .fini = _nouveau_ibus_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_ibus_ctor,
+ .dtor = _nvkm_ibus_dtor,
+ .init = _nvkm_ibus_init,
+ .fini = _nvkm_ibus_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c
similarity index 75%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/ibus/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c
index ebef970a0645..7b6e9a6cd7b2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/ibus.h>
-struct nve0_ibus_priv {
- struct nouveau_ibus base;
+struct gk104_ibus_priv {
+ struct nvkm_ibus base;
};
static void
-nve0_ibus_intr_hub(struct nve0_ibus_priv *priv, int i)
+gk104_ibus_intr_hub(struct gk104_ibus_priv *priv, int i)
{
u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0800));
u32 data = nv_rd32(priv, 0x122124 + (i * 0x0800));
@@ -39,7 +38,7 @@ nve0_ibus_intr_hub(struct nve0_ibus_priv *priv, int i)
}
static void
-nve0_ibus_intr_rop(struct nve0_ibus_priv *priv, int i)
+gk104_ibus_intr_rop(struct gk104_ibus_priv *priv, int i)
{
u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0800));
u32 data = nv_rd32(priv, 0x124124 + (i * 0x0800));
@@ -49,7 +48,7 @@ nve0_ibus_intr_rop(struct nve0_ibus_priv *priv, int i)
}
static void
-nve0_ibus_intr_gpc(struct nve0_ibus_priv *priv, int i)
+gk104_ibus_intr_gpc(struct gk104_ibus_priv *priv, int i)
{
u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0800));
u32 data = nv_rd32(priv, 0x128124 + (i * 0x0800));
@@ -59,9 +58,9 @@ nve0_ibus_intr_gpc(struct nve0_ibus_priv *priv, int i)
}
static void
-nve0_ibus_intr(struct nouveau_subdev *subdev)
+gk104_ibus_intr(struct nvkm_subdev *subdev)
{
- struct nve0_ibus_priv *priv = (void *)subdev;
+ struct gk104_ibus_priv *priv = (void *)subdev;
u32 intr0 = nv_rd32(priv, 0x120058);
u32 intr1 = nv_rd32(priv, 0x12005c);
u32 hubnr = nv_rd32(priv, 0x120070);
@@ -72,7 +71,7 @@ nve0_ibus_intr(struct nouveau_subdev *subdev)
for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) {
u32 stat = 0x00000100 << i;
if (intr0 & stat) {
- nve0_ibus_intr_hub(priv, i);
+ gk104_ibus_intr_hub(priv, i);
intr0 &= ~stat;
}
}
@@ -80,7 +79,7 @@ nve0_ibus_intr(struct nouveau_subdev *subdev)
for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) {
u32 stat = 0x00010000 << i;
if (intr0 & stat) {
- nve0_ibus_intr_rop(priv, i);
+ gk104_ibus_intr_rop(priv, i);
intr0 &= ~stat;
}
}
@@ -88,17 +87,17 @@ nve0_ibus_intr(struct nouveau_subdev *subdev)
for (i = 0; intr1 && i < gpcnr; i++) {
u32 stat = 0x00000001 << i;
if (intr1 & stat) {
- nve0_ibus_intr_gpc(priv, i);
+ gk104_ibus_intr_gpc(priv, i);
intr1 &= ~stat;
}
}
}
static int
-nve0_ibus_init(struct nouveau_object *object)
+gk104_ibus_init(struct nvkm_object *object)
{
- struct nve0_ibus_priv *priv = (void *)object;
- int ret = nouveau_ibus_init(&priv->base);
+ struct gk104_ibus_priv *priv = (void *)object;
+ int ret = nvkm_ibus_init(&priv->base);
if (ret == 0) {
nv_mask(priv, 0x122318, 0x0003ffff, 0x00001000);
nv_mask(priv, 0x12231c, 0x0003ffff, 0x00000200);
@@ -112,29 +111,29 @@ nve0_ibus_init(struct nouveau_object *object)
}
static int
-nve0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk104_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nve0_ibus_priv *priv;
+ struct gk104_ibus_priv *priv;
int ret;
- ret = nouveau_ibus_create(parent, engine, oclass, &priv);
+ ret = nvkm_ibus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- nv_subdev(priv)->intr = nve0_ibus_intr;
+ nv_subdev(priv)->intr = gk104_ibus_intr;
return 0;
}
-struct nouveau_oclass
-nve0_ibus_oclass = {
+struct nvkm_oclass
+gk104_ibus_oclass = {
.handle = NV_SUBDEV(IBUS, 0xe0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_ibus_ctor,
- .dtor = _nouveau_ibus_dtor,
- .init = nve0_ibus_init,
- .fini = _nouveau_ibus_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_ibus_ctor,
+ .dtor = _nvkm_ibus_dtor,
+ .init = gk104_ibus_init,
+ .fini = _nvkm_ibus_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c
index 245f0ebaa6af..c0fdb89e74ac 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c
@@ -19,12 +19,11 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
-
#include <subdev/ibus.h>
#include <subdev/timer.h>
struct gk20a_ibus_priv {
- struct nouveau_ibus base;
+ struct nvkm_ibus base;
};
static void
@@ -42,7 +41,7 @@ gk20a_ibus_init_priv_ring(struct gk20a_ibus_priv *priv)
}
static void
-gk20a_ibus_intr(struct nouveau_subdev *subdev)
+gk20a_ibus_intr(struct nvkm_subdev *subdev)
{
struct gk20a_ibus_priv *priv = (void *)subdev;
u32 status0 = nv_rd32(priv, 0x120058);
@@ -60,12 +59,12 @@ gk20a_ibus_intr(struct nouveau_subdev *subdev)
}
static int
-gk20a_ibus_init(struct nouveau_object *object)
+gk20a_ibus_init(struct nvkm_object *object)
{
struct gk20a_ibus_priv *priv = (void *)object;
int ret;
- ret = _nouveau_ibus_init(object);
+ ret = _nvkm_ibus_init(object);
if (ret)
return ret;
@@ -75,14 +74,14 @@ gk20a_ibus_init(struct nouveau_object *object)
}
static int
-gk20a_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk20a_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct gk20a_ibus_priv *priv;
int ret;
- ret = nouveau_ibus_create(parent, engine, oclass, &priv);
+ ret = nvkm_ibus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -91,13 +90,13 @@ gk20a_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
gk20a_ibus_oclass = {
.handle = NV_SUBDEV(IBUS, 0xea),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_ibus_ctor,
- .dtor = _nouveau_ibus_dtor,
+ .dtor = _nvkm_ibus_dtor,
.init = gk20a_ibus_init,
- .fini = _nouveau_ibus_fini,
+ .fini = _nvkm_ibus_fini,
},
};
From 78b2b4e76be2100637a92b9721aaa2ce73d0fa22 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:05:26 +1000
Subject: [PATCH 62/86] drm/nouveau/instmem: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/subdev/instmem.h | 34 +++----
.../gpu/drm/nouveau/nvkm/subdev/i2c/base.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c | 2 +-
.../drm/nouveau/nvkm/subdev/instmem/base.c | 74 +++++++--------
.../drm/nouveau/nvkm/subdev/instmem/nv04.c | 95 ++++++++++---------
.../drm/nouveau/nvkm/subdev/instmem/nv04.h | 34 +++----
.../drm/nouveau/nvkm/subdev/instmem/nv40.c | 47 +++++----
.../drm/nouveau/nvkm/subdev/instmem/nv50.c | 68 +++++++------
.../drm/nouveau/nvkm/subdev/instmem/priv.h | 72 +++++++-------
9 files changed, 203 insertions(+), 225 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
index 4953e6c6c86b..d104c1aac807 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
@@ -1,19 +1,16 @@
-#ifndef __NOUVEAU_INSTMEM_H__
-#define __NOUVEAU_INSTMEM_H__
-
+#ifndef __NVKM_INSTMEM_H__
+#define __NVKM_INSTMEM_H__
#include <core/subdev.h>
-#include <core/device.h>
-#include <core/mm.h>
-struct nouveau_instobj {
- struct nouveau_object base;
+struct nvkm_instobj {
+ struct nvkm_object base;
struct list_head head;
u32 *suspend;
u64 addr;
u32 size;
};
-static inline struct nouveau_instobj *
+static inline struct nvkm_instobj *
nv_memobj(void *obj)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
@@ -23,17 +20,17 @@ nv_memobj(void *obj)
return obj;
}
-struct nouveau_instmem {
- struct nouveau_subdev base;
+struct nvkm_instmem {
+ struct nvkm_subdev base;
struct list_head list;
u32 reserved;
- int (*alloc)(struct nouveau_instmem *, struct nouveau_object *,
- u32 size, u32 align, struct nouveau_object **);
+ int (*alloc)(struct nvkm_instmem *, struct nvkm_object *,
+ u32 size, u32 align, struct nvkm_object **);
};
-static inline struct nouveau_instmem *
-nouveau_instmem(void *obj)
+static inline struct nvkm_instmem *
+nvkm_instmem(void *obj)
{
/* nv04/nv40 impls need to create objects in their constructor,
* which is before the subdev pointer is valid
@@ -42,11 +39,10 @@ nouveau_instmem(void *obj)
nv_subidx(obj) == NVDEV_SUBDEV_INSTMEM)
return obj;
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_INSTMEM);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_INSTMEM);
}
-extern struct nouveau_oclass *nv04_instmem_oclass;
-extern struct nouveau_oclass *nv40_instmem_oclass;
-extern struct nouveau_oclass *nv50_instmem_oclass;
-
+extern struct nvkm_oclass *nv04_instmem_oclass;
+extern struct nvkm_oclass *nv40_instmem_oclass;
+extern struct nvkm_oclass *nv50_instmem_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
index bfb0388f8d5b..9200f122c02c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
@@ -34,7 +34,7 @@
* interface to linux i2c bit-banging algorithm
*****************************************************************************/
-#ifdef CONFIG_NVKM_I2C_INTERNAL_DEFAULT
+#ifdef CONFIG_NOUVEAU_I2C_INTERNAL_DEFAULT
#define CSTMSEL true
#else
#define CSTMSEL false
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c
index 35132badaa8f..861a453d2a67 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c
@@ -23,7 +23,7 @@
*/
#include "priv.h"
-#ifdef CONFIG_NVKM_I2C_INTERNAL
+#ifdef CONFIG_NOUVEAU_I2C_INTERNAL
#define T_TIMEOUT 2200000
#define T_RISEFALL 1000
#define T_HOLD 5000
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
index 767fcf70f98f..d16358cc6cbb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
@@ -21,38 +21,37 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
+#include <core/engine.h>
+
/******************************************************************************
* instmem object base implementation
*****************************************************************************/
void
-_nouveau_instobj_dtor(struct nouveau_object *object)
+_nvkm_instobj_dtor(struct nvkm_object *object)
{
- struct nouveau_instmem *imem = nouveau_instmem(object);
- struct nouveau_instobj *iobj = (void *)object;
+ struct nvkm_instmem *imem = nvkm_instmem(object);
+ struct nvkm_instobj *iobj = (void *)object;
mutex_lock(&nv_subdev(imem)->mutex);
list_del(&iobj->head);
mutex_unlock(&nv_subdev(imem)->mutex);
- return nouveau_object_destroy(&iobj->base);
+ return nvkm_object_destroy(&iobj->base);
}
int
-nouveau_instobj_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass,
- int length, void **pobject)
+nvkm_instobj_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
- struct nouveau_instmem *imem = nouveau_instmem(parent);
- struct nouveau_instobj *iobj;
+ struct nvkm_instmem *imem = nvkm_instmem(parent);
+ struct nvkm_instobj *iobj;
int ret;
- ret = nouveau_object_create_(parent, engine, oclass, NV_MEMOBJ_CLASS,
- length, pobject);
+ ret = nvkm_object_create_(parent, engine, oclass, NV_MEMOBJ_CLASS,
+ length, pobject);
iobj = *pobject;
if (ret)
return ret;
@@ -68,26 +67,24 @@ nouveau_instobj_create_(struct nouveau_object *parent,
*****************************************************************************/
static int
-nouveau_instmem_alloc(struct nouveau_instmem *imem,
- struct nouveau_object *parent, u32 size, u32 align,
- struct nouveau_object **pobject)
+nvkm_instmem_alloc(struct nvkm_instmem *imem, struct nvkm_object *parent,
+ u32 size, u32 align, struct nvkm_object **pobject)
{
- struct nouveau_instmem_impl *impl = (void *)imem->base.object.oclass;
- struct nouveau_instobj_args args = { .size = size, .align = align };
- return nouveau_object_ctor(parent, &parent->engine->subdev.object,
- impl->instobj, &args, sizeof(args), pobject);
+ struct nvkm_instmem_impl *impl = (void *)imem->base.object.oclass;
+ struct nvkm_instobj_args args = { .size = size, .align = align };
+ return nvkm_object_ctor(parent, &parent->engine->subdev.object,
+ impl->instobj, &args, sizeof(args), pobject);
}
int
-_nouveau_instmem_fini(struct nouveau_object *object, bool suspend)
+_nvkm_instmem_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_instmem *imem = (void *)object;
- struct nouveau_instobj *iobj;
+ struct nvkm_instmem *imem = (void *)object;
+ struct nvkm_instobj *iobj;
int i, ret = 0;
if (suspend) {
mutex_lock(&imem->base.mutex);
-
list_for_each_entry(iobj, &imem->list, head) {
iobj->suspend = vmalloc(iobj->size);
if (!iobj->suspend) {
@@ -98,29 +95,26 @@ _nouveau_instmem_fini(struct nouveau_object *object, bool suspend)
for (i = 0; i < iobj->size; i += 4)
iobj->suspend[i / 4] = nv_ro32(iobj, i);
}
-
mutex_unlock(&imem->base.mutex);
-
if (ret)
return ret;
}
- return nouveau_subdev_fini(&imem->base, suspend);
+ return nvkm_subdev_fini(&imem->base, suspend);
}
int
-_nouveau_instmem_init(struct nouveau_object *object)
+_nvkm_instmem_init(struct nvkm_object *object)
{
- struct nouveau_instmem *imem = (void *)object;
- struct nouveau_instobj *iobj;
+ struct nvkm_instmem *imem = (void *)object;
+ struct nvkm_instobj *iobj;
int ret, i;
- ret = nouveau_subdev_init(&imem->base);
+ ret = nvkm_subdev_init(&imem->base);
if (ret)
return ret;
mutex_lock(&imem->base.mutex);
-
list_for_each_entry(iobj, &imem->list, head) {
if (iobj->suspend) {
for (i = 0; i < iobj->size; i += 4)
@@ -129,28 +123,24 @@ _nouveau_instmem_init(struct nouveau_object *object)
iobj->suspend = NULL;
}
}
-
mutex_unlock(&imem->base.mutex);
-
return 0;
}
int
-nouveau_instmem_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass,
- int length, void **pobject)
+nvkm_instmem_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
- struct nouveau_instmem *imem;
+ struct nvkm_instmem *imem;
int ret;
- ret = nouveau_subdev_create_(parent, engine, oclass, 0,
- "INSTMEM", "instmem", length, pobject);
+ ret = nvkm_subdev_create_(parent, engine, oclass, 0, "INSTMEM",
+ "instmem", length, pobject);
imem = *pobject;
if (ret)
return ret;
INIT_LIST_HEAD(&imem->list);
- imem->alloc = nouveau_instmem_alloc;
+ imem->alloc = nvkm_instmem_alloc;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c
index 9ffd2d8d73c4..80614f1b2074 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c
@@ -21,58 +21,59 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
+#include <core/ramht.h>
+
/******************************************************************************
* instmem object implementation
*****************************************************************************/
static u32
-nv04_instobj_rd32(struct nouveau_object *object, u64 addr)
+nv04_instobj_rd32(struct nvkm_object *object, u64 addr)
{
- struct nv04_instmem_priv *priv = (void *)nouveau_instmem(object);
+ struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object);
struct nv04_instobj_priv *node = (void *)object;
return nv_ro32(priv, node->mem->offset + addr);
}
static void
-nv04_instobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
+nv04_instobj_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
- struct nv04_instmem_priv *priv = (void *)nouveau_instmem(object);
+ struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object);
struct nv04_instobj_priv *node = (void *)object;
nv_wo32(priv, node->mem->offset + addr, data);
}
static void
-nv04_instobj_dtor(struct nouveau_object *object)
+nv04_instobj_dtor(struct nvkm_object *object)
{
- struct nv04_instmem_priv *priv = (void *)nouveau_instmem(object);
+ struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object);
struct nv04_instobj_priv *node = (void *)object;
- nouveau_mm_free(&priv->heap, &node->mem);
- nouveau_instobj_destroy(&node->base);
+ nvkm_mm_free(&priv->heap, &node->mem);
+ nvkm_instobj_destroy(&node->base);
}
static int
-nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nv04_instmem_priv *priv = (void *)nouveau_instmem(parent);
+ struct nv04_instmem_priv *priv = (void *)nvkm_instmem(parent);
struct nv04_instobj_priv *node;
- struct nouveau_instobj_args *args = data;
+ struct nvkm_instobj_args *args = data;
int ret;
if (!args->align)
args->align = 1;
- ret = nouveau_instobj_create(parent, engine, oclass, &node);
+ ret = nvkm_instobj_create(parent, engine, oclass, &node);
*pobject = nv_object(node);
if (ret)
return ret;
- ret = nouveau_mm_head(&priv->heap, 0, 1, args->size, args->size,
- args->align, &node->mem);
+ ret = nvkm_mm_head(&priv->heap, 0, 1, args->size, args->size,
+ args->align, &node->mem);
if (ret)
return ret;
@@ -81,13 +82,13 @@ nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_instobj_impl
+struct nvkm_instobj_impl
nv04_instobj_oclass = {
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_instobj_ctor,
.dtor = nv04_instobj_dtor,
- .init = _nouveau_instobj_init,
- .fini = _nouveau_instobj_fini,
+ .init = _nvkm_instobj_init,
+ .fini = _nvkm_instobj_fini,
.rd32 = nv04_instobj_rd32,
.wr32 = nv04_instobj_wr32,
},
@@ -98,40 +99,40 @@ nv04_instobj_oclass = {
*****************************************************************************/
static u32
-nv04_instmem_rd32(struct nouveau_object *object, u64 addr)
+nv04_instmem_rd32(struct nvkm_object *object, u64 addr)
{
return nv_rd32(object, 0x700000 + addr);
}
static void
-nv04_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data)
+nv04_instmem_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
return nv_wr32(object, 0x700000 + addr, data);
}
void
-nv04_instmem_dtor(struct nouveau_object *object)
+nv04_instmem_dtor(struct nvkm_object *object)
{
struct nv04_instmem_priv *priv = (void *)object;
- nouveau_gpuobj_ref(NULL, &priv->ramfc);
- nouveau_gpuobj_ref(NULL, &priv->ramro);
- nouveau_ramht_ref(NULL, &priv->ramht);
- nouveau_gpuobj_ref(NULL, &priv->vbios);
- nouveau_mm_fini(&priv->heap);
+ nvkm_gpuobj_ref(NULL, &priv->ramfc);
+ nvkm_gpuobj_ref(NULL, &priv->ramro);
+ nvkm_ramht_ref(NULL, &priv->ramht);
+ nvkm_gpuobj_ref(NULL, &priv->vbios);
+ nvkm_mm_fini(&priv->heap);
if (priv->iomem)
iounmap(priv->iomem);
- nouveau_instmem_destroy(&priv->base);
+ nvkm_instmem_destroy(&priv->base);
}
static int
-nv04_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_instmem_priv *priv;
int ret;
- ret = nouveau_instmem_create(parent, engine, oclass, &priv);
+ ret = nvkm_instmem_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -139,44 +140,44 @@ nv04_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
/* PRAMIN aperture maps over the end of VRAM, reserve it */
priv->base.reserved = 512 * 1024;
- ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1);
+ ret = nvkm_mm_init(&priv->heap, 0, priv->base.reserved, 1);
if (ret)
return ret;
/* 0x00000-0x10000: reserve for probable vbios image */
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0,
- &priv->vbios);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0,
+ &priv->vbios);
if (ret)
return ret;
/* 0x10000-0x18000: reserve for RAMHT */
- ret = nouveau_ramht_new(nv_object(priv), NULL, 0x08000, 0, &priv->ramht);
+ ret = nvkm_ramht_new(nv_object(priv), NULL, 0x08000, 0, &priv->ramht);
if (ret)
return ret;
/* 0x18000-0x18800: reserve for RAMFC (enough for 32 nv30 channels) */
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x00800, 0,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x00800, 0,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc);
if (ret)
return ret;
/* 0x18800-0x18a00: reserve for RAMRO */
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x00200, 0, 0,
- &priv->ramro);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x00200, 0, 0,
+ &priv->ramro);
if (ret)
return ret;
return 0;
}
-struct nouveau_oclass *
-nv04_instmem_oclass = &(struct nouveau_instmem_impl) {
+struct nvkm_oclass *
+nv04_instmem_oclass = &(struct nvkm_instmem_impl) {
.base.handle = NV_SUBDEV(INSTMEM, 0x04),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_instmem_ctor,
.dtor = nv04_instmem_dtor,
- .init = _nouveau_instmem_init,
- .fini = _nouveau_instmem_fini,
+ .init = _nvkm_instmem_init,
+ .fini = _nvkm_instmem_fini,
.rd32 = nv04_instmem_rd32,
.wr32 = nv04_instmem_wr32,
},
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h
index 095fbc6fc099..42b6c928047c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h
@@ -1,40 +1,36 @@
#ifndef __NV04_INSTMEM_H__
#define __NV04_INSTMEM_H__
-
-#include <core/gpuobj.h>
-#include <core/ramht.h>
-#include <core/mm.h>
-
#include "priv.h"
-extern struct nouveau_instobj_impl nv04_instobj_oclass;
+#include <core/mm.h>
+
+extern struct nvkm_instobj_impl nv04_instobj_oclass;
struct nv04_instmem_priv {
- struct nouveau_instmem base;
+ struct nvkm_instmem base;
void __iomem *iomem;
- struct nouveau_mm heap;
+ struct nvkm_mm heap;
- struct nouveau_gpuobj *vbios;
- struct nouveau_ramht *ramht;
- struct nouveau_gpuobj *ramro;
- struct nouveau_gpuobj *ramfc;
+ struct nvkm_gpuobj *vbios;
+ struct nvkm_ramht *ramht;
+ struct nvkm_gpuobj *ramro;
+ struct nvkm_gpuobj *ramfc;
};
static inline struct nv04_instmem_priv *
nv04_instmem(void *obj)
{
- return (void *)nouveau_instmem(obj);
+ return (void *)nvkm_instmem(obj);
}
struct nv04_instobj_priv {
- struct nouveau_instobj base;
- struct nouveau_mm_node *mem;
+ struct nvkm_instobj base;
+ struct nvkm_mm_node *mem;
};
-void nv04_instmem_dtor(struct nouveau_object *);
-
-int nv04_instmem_alloc(struct nouveau_instmem *, struct nouveau_object *,
- u32 size, u32 align, struct nouveau_object **pobject);
+void nv04_instmem_dtor(struct nvkm_object *);
+int nv04_instmem_alloc(struct nvkm_instmem *, struct nvkm_object *,
+ u32 size, u32 align, struct nvkm_object **pobject);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
index f65bc796bcde..b42b8588fc0e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
@@ -21,39 +21,39 @@
*
* Authors: Ben Skeggs
*/
-
-#include <engine/gr/nv40.h>
-
#include "nv04.h"
+#include <core/ramht.h>
+#include <engine/gr/nv40.h>
+
/******************************************************************************
* instmem subdev implementation
*****************************************************************************/
static u32
-nv40_instmem_rd32(struct nouveau_object *object, u64 addr)
+nv40_instmem_rd32(struct nvkm_object *object, u64 addr)
{
struct nv04_instmem_priv *priv = (void *)object;
return ioread32_native(priv->iomem + addr);
}
static void
-nv40_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data)
+nv40_instmem_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
struct nv04_instmem_priv *priv = (void *)object;
iowrite32_native(data, priv->iomem + addr);
}
static int
-nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_device *device = nv_device(parent);
+ struct nvkm_device *device = nv_device(parent);
struct nv04_instmem_priv *priv;
int ret, bar, vs;
- ret = nouveau_instmem_create(parent, engine, oclass, &priv);
+ ret = nvkm_instmem_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -87,49 +87,48 @@ nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.reserved = round_up(priv->base.reserved, 4096);
- ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1);
+ ret = nvkm_mm_init(&priv->heap, 0, priv->base.reserved, 1);
if (ret)
return ret;
/* 0x00000-0x10000: reserve for probable vbios image */
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0,
- &priv->vbios);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0,
+ &priv->vbios);
if (ret)
return ret;
/* 0x10000-0x18000: reserve for RAMHT */
- ret = nouveau_ramht_new(nv_object(priv), NULL, 0x08000, 0,
- &priv->ramht);
+ ret = nvkm_ramht_new(nv_object(priv), NULL, 0x08000, 0, &priv->ramht);
if (ret)
return ret;
/* 0x18000-0x18200: reserve for RAMRO
* 0x18200-0x20000: padding
*/
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x08000, 0, 0,
- &priv->ramro);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x08000, 0, 0,
+ &priv->ramro);
if (ret)
return ret;
/* 0x20000-0x21000: reserve for RAMFC
* 0x21000-0x40000: padding and some unknown crap
*/
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x20000, 0,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x20000, 0,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc);
if (ret)
return ret;
return 0;
}
-struct nouveau_oclass *
-nv40_instmem_oclass = &(struct nouveau_instmem_impl) {
+struct nvkm_oclass *
+nv40_instmem_oclass = &(struct nvkm_instmem_impl) {
.base.handle = NV_SUBDEV(INSTMEM, 0x40),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_instmem_ctor,
.dtor = nv04_instmem_dtor,
- .init = _nouveau_instmem_init,
- .fini = _nouveau_instmem_fini,
+ .init = _nvkm_instmem_init,
+ .fini = _nvkm_instmem_fini,
.rd32 = nv40_instmem_rd32,
.wr32 = nv40_instmem_wr32,
},
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
index 64ee680232e2..8404143f93ee 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
@@ -21,21 +21,19 @@
*
* Authors: Ben Skeggs
*/
-
-#include <subdev/fb.h>
-#include <core/mm.h>
-
#include "priv.h"
+#include <subdev/fb.h>
+
struct nv50_instmem_priv {
- struct nouveau_instmem base;
+ struct nvkm_instmem base;
spinlock_t lock;
u64 addr;
};
struct nv50_instobj_priv {
- struct nouveau_instobj base;
- struct nouveau_mem *mem;
+ struct nvkm_instobj base;
+ struct nvkm_mem *mem;
};
/******************************************************************************
@@ -43,9 +41,9 @@ struct nv50_instobj_priv {
*****************************************************************************/
static u32
-nv50_instobj_rd32(struct nouveau_object *object, u64 offset)
+nv50_instobj_rd32(struct nvkm_object *object, u64 offset)
{
- struct nv50_instmem_priv *priv = (void *)nouveau_instmem(object);
+ struct nv50_instmem_priv *priv = (void *)nvkm_instmem(object);
struct nv50_instobj_priv *node = (void *)object;
unsigned long flags;
u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
@@ -63,9 +61,9 @@ nv50_instobj_rd32(struct nouveau_object *object, u64 offset)
}
static void
-nv50_instobj_wr32(struct nouveau_object *object, u64 offset, u32 data)
+nv50_instobj_wr32(struct nvkm_object *object, u64 offset, u32 data)
{
- struct nv50_instmem_priv *priv = (void *)nouveau_instmem(object);
+ struct nv50_instmem_priv *priv = (void *)nvkm_instmem(object);
struct nv50_instobj_priv *node = (void *)object;
unsigned long flags;
u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
@@ -81,28 +79,28 @@ nv50_instobj_wr32(struct nouveau_object *object, u64 offset, u32 data)
}
static void
-nv50_instobj_dtor(struct nouveau_object *object)
+nv50_instobj_dtor(struct nvkm_object *object)
{
struct nv50_instobj_priv *node = (void *)object;
- struct nouveau_fb *pfb = nouveau_fb(object);
+ struct nvkm_fb *pfb = nvkm_fb(object);
pfb->ram->put(pfb, &node->mem);
- nouveau_instobj_destroy(&node->base);
+ nvkm_instobj_destroy(&node->base);
}
static int
-nv50_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
- struct nouveau_instobj_args *args = data;
+ struct nvkm_fb *pfb = nvkm_fb(parent);
+ struct nvkm_instobj_args *args = data;
struct nv50_instobj_priv *node;
int ret;
args->size = max((args->size + 4095) & ~4095, (u32)4096);
args->align = max((args->align + 4095) & ~4095, (u32)4096);
- ret = nouveau_instobj_create(parent, engine, oclass, &node);
+ ret = nvkm_instobj_create(parent, engine, oclass, &node);
*pobject = nv_object(node);
if (ret)
return ret;
@@ -117,13 +115,13 @@ nv50_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-static struct nouveau_instobj_impl
+static struct nvkm_instobj_impl
nv50_instobj_oclass = {
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_instobj_ctor,
.dtor = nv50_instobj_dtor,
- .init = _nouveau_instobj_init,
- .fini = _nouveau_instobj_fini,
+ .init = _nvkm_instobj_init,
+ .fini = _nvkm_instobj_fini,
.rd32 = nv50_instobj_rd32,
.wr32 = nv50_instobj_wr32,
},
@@ -134,22 +132,22 @@ nv50_instobj_oclass = {
*****************************************************************************/
static int
-nv50_instmem_fini(struct nouveau_object *object, bool suspend)
+nv50_instmem_fini(struct nvkm_object *object, bool suspend)
{
struct nv50_instmem_priv *priv = (void *)object;
priv->addr = ~0ULL;
- return nouveau_instmem_fini(&priv->base, suspend);
+ return nvkm_instmem_fini(&priv->base, suspend);
}
static int
-nv50_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_instmem_priv *priv;
int ret;
- ret = nouveau_instmem_create(parent, engine, oclass, &priv);
+ ret = nvkm_instmem_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -158,13 +156,13 @@ nv50_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
-nv50_instmem_oclass = &(struct nouveau_instmem_impl) {
+struct nvkm_oclass *
+nv50_instmem_oclass = &(struct nvkm_instmem_impl) {
.base.handle = NV_SUBDEV(INSTMEM, 0x50),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_instmem_ctor,
- .dtor = _nouveau_instmem_dtor,
- .init = _nouveau_instmem_init,
+ .dtor = _nvkm_instmem_dtor,
+ .init = _nvkm_instmem_init,
.fini = nv50_instmem_fini,
},
.instobj = &nv50_instobj_oclass.base,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h
index 8d67dedc5bb2..b10e292e5607 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h
@@ -1,56 +1,54 @@
#ifndef __NVKM_INSTMEM_PRIV_H__
#define __NVKM_INSTMEM_PRIV_H__
-
#include <subdev/instmem.h>
-struct nouveau_instobj_impl {
- struct nouveau_oclass base;
+struct nvkm_instobj_impl {
+ struct nvkm_oclass base;
};
-struct nouveau_instobj_args {
+struct nvkm_instobj_args {
u32 size;
u32 align;
};
-#define nouveau_instobj_create(p,e,o,d) \
- nouveau_instobj_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_instobj_destroy(p) ({ \
- struct nouveau_instobj *iobj = (p); \
- _nouveau_instobj_dtor(nv_object(iobj)); \
+#define nvkm_instobj_create(p,e,o,d) \
+ nvkm_instobj_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_instobj_destroy(p) ({ \
+ struct nvkm_instobj *iobj = (p); \
+ _nvkm_instobj_dtor(nv_object(iobj)); \
})
-#define nouveau_instobj_init(p) \
- nouveau_object_init(&(p)->base)
-#define nouveau_instobj_fini(p,s) \
- nouveau_object_fini(&(p)->base, (s))
+#define nvkm_instobj_init(p) \
+ nvkm_object_init(&(p)->base)
+#define nvkm_instobj_fini(p,s) \
+ nvkm_object_fini(&(p)->base, (s))
-int nouveau_instobj_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-void _nouveau_instobj_dtor(struct nouveau_object *);
-#define _nouveau_instobj_init nouveau_object_init
-#define _nouveau_instobj_fini nouveau_object_fini
+int nvkm_instobj_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+void _nvkm_instobj_dtor(struct nvkm_object *);
+#define _nvkm_instobj_init nvkm_object_init
+#define _nvkm_instobj_fini nvkm_object_fini
-struct nouveau_instmem_impl {
- struct nouveau_oclass base;
- struct nouveau_oclass *instobj;
+struct nvkm_instmem_impl {
+ struct nvkm_oclass base;
+ struct nvkm_oclass *instobj;
};
-#define nouveau_instmem_create(p,e,o,d) \
- nouveau_instmem_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_instmem_destroy(p) \
- nouveau_subdev_destroy(&(p)->base)
-#define nouveau_instmem_init(p) ({ \
- struct nouveau_instmem *imem = (p); \
- _nouveau_instmem_init(nv_object(imem)); \
+#define nvkm_instmem_create(p,e,o,d) \
+ nvkm_instmem_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_instmem_destroy(p) \
+ nvkm_subdev_destroy(&(p)->base)
+#define nvkm_instmem_init(p) ({ \
+ struct nvkm_instmem *imem = (p); \
+ _nvkm_instmem_init(nv_object(imem)); \
})
-#define nouveau_instmem_fini(p,s) ({ \
- struct nouveau_instmem *imem = (p); \
- _nouveau_instmem_fini(nv_object(imem), (s)); \
+#define nvkm_instmem_fini(p,s) ({ \
+ struct nvkm_instmem *imem = (p); \
+ _nvkm_instmem_fini(nv_object(imem), (s)); \
})
-int nouveau_instmem_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-#define _nouveau_instmem_dtor _nouveau_subdev_dtor
-int _nouveau_instmem_init(struct nouveau_object *);
-int _nouveau_instmem_fini(struct nouveau_object *, bool);
-
+int nvkm_instmem_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+#define _nvkm_instmem_dtor _nvkm_subdev_dtor
+int _nvkm_instmem_init(struct nvkm_object *);
+int _nvkm_instmem_fini(struct nvkm_object *, bool);
#endif
From 2799bba69a1caf54889035ed63247d09c4a2fc84 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:06:26 +1000
Subject: [PATCH 63/86] drm/nouveau/ltc: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 39 ++++++++--------
drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h | 4 +-
.../gpu/drm/nouveau/nvkm/subdev/ltc/base.c | 30 ++++++------
.../gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c | 40 ++++++++--------
.../gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c | 7 ++-
.../gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c | 19 ++++----
.../gpu/drm/nouveau/nvkm/subdev/ltc/priv.h | 46 +++++++++----------
7 files changed, 88 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
index 432717a421d3..f37fd1a50077 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
@@ -1,35 +1,32 @@
-#ifndef __NOUVEAU_LTC_H__
-#define __NOUVEAU_LTC_H__
-
+#ifndef __NVKM_LTC_H__
+#define __NVKM_LTC_H__
#include <core/subdev.h>
-#include <core/device.h>
+struct nvkm_mm_node;
-#define NOUVEAU_LTC_MAX_ZBC_CNT 16
+#define NVKM_LTC_MAX_ZBC_CNT 16
-struct nouveau_mm_node;
+struct nvkm_ltc {
+ struct nvkm_subdev base;
-struct nouveau_ltc {
- struct nouveau_subdev base;
-
- int (*tags_alloc)(struct nouveau_ltc *, u32 count,
- struct nouveau_mm_node **);
- void (*tags_free)(struct nouveau_ltc *, struct nouveau_mm_node **);
- void (*tags_clear)(struct nouveau_ltc *, u32 first, u32 count);
+ int (*tags_alloc)(struct nvkm_ltc *, u32 count,
+ struct nvkm_mm_node **);
+ void (*tags_free)(struct nvkm_ltc *, struct nvkm_mm_node **);
+ void (*tags_clear)(struct nvkm_ltc *, u32 first, u32 count);
int zbc_min;
int zbc_max;
- int (*zbc_color_get)(struct nouveau_ltc *, int index, const u32[4]);
- int (*zbc_depth_get)(struct nouveau_ltc *, int index, const u32);
+ int (*zbc_color_get)(struct nvkm_ltc *, int index, const u32[4]);
+ int (*zbc_depth_get)(struct nvkm_ltc *, int index, const u32);
};
-static inline struct nouveau_ltc *
-nouveau_ltc(void *obj)
+static inline struct nvkm_ltc *
+nvkm_ltc(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_LTC);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_LTC);
}
-extern struct nouveau_oclass *gf100_ltc_oclass;
-extern struct nouveau_oclass *gk104_ltc_oclass;
-extern struct nouveau_oclass *gm107_ltc_oclass;
+extern struct nvkm_oclass *gf100_ltc_oclass;
+extern struct nvkm_oclass *gk104_ltc_oclass;
+extern struct nvkm_oclass *gm107_ltc_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
index f2818a2b6d68..413def63be0e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
@@ -94,8 +94,8 @@ struct nvc0_gr_priv {
struct nvc0_gr_fuc fuc41ad;
bool firmware;
- struct nvc0_gr_zbc_color zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT];
- struct nvc0_gr_zbc_depth zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT];
+ struct nvc0_gr_zbc_color zbc_color[NVKM_LTC_MAX_ZBC_CNT];
+ struct nvc0_gr_zbc_depth zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
u8 rop_nr;
u8 gpc_nr;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c
index 7fa331516f84..2fb87fbfd11c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c
@@ -21,17 +21,15 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
#include "priv.h"
static int
-nvkm_ltc_tags_alloc(struct nouveau_ltc *ltc, u32 n,
- struct nouveau_mm_node **pnode)
+nvkm_ltc_tags_alloc(struct nvkm_ltc *ltc, u32 n, struct nvkm_mm_node **pnode)
{
struct nvkm_ltc_priv *priv = (void *)ltc;
int ret;
- ret = nouveau_mm_head(&priv->tags, 0, 1, n, n, 1, pnode);
+ ret = nvkm_mm_head(&priv->tags, 0, 1, n, n, 1, pnode);
if (ret)
*pnode = NULL;
@@ -39,14 +37,14 @@ nvkm_ltc_tags_alloc(struct nouveau_ltc *ltc, u32 n,
}
static void
-nvkm_ltc_tags_free(struct nouveau_ltc *ltc, struct nouveau_mm_node **pnode)
+nvkm_ltc_tags_free(struct nvkm_ltc *ltc, struct nvkm_mm_node **pnode)
{
struct nvkm_ltc_priv *priv = (void *)ltc;
- nouveau_mm_free(&priv->tags, pnode);
+ nvkm_mm_free(&priv->tags, pnode);
}
static void
-nvkm_ltc_tags_clear(struct nouveau_ltc *ltc, u32 first, u32 count)
+nvkm_ltc_tags_clear(struct nvkm_ltc *ltc, u32 first, u32 count)
{
const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
struct nvkm_ltc_priv *priv = (void *)ltc;
@@ -59,7 +57,7 @@ nvkm_ltc_tags_clear(struct nouveau_ltc *ltc, u32 first, u32 count)
}
static int
-nvkm_ltc_zbc_color_get(struct nouveau_ltc *ltc, int index, const u32 color[4])
+nvkm_ltc_zbc_color_get(struct nvkm_ltc *ltc, int index, const u32 color[4])
{
const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
struct nvkm_ltc_priv *priv = (void *)ltc;
@@ -69,7 +67,7 @@ nvkm_ltc_zbc_color_get(struct nouveau_ltc *ltc, int index, const u32 color[4])
}
static int
-nvkm_ltc_zbc_depth_get(struct nouveau_ltc *ltc, int index, const u32 depth)
+nvkm_ltc_zbc_depth_get(struct nvkm_ltc *ltc, int index, const u32 depth)
{
const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
struct nvkm_ltc_priv *priv = (void *)ltc;
@@ -79,13 +77,13 @@ nvkm_ltc_zbc_depth_get(struct nouveau_ltc *ltc, int index, const u32 depth)
}
int
-_nvkm_ltc_init(struct nouveau_object *object)
+_nvkm_ltc_init(struct nvkm_object *object)
{
const struct nvkm_ltc_impl *impl = (void *)nv_oclass(object);
struct nvkm_ltc_priv *priv = (void *)object;
int ret, i;
- ret = nouveau_subdev_init(&priv->base.base);
+ ret = nvkm_subdev_init(&priv->base.base);
if (ret)
return ret;
@@ -98,15 +96,15 @@ _nvkm_ltc_init(struct nouveau_object *object)
}
int
-nvkm_ltc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int length, void **pobject)
+nvkm_ltc_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
const struct nvkm_ltc_impl *impl = (void *)oclass;
struct nvkm_ltc_priv *priv;
int ret;
- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PLTCG",
- "l2c", length, pobject);
+ ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PLTCG",
+ "l2c", length, pobject);
priv = *pobject;
if (ret)
return ret;
@@ -119,7 +117,7 @@ nvkm_ltc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.tags_free = nvkm_ltc_tags_free;
priv->base.tags_clear = nvkm_ltc_tags_clear;
priv->base.zbc_min = 1; /* reserve 0 for disabled */
- priv->base.zbc_max = min(impl->zbc, NOUVEAU_LTC_MAX_ZBC_CNT) - 1;
+ priv->base.zbc_max = min(impl->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1;
priv->base.zbc_color_get = nvkm_ltc_zbc_color_get;
priv->base.zbc_depth_get = nvkm_ltc_zbc_depth_get;
return 0;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c
index 2db0977284f8..8e7cc6200d60 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c
@@ -21,12 +21,12 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
+#include <core/enum.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
-#include "priv.h"
-
void
gf100_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit)
{
@@ -62,7 +62,7 @@ gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth)
nv_wr32(priv, 0x17ea58, depth);
}
-static const struct nouveau_bitfield
+static const struct nvkm_bitfield
gf100_ltc_lts_intr_name[] = {
{ 0x00000001, "IDLE_ERROR_IQ" },
{ 0x00000002, "IDLE_ERROR_CBC" },
@@ -89,7 +89,7 @@ gf100_ltc_lts_intr(struct nvkm_ltc_priv *priv, int ltc, int lts)
if (stat) {
nv_info(priv, "LTC%d_LTS%d:", ltc, lts);
- nouveau_bitfield_print(gf100_ltc_lts_intr_name, stat);
+ nvkm_bitfield_print(gf100_ltc_lts_intr_name, stat);
pr_cont("\n");
}
@@ -97,7 +97,7 @@ gf100_ltc_lts_intr(struct nvkm_ltc_priv *priv, int ltc, int lts)
}
void
-gf100_ltc_intr(struct nouveau_subdev *subdev)
+gf100_ltc_intr(struct nvkm_subdev *subdev)
{
struct nvkm_ltc_priv *priv = (void *)subdev;
u32 mask;
@@ -112,7 +112,7 @@ gf100_ltc_intr(struct nouveau_subdev *subdev)
}
static int
-gf100_ltc_init(struct nouveau_object *object)
+gf100_ltc_init(struct nvkm_object *object)
{
struct nvkm_ltc_priv *priv = (void *)object;
u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
@@ -130,13 +130,13 @@ gf100_ltc_init(struct nouveau_object *object)
}
void
-gf100_ltc_dtor(struct nouveau_object *object)
+gf100_ltc_dtor(struct nvkm_object *object)
{
- struct nouveau_fb *pfb = nouveau_fb(object);
+ struct nvkm_fb *pfb = nvkm_fb(object);
struct nvkm_ltc_priv *priv = (void *)object;
- nouveau_mm_fini(&priv->tags);
- nouveau_mm_free(&pfb->vram, &priv->tag_ram);
+ nvkm_mm_fini(&priv->tags);
+ nvkm_mm_free(&pfb->vram, &priv->tag_ram);
nvkm_ltc_destroy(priv);
}
@@ -144,7 +144,7 @@ gf100_ltc_dtor(struct nouveau_object *object)
/* TODO: Figure out tag memory details and drop the over-cautious allocation.
*/
int
-gf100_ltc_init_tag_ram(struct nouveau_fb *pfb, struct nvkm_ltc_priv *priv)
+gf100_ltc_init_tag_ram(struct nvkm_fb *pfb, struct nvkm_ltc_priv *priv)
{
u32 tag_size, tag_margin, tag_align;
int ret;
@@ -170,8 +170,8 @@ gf100_ltc_init_tag_ram(struct nouveau_fb *pfb, struct nvkm_ltc_priv *priv)
tag_size += tag_align;
tag_size = (tag_size + 0xfff) >> 12; /* round up */
- ret = nouveau_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1,
- &priv->tag_ram);
+ ret = nvkm_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1,
+ &priv->tag_ram);
if (ret) {
priv->num_tags = 0;
} else {
@@ -183,16 +183,16 @@ gf100_ltc_init_tag_ram(struct nouveau_fb *pfb, struct nvkm_ltc_priv *priv)
priv->tag_base = tag_base;
}
- ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1);
+ ret = nvkm_mm_init(&priv->tags, 0, priv->num_tags, 1);
return ret;
}
int
-gf100_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
+ struct nvkm_fb *pfb = nvkm_fb(parent);
struct nvkm_ltc_priv *priv;
u32 parts, mask;
int ret, i;
@@ -218,10 +218,10 @@ gf100_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
gf100_ltc_oclass = &(struct nvkm_ltc_impl) {
.base.handle = NV_SUBDEV(LTC, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_ltc_ctor,
.dtor = gf100_ltc_dtor,
.init = gf100_ltc_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c
index b39b5d0eb8f9..d53959b5ec67 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c
@@ -21,11 +21,10 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
static int
-gk104_ltc_init(struct nouveau_object *object)
+gk104_ltc_init(struct nvkm_object *object)
{
struct nvkm_ltc_priv *priv = (void *)object;
u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
@@ -42,10 +41,10 @@ gk104_ltc_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
gk104_ltc_oclass = &(struct nvkm_ltc_impl) {
.base.handle = NV_SUBDEV(LTC, 0xe4),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_ltc_ctor,
.dtor = gf100_ltc_dtor,
.init = gk104_ltc_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c
index 89fc4238f50c..6b3f6f4ce107 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c
@@ -21,12 +21,11 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/fb.h>
#include <subdev/timer.h>
-#include "priv.h"
-
static void
gm107_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit)
{
@@ -75,7 +74,7 @@ gm107_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts)
}
static void
-gm107_ltc_intr(struct nouveau_subdev *subdev)
+gm107_ltc_intr(struct nvkm_subdev *subdev)
{
struct nvkm_ltc_priv *priv = (void *)subdev;
u32 mask;
@@ -90,7 +89,7 @@ gm107_ltc_intr(struct nouveau_subdev *subdev)
}
static int
-gm107_ltc_init(struct nouveau_object *object)
+gm107_ltc_init(struct nvkm_object *object)
{
struct nvkm_ltc_priv *priv = (void *)object;
u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
@@ -107,11 +106,11 @@ gm107_ltc_init(struct nouveau_object *object)
}
static int
-gm107_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fb *pfb = nouveau_fb(parent);
+ struct nvkm_fb *pfb = nvkm_fb(parent);
struct nvkm_ltc_priv *priv;
u32 parts, mask;
int ret, i;
@@ -136,10 +135,10 @@ gm107_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
gm107_ltc_oclass = &(struct nvkm_ltc_impl) {
.base.handle = NV_SUBDEV(LTC, 0xff),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm107_ltc_ctor,
.dtor = gf100_ltc_dtor,
.init = gm107_ltc_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h
index 41f179d93da6..09537d7b6783 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h
@@ -1,23 +1,22 @@
#ifndef __NVKM_LTC_PRIV_H__
#define __NVKM_LTC_PRIV_H__
-
#include <subdev/ltc.h>
-#include <subdev/fb.h>
-#include <core/enum.h>
+#include <core/mm.h>
+struct nvkm_fb;
struct nvkm_ltc_priv {
- struct nouveau_ltc base;
+ struct nvkm_ltc base;
u32 ltc_nr;
u32 lts_nr;
u32 num_tags;
u32 tag_base;
- struct nouveau_mm tags;
- struct nouveau_mm_node *tag_ram;
+ struct nvkm_mm tags;
+ struct nvkm_mm_node *tag_ram;
- u32 zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT][4];
- u32 zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT];
+ u32 zbc_color[NVKM_LTC_MAX_ZBC_CNT][4];
+ u32 zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
};
#define nvkm_ltc_create(p,e,o,d) \
@@ -35,24 +34,24 @@ struct nvkm_ltc_priv {
_nvkm_ltc_fini(nv_object(_priv), (s)); \
})
-int nvkm_ltc_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
+int nvkm_ltc_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
-#define _nvkm_ltc_dtor _nouveau_subdev_dtor
-int _nvkm_ltc_init(struct nouveau_object *);
-#define _nvkm_ltc_fini _nouveau_subdev_fini
+#define _nvkm_ltc_dtor _nvkm_subdev_dtor
+int _nvkm_ltc_init(struct nvkm_object *);
+#define _nvkm_ltc_fini _nvkm_subdev_fini
-int gf100_ltc_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void gf100_ltc_dtor(struct nouveau_object *);
-int gf100_ltc_init_tag_ram(struct nouveau_fb *, struct nvkm_ltc_priv *);
-int gf100_ltc_tags_alloc(struct nouveau_ltc *, u32, struct nouveau_mm_node **);
-void gf100_ltc_tags_free(struct nouveau_ltc *, struct nouveau_mm_node **);
+int gf100_ltc_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void gf100_ltc_dtor(struct nvkm_object *);
+int gf100_ltc_init_tag_ram(struct nvkm_fb *, struct nvkm_ltc_priv *);
+int gf100_ltc_tags_alloc(struct nvkm_ltc *, u32, struct nvkm_mm_node **);
+void gf100_ltc_tags_free(struct nvkm_ltc *, struct nvkm_mm_node **);
struct nvkm_ltc_impl {
- struct nouveau_oclass base;
- void (*intr)(struct nouveau_subdev *);
+ struct nvkm_oclass base;
+ void (*intr)(struct nvkm_subdev *);
void (*cbc_clear)(struct nvkm_ltc_priv *, u32 start, u32 limit);
void (*cbc_wait)(struct nvkm_ltc_priv *);
@@ -62,10 +61,9 @@ struct nvkm_ltc_impl {
void (*zbc_clear_depth)(struct nvkm_ltc_priv *, int, const u32);
};
-void gf100_ltc_intr(struct nouveau_subdev *);
+void gf100_ltc_intr(struct nvkm_subdev *);
void gf100_ltc_cbc_clear(struct nvkm_ltc_priv *, u32, u32);
void gf100_ltc_cbc_wait(struct nvkm_ltc_priv *);
void gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *, int, const u32[4]);
void gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *, int, const u32);
-
#endif
From d7e5fcd2e7455094d6f8326b00f70864a700017a Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:08:21 +1000
Subject: [PATCH 64/86] drm/nouveau/mc: namespace + nvidia gpu names (no binary
change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 1 +
.../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 -
.../gpu/drm/nouveau/include/nvkm/subdev/mc.h | 39 +++++------
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 20 +++---
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 ++---
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 10 +--
drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild | 8 +--
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c | 69 +++++++++----------
.../nouveau/nvkm/subdev/mc/{nv94.c => g94.c} | 11 ++-
.../nouveau/nvkm/subdev/mc/{nv98.c => g98.c} | 17 +++--
.../nvkm/subdev/mc/{nvc0.c => gf100.c} | 25 ++++---
.../nvkm/subdev/mc/{nvc3.c => gf106.c} | 15 ++--
.../gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c | 13 ++--
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c | 25 ++++---
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h | 24 +++----
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c | 13 ++--
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c | 15 ++--
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c | 11 ++-
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c | 23 ++++---
drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h | 42 ++++++-----
20 files changed, 192 insertions(+), 208 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/subdev/mc/{nv94.c => g94.c} (88%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/mc/{nv98.c => g98.c} (89%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/mc/{nvc0.c => gf100.c} (84%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/mc/{nvc3.c => gf106.c} (85%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 58f8d8bf2f8e..7894ff57514b 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -239,5 +239,6 @@
#define nouveau_fb_tile nvkm_fb_tile
#define nvc0_pte_storage_type_map gf100_pte_storage_type_map
#define nouveau_fuse nvkm_fuse
+#define nouveau_mc nvkm_mc
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
index f37fd1a50077..cd5d29fc0565 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
@@ -28,5 +28,4 @@ nvkm_ltc(void *obj)
extern struct nvkm_oclass *gf100_ltc_oclass;
extern struct nvkm_oclass *gk104_ltc_oclass;
extern struct nvkm_oclass *gm107_ltc_oclass;
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
index af7926f3a93d..055bea7702a1 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
@@ -1,31 +1,28 @@
-#ifndef __NOUVEAU_MC_H__
-#define __NOUVEAU_MC_H__
-
+#ifndef __NVKM_MC_H__
+#define __NVKM_MC_H__
#include <core/subdev.h>
-#include <core/device.h>
-struct nouveau_mc {
- struct nouveau_subdev base;
+struct nvkm_mc {
+ struct nvkm_subdev base;
bool use_msi;
unsigned int irq;
- void (*unk260)(struct nouveau_mc *, u32);
+ void (*unk260)(struct nvkm_mc *, u32);
};
-static inline struct nouveau_mc *
-nouveau_mc(void *obj)
+static inline struct nvkm_mc *
+nvkm_mc(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MC);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MC);
}
-extern struct nouveau_oclass *nv04_mc_oclass;
-extern struct nouveau_oclass *nv40_mc_oclass;
-extern struct nouveau_oclass *nv44_mc_oclass;
-extern struct nouveau_oclass *nv4c_mc_oclass;
-extern struct nouveau_oclass *nv50_mc_oclass;
-extern struct nouveau_oclass *nv94_mc_oclass;
-extern struct nouveau_oclass *nv98_mc_oclass;
-extern struct nouveau_oclass *nvc0_mc_oclass;
-extern struct nouveau_oclass *nvc3_mc_oclass;
-extern struct nouveau_oclass *gk20a_mc_oclass;
-
+extern struct nvkm_oclass *nv04_mc_oclass;
+extern struct nvkm_oclass *nv40_mc_oclass;
+extern struct nvkm_oclass *nv44_mc_oclass;
+extern struct nvkm_oclass *nv4c_mc_oclass;
+extern struct nvkm_oclass *nv50_mc_oclass;
+extern struct nvkm_oclass *g94_mc_oclass;
+extern struct nvkm_oclass *g98_mc_oclass;
+extern struct nvkm_oclass *gf100_mc_oclass;
+extern struct nvkm_oclass *gf106_mc_oclass;
+extern struct nvkm_oclass *gk20a_mc_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 579829a39e25..6183cc372d17 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -184,7 +184,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@@ -213,7 +213,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@@ -242,7 +242,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@@ -271,7 +271,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@@ -300,7 +300,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
@@ -329,7 +329,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
@@ -358,7 +358,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
@@ -389,7 +389,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
@@ -419,7 +419,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
@@ -449,7 +449,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index fbe552e825b8..2363a583fc3c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -69,7 +69,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@@ -102,7 +102,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@@ -135,7 +135,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@@ -167,7 +167,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@@ -200,7 +200,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@@ -232,7 +232,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@@ -264,7 +264,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@@ -297,7 +297,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@@ -329,7 +329,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index a9b5aa3d9ed1..9ade56294c38 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -69,7 +69,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@@ -103,7 +103,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@@ -137,7 +137,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@@ -193,7 +193,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@@ -227,7 +227,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
+ device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild
index 24b589b5001a..721643f04bb5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild
@@ -4,8 +4,8 @@ nvkm-y += nvkm/subdev/mc/nv40.o
nvkm-y += nvkm/subdev/mc/nv44.o
nvkm-y += nvkm/subdev/mc/nv4c.o
nvkm-y += nvkm/subdev/mc/nv50.o
-nvkm-y += nvkm/subdev/mc/nv94.o
-nvkm-y += nvkm/subdev/mc/nv98.o
-nvkm-y += nvkm/subdev/mc/nvc0.o
-nvkm-y += nvkm/subdev/mc/nvc3.o
+nvkm-y += nvkm/subdev/mc/g94.o
+nvkm-y += nvkm/subdev/mc/g98.o
+nvkm-y += nvkm/subdev/mc/gf100.o
+nvkm-y += nvkm/subdev/mc/gf106.o
nvkm-y += nvkm/subdev/mc/gk20a.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
index 25e3b9644a3f..5b051a26653e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
@@ -21,20 +21,21 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
+
+#include <core/device.h>
#include <core/option.h>
static inline void
-nouveau_mc_unk260(struct nouveau_mc *pmc, u32 data)
+nvkm_mc_unk260(struct nvkm_mc *pmc, u32 data)
{
- const struct nouveau_mc_oclass *impl = (void *)nv_oclass(pmc);
+ const struct nvkm_mc_oclass *impl = (void *)nv_oclass(pmc);
if (impl->unk260)
impl->unk260(pmc, data);
}
static inline u32
-nouveau_mc_intr_mask(struct nouveau_mc *pmc)
+nvkm_mc_intr_mask(struct nvkm_mc *pmc)
{
u32 intr = nv_rd32(pmc, 0x000100);
if (intr == 0xffffffff) /* likely fallen off the bus */
@@ -43,25 +44,25 @@ nouveau_mc_intr_mask(struct nouveau_mc *pmc)
}
static irqreturn_t
-nouveau_mc_intr(int irq, void *arg)
+nvkm_mc_intr(int irq, void *arg)
{
- struct nouveau_mc *pmc = arg;
- const struct nouveau_mc_oclass *oclass = (void *)nv_object(pmc)->oclass;
- const struct nouveau_mc_intr *map = oclass->intr;
- struct nouveau_subdev *unit;
+ struct nvkm_mc *pmc = arg;
+ const struct nvkm_mc_oclass *oclass = (void *)nv_object(pmc)->oclass;
+ const struct nvkm_mc_intr *map = oclass->intr;
+ struct nvkm_subdev *unit;
u32 intr;
nv_wr32(pmc, 0x000140, 0x00000000);
nv_rd32(pmc, 0x000140);
- intr = nouveau_mc_intr_mask(pmc);
+ intr = nvkm_mc_intr_mask(pmc);
if (pmc->use_msi)
oclass->msi_rearm(pmc);
if (intr) {
- u32 stat = intr = nouveau_mc_intr_mask(pmc);
+ u32 stat = intr = nvkm_mc_intr_mask(pmc);
while (map->stat) {
if (intr & map->stat) {
- unit = nouveau_subdev(pmc, map->unit);
+ unit = nvkm_subdev(pmc, map->unit);
if (unit && unit->intr)
unit->intr(unit);
stat &= ~map->stat;
@@ -78,18 +79,18 @@ nouveau_mc_intr(int irq, void *arg)
}
int
-_nouveau_mc_fini(struct nouveau_object *object, bool suspend)
+_nvkm_mc_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_mc *pmc = (void *)object;
+ struct nvkm_mc *pmc = (void *)object;
nv_wr32(pmc, 0x000140, 0x00000000);
- return nouveau_subdev_fini(&pmc->base, suspend);
+ return nvkm_subdev_fini(&pmc->base, suspend);
}
int
-_nouveau_mc_init(struct nouveau_object *object)
+_nvkm_mc_init(struct nvkm_object *object)
{
- struct nouveau_mc *pmc = (void *)object;
- int ret = nouveau_subdev_init(&pmc->base);
+ struct nvkm_mc *pmc = (void *)object;
+ int ret = nvkm_subdev_init(&pmc->base);
if (ret)
return ret;
nv_wr32(pmc, 0x000140, 0x00000001);
@@ -97,32 +98,32 @@ _nouveau_mc_init(struct nouveau_object *object)
}
void
-_nouveau_mc_dtor(struct nouveau_object *object)
+_nvkm_mc_dtor(struct nvkm_object *object)
{
- struct nouveau_device *device = nv_device(object);
- struct nouveau_mc *pmc = (void *)object;
+ struct nvkm_device *device = nv_device(object);
+ struct nvkm_mc *pmc = (void *)object;
free_irq(pmc->irq, pmc);
if (pmc->use_msi)
pci_disable_msi(device->pdev);
- nouveau_subdev_destroy(&pmc->base);
+ nvkm_subdev_destroy(&pmc->base);
}
int
-nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *bclass, int length, void **pobject)
+nvkm_mc_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *bclass, int length, void **pobject)
{
- const struct nouveau_mc_oclass *oclass = (void *)bclass;
- struct nouveau_device *device = nv_device(parent);
- struct nouveau_mc *pmc;
+ const struct nvkm_mc_oclass *oclass = (void *)bclass;
+ struct nvkm_device *device = nv_device(parent);
+ struct nvkm_mc *pmc;
int ret;
- ret = nouveau_subdev_create_(parent, engine, bclass, 0, "PMC",
- "master", length, pobject);
+ ret = nvkm_subdev_create_(parent, engine, bclass, 0, "PMC",
+ "master", length, pobject);
pmc = *pobject;
if (ret)
return ret;
- pmc->unk260 = nouveau_mc_unk260;
+ pmc->unk260 = nvkm_mc_unk260;
if (nv_device_is_pci(device)) {
switch (device->pdev->device & 0x0ff0) {
@@ -141,8 +142,8 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
}
}
- pmc->use_msi = nouveau_boolopt(device->cfgopt, "NvMSI",
- pmc->use_msi);
+ pmc->use_msi = nvkm_boolopt(device->cfgopt, "NvMSI",
+ pmc->use_msi);
if (pmc->use_msi && oclass->msi_rearm) {
pmc->use_msi = pci_enable_msi(device->pdev) == 0;
@@ -160,9 +161,7 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
pmc->irq = ret;
- ret = request_irq(pmc->irq, nouveau_mc_intr, IRQF_SHARED, "nouveau",
- pmc);
-
+ ret = request_irq(pmc->irq, nvkm_mc_intr, IRQF_SHARED, "nvkm", pmc);
if (ret < 0)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c
similarity index 88%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv94.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c
index 5f4541105e73..f042e7d8321d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv94.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c
@@ -21,17 +21,16 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
-struct nouveau_oclass *
-nv94_mc_oclass = &(struct nouveau_mc_oclass) {
+struct nvkm_oclass *
+g94_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x94),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
- .dtor = _nouveau_mc_dtor,
+ .dtor = _nvkm_mc_dtor,
.init = nv50_mc_init,
- .fini = _nouveau_mc_fini,
+ .fini = _nvkm_mc_fini,
},
.intr = nv50_mc_intr,
.msi_rearm = nv40_mc_msi_rearm,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c
similarity index 89%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c
index 49de0cf57359..8ab7f1272a14 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c
@@ -21,11 +21,10 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
-static const struct nouveau_mc_intr
-nv98_mc_intr[] = {
+static const struct nvkm_mc_intr
+g98_mc_intr[] = {
{ 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */
{ 0x00000001, NVDEV_ENGINE_MSPPP },
{ 0x00000100, NVDEV_ENGINE_FIFO },
@@ -45,15 +44,15 @@ nv98_mc_intr[] = {
{},
};
-struct nouveau_oclass *
-nv98_mc_oclass = &(struct nouveau_mc_oclass) {
+struct nvkm_oclass *
+g98_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x98),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
- .dtor = _nouveau_mc_dtor,
+ .dtor = _nvkm_mc_dtor,
.init = nv50_mc_init,
- .fini = _nouveau_mc_fini,
+ .fini = _nvkm_mc_fini,
},
- .intr = nv98_mc_intr,
+ .intr = g98_mc_intr,
.msi_rearm = nv40_mc_msi_rearm,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
similarity index 84%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
index a52687a883f0..2425984b045e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
@@ -21,11 +21,10 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
-const struct nouveau_mc_intr
-nvc0_mc_intr[] = {
+const struct nvkm_mc_intr
+gf100_mc_intr[] = {
{ 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */
{ 0x00000001, NVDEV_ENGINE_MSPPP },
{ 0x00000020, NVDEV_ENGINE_CE0 },
@@ -50,28 +49,28 @@ nvc0_mc_intr[] = {
};
static void
-nvc0_mc_msi_rearm(struct nouveau_mc *pmc)
+gf100_mc_msi_rearm(struct nvkm_mc *pmc)
{
struct nv04_mc_priv *priv = (void *)pmc;
nv_wr32(priv, 0x088704, 0x00000000);
}
void
-nvc0_mc_unk260(struct nouveau_mc *pmc, u32 data)
+gf100_mc_unk260(struct nvkm_mc *pmc, u32 data)
{
nv_wr32(pmc, 0x000260, data);
}
-struct nouveau_oclass *
-nvc0_mc_oclass = &(struct nouveau_mc_oclass) {
+struct nvkm_oclass *
+gf100_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
- .dtor = _nouveau_mc_dtor,
+ .dtor = _nvkm_mc_dtor,
.init = nv50_mc_init,
- .fini = _nouveau_mc_fini,
+ .fini = _nvkm_mc_fini,
},
- .intr = nvc0_mc_intr,
- .msi_rearm = nvc0_mc_msi_rearm,
- .unk260 = nvc0_mc_unk260,
+ .intr = gf100_mc_intr,
+ .msi_rearm = gf100_mc_msi_rearm,
+ .unk260 = gf100_mc_unk260,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c
similarity index 85%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c
index 68b5f61aadb5..8d2a8f457778 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c
@@ -21,19 +21,18 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
-struct nouveau_oclass *
-nvc3_mc_oclass = &(struct nouveau_mc_oclass) {
+struct nvkm_oclass *
+gf106_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0xc3),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
- .dtor = _nouveau_mc_dtor,
+ .dtor = _nvkm_mc_dtor,
.init = nv50_mc_init,
- .fini = _nouveau_mc_fini,
+ .fini = _nvkm_mc_fini,
},
- .intr = nvc0_mc_intr,
+ .intr = gf100_mc_intr,
.msi_rearm = nv40_mc_msi_rearm,
- .unk260 = nvc0_mc_unk260,
+ .unk260 = gf100_mc_unk260,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c
index b8d6cb435d0a..43b27742956d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c
@@ -21,18 +21,17 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
-struct nouveau_oclass *
-gk20a_mc_oclass = &(struct nouveau_mc_oclass) {
+struct nvkm_oclass *
+gk20a_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0xea),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
- .dtor = _nouveau_mc_dtor,
+ .dtor = _nvkm_mc_dtor,
.init = nv50_mc_init,
- .fini = _nouveau_mc_fini,
+ .fini = _nvkm_mc_fini,
},
- .intr = nvc0_mc_intr,
+ .intr = gf100_mc_intr,
.msi_rearm = nv40_mc_msi_rearm,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
index 2d787e4dfefa..32713827b4dc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
@@ -21,10 +21,9 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
-const struct nouveau_mc_intr
+const struct nvkm_mc_intr
nv04_mc_intr[] = {
{ 0x00000001, NVDEV_ENGINE_MPEG }, /* NV17- MPEG/ME */
{ 0x00000100, NVDEV_ENGINE_FIFO },
@@ -40,25 +39,25 @@ nv04_mc_intr[] = {
};
int
-nv04_mc_init(struct nouveau_object *object)
+nv04_mc_init(struct nvkm_object *object)
{
struct nv04_mc_priv *priv = (void *)object;
nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */
nv_wr32(priv, 0x001850, 0x00000001); /* disable rom access */
- return nouveau_mc_init(&priv->base);
+ return nvkm_mc_init(&priv->base);
}
int
-nv04_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_mc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_mc_priv *priv;
int ret;
- ret = nouveau_mc_create(parent, engine, oclass, &priv);
+ ret = nvkm_mc_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -66,14 +65,14 @@ nv04_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
-nv04_mc_oclass = &(struct nouveau_mc_oclass) {
+struct nvkm_oclass *
+nv04_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x04),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
- .dtor = _nouveau_mc_dtor,
+ .dtor = _nvkm_mc_dtor,
.init = nv04_mc_init,
- .fini = _nouveau_mc_fini,
+ .fini = _nvkm_mc_fini,
},
.intr = nv04_mc_intr,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h
index 4d9ea46c47c2..411de3d08ab6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h
@@ -1,22 +1,20 @@
#ifndef __NVKM_MC_NV04_H__
#define __NVKM_MC_NV04_H__
-
#include "priv.h"
struct nv04_mc_priv {
- struct nouveau_mc base;
+ struct nvkm_mc base;
};
-int nv04_mc_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-
-extern const struct nouveau_mc_intr nv04_mc_intr[];
-int nv04_mc_init(struct nouveau_object *);
-void nv40_mc_msi_rearm(struct nouveau_mc *);
-int nv44_mc_init(struct nouveau_object *object);
-int nv50_mc_init(struct nouveau_object *);
-extern const struct nouveau_mc_intr nv50_mc_intr[];
-extern const struct nouveau_mc_intr nvc0_mc_intr[];
+int nv04_mc_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+extern const struct nvkm_mc_intr nv04_mc_intr[];
+int nv04_mc_init(struct nvkm_object *);
+void nv40_mc_msi_rearm(struct nvkm_mc *);
+int nv44_mc_init(struct nvkm_object *object);
+int nv50_mc_init(struct nvkm_object *);
+extern const struct nvkm_mc_intr nv50_mc_intr[];
+extern const struct nvkm_mc_intr gf100_mc_intr[];
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c
index 5b1faecfed2d..b7613059da08 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c
@@ -21,24 +21,23 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
void
-nv40_mc_msi_rearm(struct nouveau_mc *pmc)
+nv40_mc_msi_rearm(struct nvkm_mc *pmc)
{
struct nv04_mc_priv *priv = (void *)pmc;
nv_wr08(priv, 0x088068, 0xff);
}
-struct nouveau_oclass *
-nv40_mc_oclass = &(struct nouveau_mc_oclass) {
+struct nvkm_oclass *
+nv40_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x40),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
- .dtor = _nouveau_mc_dtor,
+ .dtor = _nvkm_mc_dtor,
.init = nv04_mc_init,
- .fini = _nouveau_mc_fini,
+ .fini = _nvkm_mc_fini,
},
.intr = nv04_mc_intr,
.msi_rearm = nv40_mc_msi_rearm,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c
index cc4d0d2d886e..2c7f7c701a2b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c
@@ -21,11 +21,10 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
int
-nv44_mc_init(struct nouveau_object *object)
+nv44_mc_init(struct nvkm_object *object)
{
struct nv04_mc_priv *priv = (void *)object;
u32 tmp = nv_rd32(priv, 0x10020c);
@@ -37,17 +36,17 @@ nv44_mc_init(struct nouveau_object *object)
nv_wr32(priv, 0x001708, 0);
nv_wr32(priv, 0x00170c, tmp);
- return nouveau_mc_init(&priv->base);
+ return nvkm_mc_init(&priv->base);
}
-struct nouveau_oclass *
-nv44_mc_oclass = &(struct nouveau_mc_oclass) {
+struct nvkm_oclass *
+nv44_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x44),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
- .dtor = _nouveau_mc_dtor,
+ .dtor = _nvkm_mc_dtor,
.init = nv44_mc_init,
- .fini = _nouveau_mc_fini,
+ .fini = _nvkm_mc_fini,
},
.intr = nv04_mc_intr,
.msi_rearm = nv40_mc_msi_rearm,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c
index 165401c4045c..c0aac7e20d45 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c
@@ -21,17 +21,16 @@
*
* Authors: Ilia Mirkin
*/
-
#include "nv04.h"
-struct nouveau_oclass *
-nv4c_mc_oclass = &(struct nouveau_mc_oclass) {
+struct nvkm_oclass *
+nv4c_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x4c),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
- .dtor = _nouveau_mc_dtor,
+ .dtor = _nvkm_mc_dtor,
.init = nv44_mc_init,
- .fini = _nouveau_mc_fini,
+ .fini = _nvkm_mc_fini,
},
.intr = nv04_mc_intr,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
index 9100f2875636..40e3019e1fde 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
@@ -21,10 +21,11 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
-const struct nouveau_mc_intr
+#include <core/device.h>
+
+const struct nvkm_mc_intr
nv50_mc_intr[] = {
{ 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */
{ 0x00000001, NVDEV_ENGINE_MPEG },
@@ -43,28 +44,28 @@ nv50_mc_intr[] = {
};
static void
-nv50_mc_msi_rearm(struct nouveau_mc *pmc)
+nv50_mc_msi_rearm(struct nvkm_mc *pmc)
{
- struct nouveau_device *device = nv_device(pmc);
+ struct nvkm_device *device = nv_device(pmc);
pci_write_config_byte(device->pdev, 0x68, 0xff);
}
int
-nv50_mc_init(struct nouveau_object *object)
+nv50_mc_init(struct nvkm_object *object)
{
struct nv04_mc_priv *priv = (void *)object;
nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */
- return nouveau_mc_init(&priv->base);
+ return nvkm_mc_init(&priv->base);
}
-struct nouveau_oclass *
-nv50_mc_oclass = &(struct nouveau_mc_oclass) {
+struct nvkm_oclass *
+nv50_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x50),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
- .dtor = _nouveau_mc_dtor,
+ .dtor = _nvkm_mc_dtor,
.init = nv50_mc_init,
- .fini = _nouveau_mc_fini,
+ .fini = _nvkm_mc_fini,
},
.intr = nv50_mc_intr,
.msi_rearm = nv50_mc_msi_rearm,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h
index 911e66392587..d2cad07afd1a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h
@@ -1,38 +1,36 @@
#ifndef __NVKM_MC_PRIV_H__
#define __NVKM_MC_PRIV_H__
-
#include <subdev/mc.h>
-#define nouveau_mc_create(p,e,o,d) \
- nouveau_mc_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_mc_destroy(p) ({ \
- struct nouveau_mc *pmc = (p); _nouveau_mc_dtor(nv_object(pmc)); \
+#define nvkm_mc_create(p,e,o,d) \
+ nvkm_mc_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_mc_destroy(p) ({ \
+ struct nvkm_mc *pmc = (p); _nvkm_mc_dtor(nv_object(pmc)); \
})
-#define nouveau_mc_init(p) ({ \
- struct nouveau_mc *pmc = (p); _nouveau_mc_init(nv_object(pmc)); \
+#define nvkm_mc_init(p) ({ \
+ struct nvkm_mc *pmc = (p); _nvkm_mc_init(nv_object(pmc)); \
})
-#define nouveau_mc_fini(p,s) ({ \
- struct nouveau_mc *pmc = (p); _nouveau_mc_fini(nv_object(pmc), (s)); \
+#define nvkm_mc_fini(p,s) ({ \
+ struct nvkm_mc *pmc = (p); _nvkm_mc_fini(nv_object(pmc), (s)); \
})
-int nouveau_mc_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-void _nouveau_mc_dtor(struct nouveau_object *);
-int _nouveau_mc_init(struct nouveau_object *);
-int _nouveau_mc_fini(struct nouveau_object *, bool);
+int nvkm_mc_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+void _nvkm_mc_dtor(struct nvkm_object *);
+int _nvkm_mc_init(struct nvkm_object *);
+int _nvkm_mc_fini(struct nvkm_object *, bool);
-struct nouveau_mc_intr {
+struct nvkm_mc_intr {
u32 stat;
u32 unit;
};
-struct nouveau_mc_oclass {
- struct nouveau_oclass base;
- const struct nouveau_mc_intr *intr;
- void (*msi_rearm)(struct nouveau_mc *);
- void (*unk260)(struct nouveau_mc *, u32);
+struct nvkm_mc_oclass {
+ struct nvkm_oclass base;
+ const struct nvkm_mc_intr *intr;
+ void (*msi_rearm)(struct nvkm_mc *);
+ void (*unk260)(struct nvkm_mc *, u32);
};
-void nvc0_mc_unk260(struct nouveau_mc *, u32);
-
+void gf100_mc_unk260(struct nvkm_mc *, u32);
#endif
From 42594600095f03244a674fecdd2b5f6da2441180 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:09:19 +1000
Subject: [PATCH 65/86] drm/nouveau/mmu: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 1 +
.../gpu/drm/nouveau/include/nvkm/engine/ce.h | 1 +
.../gpu/drm/nouveau/include/nvkm/subdev/mmu.h | 153 +++++++---------
drivers/gpu/drm/nouveau/nvkm/core/engctx.c | 1 +
drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c | 1 +
drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c | 1 +
.../drm/nouveau/nvkm/engine/device/gm100.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 16 +-
.../gpu/drm/nouveau/nvkm/engine/dmaobj/base.c | 1 +
.../gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 1 +
.../gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c | 1 +
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 1 +
drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/bar/gf100.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/fb/gf100.c | 2 +
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c | 2 +
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c | 2 +
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c | 2 +
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/mmu/base.c | 169 +++++++++---------
.../nvkm/subdev/mmu/{nvc0.c => gf100.c} | 92 +++++-----
.../gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c | 58 +++---
.../gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h | 6 +-
.../gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c | 56 +++---
.../gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c | 60 +++----
.../gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 64 ++++---
29 files changed, 348 insertions(+), 371 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/subdev/mmu/{nvc0.c => gf100.c} (75%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 7894ff57514b..423086564735 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -240,5 +240,6 @@
#define nvc0_pte_storage_type_map gf100_pte_storage_type_map
#define nouveau_fuse nvkm_fuse
#define nouveau_mc nvkm_mc
+#define nouveau_mmu nvkm_mmu
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
index 639d0fd64cad..92cfcf5ae9d4 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
@@ -1,5 +1,6 @@
#ifndef __NVKM_CE_H__
#define __NVKM_CE_H__
+#include <core/engine.h>
void nva3_ce_intr(struct nouveau_subdev *);
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
index 2c3b29967ea4..3a5368776c31 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
@@ -1,72 +1,44 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifndef __NOUVEAU_MMU_H__
-#define __NOUVEAU_MMU_H__
-
-#include <core/object.h>
+#ifndef __NVKM_MMU_H__
+#define __NVKM_MMU_H__
#include <core/subdev.h>
-#include <core/device.h>
#include <core/mm.h>
+struct nvkm_device;
+struct nvkm_mem;
-struct nouveau_vm_pgt {
- struct nouveau_gpuobj *obj[2];
+struct nvkm_vm_pgt {
+ struct nvkm_gpuobj *obj[2];
u32 refcount[2];
};
-struct nouveau_vm_pgd {
+struct nvkm_vm_pgd {
struct list_head head;
- struct nouveau_gpuobj *obj;
+ struct nvkm_gpuobj *obj;
};
-struct nouveau_gpuobj;
-struct nouveau_mem;
-
-struct nouveau_vma {
+struct nvkm_vma {
struct list_head head;
int refcount;
- struct nouveau_vm *vm;
- struct nouveau_mm_node *node;
+ struct nvkm_vm *vm;
+ struct nvkm_mm_node *node;
u64 offset;
u32 access;
};
-struct nouveau_vm {
- struct nouveau_mmu *mmu;
- struct nouveau_mm mm;
+struct nvkm_vm {
+ struct nvkm_mmu *mmu;
+ struct nvkm_mm mm;
struct kref refcount;
struct list_head pgd_list;
atomic_t engref[NVDEV_SUBDEV_NR];
- struct nouveau_vm_pgt *pgt;
+ struct nvkm_vm_pgt *pgt;
u32 fpde;
u32 lpde;
};
-struct nouveau_mmu {
- struct nouveau_subdev base;
+struct nvkm_mmu {
+ struct nvkm_subdev base;
u64 limit;
u8 dma_bits;
@@ -74,62 +46,59 @@ struct nouveau_mmu {
u8 spg_shift;
u8 lpg_shift;
- int (*create)(struct nouveau_mmu *, u64 offset, u64 length,
- u64 mm_offset, struct nouveau_vm **);
+ int (*create)(struct nvkm_mmu *, u64 offset, u64 length,
+ u64 mm_offset, struct nvkm_vm **);
- void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde,
- struct nouveau_gpuobj *pgt[2]);
- void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *,
- struct nouveau_mem *, u32 pte, u32 cnt,
+ void (*map_pgt)(struct nvkm_gpuobj *pgd, u32 pde,
+ struct nvkm_gpuobj *pgt[2]);
+ void (*map)(struct nvkm_vma *, struct nvkm_gpuobj *,
+ struct nvkm_mem *, u32 pte, u32 cnt,
u64 phys, u64 delta);
- void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *,
- struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *);
- void (*unmap)(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt);
- void (*flush)(struct nouveau_vm *);
+ void (*map_sg)(struct nvkm_vma *, struct nvkm_gpuobj *,
+ struct nvkm_mem *, u32 pte, u32 cnt, dma_addr_t *);
+ void (*unmap)(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt);
+ void (*flush)(struct nvkm_vm *);
};
-static inline struct nouveau_mmu *
-nouveau_mmu(void *obj)
+static inline struct nvkm_mmu *
+nvkm_mmu(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MMU);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MMU);
}
-#define nouveau_mmu_create(p,e,o,i,f,d) \
- nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d))
-#define nouveau_mmu_destroy(p) \
- nouveau_subdev_destroy(&(p)->base)
-#define nouveau_mmu_init(p) \
- nouveau_subdev_init(&(p)->base)
-#define nouveau_mmu_fini(p,s) \
- nouveau_subdev_fini(&(p)->base, (s))
+#define nvkm_mmu_create(p,e,o,i,f,d) \
+ nvkm_subdev_create((p), (e), (o), 0, (i), (f), (d))
+#define nvkm_mmu_destroy(p) \
+ nvkm_subdev_destroy(&(p)->base)
+#define nvkm_mmu_init(p) \
+ nvkm_subdev_init(&(p)->base)
+#define nvkm_mmu_fini(p,s) \
+ nvkm_subdev_fini(&(p)->base, (s))
-#define _nouveau_mmu_dtor _nouveau_subdev_dtor
-#define _nouveau_mmu_init _nouveau_subdev_init
-#define _nouveau_mmu_fini _nouveau_subdev_fini
+#define _nvkm_mmu_dtor _nvkm_subdev_dtor
+#define _nvkm_mmu_init _nvkm_subdev_init
+#define _nvkm_mmu_fini _nvkm_subdev_fini
-extern struct nouveau_oclass nv04_mmu_oclass;
-extern struct nouveau_oclass nv41_mmu_oclass;
-extern struct nouveau_oclass nv44_mmu_oclass;
-extern struct nouveau_oclass nv50_mmu_oclass;
-extern struct nouveau_oclass nvc0_mmu_oclass;
+extern struct nvkm_oclass nv04_mmu_oclass;
+extern struct nvkm_oclass nv41_mmu_oclass;
+extern struct nvkm_oclass nv44_mmu_oclass;
+extern struct nvkm_oclass nv50_mmu_oclass;
+extern struct nvkm_oclass gf100_mmu_oclass;
-int nv04_vm_create(struct nouveau_mmu *, u64, u64, u64,
- struct nouveau_vm **);
-void nv04_mmu_dtor(struct nouveau_object *);
-
-/* nouveau_vm.c */
-int nouveau_vm_create(struct nouveau_mmu *, u64 offset, u64 length,
- u64 mm_offset, u32 block, struct nouveau_vm **);
-int nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length,
- u64 mm_offset, struct nouveau_vm **);
-int nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **,
- struct nouveau_gpuobj *pgd);
-int nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift,
- u32 access, struct nouveau_vma *);
-void nouveau_vm_put(struct nouveau_vma *);
-void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *);
-void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *);
-void nouveau_vm_unmap(struct nouveau_vma *);
-void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length);
+int nv04_vm_create(struct nvkm_mmu *, u64, u64, u64,
+ struct nvkm_vm **);
+void nv04_mmu_dtor(struct nvkm_object *);
+int nvkm_vm_create(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset,
+ u32 block, struct nvkm_vm **);
+int nvkm_vm_new(struct nvkm_device *, u64 offset, u64 length, u64 mm_offset,
+ struct nvkm_vm **);
+int nvkm_vm_ref(struct nvkm_vm *, struct nvkm_vm **, struct nvkm_gpuobj *pgd);
+int nvkm_vm_get(struct nvkm_vm *, u64 size, u32 page_shift, u32 access,
+ struct nvkm_vma *);
+void nvkm_vm_put(struct nvkm_vma *);
+void nvkm_vm_map(struct nvkm_vma *, struct nvkm_mem *);
+void nvkm_vm_map_at(struct nvkm_vma *, u64 offset, struct nvkm_mem *);
+void nvkm_vm_unmap(struct nvkm_vma *);
+void nvkm_vm_unmap_at(struct nvkm_vma *, u64 offset, u64 length);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
index a9df07a90f9b..fb2acbca75d9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
@@ -22,6 +22,7 @@
* Authors: Ben Skeggs
*/
#include <core/engctx.h>
+#include <core/engine.h>
#include <core/client.h>
static inline int
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
index 0c5cb55fc617..2eba801aae6f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
@@ -22,6 +22,7 @@
* Authors: Ben Skeggs
*/
#include <core/gpuobj.h>
+#include <core/engine.h>
#include <subdev/instmem.h>
#include <subdev/bar.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c
index b193b5f4037a..b14617ac5abe 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c
@@ -30,6 +30,7 @@
#include <subdev/mmu.h>
#include <core/client.h>
+#include <core/device.h>
#include <core/enum.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 165271cf9959..adf9c27a88b6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -76,7 +76,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
@@ -120,7 +120,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
#if 0
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 2363a583fc3c..6cd796c33ba0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -76,7 +76,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -109,7 +109,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -142,7 +142,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -174,7 +174,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -207,7 +207,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -239,7 +239,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -271,7 +271,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -304,7 +304,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -336,7 +336,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 9ade56294c38..64aee47dee89 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -76,7 +76,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -110,7 +110,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -144,7 +144,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -172,7 +172,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
@@ -200,7 +200,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -234,7 +234,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -268,7 +268,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -301,7 +301,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
- device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
+ device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c
index e1500f77a56a..741f4a7cc0b1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c
@@ -24,6 +24,7 @@
#include <core/object.h>
#include <core/client.h>
+#include <core/device.h>
#include <nvif/unpack.h>
#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
index 604cb5286632..be0293476279 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
@@ -23,6 +23,7 @@
*/
#include <core/client.h>
+#include <core/device.h>
#include <nvif/unpack.h>
#include <nvif/class.h>
#include <core/engctx.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
index 8b7d879a7fa1..2798d26a8ca3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
@@ -20,6 +20,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include <core/device.h>
#include <core/gpuobj.h>
#define CP_FLAG_CLEAR 0
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
index 9cc5c25f571b..6b3341f9a3f4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
@@ -23,6 +23,7 @@
*/
#include <core/client.h>
+#include <core/device.h>
#include <core/os.h>
#include <core/handle.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
index 3995d2cf0668..cea90df533d9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
@@ -20,6 +20,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <engine/xtensa.h>
+#include <core/device.h>
#include <core/engctx.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
index 4c6d238dd3da..12a1aebd9a96 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
@@ -23,6 +23,7 @@
*/
#include "priv.h"
+#include <core/device.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
index 5a6c2b7a6ef1..d51aa0237baf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
@@ -23,6 +23,8 @@
*/
#include "gf100.h"
+#include <core/device.h>
+
extern const u8 gf100_pte_storage_type_map[256];
bool
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
index 6c0b82f35d94..09ebb9477e00 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
@@ -25,6 +25,8 @@
*/
#include "nv04.h"
+#include <core/device.h>
+
void
nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
u32 flags, struct nvkm_fb_tile *tile)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
index 48fd5a5bcd3c..0480ce52aa06 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
@@ -24,6 +24,7 @@
#include "nv50.h"
#include <core/client.h>
+#include <core/device.h>
#include <core/engctx.h>
#include <core/enum.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c
index 6cf526b4a12f..5f30db140b47 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c
@@ -21,6 +21,8 @@
*/
#include "priv.h"
+#include <core/device.h>
+
struct gk20a_mem {
struct nvkm_mem base;
void *cpuaddr;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
index 8bb7e432ad04..fbae05db4ffd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
@@ -23,6 +23,8 @@
*/
#include "priv.h"
+#include <core/device.h>
+
static int
nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
index 14f5ba5eefde..d2c81dd635dc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
@@ -24,6 +24,7 @@
#include "nv50.h"
#include "ramseq.h"
+#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/perf.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
index 729e27f2cbd4..012c9db687b2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
@@ -3,4 +3,4 @@ nvkm-y += nvkm/subdev/mmu/nv04.o
nvkm-y += nvkm/subdev/mmu/nv41.o
nvkm-y += nvkm/subdev/mmu/nv44.o
nvkm-y += nvkm/subdev/mmu/nv50.o
-nvkm-y += nvkm/subdev/mmu/nvc0.o
+nvkm-y += nvkm/subdev/mmu/gf100.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
index e3cb186c440b..277b6ec04e24 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
@@ -21,19 +21,17 @@
*
* Authors: Ben Skeggs
*/
+#include <subdev/mmu.h>
+#include <subdev/fb.h>
#include <core/gpuobj.h>
-#include <core/mm.h>
-
-#include <subdev/fb.h>
-#include <subdev/mmu.h>
void
-nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
+nvkm_vm_map_at(struct nvkm_vma *vma, u64 delta, struct nvkm_mem *node)
{
- struct nouveau_vm *vm = vma->vm;
- struct nouveau_mmu *mmu = vm->mmu;
- struct nouveau_mm_node *r;
+ struct nvkm_vm *vm = vma->vm;
+ struct nvkm_mmu *mmu = vm->mmu;
+ struct nvkm_mm_node *r;
int big = vma->node->type != mmu->spg_shift;
u32 offset = vma->node->offset + (delta >> 12);
u32 bits = vma->node->type - 12;
@@ -48,7 +46,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
u32 num = r->length >> bits;
while (num) {
- struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big];
+ struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big];
end = (pte + num);
if (unlikely(end >= max))
@@ -73,11 +71,11 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
}
static void
-nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
- struct nouveau_mem *mem)
+nvkm_vm_map_sg_table(struct nvkm_vma *vma, u64 delta, u64 length,
+ struct nvkm_mem *mem)
{
- struct nouveau_vm *vm = vma->vm;
- struct nouveau_mmu *mmu = vm->mmu;
+ struct nvkm_vm *vm = vma->vm;
+ struct nvkm_mmu *mmu = vm->mmu;
int big = vma->node->type != mmu->spg_shift;
u32 offset = vma->node->offset + (delta >> 12);
u32 bits = vma->node->type - 12;
@@ -91,7 +89,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
struct scatterlist *sg;
for_each_sg(mem->sg->sgl, sg, mem->sg->nents, i) {
- struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big];
+ struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big];
sglen = sg_dma_len(sg) >> PAGE_SHIFT;
end = pte + sglen;
@@ -131,11 +129,11 @@ finish:
}
static void
-nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
- struct nouveau_mem *mem)
+nvkm_vm_map_sg(struct nvkm_vma *vma, u64 delta, u64 length,
+ struct nvkm_mem *mem)
{
- struct nouveau_vm *vm = vma->vm;
- struct nouveau_mmu *mmu = vm->mmu;
+ struct nvkm_vm *vm = vma->vm;
+ struct nvkm_mmu *mmu = vm->mmu;
dma_addr_t *list = mem->pages;
int big = vma->node->type != mmu->spg_shift;
u32 offset = vma->node->offset + (delta >> 12);
@@ -147,7 +145,7 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
u32 end, len;
while (num) {
- struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big];
+ struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big];
end = (pte + num);
if (unlikely(end >= max))
@@ -169,22 +167,22 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
}
void
-nouveau_vm_map(struct nouveau_vma *vma, struct nouveau_mem *node)
+nvkm_vm_map(struct nvkm_vma *vma, struct nvkm_mem *node)
{
if (node->sg)
- nouveau_vm_map_sg_table(vma, 0, node->size << 12, node);
+ nvkm_vm_map_sg_table(vma, 0, node->size << 12, node);
else
if (node->pages)
- nouveau_vm_map_sg(vma, 0, node->size << 12, node);
+ nvkm_vm_map_sg(vma, 0, node->size << 12, node);
else
- nouveau_vm_map_at(vma, 0, node);
+ nvkm_vm_map_at(vma, 0, node);
}
void
-nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
+nvkm_vm_unmap_at(struct nvkm_vma *vma, u64 delta, u64 length)
{
- struct nouveau_vm *vm = vma->vm;
- struct nouveau_mmu *mmu = vm->mmu;
+ struct nvkm_vm *vm = vma->vm;
+ struct nvkm_mmu *mmu = vm->mmu;
int big = vma->node->type != mmu->spg_shift;
u32 offset = vma->node->offset + (delta >> 12);
u32 bits = vma->node->type - 12;
@@ -195,7 +193,7 @@ nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
u32 end, len;
while (num) {
- struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big];
+ struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big];
end = (pte + num);
if (unlikely(end >= max))
@@ -216,18 +214,18 @@ nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
}
void
-nouveau_vm_unmap(struct nouveau_vma *vma)
+nvkm_vm_unmap(struct nvkm_vma *vma)
{
- nouveau_vm_unmap_at(vma, 0, (u64)vma->node->length << 12);
+ nvkm_vm_unmap_at(vma, 0, (u64)vma->node->length << 12);
}
static void
-nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde)
+nvkm_vm_unmap_pgt(struct nvkm_vm *vm, int big, u32 fpde, u32 lpde)
{
- struct nouveau_mmu *mmu = vm->mmu;
- struct nouveau_vm_pgd *vpgd;
- struct nouveau_vm_pgt *vpgt;
- struct nouveau_gpuobj *pgt;
+ struct nvkm_mmu *mmu = vm->mmu;
+ struct nvkm_vm_pgd *vpgd;
+ struct nvkm_vm_pgt *vpgt;
+ struct nvkm_gpuobj *pgt;
u32 pde;
for (pde = fpde; pde <= lpde; pde++) {
@@ -243,18 +241,18 @@ nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde)
}
mutex_unlock(&nv_subdev(mmu)->mutex);
- nouveau_gpuobj_ref(NULL, &pgt);
+ nvkm_gpuobj_ref(NULL, &pgt);
mutex_lock(&nv_subdev(mmu)->mutex);
}
}
static int
-nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
+nvkm_vm_map_pgt(struct nvkm_vm *vm, u32 pde, u32 type)
{
- struct nouveau_mmu *mmu = vm->mmu;
- struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
- struct nouveau_vm_pgd *vpgd;
- struct nouveau_gpuobj *pgt;
+ struct nvkm_mmu *mmu = vm->mmu;
+ struct nvkm_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
+ struct nvkm_vm_pgd *vpgd;
+ struct nvkm_gpuobj *pgt;
int big = (type != mmu->spg_shift);
u32 pgt_size;
int ret;
@@ -263,8 +261,8 @@ nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
pgt_size *= 8;
mutex_unlock(&nv_subdev(mmu)->mutex);
- ret = nouveau_gpuobj_new(nv_object(vm->mmu), NULL, pgt_size, 0x1000,
- NVOBJ_FLAG_ZERO_ALLOC, &pgt);
+ ret = nvkm_gpuobj_new(nv_object(vm->mmu), NULL, pgt_size, 0x1000,
+ NVOBJ_FLAG_ZERO_ALLOC, &pgt);
mutex_lock(&nv_subdev(mmu)->mutex);
if (unlikely(ret))
return ret;
@@ -272,7 +270,7 @@ nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
/* someone beat us to filling the PDE while we didn't have the lock */
if (unlikely(vpgt->refcount[big]++)) {
mutex_unlock(&nv_subdev(mmu)->mutex);
- nouveau_gpuobj_ref(NULL, &pgt);
+ nvkm_gpuobj_ref(NULL, &pgt);
mutex_lock(&nv_subdev(mmu)->mutex);
return 0;
}
@@ -286,18 +284,18 @@ nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
}
int
-nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
- u32 access, struct nouveau_vma *vma)
+nvkm_vm_get(struct nvkm_vm *vm, u64 size, u32 page_shift, u32 access,
+ struct nvkm_vma *vma)
{
- struct nouveau_mmu *mmu = vm->mmu;
+ struct nvkm_mmu *mmu = vm->mmu;
u32 align = (1 << page_shift) >> 12;
u32 msize = size >> 12;
u32 fpde, lpde, pde;
int ret;
mutex_lock(&nv_subdev(mmu)->mutex);
- ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align,
- &vma->node);
+ ret = nvkm_mm_head(&vm->mm, 0, page_shift, msize, msize, align,
+ &vma->node);
if (unlikely(ret != 0)) {
mutex_unlock(&nv_subdev(mmu)->mutex);
return ret;
@@ -307,7 +305,7 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits;
for (pde = fpde; pde <= lpde; pde++) {
- struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
+ struct nvkm_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
int big = (vma->node->type != mmu->spg_shift);
if (likely(vpgt->refcount[big])) {
@@ -315,11 +313,11 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
continue;
}
- ret = nouveau_vm_map_pgt(vm, pde, vma->node->type);
+ ret = nvkm_vm_map_pgt(vm, pde, vma->node->type);
if (ret) {
if (pde != fpde)
- nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1);
- nouveau_mm_free(&vm->mm, &vma->node);
+ nvkm_vm_unmap_pgt(vm, big, fpde, pde - 1);
+ nvkm_mm_free(&vm->mm, &vma->node);
mutex_unlock(&nv_subdev(mmu)->mutex);
return ret;
}
@@ -327,17 +325,17 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
mutex_unlock(&nv_subdev(mmu)->mutex);
vma->vm = NULL;
- nouveau_vm_ref(vm, &vma->vm, NULL);
+ nvkm_vm_ref(vm, &vma->vm, NULL);
vma->offset = (u64)vma->node->offset << 12;
vma->access = access;
return 0;
}
void
-nouveau_vm_put(struct nouveau_vma *vma)
+nvkm_vm_put(struct nvkm_vma *vma)
{
- struct nouveau_vm *vm = vma->vm;
- struct nouveau_mmu *mmu = vm->mmu;
+ struct nvkm_vm *vm = vma->vm;
+ struct nvkm_mmu *mmu = vm->mmu;
u32 fpde, lpde;
if (unlikely(vma->node == NULL))
@@ -346,18 +344,18 @@ nouveau_vm_put(struct nouveau_vma *vma)
lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits;
mutex_lock(&nv_subdev(mmu)->mutex);
- nouveau_vm_unmap_pgt(vm, vma->node->type != mmu->spg_shift, fpde, lpde);
- nouveau_mm_free(&vm->mm, &vma->node);
+ nvkm_vm_unmap_pgt(vm, vma->node->type != mmu->spg_shift, fpde, lpde);
+ nvkm_mm_free(&vm->mm, &vma->node);
mutex_unlock(&nv_subdev(mmu)->mutex);
- nouveau_vm_ref(NULL, &vma->vm, NULL);
+ nvkm_vm_ref(NULL, &vma->vm, NULL);
}
int
-nouveau_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
- u64 mm_offset, u32 block, struct nouveau_vm **pvm)
+nvkm_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset,
+ u32 block, struct nvkm_vm **pvm)
{
- struct nouveau_vm *vm;
+ struct nvkm_vm *vm;
u64 mm_length = (offset + length) - mm_offset;
int ret;
@@ -377,8 +375,8 @@ nouveau_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
return -ENOMEM;
}
- ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12,
- block >> 12);
+ ret = nvkm_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12,
+ block >> 12);
if (ret) {
vfree(vm->pgt);
kfree(vm);
@@ -391,18 +389,18 @@ nouveau_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
}
int
-nouveau_vm_new(struct nouveau_device *device, u64 offset, u64 length,
- u64 mm_offset, struct nouveau_vm **pvm)
+nvkm_vm_new(struct nvkm_device *device, u64 offset, u64 length, u64 mm_offset,
+ struct nvkm_vm **pvm)
{
- struct nouveau_mmu *mmu = nouveau_mmu(device);
+ struct nvkm_mmu *mmu = nvkm_mmu(device);
return mmu->create(mmu, offset, length, mm_offset, pvm);
}
static int
-nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
+nvkm_vm_link(struct nvkm_vm *vm, struct nvkm_gpuobj *pgd)
{
- struct nouveau_mmu *mmu = vm->mmu;
- struct nouveau_vm_pgd *vpgd;
+ struct nvkm_mmu *mmu = vm->mmu;
+ struct nvkm_vm_pgd *vpgd;
int i;
if (!pgd)
@@ -412,7 +410,7 @@ nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
if (!vpgd)
return -ENOMEM;
- nouveau_gpuobj_ref(pgd, &vpgd->obj);
+ nvkm_gpuobj_ref(pgd, &vpgd->obj);
mutex_lock(&nv_subdev(mmu)->mutex);
for (i = vm->fpde; i <= vm->lpde; i++)
@@ -423,11 +421,11 @@ nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
}
static void
-nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd)
+nvkm_vm_unlink(struct nvkm_vm *vm, struct nvkm_gpuobj *mpgd)
{
- struct nouveau_mmu *mmu = vm->mmu;
- struct nouveau_vm_pgd *vpgd, *tmp;
- struct nouveau_gpuobj *pgd = NULL;
+ struct nvkm_mmu *mmu = vm->mmu;
+ struct nvkm_vm_pgd *vpgd, *tmp;
+ struct nvkm_gpuobj *pgd = NULL;
if (!mpgd)
return;
@@ -443,30 +441,29 @@ nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd)
}
mutex_unlock(&nv_subdev(mmu)->mutex);
- nouveau_gpuobj_ref(NULL, &pgd);
+ nvkm_gpuobj_ref(NULL, &pgd);
}
static void
-nouveau_vm_del(struct kref *kref)
+nvkm_vm_del(struct kref *kref)
{
- struct nouveau_vm *vm = container_of(kref, typeof(*vm), refcount);
- struct nouveau_vm_pgd *vpgd, *tmp;
+ struct nvkm_vm *vm = container_of(kref, typeof(*vm), refcount);
+ struct nvkm_vm_pgd *vpgd, *tmp;
list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) {
- nouveau_vm_unlink(vm, vpgd->obj);
+ nvkm_vm_unlink(vm, vpgd->obj);
}
- nouveau_mm_fini(&vm->mm);
+ nvkm_mm_fini(&vm->mm);
vfree(vm->pgt);
kfree(vm);
}
int
-nouveau_vm_ref(struct nouveau_vm *ref, struct nouveau_vm **ptr,
- struct nouveau_gpuobj *pgd)
+nvkm_vm_ref(struct nvkm_vm *ref, struct nvkm_vm **ptr, struct nvkm_gpuobj *pgd)
{
if (ref) {
- int ret = nouveau_vm_link(ref, pgd);
+ int ret = nvkm_vm_link(ref, pgd);
if (ret)
return ret;
@@ -474,8 +471,8 @@ nouveau_vm_ref(struct nouveau_vm *ref, struct nouveau_vm **ptr,
}
if (*ptr) {
- nouveau_vm_unlink(*ptr, pgd);
- kref_put(&(*ptr)->refcount, nouveau_vm_del);
+ nvkm_vm_unlink(*ptr, pgd);
+ kref_put(&(*ptr)->refcount, nvkm_vm_del);
}
*ptr = ref;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
similarity index 75%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
index bd695c59aac7..294cda37f068 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
@@ -21,25 +21,23 @@
*
* Authors: Ben Skeggs
*/
+#include <subdev/mmu.h>
+#include <subdev/bar.h>
+#include <subdev/fb.h>
+#include <subdev/ltc.h>
+#include <subdev/timer.h>
-#include <core/device.h>
#include <core/gpuobj.h>
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/mmu.h>
-#include <subdev/ltc.h>
-#include <subdev/bar.h>
-
-struct nvc0_mmu_priv {
- struct nouveau_mmu base;
+struct gf100_mmu_priv {
+ struct nvkm_mmu base;
};
/* Map from compressed to corresponding uncompressed storage type.
* The value 0xff represents an invalid storage type.
*/
-const u8 nvc0_pte_storage_type_map[256] =
+const u8 gf100_pte_storage_type_map[256] =
{
0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0xff, 0x01, /* 0x00 */
0x01, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff,
@@ -77,8 +75,7 @@ const u8 nvc0_pte_storage_type_map[256] =
static void
-nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index,
- struct nouveau_gpuobj *pgt[2])
+gf100_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 index, struct nvkm_gpuobj *pgt[2])
{
u32 pde[2] = { 0, 0 };
@@ -92,7 +89,7 @@ nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index,
}
static inline u64
-nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
+gf100_vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target)
{
phys >>= 8;
@@ -102,21 +99,20 @@ nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
phys |= ((u64)target << 32);
phys |= ((u64)memtype << 36);
-
return phys;
}
static void
-nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
- struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
+gf100_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
+ struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
{
u64 next = 1 << (vma->node->type - 8);
- phys = nvc0_vm_addr(vma, phys, mem->memtype, 0);
+ phys = gf100_vm_addr(vma, phys, mem->memtype, 0);
pte <<= 3;
if (mem->tag) {
- struct nouveau_ltc *ltc = nouveau_ltc(vma->vm->mmu);
+ struct nvkm_ltc *ltc = nvkm_ltc(vma->vm->mmu);
u32 tag = mem->tag->offset + (delta >> 17);
phys |= (u64)tag << (32 + 12);
next |= (u64)1 << (32 + 12);
@@ -132,16 +128,16 @@ nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
}
static void
-nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
- struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
+gf100_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
+ struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5;
/* compressed storage types are invalid for system memory */
- u32 memtype = nvc0_pte_storage_type_map[mem->memtype & 0xff];
+ u32 memtype = gf100_pte_storage_type_map[mem->memtype & 0xff];
pte <<= 3;
while (cnt--) {
- u64 phys = nvc0_vm_addr(vma, *list++, memtype, target);
+ u64 phys = gf100_vm_addr(vma, *list++, memtype, target);
nv_wo32(pgt, pte + 0, lower_32_bits(phys));
nv_wo32(pgt, pte + 4, upper_32_bits(phys));
pte += 8;
@@ -149,7 +145,7 @@ nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
}
static void
-nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
+gf100_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
{
pte <<= 3;
while (cnt--) {
@@ -160,11 +156,11 @@ nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
}
static void
-nvc0_vm_flush(struct nouveau_vm *vm)
+gf100_vm_flush(struct nvkm_vm *vm)
{
- struct nvc0_mmu_priv *priv = (void *)vm->mmu;
- struct nouveau_bar *bar = nouveau_bar(priv);
- struct nouveau_vm_pgd *vpgd;
+ struct gf100_mmu_priv *priv = (void *)vm->mmu;
+ struct nvkm_bar *bar = nvkm_bar(priv);
+ struct nvkm_vm_pgd *vpgd;
u32 type;
bar->flush(bar);
@@ -196,21 +192,21 @@ nvc0_vm_flush(struct nouveau_vm *vm)
}
static int
-nvc0_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
- u64 mm_offset, struct nouveau_vm **pvm)
+gf100_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset,
+ struct nvkm_vm **pvm)
{
- return nouveau_vm_create(mmu, offset, length, mm_offset, 4096, pvm);
+ return nvkm_vm_create(mmu, offset, length, mm_offset, 4096, pvm);
}
static int
-nvc0_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvc0_mmu_priv *priv;
+ struct gf100_mmu_priv *priv;
int ret;
- ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
+ ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -220,22 +216,22 @@ nvc0_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.pgt_bits = 27 - 12;
priv->base.spg_shift = 12;
priv->base.lpg_shift = 17;
- priv->base.create = nvc0_vm_create;
- priv->base.map_pgt = nvc0_vm_map_pgt;
- priv->base.map = nvc0_vm_map;
- priv->base.map_sg = nvc0_vm_map_sg;
- priv->base.unmap = nvc0_vm_unmap;
- priv->base.flush = nvc0_vm_flush;
+ priv->base.create = gf100_vm_create;
+ priv->base.map_pgt = gf100_vm_map_pgt;
+ priv->base.map = gf100_vm_map;
+ priv->base.map_sg = gf100_vm_map_sg;
+ priv->base.unmap = gf100_vm_unmap;
+ priv->base.flush = gf100_vm_flush;
return 0;
}
-struct nouveau_oclass
-nvc0_mmu_oclass = {
+struct nvkm_oclass
+gf100_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_mmu_ctor,
- .dtor = _nouveau_mmu_dtor,
- .init = _nouveau_mmu_init,
- .fini = _nouveau_mmu_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_mmu_ctor,
+ .dtor = _nvkm_mmu_dtor,
+ .init = _nvkm_mmu_init,
+ .fini = _nvkm_mmu_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
index a317d8f13570..fe93ea2711c9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
@@ -21,11 +21,11 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/gpuobj.h>
-
#include "nv04.h"
+#include <core/device.h>
+#include <core/gpuobj.h>
+
#define NV04_PDMA_SIZE (128 * 1024 * 1024)
#define NV04_PDMA_PAGE ( 4 * 1024)
@@ -34,8 +34,8 @@
******************************************************************************/
static void
-nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
- struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
+nv04_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
+ struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
pte = 0x00008 + (pte * 4);
while (cnt) {
@@ -51,7 +51,7 @@ nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
}
static void
-nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
+nv04_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
{
pte = 0x00008 + (pte * 4);
while (cnt--) {
@@ -61,7 +61,7 @@ nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
}
static void
-nv04_vm_flush(struct nouveau_vm *vm)
+nv04_vm_flush(struct nvkm_vm *vm)
{
}
@@ -70,8 +70,8 @@ nv04_vm_flush(struct nouveau_vm *vm)
******************************************************************************/
int
-nv04_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, u64 mmstart,
- struct nouveau_vm **pvm)
+nv04_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mmstart,
+ struct nvkm_vm **pvm)
{
return -EINVAL;
}
@@ -81,16 +81,16 @@ nv04_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, u64 mmstart,
******************************************************************************/
static int
-nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_mmu_priv *priv;
- struct nouveau_gpuobj *dma;
+ struct nvkm_gpuobj *dma;
int ret;
- ret = nouveau_mmu_create(parent, engine, oclass, "PCIGART",
- "pcigart", &priv);
+ ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART",
+ "pcigart", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -105,15 +105,15 @@ nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.unmap = nv04_vm_unmap;
priv->base.flush = nv04_vm_flush;
- ret = nouveau_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096,
- &priv->vm);
+ ret = nvkm_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096,
+ &priv->vm);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL,
- (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 +
- 8, 16, NVOBJ_FLAG_ZERO_ALLOC,
- &priv->vm->pgt[0].obj[0]);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL,
+ (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + 8,
+ 16, NVOBJ_FLAG_ZERO_ALLOC,
+ &priv->vm->pgt[0].obj[0]);
dma = priv->vm->pgt[0].obj[0];
priv->vm->pgt[0].refcount[0] = 1;
if (ret)
@@ -125,27 +125,27 @@ nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
void
-nv04_mmu_dtor(struct nouveau_object *object)
+nv04_mmu_dtor(struct nvkm_object *object)
{
struct nv04_mmu_priv *priv = (void *)object;
if (priv->vm) {
- nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]);
- nouveau_vm_ref(NULL, &priv->vm, NULL);
+ nvkm_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]);
+ nvkm_vm_ref(NULL, &priv->vm, NULL);
}
if (priv->nullp) {
pci_free_consistent(nv_device(priv)->pdev, 16 * 1024,
priv->nullp, priv->null);
}
- nouveau_mmu_destroy(&priv->base);
+ nvkm_mmu_destroy(&priv->base);
}
-struct nouveau_oclass
+struct nvkm_oclass
nv04_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0x04),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mmu_ctor,
.dtor = nv04_mmu_dtor,
- .init = _nouveau_mmu_init,
- .fini = _nouveau_mmu_fini,
+ .init = _nvkm_mmu_init,
+ .fini = _nvkm_mmu_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h
index 919b254ef6a1..7bf6f4b38f1d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h
@@ -4,8 +4,8 @@
#include <subdev/mmu.h>
struct nv04_mmu_priv {
- struct nouveau_mmu base;
- struct nouveau_vm *vm;
+ struct nvkm_mmu base;
+ struct nvkm_vm *vm;
dma_addr_t null;
void *nullp;
};
@@ -13,7 +13,7 @@ struct nv04_mmu_priv {
static inline struct nv04_mmu_priv *
nv04_mmu(void *obj)
{
- return (void *)nouveau_mmu(obj);
+ return (void *)nvkm_mmu(obj);
}
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
index 61af036f1252..61ee3ab11660 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
@@ -21,14 +21,12 @@
*
* Authors: Ben Skeggs
*/
+#include "nv04.h"
+#include <core/device.h>
#include <core/gpuobj.h>
#include <core/option.h>
-
#include <subdev/timer.h>
-#include <subdev/mmu.h>
-
-#include "nv04.h"
#define NV41_GART_SIZE (512 * 1024 * 1024)
#define NV41_GART_PAGE ( 4 * 1024)
@@ -38,8 +36,8 @@
******************************************************************************/
static void
-nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
- struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
+nv41_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
+ struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
pte = pte * 4;
while (cnt) {
@@ -55,7 +53,7 @@ nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
}
static void
-nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
+nv41_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
{
pte = pte * 4;
while (cnt--) {
@@ -65,7 +63,7 @@ nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
}
static void
-nv41_vm_flush(struct nouveau_vm *vm)
+nv41_vm_flush(struct nvkm_vm *vm)
{
struct nv04_mmu_priv *priv = (void *)vm->mmu;
@@ -84,22 +82,22 @@ nv41_vm_flush(struct nouveau_vm *vm)
******************************************************************************/
static int
-nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_device *device = nv_device(parent);
+ struct nvkm_device *device = nv_device(parent);
struct nv04_mmu_priv *priv;
int ret;
if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
- !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
- return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass,
- data, size, pobject);
+ !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) {
+ return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass,
+ data, size, pobject);
}
- ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART",
- "pciegart", &priv);
+ ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART",
+ "pciegart", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -114,15 +112,15 @@ nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.unmap = nv41_vm_unmap;
priv->base.flush = nv41_vm_flush;
- ret = nouveau_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096,
- &priv->vm);
+ ret = nvkm_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096,
+ &priv->vm);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL,
- (NV41_GART_SIZE / NV41_GART_PAGE) * 4,
- 16, NVOBJ_FLAG_ZERO_ALLOC,
- &priv->vm->pgt[0].obj[0]);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL,
+ (NV41_GART_SIZE / NV41_GART_PAGE) * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC,
+ &priv->vm->pgt[0].obj[0]);
priv->vm->pgt[0].refcount[0] = 1;
if (ret)
return ret;
@@ -131,13 +129,13 @@ nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
static int
-nv41_mmu_init(struct nouveau_object *object)
+nv41_mmu_init(struct nvkm_object *object)
{
struct nv04_mmu_priv *priv = (void *)object;
- struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0];
+ struct nvkm_gpuobj *dma = priv->vm->pgt[0].obj[0];
int ret;
- ret = nouveau_mmu_init(&priv->base);
+ ret = nvkm_mmu_init(&priv->base);
if (ret)
return ret;
@@ -147,13 +145,13 @@ nv41_mmu_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv41_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0x41),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv41_mmu_ctor,
.dtor = nv04_mmu_dtor,
.init = nv41_mmu_init,
- .fini = _nouveau_mmu_fini,
+ .fini = _nvkm_mmu_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
index f5319e3e7fe5..b90ded1887aa 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
@@ -21,14 +21,12 @@
*
* Authors: Ben Skeggs
*/
+#include "nv04.h"
+#include <core/device.h>
#include <core/gpuobj.h>
#include <core/option.h>
-
#include <subdev/timer.h>
-#include <subdev/mmu.h>
-
-#include "nv04.h"
#define NV44_GART_SIZE (512 * 1024 * 1024)
#define NV44_GART_PAGE ( 4 * 1024)
@@ -38,7 +36,7 @@
******************************************************************************/
static void
-nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null,
+nv44_vm_fill(struct nvkm_gpuobj *pgt, dma_addr_t null,
dma_addr_t *list, u32 pte, u32 cnt)
{
u32 base = (pte << 2) & ~0x0000000f;
@@ -84,8 +82,8 @@ nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null,
}
static void
-nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
- struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
+nv44_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
+ struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
struct nv04_mmu_priv *priv = (void *)vma->vm->mmu;
u32 tmp[4];
@@ -115,9 +113,9 @@ nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
}
static void
-nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
+nv44_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
{
- struct nv04_mmu_priv *priv = (void *)nouveau_mmu(pgt);
+ struct nv04_mmu_priv *priv = (void *)nvkm_mmu(pgt);
if (pte & 3) {
u32 max = 4 - (pte & 3);
@@ -140,7 +138,7 @@ nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
}
static void
-nv44_vm_flush(struct nouveau_vm *vm)
+nv44_vm_flush(struct nvkm_vm *vm)
{
struct nv04_mmu_priv *priv = (void *)vm->mmu;
nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE);
@@ -155,22 +153,22 @@ nv44_vm_flush(struct nouveau_vm *vm)
******************************************************************************/
static int
-nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv44_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_device *device = nv_device(parent);
+ struct nvkm_device *device = nv_device(parent);
struct nv04_mmu_priv *priv;
int ret;
if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
- !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
- return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass,
- data, size, pobject);
+ !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) {
+ return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass,
+ data, size, pobject);
}
- ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART",
- "pciegart", &priv);
+ ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART",
+ "pciegart", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -191,15 +189,15 @@ nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return -ENOMEM;
}
- ret = nouveau_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096,
- &priv->vm);
+ ret = nvkm_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096,
+ &priv->vm);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL,
- (NV44_GART_SIZE / NV44_GART_PAGE) * 4,
- 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC,
- &priv->vm->pgt[0].obj[0]);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL,
+ (NV44_GART_SIZE / NV44_GART_PAGE) * 4,
+ 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC,
+ &priv->vm->pgt[0].obj[0]);
priv->vm->pgt[0].refcount[0] = 1;
if (ret)
return ret;
@@ -208,14 +206,14 @@ nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
static int
-nv44_mmu_init(struct nouveau_object *object)
+nv44_mmu_init(struct nvkm_object *object)
{
struct nv04_mmu_priv *priv = (void *)object;
- struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0];
+ struct nvkm_gpuobj *gart = priv->vm->pgt[0].obj[0];
u32 addr;
int ret;
- ret = nouveau_mmu_init(&priv->base);
+ ret = nvkm_mmu_init(&priv->base);
if (ret)
return ret;
@@ -237,13 +235,13 @@ nv44_mmu_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv44_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0x44),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv44_mmu_ctor,
.dtor = nv04_mmu_dtor,
.init = nv44_mmu_init,
- .fini = _nouveau_mmu_fini,
+ .fini = _nvkm_mmu_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
index 70e1a140e7a3..b83550fa7f96 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
@@ -21,22 +21,20 @@
*
* Authors: Ben Skeggs
*/
+#include <subdev/mmu.h>
+#include <subdev/bar.h>
+#include <subdev/fb.h>
+#include <subdev/timer.h>
-#include <core/device.h>
+#include <core/engine.h>
#include <core/gpuobj.h>
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/bar.h>
-#include <subdev/mmu.h>
-
struct nv50_mmu_priv {
- struct nouveau_mmu base;
+ struct nvkm_mmu base;
};
static void
-nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
- struct nouveau_gpuobj *pgt[2])
+nv50_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 pde, struct nvkm_gpuobj *pgt[2])
{
u64 phys = 0xdeadcafe00000000ULL;
u32 coverage = 0;
@@ -64,7 +62,7 @@ nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
}
static inline u64
-vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
+vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target)
{
phys |= 1; /* present */
phys |= (u64)memtype << 40;
@@ -77,8 +75,8 @@ vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
}
static void
-nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
- struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
+nv50_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
+ struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
{
u32 comp = (mem->memtype & 0x180) >> 7;
u32 block, target;
@@ -86,8 +84,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
/* IGPs don't have real VRAM, re-target to stolen system memory */
target = 0;
- if (nouveau_fb(vma->vm->mmu)->ram->stolen) {
- phys += nouveau_fb(vma->vm->mmu)->ram->stolen;
+ if (nvkm_fb(vma->vm->mmu)->ram->stolen) {
+ phys += nvkm_fb(vma->vm->mmu)->ram->stolen;
target = 3;
}
@@ -124,8 +122,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
}
static void
-nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
- struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
+nv50_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
+ struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2;
pte <<= 3;
@@ -138,7 +136,7 @@ nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
}
static void
-nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
+nv50_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
{
pte <<= 3;
while (cnt--) {
@@ -149,11 +147,11 @@ nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
}
static void
-nv50_vm_flush(struct nouveau_vm *vm)
+nv50_vm_flush(struct nvkm_vm *vm)
{
struct nv50_mmu_priv *priv = (void *)vm->mmu;
- struct nouveau_bar *bar = nouveau_bar(priv);
- struct nouveau_engine *engine;
+ struct nvkm_bar *bar = nvkm_bar(priv);
+ struct nvkm_engine *engine;
int i, vme;
bar->flush(bar);
@@ -164,7 +162,7 @@ nv50_vm_flush(struct nouveau_vm *vm)
continue;
/* unfortunate hw bug workaround... */
- engine = nouveau_engine(priv, i);
+ engine = nvkm_engine(priv, i);
if (engine && engine->tlb_flush) {
engine->tlb_flush(engine);
continue;
@@ -194,25 +192,25 @@ nv50_vm_flush(struct nouveau_vm *vm)
}
static int
-nv50_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
- u64 mm_offset, struct nouveau_vm **pvm)
+nv50_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length,
+ u64 mm_offset, struct nvkm_vm **pvm)
{
u32 block = (1 << (mmu->pgt_bits + 12));
if (block > length)
block = length;
- return nouveau_vm_create(mmu, offset, length, mm_offset, block, pvm);
+ return nvkm_vm_create(mmu, offset, length, mm_offset, block, pvm);
}
static int
-nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_mmu_priv *priv;
int ret;
- ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
+ ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -231,13 +229,13 @@ nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv50_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_mmu_ctor,
- .dtor = _nouveau_mmu_dtor,
- .init = _nouveau_mmu_init,
- .fini = _nouveau_mmu_fini,
+ .dtor = _nvkm_mmu_dtor,
+ .init = _nvkm_mmu_init,
+ .fini = _nvkm_mmu_fini,
},
};
From 21b137916ec25a507dbf7b6fe8b353fe9dc723c0 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:10:40 +1000
Subject: [PATCH 66/86] drm/nouveau/pmu: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 4 ++
.../gpu/drm/nouveau/include/nvkm/subdev/pmu.h | 56 ++++++++--------
.../drm/nouveau/nvkm/engine/device/gm100.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 8 +--
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 16 ++---
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 10 +--
.../gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild | 8 +--
.../gpu/drm/nouveau/nvkm/subdev/pmu/base.c | 64 +++++++++---------
.../subdev/pmu/fuc/{nvc0.fuc3 => gf100.fuc3} | 4 +-
.../pmu/fuc/{nvc0.fuc3.h => gf100.fuc3.h} | 4 +-
.../subdev/pmu/fuc/{nvd0.fuc4 => gf110.fuc4} | 4 +-
.../pmu/fuc/{nvd0.fuc4.h => gf110.fuc4.h} | 4 +-
.../subdev/pmu/fuc/{nv108.fuc5 => gk208.fuc5} | 4 +-
.../pmu/fuc/{nv108.fuc5.h => gk208.fuc5.h} | 4 +-
.../subdev/pmu/fuc/{nva3.fuc3 => gt215.fuc3} | 4 +-
.../pmu/fuc/{nva3.fuc3.h => gt215.fuc3.h} | 4 +-
.../nvkm/subdev/pmu/{nvc0.c => gf100.c} | 25 ++++---
.../nvkm/subdev/pmu/{nvd0.c => gf110.c} | 25 ++++---
.../gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c | 22 +++----
.../nvkm/subdev/pmu/{nv108.c => gk208.c} | 25 ++++---
.../gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c | 65 +++++++++----------
.../nvkm/subdev/pmu/{nva3.c => gt215.c} | 31 +++++----
.../gpu/drm/nouveau/nvkm/subdev/pmu/memx.c | 49 +++++++-------
.../gpu/drm/nouveau/nvkm/subdev/pmu/priv.h | 44 ++++++-------
27 files changed, 239 insertions(+), 252 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/{nvc0.fuc3 => gf100.fuc3} (97%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/{nvc0.fuc3.h => gf100.fuc3.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/{nvd0.fuc4 => gf110.fuc4} (97%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/{nvd0.fuc4.h => gf110.fuc4.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/{nv108.fuc5 => gk208.fuc5} (97%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/{nv108.fuc5.h => gk208.fuc5.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/{nva3.fuc3 => gt215.fuc3} (97%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/{nva3.fuc3.h => gt215.fuc3.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/pmu/{nvc0.c => gf100.c} (75%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/pmu/{nvd0.c => gf110.c} (75%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/pmu/{nv108.c => gk208.c} (75%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/pmu/{nva3.c => gt215.c} (72%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 423086564735..625d390d4c22 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -209,6 +209,10 @@
#define nouveau_volt nvkm_volt
#define nouveau_timer nvkm_timer
#define nouveau_timer_wait_eq nvkm_timer_wait_eq
+#define nouveau_timer_alarm nvkm_timer_alarm
+#define nouveau_alarm nvkm_alarm
+#define nouveau_timer_alarm_cancel nvkm_timer_alarm_cancel
+#define nouveau_alarm_init nvkm_alarm_init
#define nva3_pll_calc gt215_pll_calc
#define nouveau_clk nvkm_clk
#define nouveau_domain nvkm_domain
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
index c890a4fb3cbb..7b86acc634a0 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
@@ -1,11 +1,9 @@
-#ifndef __NOUVEAU_PMU_H__
-#define __NOUVEAU_PMU_H__
-
+#ifndef __NVKM_PMU_H__
+#define __NVKM_PMU_H__
#include <core/subdev.h>
-#include <core/device.h>
-struct nouveau_pmu {
- struct nouveau_subdev base;
+struct nvkm_pmu {
+ struct nvkm_subdev base;
struct {
u32 base;
@@ -23,35 +21,33 @@ struct nouveau_pmu {
u32 data[2];
} recv;
- int (*message)(struct nouveau_pmu *, u32[2], u32, u32, u32, u32);
- void (*pgob)(struct nouveau_pmu *, bool);
+ int (*message)(struct nvkm_pmu *, u32[2], u32, u32, u32, u32);
+ void (*pgob)(struct nvkm_pmu *, bool);
};
-static inline struct nouveau_pmu *
-nouveau_pmu(void *obj)
+static inline struct nvkm_pmu *
+nvkm_pmu(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_PMU);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_PMU);
}
-extern struct nouveau_oclass *nva3_pmu_oclass;
-extern struct nouveau_oclass *nvc0_pmu_oclass;
-extern struct nouveau_oclass *nvd0_pmu_oclass;
-extern struct nouveau_oclass *gk104_pmu_oclass;
-extern struct nouveau_oclass *nv108_pmu_oclass;
-extern struct nouveau_oclass *gk20a_pmu_oclass;
+extern struct nvkm_oclass *gt215_pmu_oclass;
+extern struct nvkm_oclass *gf100_pmu_oclass;
+extern struct nvkm_oclass *gf110_pmu_oclass;
+extern struct nvkm_oclass *gk104_pmu_oclass;
+extern struct nvkm_oclass *gk208_pmu_oclass;
+extern struct nvkm_oclass *gk20a_pmu_oclass;
/* interface to MEMX process running on PMU */
-struct nouveau_memx;
-int nouveau_memx_init(struct nouveau_pmu *, struct nouveau_memx **);
-int nouveau_memx_fini(struct nouveau_memx **, bool exec);
-void nouveau_memx_wr32(struct nouveau_memx *, u32 addr, u32 data);
-void nouveau_memx_wait(struct nouveau_memx *,
- u32 addr, u32 mask, u32 data, u32 nsec);
-void nouveau_memx_nsec(struct nouveau_memx *, u32 nsec);
-void nouveau_memx_wait_vblank(struct nouveau_memx *);
-void nouveau_memx_train(struct nouveau_memx *);
-int nouveau_memx_train_result(struct nouveau_pmu *, u32 *, int);
-void nouveau_memx_block(struct nouveau_memx *);
-void nouveau_memx_unblock(struct nouveau_memx *);
-
+struct nvkm_memx;
+int nvkm_memx_init(struct nvkm_pmu *, struct nvkm_memx **);
+int nvkm_memx_fini(struct nvkm_memx **, bool exec);
+void nvkm_memx_wr32(struct nvkm_memx *, u32 addr, u32 data);
+void nvkm_memx_wait(struct nvkm_memx *, u32 addr, u32 mask, u32 data, u32 nsec);
+void nvkm_memx_nsec(struct nvkm_memx *, u32 nsec);
+void nvkm_memx_wait_vblank(struct nvkm_memx *);
+void nvkm_memx_train(struct nvkm_memx *);
+int nvkm_memx_train_result(struct nvkm_pmu *, u32 *, int);
+void nvkm_memx_block(struct nvkm_memx *);
+void nvkm_memx_unblock(struct nvkm_memx *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index adf9c27a88b6..342305f8abd8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -78,7 +78,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -122,7 +122,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 6183cc372d17..9394962e6c7f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -365,7 +365,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
@@ -396,7 +396,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
@@ -426,7 +426,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
@@ -456,7 +456,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nva3_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 6cd796c33ba0..90f3fcc47c55 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -78,7 +78,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -111,7 +111,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -144,7 +144,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -176,7 +176,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -209,7 +209,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -241,7 +241,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -273,7 +273,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@@ -306,7 +306,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 64aee47dee89..6b6e54828efb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -112,7 +112,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
@@ -202,7 +202,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
@@ -236,7 +236,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
@@ -270,7 +270,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
@@ -303,7 +303,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
+ device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
index dcb175bea84b..de9f39569943 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
@@ -24,6 +24,7 @@
#include "gf100.h"
#include "ramfuc.h"
+#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
index 97060ccfb80c..1ef15c3e6a81 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
@@ -24,6 +24,7 @@
#include "ramfuc.h"
#include "gf100.h"
+#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/init.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
index 692a1cc6c957..24176401b49b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
@@ -26,6 +26,7 @@
#include "ramfuc.h"
#include "nv50.h"
+#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/M0205.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild
index 85c8392c8ace..9a150d520225 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild
@@ -1,8 +1,8 @@
nvkm-y += nvkm/subdev/pmu/base.o
nvkm-y += nvkm/subdev/pmu/memx.o
-nvkm-y += nvkm/subdev/pmu/nva3.o
-nvkm-y += nvkm/subdev/pmu/nvc0.o
-nvkm-y += nvkm/subdev/pmu/nvd0.o
+nvkm-y += nvkm/subdev/pmu/gt215.o
+nvkm-y += nvkm/subdev/pmu/gf100.o
+nvkm-y += nvkm/subdev/pmu/gf110.o
nvkm-y += nvkm/subdev/pmu/gk104.o
-nvkm-y += nvkm/subdev/pmu/nv108.o
+nvkm-y += nvkm/subdev/pmu/gk208.o
nvkm-y += nvkm/subdev/pmu/gk20a.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c
index 562ea6e16819..054b2d2eec35 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/timer.h>
-#include "priv.h"
-
void
-nouveau_pmu_pgob(struct nouveau_pmu *pmu, bool enable)
+nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
{
const struct nvkm_pmu_impl *impl = (void *)nv_oclass(pmu);
if (impl->pgob)
@@ -35,10 +34,10 @@ nouveau_pmu_pgob(struct nouveau_pmu *pmu, bool enable)
}
static int
-nouveau_pmu_send(struct nouveau_pmu *pmu, u32 reply[2],
- u32 process, u32 message, u32 data0, u32 data1)
+nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2],
+ u32 process, u32 message, u32 data0, u32 data1)
{
- struct nouveau_subdev *subdev = nv_subdev(pmu);
+ struct nvkm_subdev *subdev = nv_subdev(pmu);
u32 addr;
/* wait for a free slot in the fifo */
@@ -85,10 +84,9 @@ nouveau_pmu_send(struct nouveau_pmu *pmu, u32 reply[2],
}
static void
-nouveau_pmu_recv(struct work_struct *work)
+nvkm_pmu_recv(struct work_struct *work)
{
- struct nouveau_pmu *pmu =
- container_of(work, struct nouveau_pmu, recv.work);
+ struct nvkm_pmu *pmu = container_of(work, struct nvkm_pmu, recv.work);
u32 process, message, data0, data1;
/* nothing to do if GET == PUT */
@@ -137,9 +135,9 @@ nouveau_pmu_recv(struct work_struct *work)
}
static void
-nouveau_pmu_intr(struct nouveau_subdev *subdev)
+nvkm_pmu_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_pmu *pmu = (void *)subdev;
+ struct nvkm_pmu *pmu = (void *)subdev;
u32 disp = nv_rd32(pmu, 0x10a01c);
u32 intr = nv_rd32(pmu, 0x10a008) & disp & ~(disp >> 16);
@@ -161,7 +159,7 @@ nouveau_pmu_intr(struct nouveau_subdev *subdev)
if (intr & 0x00000080) {
nv_info(pmu, "wr32 0x%06x 0x%08x\n", nv_rd32(pmu, 0x10a7a0),
- nv_rd32(pmu, 0x10a7a4));
+ nv_rd32(pmu, 0x10a7a4));
nv_wr32(pmu, 0x10a004, 0x00000080);
intr &= ~0x00000080;
}
@@ -173,30 +171,30 @@ nouveau_pmu_intr(struct nouveau_subdev *subdev)
}
int
-_nouveau_pmu_fini(struct nouveau_object *object, bool suspend)
+_nvkm_pmu_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_pmu *pmu = (void *)object;
+ struct nvkm_pmu *pmu = (void *)object;
nv_wr32(pmu, 0x10a014, 0x00000060);
flush_work(&pmu->recv.work);
- return nouveau_subdev_fini(&pmu->base, suspend);
+ return nvkm_subdev_fini(&pmu->base, suspend);
}
int
-_nouveau_pmu_init(struct nouveau_object *object)
+_nvkm_pmu_init(struct nvkm_object *object)
{
const struct nvkm_pmu_impl *impl = (void *)object->oclass;
- struct nouveau_pmu *pmu = (void *)object;
+ struct nvkm_pmu *pmu = (void *)object;
int ret, i;
- ret = nouveau_subdev_init(&pmu->base);
+ ret = nvkm_subdev_init(&pmu->base);
if (ret)
return ret;
- nv_subdev(pmu)->intr = nouveau_pmu_intr;
- pmu->message = nouveau_pmu_send;
- pmu->pgob = nouveau_pmu_pgob;
+ nv_subdev(pmu)->intr = nvkm_pmu_intr;
+ pmu->message = nvkm_pmu_send;
+ pmu->pgob = nvkm_pmu_pgob;
/* prevent previous ucode from running, wait for idle, reset */
nv_wr32(pmu, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */
@@ -241,32 +239,30 @@ _nouveau_pmu_init(struct nouveau_object *object)
}
int
-nouveau_pmu_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int length, void **pobject)
+nvkm_pmu_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
- struct nouveau_pmu *pmu;
+ struct nvkm_pmu *pmu;
int ret;
- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PMU",
- "pmu", length, pobject);
+ ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PMU",
+ "pmu", length, pobject);
pmu = *pobject;
if (ret)
return ret;
- INIT_WORK(&pmu->recv.work, nouveau_pmu_recv);
+ INIT_WORK(&pmu->recv.work, nvkm_pmu_recv);
init_waitqueue_head(&pmu->recv.wait);
return 0;
}
int
-_nouveau_pmu_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+_nvkm_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_pmu *pmu;
- int ret = nouveau_pmu_create(parent, engine, oclass, &pmu);
+ struct nvkm_pmu *pmu;
+ int ret = nvkm_pmu_create(parent, engine, oclass, &pmu);
*pobject = nv_object(pmu);
return ret;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3
similarity index 97%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvc0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3
index 6eee93d3c313..37e8407b7462 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvc0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3
@@ -32,7 +32,7 @@
#include "macros.fuc"
-.section #nvc0_pmu_data
+.section #gf100_pmu_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "arith.fuc"
@@ -56,7 +56,7 @@
#undef INCLUDE_DATA
.align 256
-.section #nvc0_pmu_code
+.section #gf100_pmu_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "arith.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvc0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h
index 124f5c13ac0a..302557c52d03 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvc0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvc0_pmu_data[] = {
+uint32_t gf100_pmu_data[] = {
/* 0x0000: proc_kern */
0x52544e49,
0x00000000,
@@ -916,7 +916,7 @@ uint32_t nvc0_pmu_data[] = {
0x00000000,
};
-uint32_t nvc0_pmu_code[] = {
+uint32_t gf100_pmu_code[] = {
0x039e0ef5,
/* 0x0004: rd32 */
0x07a007f1,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvd0.fuc4 b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4
similarity index 97%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvd0.fuc4
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4
index e11f9934d977..ae9c3f18ae01 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvd0.fuc4
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4
@@ -32,7 +32,7 @@
#include "macros.fuc"
-.section #nvd0_pmu_data
+.section #gf110_pmu_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "arith.fuc"
@@ -56,7 +56,7 @@
#undef INCLUDE_DATA
.align 256
-.section #nvd0_pmu_code
+.section #gf110_pmu_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "arith.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvd0.fuc4.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvd0.fuc4.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4.h
index 6fc8c704f38b..a0c499e4543c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nvd0.fuc4.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4.h
@@ -1,4 +1,4 @@
-uint32_t nvd0_pmu_data[] = {
+uint32_t gf110_pmu_data[] = {
/* 0x0000: proc_kern */
0x52544e49,
0x00000000,
@@ -915,7 +915,7 @@ uint32_t nvd0_pmu_data[] = {
0x00000000,
};
-uint32_t nvd0_pmu_code[] = {
+uint32_t gf110_pmu_code[] = {
0x034d0ef5,
/* 0x0004: rd32 */
0x07a007f1,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5
similarity index 97%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nv108.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5
index d2214ab68f09..093dc81880f4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nv108.fuc5
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5
@@ -32,7 +32,7 @@
#include "macros.fuc"
-.section #nv108_pmu_data
+.section #gk208_pmu_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "arith.fuc"
@@ -56,7 +56,7 @@
#undef INCLUDE_DATA
.align 256
-.section #nv108_pmu_code
+.section #gk208_pmu_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "arith.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nv108.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h
index c25ee1f88128..fe4f63deeaab 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nv108.fuc5.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h
@@ -1,4 +1,4 @@
-uint32_t nv108_pmu_data[] = {
+uint32_t gk208_pmu_data[] = {
/* 0x0000: proc_kern */
0x52544e49,
0x00000000,
@@ -915,7 +915,7 @@ uint32_t nv108_pmu_data[] = {
0x00000000,
};
-uint32_t nv108_pmu_code[] = {
+uint32_t gk208_pmu_code[] = {
0x031c0ef5,
/* 0x0004: rd32 */
0xf607a040,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nva3.fuc3 b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3
similarity index 97%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nva3.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3
index 93d76177e935..393049fc8b2d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nva3.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3
@@ -32,7 +32,7 @@
#include "macros.fuc"
-.section #nva3_pmu_data
+.section #gt215_pmu_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "arith.fuc"
@@ -56,7 +56,7 @@
#undef INCLUDE_DATA
.align 256
-.section #nva3_pmu_code
+.section #gt215_pmu_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "arith.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nva3.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nva3.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h
index e8274401338c..2686f8fad0f5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/nva3.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nva3_pmu_data[] = {
+uint32_t gt215_pmu_data[] = {
/* 0x0000: proc_kern */
0x52544e49,
0x00000000,
@@ -916,7 +916,7 @@ uint32_t nva3_pmu_data[] = {
0x00000000,
};
-uint32_t nva3_pmu_code[] = {
+uint32_t gt215_pmu_code[] = {
0x039e0ef5,
/* 0x0004: rd32 */
0x07a007f1,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c
similarity index 75%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c
index a9fd1456f5b5..78a4ea0101f1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c
@@ -21,21 +21,20 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
-#include "fuc/nvc0.fuc3.h"
+#include "fuc/gf100.fuc3.h"
-struct nouveau_oclass *
-nvc0_pmu_oclass = &(struct nvkm_pmu_impl) {
+struct nvkm_oclass *
+gf100_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pmu_ctor,
- .dtor = _nouveau_pmu_dtor,
- .init = _nouveau_pmu_init,
- .fini = _nouveau_pmu_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_pmu_ctor,
+ .dtor = _nvkm_pmu_dtor,
+ .init = _nvkm_pmu_init,
+ .fini = _nvkm_pmu_fini,
},
- .code.data = nvc0_pmu_code,
- .code.size = sizeof(nvc0_pmu_code),
- .data.data = nvc0_pmu_data,
- .data.size = sizeof(nvc0_pmu_data),
+ .code.data = gf100_pmu_code,
+ .code.size = sizeof(gf100_pmu_code),
+ .data.data = gf100_pmu_data,
+ .data.size = sizeof(gf100_pmu_data),
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf110.c
similarity index 75%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf110.c
index a9b1d7e027a3..6b3a23839ff0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nvd0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf110.c
@@ -21,21 +21,20 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
-#include "fuc/nvd0.fuc4.h"
+#include "fuc/gf110.fuc4.h"
-struct nouveau_oclass *
-nvd0_pmu_oclass = &(struct nvkm_pmu_impl) {
+struct nvkm_oclass *
+gf110_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0xd0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pmu_ctor,
- .dtor = _nouveau_pmu_dtor,
- .init = _nouveau_pmu_init,
- .fini = _nouveau_pmu_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_pmu_ctor,
+ .dtor = _nvkm_pmu_dtor,
+ .init = _nvkm_pmu_init,
+ .fini = _nvkm_pmu_fini,
},
- .code.data = nvd0_pmu_code,
- .code.size = sizeof(nvd0_pmu_code),
- .data.data = nvd0_pmu_data,
- .data.size = sizeof(nvd0_pmu_data),
+ .code.data = gf110_pmu_code,
+ .code.size = sizeof(gf110_pmu_code),
+ .data.data = gf110_pmu_data,
+ .data.size = sizeof(gf110_pmu_data),
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c
index 7776b4a0958e..28fdb8ea9ed8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c
@@ -21,15 +21,13 @@
*
* Authors: Ben Skeggs
*/
-
+#define gf110_pmu_code gk104_pmu_code
+#define gf110_pmu_data gk104_pmu_data
#include "priv.h"
-
-#define nvd0_pmu_code gk104_pmu_code
-#define nvd0_pmu_data gk104_pmu_data
-#include "fuc/nvd0.fuc4.h"
+#include "fuc/gf110.fuc4.h"
static void
-gk104_pmu_pgob(struct nouveau_pmu *pmu, bool enable)
+gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
{
nv_mask(pmu, 0x000200, 0x00001000, 0x00000000);
nv_rd32(pmu, 0x000200);
@@ -52,14 +50,14 @@ gk104_pmu_pgob(struct nouveau_pmu *pmu, bool enable)
nv_rd32(pmu, 0x000200);
}
-struct nouveau_oclass *
+struct nvkm_oclass *
gk104_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0xe4),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pmu_ctor,
- .dtor = _nouveau_pmu_dtor,
- .init = _nouveau_pmu_init,
- .fini = _nouveau_pmu_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_pmu_ctor,
+ .dtor = _nvkm_pmu_dtor,
+ .init = _nvkm_pmu_init,
+ .fini = _nvkm_pmu_fini,
},
.code.data = gk104_pmu_code,
.code.size = sizeof(gk104_pmu_code),
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nv108.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c
similarity index 75%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nv108.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c
index a7db0870ed88..6f9c09af1a49 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nv108.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c
@@ -21,21 +21,20 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
-#include "fuc/nv108.fuc5.h"
+#include "fuc/gk208.fuc5.h"
-struct nouveau_oclass *
-nv108_pmu_oclass = &(struct nvkm_pmu_impl) {
+struct nvkm_oclass *
+gk208_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0x00),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pmu_ctor,
- .dtor = _nouveau_pmu_dtor,
- .init = _nouveau_pmu_init,
- .fini = _nouveau_pmu_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_pmu_ctor,
+ .dtor = _nvkm_pmu_dtor,
+ .init = _nvkm_pmu_init,
+ .fini = _nvkm_pmu_fini,
},
- .code.data = nv108_pmu_code,
- .code.size = sizeof(nv108_pmu_code),
- .data.data = nv108_pmu_data,
- .data.size = sizeof(nv108_pmu_data),
+ .code.data = gk208_pmu_code,
+ .code.size = sizeof(gk208_pmu_code),
+ .data.data = gk208_pmu_data,
+ .data.size = sizeof(gk208_pmu_data),
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
index 28d858a875bf..a49934bbe637 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
@@ -36,8 +36,8 @@ struct gk20a_pmu_dvfs_data {
};
struct gk20a_pmu_priv {
- struct nouveau_pmu base;
- struct nouveau_alarm alarm;
+ struct nvkm_pmu base;
+ struct nvkm_alarm alarm;
struct gk20a_pmu_dvfs_data *data;
};
@@ -50,15 +50,15 @@ struct gk20a_pmu_dvfs_dev_status {
static int
gk20a_pmu_dvfs_target(struct gk20a_pmu_priv *priv, int *state)
{
- struct nouveau_clk *clk = nouveau_clk(priv);
+ struct nvkm_clk *clk = nvkm_clk(priv);
- return nouveau_clk_astate(clk, *state, 0, false);
+ return nvkm_clk_astate(clk, *state, 0, false);
}
static int
gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu_priv *priv, int *state)
{
- struct nouveau_clk *clk = nouveau_clk(priv);
+ struct nvkm_clk *clk = nvkm_clk(priv);
*state = clk->pstate;
return 0;
@@ -66,10 +66,10 @@ gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu_priv *priv, int *state)
static int
gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu_priv *priv,
- int *state, int load)
+ int *state, int load)
{
struct gk20a_pmu_dvfs_data *data = priv->data;
- struct nouveau_clk *clk = nouveau_clk(priv);
+ struct nvkm_clk *clk = nvkm_clk(priv);
int cur_level, level;
/* For GK20A, the performance level is directly mapped to pstate */
@@ -96,7 +96,7 @@ gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu_priv *priv,
static int
gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu_priv *priv,
- struct gk20a_pmu_dvfs_dev_status *status)
+ struct gk20a_pmu_dvfs_dev_status *status)
{
status->busy = nv_rd32(priv, 0x10a508 + (BUSY_SLOT * 0x10));
status->total= nv_rd32(priv, 0x10a508 + (CLK_SLOT * 0x10));
@@ -111,14 +111,14 @@ gk20a_pmu_dvfs_reset_dev_status(struct gk20a_pmu_priv *priv)
}
static void
-gk20a_pmu_dvfs_work(struct nouveau_alarm *alarm)
+gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm)
{
- struct gk20a_pmu_priv *priv = container_of(alarm,
- struct gk20a_pmu_priv, alarm);
+ struct gk20a_pmu_priv *priv =
+ container_of(alarm, struct gk20a_pmu_priv, alarm);
struct gk20a_pmu_dvfs_data *data = priv->data;
struct gk20a_pmu_dvfs_dev_status status;
- struct nouveau_clk *clk = nouveau_clk(priv);
- struct nouveau_volt *volt = nouveau_volt(priv);
+ struct nvkm_clk *clk = nvkm_clk(priv);
+ struct nvkm_volt *volt = nvkm_volt(priv);
u32 utilization = 0;
int state, ret;
@@ -156,40 +156,39 @@ gk20a_pmu_dvfs_work(struct nouveau_alarm *alarm)
resched:
gk20a_pmu_dvfs_reset_dev_status(priv);
- nouveau_timer_alarm(priv, 100000000, alarm);
+ nvkm_timer_alarm(priv, 100000000, alarm);
}
int
-gk20a_pmu_fini(struct nouveau_object *object, bool suspend)
+gk20a_pmu_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_pmu *pmu = (void *)object;
+ struct nvkm_pmu *pmu = (void *)object;
struct gk20a_pmu_priv *priv = (void *)pmu;
- nouveau_timer_alarm_cancel(priv, &priv->alarm);
+ nvkm_timer_alarm_cancel(priv, &priv->alarm);
- return nouveau_subdev_fini(&pmu->base, suspend);
+ return nvkm_subdev_fini(&pmu->base, suspend);
}
int
-gk20a_pmu_init(struct nouveau_object *object)
+gk20a_pmu_init(struct nvkm_object *object)
{
- struct nouveau_pmu *pmu = (void *)object;
+ struct nvkm_pmu *pmu = (void *)object;
struct gk20a_pmu_priv *priv = (void *)pmu;
int ret;
- ret = nouveau_subdev_init(&pmu->base);
+ ret = nvkm_subdev_init(&pmu->base);
if (ret)
return ret;
- pmu->pgob = nouveau_pmu_pgob;
+ pmu->pgob = nvkm_pmu_pgob;
/* init pwr perf counter */
nv_wr32(pmu, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001);
nv_wr32(pmu, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002);
nv_wr32(pmu, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
- nouveau_timer_alarm(pmu, 2000000000, &priv->alarm);
-
+ nvkm_timer_alarm(pmu, 2000000000, &priv->alarm);
return ret;
}
@@ -200,32 +199,30 @@ struct gk20a_pmu_dvfs_data gk20a_dvfs_data= {
};
static int
-gk20a_pmu_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk20a_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct gk20a_pmu_priv *priv;
int ret;
- ret = nouveau_pmu_create(parent, engine, oclass, &priv);
+ ret = nvkm_pmu_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->data = &gk20a_dvfs_data;
- nouveau_alarm_init(&priv->alarm, gk20a_pmu_dvfs_work);
-
+ nvkm_alarm_init(&priv->alarm, gk20a_pmu_dvfs_work);
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
gk20a_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0xea),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_pmu_ctor,
- .dtor = _nouveau_pmu_dtor,
+ .dtor = _nvkm_pmu_dtor,
.init = gk20a_pmu_init,
.fini = gk20a_pmu_fini,
},
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
similarity index 72%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
index 06f99283d1a9..30aaeb21de41 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
@@ -21,30 +21,29 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
-#include "fuc/nva3.fuc3.h"
+#include "fuc/gt215.fuc3.h"
static int
-nva3_pmu_init(struct nouveau_object *object)
+gt215_pmu_init(struct nvkm_object *object)
{
- struct nouveau_pmu *pmu = (void *)object;
+ struct nvkm_pmu *pmu = (void *)object;
nv_mask(pmu, 0x022210, 0x00000001, 0x00000000);
nv_mask(pmu, 0x022210, 0x00000001, 0x00000001);
- return nouveau_pmu_init(pmu);
+ return nvkm_pmu_init(pmu);
}
-struct nouveau_oclass *
-nva3_pmu_oclass = &(struct nvkm_pmu_impl) {
+struct nvkm_oclass *
+gt215_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0xa3),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_pmu_ctor,
- .dtor = _nouveau_pmu_dtor,
- .init = nva3_pmu_init,
- .fini = _nouveau_pmu_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_pmu_ctor,
+ .dtor = _nvkm_pmu_dtor,
+ .init = gt215_pmu_init,
+ .fini = _nvkm_pmu_fini,
},
- .code.data = nva3_pmu_code,
- .code.size = sizeof(nva3_pmu_code),
- .data.data = nva3_pmu_data,
- .data.size = sizeof(nva3_pmu_data),
+ .code.data = gt215_pmu_code,
+ .code.size = sizeof(gt215_pmu_code),
+ .data.data = gt215_pmu_data,
+ .data.size = sizeof(gt215_pmu_data),
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
index 671c7177d3af..b75c5b885980 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
@@ -1,10 +1,11 @@
#ifndef __NVKM_PMU_MEMX_H__
#define __NVKM_PMU_MEMX_H__
-
#include "priv.h"
-struct nouveau_memx {
- struct nouveau_pmu *pmu;
+#include <core/device.h>
+
+struct nvkm_memx {
+ struct nvkm_pmu *pmu;
u32 base;
u32 size;
struct {
@@ -15,9 +16,9 @@ struct nouveau_memx {
};
static void
-memx_out(struct nouveau_memx *memx)
+memx_out(struct nvkm_memx *memx)
{
- struct nouveau_pmu *pmu = memx->pmu;
+ struct nvkm_pmu *pmu = memx->pmu;
int i;
if (memx->c.mthd) {
@@ -30,7 +31,7 @@ memx_out(struct nouveau_memx *memx)
}
static void
-memx_cmd(struct nouveau_memx *memx, u32 mthd, u32 size, u32 data[])
+memx_cmd(struct nvkm_memx *memx, u32 mthd, u32 size, u32 data[])
{
if ((memx->c.size + size >= ARRAY_SIZE(memx->c.data)) ||
(memx->c.mthd && memx->c.mthd != mthd))
@@ -41,14 +42,14 @@ memx_cmd(struct nouveau_memx *memx, u32 mthd, u32 size, u32 data[])
}
int
-nouveau_memx_init(struct nouveau_pmu *pmu, struct nouveau_memx **pmemx)
+nvkm_memx_init(struct nvkm_pmu *pmu, struct nvkm_memx **pmemx)
{
- struct nouveau_memx *memx;
+ struct nvkm_memx *memx;
u32 reply[2];
int ret;
ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
- MEMX_INFO_DATA, 0);
+ MEMX_INFO_DATA, 0);
if (ret)
return ret;
@@ -64,15 +65,14 @@ nouveau_memx_init(struct nouveau_pmu *pmu, struct nouveau_memx **pmemx)
nv_wr32(pmu, 0x10a580, 0x00000003);
} while (nv_rd32(pmu, 0x10a580) != 0x00000003);
nv_wr32(pmu, 0x10a1c0, 0x01000000 | memx->base);
-
return 0;
}
int
-nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec)
+nvkm_memx_fini(struct nvkm_memx **pmemx, bool exec)
{
- struct nouveau_memx *memx = *pmemx;
- struct nouveau_pmu *pmu = memx->pmu;
+ struct nvkm_memx *memx = *pmemx;
+ struct nvkm_pmu *pmu = memx->pmu;
u32 finish, reply[2];
/* flush the cache... */
@@ -85,7 +85,7 @@ nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec)
/* call MEMX process to execute the script, and wait for reply */
if (exec) {
pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_EXEC,
- memx->base, finish);
+ memx->base, finish);
}
nv_debug(memx->pmu, "Exec took %uns, PMU_IN %08x\n",
@@ -95,14 +95,14 @@ nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec)
}
void
-nouveau_memx_wr32(struct nouveau_memx *memx, u32 addr, u32 data)
+nvkm_memx_wr32(struct nvkm_memx *memx, u32 addr, u32 data)
{
nv_debug(memx->pmu, "R[%06x] = 0x%08x\n", addr, data);
memx_cmd(memx, MEMX_WR32, 2, (u32[]){ addr, data });
}
void
-nouveau_memx_wait(struct nouveau_memx *memx,
+nvkm_memx_wait(struct nvkm_memx *memx,
u32 addr, u32 mask, u32 data, u32 nsec)
{
nv_debug(memx->pmu, "R[%06x] & 0x%08x == 0x%08x, %d us\n",
@@ -112,7 +112,7 @@ nouveau_memx_wait(struct nouveau_memx *memx,
}
void
-nouveau_memx_nsec(struct nouveau_memx *memx, u32 nsec)
+nvkm_memx_nsec(struct nvkm_memx *memx, u32 nsec)
{
nv_debug(memx->pmu, " DELAY = %d ns\n", nsec);
memx_cmd(memx, MEMX_DELAY, 1, (u32[]){ nsec });
@@ -120,9 +120,9 @@ nouveau_memx_nsec(struct nouveau_memx *memx, u32 nsec)
}
void
-nouveau_memx_wait_vblank(struct nouveau_memx *memx)
+nvkm_memx_wait_vblank(struct nvkm_memx *memx)
{
- struct nouveau_pmu *pmu = memx->pmu;
+ struct nvkm_pmu *pmu = memx->pmu;
u32 heads, x, y, px = 0;
int i, head_sync;
@@ -153,20 +153,20 @@ nouveau_memx_wait_vblank(struct nouveau_memx *memx)
}
void
-nouveau_memx_train(struct nouveau_memx *memx)
+nvkm_memx_train(struct nvkm_memx *memx)
{
nv_debug(memx->pmu, " MEM TRAIN\n");
memx_cmd(memx, MEMX_TRAIN, 0, NULL);
}
int
-nouveau_memx_train_result(struct nouveau_pmu *pmu, u32 *res, int rsize)
+nvkm_memx_train_result(struct nvkm_pmu *pmu, u32 *res, int rsize)
{
u32 reply[2], base, size, i;
int ret;
ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
- MEMX_INFO_TRAIN, 0);
+ MEMX_INFO_TRAIN, 0);
if (ret)
return ret;
@@ -185,17 +185,16 @@ nouveau_memx_train_result(struct nouveau_pmu *pmu, u32 *res, int rsize)
}
void
-nouveau_memx_block(struct nouveau_memx *memx)
+nvkm_memx_block(struct nvkm_memx *memx)
{
nv_debug(memx->pmu, " HOST BLOCKED\n");
memx_cmd(memx, MEMX_ENTER, 0, NULL);
}
void
-nouveau_memx_unblock(struct nouveau_memx *memx)
+nvkm_memx_unblock(struct nvkm_memx *memx)
{
nv_debug(memx->pmu, " HOST UNBLOCKED\n");
memx_cmd(memx, MEMX_LEAVE, 0, NULL);
}
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h
index eb5bd1cb3955..998410563bfd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h
@@ -1,35 +1,34 @@
#ifndef __NVKM_PMU_PRIV_H__
#define __NVKM_PMU_PRIV_H__
-
#include <subdev/pmu.h>
#include <subdev/pmu/fuc/os.h>
-#define nouveau_pmu_create(p, e, o, d) \
- nouveau_pmu_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_pmu_destroy(p) \
- nouveau_subdev_destroy(&(p)->base)
-#define nouveau_pmu_init(p) ({ \
- struct nouveau_pmu *_pmu = (p); \
- _nouveau_pmu_init(nv_object(_pmu)); \
+#define nvkm_pmu_create(p, e, o, d) \
+ nvkm_pmu_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_pmu_destroy(p) \
+ nvkm_subdev_destroy(&(p)->base)
+#define nvkm_pmu_init(p) ({ \
+ struct nvkm_pmu *_pmu = (p); \
+ _nvkm_pmu_init(nv_object(_pmu)); \
})
-#define nouveau_pmu_fini(p,s) ({ \
- struct nouveau_pmu *_pmu = (p); \
- _nouveau_pmu_fini(nv_object(_pmu), (s)); \
+#define nvkm_pmu_fini(p,s) ({ \
+ struct nvkm_pmu *_pmu = (p); \
+ _nvkm_pmu_fini(nv_object(_pmu), (s)); \
})
-int nouveau_pmu_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
+int nvkm_pmu_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
-int _nouveau_pmu_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-#define _nouveau_pmu_dtor _nouveau_subdev_dtor
-int _nouveau_pmu_init(struct nouveau_object *);
-int _nouveau_pmu_fini(struct nouveau_object *, bool);
-void nouveau_pmu_pgob(struct nouveau_pmu *pmu, bool enable);
+int _nvkm_pmu_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+#define _nvkm_pmu_dtor _nvkm_subdev_dtor
+int _nvkm_pmu_init(struct nvkm_object *);
+int _nvkm_pmu_fini(struct nvkm_object *, bool);
+void nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable);
struct nvkm_pmu_impl {
- struct nouveau_oclass base;
+ struct nvkm_oclass base;
struct {
u32 *data;
u32 size;
@@ -39,7 +38,6 @@ struct nvkm_pmu_impl {
u32 size;
} data;
- void (*pgob)(struct nouveau_pmu *, bool);
+ void (*pgob)(struct nvkm_pmu *, bool);
};
-
#endif
From e1404611d5f6a7c75e2b745f5eb7fbcdd23751c5 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:11:48 +1000
Subject: [PATCH 67/86] drm/nouveau/therm: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/subdev/therm.h | 116 +++++------
drivers/gpu/drm/nouveau/nouveau_hwmon.c | 44 ++--
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 26 +--
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 +-
.../gpu/drm/nouveau/nvkm/subdev/therm/Kbuild | 6 +-
.../gpu/drm/nouveau/nvkm/subdev/therm/base.c | 195 +++++++++---------
.../gpu/drm/nouveau/nvkm/subdev/therm/fan.c | 89 ++++----
.../drm/nouveau/nvkm/subdev/therm/fannil.c | 15 +-
.../drm/nouveau/nvkm/subdev/therm/fanpwm.c | 45 ++--
.../drm/nouveau/nvkm/subdev/therm/fantog.c | 52 +++--
.../nvkm/subdev/therm/{nv84.c => g84.c} | 142 +++++++------
.../nvkm/subdev/therm/{nvd0.c => gf110.c} | 64 +++---
.../gpu/drm/nouveau/nvkm/subdev/therm/gm107.c | 38 ++--
.../nvkm/subdev/therm/{nva3.c => gt215.c} | 50 +++--
.../gpu/drm/nouveau/nvkm/subdev/therm/ic.c | 22 +-
.../gpu/drm/nouveau/nvkm/subdev/therm/nv40.c | 51 +++--
.../gpu/drm/nouveau/nvkm/subdev/therm/nv50.c | 47 +++--
.../gpu/drm/nouveau/nvkm/subdev/therm/priv.h | 137 ++++++------
.../gpu/drm/nouveau/nvkm/subdev/therm/temp.c | 139 ++++++-------
20 files changed, 632 insertions(+), 678 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/subdev/therm/{nv84.c => g84.c} (60%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/therm/{nvd0.c => gf110.c} (70%)
rename drivers/gpu/drm/nouveau/nvkm/subdev/therm/{nva3.c => gt215.c} (69%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
index 42f9574a06c9..6662829b6db1 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
@@ -1,83 +1,79 @@
-#ifndef __NOUVEAU_THERM_H__
-#define __NOUVEAU_THERM_H__
-
-#include <core/device.h>
+#ifndef __NVKM_THERM_H__
+#define __NVKM_THERM_H__
#include <core/subdev.h>
-enum nouveau_therm_fan_mode {
- NOUVEAU_THERM_CTRL_NONE = 0,
- NOUVEAU_THERM_CTRL_MANUAL = 1,
- NOUVEAU_THERM_CTRL_AUTO = 2,
+enum nvkm_therm_fan_mode {
+ NVKM_THERM_CTRL_NONE = 0,
+ NVKM_THERM_CTRL_MANUAL = 1,
+ NVKM_THERM_CTRL_AUTO = 2,
};
-enum nouveau_therm_attr_type {
- NOUVEAU_THERM_ATTR_FAN_MIN_DUTY = 0,
- NOUVEAU_THERM_ATTR_FAN_MAX_DUTY = 1,
- NOUVEAU_THERM_ATTR_FAN_MODE = 2,
+enum nvkm_therm_attr_type {
+ NVKM_THERM_ATTR_FAN_MIN_DUTY = 0,
+ NVKM_THERM_ATTR_FAN_MAX_DUTY = 1,
+ NVKM_THERM_ATTR_FAN_MODE = 2,
- NOUVEAU_THERM_ATTR_THRS_FAN_BOOST = 10,
- NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST = 11,
- NOUVEAU_THERM_ATTR_THRS_DOWN_CLK = 12,
- NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST = 13,
- NOUVEAU_THERM_ATTR_THRS_CRITICAL = 14,
- NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST = 15,
- NOUVEAU_THERM_ATTR_THRS_SHUTDOWN = 16,
- NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST = 17,
+ NVKM_THERM_ATTR_THRS_FAN_BOOST = 10,
+ NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST = 11,
+ NVKM_THERM_ATTR_THRS_DOWN_CLK = 12,
+ NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST = 13,
+ NVKM_THERM_ATTR_THRS_CRITICAL = 14,
+ NVKM_THERM_ATTR_THRS_CRITICAL_HYST = 15,
+ NVKM_THERM_ATTR_THRS_SHUTDOWN = 16,
+ NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST = 17,
};
-struct nouveau_therm {
- struct nouveau_subdev base;
+struct nvkm_therm {
+ struct nvkm_subdev base;
- int (*pwm_ctrl)(struct nouveau_therm *, int line, bool);
- int (*pwm_get)(struct nouveau_therm *, int line, u32 *, u32 *);
- int (*pwm_set)(struct nouveau_therm *, int line, u32, u32);
- int (*pwm_clock)(struct nouveau_therm *, int line);
+ int (*pwm_ctrl)(struct nvkm_therm *, int line, bool);
+ int (*pwm_get)(struct nvkm_therm *, int line, u32 *, u32 *);
+ int (*pwm_set)(struct nvkm_therm *, int line, u32, u32);
+ int (*pwm_clock)(struct nvkm_therm *, int line);
- int (*fan_get)(struct nouveau_therm *);
- int (*fan_set)(struct nouveau_therm *, int);
- int (*fan_sense)(struct nouveau_therm *);
+ int (*fan_get)(struct nvkm_therm *);
+ int (*fan_set)(struct nvkm_therm *, int);
+ int (*fan_sense)(struct nvkm_therm *);
- int (*temp_get)(struct nouveau_therm *);
+ int (*temp_get)(struct nvkm_therm *);
- int (*attr_get)(struct nouveau_therm *, enum nouveau_therm_attr_type);
- int (*attr_set)(struct nouveau_therm *,
- enum nouveau_therm_attr_type, int);
+ int (*attr_get)(struct nvkm_therm *, enum nvkm_therm_attr_type);
+ int (*attr_set)(struct nvkm_therm *, enum nvkm_therm_attr_type, int);
};
-static inline struct nouveau_therm *
-nouveau_therm(void *obj)
+static inline struct nvkm_therm *
+nvkm_therm(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_THERM);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_THERM);
}
-#define nouveau_therm_create(p,e,o,d) \
- nouveau_therm_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_therm_destroy(p) ({ \
- struct nouveau_therm *therm = (p); \
- _nouveau_therm_dtor(nv_object(therm)); \
+#define nvkm_therm_create(p,e,o,d) \
+ nvkm_therm_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_therm_destroy(p) ({ \
+ struct nvkm_therm *therm = (p); \
+ _nvkm_therm_dtor(nv_object(therm)); \
})
-#define nouveau_therm_init(p) ({ \
- struct nouveau_therm *therm = (p); \
- _nouveau_therm_init(nv_object(therm)); \
+#define nvkm_therm_init(p) ({ \
+ struct nvkm_therm *therm = (p); \
+ _nvkm_therm_init(nv_object(therm)); \
})
-#define nouveau_therm_fini(p,s) ({ \
- struct nouveau_therm *therm = (p); \
- _nouveau_therm_init(nv_object(therm), (s)); \
+#define nvkm_therm_fini(p,s) ({ \
+ struct nvkm_therm *therm = (p); \
+ _nvkm_therm_init(nv_object(therm), (s)); \
})
-int nouveau_therm_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-void _nouveau_therm_dtor(struct nouveau_object *);
-int _nouveau_therm_init(struct nouveau_object *);
-int _nouveau_therm_fini(struct nouveau_object *, bool);
+int nvkm_therm_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+void _nvkm_therm_dtor(struct nvkm_object *);
+int _nvkm_therm_init(struct nvkm_object *);
+int _nvkm_therm_fini(struct nvkm_object *, bool);
-int nouveau_therm_cstate(struct nouveau_therm *, int, int);
-
-extern struct nouveau_oclass nv40_therm_oclass;
-extern struct nouveau_oclass nv50_therm_oclass;
-extern struct nouveau_oclass nv84_therm_oclass;
-extern struct nouveau_oclass nva3_therm_oclass;
-extern struct nouveau_oclass nvd0_therm_oclass;
-extern struct nouveau_oclass gm107_therm_oclass;
+int nvkm_therm_cstate(struct nvkm_therm *, int, int);
+extern struct nvkm_oclass nv40_therm_oclass;
+extern struct nvkm_oclass nv50_therm_oclass;
+extern struct nvkm_oclass g84_therm_oclass;
+extern struct nvkm_oclass gt215_therm_oclass;
+extern struct nvkm_oclass gf110_therm_oclass;
+extern struct nvkm_oclass gm107_therm_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c b/drivers/gpu/drm/nouveau/nouveau_hwmon.c
index e63c15112f2e..b5c445e02bfc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_hwmon.c
@@ -69,7 +69,7 @@ nouveau_hwmon_temp1_auto_point1_temp(struct device *d,
struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST) * 1000);
+ therm->attr_get(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST) * 1000);
}
static ssize_t
nouveau_hwmon_set_temp1_auto_point1_temp(struct device *d,
@@ -84,7 +84,7 @@ nouveau_hwmon_set_temp1_auto_point1_temp(struct device *d,
if (kstrtol(buf, 10, &value) == -EINVAL)
return count;
- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST,
+ therm->attr_set(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST,
value / 1000);
return count;
@@ -102,7 +102,7 @@ nouveau_hwmon_temp1_auto_point1_temp_hyst(struct device *d,
struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST) * 1000);
+ therm->attr_get(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST) * 1000);
}
static ssize_t
nouveau_hwmon_set_temp1_auto_point1_temp_hyst(struct device *d,
@@ -117,7 +117,7 @@ nouveau_hwmon_set_temp1_auto_point1_temp_hyst(struct device *d,
if (kstrtol(buf, 10, &value) == -EINVAL)
return count;
- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST,
+ therm->attr_set(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST,
value / 1000);
return count;
@@ -134,7 +134,7 @@ nouveau_hwmon_max_temp(struct device *d, struct device_attribute *a, char *buf)
struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK) * 1000);
+ therm->attr_get(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK) * 1000);
}
static ssize_t
nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a,
@@ -148,7 +148,7 @@ nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a,
if (kstrtol(buf, 10, &value) == -EINVAL)
return count;
- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK, value / 1000);
+ therm->attr_set(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK, value / 1000);
return count;
}
@@ -165,7 +165,7 @@ nouveau_hwmon_max_temp_hyst(struct device *d, struct device_attribute *a,
struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST) * 1000);
+ therm->attr_get(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST) * 1000);
}
static ssize_t
nouveau_hwmon_set_max_temp_hyst(struct device *d, struct device_attribute *a,
@@ -179,7 +179,7 @@ nouveau_hwmon_set_max_temp_hyst(struct device *d, struct device_attribute *a,
if (kstrtol(buf, 10, &value) == -EINVAL)
return count;
- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST,
+ therm->attr_set(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST,
value / 1000);
return count;
@@ -197,7 +197,7 @@ nouveau_hwmon_critical_temp(struct device *d, struct device_attribute *a,
struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL) * 1000);
+ therm->attr_get(therm, NVKM_THERM_ATTR_THRS_CRITICAL) * 1000);
}
static ssize_t
nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a,
@@ -212,7 +212,7 @@ nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a,
if (kstrtol(buf, 10, &value) == -EINVAL)
return count;
- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL, value / 1000);
+ therm->attr_set(therm, NVKM_THERM_ATTR_THRS_CRITICAL, value / 1000);
return count;
}
@@ -230,7 +230,7 @@ nouveau_hwmon_critical_temp_hyst(struct device *d, struct device_attribute *a,
struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST) * 1000);
+ therm->attr_get(therm, NVKM_THERM_ATTR_THRS_CRITICAL_HYST) * 1000);
}
static ssize_t
nouveau_hwmon_set_critical_temp_hyst(struct device *d,
@@ -246,7 +246,7 @@ nouveau_hwmon_set_critical_temp_hyst(struct device *d,
if (kstrtol(buf, 10, &value) == -EINVAL)
return count;
- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST,
+ therm->attr_set(therm, NVKM_THERM_ATTR_THRS_CRITICAL_HYST,
value / 1000);
return count;
@@ -263,7 +263,7 @@ nouveau_hwmon_emergency_temp(struct device *d, struct device_attribute *a,
struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN) * 1000);
+ therm->attr_get(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN) * 1000);
}
static ssize_t
nouveau_hwmon_set_emergency_temp(struct device *d, struct device_attribute *a,
@@ -278,7 +278,7 @@ nouveau_hwmon_set_emergency_temp(struct device *d, struct device_attribute *a,
if (kstrtol(buf, 10, &value) == -EINVAL)
return count;
- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN, value / 1000);
+ therm->attr_set(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN, value / 1000);
return count;
}
@@ -296,7 +296,7 @@ nouveau_hwmon_emergency_temp_hyst(struct device *d, struct device_attribute *a,
struct nouveau_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST) * 1000);
+ therm->attr_get(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST) * 1000);
}
static ssize_t
nouveau_hwmon_set_emergency_temp_hyst(struct device *d,
@@ -312,7 +312,7 @@ nouveau_hwmon_set_emergency_temp_hyst(struct device *d,
if (kstrtol(buf, 10, &value) == -EINVAL)
return count;
- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST,
+ therm->attr_set(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST,
value / 1000);
return count;
@@ -362,7 +362,7 @@ nouveau_hwmon_get_pwm1_enable(struct device *d,
struct nouveau_therm *therm = nvxx_therm(&drm->device);
int ret;
- ret = therm->attr_get(therm, NOUVEAU_THERM_ATTR_FAN_MODE);
+ ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MODE);
if (ret < 0)
return ret;
@@ -383,7 +383,7 @@ nouveau_hwmon_set_pwm1_enable(struct device *d, struct device_attribute *a,
if (ret)
return ret;
- ret = therm->attr_set(therm, NOUVEAU_THERM_ATTR_FAN_MODE, value);
+ ret = therm->attr_set(therm, NVKM_THERM_ATTR_FAN_MODE, value);
if (ret)
return ret;
else
@@ -441,7 +441,7 @@ nouveau_hwmon_get_pwm1_min(struct device *d,
struct nouveau_therm *therm = nvxx_therm(&drm->device);
int ret;
- ret = therm->attr_get(therm, NOUVEAU_THERM_ATTR_FAN_MIN_DUTY);
+ ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MIN_DUTY);
if (ret < 0)
return ret;
@@ -461,7 +461,7 @@ nouveau_hwmon_set_pwm1_min(struct device *d, struct device_attribute *a,
if (kstrtol(buf, 10, &value) == -EINVAL)
return -EINVAL;
- ret = therm->attr_set(therm, NOUVEAU_THERM_ATTR_FAN_MIN_DUTY, value);
+ ret = therm->attr_set(therm, NVKM_THERM_ATTR_FAN_MIN_DUTY, value);
if (ret < 0)
return ret;
@@ -481,7 +481,7 @@ nouveau_hwmon_get_pwm1_max(struct device *d,
struct nouveau_therm *therm = nvxx_therm(&drm->device);
int ret;
- ret = therm->attr_get(therm, NOUVEAU_THERM_ATTR_FAN_MAX_DUTY);
+ ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MAX_DUTY);
if (ret < 0)
return ret;
@@ -501,7 +501,7 @@ nouveau_hwmon_set_pwm1_max(struct device *d, struct device_attribute *a,
if (kstrtol(buf, 10, &value) == -EINVAL)
return -EINVAL;
- ret = therm->attr_set(therm, NOUVEAU_THERM_ATTR_FAN_MAX_DUTY, value);
+ ret = therm->attr_set(therm, NVKM_THERM_ATTR_FAN_MAX_DUTY, value);
if (ret < 0)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 9394962e6c7f..f1f041fdb080 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -94,7 +94,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
@@ -123,7 +123,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
@@ -152,7 +152,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
@@ -181,7 +181,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
@@ -210,7 +210,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
@@ -239,7 +239,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@@ -268,7 +268,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@@ -297,7 +297,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@@ -326,7 +326,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@@ -355,7 +355,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@@ -386,7 +386,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@@ -416,7 +416,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@@ -446,7 +446,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = >215_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 90f3fcc47c55..a4859a541aea 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -66,7 +66,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
@@ -99,7 +99,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
@@ -132,7 +132,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@@ -164,7 +164,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
@@ -197,7 +197,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@@ -229,7 +229,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@@ -261,7 +261,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
@@ -294,7 +294,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@@ -326,7 +326,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 6b6e54828efb..962a810d2b83 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -66,7 +66,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@@ -100,7 +100,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@@ -134,7 +134,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@@ -190,7 +190,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@@ -224,7 +224,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@@ -258,7 +258,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
@@ -291,7 +291,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
+ device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild
index 9ac82070944a..5837cf1292d9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild
@@ -7,7 +7,7 @@ nvkm-y += nvkm/subdev/therm/ic.o
nvkm-y += nvkm/subdev/therm/temp.o
nvkm-y += nvkm/subdev/therm/nv40.o
nvkm-y += nvkm/subdev/therm/nv50.o
-nvkm-y += nvkm/subdev/therm/nv84.o
-nvkm-y += nvkm/subdev/therm/nva3.o
-nvkm-y += nvkm/subdev/therm/nvd0.o
+nvkm-y += nvkm/subdev/therm/g84.o
+nvkm-y += nvkm/subdev/therm/gt215.o
+nvkm-y += nvkm/subdev/therm/gf110.o
nvkm-y += nvkm/subdev/therm/gm107.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
index 67ad8ea468a9..ec327cb64a0d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
@@ -21,18 +21,14 @@
*
* Authors: Martin Peres
*/
-
-#include <core/object.h>
-#include <core/device.h>
-
-#include <subdev/bios.h>
-
#include "priv.h"
+#include <core/device.h>
+
static int
-nouveau_therm_update_trip(struct nouveau_therm *therm)
+nvkm_therm_update_trip(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
struct nvbios_therm_trip_point *trip = priv->fan->bios.trip,
*cur_trip = NULL,
*last_trip = priv->last_trip;
@@ -63,9 +59,9 @@ nouveau_therm_update_trip(struct nouveau_therm *therm)
}
static int
-nouveau_therm_update_linear(struct nouveau_therm *therm)
+nvkm_therm_update_linear(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
u8 linear_min_temp = priv->fan->bios.linear_min_temp;
u8 linear_max_temp = priv->fan->bios.linear_max_temp;
u8 temp = therm->temp_get(therm);
@@ -82,15 +78,14 @@ nouveau_therm_update_linear(struct nouveau_therm *therm)
duty *= (priv->fan->bios.max_duty - priv->fan->bios.min_duty);
duty /= (linear_max_temp - linear_min_temp);
duty += priv->fan->bios.min_duty;
-
return duty;
}
static void
-nouveau_therm_update(struct nouveau_therm *therm, int mode)
+nvkm_therm_update(struct nvkm_therm *therm, int mode)
{
- struct nouveau_timer *ptimer = nouveau_timer(therm);
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_timer *ptimer = nvkm_timer(therm);
+ struct nvkm_therm_priv *priv = (void *)therm;
unsigned long flags;
bool immd = true;
bool poll = true;
@@ -102,20 +97,20 @@ nouveau_therm_update(struct nouveau_therm *therm, int mode)
priv->mode = mode;
switch (mode) {
- case NOUVEAU_THERM_CTRL_MANUAL:
+ case NVKM_THERM_CTRL_MANUAL:
ptimer->alarm_cancel(ptimer, &priv->alarm);
- duty = nouveau_therm_fan_get(therm);
+ duty = nvkm_therm_fan_get(therm);
if (duty < 0)
duty = 100;
poll = false;
break;
- case NOUVEAU_THERM_CTRL_AUTO:
+ case NVKM_THERM_CTRL_AUTO:
switch(priv->fan->bios.fan_mode) {
case NVBIOS_THERM_FAN_TRIP:
- duty = nouveau_therm_update_trip(therm);
+ duty = nvkm_therm_update_trip(therm);
break;
case NVBIOS_THERM_FAN_LINEAR:
- duty = nouveau_therm_update_linear(therm);
+ duty = nvkm_therm_update_linear(therm);
break;
case NVBIOS_THERM_FAN_OTHER:
if (priv->cstate)
@@ -125,7 +120,7 @@ nouveau_therm_update(struct nouveau_therm *therm, int mode)
}
immd = false;
break;
- case NOUVEAU_THERM_CTRL_NONE:
+ case NVKM_THERM_CTRL_NONE:
default:
ptimer->alarm_cancel(ptimer, &priv->alarm);
poll = false;
@@ -137,36 +132,36 @@ nouveau_therm_update(struct nouveau_therm *therm, int mode)
if (duty >= 0) {
nv_debug(therm, "FAN target request: %d%%\n", duty);
- nouveau_therm_fan_set(therm, immd, duty);
+ nvkm_therm_fan_set(therm, immd, duty);
}
}
int
-nouveau_therm_cstate(struct nouveau_therm *ptherm, int fan, int dir)
+nvkm_therm_cstate(struct nvkm_therm *ptherm, int fan, int dir)
{
- struct nouveau_therm_priv *priv = (void *)ptherm;
+ struct nvkm_therm_priv *priv = (void *)ptherm;
if (!dir || (dir < 0 && fan < priv->cstate) ||
(dir > 0 && fan > priv->cstate)) {
nv_debug(ptherm, "default fan speed -> %d%%\n", fan);
priv->cstate = fan;
- nouveau_therm_update(ptherm, -1);
+ nvkm_therm_update(ptherm, -1);
}
return 0;
}
static void
-nouveau_therm_alarm(struct nouveau_alarm *alarm)
+nvkm_therm_alarm(struct nvkm_alarm *alarm)
{
- struct nouveau_therm_priv *priv =
- container_of(alarm, struct nouveau_therm_priv, alarm);
- nouveau_therm_update(&priv->base, -1);
+ struct nvkm_therm_priv *priv =
+ container_of(alarm, struct nvkm_therm_priv, alarm);
+ nvkm_therm_update(&priv->base, -1);
}
int
-nouveau_therm_fan_mode(struct nouveau_therm *therm, int mode)
+nvkm_therm_fan_mode(struct nvkm_therm *therm, int mode)
{
- struct nouveau_therm_priv *priv = (void *)therm;
- struct nouveau_device *device = nv_device(therm);
+ struct nvkm_therm_priv *priv = (void *)therm;
+ struct nvkm_device *device = nv_device(therm);
static const char *name[] = {
"disabled",
"manual",
@@ -175,51 +170,51 @@ nouveau_therm_fan_mode(struct nouveau_therm *therm, int mode)
/* The default PPWR ucode on fermi interferes with fan management */
if ((mode >= ARRAY_SIZE(name)) ||
- (mode != NOUVEAU_THERM_CTRL_NONE && device->card_type >= NV_C0 &&
- !nouveau_subdev(device, NVDEV_SUBDEV_PMU)))
+ (mode != NVKM_THERM_CTRL_NONE && device->card_type >= NV_C0 &&
+ !nvkm_subdev(device, NVDEV_SUBDEV_PMU)))
return -EINVAL;
/* do not allow automatic fan management if the thermal sensor is
* not available */
- if (mode == NOUVEAU_THERM_CTRL_AUTO && therm->temp_get(therm) < 0)
+ if (mode == NVKM_THERM_CTRL_AUTO && therm->temp_get(therm) < 0)
return -EINVAL;
if (priv->mode == mode)
return 0;
nv_info(therm, "fan management: %s\n", name[mode]);
- nouveau_therm_update(therm, mode);
+ nvkm_therm_update(therm, mode);
return 0;
}
int
-nouveau_therm_attr_get(struct nouveau_therm *therm,
- enum nouveau_therm_attr_type type)
+nvkm_therm_attr_get(struct nvkm_therm *therm,
+ enum nvkm_therm_attr_type type)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
switch (type) {
- case NOUVEAU_THERM_ATTR_FAN_MIN_DUTY:
+ case NVKM_THERM_ATTR_FAN_MIN_DUTY:
return priv->fan->bios.min_duty;
- case NOUVEAU_THERM_ATTR_FAN_MAX_DUTY:
+ case NVKM_THERM_ATTR_FAN_MAX_DUTY:
return priv->fan->bios.max_duty;
- case NOUVEAU_THERM_ATTR_FAN_MODE:
+ case NVKM_THERM_ATTR_FAN_MODE:
return priv->mode;
- case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST:
+ case NVKM_THERM_ATTR_THRS_FAN_BOOST:
return priv->bios_sensor.thrs_fan_boost.temp;
- case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST:
+ case NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST:
return priv->bios_sensor.thrs_fan_boost.hysteresis;
- case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK:
+ case NVKM_THERM_ATTR_THRS_DOWN_CLK:
return priv->bios_sensor.thrs_down_clock.temp;
- case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST:
+ case NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST:
return priv->bios_sensor.thrs_down_clock.hysteresis;
- case NOUVEAU_THERM_ATTR_THRS_CRITICAL:
+ case NVKM_THERM_ATTR_THRS_CRITICAL:
return priv->bios_sensor.thrs_critical.temp;
- case NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST:
+ case NVKM_THERM_ATTR_THRS_CRITICAL_HYST:
return priv->bios_sensor.thrs_critical.hysteresis;
- case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN:
+ case NVKM_THERM_ATTR_THRS_SHUTDOWN:
return priv->bios_sensor.thrs_shutdown.temp;
- case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST:
+ case NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST:
return priv->bios_sensor.thrs_shutdown.hysteresis;
}
@@ -227,57 +222,57 @@ nouveau_therm_attr_get(struct nouveau_therm *therm,
}
int
-nouveau_therm_attr_set(struct nouveau_therm *therm,
- enum nouveau_therm_attr_type type, int value)
+nvkm_therm_attr_set(struct nvkm_therm *therm,
+ enum nvkm_therm_attr_type type, int value)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
switch (type) {
- case NOUVEAU_THERM_ATTR_FAN_MIN_DUTY:
+ case NVKM_THERM_ATTR_FAN_MIN_DUTY:
if (value < 0)
value = 0;
if (value > priv->fan->bios.max_duty)
value = priv->fan->bios.max_duty;
priv->fan->bios.min_duty = value;
return 0;
- case NOUVEAU_THERM_ATTR_FAN_MAX_DUTY:
+ case NVKM_THERM_ATTR_FAN_MAX_DUTY:
if (value < 0)
value = 0;
if (value < priv->fan->bios.min_duty)
value = priv->fan->bios.min_duty;
priv->fan->bios.max_duty = value;
return 0;
- case NOUVEAU_THERM_ATTR_FAN_MODE:
- return nouveau_therm_fan_mode(therm, value);
- case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST:
+ case NVKM_THERM_ATTR_FAN_MODE:
+ return nvkm_therm_fan_mode(therm, value);
+ case NVKM_THERM_ATTR_THRS_FAN_BOOST:
priv->bios_sensor.thrs_fan_boost.temp = value;
priv->sensor.program_alarms(therm);
return 0;
- case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST:
+ case NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST:
priv->bios_sensor.thrs_fan_boost.hysteresis = value;
priv->sensor.program_alarms(therm);
return 0;
- case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK:
+ case NVKM_THERM_ATTR_THRS_DOWN_CLK:
priv->bios_sensor.thrs_down_clock.temp = value;
priv->sensor.program_alarms(therm);
return 0;
- case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST:
+ case NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST:
priv->bios_sensor.thrs_down_clock.hysteresis = value;
priv->sensor.program_alarms(therm);
return 0;
- case NOUVEAU_THERM_ATTR_THRS_CRITICAL:
+ case NVKM_THERM_ATTR_THRS_CRITICAL:
priv->bios_sensor.thrs_critical.temp = value;
priv->sensor.program_alarms(therm);
return 0;
- case NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST:
+ case NVKM_THERM_ATTR_THRS_CRITICAL_HYST:
priv->bios_sensor.thrs_critical.hysteresis = value;
priv->sensor.program_alarms(therm);
return 0;
- case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN:
+ case NVKM_THERM_ATTR_THRS_SHUTDOWN:
priv->bios_sensor.thrs_shutdown.temp = value;
priv->sensor.program_alarms(therm);
return 0;
- case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST:
+ case NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST:
priv->bios_sensor.thrs_shutdown.hysteresis = value;
priv->sensor.program_alarms(therm);
return 0;
@@ -287,88 +282,86 @@ nouveau_therm_attr_set(struct nouveau_therm *therm,
}
int
-_nouveau_therm_init(struct nouveau_object *object)
+_nvkm_therm_init(struct nvkm_object *object)
{
- struct nouveau_therm *therm = (void *)object;
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm *therm = (void *)object;
+ struct nvkm_therm_priv *priv = (void *)therm;
int ret;
- ret = nouveau_subdev_init(&therm->base);
+ ret = nvkm_subdev_init(&therm->base);
if (ret)
return ret;
if (priv->suspend >= 0) {
/* restore the pwm value only when on manual or auto mode */
if (priv->suspend > 0)
- nouveau_therm_fan_set(therm, true, priv->fan->percent);
+ nvkm_therm_fan_set(therm, true, priv->fan->percent);
- nouveau_therm_fan_mode(therm, priv->suspend);
+ nvkm_therm_fan_mode(therm, priv->suspend);
}
- nouveau_therm_sensor_init(therm);
- nouveau_therm_fan_init(therm);
+ nvkm_therm_sensor_init(therm);
+ nvkm_therm_fan_init(therm);
return 0;
}
int
-_nouveau_therm_fini(struct nouveau_object *object, bool suspend)
+_nvkm_therm_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_therm *therm = (void *)object;
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm *therm = (void *)object;
+ struct nvkm_therm_priv *priv = (void *)therm;
- nouveau_therm_fan_fini(therm, suspend);
- nouveau_therm_sensor_fini(therm, suspend);
+ nvkm_therm_fan_fini(therm, suspend);
+ nvkm_therm_sensor_fini(therm, suspend);
if (suspend) {
priv->suspend = priv->mode;
- priv->mode = NOUVEAU_THERM_CTRL_NONE;
+ priv->mode = NVKM_THERM_CTRL_NONE;
}
- return nouveau_subdev_fini(&therm->base, suspend);
+ return nvkm_subdev_fini(&therm->base, suspend);
}
int
-nouveau_therm_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass,
- int length, void **pobject)
+nvkm_therm_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
- struct nouveau_therm_priv *priv;
+ struct nvkm_therm_priv *priv;
int ret;
- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PTHERM",
- "therm", length, pobject);
+ ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PTHERM",
+ "therm", length, pobject);
priv = *pobject;
if (ret)
return ret;
- nouveau_alarm_init(&priv->alarm, nouveau_therm_alarm);
+ nvkm_alarm_init(&priv->alarm, nvkm_therm_alarm);
spin_lock_init(&priv->lock);
spin_lock_init(&priv->sensor.alarm_program_lock);
- priv->base.fan_get = nouveau_therm_fan_user_get;
- priv->base.fan_set = nouveau_therm_fan_user_set;
- priv->base.fan_sense = nouveau_therm_fan_sense;
- priv->base.attr_get = nouveau_therm_attr_get;
- priv->base.attr_set = nouveau_therm_attr_set;
+ priv->base.fan_get = nvkm_therm_fan_user_get;
+ priv->base.fan_set = nvkm_therm_fan_user_set;
+ priv->base.fan_sense = nvkm_therm_fan_sense;
+ priv->base.attr_get = nvkm_therm_attr_get;
+ priv->base.attr_set = nvkm_therm_attr_set;
priv->mode = priv->suspend = -1; /* undefined */
return 0;
}
int
-nouveau_therm_preinit(struct nouveau_therm *therm)
+nvkm_therm_preinit(struct nvkm_therm *therm)
{
- nouveau_therm_sensor_ctor(therm);
- nouveau_therm_ic_ctor(therm);
- nouveau_therm_fan_ctor(therm);
+ nvkm_therm_sensor_ctor(therm);
+ nvkm_therm_ic_ctor(therm);
+ nvkm_therm_fan_ctor(therm);
- nouveau_therm_fan_mode(therm, NOUVEAU_THERM_CTRL_AUTO);
- nouveau_therm_sensor_preinit(therm);
+ nvkm_therm_fan_mode(therm, NVKM_THERM_CTRL_AUTO);
+ nvkm_therm_sensor_preinit(therm);
return 0;
}
void
-_nouveau_therm_dtor(struct nouveau_object *object)
+_nvkm_therm_dtor(struct nvkm_object *object)
{
- struct nouveau_therm_priv *priv = (void *)object;
+ struct nvkm_therm_priv *priv = (void *)object;
kfree(priv->fan);
- nouveau_subdev_destroy(&priv->base.base);
+ nvkm_subdev_destroy(&priv->base.base);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
index 3656d605168f..434fa745ca40 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
@@ -22,23 +22,18 @@
* Authors: Ben Skeggs
* Martin Peres
*/
-
#include "priv.h"
-#include <core/object.h>
-#include <core/device.h>
-
+#include <subdev/bios/fan.h>
#include <subdev/gpio.h>
#include <subdev/timer.h>
-#include <subdev/bios/fan.h>
-
static int
-nouveau_fan_update(struct nouveau_fan *fan, bool immediate, int target)
+nvkm_fan_update(struct nvkm_fan *fan, bool immediate, int target)
{
- struct nouveau_therm *therm = fan->parent;
- struct nouveau_therm_priv *priv = (void *)therm;
- struct nouveau_timer *ptimer = nouveau_timer(priv);
+ struct nvkm_therm *therm = fan->parent;
+ struct nvkm_therm_priv *priv = (void *)therm;
+ struct nvkm_timer *ptimer = nvkm_timer(priv);
unsigned long flags;
int ret = 0;
int duty;
@@ -107,32 +102,32 @@ nouveau_fan_update(struct nouveau_fan *fan, bool immediate, int target)
}
static void
-nouveau_fan_alarm(struct nouveau_alarm *alarm)
+nvkm_fan_alarm(struct nvkm_alarm *alarm)
{
- struct nouveau_fan *fan = container_of(alarm, struct nouveau_fan, alarm);
- nouveau_fan_update(fan, false, -1);
+ struct nvkm_fan *fan = container_of(alarm, struct nvkm_fan, alarm);
+ nvkm_fan_update(fan, false, -1);
}
int
-nouveau_therm_fan_get(struct nouveau_therm *therm)
+nvkm_therm_fan_get(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
return priv->fan->get(therm);
}
int
-nouveau_therm_fan_set(struct nouveau_therm *therm, bool immediate, int percent)
+nvkm_therm_fan_set(struct nvkm_therm *therm, bool immediate, int percent)
{
- struct nouveau_therm_priv *priv = (void *)therm;
- return nouveau_fan_update(priv->fan, immediate, percent);
+ struct nvkm_therm_priv *priv = (void *)therm;
+ return nvkm_fan_update(priv->fan, immediate, percent);
}
int
-nouveau_therm_fan_sense(struct nouveau_therm *therm)
+nvkm_therm_fan_sense(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
- struct nouveau_timer *ptimer = nouveau_timer(therm);
- struct nouveau_gpio *gpio = nouveau_gpio(therm);
+ struct nvkm_therm_priv *priv = (void *)therm;
+ struct nvkm_timer *ptimer = nvkm_timer(therm);
+ struct nvkm_gpio *gpio = nvkm_gpio(therm);
u32 cycles, cur, prev;
u64 start, end, tach;
@@ -168,26 +163,26 @@ nouveau_therm_fan_sense(struct nouveau_therm *therm)
}
int
-nouveau_therm_fan_user_get(struct nouveau_therm *therm)
+nvkm_therm_fan_user_get(struct nvkm_therm *therm)
{
- return nouveau_therm_fan_get(therm);
+ return nvkm_therm_fan_get(therm);
}
int
-nouveau_therm_fan_user_set(struct nouveau_therm *therm, int percent)
+nvkm_therm_fan_user_set(struct nvkm_therm *therm, int percent)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
- if (priv->mode != NOUVEAU_THERM_CTRL_MANUAL)
+ if (priv->mode != NVKM_THERM_CTRL_MANUAL)
return -EINVAL;
- return nouveau_therm_fan_set(therm, true, percent);
+ return nvkm_therm_fan_set(therm, true, percent);
}
static void
-nouveau_therm_fan_set_defaults(struct nouveau_therm *therm)
+nvkm_therm_fan_set_defaults(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
priv->fan->bios.pwm_freq = 0;
priv->fan->bios.min_duty = 0;
@@ -199,9 +194,9 @@ nouveau_therm_fan_set_defaults(struct nouveau_therm *therm)
}
static void
-nouveau_therm_fan_safety_checks(struct nouveau_therm *therm)
+nvkm_therm_fan_safety_checks(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
if (priv->fan->bios.min_duty > 100)
priv->fan->bios.min_duty = 100;
@@ -213,16 +208,16 @@ nouveau_therm_fan_safety_checks(struct nouveau_therm *therm)
}
int
-nouveau_therm_fan_init(struct nouveau_therm *therm)
+nvkm_therm_fan_init(struct nvkm_therm *therm)
{
return 0;
}
int
-nouveau_therm_fan_fini(struct nouveau_therm *therm, bool suspend)
+nvkm_therm_fan_fini(struct nvkm_therm *therm, bool suspend)
{
- struct nouveau_therm_priv *priv = (void *)therm;
- struct nouveau_timer *ptimer = nouveau_timer(therm);
+ struct nvkm_therm_priv *priv = (void *)therm;
+ struct nvkm_timer *ptimer = nvkm_timer(therm);
if (suspend)
ptimer->alarm_cancel(ptimer, &priv->fan->alarm);
@@ -230,11 +225,11 @@ nouveau_therm_fan_fini(struct nouveau_therm *therm, bool suspend)
}
int
-nouveau_therm_fan_ctor(struct nouveau_therm *therm)
+nvkm_therm_fan_ctor(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
- struct nouveau_gpio *gpio = nouveau_gpio(therm);
- struct nouveau_bios *bios = nouveau_bios(therm);
+ struct nvkm_therm_priv *priv = (void *)therm;
+ struct nvkm_gpio *gpio = nvkm_gpio(therm);
+ struct nvkm_bios *bios = nvkm_bios(therm);
struct dcb_gpio_func func;
int ret;
@@ -246,15 +241,15 @@ nouveau_therm_fan_ctor(struct nouveau_therm *therm)
nv_debug(therm, "GPIO_FAN is in input mode\n");
ret = -EINVAL;
} else {
- ret = nouveau_fanpwm_create(therm, &func);
+ ret = nvkm_fanpwm_create(therm, &func);
if (ret != 0)
- ret = nouveau_fantog_create(therm, &func);
+ ret = nvkm_fantog_create(therm, &func);
}
}
/* no controllable fan found, create a dummy fan module */
if (ret != 0) {
- ret = nouveau_fannil_create(therm);
+ ret = nvkm_fannil_create(therm);
if (ret)
return ret;
}
@@ -262,7 +257,7 @@ nouveau_therm_fan_ctor(struct nouveau_therm *therm)
nv_info(therm, "FAN control: %s\n", priv->fan->type);
/* read the current speed, it is useful when resuming */
- priv->fan->percent = nouveau_therm_fan_get(therm);
+ priv->fan->percent = nvkm_therm_fan_get(therm);
/* attempt to detect a tachometer connection */
ret = gpio->find(gpio, 0, DCB_GPIO_FAN_SENSE, 0xff, &priv->fan->tach);
@@ -271,17 +266,17 @@ nouveau_therm_fan_ctor(struct nouveau_therm *therm)
/* initialise fan bump/slow update handling */
priv->fan->parent = therm;
- nouveau_alarm_init(&priv->fan->alarm, nouveau_fan_alarm);
+ nvkm_alarm_init(&priv->fan->alarm, nvkm_fan_alarm);
spin_lock_init(&priv->fan->lock);
/* other random init... */
- nouveau_therm_fan_set_defaults(therm);
+ nvkm_therm_fan_set_defaults(therm);
nvbios_perf_fan_parse(bios, &priv->fan->perf);
if (!nvbios_fan_parse(bios, &priv->fan->bios)) {
nv_debug(therm, "parsing the fan table failed\n");
if (nvbios_therm_fan_parse(bios, &priv->fan->bios))
nv_error(therm, "parsing both fan tables failed\n");
}
- nouveau_therm_fan_safety_checks(therm);
+ nvkm_therm_fan_safety_checks(therm);
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.c
index b78c182e1d51..534e5970ec9c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.c
@@ -21,26 +21,25 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
static int
-nouveau_fannil_get(struct nouveau_therm *therm)
+nvkm_fannil_get(struct nvkm_therm *therm)
{
return -ENODEV;
}
static int
-nouveau_fannil_set(struct nouveau_therm *therm, int percent)
+nvkm_fannil_set(struct nvkm_therm *therm, int percent)
{
return -ENODEV;
}
int
-nouveau_fannil_create(struct nouveau_therm *therm)
+nvkm_fannil_create(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *tpriv = (void *)therm;
- struct nouveau_fan *priv;
+ struct nvkm_therm_priv *tpriv = (void *)therm;
+ struct nvkm_fan *priv;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
tpriv->fan = priv;
@@ -48,7 +47,7 @@ nouveau_fannil_create(struct nouveau_therm *therm)
return -ENOMEM;
priv->type = "none / external";
- priv->get = nouveau_fannil_get;
- priv->set = nouveau_fannil_set;
+ priv->get = nvkm_fannil_get;
+ priv->set = nvkm_fannil_set;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c
index c629d7f2a6a4..3cf4192a33af 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c
@@ -22,25 +22,24 @@
* Authors: Ben Skeggs
* Martin Peres
*/
-
-#include <core/option.h>
-#include <subdev/gpio.h>
-#include <subdev/bios.h>
-#include <subdev/bios/fan.h>
-
#include "priv.h"
-struct nouveau_fanpwm_priv {
- struct nouveau_fan base;
+#include <core/option.h>
+#include <subdev/bios.h>
+#include <subdev/bios/fan.h>
+#include <subdev/gpio.h>
+
+struct nvkm_fanpwm_priv {
+ struct nvkm_fan base;
struct dcb_gpio_func func;
};
static int
-nouveau_fanpwm_get(struct nouveau_therm *therm)
+nvkm_fanpwm_get(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *tpriv = (void *)therm;
- struct nouveau_fanpwm_priv *priv = (void *)tpriv->fan;
- struct nouveau_gpio *gpio = nouveau_gpio(therm);
+ struct nvkm_therm_priv *tpriv = (void *)therm;
+ struct nvkm_fanpwm_priv *priv = (void *)tpriv->fan;
+ struct nvkm_gpio *gpio = nvkm_gpio(therm);
int card_type = nv_device(therm)->card_type;
u32 divs, duty;
int ret;
@@ -57,10 +56,10 @@ nouveau_fanpwm_get(struct nouveau_therm *therm)
}
static int
-nouveau_fanpwm_set(struct nouveau_therm *therm, int percent)
+nvkm_fanpwm_set(struct nvkm_therm *therm, int percent)
{
- struct nouveau_therm_priv *tpriv = (void *)therm;
- struct nouveau_fanpwm_priv *priv = (void *)tpriv->fan;
+ struct nvkm_therm_priv *tpriv = (void *)therm;
+ struct nvkm_fanpwm_priv *priv = (void *)tpriv->fan;
int card_type = nv_device(therm)->card_type;
u32 divs, duty;
int ret;
@@ -84,18 +83,18 @@ nouveau_fanpwm_set(struct nouveau_therm *therm, int percent)
}
int
-nouveau_fanpwm_create(struct nouveau_therm *therm, struct dcb_gpio_func *func)
+nvkm_fanpwm_create(struct nvkm_therm *therm, struct dcb_gpio_func *func)
{
- struct nouveau_device *device = nv_device(therm);
- struct nouveau_therm_priv *tpriv = (void *)therm;
- struct nouveau_bios *bios = nouveau_bios(therm);
- struct nouveau_fanpwm_priv *priv;
+ struct nvkm_device *device = nv_device(therm);
+ struct nvkm_therm_priv *tpriv = (void *)therm;
+ struct nvkm_bios *bios = nvkm_bios(therm);
+ struct nvkm_fanpwm_priv *priv;
struct nvbios_therm_fan fan;
u32 divs, duty;
nvbios_fan_parse(bios, &fan);
- if (!nouveau_boolopt(device->cfgopt, "NvFanPWM", func->param) ||
+ if (!nvkm_boolopt(device->cfgopt, "NvFanPWM", func->param) ||
!therm->pwm_ctrl || fan.type == NVBIOS_THERM_FAN_TOGGLE ||
therm->pwm_get(therm, func->line, &divs, &duty) == -ENODEV)
return -ENODEV;
@@ -106,8 +105,8 @@ nouveau_fanpwm_create(struct nouveau_therm *therm, struct dcb_gpio_func *func)
return -ENOMEM;
priv->base.type = "PWM";
- priv->base.get = nouveau_fanpwm_get;
- priv->base.set = nouveau_fanpwm_set;
+ priv->base.get = nvkm_fanpwm_get;
+ priv->base.set = nvkm_fanpwm_set;
priv->func = *func;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c
index f69dab11f720..4ce041e81371 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c
@@ -21,18 +21,14 @@
*
* Authors: Martin Peres
*/
-
#include "priv.h"
-#include <core/object.h>
-#include <core/device.h>
-
#include <subdev/gpio.h>
#include <subdev/timer.h>
-struct nouveau_fantog_priv {
- struct nouveau_fan base;
- struct nouveau_alarm alarm;
+struct nvkm_fantog_priv {
+ struct nvkm_fan base;
+ struct nvkm_alarm alarm;
spinlock_t lock;
u32 period_us;
u32 percent;
@@ -40,11 +36,11 @@ struct nouveau_fantog_priv {
};
static void
-nouveau_fantog_update(struct nouveau_fantog_priv *priv, int percent)
+nvkm_fantog_update(struct nvkm_fantog_priv *priv, int percent)
{
- struct nouveau_therm_priv *tpriv = (void *)priv->base.parent;
- struct nouveau_timer *ptimer = nouveau_timer(tpriv);
- struct nouveau_gpio *gpio = nouveau_gpio(tpriv);
+ struct nvkm_therm_priv *tpriv = (void *)priv->base.parent;
+ struct nvkm_timer *ptimer = nvkm_timer(tpriv);
+ struct nvkm_gpio *gpio = nvkm_gpio(tpriv);
unsigned long flags;
int duty;
@@ -66,37 +62,37 @@ nouveau_fantog_update(struct nouveau_fantog_priv *priv, int percent)
}
static void
-nouveau_fantog_alarm(struct nouveau_alarm *alarm)
+nvkm_fantog_alarm(struct nvkm_alarm *alarm)
{
- struct nouveau_fantog_priv *priv =
- container_of(alarm, struct nouveau_fantog_priv, alarm);
- nouveau_fantog_update(priv, -1);
+ struct nvkm_fantog_priv *priv =
+ container_of(alarm, struct nvkm_fantog_priv, alarm);
+ nvkm_fantog_update(priv, -1);
}
static int
-nouveau_fantog_get(struct nouveau_therm *therm)
+nvkm_fantog_get(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *tpriv = (void *)therm;
- struct nouveau_fantog_priv *priv = (void *)tpriv->fan;
+ struct nvkm_therm_priv *tpriv = (void *)therm;
+ struct nvkm_fantog_priv *priv = (void *)tpriv->fan;
return priv->percent;
}
static int
-nouveau_fantog_set(struct nouveau_therm *therm, int percent)
+nvkm_fantog_set(struct nvkm_therm *therm, int percent)
{
- struct nouveau_therm_priv *tpriv = (void *)therm;
- struct nouveau_fantog_priv *priv = (void *)tpriv->fan;
+ struct nvkm_therm_priv *tpriv = (void *)therm;
+ struct nvkm_fantog_priv *priv = (void *)tpriv->fan;
if (therm->pwm_ctrl)
therm->pwm_ctrl(therm, priv->func.line, false);
- nouveau_fantog_update(priv, percent);
+ nvkm_fantog_update(priv, percent);
return 0;
}
int
-nouveau_fantog_create(struct nouveau_therm *therm, struct dcb_gpio_func *func)
+nvkm_fantog_create(struct nvkm_therm *therm, struct dcb_gpio_func *func)
{
- struct nouveau_therm_priv *tpriv = (void *)therm;
- struct nouveau_fantog_priv *priv;
+ struct nvkm_therm_priv *tpriv = (void *)therm;
+ struct nvkm_fantog_priv *priv;
int ret;
if (therm->pwm_ctrl) {
@@ -111,9 +107,9 @@ nouveau_fantog_create(struct nouveau_therm *therm, struct dcb_gpio_func *func)
return -ENOMEM;
priv->base.type = "toggle";
- priv->base.get = nouveau_fantog_get;
- priv->base.set = nouveau_fantog_set;
- nouveau_alarm_init(&priv->alarm, nouveau_fantog_alarm);
+ priv->base.get = nvkm_fantog_get;
+ priv->base.set = nvkm_fantog_set;
+ nvkm_alarm_init(&priv->alarm, nvkm_fantog_alarm);
priv->period_us = 100000; /* 10Hz */
priv->percent = 100;
priv->func = *func;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c
similarity index 60%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c
index 14e2e09bfc24..85b5d0c18c0b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c
@@ -22,18 +22,18 @@
* Authors: Ben Skeggs
* Martin Peres
*/
-
#include "priv.h"
+
#include <subdev/fuse.h>
-struct nv84_therm_priv {
- struct nouveau_therm_priv base;
+struct g84_therm_priv {
+ struct nvkm_therm_priv base;
};
int
-nv84_temp_get(struct nouveau_therm *therm)
+g84_temp_get(struct nvkm_therm *therm)
{
- struct nouveau_fuse *fuse = nouveau_fuse(therm);
+ struct nvkm_fuse *fuse = nvkm_fuse(therm);
if (nv_ro32(fuse, 0x1a8) == 1)
return nv_rd32(therm, 0x20400);
@@ -42,9 +42,9 @@ nv84_temp_get(struct nouveau_therm *therm)
}
void
-nv84_sensor_setup(struct nouveau_therm *therm)
+g84_sensor_setup(struct nvkm_therm *therm)
{
- struct nouveau_fuse *fuse = nouveau_fuse(therm);
+ struct nvkm_fuse *fuse = nvkm_fuse(therm);
/* enable temperature reading for cards with insane defaults */
if (nv_ro32(fuse, 0x1a8) == 1) {
@@ -55,9 +55,9 @@ nv84_sensor_setup(struct nouveau_therm *therm)
}
static void
-nv84_therm_program_alarms(struct nouveau_therm *therm)
+g84_therm_program_alarms(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
unsigned long flags;
@@ -92,53 +92,53 @@ nv84_therm_program_alarms(struct nouveau_therm *therm)
/* must be called with alarm_program_lock taken ! */
static void
-nv84_therm_threshold_hyst_emulation(struct nouveau_therm *therm,
+g84_therm_threshold_hyst_emulation(struct nvkm_therm *therm,
uint32_t thrs_reg, u8 status_bit,
const struct nvbios_therm_threshold *thrs,
- enum nouveau_therm_thrs thrs_name)
+ enum nvkm_therm_thrs thrs_name)
{
- enum nouveau_therm_thrs_direction direction;
- enum nouveau_therm_thrs_state prev_state, new_state;
+ enum nvkm_therm_thrs_direction direction;
+ enum nvkm_therm_thrs_state prev_state, new_state;
int temp, cur;
- prev_state = nouveau_therm_sensor_get_threshold_state(therm, thrs_name);
+ prev_state = nvkm_therm_sensor_get_threshold_state(therm, thrs_name);
temp = nv_rd32(therm, thrs_reg);
/* program the next threshold */
if (temp == thrs->temp) {
nv_wr32(therm, thrs_reg, thrs->temp - thrs->hysteresis);
- new_state = NOUVEAU_THERM_THRS_HIGHER;
+ new_state = NVKM_THERM_THRS_HIGHER;
} else {
nv_wr32(therm, thrs_reg, thrs->temp);
- new_state = NOUVEAU_THERM_THRS_LOWER;
+ new_state = NVKM_THERM_THRS_LOWER;
}
/* fix the state (in case someone reprogrammed the alarms) */
cur = therm->temp_get(therm);
- if (new_state == NOUVEAU_THERM_THRS_LOWER && cur > thrs->temp)
- new_state = NOUVEAU_THERM_THRS_HIGHER;
- else if (new_state == NOUVEAU_THERM_THRS_HIGHER &&
+ if (new_state == NVKM_THERM_THRS_LOWER && cur > thrs->temp)
+ new_state = NVKM_THERM_THRS_HIGHER;
+ else if (new_state == NVKM_THERM_THRS_HIGHER &&
cur < thrs->temp - thrs->hysteresis)
- new_state = NOUVEAU_THERM_THRS_LOWER;
- nouveau_therm_sensor_set_threshold_state(therm, thrs_name, new_state);
+ new_state = NVKM_THERM_THRS_LOWER;
+ nvkm_therm_sensor_set_threshold_state(therm, thrs_name, new_state);
/* find the direction */
if (prev_state < new_state)
- direction = NOUVEAU_THERM_THRS_RISING;
+ direction = NVKM_THERM_THRS_RISING;
else if (prev_state > new_state)
- direction = NOUVEAU_THERM_THRS_FALLING;
+ direction = NVKM_THERM_THRS_FALLING;
else
return;
/* advertise a change in direction */
- nouveau_therm_sensor_event(therm, thrs_name, direction);
+ nvkm_therm_sensor_event(therm, thrs_name, direction);
}
static void
-nv84_therm_intr(struct nouveau_subdev *subdev)
+g84_therm_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_therm *therm = nouveau_therm(subdev);
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm *therm = nvkm_therm(subdev);
+ struct nvkm_therm_priv *priv = (void *)therm;
struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
unsigned long flags;
uint32_t intr;
@@ -149,33 +149,33 @@ nv84_therm_intr(struct nouveau_subdev *subdev)
/* THRS_4: downclock */
if (intr & 0x002) {
- nv84_therm_threshold_hyst_emulation(therm, 0x20414, 24,
- &sensor->thrs_down_clock,
- NOUVEAU_THERM_THRS_DOWNCLOCK);
+ g84_therm_threshold_hyst_emulation(therm, 0x20414, 24,
+ &sensor->thrs_down_clock,
+ NVKM_THERM_THRS_DOWNCLOCK);
intr &= ~0x002;
}
/* shutdown */
if (intr & 0x004) {
- nv84_therm_threshold_hyst_emulation(therm, 0x20480, 20,
+ g84_therm_threshold_hyst_emulation(therm, 0x20480, 20,
&sensor->thrs_shutdown,
- NOUVEAU_THERM_THRS_SHUTDOWN);
+ NVKM_THERM_THRS_SHUTDOWN);
intr &= ~0x004;
}
/* THRS_1 : fan boost */
if (intr & 0x008) {
- nv84_therm_threshold_hyst_emulation(therm, 0x204c4, 21,
+ g84_therm_threshold_hyst_emulation(therm, 0x204c4, 21,
&sensor->thrs_fan_boost,
- NOUVEAU_THERM_THRS_FANBOOST);
+ NVKM_THERM_THRS_FANBOOST);
intr &= ~0x008;
}
/* THRS_2 : critical */
if (intr & 0x010) {
- nv84_therm_threshold_hyst_emulation(therm, 0x204c0, 22,
+ g84_therm_threshold_hyst_emulation(therm, 0x204c0, 22,
&sensor->thrs_critical,
- NOUVEAU_THERM_THRS_CRITICAL);
+ NVKM_THERM_THRS_CRITICAL);
intr &= ~0x010;
}
@@ -190,30 +190,28 @@ nv84_therm_intr(struct nouveau_subdev *subdev)
}
static int
-nv84_therm_init(struct nouveau_object *object)
+g84_therm_init(struct nvkm_object *object)
{
- struct nv84_therm_priv *priv = (void *)object;
+ struct g84_therm_priv *priv = (void *)object;
int ret;
- ret = nouveau_therm_init(&priv->base.base);
+ ret = nvkm_therm_init(&priv->base.base);
if (ret)
return ret;
- nv84_sensor_setup(&priv->base.base);
-
+ g84_sensor_setup(&priv->base.base);
return 0;
}
static int
-nv84_therm_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g84_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nv84_therm_priv *priv;
+ struct g84_therm_priv *priv;
int ret;
- ret = nouveau_therm_create(parent, engine, oclass, &priv);
+ ret = nvkm_therm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -222,29 +220,29 @@ nv84_therm_ctor(struct nouveau_object *parent,
priv->base.base.pwm_get = nv50_fan_pwm_get;
priv->base.base.pwm_set = nv50_fan_pwm_set;
priv->base.base.pwm_clock = nv50_fan_pwm_clock;
- priv->base.base.temp_get = nv84_temp_get;
- priv->base.sensor.program_alarms = nv84_therm_program_alarms;
- nv_subdev(priv)->intr = nv84_therm_intr;
+ priv->base.base.temp_get = g84_temp_get;
+ priv->base.sensor.program_alarms = g84_therm_program_alarms;
+ nv_subdev(priv)->intr = g84_therm_intr;
/* init the thresholds */
- nouveau_therm_sensor_set_threshold_state(&priv->base.base,
- NOUVEAU_THERM_THRS_SHUTDOWN,
- NOUVEAU_THERM_THRS_LOWER);
- nouveau_therm_sensor_set_threshold_state(&priv->base.base,
- NOUVEAU_THERM_THRS_FANBOOST,
- NOUVEAU_THERM_THRS_LOWER);
- nouveau_therm_sensor_set_threshold_state(&priv->base.base,
- NOUVEAU_THERM_THRS_CRITICAL,
- NOUVEAU_THERM_THRS_LOWER);
- nouveau_therm_sensor_set_threshold_state(&priv->base.base,
- NOUVEAU_THERM_THRS_DOWNCLOCK,
- NOUVEAU_THERM_THRS_LOWER);
+ nvkm_therm_sensor_set_threshold_state(&priv->base.base,
+ NVKM_THERM_THRS_SHUTDOWN,
+ NVKM_THERM_THRS_LOWER);
+ nvkm_therm_sensor_set_threshold_state(&priv->base.base,
+ NVKM_THERM_THRS_FANBOOST,
+ NVKM_THERM_THRS_LOWER);
+ nvkm_therm_sensor_set_threshold_state(&priv->base.base,
+ NVKM_THERM_THRS_CRITICAL,
+ NVKM_THERM_THRS_LOWER);
+ nvkm_therm_sensor_set_threshold_state(&priv->base.base,
+ NVKM_THERM_THRS_DOWNCLOCK,
+ NVKM_THERM_THRS_LOWER);
- return nouveau_therm_preinit(&priv->base.base);
+ return nvkm_therm_preinit(&priv->base.base);
}
int
-nv84_therm_fini(struct nouveau_object *object, bool suspend)
+g84_therm_fini(struct nvkm_object *object, bool suspend)
{
/* Disable PTherm IRQs */
nv_wr32(object, 0x20000, 0x00000000);
@@ -253,16 +251,16 @@ nv84_therm_fini(struct nouveau_object *object, bool suspend)
nv_wr32(object, 0x20100, 0xffffffff);
nv_wr32(object, 0x1100, 0x10000); /* PBUS */
- return _nouveau_therm_fini(object, suspend);
+ return _nvkm_therm_fini(object, suspend);
}
-struct nouveau_oclass
-nv84_therm_oclass = {
+struct nvkm_oclass
+g84_therm_oclass = {
.handle = NV_SUBDEV(THERM, 0x84),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv84_therm_ctor,
- .dtor = _nouveau_therm_dtor,
- .init = nv84_therm_init,
- .fini = nv84_therm_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g84_therm_ctor,
+ .dtor = _nvkm_therm_dtor,
+ .init = g84_therm_init,
+ .fini = g84_therm_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c
similarity index 70%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/therm/nvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c
index b70f7cc649b8..0540e6886d7d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nvd0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
-struct nvd0_therm_priv {
- struct nouveau_therm_priv base;
+struct gf110_therm_priv {
+ struct nvkm_therm_priv base;
};
static int
-pwm_info(struct nouveau_therm *therm, int line)
+pwm_info(struct nvkm_therm *therm, int line)
{
u32 gpio = nv_rd32(therm, 0x00d610 + (line * 0x04));
@@ -53,7 +52,7 @@ pwm_info(struct nouveau_therm *therm, int line)
}
static int
-nvd0_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
+gf110_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable)
{
u32 data = enable ? 0x00000040 : 0x00000000;
int indx = pwm_info(therm, line);
@@ -66,7 +65,7 @@ nvd0_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
}
static int
-nvd0_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
+gf110_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)
{
int indx = pwm_info(therm, line);
if (indx < 0)
@@ -87,7 +86,7 @@ nvd0_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
}
static int
-nvd0_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
+gf110_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)
{
int indx = pwm_info(therm, line);
if (indx < 0)
@@ -103,7 +102,7 @@ nvd0_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
}
static int
-nvd0_fan_pwm_clock(struct nouveau_therm *therm, int line)
+gf110_fan_pwm_clock(struct nvkm_therm *therm, int line)
{
int indx = pwm_info(therm, line);
if (indx < 0)
@@ -115,12 +114,12 @@ nvd0_fan_pwm_clock(struct nouveau_therm *therm, int line)
}
int
-nvd0_therm_init(struct nouveau_object *object)
+gf110_therm_init(struct nvkm_object *object)
{
- struct nvd0_therm_priv *priv = (void *)object;
+ struct gf110_therm_priv *priv = (void *)object;
int ret;
- ret = nouveau_therm_init(&priv->base.base);
+ ret = nvkm_therm_init(&priv->base.base);
if (ret)
return ret;
@@ -137,38 +136,37 @@ nvd0_therm_init(struct nouveau_object *object)
}
static int
-nvd0_therm_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf110_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvd0_therm_priv *priv;
+ struct gf110_therm_priv *priv;
int ret;
- ret = nouveau_therm_create(parent, engine, oclass, &priv);
+ ret = nvkm_therm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- nv84_sensor_setup(&priv->base.base);
+ g84_sensor_setup(&priv->base.base);
- priv->base.base.pwm_ctrl = nvd0_fan_pwm_ctrl;
- priv->base.base.pwm_get = nvd0_fan_pwm_get;
- priv->base.base.pwm_set = nvd0_fan_pwm_set;
- priv->base.base.pwm_clock = nvd0_fan_pwm_clock;
- priv->base.base.temp_get = nv84_temp_get;
- priv->base.base.fan_sense = nva3_therm_fan_sense;
- priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
- return nouveau_therm_preinit(&priv->base.base);
+ priv->base.base.pwm_ctrl = gf110_fan_pwm_ctrl;
+ priv->base.base.pwm_get = gf110_fan_pwm_get;
+ priv->base.base.pwm_set = gf110_fan_pwm_set;
+ priv->base.base.pwm_clock = gf110_fan_pwm_clock;
+ priv->base.base.temp_get = g84_temp_get;
+ priv->base.base.fan_sense = gt215_therm_fan_sense;
+ priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling;
+ return nvkm_therm_preinit(&priv->base.base);
}
-struct nouveau_oclass
-nvd0_therm_oclass = {
+struct nvkm_oclass
+gf110_therm_oclass = {
.handle = NV_SUBDEV(THERM, 0xd0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvd0_therm_ctor,
- .dtor = _nouveau_therm_dtor,
- .init = nvd0_therm_init,
- .fini = nv84_therm_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf110_therm_ctor,
+ .dtor = _nvkm_therm_dtor,
+ .init = gf110_therm_init,
+ .fini = g84_therm_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c
index 668cf3322285..c1f3cf361837 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c
@@ -21,22 +21,21 @@
*
* Authors: Martin Peres
*/
-
#include "priv.h"
struct gm107_therm_priv {
- struct nouveau_therm_priv base;
+ struct nvkm_therm_priv base;
};
static int
-gm107_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
+gm107_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable)
{
/* nothing to do, it seems hardwired */
return 0;
}
static int
-gm107_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
+gm107_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)
{
*divs = nv_rd32(therm, 0x10eb20) & 0x1fff;
*duty = nv_rd32(therm, 0x10eb24) & 0x1fff;
@@ -44,7 +43,7 @@ gm107_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
}
static int
-gm107_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
+gm107_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)
{
nv_mask(therm, 0x10eb10, 0x1fff, divs); /* keep the high bits */
nv_wr32(therm, 0x10eb14, duty | 0x80000000);
@@ -52,21 +51,20 @@ gm107_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
}
static int
-gm107_fan_pwm_clock(struct nouveau_therm *therm, int line)
+gm107_fan_pwm_clock(struct nvkm_therm *therm, int line)
{
return nv_device(therm)->crystal * 1000;
}
static int
-gm107_therm_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gm107_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct gm107_therm_priv *priv;
int ret;
- ret = nouveau_therm_create(parent, engine, oclass, &priv);
+ ret = nvkm_therm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -75,19 +73,19 @@ gm107_therm_ctor(struct nouveau_object *parent,
priv->base.base.pwm_get = gm107_fan_pwm_get;
priv->base.base.pwm_set = gm107_fan_pwm_set;
priv->base.base.pwm_clock = gm107_fan_pwm_clock;
- priv->base.base.temp_get = nv84_temp_get;
- priv->base.base.fan_sense = nva3_therm_fan_sense;
- priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
- return nouveau_therm_preinit(&priv->base.base);
+ priv->base.base.temp_get = g84_temp_get;
+ priv->base.base.fan_sense = gt215_therm_fan_sense;
+ priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling;
+ return nvkm_therm_preinit(&priv->base.base);
}
-struct nouveau_oclass
+struct nvkm_oclass
gm107_therm_oclass = {
.handle = NV_SUBDEV(THERM, 0x117),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm107_therm_ctor,
- .dtor = _nouveau_therm_dtor,
- .init = nvd0_therm_init,
- .fini = nv84_therm_fini,
+ .dtor = _nvkm_therm_dtor,
+ .init = gf110_therm_init,
+ .fini = g84_therm_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c
similarity index 69%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/therm/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c
index 7893357a7e9f..b7fa4716ca9f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c
@@ -21,17 +21,16 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/gpio.h>
-#include "priv.h"
-
-struct nva3_therm_priv {
- struct nouveau_therm_priv base;
+struct gt215_therm_priv {
+ struct nvkm_therm_priv base;
};
int
-nva3_therm_fan_sense(struct nouveau_therm *therm)
+gt215_therm_fan_sense(struct nvkm_therm *therm)
{
u32 tach = nv_rd32(therm, 0x00e728) & 0x0000ffff;
u32 ctrl = nv_rd32(therm, 0x00e720);
@@ -41,17 +40,17 @@ nva3_therm_fan_sense(struct nouveau_therm *therm)
}
static int
-nva3_therm_init(struct nouveau_object *object)
+gt215_therm_init(struct nvkm_object *object)
{
- struct nva3_therm_priv *priv = (void *)object;
+ struct gt215_therm_priv *priv = (void *)object;
struct dcb_gpio_func *tach = &priv->base.fan->tach;
int ret;
- ret = nouveau_therm_init(&priv->base.base);
+ ret = nvkm_therm_init(&priv->base.base);
if (ret)
return ret;
- nv84_sensor_setup(&priv->base.base);
+ g84_sensor_setup(&priv->base.base);
/* enable fan tach, count revolutions per-second */
nv_mask(priv, 0x00e720, 0x00000003, 0x00000002);
@@ -66,15 +65,14 @@ nva3_therm_init(struct nouveau_object *object)
}
static int
-nva3_therm_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gt215_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nva3_therm_priv *priv;
+ struct gt215_therm_priv *priv;
int ret;
- ret = nouveau_therm_create(parent, engine, oclass, &priv);
+ ret = nvkm_therm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -83,19 +81,19 @@ nva3_therm_ctor(struct nouveau_object *parent,
priv->base.base.pwm_get = nv50_fan_pwm_get;
priv->base.base.pwm_set = nv50_fan_pwm_set;
priv->base.base.pwm_clock = nv50_fan_pwm_clock;
- priv->base.base.temp_get = nv84_temp_get;
- priv->base.base.fan_sense = nva3_therm_fan_sense;
- priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
- return nouveau_therm_preinit(&priv->base.base);
+ priv->base.base.temp_get = g84_temp_get;
+ priv->base.base.fan_sense = gt215_therm_fan_sense;
+ priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling;
+ return nvkm_therm_preinit(&priv->base.base);
}
-struct nouveau_oclass
-nva3_therm_oclass = {
+struct nvkm_oclass
+gt215_therm_oclass = {
.handle = NV_SUBDEV(THERM, 0xa3),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nva3_therm_ctor,
- .dtor = _nouveau_therm_dtor,
- .init = nva3_therm_init,
- .fini = nv84_therm_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gt215_therm_ctor,
+ .dtor = _nvkm_therm_dtor,
+ .init = gt215_therm_init,
+ .fini = g84_therm_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c
index ca9ad9fd47be..09fc4605e853 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c
@@ -21,17 +21,16 @@
*
* Authors: Martin Peres
*/
-
#include "priv.h"
-#include <subdev/i2c.h>
#include <subdev/bios/extdev.h>
+#include <subdev/i2c.h>
static bool
-probe_monitoring_device(struct nouveau_i2c_port *i2c,
+probe_monitoring_device(struct nvkm_i2c_port *i2c,
struct i2c_board_info *info, void *data)
{
- struct nouveau_therm_priv *priv = data;
+ struct nvkm_therm_priv *priv = data;
struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
struct i2c_client *client;
@@ -52,11 +51,10 @@ probe_monitoring_device(struct nouveau_i2c_port *i2c,
"temp offset %+i C)\n",
info->type, info->addr, sensor->offset_constant);
priv->ic = client;
-
return true;
}
-static struct nouveau_i2c_board_info
+static struct nvkm_i2c_board_info
nv_board_infos[] = {
{ { I2C_BOARD_INFO("w83l785ts", 0x2d) }, 0 },
{ { I2C_BOARD_INFO("w83781d", 0x2d) }, 0 },
@@ -82,15 +80,15 @@ nv_board_infos[] = {
};
void
-nouveau_therm_ic_ctor(struct nouveau_therm *therm)
+nvkm_therm_ic_ctor(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
- struct nouveau_bios *bios = nouveau_bios(therm);
- struct nouveau_i2c *i2c = nouveau_i2c(therm);
+ struct nvkm_therm_priv *priv = (void *)therm;
+ struct nvkm_bios *bios = nvkm_bios(therm);
+ struct nvkm_i2c *i2c = nvkm_i2c(therm);
struct nvbios_extdev_func extdev_entry;
if (!nvbios_extdev_find(bios, NVBIOS_EXTDEV_LM89, &extdev_entry)) {
- struct nouveau_i2c_board_info board[] = {
+ struct nvkm_i2c_board_info board[] = {
{ { I2C_BOARD_INFO("lm90", extdev_entry.addr >> 1) }, 0},
{ }
};
@@ -102,7 +100,7 @@ nouveau_therm_ic_ctor(struct nouveau_therm *therm)
}
if (!nvbios_extdev_find(bios, NVBIOS_EXTDEV_ADT7473, &extdev_entry)) {
- struct nouveau_i2c_board_info board[] = {
+ struct nvkm_i2c_board_info board[] = {
{ { I2C_BOARD_INFO("adt7473", extdev_entry.addr >> 1) }, 20 },
{ }
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c
index 002e51b3af93..20f65fd7679a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c
@@ -22,19 +22,18 @@
* Authors: Ben Skeggs
* Martin Peres
*/
-
#include "priv.h"
struct nv40_therm_priv {
- struct nouveau_therm_priv base;
+ struct nvkm_therm_priv base;
};
enum nv40_sensor_style { INVALID_STYLE = -1, OLD_STYLE = 0, NEW_STYLE = 1 };
static enum nv40_sensor_style
-nv40_sensor_style(struct nouveau_therm *therm)
+nv40_sensor_style(struct nvkm_therm *therm)
{
- struct nouveau_device *device = nv_device(therm);
+ struct nvkm_device *device = nv_device(therm);
switch (device->chipset) {
case 0x43:
@@ -58,7 +57,7 @@ nv40_sensor_style(struct nouveau_therm *therm)
}
static int
-nv40_sensor_setup(struct nouveau_therm *therm)
+nv40_sensor_setup(struct nvkm_therm *therm)
{
enum nv40_sensor_style style = nv40_sensor_style(therm);
@@ -77,9 +76,9 @@ nv40_sensor_setup(struct nouveau_therm *therm)
}
static int
-nv40_temp_get(struct nouveau_therm *therm)
+nv40_temp_get(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
enum nv40_sensor_style style = nv40_sensor_style(therm);
int core_temp;
@@ -110,7 +109,7 @@ nv40_temp_get(struct nouveau_therm *therm)
}
static int
-nv40_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
+nv40_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable)
{
u32 mask = enable ? 0x80000000 : 0x0000000;
if (line == 2) nv_mask(therm, 0x0010f0, 0x80000000, mask);
@@ -123,7 +122,7 @@ nv40_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
}
static int
-nv40_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
+nv40_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)
{
if (line == 2) {
u32 reg = nv_rd32(therm, 0x0010f0);
@@ -149,7 +148,7 @@ nv40_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
}
static int
-nv40_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
+nv40_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)
{
if (line == 2) {
nv_mask(therm, 0x0010f0, 0x7fff7fff, (duty << 16) | divs);
@@ -166,9 +165,9 @@ nv40_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
}
void
-nv40_therm_intr(struct nouveau_subdev *subdev)
+nv40_therm_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_therm *therm = nouveau_therm(subdev);
+ struct nvkm_therm *therm = nvkm_therm(subdev);
uint32_t stat = nv_rd32(therm, 0x1100);
/* traitement */
@@ -180,15 +179,15 @@ nv40_therm_intr(struct nouveau_subdev *subdev)
}
static int
-nv40_therm_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_therm_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv40_therm_priv *priv;
int ret;
- ret = nouveau_therm_create(parent, engine, oclass, &priv);
+ ret = nvkm_therm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -197,28 +196,28 @@ nv40_therm_ctor(struct nouveau_object *parent,
priv->base.base.pwm_get = nv40_fan_pwm_get;
priv->base.base.pwm_set = nv40_fan_pwm_set;
priv->base.base.temp_get = nv40_temp_get;
- priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
+ priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling;
nv_subdev(priv)->intr = nv40_therm_intr;
- return nouveau_therm_preinit(&priv->base.base);
+ return nvkm_therm_preinit(&priv->base.base);
}
static int
-nv40_therm_init(struct nouveau_object *object)
+nv40_therm_init(struct nvkm_object *object)
{
- struct nouveau_therm *therm = (void *)object;
+ struct nvkm_therm *therm = (void *)object;
nv40_sensor_setup(therm);
- return _nouveau_therm_init(object);
+ return _nvkm_therm_init(object);
}
-struct nouveau_oclass
+struct nvkm_oclass
nv40_therm_oclass = {
.handle = NV_SUBDEV(THERM, 0x40),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_therm_ctor,
- .dtor = _nouveau_therm_dtor,
+ .dtor = _nvkm_therm_dtor,
.init = nv40_therm_init,
- .fini = _nouveau_therm_fini,
+ .fini = _nvkm_therm_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c
index 321db927d638..489dcf355d34 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c
@@ -22,15 +22,14 @@
* Authors: Ben Skeggs
* Martin Peres
*/
-
#include "priv.h"
struct nv50_therm_priv {
- struct nouveau_therm_priv base;
+ struct nvkm_therm_priv base;
};
static int
-pwm_info(struct nouveau_therm *therm, int *line, int *ctrl, int *indx)
+pwm_info(struct nvkm_therm *therm, int *line, int *ctrl, int *indx)
{
if (*line == 0x04) {
*ctrl = 0x00e100;
@@ -55,7 +54,7 @@ pwm_info(struct nouveau_therm *therm, int *line, int *ctrl, int *indx)
}
int
-nv50_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
+nv50_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable)
{
u32 data = enable ? 0x00000001 : 0x00000000;
int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id);
@@ -65,7 +64,7 @@ nv50_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
}
int
-nv50_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
+nv50_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)
{
int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id);
if (ret)
@@ -81,7 +80,7 @@ nv50_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
}
int
-nv50_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
+nv50_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)
{
int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id);
if (ret)
@@ -93,7 +92,7 @@ nv50_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
}
int
-nv50_fan_pwm_clock(struct nouveau_therm *therm, int line)
+nv50_fan_pwm_clock(struct nvkm_therm *therm, int line)
{
int chipset = nv_device(therm)->chipset;
int crystal = nv_device(therm)->crystal;
@@ -119,16 +118,16 @@ nv50_fan_pwm_clock(struct nouveau_therm *therm, int line)
}
static void
-nv50_sensor_setup(struct nouveau_therm *therm)
+nv50_sensor_setup(struct nvkm_therm *therm)
{
nv_mask(therm, 0x20010, 0x40000000, 0x0);
mdelay(20); /* wait for the temperature to stabilize */
}
static int
-nv50_temp_get(struct nouveau_therm *therm)
+nv50_temp_get(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
int core_temp;
@@ -151,15 +150,15 @@ nv50_temp_get(struct nouveau_therm *therm)
}
static int
-nv50_therm_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_therm_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_therm_priv *priv;
int ret;
- ret = nouveau_therm_create(parent, engine, oclass, &priv);
+ ret = nvkm_therm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -169,29 +168,29 @@ nv50_therm_ctor(struct nouveau_object *parent,
priv->base.base.pwm_set = nv50_fan_pwm_set;
priv->base.base.pwm_clock = nv50_fan_pwm_clock;
priv->base.base.temp_get = nv50_temp_get;
- priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
+ priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling;
nv_subdev(priv)->intr = nv40_therm_intr;
- return nouveau_therm_preinit(&priv->base.base);
+ return nvkm_therm_preinit(&priv->base.base);
}
static int
-nv50_therm_init(struct nouveau_object *object)
+nv50_therm_init(struct nvkm_object *object)
{
- struct nouveau_therm *therm = (void *)object;
+ struct nvkm_therm *therm = (void *)object;
nv50_sensor_setup(therm);
- return _nouveau_therm_init(object);
+ return _nvkm_therm_init(object);
}
-struct nouveau_oclass
+struct nvkm_oclass
nv50_therm_oclass = {
.handle = NV_SUBDEV(THERM, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_therm_ctor,
- .dtor = _nouveau_therm_dtor,
+ .dtor = _nvkm_therm_dtor,
.init = nv50_therm_init,
- .fini = _nouveau_therm_fini,
+ .fini = _nvkm_therm_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h
index 8db630818793..916a149efe6e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h
@@ -1,6 +1,5 @@
#ifndef __NVTHERM_PRIV_H__
#define __NVTHERM_PRIV_H__
-
/*
* Copyright 2012 The Nouveau community
*
@@ -24,9 +23,7 @@
*
* Authors: Martin Peres
*/
-
#include <subdev/therm.h>
-
#include <subdev/bios.h>
#include <subdev/bios/extdev.h>
#include <subdev/bios/gpio.h>
@@ -34,46 +31,46 @@
#include <subdev/bios/therm.h>
#include <subdev/timer.h>
-struct nouveau_fan {
- struct nouveau_therm *parent;
+struct nvkm_fan {
+ struct nvkm_therm *parent;
const char *type;
struct nvbios_therm_fan bios;
struct nvbios_perf_fan perf;
- struct nouveau_alarm alarm;
+ struct nvkm_alarm alarm;
spinlock_t lock;
int percent;
- int (*get)(struct nouveau_therm *therm);
- int (*set)(struct nouveau_therm *therm, int percent);
+ int (*get)(struct nvkm_therm *);
+ int (*set)(struct nvkm_therm *, int percent);
struct dcb_gpio_func tach;
};
-enum nouveau_therm_thrs_direction {
- NOUVEAU_THERM_THRS_FALLING = 0,
- NOUVEAU_THERM_THRS_RISING = 1
+enum nvkm_therm_thrs_direction {
+ NVKM_THERM_THRS_FALLING = 0,
+ NVKM_THERM_THRS_RISING = 1
};
-enum nouveau_therm_thrs_state {
- NOUVEAU_THERM_THRS_LOWER = 0,
- NOUVEAU_THERM_THRS_HIGHER = 1
+enum nvkm_therm_thrs_state {
+ NVKM_THERM_THRS_LOWER = 0,
+ NVKM_THERM_THRS_HIGHER = 1
};
-enum nouveau_therm_thrs {
- NOUVEAU_THERM_THRS_FANBOOST = 0,
- NOUVEAU_THERM_THRS_DOWNCLOCK = 1,
- NOUVEAU_THERM_THRS_CRITICAL = 2,
- NOUVEAU_THERM_THRS_SHUTDOWN = 3,
- NOUVEAU_THERM_THRS_NR
+enum nvkm_therm_thrs {
+ NVKM_THERM_THRS_FANBOOST = 0,
+ NVKM_THERM_THRS_DOWNCLOCK = 1,
+ NVKM_THERM_THRS_CRITICAL = 2,
+ NVKM_THERM_THRS_SHUTDOWN = 3,
+ NVKM_THERM_THRS_NR
};
-struct nouveau_therm_priv {
- struct nouveau_therm base;
+struct nvkm_therm_priv {
+ struct nvkm_therm base;
/* automatic thermal management */
- struct nouveau_alarm alarm;
+ struct nvkm_alarm alarm;
spinlock_t lock;
struct nvbios_therm_trip_point *last_trip;
int mode;
@@ -84,77 +81,73 @@ struct nouveau_therm_priv {
struct nvbios_therm_sensor bios_sensor;
/* fan priv */
- struct nouveau_fan *fan;
+ struct nvkm_fan *fan;
/* alarms priv */
struct {
spinlock_t alarm_program_lock;
- struct nouveau_alarm therm_poll_alarm;
- enum nouveau_therm_thrs_state alarm_state[NOUVEAU_THERM_THRS_NR];
- void (*program_alarms)(struct nouveau_therm *);
+ struct nvkm_alarm therm_poll_alarm;
+ enum nvkm_therm_thrs_state alarm_state[NVKM_THERM_THRS_NR];
+ void (*program_alarms)(struct nvkm_therm *);
} sensor;
/* what should be done if the card overheats */
struct {
- void (*downclock)(struct nouveau_therm *, bool active);
- void (*pause)(struct nouveau_therm *, bool active);
+ void (*downclock)(struct nvkm_therm *, bool active);
+ void (*pause)(struct nvkm_therm *, bool active);
} emergency;
/* ic */
struct i2c_client *ic;
};
-int nouveau_therm_fan_mode(struct nouveau_therm *therm, int mode);
-int nouveau_therm_attr_get(struct nouveau_therm *therm,
- enum nouveau_therm_attr_type type);
-int nouveau_therm_attr_set(struct nouveau_therm *therm,
- enum nouveau_therm_attr_type type, int value);
+int nvkm_therm_fan_mode(struct nvkm_therm *, int mode);
+int nvkm_therm_attr_get(struct nvkm_therm *, enum nvkm_therm_attr_type);
+int nvkm_therm_attr_set(struct nvkm_therm *, enum nvkm_therm_attr_type, int);
-void nouveau_therm_ic_ctor(struct nouveau_therm *therm);
+void nvkm_therm_ic_ctor(struct nvkm_therm *);
-int nouveau_therm_sensor_ctor(struct nouveau_therm *therm);
+int nvkm_therm_sensor_ctor(struct nvkm_therm *);
-int nouveau_therm_fan_ctor(struct nouveau_therm *therm);
-int nouveau_therm_fan_init(struct nouveau_therm *therm);
-int nouveau_therm_fan_fini(struct nouveau_therm *therm, bool suspend);
-int nouveau_therm_fan_get(struct nouveau_therm *therm);
-int nouveau_therm_fan_set(struct nouveau_therm *therm, bool now, int percent);
-int nouveau_therm_fan_user_get(struct nouveau_therm *therm);
-int nouveau_therm_fan_user_set(struct nouveau_therm *therm, int percent);
+int nvkm_therm_fan_ctor(struct nvkm_therm *);
+int nvkm_therm_fan_init(struct nvkm_therm *);
+int nvkm_therm_fan_fini(struct nvkm_therm *, bool suspend);
+int nvkm_therm_fan_get(struct nvkm_therm *);
+int nvkm_therm_fan_set(struct nvkm_therm *, bool now, int percent);
+int nvkm_therm_fan_user_get(struct nvkm_therm *);
+int nvkm_therm_fan_user_set(struct nvkm_therm *, int percent);
-int nouveau_therm_fan_sense(struct nouveau_therm *therm);
+int nvkm_therm_fan_sense(struct nvkm_therm *);
-int nouveau_therm_preinit(struct nouveau_therm *);
+int nvkm_therm_preinit(struct nvkm_therm *);
-int nouveau_therm_sensor_init(struct nouveau_therm *therm);
-int nouveau_therm_sensor_fini(struct nouveau_therm *therm, bool suspend);
-void nouveau_therm_sensor_preinit(struct nouveau_therm *);
-void nouveau_therm_sensor_set_threshold_state(struct nouveau_therm *therm,
- enum nouveau_therm_thrs thrs,
- enum nouveau_therm_thrs_state st);
-enum nouveau_therm_thrs_state
-nouveau_therm_sensor_get_threshold_state(struct nouveau_therm *therm,
- enum nouveau_therm_thrs thrs);
-void nouveau_therm_sensor_event(struct nouveau_therm *therm,
- enum nouveau_therm_thrs thrs,
- enum nouveau_therm_thrs_direction dir);
-void nouveau_therm_program_alarms_polling(struct nouveau_therm *therm);
+int nvkm_therm_sensor_init(struct nvkm_therm *);
+int nvkm_therm_sensor_fini(struct nvkm_therm *, bool suspend);
+void nvkm_therm_sensor_preinit(struct nvkm_therm *);
+void nvkm_therm_sensor_set_threshold_state(struct nvkm_therm *,
+ enum nvkm_therm_thrs,
+ enum nvkm_therm_thrs_state);
+enum nvkm_therm_thrs_state
+nvkm_therm_sensor_get_threshold_state(struct nvkm_therm *,
+ enum nvkm_therm_thrs);
+void nvkm_therm_sensor_event(struct nvkm_therm *, enum nvkm_therm_thrs,
+ enum nvkm_therm_thrs_direction);
+void nvkm_therm_program_alarms_polling(struct nvkm_therm *);
-void nv40_therm_intr(struct nouveau_subdev *);
-int nv50_fan_pwm_ctrl(struct nouveau_therm *, int, bool);
-int nv50_fan_pwm_get(struct nouveau_therm *, int, u32 *, u32 *);
-int nv50_fan_pwm_set(struct nouveau_therm *, int, u32, u32);
-int nv50_fan_pwm_clock(struct nouveau_therm *, int);
-int nv84_temp_get(struct nouveau_therm *therm);
-void nv84_sensor_setup(struct nouveau_therm *therm);
-int nv84_therm_fini(struct nouveau_object *object, bool suspend);
+void nv40_therm_intr(struct nvkm_subdev *);
+int nv50_fan_pwm_ctrl(struct nvkm_therm *, int, bool);
+int nv50_fan_pwm_get(struct nvkm_therm *, int, u32 *, u32 *);
+int nv50_fan_pwm_set(struct nvkm_therm *, int, u32, u32);
+int nv50_fan_pwm_clock(struct nvkm_therm *, int);
+int g84_temp_get(struct nvkm_therm *);
+void g84_sensor_setup(struct nvkm_therm *);
+int g84_therm_fini(struct nvkm_object *, bool suspend);
-int nva3_therm_fan_sense(struct nouveau_therm *);
+int gt215_therm_fan_sense(struct nvkm_therm *);
-int nvd0_therm_init(struct nouveau_object *object);
-
-int nouveau_fanpwm_create(struct nouveau_therm *, struct dcb_gpio_func *);
-int nouveau_fantog_create(struct nouveau_therm *, struct dcb_gpio_func *);
-int nouveau_fannil_create(struct nouveau_therm *);
+int gf110_therm_init(struct nvkm_object *);
+int nvkm_fanpwm_create(struct nvkm_therm *, struct dcb_gpio_func *);
+int nvkm_fantog_create(struct nvkm_therm *, struct dcb_gpio_func *);
+int nvkm_fannil_create(struct nvkm_therm *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c
index 6212537b90c5..aa13744f3854 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c
@@ -21,18 +21,12 @@
*
* Authors: Martin Peres
*/
-
#include "priv.h"
-#include <core/object.h>
-#include <core/device.h>
-
-#include <subdev/bios.h>
-
static void
-nouveau_therm_temp_set_defaults(struct nouveau_therm *therm)
+nvkm_therm_temp_set_defaults(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
priv->bios_sensor.offset_constant = 0;
@@ -51,9 +45,9 @@ nouveau_therm_temp_set_defaults(struct nouveau_therm *therm)
static void
-nouveau_therm_temp_safety_checks(struct nouveau_therm *therm)
+nvkm_therm_temp_safety_checks(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
struct nvbios_therm_sensor *s = &priv->bios_sensor;
/* enforce a minimum hysteresis on thresholds */
@@ -64,20 +58,21 @@ nouveau_therm_temp_safety_checks(struct nouveau_therm *therm)
}
/* must be called with alarm_program_lock taken ! */
-void nouveau_therm_sensor_set_threshold_state(struct nouveau_therm *therm,
- enum nouveau_therm_thrs thrs,
- enum nouveau_therm_thrs_state st)
+void
+nvkm_therm_sensor_set_threshold_state(struct nvkm_therm *therm,
+ enum nvkm_therm_thrs thrs,
+ enum nvkm_therm_thrs_state st)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
priv->sensor.alarm_state[thrs] = st;
}
/* must be called with alarm_program_lock taken ! */
-enum nouveau_therm_thrs_state
-nouveau_therm_sensor_get_threshold_state(struct nouveau_therm *therm,
- enum nouveau_therm_thrs thrs)
+enum nvkm_therm_thrs_state
+nvkm_therm_sensor_get_threshold_state(struct nvkm_therm *therm,
+ enum nvkm_therm_thrs thrs)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
return priv->sensor.alarm_state[thrs];
}
@@ -88,11 +83,11 @@ nv_poweroff_work(struct work_struct *work)
kfree(work);
}
-void nouveau_therm_sensor_event(struct nouveau_therm *therm,
- enum nouveau_therm_thrs thrs,
- enum nouveau_therm_thrs_direction dir)
+void
+nvkm_therm_sensor_event(struct nvkm_therm *therm, enum nvkm_therm_thrs thrs,
+ enum nvkm_therm_thrs_direction dir)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
bool active;
const char *thresolds[] = {
"fanboost", "downclock", "critical", "shutdown"
@@ -102,30 +97,30 @@ void nouveau_therm_sensor_event(struct nouveau_therm *therm,
if (thrs < 0 || thrs > 3)
return;
- if (dir == NOUVEAU_THERM_THRS_FALLING)
+ if (dir == NVKM_THERM_THRS_FALLING)
nv_info(therm, "temperature (%i C) went below the '%s' threshold\n",
temperature, thresolds[thrs]);
else
nv_info(therm, "temperature (%i C) hit the '%s' threshold\n",
temperature, thresolds[thrs]);
- active = (dir == NOUVEAU_THERM_THRS_RISING);
+ active = (dir == NVKM_THERM_THRS_RISING);
switch (thrs) {
- case NOUVEAU_THERM_THRS_FANBOOST:
+ case NVKM_THERM_THRS_FANBOOST:
if (active) {
- nouveau_therm_fan_set(therm, true, 100);
- nouveau_therm_fan_mode(therm, NOUVEAU_THERM_CTRL_AUTO);
+ nvkm_therm_fan_set(therm, true, 100);
+ nvkm_therm_fan_mode(therm, NVKM_THERM_CTRL_AUTO);
}
break;
- case NOUVEAU_THERM_THRS_DOWNCLOCK:
+ case NVKM_THERM_THRS_DOWNCLOCK:
if (priv->emergency.downclock)
priv->emergency.downclock(therm, active);
break;
- case NOUVEAU_THERM_THRS_CRITICAL:
+ case NVKM_THERM_THRS_CRITICAL:
if (priv->emergency.pause)
priv->emergency.pause(therm, active);
break;
- case NOUVEAU_THERM_THRS_SHUTDOWN:
+ case NVKM_THERM_THRS_SHUTDOWN:
if (active) {
struct work_struct *work;
@@ -136,7 +131,7 @@ void nouveau_therm_sensor_event(struct nouveau_therm *therm,
}
}
break;
- case NOUVEAU_THERM_THRS_NR:
+ case NVKM_THERM_THRS_NR:
break;
}
@@ -144,53 +139,53 @@ void nouveau_therm_sensor_event(struct nouveau_therm *therm,
/* must be called with alarm_program_lock taken ! */
static void
-nouveau_therm_threshold_hyst_polling(struct nouveau_therm *therm,
- const struct nvbios_therm_threshold *thrs,
- enum nouveau_therm_thrs thrs_name)
+nvkm_therm_threshold_hyst_polling(struct nvkm_therm *therm,
+ const struct nvbios_therm_threshold *thrs,
+ enum nvkm_therm_thrs thrs_name)
{
- enum nouveau_therm_thrs_direction direction;
- enum nouveau_therm_thrs_state prev_state, new_state;
+ enum nvkm_therm_thrs_direction direction;
+ enum nvkm_therm_thrs_state prev_state, new_state;
int temp = therm->temp_get(therm);
- prev_state = nouveau_therm_sensor_get_threshold_state(therm, thrs_name);
+ prev_state = nvkm_therm_sensor_get_threshold_state(therm, thrs_name);
- if (temp >= thrs->temp && prev_state == NOUVEAU_THERM_THRS_LOWER) {
- direction = NOUVEAU_THERM_THRS_RISING;
- new_state = NOUVEAU_THERM_THRS_HIGHER;
+ if (temp >= thrs->temp && prev_state == NVKM_THERM_THRS_LOWER) {
+ direction = NVKM_THERM_THRS_RISING;
+ new_state = NVKM_THERM_THRS_HIGHER;
} else if (temp <= thrs->temp - thrs->hysteresis &&
- prev_state == NOUVEAU_THERM_THRS_HIGHER) {
- direction = NOUVEAU_THERM_THRS_FALLING;
- new_state = NOUVEAU_THERM_THRS_LOWER;
+ prev_state == NVKM_THERM_THRS_HIGHER) {
+ direction = NVKM_THERM_THRS_FALLING;
+ new_state = NVKM_THERM_THRS_LOWER;
} else
return; /* nothing to do */
- nouveau_therm_sensor_set_threshold_state(therm, thrs_name, new_state);
- nouveau_therm_sensor_event(therm, thrs_name, direction);
+ nvkm_therm_sensor_set_threshold_state(therm, thrs_name, new_state);
+ nvkm_therm_sensor_event(therm, thrs_name, direction);
}
static void
-alarm_timer_callback(struct nouveau_alarm *alarm)
+alarm_timer_callback(struct nvkm_alarm *alarm)
{
- struct nouveau_therm_priv *priv =
- container_of(alarm, struct nouveau_therm_priv, sensor.therm_poll_alarm);
+ struct nvkm_therm_priv *priv =
+ container_of(alarm, struct nvkm_therm_priv, sensor.therm_poll_alarm);
struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
- struct nouveau_timer *ptimer = nouveau_timer(priv);
- struct nouveau_therm *therm = &priv->base;
+ struct nvkm_timer *ptimer = nvkm_timer(priv);
+ struct nvkm_therm *therm = &priv->base;
unsigned long flags;
spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);
- nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_fan_boost,
- NOUVEAU_THERM_THRS_FANBOOST);
+ nvkm_therm_threshold_hyst_polling(therm, &sensor->thrs_fan_boost,
+ NVKM_THERM_THRS_FANBOOST);
- nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_down_clock,
- NOUVEAU_THERM_THRS_DOWNCLOCK);
+ nvkm_therm_threshold_hyst_polling(therm, &sensor->thrs_down_clock,
+ NVKM_THERM_THRS_DOWNCLOCK);
- nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_critical,
- NOUVEAU_THERM_THRS_CRITICAL);
+ nvkm_therm_threshold_hyst_polling(therm, &sensor->thrs_critical,
+ NVKM_THERM_THRS_CRITICAL);
- nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_shutdown,
- NOUVEAU_THERM_THRS_SHUTDOWN);
+ nvkm_therm_threshold_hyst_polling(therm, &sensor->thrs_shutdown,
+ NVKM_THERM_THRS_SHUTDOWN);
spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
@@ -200,9 +195,9 @@ alarm_timer_callback(struct nouveau_alarm *alarm)
}
void
-nouveau_therm_program_alarms_polling(struct nouveau_therm *therm)
+nvkm_therm_program_alarms_polling(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
nv_debug(therm,
@@ -217,18 +212,18 @@ nouveau_therm_program_alarms_polling(struct nouveau_therm *therm)
}
int
-nouveau_therm_sensor_init(struct nouveau_therm *therm)
+nvkm_therm_sensor_init(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
+ struct nvkm_therm_priv *priv = (void *)therm;
priv->sensor.program_alarms(therm);
return 0;
}
int
-nouveau_therm_sensor_fini(struct nouveau_therm *therm, bool suspend)
+nvkm_therm_sensor_fini(struct nvkm_therm *therm, bool suspend)
{
- struct nouveau_therm_priv *priv = (void *)therm;
- struct nouveau_timer *ptimer = nouveau_timer(therm);
+ struct nvkm_therm_priv *priv = (void *)therm;
+ struct nvkm_timer *ptimer = nvkm_timer(therm);
if (suspend)
ptimer->alarm_cancel(ptimer, &priv->sensor.therm_poll_alarm);
@@ -236,7 +231,7 @@ nouveau_therm_sensor_fini(struct nouveau_therm *therm, bool suspend)
}
void
-nouveau_therm_sensor_preinit(struct nouveau_therm *therm)
+nvkm_therm_sensor_preinit(struct nvkm_therm *therm)
{
const char *sensor_avail = "yes";
@@ -247,18 +242,18 @@ nouveau_therm_sensor_preinit(struct nouveau_therm *therm)
}
int
-nouveau_therm_sensor_ctor(struct nouveau_therm *therm)
+nvkm_therm_sensor_ctor(struct nvkm_therm *therm)
{
- struct nouveau_therm_priv *priv = (void *)therm;
- struct nouveau_bios *bios = nouveau_bios(therm);
+ struct nvkm_therm_priv *priv = (void *)therm;
+ struct nvkm_bios *bios = nvkm_bios(therm);
- nouveau_alarm_init(&priv->sensor.therm_poll_alarm, alarm_timer_callback);
+ nvkm_alarm_init(&priv->sensor.therm_poll_alarm, alarm_timer_callback);
- nouveau_therm_temp_set_defaults(therm);
+ nvkm_therm_temp_set_defaults(therm);
if (nvbios_therm_sensor_parse(bios, NVBIOS_THERM_DOMAIN_CORE,
&priv->bios_sensor))
nv_error(therm, "nvbios_therm_sensor_parse failed\n");
- nouveau_therm_temp_safety_checks(therm);
+ nvkm_therm_temp_safety_checks(therm);
return 0;
}
From 9e79a85343e2191ac83f0ef4fe49b71b9d80ad38 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:12:11 +1000
Subject: [PATCH 68/86] drm/nouveau/timer: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/subdev/timer.h | 71 +++++++++----------
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c | 1 +
.../gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 1 +
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 1 +
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 1 +
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 1 +
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 1 +
drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h | 1 +
.../gpu/drm/nouveau/nvkm/subdev/bar/nv50.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/clk/gf100.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/clk/gk104.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c | 2 +
.../gpu/drm/nouveau/nvkm/subdev/clk/gt215.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c | 1 +
.../drm/nouveau/nvkm/subdev/therm/fanpwm.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/therm/gf110.c | 2 +
.../gpu/drm/nouveau/nvkm/subdev/therm/gm107.c | 2 +
.../gpu/drm/nouveau/nvkm/subdev/therm/gt215.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/therm/nv40.c | 2 +
.../gpu/drm/nouveau/nvkm/subdev/therm/nv50.c | 2 +
.../gpu/drm/nouveau/nvkm/subdev/timer/base.c | 23 +++---
.../gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c | 9 ++-
.../gpu/drm/nouveau/nvkm/subdev/timer/nv04.c | 48 ++++++-------
.../gpu/drm/nouveau/nvkm/subdev/timer/nv04.h | 14 ++--
.../gpu/drm/nouveau/nvkm/subdev/timer/priv.h | 2 -
26 files changed, 103 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
index 36b5184e35ec..4ad55082ef7a 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
@@ -1,64 +1,61 @@
-#ifndef __NOUVEAU_TIMER_H__
-#define __NOUVEAU_TIMER_H__
-
+#ifndef __NVKM_TIMER_H__
+#define __NVKM_TIMER_H__
#include <core/subdev.h>
-#include <core/device.h>
-struct nouveau_alarm {
+struct nvkm_alarm {
struct list_head head;
u64 timestamp;
- void (*func)(struct nouveau_alarm *);
+ void (*func)(struct nvkm_alarm *);
};
static inline void
-nouveau_alarm_init(struct nouveau_alarm *alarm,
- void (*func)(struct nouveau_alarm *))
+nvkm_alarm_init(struct nvkm_alarm *alarm,
+ void (*func)(struct nvkm_alarm *))
{
INIT_LIST_HEAD(&alarm->head);
alarm->func = func;
}
-bool nouveau_timer_wait_eq(void *, u64 nsec, u32 addr, u32 mask, u32 data);
-bool nouveau_timer_wait_ne(void *, u64 nsec, u32 addr, u32 mask, u32 data);
-bool nouveau_timer_wait_cb(void *, u64 nsec, bool (*func)(void *), void *data);
-void nouveau_timer_alarm(void *, u32 nsec, struct nouveau_alarm *);
-void nouveau_timer_alarm_cancel(void *, struct nouveau_alarm *);
+bool nvkm_timer_wait_eq(void *, u64 nsec, u32 addr, u32 mask, u32 data);
+bool nvkm_timer_wait_ne(void *, u64 nsec, u32 addr, u32 mask, u32 data);
+bool nvkm_timer_wait_cb(void *, u64 nsec, bool (*func)(void *), void *data);
+void nvkm_timer_alarm(void *, u32 nsec, struct nvkm_alarm *);
+void nvkm_timer_alarm_cancel(void *, struct nvkm_alarm *);
#define NV_WAIT_DEFAULT 2000000000ULL
#define nv_wait(o,a,m,v) \
- nouveau_timer_wait_eq((o), NV_WAIT_DEFAULT, (a), (m), (v))
+ nvkm_timer_wait_eq((o), NV_WAIT_DEFAULT, (a), (m), (v))
#define nv_wait_ne(o,a,m,v) \
- nouveau_timer_wait_ne((o), NV_WAIT_DEFAULT, (a), (m), (v))
+ nvkm_timer_wait_ne((o), NV_WAIT_DEFAULT, (a), (m), (v))
#define nv_wait_cb(o,c,d) \
- nouveau_timer_wait_cb((o), NV_WAIT_DEFAULT, (c), (d))
+ nvkm_timer_wait_cb((o), NV_WAIT_DEFAULT, (c), (d))
-struct nouveau_timer {
- struct nouveau_subdev base;
- u64 (*read)(struct nouveau_timer *);
- void (*alarm)(struct nouveau_timer *, u64 time, struct nouveau_alarm *);
- void (*alarm_cancel)(struct nouveau_timer *, struct nouveau_alarm *);
+struct nvkm_timer {
+ struct nvkm_subdev base;
+ u64 (*read)(struct nvkm_timer *);
+ void (*alarm)(struct nvkm_timer *, u64 time, struct nvkm_alarm *);
+ void (*alarm_cancel)(struct nvkm_timer *, struct nvkm_alarm *);
};
-static inline struct nouveau_timer *
-nouveau_timer(void *obj)
+static inline struct nvkm_timer *
+nvkm_timer(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_TIMER);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_TIMER);
}
-#define nouveau_timer_create(p,e,o,d) \
- nouveau_subdev_create_((p), (e), (o), 0, "PTIMER", "timer", \
+#define nvkm_timer_create(p,e,o,d) \
+ nvkm_subdev_create_((p), (e), (o), 0, "PTIMER", "timer", \
sizeof(**d), (void **)d)
-#define nouveau_timer_destroy(p) \
- nouveau_subdev_destroy(&(p)->base)
-#define nouveau_timer_init(p) \
- nouveau_subdev_init(&(p)->base)
-#define nouveau_timer_fini(p,s) \
- nouveau_subdev_fini(&(p)->base, (s))
+#define nvkm_timer_destroy(p) \
+ nvkm_subdev_destroy(&(p)->base)
+#define nvkm_timer_init(p) \
+ nvkm_subdev_init(&(p)->base)
+#define nvkm_timer_fini(p,s) \
+ nvkm_subdev_fini(&(p)->base, (s))
-int nouveau_timer_create_(struct nouveau_object *, struct nouveau_engine *,
- struct nouveau_oclass *, int size, void **);
-
-extern struct nouveau_oclass nv04_timer_oclass;
-extern struct nouveau_oclass gk20a_timer_oclass;
+int nvkm_timer_create_(struct nvkm_object *, struct nvkm_engine *,
+ struct nvkm_oclass *, int size, void **);
+extern struct nvkm_oclass nv04_timer_oclass;
+extern struct nvkm_oclass gk20a_timer_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
index f6e9ae95c822..30958c19e61d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
@@ -21,6 +21,7 @@
*/
#include <engine/falcon.h>
+#include <core/device.h>
#include <subdev/timer.h>
void
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
index 6f51ae0daecf..1b384bd5994e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
@@ -23,6 +23,7 @@
*/
#include <core/client.h>
+#include <core/device.h>
#include <nvif/unpack.h>
#include <nvif/class.h>
#include <core/engctx.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
index 4d25c9532b2b..5dda6ed846ba 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
@@ -23,6 +23,7 @@
*/
#include <core/client.h>
+#include <core/device.h>
#include <core/os.h>
#include <core/handle.h>
#include <core/namedb.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
index 8caf0c338425..9841b4e5964d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
@@ -1,4 +1,5 @@
#include <core/client.h>
+#include <core/device.h>
#include <core/os.h>
#include <core/engctx.h>
#include <core/handle.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
index d9d85508cbcf..6a8e0022f8af 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
@@ -1,4 +1,5 @@
#include <core/os.h>
+#include <core/device.h>
#include <core/engctx.h>
#include <core/enum.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
index bd7687c683c8..9d7fcbd96522 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
@@ -24,6 +24,7 @@
#include <core/os.h>
#include <core/client.h>
+#include <core/device.h>
#include <core/handle.h>
#include <core/engctx.h>
#include <core/enum.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
index 413def63be0e..2f2ed95fe936 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
@@ -26,6 +26,7 @@
#define __NVC0_GR_H__
#include <core/client.h>
+#include <core/device.h>
#include <core/handle.h>
#include <core/gpuobj.h>
#include <core/option.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
index 36c5c083c1e9..8548adb91dcc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
@@ -23,6 +23,7 @@
*/
#include "priv.h"
+#include <core/device.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
index e8125b5199a4..3d7330d54b02 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
@@ -24,6 +24,7 @@
#include <subdev/clk.h>
#include "pll.h"
+#include <core/device.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
index e380d62df232..e9b2310bdfbb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
@@ -24,6 +24,7 @@
#include <subdev/clk.h>
#include "pll.h"
+#include <core/device.h>
#include <subdev/timer.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
index 94d3839fd444..65c532742b08 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
@@ -25,6 +25,8 @@
#include <subdev/clk.h>
#include <subdev/timer.h>
+#include <core/device.h>
+
#ifdef __KERNEL__
#include <nouveau_platform.h>
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
index 99e3ca3b0890..822d32a28d6e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
@@ -25,6 +25,7 @@
#include "gt215.h"
#include "pll.h"
+#include <core/device.h>
#include <engine/fifo.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
index d735de2dbd74..c54417b146c7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
@@ -24,6 +24,7 @@
#include "gt215.h"
#include "pll.h"
+#include <core/device.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
index a36a90c29ba9..3d31fa45c1a6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
@@ -23,6 +23,7 @@
*/
#include "nv40.h"
+#include <core/device.h>
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/init.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c
index 3cf4192a33af..bde5ceaeb70a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c
@@ -24,6 +24,7 @@
*/
#include "priv.h"
+#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/fan.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c
index 0540e6886d7d..46b7e656a752 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c
@@ -23,6 +23,8 @@
*/
#include "priv.h"
+#include <core/device.h>
+
struct gf110_therm_priv {
struct nvkm_therm_priv base;
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c
index c1f3cf361837..2fd110f09878 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c
@@ -23,6 +23,8 @@
*/
#include "priv.h"
+#include <core/device.h>
+
struct gm107_therm_priv {
struct nvkm_therm_priv base;
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c
index b7fa4716ca9f..e99be20332f2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c
@@ -23,6 +23,7 @@
*/
#include "priv.h"
+#include <core/device.h>
#include <subdev/gpio.h>
struct gt215_therm_priv {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c
index 20f65fd7679a..8496fffd4688 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c
@@ -24,6 +24,8 @@
*/
#include "priv.h"
+#include <core/device.h>
+
struct nv40_therm_priv {
struct nvkm_therm_priv base;
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c
index 489dcf355d34..1ef59e8922d4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c
@@ -24,6 +24,8 @@
*/
#include "priv.h"
+#include <core/device.h>
+
struct nv50_therm_priv {
struct nvkm_therm_priv base;
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c
index cf8a0e0f8ee3..d894061ced52 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c
@@ -21,13 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
-#include "subdev/timer.h"
+#include <subdev/timer.h>
bool
-nouveau_timer_wait_eq(void *obj, u64 nsec, u32 addr, u32 mask, u32 data)
+nvkm_timer_wait_eq(void *obj, u64 nsec, u32 addr, u32 mask, u32 data)
{
- struct nouveau_timer *ptimer = nouveau_timer(obj);
+ struct nvkm_timer *ptimer = nvkm_timer(obj);
u64 time0;
time0 = ptimer->read(ptimer);
@@ -45,9 +44,9 @@ nouveau_timer_wait_eq(void *obj, u64 nsec, u32 addr, u32 mask, u32 data)
}
bool
-nouveau_timer_wait_ne(void *obj, u64 nsec, u32 addr, u32 mask, u32 data)
+nvkm_timer_wait_ne(void *obj, u64 nsec, u32 addr, u32 mask, u32 data)
{
- struct nouveau_timer *ptimer = nouveau_timer(obj);
+ struct nvkm_timer *ptimer = nvkm_timer(obj);
u64 time0;
time0 = ptimer->read(ptimer);
@@ -65,9 +64,9 @@ nouveau_timer_wait_ne(void *obj, u64 nsec, u32 addr, u32 mask, u32 data)
}
bool
-nouveau_timer_wait_cb(void *obj, u64 nsec, bool (*func)(void *), void *data)
+nvkm_timer_wait_cb(void *obj, u64 nsec, bool (*func)(void *), void *data)
{
- struct nouveau_timer *ptimer = nouveau_timer(obj);
+ struct nvkm_timer *ptimer = nvkm_timer(obj);
u64 time0;
time0 = ptimer->read(ptimer);
@@ -80,15 +79,15 @@ nouveau_timer_wait_cb(void *obj, u64 nsec, bool (*func)(void *), void *data)
}
void
-nouveau_timer_alarm(void *obj, u32 nsec, struct nouveau_alarm *alarm)
+nvkm_timer_alarm(void *obj, u32 nsec, struct nvkm_alarm *alarm)
{
- struct nouveau_timer *ptimer = nouveau_timer(obj);
+ struct nvkm_timer *ptimer = nvkm_timer(obj);
ptimer->alarm(ptimer, nsec, alarm);
}
void
-nouveau_timer_alarm_cancel(void *obj, struct nouveau_alarm *alarm)
+nvkm_timer_alarm_cancel(void *obj, struct nvkm_alarm *alarm)
{
- struct nouveau_timer *ptimer = nouveau_timer(obj);
+ struct nvkm_timer *ptimer = nvkm_timer(obj);
ptimer->alarm_cancel(ptimer, alarm);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c
index 37484db1f7fc..80e38063dd9b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c
@@ -21,18 +21,17 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
static int
-gk20a_timer_init(struct nouveau_object *object)
+gk20a_timer_init(struct nvkm_object *object)
{
struct nv04_timer_priv *priv = (void *)object;
u32 hi = upper_32_bits(priv->suspend_time);
u32 lo = lower_32_bits(priv->suspend_time);
int ret;
- ret = nouveau_timer_init(&priv->base);
+ ret = nvkm_timer_init(&priv->base);
if (ret)
return ret;
@@ -45,10 +44,10 @@ gk20a_timer_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
gk20a_timer_oclass = {
.handle = NV_SUBDEV(TIMER, 0xff),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_timer_ctor,
.dtor = nv04_timer_dtor,
.init = gk20a_timer_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
index 240ed0b983a9..6b7facbe59a2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
@@ -21,11 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv04.h"
+#include <core/device.h>
+
static u64
-nv04_timer_read(struct nouveau_timer *ptimer)
+nv04_timer_read(struct nvkm_timer *ptimer)
{
struct nv04_timer_priv *priv = (void *)ptimer;
u32 hi, lo;
@@ -39,10 +40,10 @@ nv04_timer_read(struct nouveau_timer *ptimer)
}
static void
-nv04_timer_alarm_trigger(struct nouveau_timer *ptimer)
+nv04_timer_alarm_trigger(struct nvkm_timer *ptimer)
{
struct nv04_timer_priv *priv = (void *)ptimer;
- struct nouveau_alarm *alarm, *atemp;
+ struct nvkm_alarm *alarm, *atemp;
unsigned long flags;
LIST_HEAD(exec);
@@ -71,11 +72,10 @@ nv04_timer_alarm_trigger(struct nouveau_timer *ptimer)
}
static void
-nv04_timer_alarm(struct nouveau_timer *ptimer, u64 time,
- struct nouveau_alarm *alarm)
+nv04_timer_alarm(struct nvkm_timer *ptimer, u64 time, struct nvkm_alarm *alarm)
{
struct nv04_timer_priv *priv = (void *)ptimer;
- struct nouveau_alarm *list;
+ struct nvkm_alarm *list;
unsigned long flags;
alarm->timestamp = ptimer->read(ptimer) + time;
@@ -99,8 +99,7 @@ nv04_timer_alarm(struct nouveau_timer *ptimer, u64 time,
}
static void
-nv04_timer_alarm_cancel(struct nouveau_timer *ptimer,
- struct nouveau_alarm *alarm)
+nv04_timer_alarm_cancel(struct nvkm_timer *ptimer, struct nvkm_alarm *alarm)
{
struct nv04_timer_priv *priv = (void *)ptimer;
unsigned long flags;
@@ -110,7 +109,7 @@ nv04_timer_alarm_cancel(struct nouveau_timer *ptimer,
}
static void
-nv04_timer_intr(struct nouveau_subdev *subdev)
+nv04_timer_intr(struct nvkm_subdev *subdev)
{
struct nv04_timer_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, NV04_PTIMER_INTR_0);
@@ -128,24 +127,24 @@ nv04_timer_intr(struct nouveau_subdev *subdev)
}
int
-nv04_timer_fini(struct nouveau_object *object, bool suspend)
+nv04_timer_fini(struct nvkm_object *object, bool suspend)
{
struct nv04_timer_priv *priv = (void *)object;
if (suspend)
priv->suspend_time = nv04_timer_read(&priv->base);
nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);
- return nouveau_timer_fini(&priv->base, suspend);
+ return nvkm_timer_fini(&priv->base, suspend);
}
static int
-nv04_timer_init(struct nouveau_object *object)
+nv04_timer_init(struct nvkm_object *object)
{
- struct nouveau_device *device = nv_device(object);
+ struct nvkm_device *device = nv_device(object);
struct nv04_timer_priv *priv = (void *)object;
u32 m = 1, f, n, d, lo, hi;
int ret;
- ret = nouveau_timer_init(&priv->base);
+ ret = nvkm_timer_init(&priv->base);
if (ret)
return ret;
@@ -155,7 +154,7 @@ nv04_timer_init(struct nouveau_object *object)
/* determine base clock for timer source */
#if 0 /*XXX*/
if (device->chipset < 0x40) {
- n = nouveau_hw_get_clock(device, PLL_CORE);
+ n = nvkm_hw_get_clock(device, PLL_CORE);
} else
#endif
if (device->chipset <= 0x40) {
@@ -217,26 +216,25 @@ nv04_timer_init(struct nouveau_object *object)
nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);
nv_wr32(priv, NV04_PTIMER_TIME_1, hi);
nv_wr32(priv, NV04_PTIMER_TIME_0, lo);
-
return 0;
}
void
-nv04_timer_dtor(struct nouveau_object *object)
+nv04_timer_dtor(struct nvkm_object *object)
{
struct nv04_timer_priv *priv = (void *)object;
- return nouveau_timer_destroy(&priv->base);
+ return nvkm_timer_destroy(&priv->base);
}
int
-nv04_timer_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_timer_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_timer_priv *priv;
int ret;
- ret = nouveau_timer_create(parent, engine, oclass, &priv);
+ ret = nvkm_timer_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -252,10 +250,10 @@ nv04_timer_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv04_timer_oclass = {
.handle = NV_SUBDEV(TIMER, 0x04),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_timer_ctor,
.dtor = nv04_timer_dtor,
.init = nv04_timer_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h
index 4bc152697c37..89996a9826b1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h
@@ -1,6 +1,5 @@
#ifndef __NVKM_TIMER_NV04_H__
#define __NVKM_TIMER_NV04_H__
-
#include "priv.h"
#define NV04_PTIMER_INTR_0 0x009100
@@ -12,16 +11,15 @@
#define NV04_PTIMER_ALARM_0 0x009420
struct nv04_timer_priv {
- struct nouveau_timer base;
+ struct nvkm_timer base;
struct list_head alarms;
spinlock_t lock;
u64 suspend_time;
};
-int nv04_timer_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nv04_timer_dtor(struct nouveau_object *);
-int nv04_timer_fini(struct nouveau_object *, bool);
-
+int nv04_timer_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void nv04_timer_dtor(struct nvkm_object *);
+int nv04_timer_fini(struct nvkm_object *, bool);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h
index 799dae3f2300..08e29a3da188 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h
@@ -1,6 +1,4 @@
#ifndef __NVKM_TIMER_PRIV_H__
#define __NVKM_TIMER_PRIV_H__
-
#include <subdev/timer.h>
-
#endif
From de3aaa6651ed7075e293c4e48c482012e8e8c87d Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:13:36 +1000
Subject: [PATCH 69/86] drm/nouveau/volt: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/subdev/volt.h | 69 +++++++++----------
.../gpu/drm/nouveau/nvkm/subdev/clk/base.c | 1 +
.../gpu/drm/nouveau/nvkm/subdev/volt/base.c | 65 +++++++++--------
.../gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c | 36 +++++-----
.../gpu/drm/nouveau/nvkm/subdev/volt/gpio.c | 16 ++---
.../gpu/drm/nouveau/nvkm/subdev/volt/nv40.c | 21 +++---
6 files changed, 100 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
index 13e9a83ceccc..e3d7243fbb1d 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
@@ -1,22 +1,20 @@
-#ifndef __NOUVEAU_VOLT_H__
-#define __NOUVEAU_VOLT_H__
-
+#ifndef __NVKM_VOLT_H__
+#define __NVKM_VOLT_H__
#include <core/subdev.h>
-#include <core/device.h>
-struct nouveau_voltage {
+struct nvkm_voltage {
u32 uv;
u8 id;
};
-struct nouveau_volt {
- struct nouveau_subdev base;
+struct nvkm_volt {
+ struct nvkm_subdev base;
- int (*vid_get)(struct nouveau_volt *);
- int (*get)(struct nouveau_volt *);
- int (*vid_set)(struct nouveau_volt *, u8 vid);
- int (*set)(struct nouveau_volt *, u32 uv);
- int (*set_id)(struct nouveau_volt *, u8 id, int condition);
+ int (*vid_get)(struct nvkm_volt *);
+ int (*get)(struct nvkm_volt *);
+ int (*vid_set)(struct nvkm_volt *, u8 vid);
+ int (*set)(struct nvkm_volt *, u32 uv);
+ int (*set_id)(struct nvkm_volt *, u8 id, int condition);
u8 vid_mask;
u8 vid_nr;
@@ -26,36 +24,35 @@ struct nouveau_volt {
} vid[256];
};
-static inline struct nouveau_volt *
-nouveau_volt(void *obj)
+static inline struct nvkm_volt *
+nvkm_volt(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_VOLT);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_VOLT);
}
-#define nouveau_volt_create(p, e, o, d) \
- nouveau_volt_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_volt_destroy(p) ({ \
- struct nouveau_volt *v = (p); \
- _nouveau_volt_dtor(nv_object(v)); \
+#define nvkm_volt_create(p, e, o, d) \
+ nvkm_volt_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_volt_destroy(p) ({ \
+ struct nvkm_volt *v = (p); \
+ _nvkm_volt_dtor(nv_object(v)); \
})
-#define nouveau_volt_init(p) ({ \
- struct nouveau_volt *v = (p); \
- _nouveau_volt_init(nv_object(v)); \
+#define nvkm_volt_init(p) ({ \
+ struct nvkm_volt *v = (p); \
+ _nvkm_volt_init(nv_object(v)); \
})
-#define nouveau_volt_fini(p,s) \
- nouveau_subdev_fini((p), (s))
+#define nvkm_volt_fini(p,s) \
+ nvkm_subdev_fini((p), (s))
-int nouveau_volt_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-void _nouveau_volt_dtor(struct nouveau_object *);
-int _nouveau_volt_init(struct nouveau_object *);
-#define _nouveau_volt_fini _nouveau_subdev_fini
+int nvkm_volt_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+void _nvkm_volt_dtor(struct nvkm_object *);
+int _nvkm_volt_init(struct nvkm_object *);
+#define _nvkm_volt_fini _nvkm_subdev_fini
-extern struct nouveau_oclass nv40_volt_oclass;
-extern struct nouveau_oclass gk20a_volt_oclass;
-
-int nouveau_voltgpio_init(struct nouveau_volt *);
-int nouveau_voltgpio_get(struct nouveau_volt *);
-int nouveau_voltgpio_set(struct nouveau_volt *, u8);
+extern struct nvkm_oclass nv40_volt_oclass;
+extern struct nvkm_oclass gk20a_volt_oclass;
+int nvkm_voltgpio_init(struct nvkm_volt *);
+int nvkm_voltgpio_get(struct nvkm_volt *);
+int nvkm_voltgpio_set(struct nvkm_volt *, u8);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
index adfd3d93e066..b24a9cc04b73 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
@@ -30,6 +30,7 @@
#include <subdev/therm.h>
#include <subdev/volt.h>
+#include <core/device.h>
#include <core/option.h>
/******************************************************************************
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
index 26ccd8df193f..39f15803f2d4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
@@ -21,15 +21,13 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/volt.h>
-
#include <subdev/bios.h>
#include <subdev/bios/vmap.h>
#include <subdev/bios/volt.h>
static int
-nouveau_volt_get(struct nouveau_volt *volt)
+nvkm_volt_get(struct nvkm_volt *volt)
{
if (volt->vid_get) {
int ret = volt->vid_get(volt), i;
@@ -46,7 +44,7 @@ nouveau_volt_get(struct nouveau_volt *volt)
}
static int
-nouveau_volt_set(struct nouveau_volt *volt, u32 uv)
+nvkm_volt_set(struct nvkm_volt *volt, u32 uv)
{
if (volt->vid_set) {
int i, ret = -EINVAL;
@@ -63,9 +61,9 @@ nouveau_volt_set(struct nouveau_volt *volt, u32 uv)
}
static int
-nouveau_volt_map(struct nouveau_volt *volt, u8 id)
+nvkm_volt_map(struct nvkm_volt *volt, u8 id)
{
- struct nouveau_bios *bios = nouveau_bios(volt);
+ struct nvkm_bios *bios = nvkm_bios(volt);
struct nvbios_vmap_entry info;
u8 ver, len;
u16 vmap;
@@ -73,7 +71,7 @@ nouveau_volt_map(struct nouveau_volt *volt, u8 id)
vmap = nvbios_vmap_entry_parse(bios, id, &ver, &len, &info);
if (vmap) {
if (info.link != 0xff) {
- int ret = nouveau_volt_map(volt, info.link);
+ int ret = nvkm_volt_map(volt, info.link);
if (ret < 0)
return ret;
info.min += ret;
@@ -85,15 +83,15 @@ nouveau_volt_map(struct nouveau_volt *volt, u8 id)
}
static int
-nouveau_volt_set_id(struct nouveau_volt *volt, u8 id, int condition)
+nvkm_volt_set_id(struct nvkm_volt *volt, u8 id, int condition)
{
- int ret = nouveau_volt_map(volt, id);
+ int ret = nvkm_volt_map(volt, id);
if (ret >= 0) {
- int prev = nouveau_volt_get(volt);
+ int prev = nvkm_volt_get(volt);
if (!condition || prev < 0 ||
(condition < 0 && ret < prev) ||
(condition > 0 && ret > prev)) {
- ret = nouveau_volt_set(volt, ret);
+ ret = nvkm_volt_set(volt, ret);
} else {
ret = 0;
}
@@ -101,8 +99,8 @@ nouveau_volt_set_id(struct nouveau_volt *volt, u8 id, int condition)
return ret;
}
-static void nouveau_volt_parse_bios(struct nouveau_bios *bios,
- struct nouveau_volt *volt)
+static void
+nvkm_volt_parse_bios(struct nvkm_bios *bios, struct nvkm_volt *volt)
{
struct nvbios_volt_entry ivid;
struct nvbios_volt info;
@@ -125,7 +123,7 @@ static void nouveau_volt_parse_bios(struct nouveau_bios *bios,
} else if (data && info.vidmask) {
for (i = 0; i < cnt; i++) {
data = nvbios_volt_entry_parse(bios, i, &ver, &hdr,
- &ivid);
+ &ivid);
if (data) {
volt->vid[volt->vid_nr].uv = ivid.voltage;
volt->vid[volt->vid_nr].vid = ivid.vid;
@@ -137,12 +135,12 @@ static void nouveau_volt_parse_bios(struct nouveau_bios *bios,
}
int
-_nouveau_volt_init(struct nouveau_object *object)
+_nvkm_volt_init(struct nvkm_object *object)
{
- struct nouveau_volt *volt = (void *)object;
+ struct nvkm_volt *volt = (void *)object;
int ret;
- ret = nouveau_subdev_init(&volt->base);
+ ret = nvkm_subdev_init(&volt->base);
if (ret)
return ret;
@@ -158,34 +156,33 @@ _nouveau_volt_init(struct nouveau_object *object)
}
void
-_nouveau_volt_dtor(struct nouveau_object *object)
+_nvkm_volt_dtor(struct nvkm_object *object)
{
- struct nouveau_volt *volt = (void *)object;
- nouveau_subdev_destroy(&volt->base);
+ struct nvkm_volt *volt = (void *)object;
+ nvkm_subdev_destroy(&volt->base);
}
int
-nouveau_volt_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int length, void **pobject)
+nvkm_volt_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
- struct nouveau_bios *bios = nouveau_bios(parent);
- struct nouveau_volt *volt;
+ struct nvkm_bios *bios = nvkm_bios(parent);
+ struct nvkm_volt *volt;
int ret, i;
- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "VOLT",
- "voltage", length, pobject);
+ ret = nvkm_subdev_create_(parent, engine, oclass, 0, "VOLT",
+ "voltage", length, pobject);
volt = *pobject;
if (ret)
return ret;
- volt->get = nouveau_volt_get;
- volt->set = nouveau_volt_set;
- volt->set_id = nouveau_volt_set_id;
+ volt->get = nvkm_volt_get;
+ volt->set = nvkm_volt_set;
+ volt->set_id = nvkm_volt_set_id;
/* Assuming the non-bios device should build the voltage table later */
if (bios)
- nouveau_volt_parse_bios(bios, volt);
+ nvkm_volt_parse_bios(bios, volt);
if (volt->vid_nr) {
for (i = 0; i < volt->vid_nr; i++) {
@@ -196,10 +193,10 @@ nouveau_volt_create_(struct nouveau_object *parent,
/*XXX: this is an assumption.. there probably exists boards
* out there with i2c-connected voltage controllers too..
*/
- ret = nouveau_voltgpio_init(volt);
+ ret = nvkm_voltgpio_init(volt);
if (ret == 0) {
- volt->vid_get = nouveau_voltgpio_get;
- volt->vid_set = nouveau_voltgpio_set;
+ volt->vid_get = nvkm_voltgpio_get;
+ volt->vid_set = nvkm_voltgpio_set;
}
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
index 717368ef31ac..871fd51011db 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
@@ -19,11 +19,10 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
-
+#include <subdev/volt.h>
#ifdef __KERNEL__
#include <nouveau_platform.h>
#endif
-#include <subdev/volt.h>
struct cvb_coef {
int c0;
@@ -35,7 +34,7 @@ struct cvb_coef {
};
struct gk20a_volt_priv {
- struct nouveau_volt base;
+ struct nvkm_volt base;
struct regulator *vdd;
};
@@ -62,8 +61,7 @@ const struct cvb_coef gk20a_cvb_coef[] = {
* cvb_mv = ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0)
*/
static inline int
-gk20a_volt_get_cvb_voltage(int speedo, int s_scale,
- const struct cvb_coef *coef)
+gk20a_volt_get_cvb_voltage(int speedo, int s_scale, const struct cvb_coef *coef)
{
int mv;
@@ -79,7 +77,7 @@ gk20a_volt_get_cvb_voltage(int speedo, int s_scale,
*/
static inline int
gk20a_volt_get_cvb_t_voltage(int speedo, int temp, int s_scale, int t_scale,
- const struct cvb_coef *coef)
+ const struct cvb_coef *coef)
{
int cvb_mv, mv;
@@ -103,7 +101,7 @@ gk20a_volt_calc_voltage(const struct cvb_coef *coef, int speedo)
}
static int
-gk20a_volt_vid_get(struct nouveau_volt *volt)
+gk20a_volt_vid_get(struct nvkm_volt *volt)
{
struct gk20a_volt_priv *priv = (void *)volt;
int i, uv;
@@ -118,7 +116,7 @@ gk20a_volt_vid_get(struct nouveau_volt *volt)
}
static int
-gk20a_volt_vid_set(struct nouveau_volt *volt, u8 vid)
+gk20a_volt_vid_set(struct nvkm_volt *volt, u8 vid)
{
struct gk20a_volt_priv *priv = (void *)volt;
@@ -127,7 +125,7 @@ gk20a_volt_vid_set(struct nouveau_volt *volt, u8 vid)
}
static int
-gk20a_volt_set_id(struct nouveau_volt *volt, u8 id, int condition)
+gk20a_volt_set_id(struct nvkm_volt *volt, u8 id, int condition)
{
struct gk20a_volt_priv *priv = (void *)volt;
int prev_uv = regulator_get_voltage(priv->vdd);
@@ -148,16 +146,16 @@ gk20a_volt_set_id(struct nouveau_volt *volt, u8 id, int condition)
}
static int
-gk20a_volt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk20a_volt_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct gk20a_volt_priv *priv;
- struct nouveau_volt *volt;
+ struct nvkm_volt *volt;
struct nouveau_platform_device *plat;
int i, ret, uv;
- ret = nouveau_volt_create(parent, engine, oclass, &priv);
+ ret = nvkm_volt_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -187,13 +185,13 @@ gk20a_volt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
gk20a_volt_oclass = {
.handle = NV_SUBDEV(VOLT, 0xea),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_volt_ctor,
- .dtor = _nouveau_volt_dtor,
- .init = _nouveau_volt_init,
- .fini = _nouveau_volt_fini,
+ .dtor = _nvkm_volt_dtor,
+ .init = _nvkm_volt_init,
+ .fini = _nvkm_volt_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.c
index 755fa91bcd09..b778deb32d93 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.c
@@ -21,10 +21,10 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/volt.h>
-#include <subdev/gpio.h>
+#include <subdev/bios.h>
#include <subdev/bios/gpio.h>
+#include <subdev/gpio.h>
static const u8 tags[] = {
DCB_GPIO_VID0, DCB_GPIO_VID1, DCB_GPIO_VID2, DCB_GPIO_VID3,
@@ -32,9 +32,9 @@ static const u8 tags[] = {
};
int
-nouveau_voltgpio_get(struct nouveau_volt *volt)
+nvkm_voltgpio_get(struct nvkm_volt *volt)
{
- struct nouveau_gpio *gpio = nouveau_gpio(volt);
+ struct nvkm_gpio *gpio = nvkm_gpio(volt);
u8 vid = 0;
int i;
@@ -51,9 +51,9 @@ nouveau_voltgpio_get(struct nouveau_volt *volt)
}
int
-nouveau_voltgpio_set(struct nouveau_volt *volt, u8 vid)
+nvkm_voltgpio_set(struct nvkm_volt *volt, u8 vid)
{
- struct nouveau_gpio *gpio = nouveau_gpio(volt);
+ struct nvkm_gpio *gpio = nvkm_gpio(volt);
int i;
for (i = 0; i < ARRAY_SIZE(tags); i++, vid >>= 1) {
@@ -68,9 +68,9 @@ nouveau_voltgpio_set(struct nouveau_volt *volt, u8 vid)
}
int
-nouveau_voltgpio_init(struct nouveau_volt *volt)
+nvkm_voltgpio_init(struct nvkm_volt *volt)
{
- struct nouveau_gpio *gpio = nouveau_gpio(volt);
+ struct nvkm_gpio *gpio = nvkm_gpio(volt);
struct dcb_gpio_func func;
int i;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c
index 87d5358376a6..0ac5a3f8c9a8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c
@@ -21,22 +21,21 @@
*
* Authors: Ben Skeggs
*/
-
#include <subdev/volt.h>
struct nv40_volt_priv {
- struct nouveau_volt base;
+ struct nvkm_volt base;
};
static int
-nv40_volt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_volt_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv40_volt_priv *priv;
int ret;
- ret = nouveau_volt_create(parent, engine, oclass, &priv);
+ ret = nvkm_volt_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -44,13 +43,13 @@ nv40_volt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv40_volt_oclass = {
.handle = NV_SUBDEV(VOLT, 0x40),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_volt_ctor,
- .dtor = _nouveau_volt_dtor,
- .init = _nouveau_volt_init,
- .fini = _nouveau_volt_fini,
+ .dtor = _nvkm_volt_dtor,
+ .init = _nvkm_volt_init,
+ .fini = _nvkm_volt_fini,
},
};
From 912a29c3f18286dcf0386631e529f1f261bac6d7 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:22:20 +1000
Subject: [PATCH 70/86] drm/nouveau/bsp: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/engine/bsp.h | 7 ++-
.../gpu/drm/nouveau/nvkm/engine/bsp/Kbuild | 2 +-
.../nouveau/nvkm/engine/bsp/{nv84.c => g84.c} | 61 +++++++++----------
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 12 ++--
4 files changed, 41 insertions(+), 41 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/bsp/{nv84.c => g84.c} (66%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
index 5ce3b620e6a9..e489beef2b92 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
@@ -1,4 +1,5 @@
-#ifndef __NOUVEAU_BSP_H__
-#define __NOUVEAU_BSP_H__
-extern struct nouveau_oclass nv84_bsp_oclass;
+#ifndef __NVKM_BSP_H__
+#define __NVKM_BSP_H__
+#include <core/engine.h>
+extern struct nvkm_oclass g84_bsp_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild
index 3c8757202931..5ac9f9e1a283 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild
@@ -1 +1 @@
-nvkm-y += nvkm/engine/bsp/nv84.o
+nvkm-y += nvkm/engine/bsp/g84.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c
similarity index 66%
rename from drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c
index 649922d983ac..a0b1fd80fa93 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c
@@ -21,9 +21,8 @@
*
* Authors: Ben Skeggs, Ilia Mirkin
*/
-
-#include <engine/xtensa.h>
#include <engine/bsp.h>
+#include <engine/xtensa.h>
#include <core/engctx.h>
@@ -31,9 +30,9 @@
* BSP object classes
******************************************************************************/
-static struct nouveau_oclass
-nv84_bsp_sclass[] = {
- { 0x74b0, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+g84_bsp_sclass[] = {
+ { 0x74b0, &nvkm_object_ofuncs },
{},
};
@@ -41,16 +40,16 @@ nv84_bsp_sclass[] = {
* BSP context
******************************************************************************/
-static struct nouveau_oclass
-nv84_bsp_cclass = {
+static struct nvkm_oclass
+g84_bsp_cclass = {
.handle = NV_ENGCTX(BSP, 0x84),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_xtensa_engctx_ctor,
- .dtor = _nouveau_engctx_dtor,
- .init = _nouveau_engctx_init,
- .fini = _nouveau_engctx_fini,
- .rd32 = _nouveau_engctx_rd32,
- .wr32 = _nouveau_engctx_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_xtensa_engctx_ctor,
+ .dtor = _nvkm_engctx_dtor,
+ .init = _nvkm_engctx_init,
+ .fini = _nvkm_engctx_fini,
+ .rd32 = _nvkm_engctx_rd32,
+ .wr32 = _nvkm_engctx_wr32,
},
};
@@ -59,36 +58,36 @@ nv84_bsp_cclass = {
******************************************************************************/
static int
-nv84_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g84_bsp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_xtensa *priv;
+ struct nvkm_xtensa *priv;
int ret;
- ret = nouveau_xtensa_create(parent, engine, oclass, 0x103000, true,
- "PBSP", "bsp", &priv);
+ ret = nvkm_xtensa_create(parent, engine, oclass, 0x103000, true,
+ "PBSP", "bsp", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x04008000;
- nv_engine(priv)->cclass = &nv84_bsp_cclass;
- nv_engine(priv)->sclass = nv84_bsp_sclass;
+ nv_engine(priv)->cclass = &g84_bsp_cclass;
+ nv_engine(priv)->sclass = g84_bsp_sclass;
priv->fifo_val = 0x1111;
priv->unkd28 = 0x90044;
return 0;
}
-struct nouveau_oclass
-nv84_bsp_oclass = {
+struct nvkm_oclass
+g84_bsp_oclass = {
.handle = NV_ENGINE(BSP, 0x84),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv84_bsp_ctor,
- .dtor = _nouveau_xtensa_dtor,
- .init = _nouveau_xtensa_init,
- .fini = _nouveau_xtensa_fini,
- .rd32 = _nouveau_xtensa_rd32,
- .wr32 = _nouveau_xtensa_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g84_bsp_ctor,
+ .dtor = _nvkm_xtensa_dtor,
+ .init = _nvkm_xtensa_init,
+ .fini = _nvkm_xtensa_fini,
+ .rd32 = _nvkm_xtensa_rd32,
+ .wr32 = _nvkm_xtensa_wr32,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index f1f041fdb080..b74e27bb81f8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -112,7 +112,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@@ -141,7 +141,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@@ -170,7 +170,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@@ -199,7 +199,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@@ -228,7 +228,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@@ -286,7 +286,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
- device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
+ device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
From bd6c5cab95a4f112af9ff1d8635b0cd5b6d8aafb Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:22:32 +1000
Subject: [PATCH 71/86] drm/nouveau/ce: namespace + nvidia gpu names (no binary
change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/engine/ce.h | 15 +-
drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild | 6 +-
.../drm/nouveau/nvkm/engine/ce/fuc/com.fuc | 33 ++--
.../engine/ce/fuc/{nva3.fuc3 => gf100.fuc3} | 2 +-
.../ce/fuc/{nvc0.fuc3.h => gf100.fuc3.h} | 4 +-
.../engine/ce/fuc/{nvc0.fuc3 => gt215.fuc3} | 2 +-
.../ce/fuc/{nva3.fuc3.h => gt215.fuc3.h} | 4 +-
.../gpu/drm/nouveau/nvkm/engine/ce/gf100.c | 166 +++++++++++++++++
.../nvkm/engine/ce/{nve0.c => gk104.c} | 139 +++++++-------
.../nvkm/engine/ce/{nva3.c => gt215.c} | 103 +++++------
drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c | 172 ------------------
.../drm/nouveau/nvkm/engine/device/gm100.c | 6 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 8 +-
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 26 +--
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 44 ++---
15 files changed, 354 insertions(+), 376 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/{nva3.fuc3 => gf100.fuc3} (57%)
rename drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/{nvc0.fuc3.h => gf100.fuc3.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/{nvc0.fuc3 => gt215.fuc3} (57%)
rename drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/{nva3.fuc3.h => gt215.fuc3.h} (99%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
rename drivers/gpu/drm/nouveau/nvkm/engine/ce/{nve0.c => gk104.c} (51%)
rename drivers/gpu/drm/nouveau/nvkm/engine/ce/{nva3.c => gt215.c} (60%)
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
index 92cfcf5ae9d4..7e29c52617ea 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
@@ -2,13 +2,12 @@
#define __NVKM_CE_H__
#include <core/engine.h>
-void nva3_ce_intr(struct nouveau_subdev *);
-
-extern struct nouveau_oclass nva3_ce_oclass;
-extern struct nouveau_oclass nvc0_ce0_oclass;
-extern struct nouveau_oclass nvc0_ce1_oclass;
-extern struct nouveau_oclass nve0_ce0_oclass;
-extern struct nouveau_oclass nve0_ce1_oclass;
-extern struct nouveau_oclass nve0_ce2_oclass;
+void gt215_ce_intr(struct nvkm_subdev *);
+extern struct nvkm_oclass gt215_ce_oclass;
+extern struct nvkm_oclass gf100_ce0_oclass;
+extern struct nvkm_oclass gf100_ce1_oclass;
+extern struct nvkm_oclass gk104_ce0_oclass;
+extern struct nvkm_oclass gk104_ce1_oclass;
+extern struct nvkm_oclass gk104_ce2_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild
index 834523d8420f..858797453e0b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild
@@ -1,3 +1,3 @@
-nvkm-y += nvkm/engine/ce/nva3.o
-nvkm-y += nvkm/engine/ce/nvc0.o
-nvkm-y += nvkm/engine/ce/nve0.o
+nvkm-y += nvkm/engine/ce/gt215.o
+nvkm-y += nvkm/engine/ce/gf100.o
+nvkm-y += nvkm/engine/ce/gk104.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc
index fcc4ba172443..a558dfa4d76a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc
@@ -1,4 +1,4 @@
-/* fuc microcode for copy engine on nva3- chipsets
+/* fuc microcode for copy engine on gt215- chipsets
*
* Copyright 2011 Red Hat Inc.
*
@@ -23,21 +23,14 @@
* Authors: Ben Skeggs
*/
-/* To build for nva3:nvc0
- * m4 -DNVA3 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nva3_copy.fuc.h
- *
- * To build for nvc0-
- * m4 -DNVC0 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_copy.fuc.h
- */
-
-#ifdef NVA3
-.section #nva3_pce_data
+#ifdef GT215
+.section #gt215_pce_data
#else
-.section #nvc0_pce_data
+.section #gf100_pce_data
#endif
ctx_object: .b32 0
-#ifdef NVA3
+#ifdef GT215
ctx_dma:
ctx_dma_query: .b32 0
ctx_dma_src: .b32 0
@@ -86,7 +79,7 @@ dispatch_table:
// mthd 0x0140, PM_TRIGGER
.b16 0x050 1
.b32 0x00010000 + #cmd_pm_trigger ~0xffffffff
-#ifdef NVA3
+#ifdef GT215
// mthd 0x0180-0x018c, DMA_
.b16 0x060 #ctx_dma_count
dispatch_dma:
@@ -134,10 +127,10 @@ dispatch_dma:
.b32 #ctx_query_counter ~0xffffffff
.b16 0x800 0
-#ifdef NVA3
-.section #nva3_pce_code
+#ifdef GT215
+.section #gt215_pce_code
#else
-.section #nvc0_pce_code
+.section #gf100_pce_code
#endif
main:
@@ -190,7 +183,7 @@ ih:
swctx:
mov $r4 0x7700
mov $xtargets $r4
-#ifdef NVA3
+#ifdef GT215
// target 7 hardcoded to ctx dma object
mov $xdbase $r0
#else
@@ -271,7 +264,7 @@ chsw:
bra e #chsw_finish_load
bset $flags $p1
call #swctx
-#ifdef NVA3
+#ifdef GT215
// load dma objects back into TARGET regs
mov $r5 #ctx_dma
mov $r6 #ctx_dma_count
@@ -396,7 +389,7 @@ cmd_pm_trigger:
iowr I[$r2] $r3
ret
-#ifdef NVA3
+#ifdef GT215
// SET_DMA_* method handler
//
// Inputs:
@@ -547,7 +540,7 @@ cmd_exec_set_surface_tiled:
ld b32 $r7 D[$r5 + #ctx_src_tile_mode]
extr $r9 $r7 8:11
extr $r8 $r7 4:7
-#ifdef NVA3
+#ifdef GT215
add b32 $r8 2
#else
add b32 $r8 3
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3
similarity index 57%
rename from drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3
index e670620227e7..36f0a99ac7a2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3
@@ -1,2 +1,2 @@
-#define NVA3
+#define GF100
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h
index 042257daef8b..d9af6e4e4585 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvc0_pce_data[] = {
+uint32_t gf100_pce_data[] = {
/* 0x0000: ctx_object */
0x00000000,
/* 0x0004: ctx_query_address_high */
@@ -171,7 +171,7 @@ uint32_t nvc0_pce_data[] = {
0x00000800,
};
-uint32_t nvc0_pce_code[] = {
+uint32_t gf100_pce_code[] = {
/* 0x0000: main */
0x04fe04bd,
0x3517f000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3
similarity index 57%
rename from drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3
index df6866c34e16..07bda93cfd79 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3
@@ -1,2 +1,2 @@
-#define NVC0
+#define GT215
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h
index 362872df592a..f42c0d0d6cee 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nva3_pce_data[] = {
+uint32_t gt215_pce_data[] = {
/* 0x0000: ctx_object */
0x00000000,
/* 0x0004: ctx_dma */
@@ -183,7 +183,7 @@ uint32_t nva3_pce_data[] = {
0x00000800,
};
-uint32_t nva3_pce_code[] = {
+uint32_t gt215_pce_code[] = {
/* 0x0000: main */
0x04fe04bd,
0x3517f000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
new file mode 100644
index 000000000000..2d2e549c2e34
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+#include <engine/ce.h>
+#include <engine/falcon.h>
+#include "fuc/gf100.fuc3.h"
+
+struct gf100_ce_priv {
+ struct nvkm_falcon base;
+};
+
+/*******************************************************************************
+ * Copy object classes
+ ******************************************************************************/
+
+static struct nvkm_oclass
+gf100_ce0_sclass[] = {
+ { 0x90b5, &nvkm_object_ofuncs },
+ {},
+};
+
+static struct nvkm_oclass
+gf100_ce1_sclass[] = {
+ { 0x90b8, &nvkm_object_ofuncs },
+ {},
+};
+
+/*******************************************************************************
+ * PCE context
+ ******************************************************************************/
+
+static struct nvkm_ofuncs
+gf100_ce_context_ofuncs = {
+ .ctor = _nvkm_falcon_context_ctor,
+ .dtor = _nvkm_falcon_context_dtor,
+ .init = _nvkm_falcon_context_init,
+ .fini = _nvkm_falcon_context_fini,
+ .rd32 = _nvkm_falcon_context_rd32,
+ .wr32 = _nvkm_falcon_context_wr32,
+};
+
+static struct nvkm_oclass
+gf100_ce0_cclass = {
+ .handle = NV_ENGCTX(CE0, 0xc0),
+ .ofuncs = &gf100_ce_context_ofuncs,
+};
+
+static struct nvkm_oclass
+gf100_ce1_cclass = {
+ .handle = NV_ENGCTX(CE1, 0xc0),
+ .ofuncs = &gf100_ce_context_ofuncs,
+};
+
+/*******************************************************************************
+ * PCE engine/subdev functions
+ ******************************************************************************/
+
+static int
+gf100_ce_init(struct nvkm_object *object)
+{
+ struct gf100_ce_priv *priv = (void *)object;
+ int ret;
+
+ ret = nvkm_falcon_init(&priv->base);
+ if (ret)
+ return ret;
+
+ nv_wo32(priv, 0x084, nv_engidx(&priv->base.base) - NVDEV_ENGINE_CE0);
+ return 0;
+}
+
+static int
+gf100_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
+{
+ struct gf100_ce_priv *priv;
+ int ret;
+
+ ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, true,
+ "PCE0", "ce0", &priv);
+ *pobject = nv_object(priv);
+ if (ret)
+ return ret;
+
+ nv_subdev(priv)->unit = 0x00000040;
+ nv_subdev(priv)->intr = gt215_ce_intr;
+ nv_engine(priv)->cclass = &gf100_ce0_cclass;
+ nv_engine(priv)->sclass = gf100_ce0_sclass;
+ nv_falcon(priv)->code.data = gf100_pce_code;
+ nv_falcon(priv)->code.size = sizeof(gf100_pce_code);
+ nv_falcon(priv)->data.data = gf100_pce_data;
+ nv_falcon(priv)->data.size = sizeof(gf100_pce_data);
+ return 0;
+}
+
+static int
+gf100_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
+{
+ struct gf100_ce_priv *priv;
+ int ret;
+
+ ret = nvkm_falcon_create(parent, engine, oclass, 0x105000, true,
+ "PCE1", "ce1", &priv);
+ *pobject = nv_object(priv);
+ if (ret)
+ return ret;
+
+ nv_subdev(priv)->unit = 0x00000080;
+ nv_subdev(priv)->intr = gt215_ce_intr;
+ nv_engine(priv)->cclass = &gf100_ce1_cclass;
+ nv_engine(priv)->sclass = gf100_ce1_sclass;
+ nv_falcon(priv)->code.data = gf100_pce_code;
+ nv_falcon(priv)->code.size = sizeof(gf100_pce_code);
+ nv_falcon(priv)->data.data = gf100_pce_data;
+ nv_falcon(priv)->data.size = sizeof(gf100_pce_data);
+ return 0;
+}
+
+struct nvkm_oclass
+gf100_ce0_oclass = {
+ .handle = NV_ENGINE(CE0, 0xc0),
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_ce0_ctor,
+ .dtor = _nvkm_falcon_dtor,
+ .init = gf100_ce_init,
+ .fini = _nvkm_falcon_fini,
+ .rd32 = _nvkm_falcon_rd32,
+ .wr32 = _nvkm_falcon_wr32,
+ },
+};
+
+struct nvkm_oclass
+gf100_ce1_oclass = {
+ .handle = NV_ENGINE(CE1, 0xc0),
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_ce1_ctor,
+ .dtor = _nvkm_falcon_dtor,
+ .init = gf100_ce_init,
+ .fini = _nvkm_falcon_fini,
+ .rd32 = _nvkm_falcon_rd32,
+ .wr32 = _nvkm_falcon_wr32,
+ },
+};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c
similarity index 51%
rename from drivers/gpu/drm/nouveau/nvkm/engine/ce/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c
index b2b31d1b768c..a998932fae45 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c
@@ -21,24 +21,21 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/os.h>
-#include <core/enum.h>
-#include <core/engctx.h>
-
#include <engine/ce.h>
-struct nve0_ce_priv {
- struct nouveau_engine base;
+#include <core/engctx.h>
+
+struct gk104_ce_priv {
+ struct nvkm_engine base;
};
/*******************************************************************************
* Copy object classes
******************************************************************************/
-static struct nouveau_oclass
-nve0_ce_sclass[] = {
- { 0xa0b5, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+gk104_ce_sclass[] = {
+ { 0xa0b5, &nvkm_object_ofuncs },
{},
};
@@ -46,20 +43,20 @@ nve0_ce_sclass[] = {
* PCE context
******************************************************************************/
-static struct nouveau_ofuncs
-nve0_ce_context_ofuncs = {
- .ctor = _nouveau_engctx_ctor,
- .dtor = _nouveau_engctx_dtor,
- .init = _nouveau_engctx_init,
- .fini = _nouveau_engctx_fini,
- .rd32 = _nouveau_engctx_rd32,
- .wr32 = _nouveau_engctx_wr32,
+static struct nvkm_ofuncs
+gk104_ce_context_ofuncs = {
+ .ctor = _nvkm_engctx_ctor,
+ .dtor = _nvkm_engctx_dtor,
+ .init = _nvkm_engctx_init,
+ .fini = _nvkm_engctx_fini,
+ .rd32 = _nvkm_engctx_rd32,
+ .wr32 = _nvkm_engctx_wr32,
};
-static struct nouveau_oclass
-nve0_ce_cclass = {
+static struct nvkm_oclass
+gk104_ce_cclass = {
.handle = NV_ENGCTX(CE0, 0xc0),
- .ofuncs = &nve0_ce_context_ofuncs,
+ .ofuncs = &gk104_ce_context_ofuncs,
};
/*******************************************************************************
@@ -67,10 +64,10 @@ nve0_ce_cclass = {
******************************************************************************/
static void
-nve0_ce_intr(struct nouveau_subdev *subdev)
+gk104_ce_intr(struct nvkm_subdev *subdev)
{
const int ce = nv_subidx(subdev) - NVDEV_ENGINE_CE0;
- struct nve0_ce_priv *priv = (void *)subdev;
+ struct gk104_ce_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000));
if (stat) {
@@ -80,97 +77,97 @@ nve0_ce_intr(struct nouveau_subdev *subdev)
}
static int
-nve0_ce0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk104_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nve0_ce_priv *priv;
+ struct gk104_ce_priv *priv;
int ret;
- ret = nouveau_engine_create(parent, engine, oclass, true,
- "PCE0", "ce0", &priv);
+ ret = nvkm_engine_create(parent, engine, oclass, true,
+ "PCE0", "ce0", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000040;
- nv_subdev(priv)->intr = nve0_ce_intr;
- nv_engine(priv)->cclass = &nve0_ce_cclass;
- nv_engine(priv)->sclass = nve0_ce_sclass;
+ nv_subdev(priv)->intr = gk104_ce_intr;
+ nv_engine(priv)->cclass = &gk104_ce_cclass;
+ nv_engine(priv)->sclass = gk104_ce_sclass;
return 0;
}
static int
-nve0_ce1_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk104_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nve0_ce_priv *priv;
+ struct gk104_ce_priv *priv;
int ret;
- ret = nouveau_engine_create(parent, engine, oclass, true,
- "PCE1", "ce1", &priv);
+ ret = nvkm_engine_create(parent, engine, oclass, true,
+ "PCE1", "ce1", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000080;
- nv_subdev(priv)->intr = nve0_ce_intr;
- nv_engine(priv)->cclass = &nve0_ce_cclass;
- nv_engine(priv)->sclass = nve0_ce_sclass;
+ nv_subdev(priv)->intr = gk104_ce_intr;
+ nv_engine(priv)->cclass = &gk104_ce_cclass;
+ nv_engine(priv)->sclass = gk104_ce_sclass;
return 0;
}
static int
-nve0_ce2_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk104_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nve0_ce_priv *priv;
+ struct gk104_ce_priv *priv;
int ret;
- ret = nouveau_engine_create(parent, engine, oclass, true,
- "PCE2", "ce2", &priv);
+ ret = nvkm_engine_create(parent, engine, oclass, true,
+ "PCE2", "ce2", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00200000;
- nv_subdev(priv)->intr = nve0_ce_intr;
- nv_engine(priv)->cclass = &nve0_ce_cclass;
- nv_engine(priv)->sclass = nve0_ce_sclass;
+ nv_subdev(priv)->intr = gk104_ce_intr;
+ nv_engine(priv)->cclass = &gk104_ce_cclass;
+ nv_engine(priv)->sclass = gk104_ce_sclass;
return 0;
}
-struct nouveau_oclass
-nve0_ce0_oclass = {
+struct nvkm_oclass
+gk104_ce0_oclass = {
.handle = NV_ENGINE(CE0, 0xe0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_ce0_ctor,
- .dtor = _nouveau_engine_dtor,
- .init = _nouveau_engine_init,
- .fini = _nouveau_engine_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_ce0_ctor,
+ .dtor = _nvkm_engine_dtor,
+ .init = _nvkm_engine_init,
+ .fini = _nvkm_engine_fini,
},
};
-struct nouveau_oclass
-nve0_ce1_oclass = {
+struct nvkm_oclass
+gk104_ce1_oclass = {
.handle = NV_ENGINE(CE1, 0xe0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_ce1_ctor,
- .dtor = _nouveau_engine_dtor,
- .init = _nouveau_engine_init,
- .fini = _nouveau_engine_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_ce1_ctor,
+ .dtor = _nvkm_engine_dtor,
+ .init = _nvkm_engine_init,
+ .fini = _nvkm_engine_fini,
},
};
-struct nouveau_oclass
-nve0_ce2_oclass = {
+struct nvkm_oclass
+gk104_ce2_oclass = {
.handle = NV_ENGINE(CE2, 0xe0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_ce2_ctor,
- .dtor = _nouveau_engine_dtor,
- .init = _nouveau_engine_init,
- .fini = _nouveau_engine_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_ce2_ctor,
+ .dtor = _nvkm_engine_dtor,
+ .init = _nvkm_engine_init,
+ .fini = _nvkm_engine_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
similarity index 60%
rename from drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
index b14617ac5abe..d8bb4293bc11 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
@@ -21,32 +21,26 @@
*
* Authors: Ben Skeggs
*/
-
+#include <engine/ce.h>
#include <engine/falcon.h>
#include <engine/fifo.h>
-#include <engine/ce.h>
-
-#include <subdev/fb.h>
-#include <subdev/mmu.h>
+#include "fuc/gt215.fuc3.h"
#include <core/client.h>
#include <core/device.h>
#include <core/enum.h>
-
-#include "fuc/nva3.fuc3.h"
-
-struct nva3_ce_priv {
- struct nouveau_falcon base;
+struct gt215_ce_priv {
+ struct nvkm_falcon base;
};
/*******************************************************************************
* Copy object classes
******************************************************************************/
-static struct nouveau_oclass
-nva3_ce_sclass[] = {
- { 0x85b5, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+gt215_ce_sclass[] = {
+ { 0x85b5, &nvkm_object_ofuncs },
{}
};
@@ -54,16 +48,16 @@ nva3_ce_sclass[] = {
* PCE context
******************************************************************************/
-static struct nouveau_oclass
-nva3_ce_cclass = {
+static struct nvkm_oclass
+gt215_ce_cclass = {
.handle = NV_ENGCTX(CE0, 0xa3),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_falcon_context_ctor,
- .dtor = _nouveau_falcon_context_dtor,
- .init = _nouveau_falcon_context_init,
- .fini = _nouveau_falcon_context_fini,
- .rd32 = _nouveau_falcon_context_rd32,
- .wr32 = _nouveau_falcon_context_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_falcon_context_ctor,
+ .dtor = _nvkm_falcon_context_dtor,
+ .init = _nvkm_falcon_context_init,
+ .fini = _nvkm_falcon_context_fini,
+ .rd32 = _nvkm_falcon_context_rd32,
+ .wr32 = _nvkm_falcon_context_wr32,
},
};
@@ -72,7 +66,8 @@ nva3_ce_cclass = {
* PCE engine/subdev functions
******************************************************************************/
-static const struct nouveau_enum nva3_ce_isr_error_name[] = {
+static const struct nvkm_enum
+gt215_ce_isr_error_name[] = {
{ 0x0001, "ILLEGAL_MTHD" },
{ 0x0002, "INVALID_ENUM" },
{ 0x0003, "INVALID_BITFIELD" },
@@ -80,12 +75,12 @@ static const struct nouveau_enum nva3_ce_isr_error_name[] = {
};
void
-nva3_ce_intr(struct nouveau_subdev *subdev)
+gt215_ce_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
- struct nouveau_engine *engine = nv_engine(subdev);
- struct nouveau_falcon *falcon = (void *)subdev;
- struct nouveau_object *engctx;
+ struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
+ struct nvkm_engine *engine = nv_engine(subdev);
+ struct nvkm_falcon *falcon = (void *)subdev;
+ struct nvkm_object *engctx;
u32 dispatch = nv_ro32(falcon, 0x01c);
u32 stat = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16);
u64 inst = nv_ro32(falcon, 0x050) & 0x3fffffff;
@@ -96,14 +91,14 @@ nva3_ce_intr(struct nouveau_subdev *subdev)
u32 data = nv_ro32(falcon, 0x044);
int chid;
- engctx = nouveau_engctx_get(engine, inst);
+ engctx = nvkm_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
if (stat & 0x00000040) {
nv_error(falcon, "DISPATCH_ERROR [");
- nouveau_enum_print(nva3_ce_isr_error_name, ssta);
+ nvkm_enum_print(gt215_ce_isr_error_name, ssta);
pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
- chid, inst << 12, nouveau_client_name(engctx), subc,
+ chid, inst << 12, nvkm_client_name(engctx), subc,
mthd, data);
nv_wo32(falcon, 0x004, 0x00000040);
stat &= ~0x00000040;
@@ -114,44 +109,44 @@ nva3_ce_intr(struct nouveau_subdev *subdev)
nv_wo32(falcon, 0x004, stat);
}
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
static int
-nva3_ce_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gt215_ce_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
bool enable = (nv_device(parent)->chipset != 0xaf);
- struct nva3_ce_priv *priv;
+ struct gt215_ce_priv *priv;
int ret;
- ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, enable,
- "PCE0", "ce0", &priv);
+ ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, enable,
+ "PCE0", "ce0", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00802000;
- nv_subdev(priv)->intr = nva3_ce_intr;
- nv_engine(priv)->cclass = &nva3_ce_cclass;
- nv_engine(priv)->sclass = nva3_ce_sclass;
- nv_falcon(priv)->code.data = nva3_pce_code;
- nv_falcon(priv)->code.size = sizeof(nva3_pce_code);
- nv_falcon(priv)->data.data = nva3_pce_data;
- nv_falcon(priv)->data.size = sizeof(nva3_pce_data);
+ nv_subdev(priv)->intr = gt215_ce_intr;
+ nv_engine(priv)->cclass = >215_ce_cclass;
+ nv_engine(priv)->sclass = gt215_ce_sclass;
+ nv_falcon(priv)->code.data = gt215_pce_code;
+ nv_falcon(priv)->code.size = sizeof(gt215_pce_code);
+ nv_falcon(priv)->data.data = gt215_pce_data;
+ nv_falcon(priv)->data.size = sizeof(gt215_pce_data);
return 0;
}
-struct nouveau_oclass
-nva3_ce_oclass = {
+struct nvkm_oclass
+gt215_ce_oclass = {
.handle = NV_ENGINE(CE0, 0xa3),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nva3_ce_ctor,
- .dtor = _nouveau_falcon_dtor,
- .init = _nouveau_falcon_init,
- .fini = _nouveau_falcon_fini,
- .rd32 = _nouveau_falcon_rd32,
- .wr32 = _nouveau_falcon_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gt215_ce_ctor,
+ .dtor = _nvkm_falcon_dtor,
+ .init = _nvkm_falcon_init,
+ .fini = _nvkm_falcon_fini,
+ .rd32 = _nvkm_falcon_rd32,
+ .wr32 = _nvkm_falcon_wr32,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c
deleted file mode 100644
index f5dff133362d..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <engine/falcon.h>
-#include <engine/fifo.h>
-#include <engine/ce.h>
-
-#include <core/enum.h>
-#include <core/enum.h>
-
-#include "fuc/nvc0.fuc3.h"
-
-struct nvc0_ce_priv {
- struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * Copy object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nvc0_ce0_sclass[] = {
- { 0x90b5, &nouveau_object_ofuncs },
- {},
-};
-
-static struct nouveau_oclass
-nvc0_ce1_sclass[] = {
- { 0x90b8, &nouveau_object_ofuncs },
- {},
-};
-
-/*******************************************************************************
- * PCE context
- ******************************************************************************/
-
-static struct nouveau_ofuncs
-nvc0_ce_context_ofuncs = {
- .ctor = _nouveau_falcon_context_ctor,
- .dtor = _nouveau_falcon_context_dtor,
- .init = _nouveau_falcon_context_init,
- .fini = _nouveau_falcon_context_fini,
- .rd32 = _nouveau_falcon_context_rd32,
- .wr32 = _nouveau_falcon_context_wr32,
-};
-
-static struct nouveau_oclass
-nvc0_ce0_cclass = {
- .handle = NV_ENGCTX(CE0, 0xc0),
- .ofuncs = &nvc0_ce_context_ofuncs,
-};
-
-static struct nouveau_oclass
-nvc0_ce1_cclass = {
- .handle = NV_ENGCTX(CE1, 0xc0),
- .ofuncs = &nvc0_ce_context_ofuncs,
-};
-
-/*******************************************************************************
- * PCE engine/subdev functions
- ******************************************************************************/
-
-static int
-nvc0_ce_init(struct nouveau_object *object)
-{
- struct nvc0_ce_priv *priv = (void *)object;
- int ret;
-
- ret = nouveau_falcon_init(&priv->base);
- if (ret)
- return ret;
-
- nv_wo32(priv, 0x084, nv_engidx(&priv->base.base) - NVDEV_ENGINE_CE0);
- return 0;
-}
-
-static int
-nvc0_ce0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
-{
- struct nvc0_ce_priv *priv;
- int ret;
-
- ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, true,
- "PCE0", "ce0", &priv);
- *pobject = nv_object(priv);
- if (ret)
- return ret;
-
- nv_subdev(priv)->unit = 0x00000040;
- nv_subdev(priv)->intr = nva3_ce_intr;
- nv_engine(priv)->cclass = &nvc0_ce0_cclass;
- nv_engine(priv)->sclass = nvc0_ce0_sclass;
- nv_falcon(priv)->code.data = nvc0_pce_code;
- nv_falcon(priv)->code.size = sizeof(nvc0_pce_code);
- nv_falcon(priv)->data.data = nvc0_pce_data;
- nv_falcon(priv)->data.size = sizeof(nvc0_pce_data);
- return 0;
-}
-
-static int
-nvc0_ce1_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
-{
- struct nvc0_ce_priv *priv;
- int ret;
-
- ret = nouveau_falcon_create(parent, engine, oclass, 0x105000, true,
- "PCE1", "ce1", &priv);
- *pobject = nv_object(priv);
- if (ret)
- return ret;
-
- nv_subdev(priv)->unit = 0x00000080;
- nv_subdev(priv)->intr = nva3_ce_intr;
- nv_engine(priv)->cclass = &nvc0_ce1_cclass;
- nv_engine(priv)->sclass = nvc0_ce1_sclass;
- nv_falcon(priv)->code.data = nvc0_pce_code;
- nv_falcon(priv)->code.size = sizeof(nvc0_pce_code);
- nv_falcon(priv)->data.data = nvc0_pce_data;
- nv_falcon(priv)->data.size = sizeof(nvc0_pce_data);
- return 0;
-}
-
-struct nouveau_oclass
-nvc0_ce0_oclass = {
- .handle = NV_ENGINE(CE0, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_ce0_ctor,
- .dtor = _nouveau_falcon_dtor,
- .init = nvc0_ce_init,
- .fini = _nouveau_falcon_fini,
- .rd32 = _nouveau_falcon_rd32,
- .wr32 = _nouveau_falcon_wr32,
- },
-};
-
-struct nouveau_oclass
-nvc0_ce1_oclass = {
- .handle = NV_ENGINE(CE1, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_ce1_ctor,
- .dtor = _nouveau_falcon_dtor,
- .init = nvc0_ce_init,
- .fini = _nouveau_falcon_fini,
- .rd32 = _nouveau_falcon_rd32,
- .wr32 = _nouveau_falcon_wr32,
- },
-};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 342305f8abd8..dfc9e544e3e6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -88,11 +88,11 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
#if 0
- device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
#endif
- device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
#if 0
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index b74e27bb81f8..88353d33974f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -375,7 +375,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
break;
@@ -405,7 +405,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
break;
@@ -435,7 +435,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
break;
@@ -465,7 +465,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index a4859a541aea..fd87b8f955ed 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -87,8 +87,8 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
- device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
@@ -120,8 +120,8 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
- device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
@@ -153,7 +153,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
@@ -185,8 +185,8 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
- device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
@@ -218,7 +218,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
@@ -250,7 +250,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
@@ -282,8 +282,8 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
- device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
@@ -315,7 +315,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
@@ -345,7 +345,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 962a810d2b83..76cc21d383cb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -85,9 +85,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
- device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
- device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -119,9 +119,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
- device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
- device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -153,9 +153,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
- device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
- device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -178,7 +178,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
- device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass;
@@ -209,9 +209,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
- device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
- device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -243,9 +243,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
- device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
- device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -277,9 +277,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
- device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
- device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -310,9 +310,9 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
- device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
- device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
- device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
+ device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
+ device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
+ device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
From ccdfdf21899924ac43b47850147af572a8dfcaa6 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:22:43 +1000
Subject: [PATCH 72/86] drm/nouveau/cipher: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/engine/cipher.h | 3 +-
.../gpu/drm/nouveau/nvkm/engine/cipher/Kbuild | 2 +-
.../nvkm/engine/cipher/{nv84.c => g84.c} | 128 +++++++++---------
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 12 +-
4 files changed, 71 insertions(+), 74 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/cipher/{nv84.c => g84.c} (56%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h
index 813bca367331..57c29e91bad5 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h
@@ -1,4 +1,5 @@
#ifndef __NVKM_CIPHER_H__
#define __NVKM_CIPHER_H__
-extern struct nouveau_oclass nv84_cipher_oclass;
+#include <core/engine.h>
+extern struct nvkm_oclass g84_cipher_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild
index 07cc2150463b..fa39945327ce 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild
@@ -1 +1 @@
-nvkm-y += nvkm/engine/cipher/nv84.o
+nvkm-y += nvkm/engine/cipher/g84.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c
similarity index 56%
rename from drivers/gpu/drm/nouveau/nvkm/engine/cipher/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c
index d4ecd91ccbe6..13f30428a305 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c
@@ -21,20 +21,15 @@
*
* Authors: Ben Skeggs
*/
+#include <engine/cipher.h>
+#include <engine/fifo.h>
#include <core/client.h>
-#include <core/os.h>
-#include <core/enum.h>
#include <core/engctx.h>
-#include <core/gpuobj.h>
+#include <core/enum.h>
-#include <subdev/fb.h>
-
-#include <engine/fifo.h>
-#include <engine/cipher.h>
-
-struct nv84_cipher_priv {
- struct nouveau_engine base;
+struct g84_cipher_priv {
+ struct nvkm_engine base;
};
/*******************************************************************************
@@ -42,16 +37,16 @@ struct nv84_cipher_priv {
******************************************************************************/
static int
-nv84_cipher_object_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g84_cipher_object_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_gpuobj *obj;
+ struct nvkm_gpuobj *obj;
int ret;
- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
- 16, 16, 0, &obj);
+ ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
+ 16, 16, 0, &obj);
*pobject = nv_object(obj);
if (ret)
return ret;
@@ -63,19 +58,19 @@ nv84_cipher_object_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_ofuncs
-nv84_cipher_ofuncs = {
- .ctor = nv84_cipher_object_ctor,
- .dtor = _nouveau_gpuobj_dtor,
- .init = _nouveau_gpuobj_init,
- .fini = _nouveau_gpuobj_fini,
- .rd32 = _nouveau_gpuobj_rd32,
- .wr32 = _nouveau_gpuobj_wr32,
+static struct nvkm_ofuncs
+g84_cipher_ofuncs = {
+ .ctor = g84_cipher_object_ctor,
+ .dtor = _nvkm_gpuobj_dtor,
+ .init = _nvkm_gpuobj_init,
+ .fini = _nvkm_gpuobj_fini,
+ .rd32 = _nvkm_gpuobj_rd32,
+ .wr32 = _nvkm_gpuobj_wr32,
};
-static struct nouveau_oclass
-nv84_cipher_sclass[] = {
- { 0x74c1, &nv84_cipher_ofuncs },
+static struct nvkm_oclass
+g84_cipher_sclass[] = {
+ { 0x74c1, &g84_cipher_ofuncs },
{}
};
@@ -83,16 +78,16 @@ nv84_cipher_sclass[] = {
* PCIPHER context
******************************************************************************/
-static struct nouveau_oclass
-nv84_cipher_cclass = {
+static struct nvkm_oclass
+g84_cipher_cclass = {
.handle = NV_ENGCTX(CIPHER, 0x84),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_engctx_ctor,
- .dtor = _nouveau_engctx_dtor,
- .init = _nouveau_engctx_init,
- .fini = _nouveau_engctx_fini,
- .rd32 = _nouveau_engctx_rd32,
- .wr32 = _nouveau_engctx_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_engctx_ctor,
+ .dtor = _nvkm_engctx_dtor,
+ .init = _nvkm_engctx_init,
+ .fini = _nvkm_engctx_fini,
+ .rd32 = _nvkm_engctx_rd32,
+ .wr32 = _nvkm_engctx_wr32,
},
};
@@ -100,7 +95,8 @@ nv84_cipher_cclass = {
* PCIPHER engine/subdev functions
******************************************************************************/
-static const struct nouveau_bitfield nv84_cipher_intr_mask[] = {
+static const struct nvkm_bitfield
+g84_cipher_intr_mask[] = {
{ 0x00000001, "INVALID_STATE" },
{ 0x00000002, "ILLEGAL_MTHD" },
{ 0x00000004, "ILLEGAL_CLASS" },
@@ -110,63 +106,63 @@ static const struct nouveau_bitfield nv84_cipher_intr_mask[] = {
};
static void
-nv84_cipher_intr(struct nouveau_subdev *subdev)
+g84_cipher_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
- struct nouveau_engine *engine = nv_engine(subdev);
- struct nouveau_object *engctx;
- struct nv84_cipher_priv *priv = (void *)subdev;
+ struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
+ struct nvkm_engine *engine = nv_engine(subdev);
+ struct nvkm_object *engctx;
+ struct g84_cipher_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, 0x102130);
u32 mthd = nv_rd32(priv, 0x102190);
u32 data = nv_rd32(priv, 0x102194);
u32 inst = nv_rd32(priv, 0x102188) & 0x7fffffff;
int chid;
- engctx = nouveau_engctx_get(engine, inst);
+ engctx = nvkm_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
if (stat) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv84_cipher_intr_mask, stat);
+ nvkm_bitfield_print(g84_cipher_intr_mask, stat);
pr_cont(" ch %d [0x%010llx %s] mthd 0x%04x data 0x%08x\n",
- chid, (u64)inst << 12, nouveau_client_name(engctx),
+ chid, (u64)inst << 12, nvkm_client_name(engctx),
mthd, data);
}
nv_wr32(priv, 0x102130, stat);
nv_wr32(priv, 0x10200c, 0x10);
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
static int
-nv84_cipher_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g84_cipher_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nv84_cipher_priv *priv;
+ struct g84_cipher_priv *priv;
int ret;
- ret = nouveau_engine_create(parent, engine, oclass, true,
- "PCIPHER", "cipher", &priv);
+ ret = nvkm_engine_create(parent, engine, oclass, true,
+ "PCIPHER", "cipher", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00004000;
- nv_subdev(priv)->intr = nv84_cipher_intr;
- nv_engine(priv)->cclass = &nv84_cipher_cclass;
- nv_engine(priv)->sclass = nv84_cipher_sclass;
+ nv_subdev(priv)->intr = g84_cipher_intr;
+ nv_engine(priv)->cclass = &g84_cipher_cclass;
+ nv_engine(priv)->sclass = g84_cipher_sclass;
return 0;
}
static int
-nv84_cipher_init(struct nouveau_object *object)
+g84_cipher_init(struct nvkm_object *object)
{
- struct nv84_cipher_priv *priv = (void *)object;
+ struct g84_cipher_priv *priv = (void *)object;
int ret;
- ret = nouveau_engine_init(&priv->base);
+ ret = nvkm_engine_init(&priv->base);
if (ret)
return ret;
@@ -176,13 +172,13 @@ nv84_cipher_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass
-nv84_cipher_oclass = {
+struct nvkm_oclass
+g84_cipher_oclass = {
.handle = NV_ENGINE(CIPHER, 0x84),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv84_cipher_ctor,
- .dtor = _nouveau_engine_dtor,
- .init = nv84_cipher_init,
- .fini = _nouveau_engine_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g84_cipher_ctor,
+ .dtor = _nvkm_engine_dtor,
+ .init = g84_cipher_init,
+ .fini = _nvkm_engine_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 88353d33974f..72a90c74506c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -111,7 +111,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
- device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
+ device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
@@ -140,7 +140,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
- device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
+ device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
@@ -169,7 +169,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
- device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
+ device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
@@ -198,7 +198,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
- device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
+ device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
@@ -227,7 +227,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
- device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
+ device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
@@ -285,7 +285,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
- device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
+ device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
From 878da15adb5ddce57339b87685d8b4630e60085f Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:24:57 +1000
Subject: [PATCH 73/86] drm/nouveau/disp: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 3 +
.../drm/nouveau/include/nvkm/engine/disp.h | 40 ++-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 26 +-
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 +-
.../gpu/drm/nouveau/nvkm/engine/disp/Kbuild | 30 +-
.../gpu/drm/nouveau/nvkm/engine/disp/base.c | 83 +++--
.../gpu/drm/nouveau/nvkm/engine/disp/conn.c | 49 ++-
.../gpu/drm/nouveau/nvkm/engine/disp/conn.h | 27 +-
.../drm/nouveau/nvkm/engine/disp/dacnv50.c | 10 +-
.../gpu/drm/nouveau/nvkm/engine/disp/dport.c | 30 +-
.../gpu/drm/nouveau/nvkm/engine/disp/dport.h | 4 +-
.../nvkm/engine/disp/{nv84.c => g84.c} | 72 +++--
.../nvkm/engine/disp/{nv94.c => g94.c} | 69 ++---
.../nvkm/engine/disp/{nvd0.c => gf110.c} | 289 +++++++++---------
.../nvkm/engine/disp/{nve0.c => gk104.c} | 96 +++---
.../nvkm/engine/disp/{nvf0.c => gk110.c} | 76 +++--
.../gpu/drm/nouveau/nvkm/engine/disp/gm107.c | 64 ++--
.../gpu/drm/nouveau/nvkm/engine/disp/gm204.c | 65 ++--
.../nvkm/engine/disp/{nva0.c => gt200.c} | 56 ++--
.../nvkm/engine/disp/{nva3.c => gt215.c} | 54 ++--
.../engine/disp/{hdanvd0.c => hdagf110.c} | 12 +-
.../engine/disp/{hdanva3.c => hdagt215.c} | 10 +-
.../engine/disp/{hdminv84.c => hdmig84.c} | 12 +-
.../engine/disp/{hdminvd0.c => hdmigf110.c} | 12 +-
.../engine/disp/{hdminve0.c => hdmigk104.c} | 12 +-
.../engine/disp/{hdminva3.c => hdmigt215.c} | 9 +-
.../gpu/drm/nouveau/nvkm/engine/disp/nv04.c | 60 ++--
.../gpu/drm/nouveau/nvkm/engine/disp/nv50.c | 260 ++++++++--------
.../gpu/drm/nouveau/nvkm/engine/disp/nv50.h | 202 ++++++------
.../gpu/drm/nouveau/nvkm/engine/disp/outp.c | 53 ++--
.../gpu/drm/nouveau/nvkm/engine/disp/outp.h | 29 +-
.../gpu/drm/nouveau/nvkm/engine/disp/outpdp.c | 53 ++--
.../gpu/drm/nouveau/nvkm/engine/disp/outpdp.h | 20 +-
.../drm/nouveau/nvkm/engine/disp/piornv50.c | 42 ++-
.../gpu/drm/nouveau/nvkm/engine/disp/priv.h | 58 ++--
.../nvkm/engine/disp/{sornv94.c => sorg94.c} | 74 +++--
.../engine/disp/{sornvd0.c => sorgf110.c} | 63 ++--
.../drm/nouveau/nvkm/engine/disp/sorgm204.c | 33 +-
.../drm/nouveau/nvkm/engine/disp/sornv50.c | 10 +-
.../gpu/drm/nouveau/nvkm/engine/disp/vga.c | 11 +-
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c | 1 +
42 files changed, 1060 insertions(+), 1151 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{nv84.c => g84.c} (82%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{nv94.c => g94.c} (72%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{nvd0.c => gf110.c} (83%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{nve0.c => gk104.c} (74%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{nvf0.c => gk110.c} (56%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{nva0.c => gt200.c} (78%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{nva3.c => gt215.c} (73%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{hdanvd0.c => hdagf110.c} (95%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{hdanva3.c => hdagt215.c} (97%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{hdminv84.c => hdmig84.c} (98%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{hdminvd0.c => hdmigf110.c} (98%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{hdminve0.c => hdmigk104.c} (98%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{hdminva3.c => hdmigt215.c} (98%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{sornv94.c => sorg94.c} (65%)
rename drivers/gpu/drm/nouveau/nvkm/engine/disp/{sornvd0.c => sorgf110.c} (66%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 625d390d4c22..e81d40c221b5 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -245,5 +245,8 @@
#define nouveau_fuse nvkm_fuse
#define nouveau_mc nvkm_mc
#define nouveau_mmu nvkm_mmu
+#define nouveau_dmaeng nvkm_dmaeng
+#define nouveau_dmaobj nvkm_dmaobj
+#define nouveau_disp nvkm_disp
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
index 626508d8da40..a5e1ed81312f 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
@@ -1,13 +1,10 @@
-#ifndef __NOUVEAU_DISP_H__
-#define __NOUVEAU_DISP_H__
-
-#include <core/object.h>
+#ifndef __NVKM_DISP_H__
+#define __NVKM_DISP_H__
#include <core/engine.h>
-#include <core/device.h>
#include <core/event.h>
-struct nouveau_disp {
- struct nouveau_engine base;
+struct nvkm_disp {
+ struct nvkm_engine base;
struct list_head outp;
@@ -15,22 +12,21 @@ struct nouveau_disp {
struct nvkm_event vblank;
};
-static inline struct nouveau_disp *
-nouveau_disp(void *obj)
+static inline struct nvkm_disp *
+nvkm_disp(void *obj)
{
- return (void *)nouveau_engine(obj, NVDEV_ENGINE_DISP);
+ return (void *)nvkm_engine(obj, NVDEV_ENGINE_DISP);
}
-extern struct nouveau_oclass *nv04_disp_oclass;
-extern struct nouveau_oclass *nv50_disp_oclass;
-extern struct nouveau_oclass *nv84_disp_oclass;
-extern struct nouveau_oclass *nva0_disp_oclass;
-extern struct nouveau_oclass *nv94_disp_oclass;
-extern struct nouveau_oclass *nva3_disp_oclass;
-extern struct nouveau_oclass *nvd0_disp_oclass;
-extern struct nouveau_oclass *nve0_disp_oclass;
-extern struct nouveau_oclass *nvf0_disp_oclass;
-extern struct nouveau_oclass *gm107_disp_oclass;
-extern struct nouveau_oclass *gm204_disp_oclass;
-
+extern struct nvkm_oclass *nv04_disp_oclass;
+extern struct nvkm_oclass *nv50_disp_oclass;
+extern struct nvkm_oclass *g84_disp_oclass;
+extern struct nvkm_oclass *gt200_disp_oclass;
+extern struct nvkm_oclass *g94_disp_oclass;
+extern struct nvkm_oclass *gt215_disp_oclass;
+extern struct nvkm_oclass *gf110_disp_oclass;
+extern struct nvkm_oclass *gk104_disp_oclass;
+extern struct nvkm_oclass *gk110_disp_oclass;
+extern struct nvkm_oclass *gm107_disp_oclass;
+extern struct nvkm_oclass *gm204_disp_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 72a90c74506c..e4baae226379 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -113,7 +113,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0x86:
@@ -142,7 +142,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0x92:
@@ -171,7 +171,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0x94:
@@ -200,7 +200,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0x96:
@@ -229,7 +229,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0x98:
@@ -258,7 +258,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0xa0:
@@ -287,7 +287,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0xaa:
@@ -316,7 +316,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0xac:
@@ -345,7 +345,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
case 0xa3:
@@ -376,7 +376,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
break;
case 0xa5:
@@ -406,7 +406,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
break;
case 0xa8:
@@ -436,7 +436,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
break;
case 0xaf:
@@ -466,7 +466,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index fd87b8f955ed..9ef067398052 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -89,7 +89,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xc4:
@@ -122,7 +122,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xc3:
@@ -154,7 +154,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xce:
@@ -187,7 +187,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xcf:
@@ -219,7 +219,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xc1:
@@ -251,7 +251,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xc8:
@@ -284,7 +284,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xd9:
@@ -316,7 +316,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
case 0xd7:
@@ -346,7 +346,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 76cc21d383cb..1072ada31416 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -84,7 +84,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
@@ -118,7 +118,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
@@ -152,7 +152,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
@@ -208,7 +208,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
@@ -242,7 +242,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
@@ -276,7 +276,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
@@ -309,7 +309,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
+ device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
index 50bd1e2bb8fa..16a4e2a37008 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
@@ -4,26 +4,26 @@ nvkm-y += nvkm/engine/disp/outp.o
nvkm-y += nvkm/engine/disp/outpdp.o
nvkm-y += nvkm/engine/disp/nv04.o
nvkm-y += nvkm/engine/disp/nv50.o
-nvkm-y += nvkm/engine/disp/nv84.o
-nvkm-y += nvkm/engine/disp/nv94.o
-nvkm-y += nvkm/engine/disp/nva0.o
-nvkm-y += nvkm/engine/disp/nva3.o
-nvkm-y += nvkm/engine/disp/nvd0.o
-nvkm-y += nvkm/engine/disp/nve0.o
-nvkm-y += nvkm/engine/disp/nvf0.o
+nvkm-y += nvkm/engine/disp/g84.o
+nvkm-y += nvkm/engine/disp/g94.o
+nvkm-y += nvkm/engine/disp/gt200.o
+nvkm-y += nvkm/engine/disp/gt215.o
+nvkm-y += nvkm/engine/disp/gf110.o
+nvkm-y += nvkm/engine/disp/gk104.o
+nvkm-y += nvkm/engine/disp/gk110.o
nvkm-y += nvkm/engine/disp/gm107.o
nvkm-y += nvkm/engine/disp/gm204.o
nvkm-y += nvkm/engine/disp/dacnv50.o
nvkm-y += nvkm/engine/disp/dport.o
-nvkm-y += nvkm/engine/disp/hdanva3.o
-nvkm-y += nvkm/engine/disp/hdanvd0.o
-nvkm-y += nvkm/engine/disp/hdminv84.o
-nvkm-y += nvkm/engine/disp/hdminva3.o
-nvkm-y += nvkm/engine/disp/hdminvd0.o
-nvkm-y += nvkm/engine/disp/hdminve0.o
+nvkm-y += nvkm/engine/disp/hdagt215.o
+nvkm-y += nvkm/engine/disp/hdagf110.o
+nvkm-y += nvkm/engine/disp/hdmig84.o
+nvkm-y += nvkm/engine/disp/hdmigt215.o
+nvkm-y += nvkm/engine/disp/hdmigf110.o
+nvkm-y += nvkm/engine/disp/hdmigk104.o
nvkm-y += nvkm/engine/disp/piornv50.o
nvkm-y += nvkm/engine/disp/sornv50.o
-nvkm-y += nvkm/engine/disp/sornv94.o
-nvkm-y += nvkm/engine/disp/sornvd0.o
+nvkm-y += nvkm/engine/disp/sorg94.o
+nvkm-y += nvkm/engine/disp/sorgf110.o
nvkm-y += nvkm/engine/disp/sorgm204.o
nvkm-y += nvkm/engine/disp/vga.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
index c8a5f810e537..23d1b5c0dc16 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
@@ -21,21 +21,23 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
+#include "conn.h"
+#include "outp.h"
+
+#include <core/notify.h>
+#include <subdev/bios.h>
+#include <subdev/bios/dcb.h>
-#include <core/os.h>
-#include <nvif/unpack.h>
#include <nvif/class.h>
#include <nvif/event.h>
-
-#include "priv.h"
-#include "outp.h"
-#include "conn.h"
+#include <nvif/unpack.h>
int
-nouveau_disp_vblank_ctor(struct nouveau_object *object, void *data, u32 size,
- struct nvkm_notify *notify)
+nvkm_disp_vblank_ctor(struct nvkm_object *object, void *data, u32 size,
+ struct nvkm_notify *notify)
{
- struct nouveau_disp *disp =
+ struct nvkm_disp *disp =
container_of(notify->event, typeof(*disp), vblank);
union {
struct nvif_notify_head_req_v0 v0;
@@ -55,17 +57,17 @@ nouveau_disp_vblank_ctor(struct nouveau_object *object, void *data, u32 size,
}
void
-nouveau_disp_vblank(struct nouveau_disp *disp, int head)
+nvkm_disp_vblank(struct nvkm_disp *disp, int head)
{
struct nvif_notify_head_rep_v0 rep = {};
nvkm_event_send(&disp->vblank, 1, head, &rep, sizeof(rep));
}
static int
-nouveau_disp_hpd_ctor(struct nouveau_object *object, void *data, u32 size,
- struct nvkm_notify *notify)
+nvkm_disp_hpd_ctor(struct nvkm_object *object, void *data, u32 size,
+ struct nvkm_notify *notify)
{
- struct nouveau_disp *disp =
+ struct nvkm_disp *disp =
container_of(notify->event, typeof(*disp), hpd);
union {
struct nvif_notify_conn_req_v0 v0;
@@ -91,15 +93,14 @@ nouveau_disp_hpd_ctor(struct nouveau_object *object, void *data, u32 size,
}
static const struct nvkm_event_func
-nouveau_disp_hpd_func = {
- .ctor = nouveau_disp_hpd_ctor
+nvkm_disp_hpd_func = {
+ .ctor = nvkm_disp_hpd_ctor
};
int
-nouveau_disp_ntfy(struct nouveau_object *object, u32 type,
- struct nvkm_event **event)
+nvkm_disp_ntfy(struct nvkm_object *object, u32 type, struct nvkm_event **event)
{
- struct nouveau_disp *disp = (void *)object->engine;
+ struct nvkm_disp *disp = (void *)object->engine;
switch (type) {
case NV04_DISP_NTFY_VBLANK:
*event = &disp->vblank;
@@ -114,9 +115,9 @@ nouveau_disp_ntfy(struct nouveau_object *object, u32 type,
}
int
-_nouveau_disp_fini(struct nouveau_object *object, bool suspend)
+_nvkm_disp_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_disp *disp = (void *)object;
+ struct nvkm_disp *disp = (void *)object;
struct nvkm_output *outp;
int ret;
@@ -126,7 +127,7 @@ _nouveau_disp_fini(struct nouveau_object *object, bool suspend)
goto fail_outp;
}
- return nouveau_engine_fini(&disp->base, suspend);
+ return nvkm_engine_fini(&disp->base, suspend);
fail_outp:
list_for_each_entry_continue_reverse(outp, &disp->outp, head) {
@@ -137,13 +138,13 @@ fail_outp:
}
int
-_nouveau_disp_init(struct nouveau_object *object)
+_nvkm_disp_init(struct nvkm_object *object)
{
- struct nouveau_disp *disp = (void *)object;
+ struct nvkm_disp *disp = (void *)object;
struct nvkm_output *outp;
int ret;
- ret = nouveau_engine_init(&disp->base);
+ ret = nvkm_engine_init(&disp->base);
if (ret)
return ret;
@@ -164,9 +165,9 @@ fail_outp:
}
void
-_nouveau_disp_dtor(struct nouveau_object *object)
+_nvkm_disp_dtor(struct nvkm_object *object)
{
- struct nouveau_disp *disp = (void *)object;
+ struct nvkm_disp *disp = (void *)object;
struct nvkm_output *outp, *outt;
nvkm_event_fini(&disp->vblank);
@@ -174,32 +175,30 @@ _nouveau_disp_dtor(struct nouveau_object *object)
if (disp->outp.next) {
list_for_each_entry_safe(outp, outt, &disp->outp, head) {
- nouveau_object_ref(NULL, (struct nouveau_object **)&outp);
+ nvkm_object_ref(NULL, (struct nvkm_object **)&outp);
}
}
- nouveau_engine_destroy(&disp->base);
+ nvkm_engine_destroy(&disp->base);
}
int
-nouveau_disp_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int heads,
- const char *intname, const char *extname,
- int length, void **pobject)
+nvkm_disp_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int heads, const char *intname,
+ const char *extname, int length, void **pobject)
{
- struct nouveau_disp_impl *impl = (void *)oclass;
- struct nouveau_bios *bios = nouveau_bios(parent);
- struct nouveau_disp *disp;
- struct nouveau_oclass **sclass;
- struct nouveau_object *object;
+ struct nvkm_disp_impl *impl = (void *)oclass;
+ struct nvkm_bios *bios = nvkm_bios(parent);
+ struct nvkm_disp *disp;
+ struct nvkm_oclass **sclass;
+ struct nvkm_object *object;
struct dcb_output dcbE;
u8 hpd = 0, ver, hdr;
u32 data;
int ret, i;
- ret = nouveau_engine_create_(parent, engine, oclass, true,
- intname, extname, length, pobject);
+ ret = nvkm_engine_create_(parent, engine, oclass, true, intname,
+ extname, length, pobject);
disp = *pobject;
if (ret)
return ret;
@@ -225,11 +224,11 @@ nouveau_disp_create_(struct nouveau_object *parent,
sclass++;
}
- nouveau_object_ctor(*pobject, NULL, oclass, &dcbE, i, &object);
+ nvkm_object_ctor(*pobject, NULL, oclass, &dcbE, i, &object);
hpd = max(hpd, (u8)(dcbE.connector + 1));
}
- ret = nvkm_event_init(&nouveau_disp_hpd_func, 3, hpd, &disp->hpd);
+ ret = nvkm_event_init(&nvkm_disp_hpd_func, 3, hpd, &disp->hpd);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c
index 498ab4b8a9af..cf03e0240ced 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c
@@ -21,21 +21,20 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/os.h>
-#include <nvif/event.h>
+#include "conn.h"
+#include "outp.h"
+#include "priv.h"
#include <subdev/gpio.h>
-#include "conn.h"
-#include "outp.h"
+#include <nvif/event.h>
static int
nvkm_connector_hpd(struct nvkm_notify *notify)
{
struct nvkm_connector *conn = container_of(notify, typeof(*conn), hpd);
- struct nouveau_disp *disp = nouveau_disp(conn);
- struct nouveau_gpio *gpio = nouveau_gpio(conn);
+ struct nvkm_disp *disp = nvkm_disp(conn);
+ struct nvkm_gpio *gpio = nvkm_gpio(conn);
const struct nvkm_gpio_ntfy_rep *line = notify->data;
struct nvif_notify_conn_rep_v0 rep;
int index = conn->index;
@@ -53,41 +52,41 @@ nvkm_connector_hpd(struct nvkm_notify *notify)
}
int
-_nvkm_connector_fini(struct nouveau_object *object, bool suspend)
+_nvkm_connector_fini(struct nvkm_object *object, bool suspend)
{
struct nvkm_connector *conn = (void *)object;
nvkm_notify_put(&conn->hpd);
- return nouveau_object_fini(&conn->base, suspend);
+ return nvkm_object_fini(&conn->base, suspend);
}
int
-_nvkm_connector_init(struct nouveau_object *object)
+_nvkm_connector_init(struct nvkm_object *object)
{
struct nvkm_connector *conn = (void *)object;
- int ret = nouveau_object_init(&conn->base);
+ int ret = nvkm_object_init(&conn->base);
if (ret == 0)
nvkm_notify_get(&conn->hpd);
return ret;
}
void
-_nvkm_connector_dtor(struct nouveau_object *object)
+_nvkm_connector_dtor(struct nvkm_object *object)
{
struct nvkm_connector *conn = (void *)object;
nvkm_notify_fini(&conn->hpd);
- nouveau_object_destroy(&conn->base);
+ nvkm_object_destroy(&conn->base);
}
int
-nvkm_connector_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass,
+nvkm_connector_create_(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass,
struct nvbios_connE *info, int index,
int length, void **pobject)
{
static const u8 hpd[] = { 0x07, 0x08, 0x51, 0x52, 0x5e, 0x5f, 0x60 };
- struct nouveau_disp *disp = nouveau_disp(parent);
- struct nouveau_gpio *gpio = nouveau_gpio(parent);
+ struct nvkm_disp *disp = nvkm_disp(parent);
+ struct nvkm_gpio *gpio = nvkm_gpio(parent);
struct nvkm_connector *conn;
struct nvkm_output *outp;
struct dcb_gpio_func func;
@@ -101,7 +100,7 @@ nvkm_connector_create_(struct nouveau_object *parent,
}
}
- ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject);
+ ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject);
conn = *pobject;
if (ret)
return ret;
@@ -145,10 +144,10 @@ nvkm_connector_create_(struct nouveau_object *parent,
}
int
-_nvkm_connector_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *info, u32 index,
- struct nouveau_object **pobject)
+_nvkm_connector_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *info, u32 index,
+ struct nvkm_object **pobject)
{
struct nvkm_connector *conn;
int ret;
@@ -161,11 +160,11 @@ _nvkm_connector_ctor(struct nouveau_object *parent,
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nvkm_connector_oclass = &(struct nvkm_connector_impl) {
.base = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_connector_ctor,
.dtor = _nvkm_connector_dtor,
.init = _nvkm_connector_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h
index 4a92d9fa1d78..c87a061f7f7d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h
@@ -1,11 +1,13 @@
#ifndef __NVKM_DISP_CONN_H__
#define __NVKM_DISP_CONN_H__
-#include "priv.h"
-
+#include <core/object.h>
#include <core/notify.h>
+#include <subdev/bios.h>
+#include <subdev/bios/conn.h>
+
struct nvkm_connector {
- struct nouveau_object base;
+ struct nvkm_object base;
struct list_head head;
struct nvbios_connE info;
@@ -29,19 +31,19 @@ struct nvkm_connector {
_nvkm_connector_fini(nv_object(disp), (s)); \
})
-int nvkm_connector_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, struct nvbios_connE *,
+int nvkm_connector_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, struct nvbios_connE *,
int, int, void **);
-int _nvkm_connector_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void _nvkm_connector_dtor(struct nouveau_object *);
-int _nvkm_connector_init(struct nouveau_object *);
-int _nvkm_connector_fini(struct nouveau_object *, bool);
+int _nvkm_connector_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void _nvkm_connector_dtor(struct nvkm_object *);
+int _nvkm_connector_init(struct nvkm_object *);
+int _nvkm_connector_fini(struct nvkm_object *, bool);
struct nvkm_connector_impl {
- struct nouveau_oclass base;
+ struct nvkm_oclass base;
};
#ifndef MSG
@@ -53,5 +55,4 @@ struct nvkm_connector_impl {
#define DBG(f,a...) MSG(debug, f, ##a)
#define ERR(f,a...) MSG(error, f, ##a)
#endif
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c
index b36addff06a9..0f7d1ec4d37e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c
@@ -21,16 +21,14 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
+#include "outp.h"
#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
#include <subdev/timer.h>
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
int
nv50_dac_power(NV50_DISP_MTHD_V1)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c
index 16db08dfba6e..68347661adca 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c
@@ -21,20 +21,16 @@
*
* Authors: Ben Skeggs
*/
+#include "dport.h"
+#include "outpdp.h"
+#include "nv50.h"
#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
#include <subdev/bios/init.h>
#include <subdev/i2c.h>
-#include "nv50.h"
-
#include <nvif/class.h>
-#include "dport.h"
-#include "outpdp.h"
-
/******************************************************************************
* link training
*****************************************************************************/
@@ -54,8 +50,8 @@ dp_set_link_config(struct dp_state *dp)
{
struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
struct nvkm_output_dp *outp = dp->outp;
- struct nouveau_disp *disp = nouveau_disp(outp);
- struct nouveau_bios *bios = nouveau_bios(disp);
+ struct nvkm_disp *disp = nvkm_disp(outp);
+ struct nvkm_bios *bios = nvkm_bios(disp);
struct nvbios_init init = {
.subdev = nv_subdev(disp),
.bios = bios,
@@ -264,8 +260,8 @@ static void
dp_link_train_init(struct dp_state *dp, bool spread)
{
struct nvkm_output_dp *outp = dp->outp;
- struct nouveau_disp *disp = nouveau_disp(outp);
- struct nouveau_bios *bios = nouveau_bios(disp);
+ struct nvkm_disp *disp = nvkm_disp(outp);
+ struct nvkm_bios *bios = nvkm_bios(disp);
struct nvbios_init init = {
.subdev = nv_subdev(disp),
.bios = bios,
@@ -290,8 +286,8 @@ static void
dp_link_train_fini(struct dp_state *dp)
{
struct nvkm_output_dp *outp = dp->outp;
- struct nouveau_disp *disp = nouveau_disp(outp);
- struct nouveau_bios *bios = nouveau_bios(disp);
+ struct nvkm_disp *disp = nvkm_disp(outp);
+ struct nvkm_bios *bios = nvkm_bios(disp);
struct nvbios_init init = {
.subdev = nv_subdev(disp),
.bios = bios,
@@ -309,7 +305,7 @@ static const struct dp_rates {
u32 rate;
u8 bw;
u8 nr;
-} nouveau_dp_rates[] = {
+} nvkm_dp_rates[] = {
{ 2160000, 0x14, 4 },
{ 1080000, 0x0a, 4 },
{ 1080000, 0x14, 2 },
@@ -323,11 +319,11 @@ static const struct dp_rates {
};
void
-nouveau_dp_train(struct work_struct *w)
+nvkm_dp_train(struct work_struct *w)
{
struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work);
- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
- const struct dp_rates *cfg = nouveau_dp_rates;
+ struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+ const struct dp_rates *cfg = nvkm_dp_rates;
struct dp_state _dp = {
.outp = outp,
}, *dp = &_dp;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h
index 5628d2d5ec71..9596290329c7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h
@@ -1,5 +1,6 @@
#ifndef __NVKM_DISP_DPORT_H__
#define __NVKM_DISP_DPORT_H__
+#include <core/os.h>
/* DPCD Receiver Capabilities */
#define DPCD_RC00_DPCD_REV 0x00000
@@ -70,6 +71,5 @@
#define DPCD_LS0C_LANE1_POST_CURSOR2 0x0c
#define DPCD_LS0C_LANE0_POST_CURSOR2 0x03
-void nouveau_dp_train(struct work_struct *);
-
+void nvkm_dp_train(struct work_struct *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c
similarity index 82%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c
index 547926678710..a0dcf534cb20 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c
@@ -21,20 +21,16 @@
*
* Authors: Ben Skeggs
*/
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
#include <nvif/class.h>
-#include "nv50.h"
-
/*******************************************************************************
* EVO master channel object
******************************************************************************/
const struct nv50_disp_mthd_list
-nv84_disp_core_mthd_dac = {
+g84_disp_core_mthd_dac = {
.mthd = 0x0080,
.addr = 0x000008,
.data = {
@@ -46,7 +42,7 @@ nv84_disp_core_mthd_dac = {
};
const struct nv50_disp_mthd_list
-nv84_disp_core_mthd_head = {
+g84_disp_core_mthd_head = {
.mthd = 0x0400,
.addr = 0x000540,
.data = {
@@ -98,15 +94,15 @@ nv84_disp_core_mthd_head = {
};
const struct nv50_disp_mthd_chan
-nv84_disp_core_mthd_chan = {
+g84_disp_core_mthd_chan = {
.name = "Core",
.addr = 0x000000,
.data = {
{ "Global", 1, &nv50_disp_core_mthd_base },
- { "DAC", 3, &nv84_disp_core_mthd_dac },
+ { "DAC", 3, &g84_disp_core_mthd_dac },
{ "SOR", 2, &nv50_disp_core_mthd_sor },
{ "PIOR", 3, &nv50_disp_core_mthd_pior },
- { "HEAD", 2, &nv84_disp_core_mthd_head },
+ { "HEAD", 2, &g84_disp_core_mthd_head },
{}
}
};
@@ -116,7 +112,7 @@ nv84_disp_core_mthd_chan = {
******************************************************************************/
static const struct nv50_disp_mthd_list
-nv84_disp_base_mthd_base = {
+g84_disp_base_mthd_base = {
.mthd = 0x0000,
.addr = 0x000000,
.data = {
@@ -146,11 +142,11 @@ nv84_disp_base_mthd_base = {
};
const struct nv50_disp_mthd_chan
-nv84_disp_base_mthd_chan = {
+g84_disp_base_mthd_chan = {
.name = "Base",
.addr = 0x000540,
.data = {
- { "Global", 1, &nv84_disp_base_mthd_base },
+ { "Global", 1, &g84_disp_base_mthd_base },
{ "Image", 2, &nv50_disp_base_mthd_image },
{}
}
@@ -161,7 +157,7 @@ nv84_disp_base_mthd_chan = {
******************************************************************************/
static const struct nv50_disp_mthd_list
-nv84_disp_ovly_mthd_base = {
+g84_disp_ovly_mthd_base = {
.mthd = 0x0000,
.addr = 0x000000,
.data = {
@@ -189,11 +185,11 @@ nv84_disp_ovly_mthd_base = {
};
const struct nv50_disp_mthd_chan
-nv84_disp_ovly_mthd_chan = {
+g84_disp_ovly_mthd_chan = {
.name = "Overlay",
.addr = 0x000540,
.data = {
- { "Global", 1, &nv84_disp_ovly_mthd_base },
+ { "Global", 1, &g84_disp_ovly_mthd_base },
{}
}
};
@@ -202,8 +198,8 @@ nv84_disp_ovly_mthd_chan = {
* Base display object
******************************************************************************/
-static struct nouveau_oclass
-nv84_disp_sclass[] = {
+static struct nvkm_oclass
+g84_disp_sclass[] = {
{ G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
{ G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
{ G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
@@ -212,8 +208,8 @@ nv84_disp_sclass[] = {
{}
};
-static struct nouveau_oclass
-nv84_disp_main_oclass[] = {
+static struct nvkm_oclass
+g84_disp_main_oclass[] = {
{ G82_DISP, &nv50_disp_main_ofuncs },
{}
};
@@ -223,15 +219,15 @@ nv84_disp_main_oclass[] = {
******************************************************************************/
static int
-nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
int ret;
- ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
- "display", &priv);
+ ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
+ "display", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -240,11 +236,11 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret)
return ret;
- nv_engine(priv)->sclass = nv84_disp_main_oclass;
+ nv_engine(priv)->sclass = g84_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nv50_disp_intr;
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
- priv->sclass = nv84_disp_sclass;
+ priv->sclass = g84_disp_sclass;
priv->head.nr = 2;
priv->dac.nr = 3;
priv->sor.nr = 2;
@@ -252,25 +248,25 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
- priv->sor.hdmi = nv84_hdmi_ctrl;
+ priv->sor.hdmi = g84_hdmi_ctrl;
priv->pior.power = nv50_pior_power;
return 0;
}
-struct nouveau_oclass *
-nv84_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+g84_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x82),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv84_disp_ctor,
- .dtor = _nouveau_disp_dtor,
- .init = _nouveau_disp_init,
- .fini = _nouveau_disp_fini,
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g84_disp_ctor,
+ .dtor = _nvkm_disp_dtor,
+ .init = _nvkm_disp_init,
+ .fini = _nvkm_disp_fini,
},
.base.vblank = &nv50_disp_vblank_func,
.base.outp = nv50_disp_outp_sclass,
- .mthd.core = &nv84_disp_core_mthd_chan,
- .mthd.base = &nv84_disp_base_mthd_chan,
- .mthd.ovly = &nv84_disp_ovly_mthd_chan,
+ .mthd.core = &g84_disp_core_mthd_chan,
+ .mthd.base = &g84_disp_base_mthd_chan,
+ .mthd.ovly = &g84_disp_ovly_mthd_chan,
.mthd.prev = 0x000004,
.head.scanoutpos = nv50_disp_main_scanoutpos,
}.base.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
similarity index 72%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
index c009be4fb11c..1ab0d0ae3cc8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
@@ -21,20 +21,17 @@
*
* Authors: Ben Skeggs
*/
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
+#include "outpdp.h"
#include <nvif/class.h>
-#include "nv50.h"
-
/*******************************************************************************
* EVO master channel object
******************************************************************************/
const struct nv50_disp_mthd_list
-nv94_disp_core_mthd_sor = {
+g94_disp_core_mthd_sor = {
.mthd = 0x0040,
.addr = 0x000008,
.data = {
@@ -44,15 +41,15 @@ nv94_disp_core_mthd_sor = {
};
const struct nv50_disp_mthd_chan
-nv94_disp_core_mthd_chan = {
+g94_disp_core_mthd_chan = {
.name = "Core",
.addr = 0x000000,
.data = {
{ "Global", 1, &nv50_disp_core_mthd_base },
- { "DAC", 3, &nv84_disp_core_mthd_dac },
- { "SOR", 4, &nv94_disp_core_mthd_sor },
+ { "DAC", 3, &g84_disp_core_mthd_dac },
+ { "SOR", 4, &g94_disp_core_mthd_sor },
{ "PIOR", 3, &nv50_disp_core_mthd_pior },
- { "HEAD", 2, &nv84_disp_core_mthd_head },
+ { "HEAD", 2, &g84_disp_core_mthd_head },
{}
}
};
@@ -61,8 +58,8 @@ nv94_disp_core_mthd_chan = {
* Base display object
******************************************************************************/
-static struct nouveau_oclass
-nv94_disp_sclass[] = {
+static struct nvkm_oclass
+g94_disp_sclass[] = {
{ GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
@@ -71,8 +68,8 @@ nv94_disp_sclass[] = {
{}
};
-static struct nouveau_oclass
-nv94_disp_main_oclass[] = {
+static struct nvkm_oclass
+g94_disp_main_oclass[] = {
{ GT206_DISP, &nv50_disp_main_ofuncs },
{}
};
@@ -82,15 +79,15 @@ nv94_disp_main_oclass[] = {
******************************************************************************/
static int
-nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g94_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
int ret;
- ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
- "display", &priv);
+ ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
+ "display", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -99,11 +96,11 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret)
return ret;
- nv_engine(priv)->sclass = nv94_disp_main_oclass;
+ nv_engine(priv)->sclass = g94_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nv50_disp_intr;
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
- priv->sclass = nv94_disp_sclass;
+ priv->sclass = g94_disp_sclass;
priv->head.nr = 2;
priv->dac.nr = 3;
priv->sor.nr = 4;
@@ -111,32 +108,32 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
- priv->sor.hdmi = nv84_hdmi_ctrl;
+ priv->sor.hdmi = g84_hdmi_ctrl;
priv->pior.power = nv50_pior_power;
return 0;
}
-struct nouveau_oclass *
-nv94_disp_outp_sclass[] = {
+struct nvkm_oclass *
+g94_disp_outp_sclass[] = {
&nv50_pior_dp_impl.base.base,
- &nv94_sor_dp_impl.base.base,
+ &g94_sor_dp_impl.base.base,
NULL
};
-struct nouveau_oclass *
-nv94_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+g94_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x88),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv94_disp_ctor,
- .dtor = _nouveau_disp_dtor,
- .init = _nouveau_disp_init,
- .fini = _nouveau_disp_fini,
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g94_disp_ctor,
+ .dtor = _nvkm_disp_dtor,
+ .init = _nvkm_disp_init,
+ .fini = _nvkm_disp_fini,
},
.base.vblank = &nv50_disp_vblank_func,
- .base.outp = nv94_disp_outp_sclass,
- .mthd.core = &nv94_disp_core_mthd_chan,
- .mthd.base = &nv84_disp_base_mthd_chan,
- .mthd.ovly = &nv84_disp_ovly_mthd_chan,
+ .base.outp = g94_disp_outp_sclass,
+ .mthd.core = &g94_disp_core_mthd_chan,
+ .mthd.base = &g84_disp_base_mthd_chan,
+ .mthd.ovly = &g84_disp_ovly_mthd_chan,
.mthd.prev = 0x000004,
.head.scanoutpos = nv50_disp_main_scanoutpos,
}.base.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c
similarity index 83%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/nvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c
index 181a2d57e356..0ebf466e9ef3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvd0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c
@@ -21,33 +21,30 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
+#include "outp.h"
+#include "outpdp.h"
-#include <core/object.h>
#include <core/client.h>
-#include <core/parent.h>
-#include <core/handle.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <engine/disp.h>
-
+#include <core/gpuobj.h>
+#include <core/ramht.h>
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/disp.h>
#include <subdev/bios/init.h>
#include <subdev/bios/pll.h>
#include <subdev/devinit.h>
-#include <subdev/fb.h>
#include <subdev/timer.h>
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
/*******************************************************************************
* EVO channel base class
******************************************************************************/
static void
-nvd0_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
+gf110_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
{
struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000000 << index);
@@ -55,7 +52,7 @@ nvd0_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
}
static void
-nvd0_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
+gf110_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
{
struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
nv_wr32(priv, 0x61008c, 0x00000001 << index);
@@ -63,10 +60,10 @@ nvd0_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
}
const struct nvkm_event_func
-nvd0_disp_chan_uevent = {
+gf110_disp_chan_uevent = {
.ctor = nv50_disp_chan_uevent_ctor,
- .init = nvd0_disp_chan_uevent_init,
- .fini = nvd0_disp_chan_uevent_fini,
+ .init = gf110_disp_chan_uevent_init,
+ .fini = gf110_disp_chan_uevent_fini,
};
/*******************************************************************************
@@ -74,25 +71,25 @@ nvd0_disp_chan_uevent = {
******************************************************************************/
static int
-nvd0_disp_dmac_object_attach(struct nouveau_object *parent,
- struct nouveau_object *object, u32 name)
+gf110_disp_dmac_object_attach(struct nvkm_object *parent,
+ struct nvkm_object *object, u32 name)
{
struct nv50_disp_base *base = (void *)parent->parent;
struct nv50_disp_chan *chan = (void *)parent;
u32 addr = nv_gpuobj(object)->node->offset;
u32 data = (chan->chid << 27) | (addr << 9) | 0x00000001;
- return nouveau_ramht_insert(base->ramht, chan->chid, name, data);
+ return nvkm_ramht_insert(base->ramht, chan->chid, name, data);
}
static void
-nvd0_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
+gf110_disp_dmac_object_detach(struct nvkm_object *parent, int cookie)
{
struct nv50_disp_base *base = (void *)parent->parent;
- nouveau_ramht_remove(base->ramht, cookie);
+ nvkm_ramht_remove(base->ramht, cookie);
}
static int
-nvd0_disp_dmac_init(struct nouveau_object *object)
+gf110_disp_dmac_init(struct nvkm_object *object)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *dmac = (void *)object;
@@ -125,7 +122,7 @@ nvd0_disp_dmac_init(struct nouveau_object *object)
}
static int
-nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend)
+gf110_disp_dmac_fini(struct nvkm_object *object, bool suspend)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *dmac = (void *)object;
@@ -153,7 +150,7 @@ nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend)
******************************************************************************/
const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_base = {
+gf110_disp_core_mthd_base = {
.mthd = 0x0000,
.addr = 0x000000,
.data = {
@@ -166,7 +163,7 @@ nvd0_disp_core_mthd_base = {
};
const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_dac = {
+gf110_disp_core_mthd_dac = {
.mthd = 0x0020,
.addr = 0x000020,
.data = {
@@ -179,7 +176,7 @@ nvd0_disp_core_mthd_dac = {
};
const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_sor = {
+gf110_disp_core_mthd_sor = {
.mthd = 0x0020,
.addr = 0x000020,
.data = {
@@ -192,7 +189,7 @@ nvd0_disp_core_mthd_sor = {
};
const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_pior = {
+gf110_disp_core_mthd_pior = {
.mthd = 0x0020,
.addr = 0x000020,
.data = {
@@ -205,7 +202,7 @@ nvd0_disp_core_mthd_pior = {
};
static const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_head = {
+gf110_disp_core_mthd_head = {
.mthd = 0x0300,
.addr = 0x000300,
.data = {
@@ -279,21 +276,21 @@ nvd0_disp_core_mthd_head = {
};
static const struct nv50_disp_mthd_chan
-nvd0_disp_core_mthd_chan = {
+gf110_disp_core_mthd_chan = {
.name = "Core",
.addr = 0x000000,
.data = {
- { "Global", 1, &nvd0_disp_core_mthd_base },
- { "DAC", 3, &nvd0_disp_core_mthd_dac },
- { "SOR", 8, &nvd0_disp_core_mthd_sor },
- { "PIOR", 4, &nvd0_disp_core_mthd_pior },
- { "HEAD", 4, &nvd0_disp_core_mthd_head },
+ { "Global", 1, &gf110_disp_core_mthd_base },
+ { "DAC", 3, &gf110_disp_core_mthd_dac },
+ { "SOR", 8, &gf110_disp_core_mthd_sor },
+ { "PIOR", 4, &gf110_disp_core_mthd_pior },
+ { "HEAD", 4, &gf110_disp_core_mthd_head },
{}
}
};
static int
-nvd0_disp_core_init(struct nouveau_object *object)
+gf110_disp_core_init(struct nvkm_object *object)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *mast = (void *)object;
@@ -324,7 +321,7 @@ nvd0_disp_core_init(struct nouveau_object *object)
}
static int
-nvd0_disp_core_fini(struct nouveau_object *object, bool suspend)
+gf110_disp_core_fini(struct nvkm_object *object, bool suspend)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *mast = (void *)object;
@@ -346,18 +343,18 @@ nvd0_disp_core_fini(struct nouveau_object *object, bool suspend)
}
struct nv50_disp_chan_impl
-nvd0_disp_core_ofuncs = {
+gf110_disp_core_ofuncs = {
.base.ctor = nv50_disp_core_ctor,
.base.dtor = nv50_disp_dmac_dtor,
- .base.init = nvd0_disp_core_init,
- .base.fini = nvd0_disp_core_fini,
+ .base.init = gf110_disp_core_init,
+ .base.fini = gf110_disp_core_fini,
.base.ntfy = nv50_disp_chan_ntfy,
.base.map = nv50_disp_chan_map,
.base.rd32 = nv50_disp_chan_rd32,
.base.wr32 = nv50_disp_chan_wr32,
.chid = 0,
- .attach = nvd0_disp_dmac_object_attach,
- .detach = nvd0_disp_dmac_object_detach,
+ .attach = gf110_disp_dmac_object_attach,
+ .detach = gf110_disp_dmac_object_detach,
};
/*******************************************************************************
@@ -365,7 +362,7 @@ nvd0_disp_core_ofuncs = {
******************************************************************************/
static const struct nv50_disp_mthd_list
-nvd0_disp_base_mthd_base = {
+gf110_disp_base_mthd_base = {
.mthd = 0x0000,
.addr = 0x000000,
.data = {
@@ -415,7 +412,7 @@ nvd0_disp_base_mthd_base = {
};
static const struct nv50_disp_mthd_list
-nvd0_disp_base_mthd_image = {
+gf110_disp_base_mthd_image = {
.mthd = 0x0400,
.addr = 0x000400,
.data = {
@@ -429,29 +426,29 @@ nvd0_disp_base_mthd_image = {
};
const struct nv50_disp_mthd_chan
-nvd0_disp_base_mthd_chan = {
+gf110_disp_base_mthd_chan = {
.name = "Base",
.addr = 0x001000,
.data = {
- { "Global", 1, &nvd0_disp_base_mthd_base },
- { "Image", 2, &nvd0_disp_base_mthd_image },
+ { "Global", 1, &gf110_disp_base_mthd_base },
+ { "Image", 2, &gf110_disp_base_mthd_image },
{}
}
};
struct nv50_disp_chan_impl
-nvd0_disp_base_ofuncs = {
+gf110_disp_base_ofuncs = {
.base.ctor = nv50_disp_base_ctor,
.base.dtor = nv50_disp_dmac_dtor,
- .base.init = nvd0_disp_dmac_init,
- .base.fini = nvd0_disp_dmac_fini,
+ .base.init = gf110_disp_dmac_init,
+ .base.fini = gf110_disp_dmac_fini,
.base.ntfy = nv50_disp_chan_ntfy,
.base.map = nv50_disp_chan_map,
.base.rd32 = nv50_disp_chan_rd32,
.base.wr32 = nv50_disp_chan_wr32,
.chid = 1,
- .attach = nvd0_disp_dmac_object_attach,
- .detach = nvd0_disp_dmac_object_detach,
+ .attach = gf110_disp_dmac_object_attach,
+ .detach = gf110_disp_dmac_object_detach,
};
/*******************************************************************************
@@ -459,7 +456,7 @@ nvd0_disp_base_ofuncs = {
******************************************************************************/
static const struct nv50_disp_mthd_list
-nvd0_disp_ovly_mthd_base = {
+gf110_disp_ovly_mthd_base = {
.mthd = 0x0000,
.data = {
{ 0x0080, 0x665080 },
@@ -511,28 +508,28 @@ nvd0_disp_ovly_mthd_base = {
};
static const struct nv50_disp_mthd_chan
-nvd0_disp_ovly_mthd_chan = {
+gf110_disp_ovly_mthd_chan = {
.name = "Overlay",
.addr = 0x001000,
.data = {
- { "Global", 1, &nvd0_disp_ovly_mthd_base },
+ { "Global", 1, &gf110_disp_ovly_mthd_base },
{}
}
};
struct nv50_disp_chan_impl
-nvd0_disp_ovly_ofuncs = {
+gf110_disp_ovly_ofuncs = {
.base.ctor = nv50_disp_ovly_ctor,
.base.dtor = nv50_disp_dmac_dtor,
- .base.init = nvd0_disp_dmac_init,
- .base.fini = nvd0_disp_dmac_fini,
+ .base.init = gf110_disp_dmac_init,
+ .base.fini = gf110_disp_dmac_fini,
.base.ntfy = nv50_disp_chan_ntfy,
.base.map = nv50_disp_chan_map,
.base.rd32 = nv50_disp_chan_rd32,
.base.wr32 = nv50_disp_chan_wr32,
.chid = 5,
- .attach = nvd0_disp_dmac_object_attach,
- .detach = nvd0_disp_dmac_object_detach,
+ .attach = gf110_disp_dmac_object_attach,
+ .detach = gf110_disp_dmac_object_detach,
};
/*******************************************************************************
@@ -540,7 +537,7 @@ nvd0_disp_ovly_ofuncs = {
******************************************************************************/
static int
-nvd0_disp_pioc_init(struct nouveau_object *object)
+gf110_disp_pioc_init(struct nvkm_object *object)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_pioc *pioc = (void *)object;
@@ -566,7 +563,7 @@ nvd0_disp_pioc_init(struct nouveau_object *object)
}
static int
-nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend)
+gf110_disp_pioc_fini(struct nvkm_object *object, bool suspend)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_pioc *pioc = (void *)object;
@@ -592,11 +589,11 @@ nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend)
******************************************************************************/
struct nv50_disp_chan_impl
-nvd0_disp_oimm_ofuncs = {
+gf110_disp_oimm_ofuncs = {
.base.ctor = nv50_disp_oimm_ctor,
.base.dtor = nv50_disp_pioc_dtor,
- .base.init = nvd0_disp_pioc_init,
- .base.fini = nvd0_disp_pioc_fini,
+ .base.init = gf110_disp_pioc_init,
+ .base.fini = gf110_disp_pioc_fini,
.base.ntfy = nv50_disp_chan_ntfy,
.base.map = nv50_disp_chan_map,
.base.rd32 = nv50_disp_chan_rd32,
@@ -609,11 +606,11 @@ nvd0_disp_oimm_ofuncs = {
******************************************************************************/
struct nv50_disp_chan_impl
-nvd0_disp_curs_ofuncs = {
+gf110_disp_curs_ofuncs = {
.base.ctor = nv50_disp_curs_ctor,
.base.dtor = nv50_disp_pioc_dtor,
- .base.init = nvd0_disp_pioc_init,
- .base.fini = nvd0_disp_pioc_fini,
+ .base.init = gf110_disp_pioc_init,
+ .base.fini = gf110_disp_pioc_fini,
.base.ntfy = nv50_disp_chan_ntfy,
.base.map = nv50_disp_chan_map,
.base.rd32 = nv50_disp_chan_rd32,
@@ -626,7 +623,7 @@ nvd0_disp_curs_ofuncs = {
******************************************************************************/
int
-nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
+gf110_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
{
const u32 total = nv_rd32(priv, 0x640414 + (head * 0x300));
const u32 blanke = nv_rd32(priv, 0x64041c + (head * 0x300));
@@ -658,14 +655,14 @@ nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
}
static int
-nvd0_disp_main_init(struct nouveau_object *object)
+gf110_disp_main_init(struct nvkm_object *object)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_base *base = (void *)object;
int ret, i;
u32 tmp;
- ret = nouveau_parent_init(&base->base);
+ ret = nvkm_parent_init(&base->base);
if (ret)
return ret;
@@ -715,7 +712,7 @@ nvd0_disp_main_init(struct nouveau_object *object)
nv_wr32(priv, 0x6100b0, 0x00000307);
/* disable underflow reporting, preventing an intermittent issue
- * on some nve4 boards where the production vbios left this
+ * on some gk104 boards where the production vbios left this
* setting enabled by default.
*
* ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
@@ -727,7 +724,7 @@ nvd0_disp_main_init(struct nouveau_object *object)
}
static int
-nvd0_disp_main_fini(struct nouveau_object *object, bool suspend)
+gf110_disp_main_fini(struct nvkm_object *object, bool suspend)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_base *base = (void *)object;
@@ -735,32 +732,32 @@ nvd0_disp_main_fini(struct nouveau_object *object, bool suspend)
/* disable all interrupts */
nv_wr32(priv, 0x6100b0, 0x00000000);
- return nouveau_parent_fini(&base->base, suspend);
+ return nvkm_parent_fini(&base->base, suspend);
}
-struct nouveau_ofuncs
-nvd0_disp_main_ofuncs = {
+struct nvkm_ofuncs
+gf110_disp_main_ofuncs = {
.ctor = nv50_disp_main_ctor,
.dtor = nv50_disp_main_dtor,
- .init = nvd0_disp_main_init,
- .fini = nvd0_disp_main_fini,
+ .init = gf110_disp_main_init,
+ .fini = gf110_disp_main_fini,
.mthd = nv50_disp_main_mthd,
- .ntfy = nouveau_disp_ntfy,
+ .ntfy = nvkm_disp_ntfy,
};
-static struct nouveau_oclass
-nvd0_disp_main_oclass[] = {
- { GF110_DISP, &nvd0_disp_main_ofuncs },
+static struct nvkm_oclass
+gf110_disp_main_oclass[] = {
+ { GF110_DISP, &gf110_disp_main_ofuncs },
{}
};
-static struct nouveau_oclass
-nvd0_disp_sclass[] = {
- { GF110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
- { GF110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
- { GF110_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
- { GF110_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
- { GF110_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
+static struct nvkm_oclass
+gf110_disp_sclass[] = {
+ { GF110_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
+ { GF110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
+ { GF110_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
+ { GF110_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
+ { GF110_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
{}
};
@@ -769,24 +766,24 @@ nvd0_disp_sclass[] = {
******************************************************************************/
static void
-nvd0_disp_vblank_init(struct nvkm_event *event, int type, int head)
+gf110_disp_vblank_init(struct nvkm_event *event, int type, int head)
{
- struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
+ struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
nv_mask(disp, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001);
}
static void
-nvd0_disp_vblank_fini(struct nvkm_event *event, int type, int head)
+gf110_disp_vblank_fini(struct nvkm_event *event, int type, int head)
{
- struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
+ struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
nv_mask(disp, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000);
}
const struct nvkm_event_func
-nvd0_disp_vblank_func = {
- .ctor = nouveau_disp_vblank_ctor,
- .init = nvd0_disp_vblank_init,
- .fini = nvd0_disp_vblank_fini,
+gf110_disp_vblank_func = {
+ .ctor = nvkm_disp_vblank_ctor,
+ .init = gf110_disp_vblank_init,
+ .fini = gf110_disp_vblank_fini,
};
static struct nvkm_output *
@@ -794,7 +791,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl,
u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_outp *info)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvkm_output *outp;
u16 mask, type;
@@ -838,7 +835,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl,
static struct nvkm_output *
exec_script(struct nv50_disp_priv *priv, int head, int id)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvkm_output *outp;
struct nvbios_outp info;
u8 ver, hdr, cnt, len;
@@ -874,7 +871,7 @@ exec_script(struct nv50_disp_priv *priv, int head, int id)
static struct nvkm_output *
exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvkm_output *outp;
struct nvbios_outp info1;
struct nvbios_ocfg info2;
@@ -934,13 +931,13 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf)
}
static void
-nvd0_disp_intr_unk1_0(struct nv50_disp_priv *priv, int head)
+gf110_disp_intr_unk1_0(struct nv50_disp_priv *priv, int head)
{
exec_script(priv, head, 1);
}
static void
-nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head)
+gf110_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head)
{
struct nvkm_output *outp = exec_script(priv, head, 2);
@@ -949,7 +946,7 @@ nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head)
struct nvkm_output_dp *outpdp = (void *)outp;
struct nvbios_init init = {
.subdev = nv_subdev(priv),
- .bios = nouveau_bios(priv),
+ .bios = nvkm_bios(priv),
.outp = &outp->info,
.crtc = head,
.offset = outpdp->info.script[4],
@@ -962,9 +959,9 @@ nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head)
}
static void
-nvd0_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head)
+gf110_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head)
{
- struct nouveau_devinit *devinit = nouveau_devinit(priv);
+ struct nvkm_devinit *devinit = nvkm_devinit(priv);
u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
if (pclk)
devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
@@ -972,8 +969,8 @@ nvd0_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head)
}
static void
-nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head,
- struct dcb_output *outp)
+gf110_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head,
+ struct dcb_output *outp)
{
const int or = ffs(outp->or) - 1;
const u32 ctrl = nv_rd32(priv, 0x660200 + (or * 0x020));
@@ -1033,7 +1030,7 @@ nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head,
}
static void
-nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
+gf110_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
{
struct nvkm_output *outp;
u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
@@ -1075,7 +1072,7 @@ nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
nv_mask(priv, addr, 0x007c0000, 0x00280000);
break;
case DCB_OUTPUT_DP:
- nvd0_disp_intr_unk2_2_tu(priv, head, &outp->info);
+ gf110_disp_intr_unk2_2_tu(priv, head, &outp->info);
break;
default:
break;
@@ -1086,7 +1083,7 @@ nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
}
static void
-nvd0_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head)
+gf110_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head)
{
u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
u32 conf;
@@ -1095,7 +1092,7 @@ nvd0_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head)
}
void
-nvd0_disp_intr_supervisor(struct work_struct *work)
+gf110_disp_intr_supervisor(struct work_struct *work)
{
struct nv50_disp_priv *priv =
container_of(work, struct nv50_disp_priv, supervisor);
@@ -1115,7 +1112,7 @@ nvd0_disp_intr_supervisor(struct work_struct *work)
if (!(mask[head] & 0x00001000))
continue;
nv_debug(priv, "supervisor 1.0 - head %d\n", head);
- nvd0_disp_intr_unk1_0(priv, head);
+ gf110_disp_intr_unk1_0(priv, head);
}
} else
if (priv->super & 0x00000002) {
@@ -1123,19 +1120,19 @@ nvd0_disp_intr_supervisor(struct work_struct *work)
if (!(mask[head] & 0x00001000))
continue;
nv_debug(priv, "supervisor 2.0 - head %d\n", head);
- nvd0_disp_intr_unk2_0(priv, head);
+ gf110_disp_intr_unk2_0(priv, head);
}
for (head = 0; head < priv->head.nr; head++) {
if (!(mask[head] & 0x00010000))
continue;
nv_debug(priv, "supervisor 2.1 - head %d\n", head);
- nvd0_disp_intr_unk2_1(priv, head);
+ gf110_disp_intr_unk2_1(priv, head);
}
for (head = 0; head < priv->head.nr; head++) {
if (!(mask[head] & 0x00001000))
continue;
nv_debug(priv, "supervisor 2.2 - head %d\n", head);
- nvd0_disp_intr_unk2_2(priv, head);
+ gf110_disp_intr_unk2_2(priv, head);
}
} else
if (priv->super & 0x00000004) {
@@ -1143,7 +1140,7 @@ nvd0_disp_intr_supervisor(struct work_struct *work)
if (!(mask[head] & 0x00001000))
continue;
nv_debug(priv, "supervisor 3.0 - head %d\n", head);
- nvd0_disp_intr_unk4_0(priv, head);
+ gf110_disp_intr_unk4_0(priv, head);
}
}
@@ -1153,7 +1150,7 @@ nvd0_disp_intr_supervisor(struct work_struct *work)
}
static void
-nvd0_disp_intr_error(struct nv50_disp_priv *priv, int chid)
+gf110_disp_intr_error(struct nv50_disp_priv *priv, int chid)
{
const struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass;
u32 mthd = nv_rd32(priv, 0x6101f0 + (chid * 12));
@@ -1200,7 +1197,7 @@ nvd0_disp_intr_error(struct nv50_disp_priv *priv, int chid)
}
void
-nvd0_disp_intr(struct nouveau_subdev *subdev)
+gf110_disp_intr(struct nvkm_subdev *subdev)
{
struct nv50_disp_priv *priv = (void *)subdev;
u32 intr = nv_rd32(priv, 0x610088);
@@ -1220,7 +1217,7 @@ nvd0_disp_intr(struct nouveau_subdev *subdev)
u32 stat = nv_rd32(priv, 0x61009c);
int chid = ffs(stat) - 1;
if (chid >= 0)
- nvd0_disp_intr_error(priv, chid);
+ gf110_disp_intr_error(priv, chid);
intr &= ~0x00000002;
}
@@ -1246,7 +1243,7 @@ nvd0_disp_intr(struct nouveau_subdev *subdev)
if (mask & intr) {
u32 stat = nv_rd32(priv, 0x6100bc + (i * 0x800));
if (stat & 0x00000001)
- nouveau_disp_vblank(&priv->base, i);
+ nvkm_disp_vblank(&priv->base, i);
nv_mask(priv, 0x6100bc + (i * 0x800), 0, 0);
nv_rd32(priv, 0x6100c0 + (i * 0x800));
}
@@ -1254,60 +1251,60 @@ nvd0_disp_intr(struct nouveau_subdev *subdev)
}
static int
-nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
int heads = nv_rd32(parent, 0x022448);
int ret;
- ret = nouveau_disp_create(parent, engine, oclass, heads,
- "PDISP", "display", &priv);
+ ret = nvkm_disp_create(parent, engine, oclass, heads,
+ "PDISP", "display", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+ ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
if (ret)
return ret;
- nv_engine(priv)->sclass = nvd0_disp_main_oclass;
+ nv_engine(priv)->sclass = gf110_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
- nv_subdev(priv)->intr = nvd0_disp_intr;
- INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
- priv->sclass = nvd0_disp_sclass;
+ nv_subdev(priv)->intr = gf110_disp_intr;
+ INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
+ priv->sclass = gf110_disp_sclass;
priv->head.nr = heads;
priv->dac.nr = 3;
priv->sor.nr = 4;
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
- priv->sor.hda_eld = nvd0_hda_eld;
- priv->sor.hdmi = nvd0_hdmi_ctrl;
+ priv->sor.hda_eld = gf110_hda_eld;
+ priv->sor.hdmi = gf110_hdmi_ctrl;
return 0;
}
-struct nouveau_oclass *
-nvd0_disp_outp_sclass[] = {
- &nvd0_sor_dp_impl.base.base,
+struct nvkm_oclass *
+gf110_disp_outp_sclass[] = {
+ &gf110_sor_dp_impl.base.base,
NULL
};
-struct nouveau_oclass *
-nvd0_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+gf110_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x90),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvd0_disp_ctor,
- .dtor = _nouveau_disp_dtor,
- .init = _nouveau_disp_init,
- .fini = _nouveau_disp_fini,
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf110_disp_ctor,
+ .dtor = _nvkm_disp_dtor,
+ .init = _nvkm_disp_init,
+ .fini = _nvkm_disp_fini,
},
- .base.vblank = &nvd0_disp_vblank_func,
- .base.outp = nvd0_disp_outp_sclass,
- .mthd.core = &nvd0_disp_core_mthd_chan,
- .mthd.base = &nvd0_disp_base_mthd_chan,
- .mthd.ovly = &nvd0_disp_ovly_mthd_chan,
+ .base.vblank = &gf110_disp_vblank_func,
+ .base.outp = gf110_disp_outp_sclass,
+ .mthd.core = &gf110_disp_core_mthd_chan,
+ .mthd.base = &gf110_disp_base_mthd_chan,
+ .mthd.ovly = &gf110_disp_ovly_mthd_chan,
.mthd.prev = -0x020000,
- .head.scanoutpos = nvd0_disp_main_scanoutpos,
+ .head.scanoutpos = gf110_disp_main_scanoutpos,
}.base.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c
similarity index 74%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c
index 063cb4ad304c..6f4019ab4e65 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c
@@ -21,20 +21,16 @@
*
* Authors: Ben Skeggs
*/
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
#include <nvif/class.h>
-#include "nv50.h"
-
/*******************************************************************************
* EVO master channel object
******************************************************************************/
static const struct nv50_disp_mthd_list
-nve0_disp_core_mthd_head = {
+gk104_disp_core_mthd_head = {
.mthd = 0x0300,
.addr = 0x000300,
.data = {
@@ -113,15 +109,15 @@ nve0_disp_core_mthd_head = {
};
const struct nv50_disp_mthd_chan
-nve0_disp_core_mthd_chan = {
+gk104_disp_core_mthd_chan = {
.name = "Core",
.addr = 0x000000,
.data = {
- { "Global", 1, &nvd0_disp_core_mthd_base },
- { "DAC", 3, &nvd0_disp_core_mthd_dac },
- { "SOR", 8, &nvd0_disp_core_mthd_sor },
- { "PIOR", 4, &nvd0_disp_core_mthd_pior },
- { "HEAD", 4, &nve0_disp_core_mthd_head },
+ { "Global", 1, &gf110_disp_core_mthd_base },
+ { "DAC", 3, &gf110_disp_core_mthd_dac },
+ { "SOR", 8, &gf110_disp_core_mthd_sor },
+ { "PIOR", 4, &gf110_disp_core_mthd_pior },
+ { "HEAD", 4, &gk104_disp_core_mthd_head },
{}
}
};
@@ -131,7 +127,7 @@ nve0_disp_core_mthd_chan = {
******************************************************************************/
static const struct nv50_disp_mthd_list
-nve0_disp_ovly_mthd_base = {
+gk104_disp_ovly_mthd_base = {
.mthd = 0x0000,
.data = {
{ 0x0080, 0x665080 },
@@ -185,11 +181,11 @@ nve0_disp_ovly_mthd_base = {
};
const struct nv50_disp_mthd_chan
-nve0_disp_ovly_mthd_chan = {
+gk104_disp_ovly_mthd_chan = {
.name = "Overlay",
.addr = 0x001000,
.data = {
- { "Global", 1, &nve0_disp_ovly_mthd_base },
+ { "Global", 1, &gk104_disp_ovly_mthd_base },
{}
}
};
@@ -198,19 +194,19 @@ nve0_disp_ovly_mthd_chan = {
* Base display object
******************************************************************************/
-static struct nouveau_oclass
-nve0_disp_sclass[] = {
- { GK104_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
- { GK104_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
- { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
- { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
- { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
+static struct nvkm_oclass
+gk104_disp_sclass[] = {
+ { GK104_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
+ { GK104_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
+ { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
+ { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
+ { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
{}
};
-static struct nouveau_oclass
-nve0_disp_main_oclass[] = {
- { GK104_DISP, &nvd0_disp_main_ofuncs },
+static struct nvkm_oclass
+gk104_disp_main_oclass[] = {
+ { GK104_DISP, &gf110_disp_main_ofuncs },
{}
};
@@ -219,54 +215,54 @@ nve0_disp_main_oclass[] = {
******************************************************************************/
static int
-nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
int heads = nv_rd32(parent, 0x022448);
int ret;
- ret = nouveau_disp_create(parent, engine, oclass, heads,
- "PDISP", "display", &priv);
+ ret = nvkm_disp_create(parent, engine, oclass, heads,
+ "PDISP", "display", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+ ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
if (ret)
return ret;
- nv_engine(priv)->sclass = nve0_disp_main_oclass;
+ nv_engine(priv)->sclass = gk104_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
- nv_subdev(priv)->intr = nvd0_disp_intr;
- INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
- priv->sclass = nve0_disp_sclass;
+ nv_subdev(priv)->intr = gf110_disp_intr;
+ INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
+ priv->sclass = gk104_disp_sclass;
priv->head.nr = heads;
priv->dac.nr = 3;
priv->sor.nr = 4;
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
- priv->sor.hda_eld = nvd0_hda_eld;
- priv->sor.hdmi = nve0_hdmi_ctrl;
+ priv->sor.hda_eld = gf110_hda_eld;
+ priv->sor.hdmi = gk104_hdmi_ctrl;
return 0;
}
-struct nouveau_oclass *
-nve0_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+gk104_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x91),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_disp_ctor,
- .dtor = _nouveau_disp_dtor,
- .init = _nouveau_disp_init,
- .fini = _nouveau_disp_fini,
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_disp_ctor,
+ .dtor = _nvkm_disp_dtor,
+ .init = _nvkm_disp_init,
+ .fini = _nvkm_disp_fini,
},
- .base.vblank = &nvd0_disp_vblank_func,
- .base.outp = nvd0_disp_outp_sclass,
- .mthd.core = &nve0_disp_core_mthd_chan,
- .mthd.base = &nvd0_disp_base_mthd_chan,
- .mthd.ovly = &nve0_disp_ovly_mthd_chan,
+ .base.vblank = &gf110_disp_vblank_func,
+ .base.outp = gf110_disp_outp_sclass,
+ .mthd.core = &gk104_disp_core_mthd_chan,
+ .mthd.base = &gf110_disp_base_mthd_chan,
+ .mthd.ovly = &gk104_disp_ovly_mthd_chan,
.mthd.prev = -0x020000,
- .head.scanoutpos = nvd0_disp_main_scanoutpos,
+ .head.scanoutpos = gf110_disp_main_scanoutpos,
}.base.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c
similarity index 56%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c
index 3fd9b462d51f..daa4b460a6ba 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c
@@ -21,31 +21,27 @@
*
* Authors: Ben Skeggs
*/
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
#include <nvif/class.h>
-#include "nv50.h"
-
/*******************************************************************************
* Base display object
******************************************************************************/
-static struct nouveau_oclass
-nvf0_disp_sclass[] = {
- { GK110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
- { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
- { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
- { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
- { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
+static struct nvkm_oclass
+gk110_disp_sclass[] = {
+ { GK110_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
+ { GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
+ { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
+ { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
+ { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
{}
};
-static struct nouveau_oclass
-nvf0_disp_main_oclass[] = {
- { GK110_DISP, &nvd0_disp_main_ofuncs },
+static struct nvkm_oclass
+gk110_disp_main_oclass[] = {
+ { GK110_DISP, &gf110_disp_main_ofuncs },
{}
};
@@ -54,54 +50,54 @@ nvf0_disp_main_oclass[] = {
******************************************************************************/
static int
-nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
int heads = nv_rd32(parent, 0x022448);
int ret;
- ret = nouveau_disp_create(parent, engine, oclass, heads,
- "PDISP", "display", &priv);
+ ret = nvkm_disp_create(parent, engine, oclass, heads,
+ "PDISP", "display", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+ ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
if (ret)
return ret;
- nv_engine(priv)->sclass = nvf0_disp_main_oclass;
+ nv_engine(priv)->sclass = gk110_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
- nv_subdev(priv)->intr = nvd0_disp_intr;
- INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
- priv->sclass = nvf0_disp_sclass;
+ nv_subdev(priv)->intr = gf110_disp_intr;
+ INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
+ priv->sclass = gk110_disp_sclass;
priv->head.nr = heads;
priv->dac.nr = 3;
priv->sor.nr = 4;
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
- priv->sor.hda_eld = nvd0_hda_eld;
- priv->sor.hdmi = nve0_hdmi_ctrl;
+ priv->sor.hda_eld = gf110_hda_eld;
+ priv->sor.hdmi = gk104_hdmi_ctrl;
return 0;
}
-struct nouveau_oclass *
-nvf0_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+gk110_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x92),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvf0_disp_ctor,
- .dtor = _nouveau_disp_dtor,
- .init = _nouveau_disp_init,
- .fini = _nouveau_disp_fini,
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk110_disp_ctor,
+ .dtor = _nvkm_disp_dtor,
+ .init = _nvkm_disp_init,
+ .fini = _nvkm_disp_fini,
},
- .base.vblank = &nvd0_disp_vblank_func,
- .base.outp = nvd0_disp_outp_sclass,
- .mthd.core = &nve0_disp_core_mthd_chan,
- .mthd.base = &nvd0_disp_base_mthd_chan,
- .mthd.ovly = &nve0_disp_ovly_mthd_chan,
+ .base.vblank = &gf110_disp_vblank_func,
+ .base.outp = gf110_disp_outp_sclass,
+ .mthd.core = &gk104_disp_core_mthd_chan,
+ .mthd.base = &gf110_disp_base_mthd_chan,
+ .mthd.ovly = &gk104_disp_ovly_mthd_chan,
.mthd.prev = -0x020000,
- .head.scanoutpos = nvd0_disp_main_scanoutpos,
+ .head.scanoutpos = gf110_disp_main_scanoutpos,
}.base.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
index 26aaa2a201e5..881cc94385a1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
@@ -21,31 +21,27 @@
*
* Authors: Ben Skeggs
*/
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
#include <nvif/class.h>
-#include "nv50.h"
-
/*******************************************************************************
* Base display object
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
gm107_disp_sclass[] = {
- { GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
- { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
- { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
- { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
- { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
+ { GM107_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
+ { GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
+ { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
+ { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
+ { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
{}
};
-static struct nouveau_oclass
+static struct nvkm_oclass
gm107_disp_main_oclass[] = {
- { GM107_DISP, &nvd0_disp_main_ofuncs },
+ { GM107_DISP, &gf110_disp_main_ofuncs },
{}
};
@@ -54,28 +50,28 @@ gm107_disp_main_oclass[] = {
******************************************************************************/
static int
-gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
int heads = nv_rd32(parent, 0x022448);
int ret;
- ret = nouveau_disp_create(parent, engine, oclass, heads,
- "PDISP", "display", &priv);
+ ret = nvkm_disp_create(parent, engine, oclass, heads,
+ "PDISP", "display", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+ ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
if (ret)
return ret;
nv_engine(priv)->sclass = gm107_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
- nv_subdev(priv)->intr = nvd0_disp_intr;
- INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
+ nv_subdev(priv)->intr = gf110_disp_intr;
+ INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
priv->sclass = gm107_disp_sclass;
priv->head.nr = heads;
priv->dac.nr = 3;
@@ -83,25 +79,25 @@ gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
- priv->sor.hda_eld = nvd0_hda_eld;
- priv->sor.hdmi = nve0_hdmi_ctrl;
+ priv->sor.hda_eld = gf110_hda_eld;
+ priv->sor.hdmi = gk104_hdmi_ctrl;
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
gm107_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x07),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm107_disp_ctor,
- .dtor = _nouveau_disp_dtor,
- .init = _nouveau_disp_init,
- .fini = _nouveau_disp_fini,
+ .dtor = _nvkm_disp_dtor,
+ .init = _nvkm_disp_init,
+ .fini = _nvkm_disp_fini,
},
- .base.vblank = &nvd0_disp_vblank_func,
- .base.outp = nvd0_disp_outp_sclass,
- .mthd.core = &nve0_disp_core_mthd_chan,
- .mthd.base = &nvd0_disp_base_mthd_chan,
- .mthd.ovly = &nve0_disp_ovly_mthd_chan,
+ .base.vblank = &gf110_disp_vblank_func,
+ .base.outp = gf110_disp_outp_sclass,
+ .mthd.core = &gk104_disp_core_mthd_chan,
+ .mthd.base = &gf110_disp_base_mthd_chan,
+ .mthd.ovly = &gk104_disp_ovly_mthd_chan,
.mthd.prev = -0x020000,
- .head.scanoutpos = nvd0_disp_main_scanoutpos,
+ .head.scanoutpos = gf110_disp_main_scanoutpos,
}.base.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
index 40b44f990990..67004f8302b3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
@@ -21,31 +21,28 @@
*
* Authors: Ben Skeggs
*/
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
+#include "outpdp.h"
#include <nvif/class.h>
-#include "nv50.h"
-
/*******************************************************************************
* Base display object
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
gm204_disp_sclass[] = {
- { GM204_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
- { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
- { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
- { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
- { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
+ { GM204_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
+ { GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
+ { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
+ { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
+ { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
{}
};
-static struct nouveau_oclass
+static struct nvkm_oclass
gm204_disp_main_oclass[] = {
- { GM204_DISP, &nvd0_disp_main_ofuncs },
+ { GM204_DISP, &gf110_disp_main_ofuncs },
{}
};
@@ -54,28 +51,28 @@ gm204_disp_main_oclass[] = {
******************************************************************************/
static int
-gm204_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
int heads = nv_rd32(parent, 0x022448);
int ret;
- ret = nouveau_disp_create(parent, engine, oclass, heads,
- "PDISP", "display", &priv);
+ ret = nvkm_disp_create(parent, engine, oclass, heads,
+ "PDISP", "display", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+ ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
if (ret)
return ret;
nv_engine(priv)->sclass = gm204_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
- nv_subdev(priv)->intr = nvd0_disp_intr;
- INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
+ nv_subdev(priv)->intr = gf110_disp_intr;
+ INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
priv->sclass = gm204_disp_sclass;
priv->head.nr = heads;
priv->dac.nr = 3;
@@ -83,32 +80,32 @@ gm204_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
- priv->sor.hda_eld = nvd0_hda_eld;
- priv->sor.hdmi = nvd0_hdmi_ctrl;
+ priv->sor.hda_eld = gf110_hda_eld;
+ priv->sor.hdmi = gf110_hdmi_ctrl;
priv->sor.magic = gm204_sor_magic;
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
gm204_disp_outp_sclass[] = {
&gm204_sor_dp_impl.base.base,
NULL
};
-struct nouveau_oclass *
+struct nvkm_oclass *
gm204_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x07),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm204_disp_ctor,
- .dtor = _nouveau_disp_dtor,
- .init = _nouveau_disp_init,
- .fini = _nouveau_disp_fini,
+ .dtor = _nvkm_disp_dtor,
+ .init = _nvkm_disp_init,
+ .fini = _nvkm_disp_fini,
},
- .base.vblank = &nvd0_disp_vblank_func,
+ .base.vblank = &gf110_disp_vblank_func,
.base.outp = gm204_disp_outp_sclass,
- .mthd.core = &nve0_disp_core_mthd_chan,
- .mthd.base = &nvd0_disp_base_mthd_chan,
- .mthd.ovly = &nve0_disp_ovly_mthd_chan,
+ .mthd.core = &gk104_disp_core_mthd_chan,
+ .mthd.base = &gf110_disp_base_mthd_chan,
+ .mthd.ovly = &gk104_disp_ovly_mthd_chan,
.mthd.prev = -0x020000,
- .head.scanoutpos = nvd0_disp_main_scanoutpos,
+ .head.scanoutpos = gf110_disp_main_scanoutpos,
}.base.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c
similarity index 78%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c
index 317fd1a22076..a45307213f4b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c
@@ -21,20 +21,16 @@
*
* Authors: Ben Skeggs
*/
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
#include <nvif/class.h>
-#include "nv50.h"
-
/*******************************************************************************
* EVO overlay channel objects
******************************************************************************/
static const struct nv50_disp_mthd_list
-nva0_disp_ovly_mthd_base = {
+gt200_disp_ovly_mthd_base = {
.mthd = 0x0000,
.addr = 0x000000,
.data = {
@@ -65,11 +61,11 @@ nva0_disp_ovly_mthd_base = {
};
static const struct nv50_disp_mthd_chan
-nva0_disp_ovly_mthd_chan = {
+gt200_disp_ovly_mthd_chan = {
.name = "Overlay",
.addr = 0x000540,
.data = {
- { "Global", 1, &nva0_disp_ovly_mthd_base },
+ { "Global", 1, >200_disp_ovly_mthd_base },
{}
}
};
@@ -78,8 +74,8 @@ nva0_disp_ovly_mthd_chan = {
* Base display object
******************************************************************************/
-static struct nouveau_oclass
-nva0_disp_sclass[] = {
+static struct nvkm_oclass
+gt200_disp_sclass[] = {
{ GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
@@ -88,8 +84,8 @@ nva0_disp_sclass[] = {
{}
};
-static struct nouveau_oclass
-nva0_disp_main_oclass[] = {
+static struct nvkm_oclass
+gt200_disp_main_oclass[] = {
{ GT200_DISP, &nv50_disp_main_ofuncs },
{}
};
@@ -99,15 +95,15 @@ nva0_disp_main_oclass[] = {
******************************************************************************/
static int
-nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gt200_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
int ret;
- ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
- "display", &priv);
+ ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
+ "display", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -116,11 +112,11 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret)
return ret;
- nv_engine(priv)->sclass = nva0_disp_main_oclass;
+ nv_engine(priv)->sclass = gt200_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nv50_disp_intr;
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
- priv->sclass = nva0_disp_sclass;
+ priv->sclass = gt200_disp_sclass;
priv->head.nr = 2;
priv->dac.nr = 3;
priv->sor.nr = 2;
@@ -128,25 +124,25 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
- priv->sor.hdmi = nv84_hdmi_ctrl;
+ priv->sor.hdmi = g84_hdmi_ctrl;
priv->pior.power = nv50_pior_power;
return 0;
}
-struct nouveau_oclass *
-nva0_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+gt200_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x83),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nva0_disp_ctor,
- .dtor = _nouveau_disp_dtor,
- .init = _nouveau_disp_init,
- .fini = _nouveau_disp_fini,
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gt200_disp_ctor,
+ .dtor = _nvkm_disp_dtor,
+ .init = _nvkm_disp_init,
+ .fini = _nvkm_disp_fini,
},
.base.vblank = &nv50_disp_vblank_func,
.base.outp = nv50_disp_outp_sclass,
- .mthd.core = &nv84_disp_core_mthd_chan,
- .mthd.base = &nv84_disp_base_mthd_chan,
- .mthd.ovly = &nva0_disp_ovly_mthd_chan,
+ .mthd.core = &g84_disp_core_mthd_chan,
+ .mthd.base = &g84_disp_base_mthd_chan,
+ .mthd.ovly = >200_disp_ovly_mthd_chan,
.mthd.prev = 0x000004,
.head.scanoutpos = nv50_disp_main_scanoutpos,
}.base.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c
similarity index 73%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c
index af9441338239..55f0d3ac591e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c
@@ -21,20 +21,16 @@
*
* Authors: Ben Skeggs
*/
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
#include <nvif/class.h>
-#include "nv50.h"
-
/*******************************************************************************
* Base display object
******************************************************************************/
-static struct nouveau_oclass
-nva3_disp_sclass[] = {
+static struct nvkm_oclass
+gt215_disp_sclass[] = {
{ GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
{ GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
{ GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
@@ -43,8 +39,8 @@ nva3_disp_sclass[] = {
{}
};
-static struct nouveau_oclass
-nva3_disp_main_oclass[] = {
+static struct nvkm_oclass
+gt215_disp_main_oclass[] = {
{ GT214_DISP, &nv50_disp_main_ofuncs },
{}
};
@@ -54,15 +50,15 @@ nva3_disp_main_oclass[] = {
******************************************************************************/
static int
-nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
int ret;
- ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
- "display", &priv);
+ ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
+ "display", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -71,11 +67,11 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret)
return ret;
- nv_engine(priv)->sclass = nva3_disp_main_oclass;
+ nv_engine(priv)->sclass = gt215_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nv50_disp_intr;
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
- priv->sclass = nva3_disp_sclass;
+ priv->sclass = gt215_disp_sclass;
priv->head.nr = 2;
priv->dac.nr = 3;
priv->sor.nr = 4;
@@ -83,26 +79,26 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
- priv->sor.hda_eld = nva3_hda_eld;
- priv->sor.hdmi = nva3_hdmi_ctrl;
+ priv->sor.hda_eld = gt215_hda_eld;
+ priv->sor.hdmi = gt215_hdmi_ctrl;
priv->pior.power = nv50_pior_power;
return 0;
}
-struct nouveau_oclass *
-nva3_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+gt215_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x85),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nva3_disp_ctor,
- .dtor = _nouveau_disp_dtor,
- .init = _nouveau_disp_init,
- .fini = _nouveau_disp_fini,
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gt215_disp_ctor,
+ .dtor = _nvkm_disp_dtor,
+ .init = _nvkm_disp_init,
+ .fini = _nvkm_disp_fini,
},
.base.vblank = &nv50_disp_vblank_func,
- .base.outp = nv94_disp_outp_sclass,
- .mthd.core = &nv94_disp_core_mthd_chan,
- .mthd.base = &nv84_disp_base_mthd_chan,
- .mthd.ovly = &nv84_disp_ovly_mthd_chan,
+ .base.outp = g94_disp_outp_sclass,
+ .mthd.core = &g94_disp_core_mthd_chan,
+ .mthd.base = &g84_disp_base_mthd_chan,
+ .mthd.ovly = &g84_disp_ovly_mthd_chan,
.mthd.prev = 0x000004,
.head.scanoutpos = nv50_disp_main_scanoutpos,
}.base.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdanvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c
similarity index 95%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/hdanvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c
index 1d4e8432d857..b9813d246ba5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdanvd0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c
@@ -21,17 +21,19 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
+#include "outp.h"
#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
+#include <subdev/bios.h>
+#include <subdev/bios/dcb.h>
#include <subdev/timer.h>
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
int
-nvd0_hda_eld(NV50_DISP_MTHD_V1)
+gf110_hda_eld(NV50_DISP_MTHD_V1)
{
union {
struct nv50_disp_sor_hda_eld_v0 v0;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdanva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c
similarity index 97%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/hdanva3.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c
index fe9ef5894dd4..891d1e7bf7d2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdanva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c
@@ -21,17 +21,17 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
+#include "outp.h"
#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
#include <subdev/timer.h>
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
int
-nva3_hda_eld(NV50_DISP_MTHD_V1)
+gt215_hda_eld(NV50_DISP_MTHD_V1)
{
union {
struct nv50_disp_sor_hda_eld_v0 v0;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c
similarity index 98%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c
index fa276dede9cd..621cb0b7ff19 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c
@@ -21,15 +21,15 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
#include "nv50.h"
+#include <core/client.h>
+
+#include <nvif/class.h>
+#include <nvif/unpack.h>
+
int
-nv84_hdmi_ctrl(NV50_DISP_MTHD_V1)
+g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
{
const u32 hoff = (head * 0x800);
union {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c
similarity index 98%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c
index bac4fc4570f0..c28449061bbd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminvd0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c
@@ -21,15 +21,15 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
#include "nv50.h"
+#include <core/client.h>
+
+#include <nvif/class.h>
+#include <nvif/unpack.h>
+
int
-nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1)
+gf110_hdmi_ctrl(NV50_DISP_MTHD_V1)
{
const u32 hoff = (head * 0x800);
union {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c
similarity index 98%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c
index 528d14ec2f7f..ca34ff81ad7f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c
@@ -21,15 +21,15 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
#include "nv50.h"
+#include <core/client.h>
+
+#include <nvif/class.h>
+#include <nvif/unpack.h>
+
int
-nve0_hdmi_ctrl(NV50_DISP_MTHD_V1)
+gk104_hdmi_ctrl(NV50_DISP_MTHD_V1)
{
const u32 hoff = (head * 0x800);
const u32 hdmi = (head * 0x400);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c
similarity index 98%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminva3.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c
index 57eeed1d1942..b641c167dcfa 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c
@@ -21,15 +21,16 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
+#include "outp.h"
#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
int
-nva3_hdmi_ctrl(NV50_DISP_MTHD_V1)
+gt215_hdmi_ctrl(NV50_DISP_MTHD_V1)
{
const u32 soff = outp->or * 0x800;
union {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c
index 366f315fc9a5..ff09b2659c17 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c
@@ -21,20 +21,20 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
#include <core/client.h>
-#include <core/event.h>
-#include <nvif/unpack.h>
+#include <core/device.h>
+
#include <nvif/class.h>
+#include <nvif/unpack.h>
struct nv04_disp_priv {
- struct nouveau_disp base;
+ struct nvkm_disp base;
};
static int
-nv04_disp_scanoutpos(struct nouveau_object *object, struct nv04_disp_priv *priv,
+nv04_disp_scanoutpos(struct nvkm_object *object, struct nv04_disp_priv *priv,
void *data, u32 size, int head)
{
const u32 hoff = head * 0x2000;
@@ -75,7 +75,7 @@ nv04_disp_scanoutpos(struct nouveau_object *object, struct nv04_disp_priv *priv,
}
static int
-nv04_disp_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size)
+nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
union {
struct nv04_disp_mthd_v0 v0;
@@ -105,17 +105,17 @@ nv04_disp_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size)
return -EINVAL;
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
nv04_disp_ofuncs = {
- .ctor = _nouveau_object_ctor,
- .dtor = nouveau_object_destroy,
- .init = nouveau_object_init,
- .fini = nouveau_object_fini,
+ .ctor = _nvkm_object_ctor,
+ .dtor = nvkm_object_destroy,
+ .init = nvkm_object_init,
+ .fini = nvkm_object_fini,
.mthd = nv04_disp_mthd,
- .ntfy = nouveau_disp_ntfy,
+ .ntfy = nvkm_disp_ntfy,
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv04_disp_sclass[] = {
{ NV04_DISP, &nv04_disp_ofuncs },
{},
@@ -128,26 +128,26 @@ nv04_disp_sclass[] = {
static void
nv04_disp_vblank_init(struct nvkm_event *event, int type, int head)
{
- struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
+ struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000001);
}
static void
nv04_disp_vblank_fini(struct nvkm_event *event, int type, int head)
{
- struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
+ struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000000);
}
static const struct nvkm_event_func
nv04_disp_vblank_func = {
- .ctor = nouveau_disp_vblank_ctor,
+ .ctor = nvkm_disp_vblank_ctor,
.init = nv04_disp_vblank_init,
.fini = nv04_disp_vblank_fini,
};
static void
-nv04_disp_intr(struct nouveau_subdev *subdev)
+nv04_disp_intr(struct nvkm_subdev *subdev)
{
struct nv04_disp_priv *priv = (void *)subdev;
u32 crtc0 = nv_rd32(priv, 0x600100);
@@ -155,12 +155,12 @@ nv04_disp_intr(struct nouveau_subdev *subdev)
u32 pvideo;
if (crtc0 & 0x00000001) {
- nouveau_disp_vblank(&priv->base, 0);
+ nvkm_disp_vblank(&priv->base, 0);
nv_wr32(priv, 0x600100, 0x00000001);
}
if (crtc1 & 0x00000001) {
- nouveau_disp_vblank(&priv->base, 1);
+ nvkm_disp_vblank(&priv->base, 1);
nv_wr32(priv, 0x602100, 0x00000001);
}
@@ -174,15 +174,15 @@ nv04_disp_intr(struct nouveau_subdev *subdev)
}
static int
-nv04_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_disp_priv *priv;
int ret;
- ret = nouveau_disp_create(parent, engine, oclass, 2, "DISPLAY",
- "display", &priv);
+ ret = nvkm_disp_create(parent, engine, oclass, 2, "DISPLAY",
+ "display", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -192,14 +192,14 @@ nv04_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
-nv04_disp_oclass = &(struct nouveau_disp_impl) {
+struct nvkm_oclass *
+nv04_disp_oclass = &(struct nvkm_disp_impl) {
.base.handle = NV_ENGINE(DISP, 0x04),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_disp_ctor,
- .dtor = _nouveau_disp_dtor,
- .init = _nouveau_disp_init,
- .fini = _nouveau_disp_fini,
+ .dtor = _nvkm_disp_dtor,
+ .init = _nvkm_disp_init,
+ .fini = _nvkm_disp_fini,
},
.vblank = &nv04_disp_vblank_func,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
index 44a8290aaea5..84ade810e27c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
@@ -21,35 +21,38 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
+#include "outp.h"
+#include "outpdp.h"
-#include <core/object.h>
#include <core/client.h>
-#include <core/parent.h>
-#include <core/handle.h>
+#include <core/device.h>
+#include <core/engctx.h>
#include <core/enum.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <nvif/event.h>
-
+#include <core/handle.h>
+#include <core/ramht.h>
+#include <engine/dmaobj.h>
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/disp.h>
#include <subdev/bios/init.h>
#include <subdev/bios/pll.h>
#include <subdev/devinit.h>
-#include <subdev/timer.h>
#include <subdev/fb.h>
+#include <subdev/timer.h>
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/event.h>
+#include <nvif/unpack.h>
/*******************************************************************************
* EVO channel base class
******************************************************************************/
static int
-nv50_disp_chan_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int head,
+nv50_disp_chan_create_(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int head,
int length, void **pobject)
{
const struct nv50_disp_chan_impl *impl = (void *)oclass->ofuncs;
@@ -62,9 +65,9 @@ nv50_disp_chan_create_(struct nouveau_object *parent,
return -EBUSY;
base->chan |= (1 << chid);
- ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL,
- (1ULL << NVDEV_ENGINE_DMAOBJ),
- length, pobject);
+ ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL,
+ (1ULL << NVDEV_ENGINE_DMAOBJ),
+ length, pobject);
chan = *pobject;
if (ret)
return ret;
@@ -80,7 +83,7 @@ nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
{
struct nv50_disp_base *base = (void *)nv_object(chan)->parent;
base->chan &= ~(1 << chan->chid);
- nouveau_namedb_destroy(&chan->base);
+ nvkm_namedb_destroy(&chan->base);
}
static void
@@ -109,7 +112,7 @@ nv50_disp_chan_uevent_send(struct nv50_disp_priv *priv, int chid)
}
int
-nv50_disp_chan_uevent_ctor(struct nouveau_object *object, void *data, u32 size,
+nv50_disp_chan_uevent_ctor(struct nvkm_object *object, void *data, u32 size,
struct nvkm_notify *notify)
{
struct nv50_disp_dmac *dmac = (void *)object;
@@ -136,7 +139,7 @@ nv50_disp_chan_uevent = {
};
int
-nv50_disp_chan_ntfy(struct nouveau_object *object, u32 type,
+nv50_disp_chan_ntfy(struct nvkm_object *object, u32 type,
struct nvkm_event **pevent)
{
struct nv50_disp_priv *priv = (void *)object->engine;
@@ -151,7 +154,7 @@ nv50_disp_chan_ntfy(struct nouveau_object *object, u32 type,
}
int
-nv50_disp_chan_map(struct nouveau_object *object, u64 *addr, u32 *size)
+nv50_disp_chan_map(struct nvkm_object *object, u64 *addr, u32 *size)
{
struct nv50_disp_chan *chan = (void *)object;
*addr = nv_device_resource_start(nv_device(object), 0) +
@@ -161,7 +164,7 @@ nv50_disp_chan_map(struct nouveau_object *object, u64 *addr, u32 *size)
}
u32
-nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr)
+nv50_disp_chan_rd32(struct nvkm_object *object, u64 addr)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_chan *chan = (void *)object;
@@ -169,7 +172,7 @@ nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr)
}
void
-nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data)
+nv50_disp_chan_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_chan *chan = (void *)object;
@@ -181,28 +184,28 @@ nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data)
******************************************************************************/
static int
-nv50_disp_dmac_object_attach(struct nouveau_object *parent,
- struct nouveau_object *object, u32 name)
+nv50_disp_dmac_object_attach(struct nvkm_object *parent,
+ struct nvkm_object *object, u32 name)
{
struct nv50_disp_base *base = (void *)parent->parent;
struct nv50_disp_chan *chan = (void *)parent;
u32 addr = nv_gpuobj(object)->node->offset;
u32 chid = chan->chid;
u32 data = (chid << 28) | (addr << 10) | chid;
- return nouveau_ramht_insert(base->ramht, chid, name, data);
+ return nvkm_ramht_insert(base->ramht, chid, name, data);
}
static void
-nv50_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
+nv50_disp_dmac_object_detach(struct nvkm_object *parent, int cookie)
{
struct nv50_disp_base *base = (void *)parent->parent;
- nouveau_ramht_remove(base->ramht, cookie);
+ nvkm_ramht_remove(base->ramht, cookie);
}
static int
-nv50_disp_dmac_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, u32 pushbuf, int head,
+nv50_disp_dmac_create_(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, u32 pushbuf, int head,
int length, void **pobject)
{
struct nv50_disp_dmac *dmac;
@@ -214,7 +217,7 @@ nv50_disp_dmac_create_(struct nouveau_object *parent,
if (ret)
return ret;
- dmac->pushdma = (void *)nouveau_handle_ref(parent, pushbuf);
+ dmac->pushdma = (void *)nvkm_handle_ref(parent, pushbuf);
if (!dmac->pushdma)
return -ENOENT;
@@ -243,15 +246,15 @@ nv50_disp_dmac_create_(struct nouveau_object *parent,
}
void
-nv50_disp_dmac_dtor(struct nouveau_object *object)
+nv50_disp_dmac_dtor(struct nvkm_object *object)
{
struct nv50_disp_dmac *dmac = (void *)object;
- nouveau_object_ref(NULL, (struct nouveau_object **)&dmac->pushdma);
+ nvkm_object_ref(NULL, (struct nvkm_object **)&dmac->pushdma);
nv50_disp_chan_destroy(&dmac->base);
}
static int
-nv50_disp_dmac_init(struct nouveau_object *object)
+nv50_disp_dmac_init(struct nvkm_object *object)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *dmac = (void *)object;
@@ -284,7 +287,7 @@ nv50_disp_dmac_init(struct nouveau_object *object)
}
static int
-nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend)
+nv50_disp_dmac_fini(struct nvkm_object *object, bool suspend)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *dmac = (void *)object;
@@ -314,7 +317,7 @@ static void
nv50_disp_mthd_list(struct nv50_disp_priv *priv, int debug, u32 base, int c,
const struct nv50_disp_mthd_list *list, int inst)
{
- struct nouveau_object *disp = nv_object(priv);
+ struct nvkm_object *disp = nv_object(priv);
int i;
for (i = 0; list->data[i].mthd; i++) {
@@ -341,7 +344,7 @@ void
nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head,
const struct nv50_disp_mthd_chan *chan)
{
- struct nouveau_object *disp = nv_object(priv);
+ struct nvkm_object *disp = nv_object(priv);
const struct nv50_disp_impl *impl = (void *)disp->oclass;
const struct nv50_disp_mthd_list *list;
int i, j;
@@ -482,10 +485,10 @@ nv50_disp_core_mthd_chan = {
};
int
-nv50_disp_core_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_disp_core_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv50_disp_core_channel_dma_v0 v0;
@@ -511,7 +514,7 @@ nv50_disp_core_ctor(struct nouveau_object *parent,
}
static int
-nv50_disp_core_init(struct nouveau_object *object)
+nv50_disp_core_init(struct nvkm_object *object)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *mast = (void *)object;
@@ -548,7 +551,7 @@ nv50_disp_core_init(struct nouveau_object *object)
}
static int
-nv50_disp_core_fini(struct nouveau_object *object, bool suspend)
+nv50_disp_core_fini(struct nvkm_object *object, bool suspend)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *mast = (void *)object;
@@ -638,10 +641,10 @@ nv50_disp_base_mthd_chan = {
};
int
-nv50_disp_base_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_disp_base_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv50_disp_base_channel_dma_v0 v0;
@@ -728,10 +731,10 @@ nv50_disp_ovly_mthd_chan = {
};
int
-nv50_disp_ovly_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_disp_ovly_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv50_disp_overlay_channel_dma_v0 v0;
@@ -780,9 +783,9 @@ nv50_disp_ovly_ofuncs = {
******************************************************************************/
static int
-nv50_disp_pioc_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int head,
+nv50_disp_pioc_create_(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int head,
int length, void **pobject)
{
return nv50_disp_chan_create_(parent, engine, oclass, head,
@@ -790,14 +793,14 @@ nv50_disp_pioc_create_(struct nouveau_object *parent,
}
void
-nv50_disp_pioc_dtor(struct nouveau_object *object)
+nv50_disp_pioc_dtor(struct nvkm_object *object)
{
struct nv50_disp_pioc *pioc = (void *)object;
nv50_disp_chan_destroy(&pioc->base);
}
static int
-nv50_disp_pioc_init(struct nouveau_object *object)
+nv50_disp_pioc_init(struct nvkm_object *object)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_pioc *pioc = (void *)object;
@@ -826,7 +829,7 @@ nv50_disp_pioc_init(struct nouveau_object *object)
}
static int
-nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend)
+nv50_disp_pioc_fini(struct nvkm_object *object, bool suspend)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_pioc *pioc = (void *)object;
@@ -848,10 +851,10 @@ nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend)
******************************************************************************/
int
-nv50_disp_oimm_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_disp_oimm_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv50_disp_overlay_v0 v0;
@@ -896,10 +899,10 @@ nv50_disp_oimm_ofuncs = {
******************************************************************************/
int
-nv50_disp_curs_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_disp_curs_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv50_disp_cursor_v0 v0;
@@ -976,8 +979,7 @@ nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
}
int
-nv50_disp_main_mthd(struct nouveau_object *object, u32 mthd,
- void *data, u32 size)
+nv50_disp_main_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine);
union {
@@ -1100,42 +1102,42 @@ nv50_disp_main_mthd(struct nouveau_object *object, u32 mthd,
}
int
-nv50_disp_main_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_disp_main_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv = (void *)engine;
struct nv50_disp_base *base;
int ret;
- ret = nouveau_parent_create(parent, engine, oclass, 0,
- priv->sclass, 0, &base);
+ ret = nvkm_parent_create(parent, engine, oclass, 0,
+ priv->sclass, 0, &base);
*pobject = nv_object(base);
if (ret)
return ret;
- return nouveau_ramht_new(nv_object(base), nv_object(base), 0x1000, 0,
- &base->ramht);
+ return nvkm_ramht_new(nv_object(base), nv_object(base), 0x1000, 0,
+ &base->ramht);
}
void
-nv50_disp_main_dtor(struct nouveau_object *object)
+nv50_disp_main_dtor(struct nvkm_object *object)
{
struct nv50_disp_base *base = (void *)object;
- nouveau_ramht_ref(NULL, &base->ramht);
- nouveau_parent_destroy(&base->base);
+ nvkm_ramht_ref(NULL, &base->ramht);
+ nvkm_parent_destroy(&base->base);
}
static int
-nv50_disp_main_init(struct nouveau_object *object)
+nv50_disp_main_init(struct nvkm_object *object)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_base *base = (void *)object;
int ret, i;
u32 tmp;
- ret = nouveau_parent_init(&base->base);
+ ret = nvkm_parent_init(&base->base);
if (ret)
return ret;
@@ -1196,7 +1198,7 @@ nv50_disp_main_init(struct nouveau_object *object)
}
static int
-nv50_disp_main_fini(struct nouveau_object *object, bool suspend)
+nv50_disp_main_fini(struct nvkm_object *object, bool suspend)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_base *base = (void *)object;
@@ -1205,26 +1207,26 @@ nv50_disp_main_fini(struct nouveau_object *object, bool suspend)
nv_wr32(priv, 0x610024, 0x00000000);
nv_wr32(priv, 0x610020, 0x00000000);
- return nouveau_parent_fini(&base->base, suspend);
+ return nvkm_parent_fini(&base->base, suspend);
}
-struct nouveau_ofuncs
+struct nvkm_ofuncs
nv50_disp_main_ofuncs = {
.ctor = nv50_disp_main_ctor,
.dtor = nv50_disp_main_dtor,
.init = nv50_disp_main_init,
.fini = nv50_disp_main_fini,
.mthd = nv50_disp_main_mthd,
- .ntfy = nouveau_disp_ntfy,
+ .ntfy = nvkm_disp_ntfy,
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv50_disp_main_oclass[] = {
{ NV50_DISP, &nv50_disp_main_ofuncs },
{}
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv50_disp_sclass[] = {
{ NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
{ NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
@@ -1240,13 +1242,13 @@ nv50_disp_sclass[] = {
******************************************************************************/
static int
-nv50_disp_data_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_disp_data_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv = (void *)engine;
- struct nouveau_engctx *ectx;
+ struct nvkm_engctx *ectx;
int ret = -EBUSY;
/* no context needed for channel objects... */
@@ -1259,25 +1261,24 @@ nv50_disp_data_ctor(struct nouveau_object *parent,
/* allocate display hardware to client */
mutex_lock(&nv_subdev(priv)->mutex);
if (list_empty(&nv_engine(priv)->contexts)) {
- ret = nouveau_engctx_create(parent, engine, oclass, NULL,
- 0x10000, 0x10000,
- NVOBJ_FLAG_HEAP, &ectx);
+ ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000,
+ 0x10000, NVOBJ_FLAG_HEAP, &ectx);
*pobject = nv_object(ectx);
}
mutex_unlock(&nv_subdev(priv)->mutex);
return ret;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv50_disp_cclass = {
.handle = NV_ENGCTX(DISP, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_disp_data_ctor,
- .dtor = _nouveau_engctx_dtor,
- .init = _nouveau_engctx_init,
- .fini = _nouveau_engctx_fini,
- .rd32 = _nouveau_engctx_rd32,
- .wr32 = _nouveau_engctx_wr32,
+ .dtor = _nvkm_engctx_dtor,
+ .init = _nvkm_engctx_init,
+ .fini = _nvkm_engctx_fini,
+ .rd32 = _nvkm_engctx_rd32,
+ .wr32 = _nvkm_engctx_wr32,
},
};
@@ -1288,25 +1289,25 @@ nv50_disp_cclass = {
static void
nv50_disp_vblank_fini(struct nvkm_event *event, int type, int head)
{
- struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
+ struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
nv_mask(disp, 0x61002c, (4 << head), 0);
}
static void
nv50_disp_vblank_init(struct nvkm_event *event, int type, int head)
{
- struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
+ struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
nv_mask(disp, 0x61002c, (4 << head), (4 << head));
}
const struct nvkm_event_func
nv50_disp_vblank_func = {
- .ctor = nouveau_disp_vblank_ctor,
+ .ctor = nvkm_disp_vblank_ctor,
.init = nv50_disp_vblank_init,
.fini = nv50_disp_vblank_fini,
};
-static const struct nouveau_enum
+static const struct nvkm_enum
nv50_disp_intr_error_type[] = {
{ 3, "ILLEGAL_MTHD" },
{ 4, "INVALID_VALUE" },
@@ -1315,7 +1316,7 @@ nv50_disp_intr_error_type[] = {
{}
};
-static const struct nouveau_enum
+static const struct nvkm_enum
nv50_disp_intr_error_code[] = {
{ 0x00, "" },
{}
@@ -1330,14 +1331,14 @@ nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid)
u32 code = (addr & 0x00ff0000) >> 16;
u32 type = (addr & 0x00007000) >> 12;
u32 mthd = (addr & 0x00000ffc);
- const struct nouveau_enum *ec, *et;
+ const struct nvkm_enum *ec, *et;
char ecunk[6], etunk[6];
- et = nouveau_enum_find(nv50_disp_intr_error_type, type);
+ et = nvkm_enum_find(nv50_disp_intr_error_type, type);
if (!et)
snprintf(etunk, sizeof(etunk), "UNK%02X", type);
- ec = nouveau_enum_find(nv50_disp_intr_error_code, code);
+ ec = nvkm_enum_find(nv50_disp_intr_error_code, code);
if (!ec)
snprintf(ecunk, sizeof(ecunk), "UNK%02X", code);
@@ -1385,7 +1386,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl,
u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_outp *info)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvkm_output *outp;
u16 mask, type;
@@ -1440,7 +1441,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl,
static struct nvkm_output *
exec_script(struct nv50_disp_priv *priv, int head, int id)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvkm_output *outp;
struct nvbios_outp info;
u8 ver, hdr, cnt, len;
@@ -1497,7 +1498,7 @@ exec_script(struct nv50_disp_priv *priv, int head, int id)
static struct nvkm_output *
exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvkm_output *outp;
struct nvbios_outp info1;
struct nvbios_ocfg info2;
@@ -1610,7 +1611,7 @@ nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head)
struct nvkm_output_dp *outpdp = (void *)outp;
struct nvbios_init init = {
.subdev = nv_subdev(priv),
- .bios = nouveau_bios(priv),
+ .bios = nvkm_bios(priv),
.outp = &outp->info,
.crtc = head,
.offset = outpdp->info.script[4],
@@ -1625,7 +1626,7 @@ nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head)
static void
nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head)
{
- struct nouveau_devinit *devinit = nouveau_devinit(priv);
+ struct nvkm_devinit *devinit = nvkm_devinit(priv);
u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
if (pclk)
devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
@@ -1841,9 +1842,10 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
* programmed for DisplayPort.
*/
static void
-nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
+nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv,
+ struct dcb_output *outp)
{
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
const int link = !(outp->sorconf.link & 1);
const int or = ffs(outp->or) - 1;
const u32 loff = (or * 0x800) + (link * 0x80);
@@ -1920,7 +1922,7 @@ nv50_disp_intr_supervisor(struct work_struct *work)
}
void
-nv50_disp_intr(struct nouveau_subdev *subdev)
+nv50_disp_intr(struct nvkm_subdev *subdev)
{
struct nv50_disp_priv *priv = (void *)subdev;
u32 intr0 = nv_rd32(priv, 0x610020);
@@ -1939,13 +1941,13 @@ nv50_disp_intr(struct nouveau_subdev *subdev)
}
if (intr1 & 0x00000004) {
- nouveau_disp_vblank(&priv->base, 0);
+ nvkm_disp_vblank(&priv->base, 0);
nv_wr32(priv, 0x610024, 0x00000004);
intr1 &= ~0x00000004;
}
if (intr1 & 0x00000008) {
- nouveau_disp_vblank(&priv->base, 1);
+ nvkm_disp_vblank(&priv->base, 1);
nv_wr32(priv, 0x610024, 0x00000008);
intr1 &= ~0x00000008;
}
@@ -1959,15 +1961,15 @@ nv50_disp_intr(struct nouveau_subdev *subdev)
}
static int
-nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_disp_priv *priv;
int ret;
- ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
- "display", &priv);
+ ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
+ "display", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -1992,20 +1994,20 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv50_disp_outp_sclass[] = {
&nv50_pior_dp_impl.base.base,
NULL
};
-struct nouveau_oclass *
+struct nvkm_oclass *
nv50_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x50),
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_disp_ctor,
- .dtor = _nouveau_disp_dtor,
- .init = _nouveau_disp_init,
- .fini = _nouveau_disp_fini,
+ .dtor = _nvkm_disp_dtor,
+ .init = _nvkm_disp_init,
+ .fini = _nvkm_disp_fini,
},
.base.vblank = &nv50_disp_vblank_func,
.base.outp = nv50_disp_outp_sclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
index 7f08078ee925..b4ed620070fa 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
@@ -1,27 +1,17 @@
#ifndef __NV50_DISP_H__
#define __NV50_DISP_H__
-
-#include <core/parent.h>
-#include <core/namedb.h>
-#include <core/engctx.h>
-#include <core/ramht.h>
-#include <core/event.h>
-
-#include <engine/dmaobj.h>
-
-#include "dport.h"
#include "priv.h"
-#include "outp.h"
-#include "outpdp.h"
+struct nvkm_output;
+struct nvkm_output_dp;
-#define NV50_DISP_MTHD_ struct nouveau_object *object, \
+#define NV50_DISP_MTHD_ struct nvkm_object *object, \
struct nv50_disp_priv *priv, void *data, u32 size
#define NV50_DISP_MTHD_V0 NV50_DISP_MTHD_, int head
#define NV50_DISP_MTHD_V1 NV50_DISP_MTHD_, int head, struct nvkm_output *outp
struct nv50_disp_priv {
- struct nouveau_disp base;
- struct nouveau_oclass *sclass;
+ struct nvkm_disp base;
+ struct nvkm_oclass *sclass;
struct work_struct supervisor;
u32 super;
@@ -52,7 +42,7 @@ struct nv50_disp_priv {
};
struct nv50_disp_impl {
- struct nouveau_disp_impl base;
+ struct nvkm_disp_impl base;
struct {
const struct nv50_disp_mthd_chan *core;
const struct nv50_disp_mthd_chan *base;
@@ -65,90 +55,75 @@ struct nv50_disp_impl {
};
int nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
-int nv50_disp_main_mthd(struct nouveau_object *, u32, void *, u32);
+int nv50_disp_main_mthd(struct nvkm_object *, u32, void *, u32);
-int nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
+int gf110_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
int nv50_dac_power(NV50_DISP_MTHD_V1);
int nv50_dac_sense(NV50_DISP_MTHD_V1);
-int nva3_hda_eld(NV50_DISP_MTHD_V1);
-int nvd0_hda_eld(NV50_DISP_MTHD_V1);
+int gt215_hda_eld(NV50_DISP_MTHD_V1);
+int gf110_hda_eld(NV50_DISP_MTHD_V1);
-int nv84_hdmi_ctrl(NV50_DISP_MTHD_V1);
-int nva3_hdmi_ctrl(NV50_DISP_MTHD_V1);
-int nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1);
-int nve0_hdmi_ctrl(NV50_DISP_MTHD_V1);
+int g84_hdmi_ctrl(NV50_DISP_MTHD_V1);
+int gt215_hdmi_ctrl(NV50_DISP_MTHD_V1);
+int gf110_hdmi_ctrl(NV50_DISP_MTHD_V1);
+int gk104_hdmi_ctrl(NV50_DISP_MTHD_V1);
int nv50_sor_power(NV50_DISP_MTHD_V1);
-
-int nv94_sor_dp_train_init(struct nv50_disp_priv *, int, int, int, u16, u16,
- u32, struct dcb_output *);
-int nv94_sor_dp_train_fini(struct nv50_disp_priv *, int, int, int, u16, u16,
- u32, struct dcb_output *);
-int nv94_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32,
- struct dcb_output *);
-int nv94_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
- struct dcb_output *);
-int nv94_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
- struct dcb_output *);
-
-int nvd0_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32,
- struct dcb_output *);
-int nvd0_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
- struct dcb_output *);
-int nvd0_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
- struct dcb_output *);
-
int nv50_pior_power(NV50_DISP_MTHD_V1);
+#include <core/parent.h>
+
struct nv50_disp_base {
- struct nouveau_parent base;
- struct nouveau_ramht *ramht;
+ struct nvkm_parent base;
+ struct nvkm_ramht *ramht;
u32 chan;
};
struct nv50_disp_chan_impl {
- struct nouveau_ofuncs base;
+ struct nvkm_ofuncs base;
int chid;
- int (*attach)(struct nouveau_object *, struct nouveau_object *, u32);
- void (*detach)(struct nouveau_object *, int);
+ int (*attach)(struct nvkm_object *, struct nvkm_object *, u32);
+ void (*detach)(struct nvkm_object *, int);
};
+#include <core/namedb.h>
+
struct nv50_disp_chan {
- struct nouveau_namedb base;
+ struct nvkm_namedb base;
int chid;
};
-int nv50_disp_chan_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
-int nv50_disp_chan_map(struct nouveau_object *, u64 *, u32 *);
-u32 nv50_disp_chan_rd32(struct nouveau_object *, u64);
-void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32);
+int nv50_disp_chan_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
+int nv50_disp_chan_map(struct nvkm_object *, u64 *, u32 *);
+u32 nv50_disp_chan_rd32(struct nvkm_object *, u64);
+void nv50_disp_chan_wr32(struct nvkm_object *, u64, u32);
extern const struct nvkm_event_func nv50_disp_chan_uevent;
-int nv50_disp_chan_uevent_ctor(struct nouveau_object *, void *, u32,
+int nv50_disp_chan_uevent_ctor(struct nvkm_object *, void *, u32,
struct nvkm_notify *);
void nv50_disp_chan_uevent_send(struct nv50_disp_priv *, int);
-extern const struct nvkm_event_func nvd0_disp_chan_uevent;
+extern const struct nvkm_event_func gf110_disp_chan_uevent;
#define nv50_disp_chan_init(a) \
- nouveau_namedb_init(&(a)->base)
+ nvkm_namedb_init(&(a)->base)
#define nv50_disp_chan_fini(a,b) \
- nouveau_namedb_fini(&(a)->base, (b))
+ nvkm_namedb_fini(&(a)->base, (b))
struct nv50_disp_dmac {
struct nv50_disp_chan base;
- struct nouveau_dmaobj *pushdma;
+ struct nvkm_dmaobj *pushdma;
u32 push;
};
-void nv50_disp_dmac_dtor(struct nouveau_object *);
+void nv50_disp_dmac_dtor(struct nvkm_object *);
struct nv50_disp_pioc {
struct nv50_disp_chan base;
};
-void nv50_disp_pioc_dtor(struct nouveau_object *);
+void nv50_disp_pioc_dtor(struct nvkm_object *);
struct nv50_disp_mthd_list {
u32 mthd;
@@ -171,82 +146,81 @@ struct nv50_disp_mthd_chan {
};
extern struct nv50_disp_chan_impl nv50_disp_core_ofuncs;
-int nv50_disp_core_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
+int nv50_disp_core_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_base;
extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_sor;
extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_pior;
extern struct nv50_disp_chan_impl nv50_disp_base_ofuncs;
-int nv50_disp_base_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
+int nv50_disp_base_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
extern const struct nv50_disp_mthd_list nv50_disp_base_mthd_image;
extern struct nv50_disp_chan_impl nv50_disp_ovly_ofuncs;
-int nv50_disp_ovly_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
+int nv50_disp_ovly_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
extern const struct nv50_disp_mthd_list nv50_disp_ovly_mthd_base;
extern struct nv50_disp_chan_impl nv50_disp_oimm_ofuncs;
-int nv50_disp_oimm_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
+int nv50_disp_oimm_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
extern struct nv50_disp_chan_impl nv50_disp_curs_ofuncs;
-int nv50_disp_curs_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-extern struct nouveau_ofuncs nv50_disp_main_ofuncs;
-int nv50_disp_main_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nv50_disp_main_dtor(struct nouveau_object *);
-extern struct nouveau_omthds nv50_disp_main_omthds[];
-extern struct nouveau_oclass nv50_disp_cclass;
+int nv50_disp_curs_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+extern struct nvkm_ofuncs nv50_disp_main_ofuncs;
+int nv50_disp_main_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void nv50_disp_main_dtor(struct nvkm_object *);
+extern struct nvkm_omthds nv50_disp_main_omthds[];
+extern struct nvkm_oclass nv50_disp_cclass;
void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head,
const struct nv50_disp_mthd_chan *);
void nv50_disp_intr_supervisor(struct work_struct *);
-void nv50_disp_intr(struct nouveau_subdev *);
+void nv50_disp_intr(struct nvkm_subdev *);
extern const struct nvkm_event_func nv50_disp_vblank_func;
-extern const struct nv50_disp_mthd_chan nv84_disp_core_mthd_chan;
-extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_dac;
-extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_head;
-extern const struct nv50_disp_mthd_chan nv84_disp_base_mthd_chan;
-extern const struct nv50_disp_mthd_chan nv84_disp_ovly_mthd_chan;
+extern const struct nv50_disp_mthd_chan g84_disp_core_mthd_chan;
+extern const struct nv50_disp_mthd_list g84_disp_core_mthd_dac;
+extern const struct nv50_disp_mthd_list g84_disp_core_mthd_head;
+extern const struct nv50_disp_mthd_chan g84_disp_base_mthd_chan;
+extern const struct nv50_disp_mthd_chan g84_disp_ovly_mthd_chan;
-extern const struct nv50_disp_mthd_chan nv94_disp_core_mthd_chan;
+extern const struct nv50_disp_mthd_chan g94_disp_core_mthd_chan;
-extern struct nv50_disp_chan_impl nvd0_disp_core_ofuncs;
-extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_base;
-extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_dac;
-extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_sor;
-extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_pior;
-extern struct nv50_disp_chan_impl nvd0_disp_base_ofuncs;
-extern struct nv50_disp_chan_impl nvd0_disp_ovly_ofuncs;
-extern const struct nv50_disp_mthd_chan nvd0_disp_base_mthd_chan;
-extern struct nv50_disp_chan_impl nvd0_disp_oimm_ofuncs;
-extern struct nv50_disp_chan_impl nvd0_disp_curs_ofuncs;
-extern struct nouveau_ofuncs nvd0_disp_main_ofuncs;
-extern struct nouveau_oclass nvd0_disp_cclass;
-void nvd0_disp_intr_supervisor(struct work_struct *);
-void nvd0_disp_intr(struct nouveau_subdev *);
-extern const struct nvkm_event_func nvd0_disp_vblank_func;
+extern struct nv50_disp_chan_impl gf110_disp_core_ofuncs;
+extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_base;
+extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_dac;
+extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_sor;
+extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_pior;
+extern struct nv50_disp_chan_impl gf110_disp_base_ofuncs;
+extern struct nv50_disp_chan_impl gf110_disp_ovly_ofuncs;
+extern const struct nv50_disp_mthd_chan gf110_disp_base_mthd_chan;
+extern struct nv50_disp_chan_impl gf110_disp_oimm_ofuncs;
+extern struct nv50_disp_chan_impl gf110_disp_curs_ofuncs;
+extern struct nvkm_ofuncs gf110_disp_main_ofuncs;
+extern struct nvkm_oclass gf110_disp_cclass;
+void gf110_disp_intr_supervisor(struct work_struct *);
+void gf110_disp_intr(struct nvkm_subdev *);
+extern const struct nvkm_event_func gf110_disp_vblank_func;
-extern const struct nv50_disp_mthd_chan nve0_disp_core_mthd_chan;
-extern const struct nv50_disp_mthd_chan nve0_disp_ovly_mthd_chan;
+extern const struct nv50_disp_mthd_chan gk104_disp_core_mthd_chan;
+extern const struct nv50_disp_mthd_chan gk104_disp_ovly_mthd_chan;
extern struct nvkm_output_dp_impl nv50_pior_dp_impl;
-extern struct nouveau_oclass *nv50_disp_outp_sclass[];
+extern struct nvkm_oclass *nv50_disp_outp_sclass[];
-extern struct nvkm_output_dp_impl nv94_sor_dp_impl;
-int nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int);
-extern struct nouveau_oclass *nv94_disp_outp_sclass[];
+extern struct nvkm_output_dp_impl g94_sor_dp_impl;
+int g94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int);
+extern struct nvkm_oclass *g94_disp_outp_sclass[];
-extern struct nvkm_output_dp_impl nvd0_sor_dp_impl;
-int nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool);
-extern struct nouveau_oclass *nvd0_disp_outp_sclass[];
+extern struct nvkm_output_dp_impl gf110_sor_dp_impl;
+int gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool);
+extern struct nvkm_oclass *gf110_disp_outp_sclass[];
void gm204_sor_magic(struct nvkm_output *outp);
extern struct nvkm_output_dp_impl gm204_sor_dp_impl;
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c
index c5589c26e07d..9224bcbf0159 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c
@@ -21,57 +21,58 @@
*
* Authors: Ben Skeggs
*/
+#include "outp.h"
+#include "priv.h"
-#include <subdev/i2c.h>
#include <subdev/bios.h>
#include <subdev/bios/conn.h>
-
-#include "outp.h"
+#include <subdev/bios/dcb.h>
+#include <subdev/i2c.h>
int
-_nvkm_output_fini(struct nouveau_object *object, bool suspend)
+_nvkm_output_fini(struct nvkm_object *object, bool suspend)
{
struct nvkm_output *outp = (void *)object;
nv_ofuncs(outp->conn)->fini(nv_object(outp->conn), suspend);
- return nouveau_object_fini(&outp->base, suspend);
+ return nvkm_object_fini(&outp->base, suspend);
}
int
-_nvkm_output_init(struct nouveau_object *object)
+_nvkm_output_init(struct nvkm_object *object)
{
struct nvkm_output *outp = (void *)object;
- int ret = nouveau_object_init(&outp->base);
+ int ret = nvkm_object_init(&outp->base);
if (ret == 0)
nv_ofuncs(outp->conn)->init(nv_object(outp->conn));
return 0;
}
void
-_nvkm_output_dtor(struct nouveau_object *object)
+_nvkm_output_dtor(struct nvkm_object *object)
{
struct nvkm_output *outp = (void *)object;
list_del(&outp->head);
- nouveau_object_ref(NULL, (void *)&outp->conn);
- nouveau_object_destroy(&outp->base);
+ nvkm_object_ref(NULL, (void *)&outp->conn);
+ nvkm_object_destroy(&outp->base);
}
int
-nvkm_output_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass,
+nvkm_output_create_(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass,
struct dcb_output *dcbE, int index,
int length, void **pobject)
{
- struct nouveau_disp *disp = nouveau_disp(parent);
- struct nouveau_bios *bios = nouveau_bios(parent);
- struct nouveau_i2c *i2c = nouveau_i2c(parent);
+ struct nvkm_disp *disp = nvkm_disp(parent);
+ struct nvkm_bios *bios = nvkm_bios(parent);
+ struct nvkm_i2c *i2c = nvkm_i2c(parent);
struct nvbios_connE connE;
struct nvkm_output *outp;
u8 ver, hdr;
u32 data;
int ret;
- ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject);
+ ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject);
outp = *pobject;
if (ret)
return ret;
@@ -98,9 +99,9 @@ nvkm_output_create_(struct nouveau_object *parent,
connE.type = DCB_CONNECTOR_NONE;
}
- ret = nouveau_object_ctor(parent, NULL, nvkm_connector_oclass,
- &connE, outp->info.connector,
- (struct nouveau_object **)&outp->conn);
+ ret = nvkm_object_ctor(parent, NULL, nvkm_connector_oclass,
+ &connE, outp->info.connector,
+ (struct nvkm_object **)&outp->conn);
if (ret < 0) {
ERR("error %d creating connector, disabling\n", ret);
return ret;
@@ -111,10 +112,10 @@ nvkm_output_create_(struct nouveau_object *parent,
}
int
-_nvkm_output_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *dcbE, u32 index,
- struct nouveau_object **pobject)
+_nvkm_output_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *dcbE, u32 index,
+ struct nvkm_object **pobject)
{
struct nvkm_output *outp;
int ret;
@@ -127,11 +128,11 @@ _nvkm_output_ctor(struct nouveau_object *parent,
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nvkm_output_oclass = &(struct nvkm_output_impl) {
.base = {
.handle = 0,
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_output_ctor,
.dtor = _nvkm_output_dtor,
.init = _nvkm_output_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h
index 5305aa0f73b6..d9253d26c31b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h
@@ -1,18 +1,20 @@
#ifndef __NVKM_DISP_OUTP_H__
#define __NVKM_DISP_OUTP_H__
+#include <core/object.h>
-#include "priv.h"
+#include <subdev/bios.h>
+#include <subdev/bios/dcb.h>
struct nvkm_output {
- struct nouveau_object base;
+ struct nvkm_object base;
struct list_head head;
struct dcb_output info;
int index;
int or;
- struct nouveau_i2c_port *port;
- struct nouveau_i2c_port *edid;
+ struct nvkm_i2c_port *port;
+ struct nvkm_i2c_port *edid;
struct nvkm_connector *conn;
};
@@ -32,19 +34,19 @@ struct nvkm_output {
_nvkm_output_fini(nv_object(_outp), (s)); \
})
-int nvkm_output_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, struct dcb_output *,
+int nvkm_output_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, struct dcb_output *,
int, int, void **);
-int _nvkm_output_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void _nvkm_output_dtor(struct nouveau_object *);
-int _nvkm_output_init(struct nouveau_object *);
-int _nvkm_output_fini(struct nouveau_object *, bool);
+int _nvkm_output_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void _nvkm_output_dtor(struct nvkm_object *);
+int _nvkm_output_init(struct nvkm_object *);
+int _nvkm_output_fini(struct nvkm_object *, bool);
struct nvkm_output_impl {
- struct nouveau_oclass base;
+ struct nvkm_oclass base;
};
#ifndef MSG
@@ -56,5 +58,4 @@ struct nvkm_output_impl {
#define DBG(f,a...) MSG(debug, f, ##a)
#define ERR(f,a...) MSG(error, f, ##a)
#endif
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.c
index 667a9070e006..0bde0fa5b59d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/os.h>
-#include <nvif/event.h>
-
-#include <subdev/i2c.h>
-
#include "outpdp.h"
#include "conn.h"
#include "dport.h"
+#include "priv.h"
+
+#include <subdev/i2c.h>
+
+#include <nvif/event.h>
int
nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait)
@@ -105,17 +104,17 @@ done:
static void
nvkm_output_dp_enable(struct nvkm_output_dp *outp, bool present)
{
- struct nouveau_i2c_port *port = outp->base.edid;
+ struct nvkm_i2c_port *port = outp->base.edid;
if (present) {
if (!outp->present) {
- nouveau_i2c(port)->acquire_pad(port, 0);
+ nvkm_i2c(port)->acquire_pad(port, 0);
DBG("aux power -> always\n");
outp->present = true;
}
nvkm_output_dp_train(&outp->base, 0, true);
} else {
if (outp->present) {
- nouveau_i2c(port)->release_pad(port);
+ nvkm_i2c(port)->release_pad(port);
DBG("aux power -> demand\n");
outp->present = false;
}
@@ -126,13 +125,13 @@ nvkm_output_dp_enable(struct nvkm_output_dp *outp, bool present)
static void
nvkm_output_dp_detect(struct nvkm_output_dp *outp)
{
- struct nouveau_i2c_port *port = outp->base.edid;
- int ret = nouveau_i2c(port)->acquire_pad(port, 0);
+ struct nvkm_i2c_port *port = outp->base.edid;
+ int ret = nvkm_i2c(port)->acquire_pad(port, 0);
if (ret == 0) {
ret = nv_rdaux(outp->base.edid, DPCD_RC00_DPCD_REV,
outp->dpcd, sizeof(outp->dpcd));
nvkm_output_dp_enable(outp, ret == 0);
- nouveau_i2c(port)->release_pad(port);
+ nvkm_i2c(port)->release_pad(port);
}
}
@@ -141,7 +140,7 @@ nvkm_output_dp_hpd(struct nvkm_notify *notify)
{
struct nvkm_connector *conn = container_of(notify, typeof(*conn), hpd);
struct nvkm_output_dp *outp;
- struct nouveau_disp *disp = nouveau_disp(conn);
+ struct nvkm_disp *disp = nvkm_disp(conn);
const struct nvkm_i2c_ntfy_rep *line = notify->data;
struct nvif_notify_conn_rep_v0 rep = {};
@@ -170,7 +169,7 @@ static int
nvkm_output_dp_irq(struct nvkm_notify *notify)
{
struct nvkm_output_dp *outp = container_of(notify, typeof(*outp), irq);
- struct nouveau_disp *disp = nouveau_disp(outp);
+ struct nvkm_disp *disp = nvkm_disp(outp);
const struct nvkm_i2c_ntfy_rep *line = notify->data;
struct nvif_notify_conn_rep_v0 rep = {
.mask = NVIF_NOTIFY_CONN_V0_IRQ,
@@ -185,7 +184,7 @@ nvkm_output_dp_irq(struct nvkm_notify *notify)
}
int
-_nvkm_output_dp_fini(struct nouveau_object *object, bool suspend)
+_nvkm_output_dp_fini(struct nvkm_object *object, bool suspend)
{
struct nvkm_output_dp *outp = (void *)object;
nvkm_notify_put(&outp->irq);
@@ -194,7 +193,7 @@ _nvkm_output_dp_fini(struct nouveau_object *object, bool suspend)
}
int
-_nvkm_output_dp_init(struct nouveau_object *object)
+_nvkm_output_dp_init(struct nvkm_object *object)
{
struct nvkm_output_dp *outp = (void *)object;
nvkm_output_dp_detect(outp);
@@ -202,7 +201,7 @@ _nvkm_output_dp_init(struct nouveau_object *object)
}
void
-_nvkm_output_dp_dtor(struct nouveau_object *object)
+_nvkm_output_dp_dtor(struct nvkm_object *object)
{
struct nvkm_output_dp *outp = (void *)object;
nvkm_notify_fini(&outp->irq);
@@ -210,14 +209,14 @@ _nvkm_output_dp_dtor(struct nouveau_object *object)
}
int
-nvkm_output_dp_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass,
+nvkm_output_dp_create_(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass,
struct dcb_output *info, int index,
int length, void **pobject)
{
- struct nouveau_bios *bios = nouveau_bios(parent);
- struct nouveau_i2c *i2c = nouveau_i2c(parent);
+ struct nvkm_bios *bios = nvkm_bios(parent);
+ struct nvkm_i2c *i2c = nvkm_i2c(parent);
struct nvkm_output_dp *outp;
u8 hdr, cnt, len;
u32 data;
@@ -249,7 +248,7 @@ nvkm_output_dp_create_(struct nouveau_object *parent,
DBG("bios dp %02x %02x %02x %02x\n", outp->version, hdr, cnt, len);
/* link training */
- INIT_WORK(&outp->lt.work, nouveau_dp_train);
+ INIT_WORK(&outp->lt.work, nvkm_dp_train);
init_waitqueue_head(&outp->lt.wait);
atomic_set(&outp->lt.done, 0);
@@ -285,10 +284,10 @@ nvkm_output_dp_create_(struct nouveau_object *parent,
}
int
-_nvkm_output_dp_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *info, u32 index,
- struct nouveau_object **pobject)
+_nvkm_output_dp_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *info, u32 index,
+ struct nvkm_object **pobject)
{
struct nvkm_output_dp *outp;
int ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h
index 74ef058ff051..70c77aec4850 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h
@@ -1,12 +1,11 @@
#ifndef __NVKM_DISP_OUTP_DP_H__
#define __NVKM_DISP_OUTP_DP_H__
+#include "outp.h"
#include <core/notify.h>
#include <subdev/bios.h>
#include <subdev/bios/dp.h>
-#include "outp.h"
-
struct nvkm_output_dp {
struct nvkm_output base;
@@ -39,16 +38,16 @@ struct nvkm_output_dp {
_nvkm_output_dp_fini(nv_object(_outp), (s)); \
})
-int nvkm_output_dp_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, struct dcb_output *,
+int nvkm_output_dp_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, struct dcb_output *,
int, int, void **);
-int _nvkm_output_dp_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void _nvkm_output_dp_dtor(struct nouveau_object *);
-int _nvkm_output_dp_init(struct nouveau_object *);
-int _nvkm_output_dp_fini(struct nouveau_object *, bool);
+int _nvkm_output_dp_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void _nvkm_output_dp_dtor(struct nvkm_object *);
+int _nvkm_output_dp_init(struct nvkm_object *);
+int _nvkm_output_dp_fini(struct nvkm_object *, bool);
struct nvkm_output_dp_impl {
struct nvkm_output_impl base;
@@ -59,5 +58,4 @@ struct nvkm_output_dp_impl {
};
int nvkm_output_dp_train(struct nvkm_output *, u32 rate, bool wait);
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c
index d00f89a468a7..2a1d8871bf82 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c
@@ -21,29 +21,27 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
+#include "outpdp.h"
#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/timer.h>
#include <subdev/i2c.h>
+#include <subdev/timer.h>
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
/******************************************************************************
* TMDS
*****************************************************************************/
static int
-nv50_pior_tmds_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *info, u32 index,
- struct nouveau_object **pobject)
+nv50_pior_tmds_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *info, u32 index,
+ struct nvkm_object **pobject)
{
- struct nouveau_i2c *i2c = nouveau_i2c(parent);
+ struct nvkm_i2c *i2c = nvkm_i2c(parent);
struct nvkm_output *outp;
int ret;
@@ -59,7 +57,7 @@ nv50_pior_tmds_ctor(struct nouveau_object *parent,
struct nvkm_output_impl
nv50_pior_tmds_impl = {
.base.handle = DCB_OUTPUT_TMDS | 0x0100,
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_pior_tmds_ctor,
.dtor = _nvkm_output_dtor,
.init = _nvkm_output_init,
@@ -74,7 +72,7 @@ nv50_pior_tmds_impl = {
static int
nv50_pior_dp_pattern(struct nvkm_output_dp *outp, int pattern)
{
- struct nouveau_i2c_port *port = outp->base.edid;
+ struct nvkm_i2c_port *port = outp->base.edid;
if (port && port->func->pattern)
return port->func->pattern(port, pattern);
return port ? 0 : -ENODEV;
@@ -89,7 +87,7 @@ nv50_pior_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
static int
nv50_pior_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
{
- struct nouveau_i2c_port *port = outp->base.edid;
+ struct nvkm_i2c_port *port = outp->base.edid;
if (port && port->func->lnk_ctl)
return port->func->lnk_ctl(port, nr, bw, ef);
return port ? 0 : -ENODEV;
@@ -98,19 +96,19 @@ nv50_pior_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
static int
nv50_pior_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
{
- struct nouveau_i2c_port *port = outp->base.edid;
+ struct nvkm_i2c_port *port = outp->base.edid;
if (port && port->func->drv_ctl)
return port->func->drv_ctl(port, ln, vs, pe);
return port ? 0 : -ENODEV;
}
static int
-nv50_pior_dp_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *info, u32 index,
- struct nouveau_object **pobject)
+nv50_pior_dp_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *info, u32 index,
+ struct nvkm_object **pobject)
{
- struct nouveau_i2c *i2c = nouveau_i2c(parent);
+ struct nvkm_i2c *i2c = nvkm_i2c(parent);
struct nvkm_output_dp *outp;
int ret;
@@ -127,7 +125,7 @@ nv50_pior_dp_ctor(struct nouveau_object *parent,
struct nvkm_output_dp_impl
nv50_pior_dp_impl = {
.base.base.handle = DCB_OUTPUT_DP | 0x0010,
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_pior_dp_ctor,
.dtor = _nvkm_output_dp_dtor,
.init = _nvkm_output_dp_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h
index 6a0511d54ce6..961ce8bb2135 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h
@@ -1,48 +1,42 @@
#ifndef __NVKM_DISP_PRIV_H__
#define __NVKM_DISP_PRIV_H__
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/conn.h>
-
#include <engine/disp.h>
-struct nouveau_disp_impl {
- struct nouveau_oclass base;
- struct nouveau_oclass **outp;
- struct nouveau_oclass **conn;
+struct nvkm_disp_impl {
+ struct nvkm_oclass base;
+ struct nvkm_oclass **outp;
+ struct nvkm_oclass **conn;
const struct nvkm_event_func *vblank;
};
-#define nouveau_disp_create(p,e,c,h,i,x,d) \
- nouveau_disp_create_((p), (e), (c), (h), (i), (x), \
+#define nvkm_disp_create(p,e,c,h,i,x,d) \
+ nvkm_disp_create_((p), (e), (c), (h), (i), (x), \
sizeof(**d), (void **)d)
-#define nouveau_disp_destroy(d) ({ \
- struct nouveau_disp *disp = (d); \
- _nouveau_disp_dtor(nv_object(disp)); \
+#define nvkm_disp_destroy(d) ({ \
+ struct nvkm_disp *disp = (d); \
+ _nvkm_disp_dtor(nv_object(disp)); \
})
-#define nouveau_disp_init(d) ({ \
- struct nouveau_disp *disp = (d); \
- _nouveau_disp_init(nv_object(disp)); \
+#define nvkm_disp_init(d) ({ \
+ struct nvkm_disp *disp = (d); \
+ _nvkm_disp_init(nv_object(disp)); \
})
-#define nouveau_disp_fini(d,s) ({ \
- struct nouveau_disp *disp = (d); \
- _nouveau_disp_fini(nv_object(disp), (s)); \
+#define nvkm_disp_fini(d,s) ({ \
+ struct nvkm_disp *disp = (d); \
+ _nvkm_disp_fini(nv_object(disp), (s)); \
})
-int nouveau_disp_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int heads,
+int nvkm_disp_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int heads,
const char *, const char *, int, void **);
-void _nouveau_disp_dtor(struct nouveau_object *);
-int _nouveau_disp_init(struct nouveau_object *);
-int _nouveau_disp_fini(struct nouveau_object *, bool);
+void _nvkm_disp_dtor(struct nvkm_object *);
+int _nvkm_disp_init(struct nvkm_object *);
+int _nvkm_disp_fini(struct nvkm_object *, bool);
-extern struct nouveau_oclass *nvkm_output_oclass;
-extern struct nouveau_oclass *nvkm_connector_oclass;
-
-int nouveau_disp_vblank_ctor(struct nouveau_object *, void *data, u32 size,
- struct nvkm_notify *);
-void nouveau_disp_vblank(struct nouveau_disp *, int head);
-int nouveau_disp_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
+extern struct nvkm_oclass *nvkm_output_oclass;
+extern struct nvkm_oclass *nvkm_connector_oclass;
+int nvkm_disp_vblank_ctor(struct nvkm_object *, void *data, u32 size,
+ struct nvkm_notify *);
+void nvkm_disp_vblank(struct nvkm_disp *, int head);
+int nvkm_disp_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
similarity index 65%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv94.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
index 39f85d627336..8918da7ffdf2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv94.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
@@ -21,59 +21,53 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/os.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
-#include <subdev/bios/init.h>
-#include <subdev/timer.h>
-
#include "nv50.h"
#include "outpdp.h"
+#include <core/device.h>
+#include <subdev/timer.h>
+
static inline u32
-nv94_sor_soff(struct nvkm_output_dp *outp)
+g94_sor_soff(struct nvkm_output_dp *outp)
{
return (ffs(outp->base.info.or) - 1) * 0x800;
}
static inline u32
-nv94_sor_loff(struct nvkm_output_dp *outp)
+g94_sor_loff(struct nvkm_output_dp *outp)
{
- return nv94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
+ return g94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
}
static inline u32
-nv94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
+g94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
{
- static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
- static const u8 nv94[] = { 16, 8, 0, 24 };
+ static const u8 mcp89[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
+ static const u8 g94[] = { 16, 8, 0, 24 };
if (nv_device(priv)->chipset == 0xaf)
- return nvaf[lane];
- return nv94[lane];
+ return mcp89[lane];
+ return g94[lane];
}
static int
-nv94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
+g94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
{
- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
- const u32 loff = nv94_sor_loff(outp);
+ struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+ const u32 loff = g94_sor_loff(outp);
nv_mask(priv, 0x61c10c + loff, 0x0f000000, pattern << 24);
return 0;
}
int
-nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
+g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
{
- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
- const u32 soff = nv94_sor_soff(outp);
- const u32 loff = nv94_sor_loff(outp);
+ struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+ const u32 soff = g94_sor_soff(outp);
+ const u32 loff = g94_sor_loff(outp);
u32 mask = 0, i;
for (i = 0; i < nr; i++)
- mask |= 1 << (nv94_sor_dp_lane_map(priv, i) >> 3);
+ mask |= 1 << (g94_sor_dp_lane_map(priv, i) >> 3);
nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask);
nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000);
@@ -82,11 +76,11 @@ nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
}
static int
-nv94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
+g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
{
- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
- const u32 soff = nv94_sor_soff(outp);
- const u32 loff = nv94_sor_loff(outp);
+ struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+ const u32 soff = g94_sor_soff(outp);
+ const u32 loff = g94_sor_loff(outp);
u32 dpctrl = 0x00000000;
u32 clksor = 0x00000000;
@@ -102,12 +96,12 @@ nv94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
}
static int
-nv94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
+g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
{
- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
- struct nouveau_bios *bios = nouveau_bios(priv);
- const u32 shift = nv94_sor_dp_lane_map(priv, ln);
- const u32 loff = nv94_sor_loff(outp);
+ struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+ struct nvkm_bios *bios = nvkm_bios(priv);
+ const u32 shift = g94_sor_dp_lane_map(priv, ln);
+ const u32 loff = g94_sor_loff(outp);
u32 addr, data[3];
u8 ver, hdr, cnt, len;
struct nvbios_dpout info;
@@ -136,16 +130,16 @@ nv94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
}
struct nvkm_output_dp_impl
-nv94_sor_dp_impl = {
+g94_sor_dp_impl = {
.base.base.handle = DCB_OUTPUT_DP,
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_output_dp_ctor,
.dtor = _nvkm_output_dp_dtor,
.init = _nvkm_output_dp_init,
.fini = _nvkm_output_dp_fini,
},
- .pattern = nv94_sor_dp_pattern,
- .lnk_pwr = nv94_sor_dp_lnk_pwr,
- .lnk_ctl = nv94_sor_dp_lnk_ctl,
- .drv_ctl = nv94_sor_dp_drv_ctl,
+ .pattern = g94_sor_dp_pattern,
+ .lnk_pwr = g94_sor_dp_lnk_pwr,
+ .lnk_ctl = g94_sor_dp_lnk_ctl,
+ .drv_ctl = g94_sor_dp_drv_ctl,
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c
similarity index 66%
rename from drivers/gpu/drm/nouveau/nvkm/engine/disp/sornvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c
index fdab2939070c..52fbe4880e13 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornvd0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c
@@ -21,51 +21,43 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/os.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
-#include <subdev/bios/init.h>
-#include <subdev/timer.h>
-
#include "nv50.h"
+#include "outpdp.h"
static inline u32
-nvd0_sor_soff(struct nvkm_output_dp *outp)
+gf110_sor_soff(struct nvkm_output_dp *outp)
{
return (ffs(outp->base.info.or) - 1) * 0x800;
}
static inline u32
-nvd0_sor_loff(struct nvkm_output_dp *outp)
+gf110_sor_loff(struct nvkm_output_dp *outp)
{
- return nvd0_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
+ return gf110_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
}
static inline u32
-nvd0_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
+gf110_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
{
- static const u8 nvd0[] = { 16, 8, 0, 24 };
- return nvd0[lane];
+ static const u8 gf110[] = { 16, 8, 0, 24 };
+ return gf110[lane];
}
static int
-nvd0_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
+gf110_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
{
- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
- const u32 loff = nvd0_sor_loff(outp);
+ struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+ const u32 loff = gf110_sor_loff(outp);
nv_mask(priv, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
return 0;
}
int
-nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
+gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
{
- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
- const u32 soff = nvd0_sor_soff(outp);
- const u32 loff = nvd0_sor_loff(outp);
+ struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+ const u32 soff = gf110_sor_soff(outp);
+ const u32 loff = gf110_sor_loff(outp);
u32 dpctrl = 0x00000000;
u32 clksor = 0x00000000;
@@ -80,12 +72,13 @@ nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
}
static int
-nvd0_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
+gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
+ int ln, int vs, int pe, int pc)
{
- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
- struct nouveau_bios *bios = nouveau_bios(priv);
- const u32 shift = nvd0_sor_dp_lane_map(priv, ln);
- const u32 loff = nvd0_sor_loff(outp);
+ struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+ struct nvkm_bios *bios = nvkm_bios(priv);
+ const u32 shift = gf110_sor_dp_lane_map(priv, ln);
+ const u32 loff = gf110_sor_loff(outp);
u32 addr, data[4];
u8 ver, hdr, cnt, len;
struct nvbios_dpout info;
@@ -93,12 +86,12 @@ nvd0_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
addr = nvbios_dpout_match(bios, outp->base.info.hasht,
outp->base.info.hashm,
- &ver, &hdr, &cnt, &len, &info);
+ &ver, &hdr, &cnt, &len, &info);
if (!addr)
return -ENODEV;
addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe,
- &ver, &hdr, &cnt, &len, &ocfg);
+ &ver, &hdr, &cnt, &len, &ocfg);
if (!addr)
return -EINVAL;
@@ -116,16 +109,16 @@ nvd0_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
}
struct nvkm_output_dp_impl
-nvd0_sor_dp_impl = {
+gf110_sor_dp_impl = {
.base.base.handle = DCB_OUTPUT_DP,
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_output_dp_ctor,
.dtor = _nvkm_output_dp_dtor,
.init = _nvkm_output_dp_init,
.fini = _nvkm_output_dp_fini,
},
- .pattern = nvd0_sor_dp_pattern,
- .lnk_pwr = nv94_sor_dp_lnk_pwr,
- .lnk_ctl = nvd0_sor_dp_lnk_ctl,
- .drv_ctl = nvd0_sor_dp_drv_ctl,
+ .pattern = gf110_sor_dp_pattern,
+ .lnk_pwr = g94_sor_dp_lnk_pwr,
+ .lnk_ctl = gf110_sor_dp_lnk_ctl,
+ .drv_ctl = gf110_sor_dp_drv_ctl,
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c
index 0b4fad39e9a6..1e40dfe11319 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c
@@ -21,16 +21,10 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/os.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
-#include <subdev/bios/init.h>
-#include <subdev/timer.h>
-
#include "nv50.h"
+#include "outpdp.h"
+
+#include <subdev/timer.h>
static inline u32
gm204_sor_soff(struct nvkm_output_dp *outp)
@@ -47,7 +41,7 @@ gm204_sor_loff(struct nvkm_output_dp *outp)
void
gm204_sor_magic(struct nvkm_output *outp)
{
- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
+ struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
const u32 soff = outp->or * 0x100;
const u32 data = outp->or + 1;
if (outp->info.sorconf.link & 1)
@@ -65,7 +59,7 @@ gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
static int
gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
{
- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
+ struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
const u32 soff = gm204_sor_soff(outp);
const u32 data = 0x01010101 * pattern;
if (outp->base.info.sorconf.link & 1)
@@ -78,7 +72,7 @@ gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
static int
gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
{
- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
+ struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
const u32 soff = gm204_sor_soff(outp);
const u32 loff = gm204_sor_loff(outp);
u32 mask = 0, i;
@@ -93,10 +87,11 @@ gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
}
static int
-gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
+gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
+ int ln, int vs, int pe, int pc)
{
- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+ struct nvkm_bios *bios = nvkm_bios(priv);
const u32 shift = gm204_sor_dp_lane_map(priv, ln);
const u32 loff = gm204_sor_loff(outp);
u32 addr, data[4];
@@ -106,12 +101,12 @@ gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc
addr = nvbios_dpout_match(bios, outp->base.info.hasht,
outp->base.info.hashm,
- &ver, &hdr, &cnt, &len, &info);
+ &ver, &hdr, &cnt, &len, &info);
if (!addr)
return -ENODEV;
addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe,
- &ver, &hdr, &cnt, &len, &ocfg);
+ &ver, &hdr, &cnt, &len, &ocfg);
if (!addr)
return -EINVAL;
@@ -131,7 +126,7 @@ gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc
struct nvkm_output_dp_impl
gm204_sor_dp_impl = {
.base.base.handle = DCB_OUTPUT_DP,
- .base.base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_output_dp_ctor,
.dtor = _nvkm_output_dp_dtor,
.init = _nvkm_output_dp_init,
@@ -139,6 +134,6 @@ gm204_sor_dp_impl = {
},
.pattern = gm204_sor_dp_pattern,
.lnk_pwr = gm204_sor_dp_lnk_pwr,
- .lnk_ctl = nvd0_sor_dp_lnk_ctl,
+ .lnk_ctl = gf110_sor_dp_lnk_ctl,
.drv_ctl = gm204_sor_dp_drv_ctl,
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c
index ddf1760c4400..b229a311c78c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c
@@ -21,16 +21,14 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
+#include "outp.h"
#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
#include <subdev/timer.h>
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
int
nv50_sor_power(NV50_DISP_MTHD_V1)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c
index 8836c3cb99c3..c4622c7388d0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/subdev.h>
-#include <core/device.h>
#include <subdev/vga.h>
+#include <core/device.h>
+
u8
nv_rdport(void *obj, int head, u16 port)
{
- struct nouveau_device *device = nv_device(obj);
+ struct nvkm_device *device = nv_device(obj);
if (device->card_type >= NV_50)
return nv_rd08(obj, 0x601000 + port);
@@ -54,7 +53,7 @@ nv_rdport(void *obj, int head, u16 port)
void
nv_wrport(void *obj, int head, u16 port, u8 data)
{
- struct nouveau_device *device = nv_device(obj);
+ struct nvkm_device *device = nv_device(obj);
if (device->card_type >= NV_50)
nv_wr08(obj, 0x601000 + port, data);
@@ -138,7 +137,7 @@ nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value)
bool
nv_lockvgac(void *obj, bool lock)
{
- struct nouveau_device *dev = nv_device(obj);
+ struct nvkm_device *dev = nv_device(obj);
bool locked = !nv_rdvgac(obj, 0, 0x1f);
u8 data = lock ? 0x99 : 0x57;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
index a214a4debcc4..6833e00827c2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
@@ -23,6 +23,7 @@
*/
#include <core/os.h>
+#include <core/device.h>
#include <core/engctx.h>
#include <core/namedb.h>
#include <core/handle.h>
From 5b85057acc411ee146ee4b230c773272ccee464d Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:27:54 +1000
Subject: [PATCH 74/86] drm/nouveau/dmaobj: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/engine/dmaobj.h | 33 ++++------
.../drm/nouveau/nvkm/engine/device/gm100.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 ++---
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 16 ++---
.../gpu/drm/nouveau/nvkm/engine/dmaobj/Kbuild | 4 +-
.../gpu/drm/nouveau/nvkm/engine/dmaobj/base.c | 44 ++++++-------
.../nvkm/engine/dmaobj/{nvc0.c => gf100.c} | 65 +++++++++----------
.../nvkm/engine/dmaobj/{nvd0.c => gf110.c} | 65 +++++++++----------
.../gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c | 36 +++++-----
.../gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c | 32 +++++----
.../gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h | 32 +++++----
11 files changed, 165 insertions(+), 184 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/{nvc0.c => gf100.c} (78%)
rename drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/{nvd0.c => gf110.c} (78%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h
index 1b283a7b78e6..c4fce8afcf83 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h
@@ -1,31 +1,26 @@
-#ifndef __NOUVEAU_DMAOBJ_H__
-#define __NOUVEAU_DMAOBJ_H__
-
-#include <core/object.h>
+#ifndef __NVKM_DMAOBJ_H__
+#define __NVKM_DMAOBJ_H__
#include <core/engine.h>
+struct nvkm_gpuobj;
-struct nouveau_gpuobj;
-
-struct nouveau_dmaobj {
- struct nouveau_object base;
+struct nvkm_dmaobj {
+ struct nvkm_object base;
u32 target;
u32 access;
u64 start;
u64 limit;
};
-struct nouveau_dmaeng {
- struct nouveau_engine base;
+struct nvkm_dmaeng {
+ struct nvkm_engine base;
- /* creates a "physical" dma object from a struct nouveau_dmaobj */
- int (*bind)(struct nouveau_dmaobj *dmaobj,
- struct nouveau_object *parent,
- struct nouveau_gpuobj **);
+ /* creates a "physical" dma object from a struct nvkm_dmaobj */
+ int (*bind)(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
+ struct nvkm_gpuobj **);
};
-extern struct nouveau_oclass *nv04_dmaeng_oclass;
-extern struct nouveau_oclass *nv50_dmaeng_oclass;
-extern struct nouveau_oclass *nvc0_dmaeng_oclass;
-extern struct nouveau_oclass *nvd0_dmaeng_oclass;
-
+extern struct nvkm_oclass *nv04_dmaeng_oclass;
+extern struct nvkm_oclass *nv50_dmaeng_oclass;
+extern struct nvkm_oclass *gf100_dmaeng_oclass;
+extern struct nvkm_oclass *gf110_dmaeng_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index dfc9e544e3e6..1d851d61f982 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -83,7 +83,7 @@ gm100_identify(struct nouveau_device *device)
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
@@ -126,7 +126,7 @@ gm100_identify(struct nouveau_device *device)
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
#if 0
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 9ef067398052..9a4e062656ac 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -80,7 +80,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
@@ -113,7 +113,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
@@ -146,7 +146,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
@@ -178,7 +178,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
@@ -211,7 +211,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
@@ -243,7 +243,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
@@ -275,7 +275,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
@@ -308,7 +308,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
@@ -338,7 +338,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 1072ada31416..91aea039bfb1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -80,7 +80,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
@@ -114,7 +114,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
@@ -148,7 +148,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
@@ -174,7 +174,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
@@ -204,7 +204,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass;
@@ -238,7 +238,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
@@ -272,7 +272,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
@@ -305,7 +305,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
+ device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/Kbuild
index 4f9286a038ef..7529632dbedb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/Kbuild
@@ -1,5 +1,5 @@
nvkm-y += nvkm/engine/dmaobj/base.o
nvkm-y += nvkm/engine/dmaobj/nv04.o
nvkm-y += nvkm/engine/dmaobj/nv50.o
-nvkm-y += nvkm/engine/dmaobj/nvc0.o
-nvkm-y += nvkm/engine/dmaobj/nvd0.o
+nvkm-y += nvkm/engine/dmaobj/gf100.o
+nvkm-y += nvkm/engine/dmaobj/gf110.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c
index 741f4a7cc0b1..a2b60d86baba 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c
@@ -21,21 +21,19 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
-#include <core/object.h>
#include <core/client.h>
#include <core/device.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
#include <subdev/fb.h>
#include <subdev/instmem.h>
-#include "priv.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
static int
-nvkm_dmaobj_bind(struct nouveau_dmaobj *dmaobj, struct nouveau_object *parent,
- struct nouveau_gpuobj **pgpuobj)
+nvkm_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
+ struct nvkm_gpuobj **pgpuobj)
{
const struct nvkm_dmaeng_impl *impl = (void *)
nv_oclass(nv_object(dmaobj)->engine);
@@ -48,7 +46,7 @@ nvkm_dmaobj_bind(struct nouveau_dmaobj *dmaobj, struct nouveau_object *parent,
}
ret = impl->bind(dmaobj, parent, pgpuobj);
if (ret == 0)
- nouveau_object_ref(NULL, &parent);
+ nvkm_object_ref(NULL, &parent);
return ret;
}
@@ -56,24 +54,24 @@ nvkm_dmaobj_bind(struct nouveau_dmaobj *dmaobj, struct nouveau_object *parent,
}
int
-nvkm_dmaobj_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void **pdata, u32 *psize,
+nvkm_dmaobj_create_(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void **pdata, u32 *psize,
int length, void **pobject)
{
union {
struct nv_dma_v0 v0;
} *args = *pdata;
- struct nouveau_instmem *instmem = nouveau_instmem(parent);
- struct nouveau_client *client = nouveau_client(parent);
- struct nouveau_device *device = nv_device(parent);
- struct nouveau_fb *pfb = nouveau_fb(parent);
- struct nouveau_dmaobj *dmaobj;
+ struct nvkm_instmem *instmem = nvkm_instmem(parent);
+ struct nvkm_client *client = nvkm_client(parent);
+ struct nvkm_device *device = nv_device(parent);
+ struct nvkm_fb *pfb = nvkm_fb(parent);
+ struct nvkm_dmaobj *dmaobj;
void *data = *pdata;
u32 size = *psize;
int ret;
- ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject);
+ ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject);
dmaobj = *pobject;
if (ret)
return ret;
@@ -146,16 +144,16 @@ nvkm_dmaobj_create_(struct nouveau_object *parent,
}
int
-_nvkm_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+_nvkm_dmaeng_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
const struct nvkm_dmaeng_impl *impl = (void *)oclass;
- struct nouveau_dmaeng *dmaeng;
+ struct nvkm_dmaeng *dmaeng;
int ret;
- ret = nouveau_engine_create(parent, engine, oclass, true, "DMAOBJ",
- "dmaobj", &dmaeng);
+ ret = nvkm_engine_create(parent, engine, oclass, true, "DMAOBJ",
+ "dmaobj", &dmaeng);
*pobject = nv_object(dmaeng);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c
similarity index 78%
rename from drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c
index 88ec33b20048..f880e5167e45 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c
@@ -21,29 +21,26 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/client.h>
-#include <core/device.h>
-#include <core/gpuobj.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/fb.h>
-
#include "priv.h"
-struct nvc0_dmaobj_priv {
- struct nouveau_dmaobj base;
+#include <core/client.h>
+#include <core/gpuobj.h>
+#include <subdev/fb.h>
+
+#include <nvif/class.h>
+#include <nvif/unpack.h>
+
+struct gf100_dmaobj_priv {
+ struct nvkm_dmaobj base;
u32 flags0;
u32 flags5;
};
static int
-nvc0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
- struct nouveau_object *parent,
- struct nouveau_gpuobj **pgpuobj)
+gf100_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
+ struct nvkm_gpuobj **pgpuobj)
{
- struct nvc0_dmaobj_priv *priv = (void *)dmaobj;
+ struct gf100_dmaobj_priv *priv = (void *)dmaobj;
int ret;
if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
@@ -58,7 +55,7 @@ nvc0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
} else
return 0;
- ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
+ ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
if (ret == 0) {
nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
@@ -73,15 +70,15 @@ nvc0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
}
static int
-nvc0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_dmaeng *dmaeng = (void *)engine;
+ struct nvkm_dmaeng *dmaeng = (void *)engine;
union {
struct gf100_dma_v0 v0;
} *args;
- struct nvc0_dmaobj_priv *priv;
+ struct gf100_dmaobj_priv *priv;
u32 kind, user, unkn;
int ret;
@@ -149,31 +146,31 @@ nvc0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
}
-static struct nouveau_ofuncs
-nvc0_dmaobj_ofuncs = {
- .ctor = nvc0_dmaobj_ctor,
+static struct nvkm_ofuncs
+gf100_dmaobj_ofuncs = {
+ .ctor = gf100_dmaobj_ctor,
.dtor = _nvkm_dmaobj_dtor,
.init = _nvkm_dmaobj_init,
.fini = _nvkm_dmaobj_fini,
};
-static struct nouveau_oclass
-nvc0_dmaeng_sclass[] = {
- { NV_DMA_FROM_MEMORY, &nvc0_dmaobj_ofuncs },
- { NV_DMA_TO_MEMORY, &nvc0_dmaobj_ofuncs },
- { NV_DMA_IN_MEMORY, &nvc0_dmaobj_ofuncs },
+static struct nvkm_oclass
+gf100_dmaeng_sclass[] = {
+ { NV_DMA_FROM_MEMORY, &gf100_dmaobj_ofuncs },
+ { NV_DMA_TO_MEMORY, &gf100_dmaobj_ofuncs },
+ { NV_DMA_IN_MEMORY, &gf100_dmaobj_ofuncs },
{}
};
-struct nouveau_oclass *
-nvc0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
+struct nvkm_oclass *
+gf100_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
.base.handle = NV_ENGINE(DMAOBJ, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_dmaeng_ctor,
.dtor = _nvkm_dmaeng_dtor,
.init = _nvkm_dmaeng_init,
.fini = _nvkm_dmaeng_fini,
},
- .sclass = nvc0_dmaeng_sclass,
- .bind = nvc0_dmaobj_bind,
+ .sclass = gf100_dmaeng_sclass,
+ .bind = gf100_dmaobj_bind,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nvd0.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c
similarity index 78%
rename from drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nvd0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c
index 19f5f6522962..bf8f0f20976c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nvd0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c
@@ -21,28 +21,25 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/client.h>
-#include <core/device.h>
-#include <core/gpuobj.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/fb.h>
-
#include "priv.h"
-struct nvd0_dmaobj_priv {
- struct nouveau_dmaobj base;
+#include <core/client.h>
+#include <core/gpuobj.h>
+#include <subdev/fb.h>
+
+#include <nvif/class.h>
+#include <nvif/unpack.h>
+
+struct gf110_dmaobj_priv {
+ struct nvkm_dmaobj base;
u32 flags0;
};
static int
-nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
- struct nouveau_object *parent,
- struct nouveau_gpuobj **pgpuobj)
+gf110_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
+ struct nvkm_gpuobj **pgpuobj)
{
- struct nvd0_dmaobj_priv *priv = (void *)dmaobj;
+ struct gf110_dmaobj_priv *priv = (void *)dmaobj;
int ret;
if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
@@ -64,7 +61,7 @@ nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
} else
return 0;
- ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
+ ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
if (ret == 0) {
nv_wo32(*pgpuobj, 0x00, priv->flags0);
nv_wo32(*pgpuobj, 0x04, priv->base.start >> 8);
@@ -78,15 +75,15 @@ nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
}
static int
-nvd0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf110_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_dmaeng *dmaeng = (void *)engine;
+ struct nvkm_dmaeng *dmaeng = (void *)engine;
union {
struct gf110_dma_v0 v0;
} *args;
- struct nvd0_dmaobj_priv *priv;
+ struct gf110_dmaobj_priv *priv;
u32 kind, page;
int ret;
@@ -138,31 +135,31 @@ nvd0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
}
-static struct nouveau_ofuncs
-nvd0_dmaobj_ofuncs = {
- .ctor = nvd0_dmaobj_ctor,
+static struct nvkm_ofuncs
+gf110_dmaobj_ofuncs = {
+ .ctor = gf110_dmaobj_ctor,
.dtor = _nvkm_dmaobj_dtor,
.init = _nvkm_dmaobj_init,
.fini = _nvkm_dmaobj_fini,
};
-static struct nouveau_oclass
-nvd0_dmaeng_sclass[] = {
- { NV_DMA_FROM_MEMORY, &nvd0_dmaobj_ofuncs },
- { NV_DMA_TO_MEMORY, &nvd0_dmaobj_ofuncs },
- { NV_DMA_IN_MEMORY, &nvd0_dmaobj_ofuncs },
+static struct nvkm_oclass
+gf110_dmaeng_sclass[] = {
+ { NV_DMA_FROM_MEMORY, &gf110_dmaobj_ofuncs },
+ { NV_DMA_TO_MEMORY, &gf110_dmaobj_ofuncs },
+ { NV_DMA_IN_MEMORY, &gf110_dmaobj_ofuncs },
{}
};
-struct nouveau_oclass *
-nvd0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
+struct nvkm_oclass *
+gf110_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
.base.handle = NV_ENGINE(DMAOBJ, 0xd0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_dmaeng_ctor,
.dtor = _nvkm_dmaeng_dtor,
.init = _nvkm_dmaeng_init,
.fini = _nvkm_dmaeng_fini,
},
- .sclass = nvd0_dmaeng_sclass,
- .bind = nvd0_dmaobj_bind,
+ .sclass = gf110_dmaeng_sclass,
+ .bind = gf110_dmaobj_bind,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
index 8089310f1157..b4379c2a2fb5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
@@ -21,29 +21,27 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <core/gpuobj.h>
-#include <nvif/class.h>
-
#include <subdev/fb.h>
#include <subdev/mmu/nv04.h>
-#include "priv.h"
+#include <nvif/class.h>
struct nv04_dmaobj_priv {
- struct nouveau_dmaobj base;
+ struct nvkm_dmaobj base;
bool clone;
u32 flags0;
u32 flags2;
};
static int
-nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
- struct nouveau_object *parent,
- struct nouveau_gpuobj **pgpuobj)
+nv04_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
+ struct nvkm_gpuobj **pgpuobj)
{
struct nv04_dmaobj_priv *priv = (void *)dmaobj;
- struct nouveau_gpuobj *gpuobj;
+ struct nvkm_gpuobj *gpuobj;
u64 offset = priv->base.start & 0xfffff000;
u64 adjust = priv->base.start & 0x00000fff;
u32 length = priv->base.limit - priv->base.start;
@@ -63,14 +61,14 @@ nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
if (priv->clone) {
struct nv04_mmu_priv *mmu = nv04_mmu(dmaobj);
- struct nouveau_gpuobj *pgt = mmu->vm->pgt[0].obj[0];
+ struct nvkm_gpuobj *pgt = mmu->vm->pgt[0].obj[0];
if (!dmaobj->start)
- return nouveau_gpuobj_dup(parent, pgt, pgpuobj);
+ return nvkm_gpuobj_dup(parent, pgt, pgpuobj);
offset = nv_ro32(pgt, 8 + (offset >> 10));
offset &= 0xfffff000;
}
- ret = nouveau_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj);
+ ret = nvkm_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj);
*pgpuobj = gpuobj;
if (ret == 0) {
nv_wo32(*pgpuobj, 0x00, priv->flags0 | (adjust << 20));
@@ -83,11 +81,11 @@ nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
}
static int
-nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_dmaeng *dmaeng = (void *)engine;
+ struct nvkm_dmaeng *dmaeng = (void *)engine;
struct nv04_mmu_priv *mmu = nv04_mmu(engine);
struct nv04_dmaobj_priv *priv;
int ret;
@@ -135,7 +133,7 @@ nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
nv04_dmaobj_ofuncs = {
.ctor = nv04_dmaobj_ctor,
.dtor = _nvkm_dmaobj_dtor,
@@ -143,7 +141,7 @@ nv04_dmaobj_ofuncs = {
.fini = _nvkm_dmaobj_fini,
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv04_dmaeng_sclass[] = {
{ NV_DMA_FROM_MEMORY, &nv04_dmaobj_ofuncs },
{ NV_DMA_TO_MEMORY, &nv04_dmaobj_ofuncs },
@@ -151,10 +149,10 @@ nv04_dmaeng_sclass[] = {
{}
};
-struct nouveau_oclass *
+struct nvkm_oclass *
nv04_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
.base.handle = NV_ENGINE(DMAOBJ, 0x04),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_dmaeng_ctor,
.dtor = _nvkm_dmaeng_dtor,
.init = _nvkm_dmaeng_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c
index a740ddba2ee2..4d3c828fe0e6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c
@@ -21,26 +21,24 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <core/client.h>
#include <core/gpuobj.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
#include <subdev/fb.h>
-#include "priv.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
struct nv50_dmaobj_priv {
- struct nouveau_dmaobj base;
+ struct nvkm_dmaobj base;
u32 flags0;
u32 flags5;
};
static int
-nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
- struct nouveau_object *parent,
- struct nouveau_gpuobj **pgpuobj)
+nv50_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
+ struct nvkm_gpuobj **pgpuobj)
{
struct nv50_dmaobj_priv *priv = (void *)dmaobj;
int ret;
@@ -69,7 +67,7 @@ nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
}
}
- ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
+ ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
if (ret == 0) {
nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
@@ -84,11 +82,11 @@ nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
}
static int
-nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_dmaeng *dmaeng = (void *)engine;
+ struct nvkm_dmaeng *dmaeng = (void *)engine;
union {
struct nv50_dma_v0 v0;
} *args;
@@ -167,7 +165,7 @@ nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
nv50_dmaobj_ofuncs = {
.ctor = nv50_dmaobj_ctor,
.dtor = _nvkm_dmaobj_dtor,
@@ -175,7 +173,7 @@ nv50_dmaobj_ofuncs = {
.fini = _nvkm_dmaobj_fini,
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv50_dmaeng_sclass[] = {
{ NV_DMA_FROM_MEMORY, &nv50_dmaobj_ofuncs },
{ NV_DMA_TO_MEMORY, &nv50_dmaobj_ofuncs },
@@ -183,10 +181,10 @@ nv50_dmaeng_sclass[] = {
{}
};
-struct nouveau_oclass *
+struct nvkm_oclass *
nv50_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
.base.handle = NV_ENGINE(DMAOBJ, 0x50),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_dmaeng_ctor,
.dtor = _nvkm_dmaeng_dtor,
.init = _nvkm_dmaeng_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h
index 36f743866937..44ae8a0ca65c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h
@@ -1,30 +1,28 @@
#ifndef __NVKM_DMAOBJ_PRIV_H__
#define __NVKM_DMAOBJ_PRIV_H__
-
#include <engine/dmaobj.h>
#define nvkm_dmaobj_create(p,e,c,pa,sa,d) \
nvkm_dmaobj_create_((p), (e), (c), (pa), (sa), sizeof(**d), (void **)d)
-int nvkm_dmaobj_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void **, u32 *,
+int nvkm_dmaobj_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void **, u32 *,
int, void **);
-#define _nvkm_dmaobj_dtor nouveau_object_destroy
-#define _nvkm_dmaobj_init nouveau_object_init
-#define _nvkm_dmaobj_fini nouveau_object_fini
+#define _nvkm_dmaobj_dtor nvkm_object_destroy
+#define _nvkm_dmaobj_init nvkm_object_init
+#define _nvkm_dmaobj_fini nvkm_object_fini
-int _nvkm_dmaeng_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-#define _nvkm_dmaeng_dtor _nouveau_engine_dtor
-#define _nvkm_dmaeng_init _nouveau_engine_init
-#define _nvkm_dmaeng_fini _nouveau_engine_fini
+int _nvkm_dmaeng_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+#define _nvkm_dmaeng_dtor _nvkm_engine_dtor
+#define _nvkm_dmaeng_init _nvkm_engine_init
+#define _nvkm_dmaeng_fini _nvkm_engine_fini
struct nvkm_dmaeng_impl {
- struct nouveau_oclass base;
- struct nouveau_oclass *sclass;
- int (*bind)(struct nouveau_dmaobj *, struct nouveau_object *,
- struct nouveau_gpuobj **);
+ struct nvkm_oclass base;
+ struct nvkm_oclass *sclass;
+ int (*bind)(struct nvkm_dmaobj *, struct nvkm_object *,
+ struct nvkm_gpuobj **);
};
-
#endif
From 05c7145dae17a53b030238f477bf28211a21b736 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:28:47 +1000
Subject: [PATCH 75/86] drm/nouveau/fifo: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 2 +
.../drm/nouveau/include/nvkm/engine/fifo.h | 162 +++----
.../drm/nouveau/nvkm/engine/device/gm100.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 26 +-
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 +-
.../gpu/drm/nouveau/nvkm/engine/fifo/Kbuild | 8 +-
.../gpu/drm/nouveau/nvkm/engine/fifo/base.c | 115 +++--
.../nvkm/engine/fifo/{nv84.c => g84.c} | 279 ++++++-----
.../nvkm/engine/fifo/{nvc0.c => gf100.c} | 433 ++++++++---------
.../nvkm/engine/fifo/{nve0.c => gk104.c} | 456 +++++++++---------
.../gpu/drm/nouveau/nvkm/engine/fifo/gk104.h | 16 +
.../nvkm/engine/fifo/{nv108.c => gk208.c} | 17 +-
.../gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c | 17 +-
.../gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 167 +++----
.../gpu/drm/nouveau/nvkm/engine/fifo/nv04.h | 39 +-
.../gpu/drm/nouveau/nvkm/engine/fifo/nv10.c | 77 ++-
.../gpu/drm/nouveau/nvkm/engine/fifo/nv17.c | 85 ++--
.../gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 98 ++--
.../gpu/drm/nouveau/nvkm/engine/fifo/nv50.c | 219 ++++-----
.../gpu/drm/nouveau/nvkm/engine/fifo/nv50.h | 34 +-
.../gpu/drm/nouveau/nvkm/engine/fifo/nve0.h | 18 -
22 files changed, 1121 insertions(+), 1183 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/fifo/{nv84.c => g84.c} (61%)
rename drivers/gpu/drm/nouveau/nvkm/engine/fifo/{nvc0.c => gf100.c} (64%)
rename drivers/gpu/drm/nouveau/nvkm/engine/fifo/{nve0.c => gk104.c} (67%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
rename drivers/gpu/drm/nouveau/nvkm/engine/fifo/{nv108.c => gk208.c} (83%)
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.h
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index e81d40c221b5..9d6990aa5b47 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -248,5 +248,7 @@
#define nouveau_dmaeng nvkm_dmaeng
#define nouveau_dmaobj nvkm_dmaobj
#define nouveau_disp nvkm_disp
+#define nouveau_fifo_chan nvkm_fifo_chan
+#define nouveau_fifo nvkm_fifo
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
index 27f05de8fd0a..05321ce7ab15 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
@@ -1,15 +1,11 @@
-#ifndef __NOUVEAU_FIFO_H__
-#define __NOUVEAU_FIFO_H__
-
+#ifndef __NVKM_FIFO_H__
+#define __NVKM_FIFO_H__
#include <core/namedb.h>
-#include <core/gpuobj.h>
-#include <core/engine.h>
-#include <core/event.h>
-struct nouveau_fifo_chan {
- struct nouveau_namedb namedb;
- struct nouveau_dmaobj *pushdma;
- struct nouveau_gpuobj *pushgpu;
+struct nvkm_fifo_chan {
+ struct nvkm_namedb namedb;
+ struct nvkm_dmaobj *pushdma;
+ struct nvkm_gpuobj *pushgpu;
void __iomem *user;
u64 addr;
u32 size;
@@ -17,110 +13,114 @@ struct nouveau_fifo_chan {
atomic_t refcnt; /* NV04_NVSW_SET_REF */
};
-static inline struct nouveau_fifo_chan *
-nouveau_fifo_chan(void *obj)
+static inline struct nvkm_fifo_chan *
+nvkm_fifo_chan(void *obj)
{
return (void *)nv_namedb(obj);
}
-#define nouveau_fifo_channel_create(p,e,c,b,a,s,n,m,d) \
- nouveau_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \
+#define nvkm_fifo_channel_create(p,e,c,b,a,s,n,m,d) \
+ nvkm_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \
(m), sizeof(**d), (void **)d)
-#define nouveau_fifo_channel_init(p) \
- nouveau_namedb_init(&(p)->namedb)
-#define nouveau_fifo_channel_fini(p,s) \
- nouveau_namedb_fini(&(p)->namedb, (s))
+#define nvkm_fifo_channel_init(p) \
+ nvkm_namedb_init(&(p)->namedb)
+#define nvkm_fifo_channel_fini(p,s) \
+ nvkm_namedb_fini(&(p)->namedb, (s))
-int nouveau_fifo_channel_create_(struct nouveau_object *,
- struct nouveau_object *,
- struct nouveau_oclass *,
+int nvkm_fifo_channel_create_(struct nvkm_object *,
+ struct nvkm_object *,
+ struct nvkm_oclass *,
int bar, u32 addr, u32 size, u32 push,
u64 engmask, int len, void **);
-void nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *);
+void nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *);
-#define _nouveau_fifo_channel_init _nouveau_namedb_init
-#define _nouveau_fifo_channel_fini _nouveau_namedb_fini
+#define _nvkm_fifo_channel_init _nvkm_namedb_init
+#define _nvkm_fifo_channel_fini _nvkm_namedb_fini
-void _nouveau_fifo_channel_dtor(struct nouveau_object *);
-int _nouveau_fifo_channel_map(struct nouveau_object *, u64 *, u32 *);
-u32 _nouveau_fifo_channel_rd32(struct nouveau_object *, u64);
-void _nouveau_fifo_channel_wr32(struct nouveau_object *, u64, u32);
-int _nouveau_fifo_channel_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
+void _nvkm_fifo_channel_dtor(struct nvkm_object *);
+int _nvkm_fifo_channel_map(struct nvkm_object *, u64 *, u32 *);
+u32 _nvkm_fifo_channel_rd32(struct nvkm_object *, u64);
+void _nvkm_fifo_channel_wr32(struct nvkm_object *, u64, u32);
+int _nvkm_fifo_channel_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
-struct nouveau_fifo_base {
- struct nouveau_gpuobj gpuobj;
+#include <core/gpuobj.h>
+
+struct nvkm_fifo_base {
+ struct nvkm_gpuobj gpuobj;
};
-#define nouveau_fifo_context_create(p,e,c,g,s,a,f,d) \
- nouveau_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d))
-#define nouveau_fifo_context_destroy(p) \
- nouveau_gpuobj_destroy(&(p)->gpuobj)
-#define nouveau_fifo_context_init(p) \
- nouveau_gpuobj_init(&(p)->gpuobj)
-#define nouveau_fifo_context_fini(p,s) \
- nouveau_gpuobj_fini(&(p)->gpuobj, (s))
+#define nvkm_fifo_context_create(p,e,c,g,s,a,f,d) \
+ nvkm_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d))
+#define nvkm_fifo_context_destroy(p) \
+ nvkm_gpuobj_destroy(&(p)->gpuobj)
+#define nvkm_fifo_context_init(p) \
+ nvkm_gpuobj_init(&(p)->gpuobj)
+#define nvkm_fifo_context_fini(p,s) \
+ nvkm_gpuobj_fini(&(p)->gpuobj, (s))
-#define _nouveau_fifo_context_dtor _nouveau_gpuobj_dtor
-#define _nouveau_fifo_context_init _nouveau_gpuobj_init
-#define _nouveau_fifo_context_fini _nouveau_gpuobj_fini
-#define _nouveau_fifo_context_rd32 _nouveau_gpuobj_rd32
-#define _nouveau_fifo_context_wr32 _nouveau_gpuobj_wr32
+#define _nvkm_fifo_context_dtor _nvkm_gpuobj_dtor
+#define _nvkm_fifo_context_init _nvkm_gpuobj_init
+#define _nvkm_fifo_context_fini _nvkm_gpuobj_fini
+#define _nvkm_fifo_context_rd32 _nvkm_gpuobj_rd32
+#define _nvkm_fifo_context_wr32 _nvkm_gpuobj_wr32
-struct nouveau_fifo {
- struct nouveau_engine base;
+#include <core/engine.h>
+#include <core/event.h>
+
+struct nvkm_fifo {
+ struct nvkm_engine base;
struct nvkm_event cevent; /* channel creation event */
struct nvkm_event uevent; /* async user trigger */
- struct nouveau_object **channel;
+ struct nvkm_object **channel;
spinlock_t lock;
u16 min;
u16 max;
- int (*chid)(struct nouveau_fifo *, struct nouveau_object *);
- void (*pause)(struct nouveau_fifo *, unsigned long *);
- void (*start)(struct nouveau_fifo *, unsigned long *);
+ int (*chid)(struct nvkm_fifo *, struct nvkm_object *);
+ void (*pause)(struct nvkm_fifo *, unsigned long *);
+ void (*start)(struct nvkm_fifo *, unsigned long *);
};
-static inline struct nouveau_fifo *
-nouveau_fifo(void *obj)
+static inline struct nvkm_fifo *
+nvkm_fifo(void *obj)
{
- return (void *)nouveau_engine(obj, NVDEV_ENGINE_FIFO);
+ return (void *)nvkm_engine(obj, NVDEV_ENGINE_FIFO);
}
-#define nouveau_fifo_create(o,e,c,fc,lc,d) \
- nouveau_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d)
-#define nouveau_fifo_init(p) \
- nouveau_engine_init(&(p)->base)
-#define nouveau_fifo_fini(p,s) \
- nouveau_engine_fini(&(p)->base, (s))
+#define nvkm_fifo_create(o,e,c,fc,lc,d) \
+ nvkm_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d)
+#define nvkm_fifo_init(p) \
+ nvkm_engine_init(&(p)->base)
+#define nvkm_fifo_fini(p,s) \
+ nvkm_engine_fini(&(p)->base, (s))
-int nouveau_fifo_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int min, int max,
+int nvkm_fifo_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int min, int max,
int size, void **);
-void nouveau_fifo_destroy(struct nouveau_fifo *);
+void nvkm_fifo_destroy(struct nvkm_fifo *);
const char *
-nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid);
+nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid);
-#define _nouveau_fifo_init _nouveau_engine_init
-#define _nouveau_fifo_fini _nouveau_engine_fini
+#define _nvkm_fifo_init _nvkm_engine_init
+#define _nvkm_fifo_fini _nvkm_engine_fini
-extern struct nouveau_oclass *nv04_fifo_oclass;
-extern struct nouveau_oclass *nv10_fifo_oclass;
-extern struct nouveau_oclass *nv17_fifo_oclass;
-extern struct nouveau_oclass *nv40_fifo_oclass;
-extern struct nouveau_oclass *nv50_fifo_oclass;
-extern struct nouveau_oclass *nv84_fifo_oclass;
-extern struct nouveau_oclass *nvc0_fifo_oclass;
-extern struct nouveau_oclass *nve0_fifo_oclass;
-extern struct nouveau_oclass *gk20a_fifo_oclass;
-extern struct nouveau_oclass *nv108_fifo_oclass;
+extern struct nvkm_oclass *nv04_fifo_oclass;
+extern struct nvkm_oclass *nv10_fifo_oclass;
+extern struct nvkm_oclass *nv17_fifo_oclass;
+extern struct nvkm_oclass *nv40_fifo_oclass;
+extern struct nvkm_oclass *nv50_fifo_oclass;
+extern struct nvkm_oclass *g84_fifo_oclass;
+extern struct nvkm_oclass *gf100_fifo_oclass;
+extern struct nvkm_oclass *gk104_fifo_oclass;
+extern struct nvkm_oclass *gk20a_fifo_oclass;
+extern struct nvkm_oclass *gk208_fifo_oclass;
-int nouveau_fifo_uevent_ctor(struct nouveau_object *, void *, u32,
- struct nvkm_notify *);
-void nouveau_fifo_uevent(struct nouveau_fifo *);
-
-void nv04_fifo_intr(struct nouveau_subdev *);
-int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *);
+int nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32,
+ struct nvkm_notify *);
+void nvkm_fifo_uevent(struct nvkm_fifo *);
+void nv04_fifo_intr(struct nvkm_subdev *);
+int nv04_fifo_context_attach(struct nvkm_object *, struct nvkm_object *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 1d851d61f982..bcdc5bdd10cf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -84,7 +84,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
@@ -128,7 +128,7 @@ gm100_identify(struct nouveau_device *device)
#endif
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
#if 0
- device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index e4baae226379..f48fd5a22f26 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -106,7 +106,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -135,7 +135,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -164,7 +164,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -193,7 +193,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -222,7 +222,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -251,7 +251,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
@@ -280,7 +280,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -309,7 +309,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
@@ -338,7 +338,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
@@ -368,7 +368,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
@@ -399,7 +399,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
@@ -429,7 +429,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
@@ -459,7 +459,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 9a4e062656ac..3ebf7172835b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -81,7 +81,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -114,7 +114,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -147,7 +147,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -179,7 +179,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -212,7 +212,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -244,7 +244,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -276,7 +276,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -309,7 +309,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
@@ -339,7 +339,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 91aea039bfb1..cc06a67bbeac 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -81,7 +81,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
@@ -115,7 +115,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
@@ -149,7 +149,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
@@ -205,7 +205,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
@@ -239,7 +239,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
@@ -273,7 +273,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
@@ -306,7 +306,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
- device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
+ device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
index f38820faf44f..c5a2d8718c5b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
@@ -4,8 +4,8 @@ nvkm-y += nvkm/engine/fifo/nv10.o
nvkm-y += nvkm/engine/fifo/nv17.o
nvkm-y += nvkm/engine/fifo/nv40.o
nvkm-y += nvkm/engine/fifo/nv50.o
-nvkm-y += nvkm/engine/fifo/nv84.o
-nvkm-y += nvkm/engine/fifo/nvc0.o
-nvkm-y += nvkm/engine/fifo/nve0.o
+nvkm-y += nvkm/engine/fifo/g84.o
+nvkm-y += nvkm/engine/fifo/gf100.o
+nvkm-y += nvkm/engine/fifo/gk104.o
nvkm-y += nvkm/engine/fifo/gk20a.o
-nvkm-y += nvkm/engine/fifo/nv108.o
+nvkm-y += nvkm/engine/fifo/gk208.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
index 7e54a521bc05..fa223f88d25e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
@@ -21,23 +21,21 @@
*
* Authors: Ben Skeggs
*/
+#include <engine/fifo.h>
#include <core/client.h>
#include <core/device.h>
-#include <core/notify.h>
-#include <core/object.h>
#include <core/handle.h>
-#include <core/event.h>
-#include <nvif/unpack.h>
+#include <core/notify.h>
+#include <engine/dmaobj.h>
+
#include <nvif/class.h>
#include <nvif/event.h>
-
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
+#include <nvif/unpack.h>
static int
-nouveau_fifo_event_ctor(struct nouveau_object *object, void *data, u32 size,
- struct nvkm_notify *notify)
+nvkm_fifo_event_ctor(struct nvkm_object *object, void *data, u32 size,
+ struct nvkm_notify *notify)
{
if (size == 0) {
notify->size = 0;
@@ -49,33 +47,33 @@ nouveau_fifo_event_ctor(struct nouveau_object *object, void *data, u32 size,
}
static const struct nvkm_event_func
-nouveau_fifo_event_func = {
- .ctor = nouveau_fifo_event_ctor,
+nvkm_fifo_event_func = {
+ .ctor = nvkm_fifo_event_ctor,
};
int
-nouveau_fifo_channel_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass,
- int bar, u32 addr, u32 size, u32 pushbuf,
- u64 engmask, int len, void **ptr)
+nvkm_fifo_channel_create_(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass,
+ int bar, u32 addr, u32 size, u32 pushbuf,
+ u64 engmask, int len, void **ptr)
{
- struct nouveau_device *device = nv_device(engine);
- struct nouveau_fifo *priv = (void *)engine;
- struct nouveau_fifo_chan *chan;
- struct nouveau_dmaeng *dmaeng;
+ struct nvkm_device *device = nv_device(engine);
+ struct nvkm_fifo *priv = (void *)engine;
+ struct nvkm_fifo_chan *chan;
+ struct nvkm_dmaeng *dmaeng;
unsigned long flags;
int ret;
/* create base object class */
- ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL,
- engmask, len, ptr);
+ ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL,
+ engmask, len, ptr);
chan = *ptr;
if (ret)
return ret;
/* validate dma object representing push buffer */
- chan->pushdma = (void *)nouveau_handle_ref(parent, pushbuf);
+ chan->pushdma = (void *)nvkm_handle_ref(parent, pushbuf);
if (!chan->pushdma)
return -ENOENT;
@@ -115,9 +113,9 @@ nouveau_fifo_channel_create_(struct nouveau_object *parent,
}
void
-nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *chan)
+nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *chan)
{
- struct nouveau_fifo *priv = (void *)nv_object(chan)->engine;
+ struct nvkm_fifo *priv = (void *)nv_object(chan)->engine;
unsigned long flags;
if (chan->user)
@@ -127,31 +125,31 @@ nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *chan)
priv->channel[chan->chid] = NULL;
spin_unlock_irqrestore(&priv->lock, flags);
- nouveau_gpuobj_ref(NULL, &chan->pushgpu);
- nouveau_object_ref(NULL, (struct nouveau_object **)&chan->pushdma);
- nouveau_namedb_destroy(&chan->namedb);
+ nvkm_gpuobj_ref(NULL, &chan->pushgpu);
+ nvkm_object_ref(NULL, (struct nvkm_object **)&chan->pushdma);
+ nvkm_namedb_destroy(&chan->namedb);
}
void
-_nouveau_fifo_channel_dtor(struct nouveau_object *object)
+_nvkm_fifo_channel_dtor(struct nvkm_object *object)
{
- struct nouveau_fifo_chan *chan = (void *)object;
- nouveau_fifo_channel_destroy(chan);
+ struct nvkm_fifo_chan *chan = (void *)object;
+ nvkm_fifo_channel_destroy(chan);
}
int
-_nouveau_fifo_channel_map(struct nouveau_object *object, u64 *addr, u32 *size)
+_nvkm_fifo_channel_map(struct nvkm_object *object, u64 *addr, u32 *size)
{
- struct nouveau_fifo_chan *chan = (void *)object;
+ struct nvkm_fifo_chan *chan = (void *)object;
*addr = chan->addr;
*size = chan->size;
return 0;
}
u32
-_nouveau_fifo_channel_rd32(struct nouveau_object *object, u64 addr)
+_nvkm_fifo_channel_rd32(struct nvkm_object *object, u64 addr)
{
- struct nouveau_fifo_chan *chan = (void *)object;
+ struct nvkm_fifo_chan *chan = (void *)object;
if (unlikely(!chan->user)) {
chan->user = ioremap(chan->addr, chan->size);
if (WARN_ON_ONCE(chan->user == NULL))
@@ -161,9 +159,9 @@ _nouveau_fifo_channel_rd32(struct nouveau_object *object, u64 addr)
}
void
-_nouveau_fifo_channel_wr32(struct nouveau_object *object, u64 addr, u32 data)
+_nvkm_fifo_channel_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
- struct nouveau_fifo_chan *chan = (void *)object;
+ struct nvkm_fifo_chan *chan = (void *)object;
if (unlikely(!chan->user)) {
chan->user = ioremap(chan->addr, chan->size);
if (WARN_ON_ONCE(chan->user == NULL))
@@ -173,8 +171,8 @@ _nouveau_fifo_channel_wr32(struct nouveau_object *object, u64 addr, u32 data)
}
int
-nouveau_fifo_uevent_ctor(struct nouveau_object *object, void *data, u32 size,
- struct nvkm_notify *notify)
+nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size,
+ struct nvkm_notify *notify)
{
union {
struct nvif_notify_uevent_req none;
@@ -191,7 +189,7 @@ nouveau_fifo_uevent_ctor(struct nouveau_object *object, void *data, u32 size,
}
void
-nouveau_fifo_uevent(struct nouveau_fifo *fifo)
+nvkm_fifo_uevent(struct nvkm_fifo *fifo)
{
struct nvif_notify_uevent_rep rep = {
};
@@ -199,10 +197,10 @@ nouveau_fifo_uevent(struct nouveau_fifo *fifo)
}
int
-_nouveau_fifo_channel_ntfy(struct nouveau_object *object, u32 type,
- struct nvkm_event **event)
+_nvkm_fifo_channel_ntfy(struct nvkm_object *object, u32 type,
+ struct nvkm_event **event)
{
- struct nouveau_fifo *fifo = (void *)object->engine;
+ struct nvkm_fifo *fifo = (void *)object->engine;
switch (type) {
case G82_CHANNEL_DMA_V0_NTFY_UEVENT:
if (nv_mclass(object) >= G82_CHANNEL_DMA) {
@@ -217,14 +215,14 @@ _nouveau_fifo_channel_ntfy(struct nouveau_object *object, u32 type,
}
static int
-nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object)
+nvkm_fifo_chid(struct nvkm_fifo *priv, struct nvkm_object *object)
{
int engidx = nv_hclass(priv) & 0xff;
while (object && object->parent) {
if ( nv_iclass(object->parent, NV_ENGCTX_CLASS) &&
(nv_hclass(object->parent) & 0xff) == engidx)
- return nouveau_fifo_chan(object)->chid;
+ return nvkm_fifo_chan(object)->chid;
object = object->parent;
}
@@ -232,9 +230,9 @@ nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object)
}
const char *
-nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid)
+nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid)
{
- struct nouveau_fifo_chan *chan = NULL;
+ struct nvkm_fifo_chan *chan = NULL;
unsigned long flags;
spin_lock_irqsave(&fifo->lock, flags);
@@ -242,29 +240,28 @@ nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid)
chan = (void *)fifo->channel[chid];
spin_unlock_irqrestore(&fifo->lock, flags);
- return nouveau_client_name(chan);
+ return nvkm_client_name(chan);
}
void
-nouveau_fifo_destroy(struct nouveau_fifo *priv)
+nvkm_fifo_destroy(struct nvkm_fifo *priv)
{
kfree(priv->channel);
nvkm_event_fini(&priv->uevent);
nvkm_event_fini(&priv->cevent);
- nouveau_engine_destroy(&priv->base);
+ nvkm_engine_destroy(&priv->base);
}
int
-nouveau_fifo_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass,
- int min, int max, int length, void **pobject)
+nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass,
+ int min, int max, int length, void **pobject)
{
- struct nouveau_fifo *priv;
+ struct nvkm_fifo *priv;
int ret;
- ret = nouveau_engine_create_(parent, engine, oclass, true, "PFIFO",
- "fifo", length, pobject);
+ ret = nvkm_engine_create_(parent, engine, oclass, true, "PFIFO",
+ "fifo", length, pobject);
priv = *pobject;
if (ret)
return ret;
@@ -275,11 +272,11 @@ nouveau_fifo_create_(struct nouveau_object *parent,
if (!priv->channel)
return -ENOMEM;
- ret = nvkm_event_init(&nouveau_fifo_event_func, 1, 1, &priv->cevent);
+ ret = nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &priv->cevent);
if (ret)
return ret;
- priv->chid = nouveau_fifo_chid;
+ priv->chid = nvkm_fifo_chid;
spin_lock_init(&priv->lock);
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
similarity index 61%
rename from drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
index 727358d8ac77..a04920b3cf84 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
@@ -21,35 +21,29 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
+#include "nv04.h"
-#include <core/os.h>
#include <core/client.h>
#include <core/engctx.h>
#include <core/ramht.h>
-#include <core/event.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/timer.h>
#include <subdev/bar.h>
+#include <subdev/mmu.h>
+#include <subdev/timer.h>
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-
-#include "nv04.h"
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
/*******************************************************************************
* FIFO channel objects
******************************************************************************/
static int
-nv84_fifo_context_attach(struct nouveau_object *parent,
- struct nouveau_object *object)
+g84_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object)
{
- struct nouveau_bar *bar = nouveau_bar(parent);
+ struct nvkm_bar *bar = nvkm_bar(parent);
struct nv50_fifo_base *base = (void *)parent->parent;
- struct nouveau_gpuobj *ectx = (void *)object;
+ struct nvkm_gpuobj *ectx = (void *)object;
u64 limit = ectx->addr + ectx->size - 1;
u64 start = ectx->addr;
u32 addr;
@@ -83,10 +77,10 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
}
static int
-nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
- struct nouveau_object *object)
+g84_fifo_context_detach(struct nvkm_object *parent, bool suspend,
+ struct nvkm_object *object)
{
- struct nouveau_bar *bar = nouveau_bar(parent);
+ struct nvkm_bar *bar = nvkm_bar(parent);
struct nv50_fifo_priv *priv = (void *)parent->engine;
struct nv50_fifo_base *base = (void *)parent->parent;
struct nv50_fifo_chan *chan = (void *)parent;
@@ -115,7 +109,7 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
nv_wr32(priv, 0x002520, save);
if (!done) {
nv_error(priv, "channel %d [%s] unload timeout\n",
- chan->base.chid, nouveau_client_name(chan));
+ chan->base.chid, nvkm_client_name(chan));
if (suspend)
return -EBUSY;
}
@@ -131,8 +125,8 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
}
static int
-nv84_fifo_object_attach(struct nouveau_object *parent,
- struct nouveau_object *object, u32 handle)
+g84_fifo_object_attach(struct nvkm_object *parent,
+ struct nvkm_object *object, u32 handle)
{
struct nv50_fifo_chan *chan = (void *)parent;
u32 context;
@@ -161,19 +155,18 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
return -EINVAL;
}
- return nouveau_ramht_insert(chan->ramht, 0, handle, context);
+ return nvkm_ramht_insert(chan->ramht, 0, handle, context);
}
static int
-nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv03_channel_dma_v0 v0;
} *args = data;
- struct nouveau_bar *bar = nouveau_bar(parent);
+ struct nvkm_bar *bar = nvkm_bar(parent);
struct nv50_fifo_base *base = (void *)parent;
struct nv50_fifo_chan *chan;
int ret;
@@ -186,36 +179,36 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
} else
return ret;
- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
- 0x2000, args->v0.pushbuf,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_MPEG) |
- (1ULL << NVDEV_ENGINE_ME) |
- (1ULL << NVDEV_ENGINE_VP) |
- (1ULL << NVDEV_ENGINE_CIPHER) |
- (1ULL << NVDEV_ENGINE_SEC) |
- (1ULL << NVDEV_ENGINE_BSP) |
- (1ULL << NVDEV_ENGINE_MSVLD) |
- (1ULL << NVDEV_ENGINE_MSPDEC) |
- (1ULL << NVDEV_ENGINE_MSPPP) |
- (1ULL << NVDEV_ENGINE_CE0) |
- (1ULL << NVDEV_ENGINE_VIC), &chan);
+ ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
+ 0x2000, args->v0.pushbuf,
+ (1ULL << NVDEV_ENGINE_DMAOBJ) |
+ (1ULL << NVDEV_ENGINE_SW) |
+ (1ULL << NVDEV_ENGINE_GR) |
+ (1ULL << NVDEV_ENGINE_MPEG) |
+ (1ULL << NVDEV_ENGINE_ME) |
+ (1ULL << NVDEV_ENGINE_VP) |
+ (1ULL << NVDEV_ENGINE_CIPHER) |
+ (1ULL << NVDEV_ENGINE_SEC) |
+ (1ULL << NVDEV_ENGINE_BSP) |
+ (1ULL << NVDEV_ENGINE_MSVLD) |
+ (1ULL << NVDEV_ENGINE_MSPDEC) |
+ (1ULL << NVDEV_ENGINE_MSPPP) |
+ (1ULL << NVDEV_ENGINE_CE0) |
+ (1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
args->v0.chid = chan->base.chid;
- ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
- &chan->ramht);
+ ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
+ &chan->ramht);
if (ret)
return ret;
- nv_parent(chan)->context_attach = nv84_fifo_context_attach;
- nv_parent(chan)->context_detach = nv84_fifo_context_detach;
- nv_parent(chan)->object_attach = nv84_fifo_object_attach;
+ nv_parent(chan)->context_attach = g84_fifo_context_attach;
+ nv_parent(chan)->context_detach = g84_fifo_context_detach;
+ nv_parent(chan)->object_attach = g84_fifo_object_attach;
nv_parent(chan)->object_detach = nv50_fifo_object_detach;
nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset));
@@ -239,15 +232,14 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
}
static int
-nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv50_channel_gpfifo_v0 v0;
} *args = data;
- struct nouveau_bar *bar = nouveau_bar(parent);
+ struct nvkm_bar *bar = nvkm_bar(parent);
struct nv50_fifo_base *base = (void *)parent;
struct nv50_fifo_chan *chan;
u64 ioffset, ilength;
@@ -262,36 +254,36 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
} else
return ret;
- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
- 0x2000, args->v0.pushbuf,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_MPEG) |
- (1ULL << NVDEV_ENGINE_ME) |
- (1ULL << NVDEV_ENGINE_VP) |
- (1ULL << NVDEV_ENGINE_CIPHER) |
- (1ULL << NVDEV_ENGINE_SEC) |
- (1ULL << NVDEV_ENGINE_BSP) |
- (1ULL << NVDEV_ENGINE_MSVLD) |
- (1ULL << NVDEV_ENGINE_MSPDEC) |
- (1ULL << NVDEV_ENGINE_MSPPP) |
- (1ULL << NVDEV_ENGINE_CE0) |
- (1ULL << NVDEV_ENGINE_VIC), &chan);
+ ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
+ 0x2000, args->v0.pushbuf,
+ (1ULL << NVDEV_ENGINE_DMAOBJ) |
+ (1ULL << NVDEV_ENGINE_SW) |
+ (1ULL << NVDEV_ENGINE_GR) |
+ (1ULL << NVDEV_ENGINE_MPEG) |
+ (1ULL << NVDEV_ENGINE_ME) |
+ (1ULL << NVDEV_ENGINE_VP) |
+ (1ULL << NVDEV_ENGINE_CIPHER) |
+ (1ULL << NVDEV_ENGINE_SEC) |
+ (1ULL << NVDEV_ENGINE_BSP) |
+ (1ULL << NVDEV_ENGINE_MSVLD) |
+ (1ULL << NVDEV_ENGINE_MSPDEC) |
+ (1ULL << NVDEV_ENGINE_MSPPP) |
+ (1ULL << NVDEV_ENGINE_CE0) |
+ (1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
args->v0.chid = chan->base.chid;
- ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
- &chan->ramht);
+ ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
+ &chan->ramht);
if (ret)
return ret;
- nv_parent(chan)->context_attach = nv84_fifo_context_attach;
- nv_parent(chan)->context_detach = nv84_fifo_context_detach;
- nv_parent(chan)->object_attach = nv84_fifo_object_attach;
+ nv_parent(chan)->context_attach = g84_fifo_context_attach;
+ nv_parent(chan)->context_detach = g84_fifo_context_detach;
+ nv_parent(chan)->object_attach = g84_fifo_object_attach;
nv_parent(chan)->object_detach = nv50_fifo_object_detach;
ioffset = args->v0.ioffset;
@@ -315,16 +307,16 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
}
static int
-nv84_fifo_chan_init(struct nouveau_object *object)
+g84_fifo_chan_init(struct nvkm_object *object)
{
struct nv50_fifo_priv *priv = (void *)object->engine;
struct nv50_fifo_base *base = (void *)object->parent;
struct nv50_fifo_chan *chan = (void *)object;
- struct nouveau_gpuobj *ramfc = base->ramfc;
+ struct nvkm_gpuobj *ramfc = base->ramfc;
u32 chid = chan->base.chid;
int ret;
- ret = nouveau_fifo_channel_init(&chan->base);
+ ret = nvkm_fifo_channel_init(&chan->base);
if (ret)
return ret;
@@ -333,34 +325,34 @@ nv84_fifo_chan_init(struct nouveau_object *object)
return 0;
}
-static struct nouveau_ofuncs
-nv84_fifo_ofuncs_dma = {
- .ctor = nv84_fifo_chan_ctor_dma,
+static struct nvkm_ofuncs
+g84_fifo_ofuncs_dma = {
+ .ctor = g84_fifo_chan_ctor_dma,
.dtor = nv50_fifo_chan_dtor,
- .init = nv84_fifo_chan_init,
+ .init = g84_fifo_chan_init,
.fini = nv50_fifo_chan_fini,
- .map = _nouveau_fifo_channel_map,
- .rd32 = _nouveau_fifo_channel_rd32,
- .wr32 = _nouveau_fifo_channel_wr32,
- .ntfy = _nouveau_fifo_channel_ntfy
+ .map = _nvkm_fifo_channel_map,
+ .rd32 = _nvkm_fifo_channel_rd32,
+ .wr32 = _nvkm_fifo_channel_wr32,
+ .ntfy = _nvkm_fifo_channel_ntfy
};
-static struct nouveau_ofuncs
-nv84_fifo_ofuncs_ind = {
- .ctor = nv84_fifo_chan_ctor_ind,
+static struct nvkm_ofuncs
+g84_fifo_ofuncs_ind = {
+ .ctor = g84_fifo_chan_ctor_ind,
.dtor = nv50_fifo_chan_dtor,
- .init = nv84_fifo_chan_init,
+ .init = g84_fifo_chan_init,
.fini = nv50_fifo_chan_fini,
- .map = _nouveau_fifo_channel_map,
- .rd32 = _nouveau_fifo_channel_rd32,
- .wr32 = _nouveau_fifo_channel_wr32,
- .ntfy = _nouveau_fifo_channel_ntfy
+ .map = _nvkm_fifo_channel_map,
+ .rd32 = _nvkm_fifo_channel_rd32,
+ .wr32 = _nvkm_fifo_channel_wr32,
+ .ntfy = _nvkm_fifo_channel_ntfy
};
-static struct nouveau_oclass
-nv84_fifo_sclass[] = {
- { G82_CHANNEL_DMA, &nv84_fifo_ofuncs_dma },
- { G82_CHANNEL_GPFIFO, &nv84_fifo_ofuncs_ind },
+static struct nvkm_oclass
+g84_fifo_sclass[] = {
+ { G82_CHANNEL_DMA, &g84_fifo_ofuncs_dma },
+ { G82_CHANNEL_GPFIFO, &g84_fifo_ofuncs_ind },
{}
};
@@ -369,57 +361,56 @@ nv84_fifo_sclass[] = {
******************************************************************************/
static int
-nv84_fifo_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_fifo_base *base;
int ret;
- ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
- 0x1000, NVOBJ_FLAG_HEAP, &base);
+ ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
+ 0x1000, NVOBJ_FLAG_HEAP, &base);
*pobject = nv_object(base);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0,
- NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
+ ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0,
+ NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0,
- 0, &base->pgd);
+ ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0,
+ 0, &base->pgd);
if (ret)
return ret;
- ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
+ ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1000,
- 0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
+ ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x1000,
+ 0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0100,
- 0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
+ ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0100,
+ 0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
if (ret)
return ret;
return 0;
}
-static struct nouveau_oclass
-nv84_fifo_cclass = {
+static struct nvkm_oclass
+g84_fifo_cclass = {
.handle = NV_ENGCTX(FIFO, 0x84),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv84_fifo_context_ctor,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g84_fifo_context_ctor,
.dtor = nv50_fifo_context_dtor,
- .init = _nouveau_fifo_context_init,
- .fini = _nouveau_fifo_context_fini,
- .rd32 = _nouveau_fifo_context_rd32,
- .wr32 = _nouveau_fifo_context_wr32,
+ .init = _nvkm_fifo_context_init,
+ .fini = _nvkm_fifo_context_fini,
+ .rd32 = _nvkm_fifo_context_rd32,
+ .wr32 = _nvkm_fifo_context_wr32,
},
};
@@ -428,69 +419,69 @@ nv84_fifo_cclass = {
******************************************************************************/
static void
-nv84_fifo_uevent_init(struct nvkm_event *event, int type, int index)
+g84_fifo_uevent_init(struct nvkm_event *event, int type, int index)
{
- struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
+ struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
nv_mask(fifo, 0x002140, 0x40000000, 0x40000000);
}
static void
-nv84_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
+g84_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
{
- struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
+ struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
nv_mask(fifo, 0x002140, 0x40000000, 0x00000000);
}
static const struct nvkm_event_func
-nv84_fifo_uevent_func = {
- .ctor = nouveau_fifo_uevent_ctor,
- .init = nv84_fifo_uevent_init,
- .fini = nv84_fifo_uevent_fini,
+g84_fifo_uevent_func = {
+ .ctor = nvkm_fifo_uevent_ctor,
+ .init = g84_fifo_uevent_init,
+ .fini = g84_fifo_uevent_fini,
};
static int
-nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_fifo_priv *priv;
int ret;
- ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
+ ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
- &priv->playlist[0]);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
+ &priv->playlist[0]);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
- &priv->playlist[1]);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
+ &priv->playlist[1]);
if (ret)
return ret;
- ret = nvkm_event_init(&nv84_fifo_uevent_func, 1, 1, &priv->base.uevent);
+ ret = nvkm_event_init(&g84_fifo_uevent_func, 1, 1, &priv->base.uevent);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000100;
nv_subdev(priv)->intr = nv04_fifo_intr;
- nv_engine(priv)->cclass = &nv84_fifo_cclass;
- nv_engine(priv)->sclass = nv84_fifo_sclass;
+ nv_engine(priv)->cclass = &g84_fifo_cclass;
+ nv_engine(priv)->sclass = g84_fifo_sclass;
priv->base.pause = nv04_fifo_pause;
priv->base.start = nv04_fifo_start;
return 0;
}
-struct nouveau_oclass *
-nv84_fifo_oclass = &(struct nouveau_oclass) {
+struct nvkm_oclass *
+g84_fifo_oclass = &(struct nvkm_oclass) {
.handle = NV_ENGINE(FIFO, 0x84),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv84_fifo_ctor,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g84_fifo_ctor,
.dtor = nv50_fifo_dtor,
.init = nv50_fifo_init,
- .fini = _nouveau_fifo_fini,
+ .fini = _nvkm_fifo_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
similarity index 64%
rename from drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
index 6e05b0b706fa..b745252f2261 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
@@ -21,52 +21,47 @@
*
* Authors: Ben Skeggs
*/
+#include <engine/fifo.h>
#include <core/client.h>
-#include <core/handle.h>
-#include <core/namedb.h>
-#include <core/gpuobj.h>
#include <core/engctx.h>
-#include <core/event.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
#include <core/enum.h>
-
-#include <subdev/timer.h>
+#include <core/handle.h>
#include <subdev/bar.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>
+#include <subdev/timer.h>
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
+#include <nvif/class.h>
+#include <nvif/unpack.h>
-struct nvc0_fifo_priv {
- struct nouveau_fifo base;
+struct gf100_fifo_priv {
+ struct nvkm_fifo base;
struct work_struct fault;
u64 mask;
struct {
- struct nouveau_gpuobj *mem[2];
+ struct nvkm_gpuobj *mem[2];
int active;
wait_queue_head_t wait;
} runlist;
struct {
- struct nouveau_gpuobj *mem;
- struct nouveau_vma bar;
+ struct nvkm_gpuobj *mem;
+ struct nvkm_vma bar;
} user;
int spoon_nr;
};
-struct nvc0_fifo_base {
- struct nouveau_fifo_base base;
- struct nouveau_gpuobj *pgd;
- struct nouveau_vm *vm;
+struct gf100_fifo_base {
+ struct nvkm_fifo_base base;
+ struct nvkm_gpuobj *pgd;
+ struct nvkm_vm *vm;
};
-struct nvc0_fifo_chan {
- struct nouveau_fifo_chan base;
+struct gf100_fifo_chan {
+ struct nvkm_fifo_chan base;
enum {
STOPPED,
RUNNING,
@@ -79,10 +74,10 @@ struct nvc0_fifo_chan {
******************************************************************************/
static void
-nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv)
+gf100_fifo_runlist_update(struct gf100_fifo_priv *priv)
{
- struct nouveau_bar *bar = nouveau_bar(priv);
- struct nouveau_gpuobj *cur;
+ struct nvkm_bar *bar = nvkm_bar(priv);
+ struct nvkm_gpuobj *cur;
int i, p;
mutex_lock(&nv_subdev(priv)->mutex);
@@ -90,7 +85,7 @@ nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv)
priv->runlist.active = !priv->runlist.active;
for (i = 0, p = 0; i < 128; i++) {
- struct nvc0_fifo_chan *chan = (void *)priv->base.channel[i];
+ struct gf100_fifo_chan *chan = (void *)priv->base.channel[i];
if (chan && chan->state == RUNNING) {
nv_wo32(cur, p + 0, i);
nv_wo32(cur, p + 4, 0x00000004);
@@ -110,12 +105,12 @@ nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv)
}
static int
-nvc0_fifo_context_attach(struct nouveau_object *parent,
- struct nouveau_object *object)
+gf100_fifo_context_attach(struct nvkm_object *parent,
+ struct nvkm_object *object)
{
- struct nouveau_bar *bar = nouveau_bar(parent);
- struct nvc0_fifo_base *base = (void *)parent->parent;
- struct nouveau_engctx *ectx = (void *)object;
+ struct nvkm_bar *bar = nvkm_bar(parent);
+ struct gf100_fifo_base *base = (void *)parent->parent;
+ struct nvkm_engctx *ectx = (void *)object;
u32 addr;
int ret;
@@ -132,8 +127,8 @@ nvc0_fifo_context_attach(struct nouveau_object *parent,
}
if (!ectx->vma.node) {
- ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
- NV_MEM_ACCESS_RW, &ectx->vma);
+ ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
+ NV_MEM_ACCESS_RW, &ectx->vma);
if (ret)
return ret;
@@ -147,13 +142,13 @@ nvc0_fifo_context_attach(struct nouveau_object *parent,
}
static int
-nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
- struct nouveau_object *object)
+gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend,
+ struct nvkm_object *object)
{
- struct nouveau_bar *bar = nouveau_bar(parent);
- struct nvc0_fifo_priv *priv = (void *)parent->engine;
- struct nvc0_fifo_base *base = (void *)parent->parent;
- struct nvc0_fifo_chan *chan = (void *)parent;
+ struct nvkm_bar *bar = nvkm_bar(parent);
+ struct gf100_fifo_priv *priv = (void *)parent->engine;
+ struct gf100_fifo_base *base = (void *)parent->parent;
+ struct gf100_fifo_chan *chan = (void *)parent;
u32 addr;
switch (nv_engidx(object->engine)) {
@@ -171,7 +166,7 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
nv_wr32(priv, 0x002634, chan->base.chid);
if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
nv_error(priv, "channel %d [%s] kick timeout\n",
- chan->base.chid, nouveau_client_name(chan));
+ chan->base.chid, nvkm_client_name(chan));
if (suspend)
return -EBUSY;
}
@@ -183,18 +178,17 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
}
static int
-nvc0_fifo_chan_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv50_channel_gpfifo_v0 v0;
} *args = data;
- struct nouveau_bar *bar = nouveau_bar(parent);
- struct nvc0_fifo_priv *priv = (void *)engine;
- struct nvc0_fifo_base *base = (void *)parent;
- struct nvc0_fifo_chan *chan;
+ struct nvkm_bar *bar = nvkm_bar(parent);
+ struct gf100_fifo_priv *priv = (void *)engine;
+ struct gf100_fifo_base *base = (void *)parent;
+ struct gf100_fifo_chan *chan;
u64 usermem, ioffset, ilength;
int ret, i;
@@ -207,24 +201,24 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent,
} else
return ret;
- ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
- priv->user.bar.offset, 0x1000,
- args->v0.pushbuf,
- (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_CE0) |
- (1ULL << NVDEV_ENGINE_CE1) |
- (1ULL << NVDEV_ENGINE_MSVLD) |
- (1ULL << NVDEV_ENGINE_MSPDEC) |
- (1ULL << NVDEV_ENGINE_MSPPP), &chan);
+ ret = nvkm_fifo_channel_create(parent, engine, oclass, 1,
+ priv->user.bar.offset, 0x1000,
+ args->v0.pushbuf,
+ (1ULL << NVDEV_ENGINE_SW) |
+ (1ULL << NVDEV_ENGINE_GR) |
+ (1ULL << NVDEV_ENGINE_CE0) |
+ (1ULL << NVDEV_ENGINE_CE1) |
+ (1ULL << NVDEV_ENGINE_MSVLD) |
+ (1ULL << NVDEV_ENGINE_MSPDEC) |
+ (1ULL << NVDEV_ENGINE_MSPPP), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
args->v0.chid = chan->base.chid;
- nv_parent(chan)->context_attach = nvc0_fifo_context_attach;
- nv_parent(chan)->context_detach = nvc0_fifo_context_detach;
+ nv_parent(chan)->context_attach = gf100_fifo_context_attach;
+ nv_parent(chan)->context_detach = gf100_fifo_context_detach;
usermem = chan->base.chid * 0x1000;
ioffset = args->v0.ioffset;
@@ -254,15 +248,15 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent,
}
static int
-nvc0_fifo_chan_init(struct nouveau_object *object)
+gf100_fifo_chan_init(struct nvkm_object *object)
{
- struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
- struct nvc0_fifo_priv *priv = (void *)object->engine;
- struct nvc0_fifo_chan *chan = (void *)object;
+ struct nvkm_gpuobj *base = nv_gpuobj(object->parent);
+ struct gf100_fifo_priv *priv = (void *)object->engine;
+ struct gf100_fifo_chan *chan = (void *)object;
u32 chid = chan->base.chid;
int ret;
- ret = nouveau_fifo_channel_init(&chan->base);
+ ret = nvkm_fifo_channel_init(&chan->base);
if (ret)
return ret;
@@ -270,47 +264,47 @@ nvc0_fifo_chan_init(struct nouveau_object *object)
if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) {
nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001);
- nvc0_fifo_runlist_update(priv);
+ gf100_fifo_runlist_update(priv);
}
return 0;
}
-static void nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv);
+static void gf100_fifo_intr_engine(struct gf100_fifo_priv *priv);
static int
-nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
+gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend)
{
- struct nvc0_fifo_priv *priv = (void *)object->engine;
- struct nvc0_fifo_chan *chan = (void *)object;
+ struct gf100_fifo_priv *priv = (void *)object->engine;
+ struct gf100_fifo_chan *chan = (void *)object;
u32 chid = chan->base.chid;
if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) {
nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
- nvc0_fifo_runlist_update(priv);
+ gf100_fifo_runlist_update(priv);
}
- nvc0_fifo_intr_engine(priv);
+ gf100_fifo_intr_engine(priv);
nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000);
- return nouveau_fifo_channel_fini(&chan->base, suspend);
+ return nvkm_fifo_channel_fini(&chan->base, suspend);
}
-static struct nouveau_ofuncs
-nvc0_fifo_ofuncs = {
- .ctor = nvc0_fifo_chan_ctor,
- .dtor = _nouveau_fifo_channel_dtor,
- .init = nvc0_fifo_chan_init,
- .fini = nvc0_fifo_chan_fini,
- .map = _nouveau_fifo_channel_map,
- .rd32 = _nouveau_fifo_channel_rd32,
- .wr32 = _nouveau_fifo_channel_wr32,
- .ntfy = _nouveau_fifo_channel_ntfy
+static struct nvkm_ofuncs
+gf100_fifo_ofuncs = {
+ .ctor = gf100_fifo_chan_ctor,
+ .dtor = _nvkm_fifo_channel_dtor,
+ .init = gf100_fifo_chan_init,
+ .fini = gf100_fifo_chan_fini,
+ .map = _nvkm_fifo_channel_map,
+ .rd32 = _nvkm_fifo_channel_rd32,
+ .wr32 = _nvkm_fifo_channel_wr32,
+ .ntfy = _nvkm_fifo_channel_ntfy
};
-static struct nouveau_oclass
-nvc0_fifo_sclass[] = {
- { FERMI_CHANNEL_GPFIFO, &nvc0_fifo_ofuncs },
+static struct nvkm_oclass
+gf100_fifo_sclass[] = {
+ { FERMI_CHANNEL_GPFIFO, &gf100_fifo_ofuncs },
{}
};
@@ -319,23 +313,22 @@ nvc0_fifo_sclass[] = {
******************************************************************************/
static int
-nvc0_fifo_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvc0_fifo_base *base;
+ struct gf100_fifo_base *base;
int ret;
- ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
- 0x1000, NVOBJ_FLAG_ZERO_ALLOC |
- NVOBJ_FLAG_HEAP, &base);
+ ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
+ 0x1000, NVOBJ_FLAG_ZERO_ALLOC |
+ NVOBJ_FLAG_HEAP, &base);
*pobject = nv_object(base);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
- &base->pgd);
+ ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
+ &base->pgd);
if (ret)
return ret;
@@ -344,7 +337,7 @@ nvc0_fifo_context_ctor(struct nouveau_object *parent,
nv_wo32(base, 0x0208, 0xffffffff);
nv_wo32(base, 0x020c, 0x000000ff);
- ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
+ ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);
if (ret)
return ret;
@@ -352,24 +345,24 @@ nvc0_fifo_context_ctor(struct nouveau_object *parent,
}
static void
-nvc0_fifo_context_dtor(struct nouveau_object *object)
+gf100_fifo_context_dtor(struct nvkm_object *object)
{
- struct nvc0_fifo_base *base = (void *)object;
- nouveau_vm_ref(NULL, &base->vm, base->pgd);
- nouveau_gpuobj_ref(NULL, &base->pgd);
- nouveau_fifo_context_destroy(&base->base);
+ struct gf100_fifo_base *base = (void *)object;
+ nvkm_vm_ref(NULL, &base->vm, base->pgd);
+ nvkm_gpuobj_ref(NULL, &base->pgd);
+ nvkm_fifo_context_destroy(&base->base);
}
-static struct nouveau_oclass
-nvc0_fifo_cclass = {
+static struct nvkm_oclass
+gf100_fifo_cclass = {
.handle = NV_ENGCTX(FIFO, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_fifo_context_ctor,
- .dtor = nvc0_fifo_context_dtor,
- .init = _nouveau_fifo_context_init,
- .fini = _nouveau_fifo_context_fini,
- .rd32 = _nouveau_fifo_context_rd32,
- .wr32 = _nouveau_fifo_context_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_fifo_context_ctor,
+ .dtor = gf100_fifo_context_dtor,
+ .init = _nvkm_fifo_context_init,
+ .fini = _nvkm_fifo_context_fini,
+ .rd32 = _nvkm_fifo_context_rd32,
+ .wr32 = _nvkm_fifo_context_wr32,
},
};
@@ -378,7 +371,7 @@ nvc0_fifo_cclass = {
******************************************************************************/
static inline int
-nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
+gf100_fifo_engidx(struct gf100_fifo_priv *priv, u32 engn)
{
switch (engn) {
case NVDEV_ENGINE_GR : engn = 0; break;
@@ -394,8 +387,8 @@ nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
return engn;
}
-static inline struct nouveau_engine *
-nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
+static inline struct nvkm_engine *
+gf100_fifo_engine(struct gf100_fifo_priv *priv, u32 engn)
{
switch (engn) {
case 0: engn = NVDEV_ENGINE_GR; break;
@@ -408,14 +401,14 @@ nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
return NULL;
}
- return nouveau_engine(priv, engn);
+ return nvkm_engine(priv, engn);
}
static void
-nvc0_fifo_recover_work(struct work_struct *work)
+gf100_fifo_recover_work(struct work_struct *work)
{
- struct nvc0_fifo_priv *priv = container_of(work, typeof(*priv), fault);
- struct nouveau_object *engine;
+ struct gf100_fifo_priv *priv = container_of(work, typeof(*priv), fault);
+ struct nvkm_object *engine;
unsigned long flags;
u32 engn, engm = 0;
u64 mask, todo;
@@ -426,24 +419,24 @@ nvc0_fifo_recover_work(struct work_struct *work)
spin_unlock_irqrestore(&priv->base.lock, flags);
for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
- engm |= 1 << nvc0_fifo_engidx(priv, engn);
+ engm |= 1 << gf100_fifo_engidx(priv, engn);
nv_mask(priv, 0x002630, engm, engm);
for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
- if ((engine = (void *)nouveau_engine(priv, engn))) {
+ if ((engine = (void *)nvkm_engine(priv, engn))) {
nv_ofuncs(engine)->fini(engine, false);
WARN_ON(nv_ofuncs(engine)->init(engine));
}
}
- nvc0_fifo_runlist_update(priv);
+ gf100_fifo_runlist_update(priv);
nv_wr32(priv, 0x00262c, engm);
nv_mask(priv, 0x002630, engm, 0x00000000);
}
static void
-nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine,
- struct nvc0_fifo_chan *chan)
+gf100_fifo_recover(struct gf100_fifo_priv *priv, struct nvkm_engine *engine,
+ struct gf100_fifo_chan *chan)
{
u32 chid = chan->base.chid;
unsigned long flags;
@@ -461,10 +454,10 @@ nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine,
}
static int
-nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
+gf100_fifo_swmthd(struct gf100_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
{
- struct nvc0_fifo_chan *chan = NULL;
- struct nouveau_handle *bind;
+ struct gf100_fifo_chan *chan = NULL;
+ struct nvkm_handle *bind;
unsigned long flags;
int ret = -EINVAL;
@@ -474,11 +467,11 @@ nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
if (unlikely(!chan))
goto out;
- bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
+ bind = nvkm_namedb_get_class(nv_namedb(chan), 0x906e);
if (likely(bind)) {
if (!mthd || !nv_call(bind->object, mthd, data))
ret = 0;
- nouveau_namedb_put(bind);
+ nvkm_namedb_put(bind);
}
out:
@@ -486,17 +479,17 @@ out:
return ret;
}
-static const struct nouveau_enum
-nvc0_fifo_sched_reason[] = {
+static const struct nvkm_enum
+gf100_fifo_sched_reason[] = {
{ 0x0a, "CTXSW_TIMEOUT" },
{}
};
static void
-nvc0_fifo_intr_sched_ctxsw(struct nvc0_fifo_priv *priv)
+gf100_fifo_intr_sched_ctxsw(struct gf100_fifo_priv *priv)
{
- struct nouveau_engine *engine;
- struct nvc0_fifo_chan *chan;
+ struct nvkm_engine *engine;
+ struct gf100_fifo_chan *chan;
u32 engn;
for (engn = 0; engn < 6; engn++) {
@@ -511,22 +504,22 @@ nvc0_fifo_intr_sched_ctxsw(struct nvc0_fifo_priv *priv)
if (busy && unk0 && unk1) {
if (!(chan = (void *)priv->base.channel[chid]))
continue;
- if (!(engine = nvc0_fifo_engine(priv, engn)))
+ if (!(engine = gf100_fifo_engine(priv, engn)))
continue;
- nvc0_fifo_recover(priv, engine, chan);
+ gf100_fifo_recover(priv, engine, chan);
}
}
}
static void
-nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv)
+gf100_fifo_intr_sched(struct gf100_fifo_priv *priv)
{
u32 intr = nv_rd32(priv, 0x00254c);
u32 code = intr & 0x000000ff;
- const struct nouveau_enum *en;
+ const struct nvkm_enum *en;
char enunk[6] = "";
- en = nouveau_enum_find(nvc0_fifo_sched_reason, code);
+ en = nvkm_enum_find(gf100_fifo_sched_reason, code);
if (!en)
snprintf(enunk, sizeof(enunk), "UNK%02x", code);
@@ -534,15 +527,15 @@ nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv)
switch (code) {
case 0x0a:
- nvc0_fifo_intr_sched_ctxsw(priv);
+ gf100_fifo_intr_sched_ctxsw(priv);
break;
default:
break;
}
}
-static const struct nouveau_enum
-nvc0_fifo_fault_engine[] = {
+static const struct nvkm_enum
+gf100_fifo_fault_engine[] = {
{ 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
{ 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB },
{ 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
@@ -558,8 +551,8 @@ nvc0_fifo_fault_engine[] = {
{}
};
-static const struct nouveau_enum
-nvc0_fifo_fault_reason[] = {
+static const struct nvkm_enum
+gf100_fifo_fault_reason[] = {
{ 0x00, "PT_NOT_PRESENT" },
{ 0x01, "PT_TOO_SHORT" },
{ 0x02, "PAGE_NOT_PRESENT" },
@@ -572,8 +565,8 @@ nvc0_fifo_fault_reason[] = {
{}
};
-static const struct nouveau_enum
-nvc0_fifo_fault_hubclient[] = {
+static const struct nvkm_enum
+gf100_fifo_fault_hubclient[] = {
{ 0x01, "PCOPY0" },
{ 0x02, "PCOPY1" },
{ 0x04, "DISPATCH" },
@@ -591,8 +584,8 @@ nvc0_fifo_fault_hubclient[] = {
{}
};
-static const struct nouveau_enum
-nvc0_fifo_fault_gpcclient[] = {
+static const struct nvkm_enum
+gf100_fifo_fault_gpcclient[] = {
{ 0x01, "TEX" },
{ 0x0c, "ESETUP" },
{ 0x0e, "CTXCTL" },
@@ -601,7 +594,7 @@ nvc0_fifo_fault_gpcclient[] = {
};
static void
-nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit)
+gf100_fifo_intr_fault(struct gf100_fifo_priv *priv, int unit)
{
u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10));
u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10));
@@ -612,19 +605,19 @@ nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit)
u32 write = (stat & 0x00000080);
u32 hub = (stat & 0x00000040);
u32 reason = (stat & 0x0000000f);
- struct nouveau_object *engctx = NULL, *object;
- struct nouveau_engine *engine = NULL;
- const struct nouveau_enum *er, *eu, *ec;
+ struct nvkm_object *engctx = NULL, *object;
+ struct nvkm_engine *engine = NULL;
+ const struct nvkm_enum *er, *eu, *ec;
char erunk[6] = "";
char euunk[6] = "";
char ecunk[6] = "";
char gpcid[3] = "";
- er = nouveau_enum_find(nvc0_fifo_fault_reason, reason);
+ er = nvkm_enum_find(gf100_fifo_fault_reason, reason);
if (!er)
snprintf(erunk, sizeof(erunk), "UNK%02X", reason);
- eu = nouveau_enum_find(nvc0_fifo_fault_engine, unit);
+ eu = nvkm_enum_find(gf100_fifo_fault_engine, unit);
if (eu) {
switch (eu->data2) {
case NVDEV_SUBDEV_BAR:
@@ -637,9 +630,9 @@ nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit)
nv_mask(priv, 0x001718, 0x00000000, 0x00000000);
break;
default:
- engine = nouveau_engine(priv, eu->data2);
+ engine = nvkm_engine(priv, eu->data2);
if (engine)
- engctx = nouveau_engctx_get(engine, inst);
+ engctx = nvkm_engctx_get(engine, inst);
break;
}
} else {
@@ -647,9 +640,9 @@ nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit)
}
if (hub) {
- ec = nouveau_enum_find(nvc0_fifo_fault_hubclient, client);
+ ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client);
} else {
- ec = nouveau_enum_find(nvc0_fifo_fault_gpcclient, client);
+ ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client);
snprintf(gpcid, sizeof(gpcid), "%d", gpc);
}
@@ -661,23 +654,23 @@ nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit)
(u64)vahi << 32 | valo, er ? er->name : erunk,
eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/",
ec ? ec->name : ecunk, (u64)inst << 12,
- nouveau_client_name(engctx));
+ nvkm_client_name(engctx));
object = engctx;
while (object) {
switch (nv_mclass(object)) {
case FERMI_CHANNEL_GPFIFO:
- nvc0_fifo_recover(priv, engine, (void *)object);
+ gf100_fifo_recover(priv, engine, (void *)object);
break;
}
object = object->parent;
}
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
-static const struct nouveau_bitfield
-nvc0_fifo_pbdma_intr[] = {
+static const struct nvkm_bitfield
+gf100_fifo_pbdma_intr[] = {
/* { 0x00008000, "" } seen with null ib push */
{ 0x00200000, "ILLEGAL_MTHD" },
{ 0x00800000, "EMPTY_SUBC" },
@@ -685,7 +678,7 @@ nvc0_fifo_pbdma_intr[] = {
};
static void
-nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit)
+gf100_fifo_intr_pbdma(struct gf100_fifo_priv *priv, int unit)
{
u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
@@ -696,18 +689,18 @@ nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit)
u32 show = stat;
if (stat & 0x00800000) {
- if (!nvc0_fifo_swmthd(priv, chid, mthd, data))
+ if (!gf100_fifo_swmthd(priv, chid, mthd, data))
show &= ~0x00800000;
}
if (show) {
nv_error(priv, "PBDMA%d:", unit);
- nouveau_bitfield_print(nvc0_fifo_pbdma_intr, show);
+ nvkm_bitfield_print(gf100_fifo_pbdma_intr, show);
pr_cont("\n");
nv_error(priv,
"PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
unit, chid,
- nouveau_client_name_for_fifo_chid(&priv->base, chid),
+ nvkm_client_name_for_fifo_chid(&priv->base, chid),
subc, mthd, data);
}
@@ -716,7 +709,7 @@ nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit)
}
static void
-nvc0_fifo_intr_runlist(struct nvc0_fifo_priv *priv)
+gf100_fifo_intr_runlist(struct gf100_fifo_priv *priv)
{
u32 intr = nv_rd32(priv, 0x002a00);
@@ -733,7 +726,7 @@ nvc0_fifo_intr_runlist(struct nvc0_fifo_priv *priv)
}
static void
-nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn)
+gf100_fifo_intr_engine_unit(struct gf100_fifo_priv *priv, int engn)
{
u32 intr = nv_rd32(priv, 0x0025a8 + (engn * 0x04));
u32 inte = nv_rd32(priv, 0x002628);
@@ -744,7 +737,7 @@ nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn)
for (unkn = 0; unkn < 8; unkn++) {
u32 ints = (intr >> (unkn * 0x04)) & inte;
if (ints & 0x1) {
- nouveau_fifo_uevent(&priv->base);
+ nvkm_fifo_uevent(&priv->base);
ints &= ~1;
}
if (ints) {
@@ -755,20 +748,20 @@ nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn)
}
static void
-nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv)
+gf100_fifo_intr_engine(struct gf100_fifo_priv *priv)
{
u32 mask = nv_rd32(priv, 0x0025a4);
while (mask) {
u32 unit = __ffs(mask);
- nvc0_fifo_intr_engine_unit(priv, unit);
+ gf100_fifo_intr_engine_unit(priv, unit);
mask &= ~(1 << unit);
}
}
static void
-nvc0_fifo_intr(struct nouveau_subdev *subdev)
+gf100_fifo_intr(struct nvkm_subdev *subdev)
{
- struct nvc0_fifo_priv *priv = (void *)subdev;
+ struct gf100_fifo_priv *priv = (void *)subdev;
u32 mask = nv_rd32(priv, 0x002140);
u32 stat = nv_rd32(priv, 0x002100) & mask;
@@ -780,7 +773,7 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev)
}
if (stat & 0x00000100) {
- nvc0_fifo_intr_sched(priv);
+ gf100_fifo_intr_sched(priv);
nv_wr32(priv, 0x002100, 0x00000100);
stat &= ~0x00000100;
}
@@ -803,7 +796,7 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev)
u32 mask = nv_rd32(priv, 0x00259c);
while (mask) {
u32 unit = __ffs(mask);
- nvc0_fifo_intr_fault(priv, unit);
+ gf100_fifo_intr_fault(priv, unit);
nv_wr32(priv, 0x00259c, (1 << unit));
mask &= ~(1 << unit);
}
@@ -814,7 +807,7 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev)
u32 mask = nv_rd32(priv, 0x0025a0);
while (mask) {
u32 unit = __ffs(mask);
- nvc0_fifo_intr_pbdma(priv, unit);
+ gf100_fifo_intr_pbdma(priv, unit);
nv_wr32(priv, 0x0025a0, (1 << unit));
mask &= ~(1 << unit);
}
@@ -822,12 +815,12 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev)
}
if (stat & 0x40000000) {
- nvc0_fifo_intr_runlist(priv);
+ gf100_fifo_intr_runlist(priv);
stat &= ~0x40000000;
}
if (stat & 0x80000000) {
- nvc0_fifo_intr_engine(priv);
+ gf100_fifo_intr_engine(priv);
stat &= ~0x80000000;
}
@@ -839,94 +832,94 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev)
}
static void
-nvc0_fifo_uevent_init(struct nvkm_event *event, int type, int index)
+gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index)
{
- struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
+ struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
nv_mask(fifo, 0x002140, 0x80000000, 0x80000000);
}
static void
-nvc0_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
+gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
{
- struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
+ struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
nv_mask(fifo, 0x002140, 0x80000000, 0x00000000);
}
static const struct nvkm_event_func
-nvc0_fifo_uevent_func = {
- .ctor = nouveau_fifo_uevent_ctor,
- .init = nvc0_fifo_uevent_init,
- .fini = nvc0_fifo_uevent_fini,
+gf100_fifo_uevent_func = {
+ .ctor = nvkm_fifo_uevent_ctor,
+ .init = gf100_fifo_uevent_init,
+ .fini = gf100_fifo_uevent_fini,
};
static int
-nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvc0_fifo_priv *priv;
+ struct gf100_fifo_priv *priv;
int ret;
- ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv);
+ ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- INIT_WORK(&priv->fault, nvc0_fifo_recover_work);
+ INIT_WORK(&priv->fault, gf100_fifo_recover_work);
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
- &priv->runlist.mem[0]);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
+ &priv->runlist.mem[0]);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
- &priv->runlist.mem[1]);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
+ &priv->runlist.mem[1]);
if (ret)
return ret;
init_waitqueue_head(&priv->runlist.wait);
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0,
- &priv->user.mem);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0,
+ &priv->user.mem);
if (ret)
return ret;
- ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
- &priv->user.bar);
+ ret = nvkm_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
+ &priv->user.bar);
if (ret)
return ret;
- ret = nvkm_event_init(&nvc0_fifo_uevent_func, 1, 1, &priv->base.uevent);
+ ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &priv->base.uevent);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000100;
- nv_subdev(priv)->intr = nvc0_fifo_intr;
- nv_engine(priv)->cclass = &nvc0_fifo_cclass;
- nv_engine(priv)->sclass = nvc0_fifo_sclass;
+ nv_subdev(priv)->intr = gf100_fifo_intr;
+ nv_engine(priv)->cclass = &gf100_fifo_cclass;
+ nv_engine(priv)->sclass = gf100_fifo_sclass;
return 0;
}
static void
-nvc0_fifo_dtor(struct nouveau_object *object)
+gf100_fifo_dtor(struct nvkm_object *object)
{
- struct nvc0_fifo_priv *priv = (void *)object;
+ struct gf100_fifo_priv *priv = (void *)object;
- nouveau_gpuobj_unmap(&priv->user.bar);
- nouveau_gpuobj_ref(NULL, &priv->user.mem);
- nouveau_gpuobj_ref(NULL, &priv->runlist.mem[0]);
- nouveau_gpuobj_ref(NULL, &priv->runlist.mem[1]);
+ nvkm_gpuobj_unmap(&priv->user.bar);
+ nvkm_gpuobj_ref(NULL, &priv->user.mem);
+ nvkm_gpuobj_ref(NULL, &priv->runlist.mem[0]);
+ nvkm_gpuobj_ref(NULL, &priv->runlist.mem[1]);
- nouveau_fifo_destroy(&priv->base);
+ nvkm_fifo_destroy(&priv->base);
}
static int
-nvc0_fifo_init(struct nouveau_object *object)
+gf100_fifo_init(struct nvkm_object *object)
{
- struct nvc0_fifo_priv *priv = (void *)object;
+ struct gf100_fifo_priv *priv = (void *)object;
int ret, i;
- ret = nouveau_fifo_init(&priv->base);
+ ret = nvkm_fifo_init(&priv->base);
if (ret)
return ret;
@@ -962,13 +955,13 @@ nvc0_fifo_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
-nvc0_fifo_oclass = &(struct nouveau_oclass) {
+struct nvkm_oclass *
+gf100_fifo_oclass = &(struct nvkm_oclass) {
.handle = NV_ENGINE(FIFO, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_fifo_ctor,
- .dtor = nvc0_fifo_dtor,
- .init = nvc0_fifo_init,
- .fini = _nouveau_fifo_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_fifo_ctor,
+ .dtor = gf100_fifo_dtor,
+ .init = gf100_fifo_init,
+ .fini = _nvkm_fifo_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
similarity index 67%
rename from drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
index f5965eb6b262..9585539e59f2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
@@ -21,25 +21,19 @@
*
* Authors: Ben Skeggs
*/
+#include "gk104.h"
#include <core/client.h>
-#include <core/handle.h>
-#include <core/namedb.h>
-#include <core/gpuobj.h>
#include <core/engctx.h>
-#include <core/event.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
#include <core/enum.h>
-
-#include <subdev/timer.h>
+#include <core/handle.h>
#include <subdev/bar.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>
+#include <subdev/timer.h>
-#include <engine/dmaobj.h>
-
-#include "nve0.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
#define _(a,b) { (a), ((1ULL << (a)) | (b)) }
static const struct {
@@ -58,34 +52,34 @@ static const struct {
#undef _
#define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine)
-struct nve0_fifo_engn {
- struct nouveau_gpuobj *runlist[2];
+struct gk104_fifo_engn {
+ struct nvkm_gpuobj *runlist[2];
int cur_runlist;
wait_queue_head_t wait;
};
-struct nve0_fifo_priv {
- struct nouveau_fifo base;
+struct gk104_fifo_priv {
+ struct nvkm_fifo base;
struct work_struct fault;
u64 mask;
- struct nve0_fifo_engn engine[FIFO_ENGINE_NR];
+ struct gk104_fifo_engn engine[FIFO_ENGINE_NR];
struct {
- struct nouveau_gpuobj *mem;
- struct nouveau_vma bar;
+ struct nvkm_gpuobj *mem;
+ struct nvkm_vma bar;
} user;
int spoon_nr;
};
-struct nve0_fifo_base {
- struct nouveau_fifo_base base;
- struct nouveau_gpuobj *pgd;
- struct nouveau_vm *vm;
+struct gk104_fifo_base {
+ struct nvkm_fifo_base base;
+ struct nvkm_gpuobj *pgd;
+ struct nvkm_vm *vm;
};
-struct nve0_fifo_chan {
- struct nouveau_fifo_chan base;
+struct gk104_fifo_chan {
+ struct nvkm_fifo_chan base;
u32 engine;
enum {
STOPPED,
@@ -99,11 +93,11 @@ struct nve0_fifo_chan {
******************************************************************************/
static void
-nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine)
+gk104_fifo_runlist_update(struct gk104_fifo_priv *priv, u32 engine)
{
- struct nouveau_bar *bar = nouveau_bar(priv);
- struct nve0_fifo_engn *engn = &priv->engine[engine];
- struct nouveau_gpuobj *cur;
+ struct nvkm_bar *bar = nvkm_bar(priv);
+ struct gk104_fifo_engn *engn = &priv->engine[engine];
+ struct nvkm_gpuobj *cur;
int i, p;
mutex_lock(&nv_subdev(priv)->mutex);
@@ -111,7 +105,7 @@ nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine)
engn->cur_runlist = !engn->cur_runlist;
for (i = 0, p = 0; i < priv->base.max; i++) {
- struct nve0_fifo_chan *chan = (void *)priv->base.channel[i];
+ struct gk104_fifo_chan *chan = (void *)priv->base.channel[i];
if (chan && chan->state == RUNNING && chan->engine == engine) {
nv_wo32(cur, p + 0, i);
nv_wo32(cur, p + 4, 0x00000000);
@@ -131,12 +125,12 @@ nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine)
}
static int
-nve0_fifo_context_attach(struct nouveau_object *parent,
- struct nouveau_object *object)
+gk104_fifo_context_attach(struct nvkm_object *parent,
+ struct nvkm_object *object)
{
- struct nouveau_bar *bar = nouveau_bar(parent);
- struct nve0_fifo_base *base = (void *)parent->parent;
- struct nouveau_engctx *ectx = (void *)object;
+ struct nvkm_bar *bar = nvkm_bar(parent);
+ struct gk104_fifo_base *base = (void *)parent->parent;
+ struct nvkm_engctx *ectx = (void *)object;
u32 addr;
int ret;
@@ -157,8 +151,8 @@ nve0_fifo_context_attach(struct nouveau_object *parent,
}
if (!ectx->vma.node) {
- ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
- NV_MEM_ACCESS_RW, &ectx->vma);
+ ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
+ NV_MEM_ACCESS_RW, &ectx->vma);
if (ret)
return ret;
@@ -172,13 +166,13 @@ nve0_fifo_context_attach(struct nouveau_object *parent,
}
static int
-nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
- struct nouveau_object *object)
+gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend,
+ struct nvkm_object *object)
{
- struct nouveau_bar *bar = nouveau_bar(parent);
- struct nve0_fifo_priv *priv = (void *)parent->engine;
- struct nve0_fifo_base *base = (void *)parent->parent;
- struct nve0_fifo_chan *chan = (void *)parent;
+ struct nvkm_bar *bar = nvkm_bar(parent);
+ struct gk104_fifo_priv *priv = (void *)parent->engine;
+ struct gk104_fifo_base *base = (void *)parent->parent;
+ struct gk104_fifo_chan *chan = (void *)parent;
u32 addr;
switch (nv_engidx(object->engine)) {
@@ -197,7 +191,7 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
nv_wr32(priv, 0x002634, chan->base.chid);
if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
nv_error(priv, "channel %d [%s] kick timeout\n",
- chan->base.chid, nouveau_client_name(chan));
+ chan->base.chid, nvkm_client_name(chan));
if (suspend)
return -EBUSY;
}
@@ -212,18 +206,17 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
}
static int
-nve0_fifo_chan_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct kepler_channel_gpfifo_a_v0 v0;
} *args = data;
- struct nouveau_bar *bar = nouveau_bar(parent);
- struct nve0_fifo_priv *priv = (void *)engine;
- struct nve0_fifo_base *base = (void *)parent;
- struct nve0_fifo_chan *chan;
+ struct nvkm_bar *bar = nvkm_bar(parent);
+ struct gk104_fifo_priv *priv = (void *)engine;
+ struct gk104_fifo_base *base = (void *)parent;
+ struct gk104_fifo_chan *chan;
u64 usermem, ioffset, ilength;
int ret, i;
@@ -238,7 +231,7 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent,
for (i = 0; i < FIFO_ENGINE_NR; i++) {
if (args->v0.engine & (1 << i)) {
- if (nouveau_engine(parent, fifo_engine[i].subdev)) {
+ if (nvkm_engine(parent, fifo_engine[i].subdev)) {
args->v0.engine = (1 << i);
break;
}
@@ -250,18 +243,18 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent,
return -ENODEV;
}
- ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
- priv->user.bar.offset, 0x200,
- args->v0.pushbuf,
- fifo_engine[i].mask, &chan);
+ ret = nvkm_fifo_channel_create(parent, engine, oclass, 1,
+ priv->user.bar.offset, 0x200,
+ args->v0.pushbuf,
+ fifo_engine[i].mask, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
args->v0.chid = chan->base.chid;
- nv_parent(chan)->context_attach = nve0_fifo_context_attach;
- nv_parent(chan)->context_detach = nve0_fifo_context_detach;
+ nv_parent(chan)->context_attach = gk104_fifo_context_attach;
+ nv_parent(chan)->context_detach = gk104_fifo_context_detach;
chan->engine = i;
usermem = chan->base.chid * 0x200;
@@ -290,15 +283,15 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent,
}
static int
-nve0_fifo_chan_init(struct nouveau_object *object)
+gk104_fifo_chan_init(struct nvkm_object *object)
{
- struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
- struct nve0_fifo_priv *priv = (void *)object->engine;
- struct nve0_fifo_chan *chan = (void *)object;
+ struct nvkm_gpuobj *base = nv_gpuobj(object->parent);
+ struct gk104_fifo_priv *priv = (void *)object->engine;
+ struct gk104_fifo_chan *chan = (void *)object;
u32 chid = chan->base.chid;
int ret;
- ret = nouveau_fifo_channel_init(&chan->base);
+ ret = nvkm_fifo_channel_init(&chan->base);
if (ret)
return ret;
@@ -307,7 +300,7 @@ nve0_fifo_chan_init(struct nouveau_object *object)
if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) {
nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
- nve0_fifo_runlist_update(priv, chan->engine);
+ gk104_fifo_runlist_update(priv, chan->engine);
nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
}
@@ -315,36 +308,36 @@ nve0_fifo_chan_init(struct nouveau_object *object)
}
static int
-nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
+gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend)
{
- struct nve0_fifo_priv *priv = (void *)object->engine;
- struct nve0_fifo_chan *chan = (void *)object;
+ struct gk104_fifo_priv *priv = (void *)object->engine;
+ struct gk104_fifo_chan *chan = (void *)object;
u32 chid = chan->base.chid;
if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) {
nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800);
- nve0_fifo_runlist_update(priv, chan->engine);
+ gk104_fifo_runlist_update(priv, chan->engine);
}
nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000);
- return nouveau_fifo_channel_fini(&chan->base, suspend);
+ return nvkm_fifo_channel_fini(&chan->base, suspend);
}
-static struct nouveau_ofuncs
-nve0_fifo_ofuncs = {
- .ctor = nve0_fifo_chan_ctor,
- .dtor = _nouveau_fifo_channel_dtor,
- .init = nve0_fifo_chan_init,
- .fini = nve0_fifo_chan_fini,
- .map = _nouveau_fifo_channel_map,
- .rd32 = _nouveau_fifo_channel_rd32,
- .wr32 = _nouveau_fifo_channel_wr32,
- .ntfy = _nouveau_fifo_channel_ntfy
+static struct nvkm_ofuncs
+gk104_fifo_ofuncs = {
+ .ctor = gk104_fifo_chan_ctor,
+ .dtor = _nvkm_fifo_channel_dtor,
+ .init = gk104_fifo_chan_init,
+ .fini = gk104_fifo_chan_fini,
+ .map = _nvkm_fifo_channel_map,
+ .rd32 = _nvkm_fifo_channel_rd32,
+ .wr32 = _nvkm_fifo_channel_wr32,
+ .ntfy = _nvkm_fifo_channel_ntfy
};
-static struct nouveau_oclass
-nve0_fifo_sclass[] = {
- { KEPLER_CHANNEL_GPFIFO_A, &nve0_fifo_ofuncs },
+static struct nvkm_oclass
+gk104_fifo_sclass[] = {
+ { KEPLER_CHANNEL_GPFIFO_A, &gk104_fifo_ofuncs },
{}
};
@@ -353,22 +346,21 @@ nve0_fifo_sclass[] = {
******************************************************************************/
static int
-nve0_fifo_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk104_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nve0_fifo_base *base;
+ struct gk104_fifo_base *base;
int ret;
- ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
- 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base);
+ ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
+ 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base);
*pobject = nv_object(base);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
- &base->pgd);
+ ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
+ &base->pgd);
if (ret)
return ret;
@@ -377,7 +369,7 @@ nve0_fifo_context_ctor(struct nouveau_object *parent,
nv_wo32(base, 0x0208, 0xffffffff);
nv_wo32(base, 0x020c, 0x000000ff);
- ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
+ ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);
if (ret)
return ret;
@@ -385,24 +377,24 @@ nve0_fifo_context_ctor(struct nouveau_object *parent,
}
static void
-nve0_fifo_context_dtor(struct nouveau_object *object)
+gk104_fifo_context_dtor(struct nvkm_object *object)
{
- struct nve0_fifo_base *base = (void *)object;
- nouveau_vm_ref(NULL, &base->vm, base->pgd);
- nouveau_gpuobj_ref(NULL, &base->pgd);
- nouveau_fifo_context_destroy(&base->base);
+ struct gk104_fifo_base *base = (void *)object;
+ nvkm_vm_ref(NULL, &base->vm, base->pgd);
+ nvkm_gpuobj_ref(NULL, &base->pgd);
+ nvkm_fifo_context_destroy(&base->base);
}
-static struct nouveau_oclass
-nve0_fifo_cclass = {
+static struct nvkm_oclass
+gk104_fifo_cclass = {
.handle = NV_ENGCTX(FIFO, 0xe0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_fifo_context_ctor,
- .dtor = nve0_fifo_context_dtor,
- .init = _nouveau_fifo_context_init,
- .fini = _nouveau_fifo_context_fini,
- .rd32 = _nouveau_fifo_context_rd32,
- .wr32 = _nouveau_fifo_context_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_fifo_context_ctor,
+ .dtor = gk104_fifo_context_dtor,
+ .init = _nvkm_fifo_context_init,
+ .fini = _nvkm_fifo_context_fini,
+ .rd32 = _nvkm_fifo_context_rd32,
+ .wr32 = _nvkm_fifo_context_wr32,
},
};
@@ -411,7 +403,7 @@ nve0_fifo_cclass = {
******************************************************************************/
static inline int
-nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
+gk104_fifo_engidx(struct gk104_fifo_priv *priv, u32 engn)
{
switch (engn) {
case NVDEV_ENGINE_GR :
@@ -429,19 +421,19 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
return engn;
}
-static inline struct nouveau_engine *
-nve0_fifo_engine(struct nve0_fifo_priv *priv, u32 engn)
+static inline struct nvkm_engine *
+gk104_fifo_engine(struct gk104_fifo_priv *priv, u32 engn)
{
if (engn >= ARRAY_SIZE(fifo_engine))
return NULL;
- return nouveau_engine(priv, fifo_engine[engn].subdev);
+ return nvkm_engine(priv, fifo_engine[engn].subdev);
}
static void
-nve0_fifo_recover_work(struct work_struct *work)
+gk104_fifo_recover_work(struct work_struct *work)
{
- struct nve0_fifo_priv *priv = container_of(work, typeof(*priv), fault);
- struct nouveau_object *engine;
+ struct gk104_fifo_priv *priv = container_of(work, typeof(*priv), fault);
+ struct nvkm_object *engine;
unsigned long flags;
u32 engn, engm = 0;
u64 mask, todo;
@@ -452,15 +444,15 @@ nve0_fifo_recover_work(struct work_struct *work)
spin_unlock_irqrestore(&priv->base.lock, flags);
for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
- engm |= 1 << nve0_fifo_engidx(priv, engn);
+ engm |= 1 << gk104_fifo_engidx(priv, engn);
nv_mask(priv, 0x002630, engm, engm);
for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
- if ((engine = (void *)nouveau_engine(priv, engn))) {
+ if ((engine = (void *)nvkm_engine(priv, engn))) {
nv_ofuncs(engine)->fini(engine, false);
WARN_ON(nv_ofuncs(engine)->init(engine));
}
- nve0_fifo_runlist_update(priv, nve0_fifo_engidx(priv, engn));
+ gk104_fifo_runlist_update(priv, gk104_fifo_engidx(priv, engn));
}
nv_wr32(priv, 0x00262c, engm);
@@ -468,8 +460,8 @@ nve0_fifo_recover_work(struct work_struct *work)
}
static void
-nve0_fifo_recover(struct nve0_fifo_priv *priv, struct nouveau_engine *engine,
- struct nve0_fifo_chan *chan)
+gk104_fifo_recover(struct gk104_fifo_priv *priv, struct nvkm_engine *engine,
+ struct gk104_fifo_chan *chan)
{
u32 chid = chan->base.chid;
unsigned long flags;
@@ -487,10 +479,10 @@ nve0_fifo_recover(struct nve0_fifo_priv *priv, struct nouveau_engine *engine,
}
static int
-nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
+gk104_fifo_swmthd(struct gk104_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
{
- struct nve0_fifo_chan *chan = NULL;
- struct nouveau_handle *bind;
+ struct gk104_fifo_chan *chan = NULL;
+ struct nvkm_handle *bind;
unsigned long flags;
int ret = -EINVAL;
@@ -500,11 +492,11 @@ nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
if (unlikely(!chan))
goto out;
- bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
+ bind = nvkm_namedb_get_class(nv_namedb(chan), 0x906e);
if (likely(bind)) {
if (!mthd || !nv_call(bind->object, mthd, data))
ret = 0;
- nouveau_namedb_put(bind);
+ nvkm_namedb_put(bind);
}
out:
@@ -512,8 +504,8 @@ out:
return ret;
}
-static const struct nouveau_enum
-nve0_fifo_bind_reason[] = {
+static const struct nvkm_enum
+gk104_fifo_bind_reason[] = {
{ 0x01, "BIND_NOT_UNBOUND" },
{ 0x02, "SNOOP_WITHOUT_BAR1" },
{ 0x03, "UNBIND_WHILE_RUNNING" },
@@ -524,31 +516,31 @@ nve0_fifo_bind_reason[] = {
};
static void
-nve0_fifo_intr_bind(struct nve0_fifo_priv *priv)
+gk104_fifo_intr_bind(struct gk104_fifo_priv *priv)
{
u32 intr = nv_rd32(priv, 0x00252c);
u32 code = intr & 0x000000ff;
- const struct nouveau_enum *en;
+ const struct nvkm_enum *en;
char enunk[6] = "";
- en = nouveau_enum_find(nve0_fifo_bind_reason, code);
+ en = nvkm_enum_find(gk104_fifo_bind_reason, code);
if (!en)
snprintf(enunk, sizeof(enunk), "UNK%02x", code);
nv_error(priv, "BIND_ERROR [ %s ]\n", en ? en->name : enunk);
}
-static const struct nouveau_enum
-nve0_fifo_sched_reason[] = {
+static const struct nvkm_enum
+gk104_fifo_sched_reason[] = {
{ 0x0a, "CTXSW_TIMEOUT" },
{}
};
static void
-nve0_fifo_intr_sched_ctxsw(struct nve0_fifo_priv *priv)
+gk104_fifo_intr_sched_ctxsw(struct gk104_fifo_priv *priv)
{
- struct nouveau_engine *engine;
- struct nve0_fifo_chan *chan;
+ struct nvkm_engine *engine;
+ struct gk104_fifo_chan *chan;
u32 engn;
for (engn = 0; engn < ARRAY_SIZE(fifo_engine); engn++) {
@@ -565,22 +557,22 @@ nve0_fifo_intr_sched_ctxsw(struct nve0_fifo_priv *priv)
if (busy && chsw) {
if (!(chan = (void *)priv->base.channel[chid]))
continue;
- if (!(engine = nve0_fifo_engine(priv, engn)))
+ if (!(engine = gk104_fifo_engine(priv, engn)))
continue;
- nve0_fifo_recover(priv, engine, chan);
+ gk104_fifo_recover(priv, engine, chan);
}
}
}
static void
-nve0_fifo_intr_sched(struct nve0_fifo_priv *priv)
+gk104_fifo_intr_sched(struct gk104_fifo_priv *priv)
{
u32 intr = nv_rd32(priv, 0x00254c);
u32 code = intr & 0x000000ff;
- const struct nouveau_enum *en;
+ const struct nvkm_enum *en;
char enunk[6] = "";
- en = nouveau_enum_find(nve0_fifo_sched_reason, code);
+ en = nvkm_enum_find(gk104_fifo_sched_reason, code);
if (!en)
snprintf(enunk, sizeof(enunk), "UNK%02x", code);
@@ -588,7 +580,7 @@ nve0_fifo_intr_sched(struct nve0_fifo_priv *priv)
switch (code) {
case 0x0a:
- nve0_fifo_intr_sched_ctxsw(priv);
+ gk104_fifo_intr_sched_ctxsw(priv);
break;
default:
break;
@@ -596,7 +588,7 @@ nve0_fifo_intr_sched(struct nve0_fifo_priv *priv)
}
static void
-nve0_fifo_intr_chsw(struct nve0_fifo_priv *priv)
+gk104_fifo_intr_chsw(struct gk104_fifo_priv *priv)
{
u32 stat = nv_rd32(priv, 0x00256c);
nv_error(priv, "CHSW_ERROR 0x%08x\n", stat);
@@ -604,14 +596,14 @@ nve0_fifo_intr_chsw(struct nve0_fifo_priv *priv)
}
static void
-nve0_fifo_intr_dropped_fault(struct nve0_fifo_priv *priv)
+gk104_fifo_intr_dropped_fault(struct gk104_fifo_priv *priv)
{
u32 stat = nv_rd32(priv, 0x00259c);
nv_error(priv, "DROPPED_MMU_FAULT 0x%08x\n", stat);
}
-static const struct nouveau_enum
-nve0_fifo_fault_engine[] = {
+static const struct nvkm_enum
+gk104_fifo_fault_engine[] = {
{ 0x00, "GR", NULL, NVDEV_ENGINE_GR },
{ 0x03, "IFB", NULL, NVDEV_ENGINE_IFB },
{ 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
@@ -631,8 +623,8 @@ nve0_fifo_fault_engine[] = {
{}
};
-static const struct nouveau_enum
-nve0_fifo_fault_reason[] = {
+static const struct nvkm_enum
+gk104_fifo_fault_reason[] = {
{ 0x00, "PDE" },
{ 0x01, "PDE_SIZE" },
{ 0x02, "PTE" },
@@ -652,8 +644,8 @@ nve0_fifo_fault_reason[] = {
{}
};
-static const struct nouveau_enum
-nve0_fifo_fault_hubclient[] = {
+static const struct nvkm_enum
+gk104_fifo_fault_hubclient[] = {
{ 0x00, "VIP" },
{ 0x01, "CE0" },
{ 0x02, "CE1" },
@@ -689,8 +681,8 @@ nve0_fifo_fault_hubclient[] = {
{}
};
-static const struct nouveau_enum
-nve0_fifo_fault_gpcclient[] = {
+static const struct nvkm_enum
+gk104_fifo_fault_gpcclient[] = {
{ 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" },
{ 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" },
{ 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" },
@@ -716,7 +708,7 @@ nve0_fifo_fault_gpcclient[] = {
};
static void
-nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit)
+gk104_fifo_intr_fault(struct gk104_fifo_priv *priv, int unit)
{
u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10));
u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10));
@@ -727,19 +719,19 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit)
u32 write = (stat & 0x00000080);
u32 hub = (stat & 0x00000040);
u32 reason = (stat & 0x0000000f);
- struct nouveau_object *engctx = NULL, *object;
- struct nouveau_engine *engine = NULL;
- const struct nouveau_enum *er, *eu, *ec;
+ struct nvkm_object *engctx = NULL, *object;
+ struct nvkm_engine *engine = NULL;
+ const struct nvkm_enum *er, *eu, *ec;
char erunk[6] = "";
char euunk[6] = "";
char ecunk[6] = "";
char gpcid[3] = "";
- er = nouveau_enum_find(nve0_fifo_fault_reason, reason);
+ er = nvkm_enum_find(gk104_fifo_fault_reason, reason);
if (!er)
snprintf(erunk, sizeof(erunk), "UNK%02X", reason);
- eu = nouveau_enum_find(nve0_fifo_fault_engine, unit);
+ eu = nvkm_enum_find(gk104_fifo_fault_engine, unit);
if (eu) {
switch (eu->data2) {
case NVDEV_SUBDEV_BAR:
@@ -752,9 +744,9 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit)
nv_mask(priv, 0x001718, 0x00000000, 0x00000000);
break;
default:
- engine = nouveau_engine(priv, eu->data2);
+ engine = nvkm_engine(priv, eu->data2);
if (engine)
- engctx = nouveau_engctx_get(engine, inst);
+ engctx = nvkm_engctx_get(engine, inst);
break;
}
} else {
@@ -762,9 +754,9 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit)
}
if (hub) {
- ec = nouveau_enum_find(nve0_fifo_fault_hubclient, client);
+ ec = nvkm_enum_find(gk104_fifo_fault_hubclient, client);
} else {
- ec = nouveau_enum_find(nve0_fifo_fault_gpcclient, client);
+ ec = nvkm_enum_find(gk104_fifo_fault_gpcclient, client);
snprintf(gpcid, sizeof(gpcid), "%d", gpc);
}
@@ -776,22 +768,22 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit)
(u64)vahi << 32 | valo, er ? er->name : erunk,
eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/",
ec ? ec->name : ecunk, (u64)inst << 12,
- nouveau_client_name(engctx));
+ nvkm_client_name(engctx));
object = engctx;
while (object) {
switch (nv_mclass(object)) {
case KEPLER_CHANNEL_GPFIFO_A:
- nve0_fifo_recover(priv, engine, (void *)object);
+ gk104_fifo_recover(priv, engine, (void *)object);
break;
}
object = object->parent;
}
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
-static const struct nouveau_bitfield nve0_fifo_pbdma_intr_0[] = {
+static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = {
{ 0x00000001, "MEMREQ" },
{ 0x00000002, "MEMACK_TIMEOUT" },
{ 0x00000004, "MEMACK_EXTRA" },
@@ -826,7 +818,7 @@ static const struct nouveau_bitfield nve0_fifo_pbdma_intr_0[] = {
};
static void
-nve0_fifo_intr_pbdma_0(struct nve0_fifo_priv *priv, int unit)
+gk104_fifo_intr_pbdma_0(struct gk104_fifo_priv *priv, int unit)
{
u32 mask = nv_rd32(priv, 0x04010c + (unit * 0x2000));
u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)) & mask;
@@ -838,26 +830,26 @@ nve0_fifo_intr_pbdma_0(struct nve0_fifo_priv *priv, int unit)
u32 show = stat;
if (stat & 0x00800000) {
- if (!nve0_fifo_swmthd(priv, chid, mthd, data))
+ if (!gk104_fifo_swmthd(priv, chid, mthd, data))
show &= ~0x00800000;
nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
}
if (show) {
nv_error(priv, "PBDMA%d:", unit);
- nouveau_bitfield_print(nve0_fifo_pbdma_intr_0, show);
+ nvkm_bitfield_print(gk104_fifo_pbdma_intr_0, show);
pr_cont("\n");
nv_error(priv,
"PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
unit, chid,
- nouveau_client_name_for_fifo_chid(&priv->base, chid),
+ nvkm_client_name_for_fifo_chid(&priv->base, chid),
subc, mthd, data);
}
nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
}
-static const struct nouveau_bitfield nve0_fifo_pbdma_intr_1[] = {
+static const struct nvkm_bitfield gk104_fifo_pbdma_intr_1[] = {
{ 0x00000001, "HCE_RE_ILLEGAL_OP" },
{ 0x00000002, "HCE_RE_ALIGNB" },
{ 0x00000004, "HCE_PRIV" },
@@ -867,7 +859,7 @@ static const struct nouveau_bitfield nve0_fifo_pbdma_intr_1[] = {
};
static void
-nve0_fifo_intr_pbdma_1(struct nve0_fifo_priv *priv, int unit)
+gk104_fifo_intr_pbdma_1(struct gk104_fifo_priv *priv, int unit)
{
u32 mask = nv_rd32(priv, 0x04014c + (unit * 0x2000));
u32 stat = nv_rd32(priv, 0x040148 + (unit * 0x2000)) & mask;
@@ -875,7 +867,7 @@ nve0_fifo_intr_pbdma_1(struct nve0_fifo_priv *priv, int unit)
if (stat) {
nv_error(priv, "PBDMA%d:", unit);
- nouveau_bitfield_print(nve0_fifo_pbdma_intr_1, stat);
+ nvkm_bitfield_print(gk104_fifo_pbdma_intr_1, stat);
pr_cont("\n");
nv_error(priv, "PBDMA%d: ch %d %08x %08x\n", unit, chid,
nv_rd32(priv, 0x040150 + (unit * 0x2000)),
@@ -886,7 +878,7 @@ nve0_fifo_intr_pbdma_1(struct nve0_fifo_priv *priv, int unit)
}
static void
-nve0_fifo_intr_runlist(struct nve0_fifo_priv *priv)
+gk104_fifo_intr_runlist(struct gk104_fifo_priv *priv)
{
u32 mask = nv_rd32(priv, 0x002a00);
while (mask) {
@@ -898,20 +890,20 @@ nve0_fifo_intr_runlist(struct nve0_fifo_priv *priv)
}
static void
-nve0_fifo_intr_engine(struct nve0_fifo_priv *priv)
+gk104_fifo_intr_engine(struct gk104_fifo_priv *priv)
{
- nouveau_fifo_uevent(&priv->base);
+ nvkm_fifo_uevent(&priv->base);
}
static void
-nve0_fifo_intr(struct nouveau_subdev *subdev)
+gk104_fifo_intr(struct nvkm_subdev *subdev)
{
- struct nve0_fifo_priv *priv = (void *)subdev;
+ struct gk104_fifo_priv *priv = (void *)subdev;
u32 mask = nv_rd32(priv, 0x002140);
u32 stat = nv_rd32(priv, 0x002100) & mask;
if (stat & 0x00000001) {
- nve0_fifo_intr_bind(priv);
+ gk104_fifo_intr_bind(priv);
nv_wr32(priv, 0x002100, 0x00000001);
stat &= ~0x00000001;
}
@@ -923,13 +915,13 @@ nve0_fifo_intr(struct nouveau_subdev *subdev)
}
if (stat & 0x00000100) {
- nve0_fifo_intr_sched(priv);
+ gk104_fifo_intr_sched(priv);
nv_wr32(priv, 0x002100, 0x00000100);
stat &= ~0x00000100;
}
if (stat & 0x00010000) {
- nve0_fifo_intr_chsw(priv);
+ gk104_fifo_intr_chsw(priv);
nv_wr32(priv, 0x002100, 0x00010000);
stat &= ~0x00010000;
}
@@ -947,7 +939,7 @@ nve0_fifo_intr(struct nouveau_subdev *subdev)
}
if (stat & 0x08000000) {
- nve0_fifo_intr_dropped_fault(priv);
+ gk104_fifo_intr_dropped_fault(priv);
nv_wr32(priv, 0x002100, 0x08000000);
stat &= ~0x08000000;
}
@@ -956,7 +948,7 @@ nve0_fifo_intr(struct nouveau_subdev *subdev)
u32 mask = nv_rd32(priv, 0x00259c);
while (mask) {
u32 unit = __ffs(mask);
- nve0_fifo_intr_fault(priv, unit);
+ gk104_fifo_intr_fault(priv, unit);
nv_wr32(priv, 0x00259c, (1 << unit));
mask &= ~(1 << unit);
}
@@ -967,8 +959,8 @@ nve0_fifo_intr(struct nouveau_subdev *subdev)
u32 mask = nv_rd32(priv, 0x0025a0);
while (mask) {
u32 unit = __ffs(mask);
- nve0_fifo_intr_pbdma_0(priv, unit);
- nve0_fifo_intr_pbdma_1(priv, unit);
+ gk104_fifo_intr_pbdma_0(priv, unit);
+ gk104_fifo_intr_pbdma_1(priv, unit);
nv_wr32(priv, 0x0025a0, (1 << unit));
mask &= ~(1 << unit);
}
@@ -976,13 +968,13 @@ nve0_fifo_intr(struct nouveau_subdev *subdev)
}
if (stat & 0x40000000) {
- nve0_fifo_intr_runlist(priv);
+ gk104_fifo_intr_runlist(priv);
stat &= ~0x40000000;
}
if (stat & 0x80000000) {
nv_wr32(priv, 0x002100, 0x80000000);
- nve0_fifo_intr_engine(priv);
+ gk104_fifo_intr_engine(priv);
stat &= ~0x80000000;
}
@@ -994,33 +986,33 @@ nve0_fifo_intr(struct nouveau_subdev *subdev)
}
static void
-nve0_fifo_uevent_init(struct nvkm_event *event, int type, int index)
+gk104_fifo_uevent_init(struct nvkm_event *event, int type, int index)
{
- struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
+ struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
nv_mask(fifo, 0x002140, 0x80000000, 0x80000000);
}
static void
-nve0_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
+gk104_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
{
- struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
+ struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
nv_mask(fifo, 0x002140, 0x80000000, 0x00000000);
}
static const struct nvkm_event_func
-nve0_fifo_uevent_func = {
- .ctor = nouveau_fifo_uevent_ctor,
- .init = nve0_fifo_uevent_init,
- .fini = nve0_fifo_uevent_fini,
+gk104_fifo_uevent_func = {
+ .ctor = nvkm_fifo_uevent_ctor,
+ .init = gk104_fifo_uevent_init,
+ .fini = gk104_fifo_uevent_fini,
};
int
-nve0_fifo_fini(struct nouveau_object *object, bool suspend)
+gk104_fifo_fini(struct nvkm_object *object, bool suspend)
{
- struct nve0_fifo_priv *priv = (void *)object;
+ struct gk104_fifo_priv *priv = (void *)object;
int ret;
- ret = nouveau_fifo_fini(&priv->base, suspend);
+ ret = nvkm_fifo_fini(&priv->base, suspend);
if (ret)
return ret;
@@ -1030,12 +1022,12 @@ nve0_fifo_fini(struct nouveau_object *object, bool suspend)
}
int
-nve0_fifo_init(struct nouveau_object *object)
+gk104_fifo_init(struct nvkm_object *object)
{
- struct nve0_fifo_priv *priv = (void *)object;
+ struct gk104_fifo_priv *priv = (void *)object;
int ret, i;
- ret = nouveau_fifo_init(&priv->base);
+ ret = nvkm_fifo_init(&priv->base);
if (ret)
return ret;
@@ -1065,82 +1057,82 @@ nve0_fifo_init(struct nouveau_object *object)
}
void
-nve0_fifo_dtor(struct nouveau_object *object)
+gk104_fifo_dtor(struct nvkm_object *object)
{
- struct nve0_fifo_priv *priv = (void *)object;
+ struct gk104_fifo_priv *priv = (void *)object;
int i;
- nouveau_gpuobj_unmap(&priv->user.bar);
- nouveau_gpuobj_ref(NULL, &priv->user.mem);
+ nvkm_gpuobj_unmap(&priv->user.bar);
+ nvkm_gpuobj_ref(NULL, &priv->user.mem);
for (i = 0; i < FIFO_ENGINE_NR; i++) {
- nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[1]);
- nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[0]);
+ nvkm_gpuobj_ref(NULL, &priv->engine[i].runlist[1]);
+ nvkm_gpuobj_ref(NULL, &priv->engine[i].runlist[0]);
}
- nouveau_fifo_destroy(&priv->base);
+ nvkm_fifo_destroy(&priv->base);
}
int
-nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nve0_fifo_impl *impl = (void *)oclass;
- struct nve0_fifo_priv *priv;
+ struct gk104_fifo_impl *impl = (void *)oclass;
+ struct gk104_fifo_priv *priv;
int ret, i;
- ret = nouveau_fifo_create(parent, engine, oclass, 0,
- impl->channels - 1, &priv);
+ ret = nvkm_fifo_create(parent, engine, oclass, 0,
+ impl->channels - 1, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- INIT_WORK(&priv->fault, nve0_fifo_recover_work);
+ INIT_WORK(&priv->fault, gk104_fifo_recover_work);
for (i = 0; i < FIFO_ENGINE_NR; i++) {
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
- 0, &priv->engine[i].runlist[0]);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
+ 0, &priv->engine[i].runlist[0]);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
- 0, &priv->engine[i].runlist[1]);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
+ 0, &priv->engine[i].runlist[1]);
if (ret)
return ret;
init_waitqueue_head(&priv->engine[i].wait);
}
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200,
- 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200,
+ 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem);
if (ret)
return ret;
- ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
- &priv->user.bar);
+ ret = nvkm_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
+ &priv->user.bar);
if (ret)
return ret;
- ret = nvkm_event_init(&nve0_fifo_uevent_func, 1, 1, &priv->base.uevent);
+ ret = nvkm_event_init(&gk104_fifo_uevent_func, 1, 1, &priv->base.uevent);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000100;
- nv_subdev(priv)->intr = nve0_fifo_intr;
- nv_engine(priv)->cclass = &nve0_fifo_cclass;
- nv_engine(priv)->sclass = nve0_fifo_sclass;
+ nv_subdev(priv)->intr = gk104_fifo_intr;
+ nv_engine(priv)->cclass = &gk104_fifo_cclass;
+ nv_engine(priv)->sclass = gk104_fifo_sclass;
return 0;
}
-struct nouveau_oclass *
-nve0_fifo_oclass = &(struct nve0_fifo_impl) {
+struct nvkm_oclass *
+gk104_fifo_oclass = &(struct gk104_fifo_impl) {
.base.handle = NV_ENGINE(FIFO, 0xe0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_fifo_ctor,
- .dtor = nve0_fifo_dtor,
- .init = nve0_fifo_init,
- .fini = nve0_fifo_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_fifo_ctor,
+ .dtor = gk104_fifo_dtor,
+ .init = gk104_fifo_init,
+ .fini = gk104_fifo_fini,
},
.channels = 4096,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
new file mode 100644
index 000000000000..3046e00ed6ba
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
@@ -0,0 +1,16 @@
+#ifndef __NVKM_FIFO_NVE0_H__
+#define __NVKM_FIFO_NVE0_H__
+#include <engine/fifo.h>
+
+int gk104_fifo_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void gk104_fifo_dtor(struct nvkm_object *);
+int gk104_fifo_init(struct nvkm_object *);
+int gk104_fifo_fini(struct nvkm_object *, bool);
+
+struct gk104_fifo_impl {
+ struct nvkm_oclass base;
+ u32 channels;
+};
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
similarity index 83%
rename from drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv108.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
index 09362a51ba57..927092217a06 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv108.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
@@ -21,17 +21,16 @@
*
* Authors: Ben Skeggs
*/
+#include "gk104.h"
-#include "nve0.h"
-
-struct nouveau_oclass *
-nv108_fifo_oclass = &(struct nve0_fifo_impl) {
+struct nvkm_oclass *
+gk208_fifo_oclass = &(struct gk104_fifo_impl) {
.base.handle = NV_ENGINE(FIFO, 0x08),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_fifo_ctor,
- .dtor = nve0_fifo_dtor,
- .init = nve0_fifo_init,
- .fini = _nouveau_fifo_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_fifo_ctor,
+ .dtor = gk104_fifo_dtor,
+ .init = gk104_fifo_init,
+ .fini = _nvkm_fifo_fini,
},
.channels = 1024,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
index 327456eae963..b30dc87a1357 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
@@ -19,17 +19,16 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+#include "gk104.h"
-#include "nve0.h"
-
-struct nouveau_oclass *
-gk20a_fifo_oclass = &(struct nve0_fifo_impl) {
+struct nvkm_oclass *
+gk20a_fifo_oclass = &(struct gk104_fifo_impl) {
.base.handle = NV_ENGINE(FIFO, 0xea),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_fifo_ctor,
- .dtor = nve0_fifo_dtor,
- .init = nve0_fifo_init,
- .fini = nve0_fifo_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_fifo_ctor,
+ .dtor = gk104_fifo_dtor,
+ .init = gk104_fifo_init,
+ .fini = gk104_fifo_fini,
},
.channels = 128,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
index 1b384bd5994e..b038b6eb51db 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
@@ -21,25 +21,18 @@
*
* Authors: Ben Skeggs
*/
+#include "nv04.h"
#include <core/client.h>
#include <core/device.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
#include <core/engctx.h>
-#include <core/namedb.h>
#include <core/handle.h>
#include <core/ramht.h>
-#include <core/event.h>
-
-#include <subdev/instmem.h>
#include <subdev/instmem/nv04.h>
#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <engine/fifo.h>
-
-#include "nv04.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
static struct ramfc_desc
nv04_ramfc[] = {
@@ -59,8 +52,8 @@ nv04_ramfc[] = {
******************************************************************************/
int
-nv04_fifo_object_attach(struct nouveau_object *parent,
- struct nouveau_object *object, u32 handle)
+nv04_fifo_object_attach(struct nvkm_object *parent,
+ struct nvkm_object *object, u32 handle)
{
struct nv04_fifo_priv *priv = (void *)parent->engine;
struct nv04_fifo_chan *chan = (void *)parent;
@@ -91,33 +84,33 @@ nv04_fifo_object_attach(struct nouveau_object *parent,
context |= chid << 24;
mutex_lock(&nv_subdev(priv)->mutex);
- ret = nouveau_ramht_insert(priv->ramht, chid, handle, context);
+ ret = nvkm_ramht_insert(priv->ramht, chid, handle, context);
mutex_unlock(&nv_subdev(priv)->mutex);
return ret;
}
void
-nv04_fifo_object_detach(struct nouveau_object *parent, int cookie)
+nv04_fifo_object_detach(struct nvkm_object *parent, int cookie)
{
struct nv04_fifo_priv *priv = (void *)parent->engine;
mutex_lock(&nv_subdev(priv)->mutex);
- nouveau_ramht_remove(priv->ramht, cookie);
+ nvkm_ramht_remove(priv->ramht, cookie);
mutex_unlock(&nv_subdev(priv)->mutex);
}
int
-nv04_fifo_context_attach(struct nouveau_object *parent,
- struct nouveau_object *object)
+nv04_fifo_context_attach(struct nvkm_object *parent,
+ struct nvkm_object *object)
{
- nv_engctx(object)->addr = nouveau_fifo_chan(parent)->chid;
+ nv_engctx(object)->addr = nvkm_fifo_chan(parent)->chid;
return 0;
}
static int
-nv04_fifo_chan_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_fifo_chan_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv03_channel_dma_v0 v0;
@@ -134,11 +127,11 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent,
} else
return ret;
- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
- 0x10000, args->v0.pushbuf,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_GR), &chan);
+ ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
+ 0x10000, args->v0.pushbuf,
+ (1ULL << NVDEV_ENGINE_DMAOBJ) |
+ (1ULL << NVDEV_ENGINE_SW) |
+ (1ULL << NVDEV_ENGINE_GR), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -164,7 +157,7 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent,
}
void
-nv04_fifo_chan_dtor(struct nouveau_object *object)
+nv04_fifo_chan_dtor(struct nvkm_object *object)
{
struct nv04_fifo_priv *priv = (void *)object->engine;
struct nv04_fifo_chan *chan = (void *)object;
@@ -174,11 +167,11 @@ nv04_fifo_chan_dtor(struct nouveau_object *object)
nv_wo32(priv->ramfc, chan->ramfc + c->ctxp, 0x00000000);
} while ((++c)->bits);
- nouveau_fifo_channel_destroy(&chan->base);
+ nvkm_fifo_channel_destroy(&chan->base);
}
int
-nv04_fifo_chan_init(struct nouveau_object *object)
+nv04_fifo_chan_init(struct nvkm_object *object)
{
struct nv04_fifo_priv *priv = (void *)object->engine;
struct nv04_fifo_chan *chan = (void *)object;
@@ -186,7 +179,7 @@ nv04_fifo_chan_init(struct nouveau_object *object)
unsigned long flags;
int ret;
- ret = nouveau_fifo_channel_init(&chan->base);
+ ret = nvkm_fifo_channel_init(&chan->base);
if (ret)
return ret;
@@ -197,11 +190,11 @@ nv04_fifo_chan_init(struct nouveau_object *object)
}
int
-nv04_fifo_chan_fini(struct nouveau_object *object, bool suspend)
+nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend)
{
struct nv04_fifo_priv *priv = (void *)object->engine;
struct nv04_fifo_chan *chan = (void *)object;
- struct nouveau_gpuobj *fctx = priv->ramfc;
+ struct nvkm_gpuobj *fctx = priv->ramfc;
struct ramfc_desc *c;
unsigned long flags;
u32 data = chan->ramfc;
@@ -244,22 +237,22 @@ nv04_fifo_chan_fini(struct nouveau_object *object, bool suspend)
nv_wr32(priv, NV03_PFIFO_CACHES, 1);
spin_unlock_irqrestore(&priv->base.lock, flags);
- return nouveau_fifo_channel_fini(&chan->base, suspend);
+ return nvkm_fifo_channel_fini(&chan->base, suspend);
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
nv04_fifo_ofuncs = {
.ctor = nv04_fifo_chan_ctor,
.dtor = nv04_fifo_chan_dtor,
.init = nv04_fifo_chan_init,
.fini = nv04_fifo_chan_fini,
- .map = _nouveau_fifo_channel_map,
- .rd32 = _nouveau_fifo_channel_rd32,
- .wr32 = _nouveau_fifo_channel_wr32,
- .ntfy = _nouveau_fifo_channel_ntfy
+ .map = _nvkm_fifo_channel_map,
+ .rd32 = _nvkm_fifo_channel_rd32,
+ .wr32 = _nvkm_fifo_channel_wr32,
+ .ntfy = _nvkm_fifo_channel_ntfy
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv04_fifo_sclass[] = {
{ NV03_CHANNEL_DMA, &nv04_fifo_ofuncs },
{}
@@ -270,16 +263,16 @@ nv04_fifo_sclass[] = {
******************************************************************************/
int
-nv04_fifo_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_fifo_context_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_fifo_base *base;
int ret;
- ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
- 0x1000, NVOBJ_FLAG_HEAP, &base);
+ ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
+ 0x1000, NVOBJ_FLAG_HEAP, &base);
*pobject = nv_object(base);
if (ret)
return ret;
@@ -287,16 +280,16 @@ nv04_fifo_context_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv04_fifo_cclass = {
.handle = NV_ENGCTX(FIFO, 0x04),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fifo_context_ctor,
- .dtor = _nouveau_fifo_context_dtor,
- .init = _nouveau_fifo_context_init,
- .fini = _nouveau_fifo_context_fini,
- .rd32 = _nouveau_fifo_context_rd32,
- .wr32 = _nouveau_fifo_context_wr32,
+ .dtor = _nvkm_fifo_context_dtor,
+ .init = _nvkm_fifo_context_init,
+ .fini = _nvkm_fifo_context_fini,
+ .rd32 = _nvkm_fifo_context_rd32,
+ .wr32 = _nvkm_fifo_context_wr32,
},
};
@@ -305,7 +298,7 @@ nv04_fifo_cclass = {
******************************************************************************/
void
-nv04_fifo_pause(struct nouveau_fifo *pfifo, unsigned long *pflags)
+nv04_fifo_pause(struct nvkm_fifo *pfifo, unsigned long *pflags)
__acquires(priv->base.lock)
{
struct nv04_fifo_priv *priv = (void *)pfifo;
@@ -338,7 +331,7 @@ __acquires(priv->base.lock)
}
void
-nv04_fifo_start(struct nouveau_fifo *pfifo, unsigned long *pflags)
+nv04_fifo_start(struct nvkm_fifo *pfifo, unsigned long *pflags)
__releases(priv->base.lock)
{
struct nv04_fifo_priv *priv = (void *)pfifo;
@@ -364,7 +357,7 @@ static bool
nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data)
{
struct nv04_fifo_chan *chan = NULL;
- struct nouveau_handle *bind;
+ struct nvkm_handle *bind;
const int subc = (addr >> 13) & 0x7;
const int mthd = addr & 0x1ffc;
bool handled = false;
@@ -379,7 +372,7 @@ nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data)
switch (mthd) {
case 0x0000:
- bind = nouveau_namedb_get(nv_namedb(chan), data);
+ bind = nvkm_namedb_get(nv_namedb(chan), data);
if (unlikely(!bind))
break;
@@ -391,18 +384,18 @@ nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data)
nv_mask(priv, NV04_PFIFO_CACHE1_ENGINE, engine, 0);
}
- nouveau_namedb_put(bind);
+ nvkm_namedb_put(bind);
break;
default:
engine = nv_rd32(priv, NV04_PFIFO_CACHE1_ENGINE);
if (unlikely(((engine >> (subc * 4)) & 0xf) != 0))
break;
- bind = nouveau_namedb_get(nv_namedb(chan), chan->subc[subc]);
+ bind = nvkm_namedb_get(nv_namedb(chan), chan->subc[subc]);
if (likely(bind)) {
if (!nv_call(bind->object, mthd, data))
handled = true;
- nouveau_namedb_put(bind);
+ nvkm_namedb_put(bind);
}
break;
}
@@ -413,8 +406,8 @@ out:
}
static void
-nv04_fifo_cache_error(struct nouveau_device *device,
- struct nv04_fifo_priv *priv, u32 chid, u32 get)
+nv04_fifo_cache_error(struct nvkm_device *device,
+ struct nv04_fifo_priv *priv, u32 chid, u32 get)
{
u32 mthd, data;
int ptr;
@@ -436,7 +429,7 @@ nv04_fifo_cache_error(struct nouveau_device *device,
if (!nv04_fifo_swmthd(priv, chid, mthd, data)) {
const char *client_name =
- nouveau_client_name_for_fifo_chid(&priv->base, chid);
+ nvkm_client_name_for_fifo_chid(&priv->base, chid);
nv_error(priv,
"CACHE_ERROR - ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
chid, client_name, (mthd >> 13) & 7, mthd & 0x1ffc,
@@ -459,8 +452,8 @@ nv04_fifo_cache_error(struct nouveau_device *device,
}
static void
-nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv,
- u32 chid)
+nv04_fifo_dma_pusher(struct nvkm_device *device,
+ struct nv04_fifo_priv *priv, u32 chid)
{
const char *client_name;
u32 dma_get = nv_rd32(priv, 0x003244);
@@ -468,7 +461,7 @@ nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv,
u32 push = nv_rd32(priv, 0x003220);
u32 state = nv_rd32(priv, 0x003228);
- client_name = nouveau_client_name_for_fifo_chid(&priv->base, chid);
+ client_name = nvkm_client_name_for_fifo_chid(&priv->base, chid);
if (device->card_type == NV_50) {
u32 ho_get = nv_rd32(priv, 0x003328);
@@ -505,9 +498,9 @@ nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv,
}
void
-nv04_fifo_intr(struct nouveau_subdev *subdev)
+nv04_fifo_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_device *device = nv_device(subdev);
+ struct nvkm_device *device = nv_device(subdev);
struct nv04_fifo_priv *priv = (void *)subdev;
uint32_t status, reassign;
int cnt = 0;
@@ -553,7 +546,7 @@ nv04_fifo_intr(struct nouveau_subdev *subdev)
if (status & 0x40000000) {
nv_wr32(priv, 0x002100, 0x40000000);
- nouveau_fifo_uevent(&priv->base);
+ nvkm_fifo_uevent(&priv->base);
status &= ~0x40000000;
}
}
@@ -578,22 +571,22 @@ nv04_fifo_intr(struct nouveau_subdev *subdev)
}
static int
-nv04_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_instmem_priv *imem = nv04_instmem(parent);
struct nv04_fifo_priv *priv;
int ret;
- ret = nouveau_fifo_create(parent, engine, oclass, 0, 15, &priv);
+ ret = nvkm_fifo_create(parent, engine, oclass, 0, 15, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- nouveau_ramht_ref(imem->ramht, &priv->ramht);
- nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
- nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
+ nvkm_ramht_ref(imem->ramht, &priv->ramht);
+ nvkm_gpuobj_ref(imem->ramro, &priv->ramro);
+ nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc);
nv_subdev(priv)->unit = 0x00000100;
nv_subdev(priv)->intr = nv04_fifo_intr;
@@ -606,22 +599,22 @@ nv04_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
void
-nv04_fifo_dtor(struct nouveau_object *object)
+nv04_fifo_dtor(struct nvkm_object *object)
{
struct nv04_fifo_priv *priv = (void *)object;
- nouveau_gpuobj_ref(NULL, &priv->ramfc);
- nouveau_gpuobj_ref(NULL, &priv->ramro);
- nouveau_ramht_ref(NULL, &priv->ramht);
- nouveau_fifo_destroy(&priv->base);
+ nvkm_gpuobj_ref(NULL, &priv->ramfc);
+ nvkm_gpuobj_ref(NULL, &priv->ramro);
+ nvkm_ramht_ref(NULL, &priv->ramht);
+ nvkm_fifo_destroy(&priv->base);
}
int
-nv04_fifo_init(struct nouveau_object *object)
+nv04_fifo_init(struct nvkm_object *object)
{
struct nv04_fifo_priv *priv = (void *)object;
int ret;
- ret = nouveau_fifo_init(&priv->base);
+ ret = nvkm_fifo_init(&priv->base);
if (ret)
return ret;
@@ -645,13 +638,13 @@ nv04_fifo_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
-nv04_fifo_oclass = &(struct nouveau_oclass) {
+struct nvkm_oclass *
+nv04_fifo_oclass = &(struct nvkm_oclass) {
.handle = NV_ENGINE(FIFO, 0x04),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fifo_ctor,
.dtor = nv04_fifo_dtor,
.init = nv04_fifo_init,
- .fini = _nouveau_fifo_fini,
+ .fini = _nvkm_fifo_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h
index 496a4b4fdfaf..e0e0c47cb4ca 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h
@@ -1,6 +1,5 @@
#ifndef __NV04_FIFO_H__
#define __NV04_FIFO_H__
-
#include <engine/fifo.h>
#define NV04_PFIFO_DELAY_0 0x00002040
@@ -141,38 +140,36 @@ struct ramfc_desc {
};
struct nv04_fifo_priv {
- struct nouveau_fifo base;
+ struct nvkm_fifo base;
struct ramfc_desc *ramfc_desc;
- struct nouveau_ramht *ramht;
- struct nouveau_gpuobj *ramro;
- struct nouveau_gpuobj *ramfc;
+ struct nvkm_ramht *ramht;
+ struct nvkm_gpuobj *ramro;
+ struct nvkm_gpuobj *ramfc;
};
struct nv04_fifo_base {
- struct nouveau_fifo_base base;
+ struct nvkm_fifo_base base;
};
struct nv04_fifo_chan {
- struct nouveau_fifo_chan base;
+ struct nvkm_fifo_chan base;
u32 subc[8];
u32 ramfc;
};
-int nv04_fifo_object_attach(struct nouveau_object *,
- struct nouveau_object *, u32);
-void nv04_fifo_object_detach(struct nouveau_object *, int);
+int nv04_fifo_object_attach(struct nvkm_object *, struct nvkm_object *, u32);
+void nv04_fifo_object_detach(struct nvkm_object *, int);
-void nv04_fifo_chan_dtor(struct nouveau_object *);
-int nv04_fifo_chan_init(struct nouveau_object *);
-int nv04_fifo_chan_fini(struct nouveau_object *, bool suspend);
+void nv04_fifo_chan_dtor(struct nvkm_object *);
+int nv04_fifo_chan_init(struct nvkm_object *);
+int nv04_fifo_chan_fini(struct nvkm_object *, bool suspend);
-int nv04_fifo_context_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-
-void nv04_fifo_dtor(struct nouveau_object *);
-int nv04_fifo_init(struct nouveau_object *);
-void nv04_fifo_pause(struct nouveau_fifo *, unsigned long *);
-void nv04_fifo_start(struct nouveau_fifo *, unsigned long *);
+int nv04_fifo_context_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void nv04_fifo_dtor(struct nvkm_object *);
+int nv04_fifo_init(struct nvkm_object *);
+void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *);
+void nv04_fifo_start(struct nvkm_fifo *, unsigned long *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
index 2a32add51c81..48ce4af6f543 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
@@ -21,20 +21,15 @@
*
* Authors: Ben Skeggs
*/
+#include "nv04.h"
#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
#include <core/engctx.h>
#include <core/ramht.h>
-
-#include <subdev/instmem.h>
#include <subdev/instmem/nv04.h>
-#include <subdev/fb.h>
-#include <engine/fifo.h>
-
-#include "nv04.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
static struct ramfc_desc
nv10_ramfc[] = {
@@ -55,10 +50,10 @@ nv10_ramfc[] = {
******************************************************************************/
static int
-nv10_fifo_chan_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv10_fifo_chan_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv03_channel_dma_v0 v0;
@@ -75,11 +70,11 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent,
} else
return ret;
- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
- 0x10000, args->v0.pushbuf,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_GR), &chan);
+ ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
+ 0x10000, args->v0.pushbuf,
+ (1ULL << NVDEV_ENGINE_DMAOBJ) |
+ (1ULL << NVDEV_ENGINE_SW) |
+ (1ULL << NVDEV_ENGINE_GR), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -104,19 +99,19 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
nv10_fifo_ofuncs = {
.ctor = nv10_fifo_chan_ctor,
.dtor = nv04_fifo_chan_dtor,
.init = nv04_fifo_chan_init,
.fini = nv04_fifo_chan_fini,
- .map = _nouveau_fifo_channel_map,
- .rd32 = _nouveau_fifo_channel_rd32,
- .wr32 = _nouveau_fifo_channel_wr32,
- .ntfy = _nouveau_fifo_channel_ntfy
+ .map = _nvkm_fifo_channel_map,
+ .rd32 = _nvkm_fifo_channel_rd32,
+ .wr32 = _nvkm_fifo_channel_wr32,
+ .ntfy = _nvkm_fifo_channel_ntfy
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv10_fifo_sclass[] = {
{ NV10_CHANNEL_DMA, &nv10_fifo_ofuncs },
{}
@@ -126,16 +121,16 @@ nv10_fifo_sclass[] = {
* FIFO context - basically just the instmem reserved for the channel
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
nv10_fifo_cclass = {
.handle = NV_ENGCTX(FIFO, 0x10),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fifo_context_ctor,
- .dtor = _nouveau_fifo_context_dtor,
- .init = _nouveau_fifo_context_init,
- .fini = _nouveau_fifo_context_fini,
- .rd32 = _nouveau_fifo_context_rd32,
- .wr32 = _nouveau_fifo_context_wr32,
+ .dtor = _nvkm_fifo_context_dtor,
+ .init = _nvkm_fifo_context_init,
+ .fini = _nvkm_fifo_context_fini,
+ .rd32 = _nvkm_fifo_context_rd32,
+ .wr32 = _nvkm_fifo_context_wr32,
},
};
@@ -144,22 +139,22 @@ nv10_fifo_cclass = {
******************************************************************************/
static int
-nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_instmem_priv *imem = nv04_instmem(parent);
struct nv04_fifo_priv *priv;
int ret;
- ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
+ ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- nouveau_ramht_ref(imem->ramht, &priv->ramht);
- nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
- nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
+ nvkm_ramht_ref(imem->ramht, &priv->ramht);
+ nvkm_gpuobj_ref(imem->ramro, &priv->ramro);
+ nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc);
nv_subdev(priv)->unit = 0x00000100;
nv_subdev(priv)->intr = nv04_fifo_intr;
@@ -171,13 +166,13 @@ nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
-nv10_fifo_oclass = &(struct nouveau_oclass) {
+struct nvkm_oclass *
+nv10_fifo_oclass = &(struct nvkm_oclass) {
.handle = NV_ENGINE(FIFO, 0x10),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv10_fifo_ctor,
.dtor = nv04_fifo_dtor,
.init = nv04_fifo_init,
- .fini = _nouveau_fifo_fini,
+ .fini = _nvkm_fifo_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
index 01fbb11af00d..4a20a6fd3887 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
@@ -21,20 +21,15 @@
*
* Authors: Ben Skeggs
*/
+#include "nv04.h"
#include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
#include <core/engctx.h>
#include <core/ramht.h>
-
-#include <subdev/instmem.h>
#include <subdev/instmem/nv04.h>
-#include <subdev/fb.h>
-#include <engine/fifo.h>
-
-#include "nv04.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
static struct ramfc_desc
nv17_ramfc[] = {
@@ -60,10 +55,10 @@ nv17_ramfc[] = {
******************************************************************************/
static int
-nv17_fifo_chan_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv17_fifo_chan_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv03_channel_dma_v0 v0;
@@ -80,13 +75,13 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent,
} else
return ret;
- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
- 0x10000, args->v0.pushbuf,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */
- &chan);
+ ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
+ 0x10000, args->v0.pushbuf,
+ (1ULL << NVDEV_ENGINE_DMAOBJ) |
+ (1ULL << NVDEV_ENGINE_SW) |
+ (1ULL << NVDEV_ENGINE_GR) |
+ (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */
+ &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -111,19 +106,19 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
nv17_fifo_ofuncs = {
.ctor = nv17_fifo_chan_ctor,
.dtor = nv04_fifo_chan_dtor,
.init = nv04_fifo_chan_init,
.fini = nv04_fifo_chan_fini,
- .map = _nouveau_fifo_channel_map,
- .rd32 = _nouveau_fifo_channel_rd32,
- .wr32 = _nouveau_fifo_channel_wr32,
- .ntfy = _nouveau_fifo_channel_ntfy
+ .map = _nvkm_fifo_channel_map,
+ .rd32 = _nvkm_fifo_channel_rd32,
+ .wr32 = _nvkm_fifo_channel_wr32,
+ .ntfy = _nvkm_fifo_channel_ntfy
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv17_fifo_sclass[] = {
{ NV17_CHANNEL_DMA, &nv17_fifo_ofuncs },
{}
@@ -133,16 +128,16 @@ nv17_fifo_sclass[] = {
* FIFO context - basically just the instmem reserved for the channel
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
nv17_fifo_cclass = {
.handle = NV_ENGCTX(FIFO, 0x17),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fifo_context_ctor,
- .dtor = _nouveau_fifo_context_dtor,
- .init = _nouveau_fifo_context_init,
- .fini = _nouveau_fifo_context_fini,
- .rd32 = _nouveau_fifo_context_rd32,
- .wr32 = _nouveau_fifo_context_wr32,
+ .dtor = _nvkm_fifo_context_dtor,
+ .init = _nvkm_fifo_context_init,
+ .fini = _nvkm_fifo_context_fini,
+ .rd32 = _nvkm_fifo_context_rd32,
+ .wr32 = _nvkm_fifo_context_wr32,
},
};
@@ -151,22 +146,22 @@ nv17_fifo_cclass = {
******************************************************************************/
static int
-nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_instmem_priv *imem = nv04_instmem(parent);
struct nv04_fifo_priv *priv;
int ret;
- ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
+ ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- nouveau_ramht_ref(imem->ramht, &priv->ramht);
- nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
- nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
+ nvkm_ramht_ref(imem->ramht, &priv->ramht);
+ nvkm_gpuobj_ref(imem->ramro, &priv->ramro);
+ nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc);
nv_subdev(priv)->unit = 0x00000100;
nv_subdev(priv)->intr = nv04_fifo_intr;
@@ -179,12 +174,12 @@ nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
static int
-nv17_fifo_init(struct nouveau_object *object)
+nv17_fifo_init(struct nvkm_object *object)
{
struct nv04_fifo_priv *priv = (void *)object;
int ret;
- ret = nouveau_fifo_init(&priv->base);
+ ret = nvkm_fifo_init(&priv->base);
if (ret)
return ret;
@@ -208,13 +203,13 @@ nv17_fifo_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
-nv17_fifo_oclass = &(struct nouveau_oclass) {
+struct nvkm_oclass *
+nv17_fifo_oclass = &(struct nvkm_oclass) {
.handle = NV_ENGINE(FIFO, 0x17),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv17_fifo_ctor,
.dtor = nv04_fifo_dtor,
.init = nv17_fifo_init,
- .fini = _nouveau_fifo_fini,
+ .fini = _nvkm_fifo_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
index be0293476279..5bfc96265f3b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
@@ -21,21 +21,17 @@
*
* Authors: Ben Skeggs
*/
+#include "nv04.h"
#include <core/client.h>
#include <core/device.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
#include <core/engctx.h>
#include <core/ramht.h>
-
-#include <subdev/instmem.h>
-#include <subdev/instmem/nv04.h>
#include <subdev/fb.h>
+#include <subdev/instmem/nv04.h>
-#include <engine/fifo.h>
-
-#include "nv04.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
static struct ramfc_desc
nv40_ramfc[] = {
@@ -69,8 +65,8 @@ nv40_ramfc[] = {
******************************************************************************/
static int
-nv40_fifo_object_attach(struct nouveau_object *parent,
- struct nouveau_object *object, u32 handle)
+nv40_fifo_object_attach(struct nvkm_object *parent,
+ struct nvkm_object *object, u32 handle)
{
struct nv04_fifo_priv *priv = (void *)parent->engine;
struct nv04_fifo_chan *chan = (void *)parent;
@@ -100,14 +96,13 @@ nv40_fifo_object_attach(struct nouveau_object *parent,
context |= chid << 23;
mutex_lock(&nv_subdev(priv)->mutex);
- ret = nouveau_ramht_insert(priv->ramht, chid, handle, context);
+ ret = nvkm_ramht_insert(priv->ramht, chid, handle, context);
mutex_unlock(&nv_subdev(priv)->mutex);
return ret;
}
static int
-nv40_fifo_context_attach(struct nouveau_object *parent,
- struct nouveau_object *engctx)
+nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx)
{
struct nv04_fifo_priv *priv = (void *)parent->engine;
struct nv04_fifo_chan *chan = (void *)parent;
@@ -143,8 +138,8 @@ nv40_fifo_context_attach(struct nouveau_object *parent,
}
static int
-nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend,
- struct nouveau_object *engctx)
+nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend,
+ struct nvkm_object *engctx)
{
struct nv04_fifo_priv *priv = (void *)parent->engine;
struct nv04_fifo_chan *chan = (void *)parent;
@@ -179,10 +174,9 @@ nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend,
}
static int
-nv40_fifo_chan_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv03_channel_dma_v0 v0;
@@ -199,12 +193,12 @@ nv40_fifo_chan_ctor(struct nouveau_object *parent,
} else
return ret;
- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
- 0x1000, args->v0.pushbuf,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_MPEG), &chan);
+ ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
+ 0x1000, args->v0.pushbuf,
+ (1ULL << NVDEV_ENGINE_DMAOBJ) |
+ (1ULL << NVDEV_ENGINE_SW) |
+ (1ULL << NVDEV_ENGINE_GR) |
+ (1ULL << NVDEV_ENGINE_MPEG), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -231,19 +225,19 @@ nv40_fifo_chan_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
nv40_fifo_ofuncs = {
.ctor = nv40_fifo_chan_ctor,
.dtor = nv04_fifo_chan_dtor,
.init = nv04_fifo_chan_init,
.fini = nv04_fifo_chan_fini,
- .map = _nouveau_fifo_channel_map,
- .rd32 = _nouveau_fifo_channel_rd32,
- .wr32 = _nouveau_fifo_channel_wr32,
- .ntfy = _nouveau_fifo_channel_ntfy
+ .map = _nvkm_fifo_channel_map,
+ .rd32 = _nvkm_fifo_channel_rd32,
+ .wr32 = _nvkm_fifo_channel_wr32,
+ .ntfy = _nvkm_fifo_channel_ntfy
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv40_fifo_sclass[] = {
{ NV40_CHANNEL_DMA, &nv40_fifo_ofuncs },
{}
@@ -253,16 +247,16 @@ nv40_fifo_sclass[] = {
* FIFO context - basically just the instmem reserved for the channel
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
nv40_fifo_cclass = {
.handle = NV_ENGCTX(FIFO, 0x40),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fifo_context_ctor,
- .dtor = _nouveau_fifo_context_dtor,
- .init = _nouveau_fifo_context_init,
- .fini = _nouveau_fifo_context_fini,
- .rd32 = _nouveau_fifo_context_rd32,
- .wr32 = _nouveau_fifo_context_wr32,
+ .dtor = _nvkm_fifo_context_dtor,
+ .init = _nvkm_fifo_context_init,
+ .fini = _nvkm_fifo_context_fini,
+ .rd32 = _nvkm_fifo_context_rd32,
+ .wr32 = _nvkm_fifo_context_wr32,
},
};
@@ -271,22 +265,22 @@ nv40_fifo_cclass = {
******************************************************************************/
static int
-nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_instmem_priv *imem = nv04_instmem(parent);
struct nv04_fifo_priv *priv;
int ret;
- ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
+ ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- nouveau_ramht_ref(imem->ramht, &priv->ramht);
- nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
- nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
+ nvkm_ramht_ref(imem->ramht, &priv->ramht);
+ nvkm_gpuobj_ref(imem->ramro, &priv->ramro);
+ nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc);
nv_subdev(priv)->unit = 0x00000100;
nv_subdev(priv)->intr = nv04_fifo_intr;
@@ -299,13 +293,13 @@ nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
static int
-nv40_fifo_init(struct nouveau_object *object)
+nv40_fifo_init(struct nvkm_object *object)
{
struct nv04_fifo_priv *priv = (void *)object;
- struct nouveau_fb *pfb = nouveau_fb(object);
+ struct nvkm_fb *pfb = nvkm_fb(object);
int ret;
- ret = nouveau_fifo_init(&priv->base);
+ ret = nvkm_fifo_init(&priv->base);
if (ret)
return ret;
@@ -350,13 +344,13 @@ nv40_fifo_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
-nv40_fifo_oclass = &(struct nouveau_oclass) {
+struct nvkm_oclass *
+nv40_fifo_oclass = &(struct nvkm_oclass) {
.handle = NV_ENGINE(FIFO, 0x40),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_fifo_ctor,
.dtor = nv04_fifo_dtor,
.init = nv40_fifo_init,
- .fini = _nouveau_fifo_fini,
+ .fini = _nvkm_fifo_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
index 403fafc05072..f25f0fd0655d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
@@ -21,21 +21,18 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
+#include "nv04.h"
#include <core/client.h>
#include <core/engctx.h>
#include <core/ramht.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/timer.h>
#include <subdev/bar.h>
+#include <subdev/mmu.h>
+#include <subdev/timer.h>
-#include <engine/dmaobj.h>
-#include <engine/fifo.h>
-
-#include "nv04.h"
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
/*******************************************************************************
* FIFO channel objects
@@ -44,8 +41,8 @@
static void
nv50_fifo_playlist_update_locked(struct nv50_fifo_priv *priv)
{
- struct nouveau_bar *bar = nouveau_bar(priv);
- struct nouveau_gpuobj *cur;
+ struct nvkm_bar *bar = nvkm_bar(priv);
+ struct nvkm_gpuobj *cur;
int i, p;
cur = priv->playlist[priv->cur_playlist];
@@ -72,12 +69,11 @@ nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
}
static int
-nv50_fifo_context_attach(struct nouveau_object *parent,
- struct nouveau_object *object)
+nv50_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object)
{
- struct nouveau_bar *bar = nouveau_bar(parent);
+ struct nvkm_bar *bar = nvkm_bar(parent);
struct nv50_fifo_base *base = (void *)parent->parent;
- struct nouveau_gpuobj *ectx = (void *)object;
+ struct nvkm_gpuobj *ectx = (void *)object;
u64 limit = ectx->addr + ectx->size - 1;
u64 start = ectx->addr;
u32 addr;
@@ -103,10 +99,10 @@ nv50_fifo_context_attach(struct nouveau_object *parent,
}
static int
-nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend,
- struct nouveau_object *object)
+nv50_fifo_context_detach(struct nvkm_object *parent, bool suspend,
+ struct nvkm_object *object)
{
- struct nouveau_bar *bar = nouveau_bar(parent);
+ struct nvkm_bar *bar = nvkm_bar(parent);
struct nv50_fifo_priv *priv = (void *)parent->engine;
struct nv50_fifo_base *base = (void *)parent->parent;
struct nv50_fifo_chan *chan = (void *)parent;
@@ -139,7 +135,7 @@ nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend,
nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) {
nv_error(priv, "channel %d [%s] unload timeout\n",
- chan->base.chid, nouveau_client_name(chan));
+ chan->base.chid, nvkm_client_name(chan));
if (suspend)
ret = -EBUSY;
}
@@ -159,8 +155,8 @@ nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend,
}
static int
-nv50_fifo_object_attach(struct nouveau_object *parent,
- struct nouveau_object *object, u32 handle)
+nv50_fifo_object_attach(struct nvkm_object *parent,
+ struct nvkm_object *object, u32 handle)
{
struct nv50_fifo_chan *chan = (void *)parent;
u32 context;
@@ -179,26 +175,25 @@ nv50_fifo_object_attach(struct nouveau_object *parent,
return -EINVAL;
}
- return nouveau_ramht_insert(chan->ramht, 0, handle, context);
+ return nvkm_ramht_insert(chan->ramht, 0, handle, context);
}
void
-nv50_fifo_object_detach(struct nouveau_object *parent, int cookie)
+nv50_fifo_object_detach(struct nvkm_object *parent, int cookie)
{
struct nv50_fifo_chan *chan = (void *)parent;
- nouveau_ramht_remove(chan->ramht, cookie);
+ nvkm_ramht_remove(chan->ramht, cookie);
}
static int
-nv50_fifo_chan_ctor_dma(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv03_channel_dma_v0 v0;
} *args = data;
- struct nouveau_bar *bar = nouveau_bar(parent);
+ struct nvkm_bar *bar = nvkm_bar(parent);
struct nv50_fifo_base *base = (void *)parent;
struct nv50_fifo_chan *chan;
int ret;
@@ -211,12 +206,12 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent,
} else
return ret;
- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
- 0x2000, args->v0.pushbuf,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_MPEG), &chan);
+ ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
+ 0x2000, args->v0.pushbuf,
+ (1ULL << NVDEV_ENGINE_DMAOBJ) |
+ (1ULL << NVDEV_ENGINE_SW) |
+ (1ULL << NVDEV_ENGINE_GR) |
+ (1ULL << NVDEV_ENGINE_MPEG), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -228,8 +223,8 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent,
nv_parent(chan)->object_attach = nv50_fifo_object_attach;
nv_parent(chan)->object_detach = nv50_fifo_object_detach;
- ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
- &chan->ramht);
+ ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
+ &chan->ramht);
if (ret)
return ret;
@@ -252,15 +247,14 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent,
}
static int
-nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv50_channel_gpfifo_v0 v0;
} *args = data;
- struct nouveau_bar *bar = nouveau_bar(parent);
+ struct nvkm_bar *bar = nvkm_bar(parent);
struct nv50_fifo_base *base = (void *)parent;
struct nv50_fifo_chan *chan;
u64 ioffset, ilength;
@@ -275,12 +269,12 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
} else
return ret;
- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
- 0x2000, args->v0.pushbuf,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_MPEG), &chan);
+ ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
+ 0x2000, args->v0.pushbuf,
+ (1ULL << NVDEV_ENGINE_DMAOBJ) |
+ (1ULL << NVDEV_ENGINE_SW) |
+ (1ULL << NVDEV_ENGINE_GR) |
+ (1ULL << NVDEV_ENGINE_MPEG), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -292,8 +286,8 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
nv_parent(chan)->object_attach = nv50_fifo_object_attach;
nv_parent(chan)->object_detach = nv50_fifo_object_detach;
- ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
- &chan->ramht);
+ ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
+ &chan->ramht);
if (ret)
return ret;
@@ -316,24 +310,24 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
}
void
-nv50_fifo_chan_dtor(struct nouveau_object *object)
+nv50_fifo_chan_dtor(struct nvkm_object *object)
{
struct nv50_fifo_chan *chan = (void *)object;
- nouveau_ramht_ref(NULL, &chan->ramht);
- nouveau_fifo_channel_destroy(&chan->base);
+ nvkm_ramht_ref(NULL, &chan->ramht);
+ nvkm_fifo_channel_destroy(&chan->base);
}
static int
-nv50_fifo_chan_init(struct nouveau_object *object)
+nv50_fifo_chan_init(struct nvkm_object *object)
{
struct nv50_fifo_priv *priv = (void *)object->engine;
struct nv50_fifo_base *base = (void *)object->parent;
struct nv50_fifo_chan *chan = (void *)object;
- struct nouveau_gpuobj *ramfc = base->ramfc;
+ struct nvkm_gpuobj *ramfc = base->ramfc;
u32 chid = chan->base.chid;
int ret;
- ret = nouveau_fifo_channel_init(&chan->base);
+ ret = nvkm_fifo_channel_init(&chan->base);
if (ret)
return ret;
@@ -343,7 +337,7 @@ nv50_fifo_chan_init(struct nouveau_object *object)
}
int
-nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend)
+nv50_fifo_chan_fini(struct nvkm_object *object, bool suspend)
{
struct nv50_fifo_priv *priv = (void *)object->engine;
struct nv50_fifo_chan *chan = (void *)object;
@@ -354,34 +348,34 @@ nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend)
nv50_fifo_playlist_update(priv);
nv_wr32(priv, 0x002600 + (chid * 4), 0x00000000);
- return nouveau_fifo_channel_fini(&chan->base, suspend);
+ return nvkm_fifo_channel_fini(&chan->base, suspend);
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
nv50_fifo_ofuncs_dma = {
.ctor = nv50_fifo_chan_ctor_dma,
.dtor = nv50_fifo_chan_dtor,
.init = nv50_fifo_chan_init,
.fini = nv50_fifo_chan_fini,
- .map = _nouveau_fifo_channel_map,
- .rd32 = _nouveau_fifo_channel_rd32,
- .wr32 = _nouveau_fifo_channel_wr32,
- .ntfy = _nouveau_fifo_channel_ntfy
+ .map = _nvkm_fifo_channel_map,
+ .rd32 = _nvkm_fifo_channel_rd32,
+ .wr32 = _nvkm_fifo_channel_wr32,
+ .ntfy = _nvkm_fifo_channel_ntfy
};
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
nv50_fifo_ofuncs_ind = {
.ctor = nv50_fifo_chan_ctor_ind,
.dtor = nv50_fifo_chan_dtor,
.init = nv50_fifo_chan_init,
.fini = nv50_fifo_chan_fini,
- .map = _nouveau_fifo_channel_map,
- .rd32 = _nouveau_fifo_channel_rd32,
- .wr32 = _nouveau_fifo_channel_wr32,
- .ntfy = _nouveau_fifo_channel_ntfy
+ .map = _nvkm_fifo_channel_map,
+ .rd32 = _nvkm_fifo_channel_rd32,
+ .wr32 = _nvkm_fifo_channel_wr32,
+ .ntfy = _nvkm_fifo_channel_ntfy
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv50_fifo_sclass[] = {
{ NV50_CHANNEL_DMA, &nv50_fifo_ofuncs_dma },
{ NV50_CHANNEL_GPFIFO, &nv50_fifo_ofuncs_ind },
@@ -393,36 +387,35 @@ nv50_fifo_sclass[] = {
******************************************************************************/
static int
-nv50_fifo_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_fifo_base *base;
int ret;
- ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
- 0x1000, NVOBJ_FLAG_HEAP, &base);
+ ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
+ 0x1000, NVOBJ_FLAG_HEAP, &base);
*pobject = nv_object(base);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200,
- 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
+ ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0200,
+ 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1200, 0,
- NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
+ ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x1200, 0,
+ NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 0,
- &base->pgd);
+ ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 0,
+ &base->pgd);
if (ret)
return ret;
- ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
+ ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);
if (ret)
return ret;
@@ -430,27 +423,27 @@ nv50_fifo_context_ctor(struct nouveau_object *parent,
}
void
-nv50_fifo_context_dtor(struct nouveau_object *object)
+nv50_fifo_context_dtor(struct nvkm_object *object)
{
struct nv50_fifo_base *base = (void *)object;
- nouveau_vm_ref(NULL, &base->vm, base->pgd);
- nouveau_gpuobj_ref(NULL, &base->pgd);
- nouveau_gpuobj_ref(NULL, &base->eng);
- nouveau_gpuobj_ref(NULL, &base->ramfc);
- nouveau_gpuobj_ref(NULL, &base->cache);
- nouveau_fifo_context_destroy(&base->base);
+ nvkm_vm_ref(NULL, &base->vm, base->pgd);
+ nvkm_gpuobj_ref(NULL, &base->pgd);
+ nvkm_gpuobj_ref(NULL, &base->eng);
+ nvkm_gpuobj_ref(NULL, &base->ramfc);
+ nvkm_gpuobj_ref(NULL, &base->cache);
+ nvkm_fifo_context_destroy(&base->base);
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv50_fifo_cclass = {
.handle = NV_ENGCTX(FIFO, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_fifo_context_ctor,
.dtor = nv50_fifo_context_dtor,
- .init = _nouveau_fifo_context_init,
- .fini = _nouveau_fifo_context_fini,
- .rd32 = _nouveau_fifo_context_rd32,
- .wr32 = _nouveau_fifo_context_wr32,
+ .init = _nvkm_fifo_context_init,
+ .fini = _nvkm_fifo_context_fini,
+ .rd32 = _nvkm_fifo_context_rd32,
+ .wr32 = _nvkm_fifo_context_wr32,
},
};
@@ -459,25 +452,25 @@ nv50_fifo_cclass = {
******************************************************************************/
static int
-nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_fifo_priv *priv;
int ret;
- ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
+ ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
- &priv->playlist[0]);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
+ &priv->playlist[0]);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
- &priv->playlist[1]);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
+ &priv->playlist[1]);
if (ret)
return ret;
@@ -491,23 +484,23 @@ nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
void
-nv50_fifo_dtor(struct nouveau_object *object)
+nv50_fifo_dtor(struct nvkm_object *object)
{
struct nv50_fifo_priv *priv = (void *)object;
- nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
- nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
+ nvkm_gpuobj_ref(NULL, &priv->playlist[1]);
+ nvkm_gpuobj_ref(NULL, &priv->playlist[0]);
- nouveau_fifo_destroy(&priv->base);
+ nvkm_fifo_destroy(&priv->base);
}
int
-nv50_fifo_init(struct nouveau_object *object)
+nv50_fifo_init(struct nvkm_object *object)
{
struct nv50_fifo_priv *priv = (void *)object;
int ret, i;
- ret = nouveau_fifo_init(&priv->base);
+ ret = nvkm_fifo_init(&priv->base);
if (ret)
return ret;
@@ -529,13 +522,13 @@ nv50_fifo_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass *
-nv50_fifo_oclass = &(struct nouveau_oclass) {
+struct nvkm_oclass *
+nv50_fifo_oclass = &(struct nvkm_oclass) {
.handle = NV_ENGINE(FIFO, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_fifo_ctor,
.dtor = nv50_fifo_dtor,
.init = nv50_fifo_init,
- .fini = _nouveau_fifo_fini,
+ .fini = _nvkm_fifo_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h
index 3a9ceb315c20..09ed93c66567 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h
@@ -1,36 +1,36 @@
#ifndef __NV50_FIFO_H__
#define __NV50_FIFO_H__
+#include <engine/fifo.h>
struct nv50_fifo_priv {
- struct nouveau_fifo base;
- struct nouveau_gpuobj *playlist[2];
+ struct nvkm_fifo base;
+ struct nvkm_gpuobj *playlist[2];
int cur_playlist;
};
struct nv50_fifo_base {
- struct nouveau_fifo_base base;
- struct nouveau_gpuobj *ramfc;
- struct nouveau_gpuobj *cache;
- struct nouveau_gpuobj *eng;
- struct nouveau_gpuobj *pgd;
- struct nouveau_vm *vm;
+ struct nvkm_fifo_base base;
+ struct nvkm_gpuobj *ramfc;
+ struct nvkm_gpuobj *cache;
+ struct nvkm_gpuobj *eng;
+ struct nvkm_gpuobj *pgd;
+ struct nvkm_vm *vm;
};
struct nv50_fifo_chan {
- struct nouveau_fifo_chan base;
+ struct nvkm_fifo_chan base;
u32 subc[8];
- struct nouveau_ramht *ramht;
+ struct nvkm_ramht *ramht;
};
void nv50_fifo_playlist_update(struct nv50_fifo_priv *);
-void nv50_fifo_object_detach(struct nouveau_object *, int);
-void nv50_fifo_chan_dtor(struct nouveau_object *);
-int nv50_fifo_chan_fini(struct nouveau_object *, bool);
+void nv50_fifo_object_detach(struct nvkm_object *, int);
+void nv50_fifo_chan_dtor(struct nvkm_object *);
+int nv50_fifo_chan_fini(struct nvkm_object *, bool);
-void nv50_fifo_context_dtor(struct nouveau_object *);
-
-void nv50_fifo_dtor(struct nouveau_object *);
-int nv50_fifo_init(struct nouveau_object *);
+void nv50_fifo_context_dtor(struct nvkm_object *);
+void nv50_fifo_dtor(struct nvkm_object *);
+int nv50_fifo_init(struct nvkm_object *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.h
deleted file mode 100644
index e96b32bb1bbc..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef __NVKM_FIFO_NVE0_H__
-#define __NVKM_FIFO_NVE0_H__
-
-#include <engine/fifo.h>
-
-int nve0_fifo_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nve0_fifo_dtor(struct nouveau_object *);
-int nve0_fifo_init(struct nouveau_object *);
-int nve0_fifo_fini(struct nouveau_object *, bool);
-
-struct nve0_fifo_impl {
- struct nouveau_oclass base;
- u32 channels;
-};
-
-#endif
From e3c71eb27419b600dcacea9f268254369e6550c4 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:29:43 +1000
Subject: [PATCH 76/86] drm/nouveau/gr: namespace + nvidia gpu names (no binary
change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 1 +
.../gpu/drm/nouveau/include/nvkm/engine/gr.h | 130 ++--
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 12 +-
drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild | 36 +-
.../nvkm/engine/gr/{ctxnvc0.c => ctxgf100.c} | 330 ++++-----
.../gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h | 199 ++++++
.../nvkm/engine/gr/{ctxnvc4.c => ctxgf104.c} | 73 +-
.../nvkm/engine/gr/{ctxnvc1.c => ctxgf108.c} | 175 ++---
.../nvkm/engine/gr/{ctxnvc8.c => ctxgf110.c} | 101 ++-
.../nvkm/engine/gr/{ctxnvd7.c => ctxgf117.c} | 186 +++---
.../nvkm/engine/gr/{ctxnvd9.c => ctxgf119.c} | 177 +++--
.../nvkm/engine/gr/{ctxnve4.c => ctxgk104.c} | 244 +++----
.../nvkm/engine/gr/{ctxnvf0.c => ctxgk110.c} | 185 +++--
.../drm/nouveau/nvkm/engine/gr/ctxgk110b.c | 55 +-
.../nvkm/engine/gr/{ctxnv108.c => ctxgk208.c} | 177 +++--
.../gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c | 49 +-
.../gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c | 138 ++--
.../gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c | 43 +-
.../nvkm/engine/gr/{ctx.h => ctxnv40.h} | 38 +-
.../gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c | 185 +++--
.../gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h | 202 ------
.../drm/nouveau/nvkm/engine/gr/fuc/com.fuc | 2 +-
.../drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc | 2 +-
.../gr/fuc/{gpcnvc0.fuc3 => gpcgf100.fuc3} | 4 +-
.../fuc/{gpcnvc0.fuc3.h => gpcgf100.fuc3.h} | 4 +-
.../gr/fuc/{gpcnvd7.fuc3 => gpcgf117.fuc3} | 4 +-
.../fuc/{gpcnve0.fuc3.h => gpcgf117.fuc3.h} | 4 +-
.../gr/fuc/{gpcnve0.fuc3 => gpcgk104.fuc3} | 4 +-
.../fuc/{gpcnvd7.fuc3.h => gpcgk104.fuc3.h} | 4 +-
.../gr/fuc/{gpcnvf0.fuc3 => gpcgk110.fuc3} | 4 +-
.../fuc/{gpcnvf0.fuc3.h => gpcgk110.fuc3.h} | 4 +-
.../gr/fuc/{gpcnv108.fuc5 => gpcgk208.fuc5} | 4 +-
.../fuc/{gpcnv108.fuc5.h => gpcgk208.fuc5.h} | 4 +-
.../drm/nouveau/nvkm/engine/gr/fuc/hub.fuc | 2 +-
.../gr/fuc/{hubnvc0.fuc3 => hubgf100.fuc3} | 4 +-
.../fuc/{hubnvd7.fuc3.h => hubgf100.fuc3.h} | 4 +-
.../gr/fuc/{hubnvd7.fuc3 => hubgf117.fuc3} | 4 +-
.../fuc/{hubnvc0.fuc3.h => hubgf117.fuc3.h} | 4 +-
.../gr/fuc/{hubnve0.fuc3 => hubgk104.fuc3} | 4 +-
.../fuc/{hubnve0.fuc3.h => hubgk104.fuc3.h} | 4 +-
.../gr/fuc/{hubnvf0.fuc3 => hubgk110.fuc3} | 4 +-
.../fuc/{hubnvf0.fuc3.h => hubgk110.fuc3.h} | 4 +-
.../gr/fuc/{hubnv108.fuc5 => hubgk208.fuc5} | 4 +-
.../fuc/{hubnv108.fuc5.h => hubgk208.fuc5.h} | 4 +-
.../nvkm/engine/gr/{nvc0.c => gf100.c} | 631 +++++++++---------
.../gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 250 +++++++
.../nvkm/engine/gr/{nvc4.c => gf104.c} | 101 ++-
.../nvkm/engine/gr/{nvc1.c => gf108.c} | 115 ++--
.../nvkm/engine/gr/{nvc8.c => gf110.c} | 107 +--
.../nvkm/engine/gr/{nvd7.c => gf117.c} | 131 ++--
.../nvkm/engine/gr/{nvd9.c => gf119.c} | 129 ++--
.../nvkm/engine/gr/{nve4.c => gk104.c} | 187 +++---
.../nvkm/engine/gr/{nvf0.c => gk110.c} | 171 ++---
.../gpu/drm/nouveau/nvkm/engine/gr/gk110b.c | 85 ++-
.../nvkm/engine/gr/{nv108.c => gk208.c} | 163 ++---
.../gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 31 +-
.../gpu/drm/nouveau/nvkm/engine/gr/gm107.c | 111 +--
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 219 +++---
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 113 ++--
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 116 ++--
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h | 27 +-
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c | 54 +-
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c | 52 +-
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 65 +-
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c | 54 +-
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c | 52 +-
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 135 ++--
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h | 13 +-
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 213 +++---
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h | 6 +-
drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h | 271 --------
drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h | 4 +-
73 files changed, 3180 insertions(+), 3266 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{ctxnvc0.c => ctxgf100.c} (86%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{ctxnvc4.c => ctxgf104.c} (68%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{ctxnvc1.c => ctxgf108.c} (89%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{ctxnvc8.c => ctxgf110.c} (87%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{ctxnvd7.c => ctxgf117.c} (63%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{ctxnvd9.c => ctxgf119.c} (84%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{ctxnve4.c => ctxgk104.c} (87%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{ctxnvf0.c => ctxgk110.c} (90%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{ctxnv108.c => ctxgk208.c} (85%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{ctx.h => ctxnv40.h} (74%)
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{gpcnvc0.fuc3 => gpcgf100.fuc3} (96%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{gpcnvc0.fuc3.h => gpcgf100.fuc3.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{gpcnvd7.fuc3 => gpcgf117.fuc3} (96%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{gpcnve0.fuc3.h => gpcgf117.fuc3.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{gpcnve0.fuc3 => gpcgk104.fuc3} (96%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{gpcnvd7.fuc3.h => gpcgk104.fuc3.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{gpcnvf0.fuc3 => gpcgk110.fuc3} (96%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{gpcnvf0.fuc3.h => gpcgk110.fuc3.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{gpcnv108.fuc5 => gpcgk208.fuc5} (96%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{gpcnv108.fuc5.h => gpcgk208.fuc5.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{hubnvc0.fuc3 => hubgf100.fuc3} (96%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{hubnvd7.fuc3.h => hubgf100.fuc3.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{hubnvd7.fuc3 => hubgf117.fuc3} (96%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{hubnvc0.fuc3.h => hubgf117.fuc3.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{hubnve0.fuc3 => hubgk104.fuc3} (96%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{hubnve0.fuc3.h => hubgk104.fuc3.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{hubnvf0.fuc3 => hubgk110.fuc3} (96%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{hubnvf0.fuc3.h => hubgk110.fuc3.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{hubnv108.fuc5 => hubgk208.fuc5} (96%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/{hubnv108.fuc5.h => hubgk208.fuc5.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{nvc0.c => gf100.c} (72%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{nvc4.c => gf104.c} (65%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{nvc1.c => gf108.c} (59%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{nvc8.c => gf110.c} (58%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{nvd7.c => gf117.c} (54%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{nvd9.c => gf119.c} (68%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{nve4.c => gk104.c} (73%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{nvf0.c => gk110.c} (64%)
rename drivers/gpu/drm/nouveau/nvkm/engine/gr/{nv108.c => gk208.c} (62%)
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 9d6990aa5b47..2fe75c15e5ac 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -250,5 +250,6 @@
#define nouveau_disp nvkm_disp
#define nouveau_fifo_chan nvkm_fifo_chan
#define nouveau_fifo nvkm_fifo
+#define nouveau_gr nvkm_gr
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
index 9985adca0fda..93ef1f2bfac4 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
@@ -1,86 +1,86 @@
-#ifndef __NOUVEAU_GR_H__
-#define __NOUVEAU_GR_H__
-
-#include <core/engine.h>
+#ifndef __NVKM_GR_H__
+#define __NVKM_GR_H__
#include <core/engctx.h>
-#include <core/enum.h>
-struct nouveau_gr_chan {
- struct nouveau_engctx base;
+struct nvkm_gr_chan {
+ struct nvkm_engctx base;
};
-#define nouveau_gr_context_create(p,e,c,g,s,a,f,d) \
- nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
-#define nouveau_gr_context_destroy(d) \
- nouveau_engctx_destroy(&(d)->base)
-#define nouveau_gr_context_init(d) \
- nouveau_engctx_init(&(d)->base)
-#define nouveau_gr_context_fini(d,s) \
- nouveau_engctx_fini(&(d)->base, (s))
+#define nvkm_gr_context_create(p,e,c,g,s,a,f,d) \
+ nvkm_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
+#define nvkm_gr_context_destroy(d) \
+ nvkm_engctx_destroy(&(d)->base)
+#define nvkm_gr_context_init(d) \
+ nvkm_engctx_init(&(d)->base)
+#define nvkm_gr_context_fini(d,s) \
+ nvkm_engctx_fini(&(d)->base, (s))
-#define _nouveau_gr_context_dtor _nouveau_engctx_dtor
-#define _nouveau_gr_context_init _nouveau_engctx_init
-#define _nouveau_gr_context_fini _nouveau_engctx_fini
-#define _nouveau_gr_context_rd32 _nouveau_engctx_rd32
-#define _nouveau_gr_context_wr32 _nouveau_engctx_wr32
+#define _nvkm_gr_context_dtor _nvkm_engctx_dtor
+#define _nvkm_gr_context_init _nvkm_engctx_init
+#define _nvkm_gr_context_fini _nvkm_engctx_fini
+#define _nvkm_gr_context_rd32 _nvkm_engctx_rd32
+#define _nvkm_gr_context_wr32 _nvkm_engctx_wr32
-struct nouveau_gr {
- struct nouveau_engine base;
+#include <core/engine.h>
+
+struct nvkm_gr {
+ struct nvkm_engine base;
/* Returns chipset-specific counts of units packed into an u64.
*/
- u64 (*units)(struct nouveau_gr *);
+ u64 (*units)(struct nvkm_gr *);
};
-static inline struct nouveau_gr *
-nouveau_gr(void *obj)
+static inline struct nvkm_gr *
+nvkm_gr(void *obj)
{
- return (void *)nouveau_engine(obj, NVDEV_ENGINE_GR);
+ return (void *)nvkm_engine(obj, NVDEV_ENGINE_GR);
}
-#define nouveau_gr_create(p,e,c,y,d) \
- nouveau_engine_create((p), (e), (c), (y), "PGR", "graphics", (d))
-#define nouveau_gr_destroy(d) \
- nouveau_engine_destroy(&(d)->base)
-#define nouveau_gr_init(d) \
- nouveau_engine_init(&(d)->base)
-#define nouveau_gr_fini(d,s) \
- nouveau_engine_fini(&(d)->base, (s))
+#define nvkm_gr_create(p,e,c,y,d) \
+ nvkm_engine_create((p), (e), (c), (y), "PGR", "graphics", (d))
+#define nvkm_gr_destroy(d) \
+ nvkm_engine_destroy(&(d)->base)
+#define nvkm_gr_init(d) \
+ nvkm_engine_init(&(d)->base)
+#define nvkm_gr_fini(d,s) \
+ nvkm_engine_fini(&(d)->base, (s))
-#define _nouveau_gr_dtor _nouveau_engine_dtor
-#define _nouveau_gr_init _nouveau_engine_init
-#define _nouveau_gr_fini _nouveau_engine_fini
+#define _nvkm_gr_dtor _nvkm_engine_dtor
+#define _nvkm_gr_init _nvkm_engine_init
+#define _nvkm_gr_fini _nvkm_engine_fini
-extern struct nouveau_oclass nv04_gr_oclass;
-extern struct nouveau_oclass nv10_gr_oclass;
-extern struct nouveau_oclass nv20_gr_oclass;
-extern struct nouveau_oclass nv25_gr_oclass;
-extern struct nouveau_oclass nv2a_gr_oclass;
-extern struct nouveau_oclass nv30_gr_oclass;
-extern struct nouveau_oclass nv34_gr_oclass;
-extern struct nouveau_oclass nv35_gr_oclass;
-extern struct nouveau_oclass nv40_gr_oclass;
-extern struct nouveau_oclass nv50_gr_oclass;
-extern struct nouveau_oclass *nvc0_gr_oclass;
-extern struct nouveau_oclass *nvc1_gr_oclass;
-extern struct nouveau_oclass *nvc4_gr_oclass;
-extern struct nouveau_oclass *nvc8_gr_oclass;
-extern struct nouveau_oclass *nvd7_gr_oclass;
-extern struct nouveau_oclass *nvd9_gr_oclass;
-extern struct nouveau_oclass *nve4_gr_oclass;
-extern struct nouveau_oclass *gk20a_gr_oclass;
-extern struct nouveau_oclass *nvf0_gr_oclass;
-extern struct nouveau_oclass *gk110b_gr_oclass;
-extern struct nouveau_oclass *nv108_gr_oclass;
-extern struct nouveau_oclass *gm107_gr_oclass;
+extern struct nvkm_oclass nv04_gr_oclass;
+extern struct nvkm_oclass nv10_gr_oclass;
+extern struct nvkm_oclass nv20_gr_oclass;
+extern struct nvkm_oclass nv25_gr_oclass;
+extern struct nvkm_oclass nv2a_gr_oclass;
+extern struct nvkm_oclass nv30_gr_oclass;
+extern struct nvkm_oclass nv34_gr_oclass;
+extern struct nvkm_oclass nv35_gr_oclass;
+extern struct nvkm_oclass nv40_gr_oclass;
+extern struct nvkm_oclass nv50_gr_oclass;
+extern struct nvkm_oclass *gf100_gr_oclass;
+extern struct nvkm_oclass *gf108_gr_oclass;
+extern struct nvkm_oclass *gf104_gr_oclass;
+extern struct nvkm_oclass *gf110_gr_oclass;
+extern struct nvkm_oclass *gf117_gr_oclass;
+extern struct nvkm_oclass *gf119_gr_oclass;
+extern struct nvkm_oclass *gk104_gr_oclass;
+extern struct nvkm_oclass *gk20a_gr_oclass;
+extern struct nvkm_oclass *gk110_gr_oclass;
+extern struct nvkm_oclass *gk110b_gr_oclass;
+extern struct nvkm_oclass *gk208_gr_oclass;
+extern struct nvkm_oclass *gm107_gr_oclass;
-extern const struct nouveau_bitfield nv04_gr_nsource[];
-extern struct nouveau_ofuncs nv04_gr_ofuncs;
+#include <core/enum.h>
+
+extern const struct nvkm_bitfield nv04_gr_nsource[];
+extern struct nvkm_ofuncs nv04_gr_ofuncs;
bool nv04_gr_idle(void *obj);
-extern const struct nouveau_bitfield nv10_gr_intr_name[];
-extern const struct nouveau_bitfield nv10_gr_nstatus[];
-
-extern const struct nouveau_enum nv50_data_error_names[];
+extern const struct nvkm_bitfield nv10_gr_intr_name[];
+extern const struct nvkm_bitfield nv10_gr_nstatus[];
+extern const struct nvkm_enum nv50_data_error_names[];
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 3ebf7172835b..15ed4382e67e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -83,7 +83,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -116,7 +116,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -149,7 +149,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -181,7 +181,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -214,7 +214,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -246,7 +246,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -278,7 +278,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -311,7 +311,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -341,7 +341,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index cc06a67bbeac..6c3842ce034b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -83,7 +83,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
@@ -117,7 +117,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
@@ -151,7 +151,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
@@ -207,7 +207,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
@@ -275,7 +275,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
@@ -308,7 +308,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
index ce508e85b8f0..1771d944591b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
@@ -1,16 +1,16 @@
nvkm-y += nvkm/engine/gr/ctxnv40.o
nvkm-y += nvkm/engine/gr/ctxnv50.o
-nvkm-y += nvkm/engine/gr/ctxnvc0.o
-nvkm-y += nvkm/engine/gr/ctxnvc1.o
-nvkm-y += nvkm/engine/gr/ctxnvc4.o
-nvkm-y += nvkm/engine/gr/ctxnvc8.o
-nvkm-y += nvkm/engine/gr/ctxnvd7.o
-nvkm-y += nvkm/engine/gr/ctxnvd9.o
-nvkm-y += nvkm/engine/gr/ctxnve4.o
+nvkm-y += nvkm/engine/gr/ctxgf100.o
+nvkm-y += nvkm/engine/gr/ctxgf108.o
+nvkm-y += nvkm/engine/gr/ctxgf104.o
+nvkm-y += nvkm/engine/gr/ctxgf110.o
+nvkm-y += nvkm/engine/gr/ctxgf117.o
+nvkm-y += nvkm/engine/gr/ctxgf119.o
+nvkm-y += nvkm/engine/gr/ctxgk104.o
nvkm-y += nvkm/engine/gr/ctxgk20a.o
-nvkm-y += nvkm/engine/gr/ctxnvf0.o
+nvkm-y += nvkm/engine/gr/ctxgk110.o
nvkm-y += nvkm/engine/gr/ctxgk110b.o
-nvkm-y += nvkm/engine/gr/ctxnv108.o
+nvkm-y += nvkm/engine/gr/ctxgk208.o
nvkm-y += nvkm/engine/gr/ctxgm107.o
nvkm-y += nvkm/engine/gr/nv04.o
nvkm-y += nvkm/engine/gr/nv10.o
@@ -22,15 +22,15 @@ nvkm-y += nvkm/engine/gr/nv34.o
nvkm-y += nvkm/engine/gr/nv35.o
nvkm-y += nvkm/engine/gr/nv40.o
nvkm-y += nvkm/engine/gr/nv50.o
-nvkm-y += nvkm/engine/gr/nvc0.o
-nvkm-y += nvkm/engine/gr/nvc1.o
-nvkm-y += nvkm/engine/gr/nvc4.o
-nvkm-y += nvkm/engine/gr/nvc8.o
-nvkm-y += nvkm/engine/gr/nvd7.o
-nvkm-y += nvkm/engine/gr/nvd9.o
-nvkm-y += nvkm/engine/gr/nve4.o
+nvkm-y += nvkm/engine/gr/gf100.o
+nvkm-y += nvkm/engine/gr/gf108.o
+nvkm-y += nvkm/engine/gr/gf104.o
+nvkm-y += nvkm/engine/gr/gf110.o
+nvkm-y += nvkm/engine/gr/gf117.o
+nvkm-y += nvkm/engine/gr/gf119.o
+nvkm-y += nvkm/engine/gr/gk104.o
nvkm-y += nvkm/engine/gr/gk20a.o
-nvkm-y += nvkm/engine/gr/nvf0.o
+nvkm-y += nvkm/engine/gr/gk110.o
nvkm-y += nvkm/engine/gr/gk110b.o
-nvkm-y += nvkm/engine/gr/nv108.o
+nvkm-y += nvkm/engine/gr/gk208.o
nvkm-y += nvkm/engine/gr/gm107.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
similarity index 86%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
index 08a925efecf2..2e7ec389eea7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
@@ -21,15 +21,19 @@
*
* Authors: Ben Skeggs
*/
+#include "ctxgf100.h"
-#include "ctxnvc0.h"
+#include <subdev/bar.h>
+#include <subdev/fb.h>
+#include <subdev/mc.h>
+#include <subdev/timer.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvc0_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
@@ -266,14 +270,14 @@ nvc0_grctx_init_icmd_0[] = {
{}
};
-const struct nvc0_gr_pack
-nvc0_grctx_pack_icmd[] = {
- { nvc0_grctx_init_icmd_0 },
+const struct gf100_gr_pack
+gf100_grctx_pack_icmd[] = {
+ { gf100_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_9097_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_9097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
@@ -575,8 +579,8 @@ nvc0_grctx_init_9097_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_902d_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_902d_0[] = {
{ 0x000200, 1, 0x04, 0x000000cf },
{ 0x000204, 1, 0x04, 0x00000001 },
{ 0x000208, 1, 0x04, 0x00000020 },
@@ -594,8 +598,8 @@ nvc0_grctx_init_902d_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_9039_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_9039_0[] = {
{ 0x00030c, 3, 0x04, 0x00000000 },
{ 0x000320, 1, 0x04, 0x00000000 },
{ 0x000238, 2, 0x04, 0x00000000 },
@@ -603,8 +607,8 @@ nvc0_grctx_init_9039_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_90c0_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_90c0_0[] = {
{ 0x00270c, 8, 0x20, 0x00000000 },
{ 0x00030c, 1, 0x04, 0x00000001 },
{ 0x001944, 1, 0x04, 0x00000000 },
@@ -621,23 +625,23 @@ nvc0_grctx_init_90c0_0[] = {
{}
};
-const struct nvc0_gr_pack
-nvc0_grctx_pack_mthd[] = {
- { nvc0_grctx_init_9097_0, 0x9097 },
- { nvc0_grctx_init_902d_0, 0x902d },
- { nvc0_grctx_init_9039_0, 0x9039 },
- { nvc0_grctx_init_90c0_0, 0x90c0 },
+const struct gf100_gr_pack
+gf100_grctx_pack_mthd[] = {
+ { gf100_grctx_init_9097_0, 0x9097 },
+ { gf100_grctx_init_902d_0, 0x902d },
+ { gf100_grctx_init_9039_0, 0x9039 },
+ { gf100_grctx_init_90c0_0, 0x90c0 },
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_main_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_main_0[] = {
{ 0x400204, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_fe_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_fe_0[] = {
{ 0x404004, 11, 0x04, 0x00000000 },
{ 0x404044, 1, 0x04, 0x00000000 },
{ 0x404094, 13, 0x04, 0x00000000 },
@@ -657,8 +661,8 @@ nvc0_grctx_init_fe_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_pri_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_pri_0[] = {
{ 0x404404, 14, 0x04, 0x00000000 },
{ 0x404460, 2, 0x04, 0x00000000 },
{ 0x404468, 1, 0x04, 0x00ffffff },
@@ -668,8 +672,8 @@ nvc0_grctx_init_pri_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_memfmt_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_memfmt_0[] = {
{ 0x404604, 1, 0x04, 0x00000015 },
{ 0x404608, 1, 0x04, 0x00000000 },
{ 0x40460c, 1, 0x04, 0x00002e00 },
@@ -690,8 +694,8 @@ nvc0_grctx_init_memfmt_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_ds_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x078000bf },
{ 0x405830, 1, 0x04, 0x02180000 },
{ 0x405834, 2, 0x04, 0x00000000 },
@@ -702,8 +706,8 @@ nvc0_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -712,8 +716,8 @@ nvc0_grctx_init_pd_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_rstr2d_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_rstr2d_0[] = {
{ 0x407804, 1, 0x04, 0x00000023 },
{ 0x40780c, 1, 0x04, 0x0a418820 },
{ 0x407810, 1, 0x04, 0x062080e6 },
@@ -725,8 +729,8 @@ nvc0_grctx_init_rstr2d_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_scc_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_scc_0[] = {
{ 0x408000, 2, 0x04, 0x00000000 },
{ 0x408008, 1, 0x04, 0x00000018 },
{ 0x40800c, 2, 0x04, 0x00000000 },
@@ -736,8 +740,8 @@ nvc0_grctx_init_scc_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_be_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x0003e00d },
@@ -748,28 +752,28 @@ nvc0_grctx_init_be_0[] = {
{}
};
-const struct nvc0_gr_pack
-nvc0_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nvc0_grctx_init_fe_0 },
- { nvc0_grctx_init_pri_0 },
- { nvc0_grctx_init_memfmt_0 },
- { nvc0_grctx_init_ds_0 },
- { nvc0_grctx_init_pd_0 },
- { nvc0_grctx_init_rstr2d_0 },
- { nvc0_grctx_init_scc_0 },
- { nvc0_grctx_init_be_0 },
+const struct gf100_gr_pack
+gf100_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gf100_grctx_init_fe_0 },
+ { gf100_grctx_init_pri_0 },
+ { gf100_grctx_init_memfmt_0 },
+ { gf100_grctx_init_ds_0 },
+ { gf100_grctx_init_pd_0 },
+ { gf100_grctx_init_rstr2d_0 },
+ { gf100_grctx_init_scc_0 },
+ { gf100_grctx_init_be_0 },
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_gpc_unk_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_gpc_unk_0[] = {
{ 0x418380, 1, 0x04, 0x00000016 },
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_prop_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38004e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
{ 0x418408, 1, 0x04, 0x00000000 },
@@ -782,8 +786,8 @@ nvc0_grctx_init_prop_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_gpc_unk_1[] = {
+const struct gf100_gr_init
+gf100_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000001f },
{ 0x418684, 1, 0x04, 0x0000000f },
{ 0x418700, 1, 0x04, 0x00000002 },
@@ -794,8 +798,8 @@ nvc0_grctx_init_gpc_unk_1[] = {
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
@@ -807,8 +811,8 @@ nvc0_grctx_init_setup_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_zcull_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_zcull_0[] = {
{ 0x41891c, 1, 0x04, 0x00ff00ff },
{ 0x418924, 1, 0x04, 0x00000000 },
{ 0x418928, 1, 0x04, 0x00ffff00 },
@@ -816,8 +820,8 @@ nvc0_grctx_init_zcull_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_crstr_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x00000000 },
{ 0x418b08, 1, 0x04, 0x0a418820 },
{ 0x418b0c, 1, 0x04, 0x062080e6 },
@@ -829,8 +833,8 @@ nvc0_grctx_init_crstr_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_gpm_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c80, 1, 0x04, 0x20200004 },
@@ -838,29 +842,29 @@ nvc0_grctx_init_gpm_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_gcc_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_gcc_0[] = {
{ 0x419000, 1, 0x04, 0x00000780 },
{ 0x419004, 2, 0x04, 0x00000000 },
{ 0x419014, 1, 0x04, 0x00000004 },
{}
};
-const struct nvc0_gr_pack
-nvc0_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvc0_grctx_init_prop_0 },
- { nvc0_grctx_init_gpc_unk_1 },
- { nvc0_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvc0_grctx_init_crstr_0 },
- { nvc0_grctx_init_gpm_0 },
- { nvc0_grctx_init_gcc_0 },
+const struct gf100_gr_pack
+gf100_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf100_grctx_init_prop_0 },
+ { gf100_grctx_init_gpc_unk_1 },
+ { gf100_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf100_grctx_init_crstr_0 },
+ { gf100_grctx_init_gpm_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_zcullr_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_zcullr_0[] = {
{ 0x418a00, 3, 0x04, 0x00000000 },
{ 0x418a0c, 1, 0x04, 0x00010000 },
{ 0x418a10, 3, 0x04, 0x00000000 },
@@ -888,14 +892,14 @@ nvc0_grctx_init_zcullr_0[] = {
{}
};
-const struct nvc0_gr_pack
-nvc0_grctx_pack_zcull[] = {
- { nvc0_grctx_init_zcullr_0 },
+const struct gf100_gr_pack
+gf100_grctx_pack_zcull[] = {
+ { gf100_grctx_init_zcullr_0 },
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_pe_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_pe_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
@@ -904,8 +908,8 @@ nvc0_grctx_init_pe_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_tex_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
@@ -915,8 +919,8 @@ nvc0_grctx_init_tex_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_wwdx_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_wwdx_0[] = {
{ 0x419b00, 1, 0x04, 0x0a418820 },
{ 0x419b04, 1, 0x04, 0x062080e6 },
{ 0x419b08, 1, 0x04, 0x020398a4 },
@@ -929,8 +933,8 @@ nvc0_grctx_init_wwdx_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_mpc_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x00000002 },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
@@ -938,23 +942,23 @@ nvc0_grctx_init_mpc_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_l1c_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_l1c_0[] = {
{ 0x419cb0, 1, 0x04, 0x00060048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000183 },
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_tpccs_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_tpccs_0[] = {
{ 0x419d20, 1, 0x04, 0x02180000 },
{ 0x419d24, 1, 0x04, 0x00001fff },
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_sm_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
@@ -966,15 +970,15 @@ nvc0_grctx_init_sm_0[] = {
{}
};
-const struct nvc0_gr_pack
-nvc0_grctx_pack_tpc[] = {
- { nvc0_grctx_init_pe_0 },
- { nvc0_grctx_init_tex_0 },
- { nvc0_grctx_init_wwdx_0 },
- { nvc0_grctx_init_mpc_0 },
- { nvc0_grctx_init_l1c_0 },
- { nvc0_grctx_init_tpccs_0 },
- { nvc0_grctx_init_sm_0 },
+const struct gf100_gr_pack
+gf100_grctx_pack_tpc[] = {
+ { gf100_grctx_init_pe_0 },
+ { gf100_grctx_init_tex_0 },
+ { gf100_grctx_init_wwdx_0 },
+ { gf100_grctx_init_mpc_0 },
+ { gf100_grctx_init_l1c_0 },
+ { gf100_grctx_init_tpccs_0 },
+ { gf100_grctx_init_sm_0 },
{}
};
@@ -983,7 +987,7 @@ nvc0_grctx_pack_tpc[] = {
******************************************************************************/
int
-nvc0_grctx_mmio_data(struct nvc0_grctx *info, u32 size, u32 align, u32 access)
+gf100_grctx_mmio_data(struct gf100_grctx *info, u32 size, u32 align, u32 access)
{
if (info->data) {
info->buffer[info->buffer_nr] = round_up(info->addr, align);
@@ -998,8 +1002,8 @@ nvc0_grctx_mmio_data(struct nvc0_grctx *info, u32 size, u32 align, u32 access)
}
void
-nvc0_grctx_mmio_item(struct nvc0_grctx *info, u32 addr, u32 data,
- int shift, int buffer)
+gf100_grctx_mmio_item(struct gf100_grctx *info, u32 addr, u32 data,
+ int shift, int buffer)
{
if (info->data) {
if (shift >= 0) {
@@ -1021,9 +1025,9 @@ nvc0_grctx_mmio_item(struct nvc0_grctx *info, u32 addr, u32 data,
}
void
-nvc0_grctx_generate_bundle(struct nvc0_grctx *info)
+gf100_grctx_generate_bundle(struct gf100_grctx *info)
{
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);
@@ -1034,9 +1038,9 @@ nvc0_grctx_generate_bundle(struct nvc0_grctx *info)
}
void
-nvc0_grctx_generate_pagepool(struct nvc0_grctx *info)
+gf100_grctx_generate_pagepool(struct gf100_grctx *info)
{
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
@@ -1047,10 +1051,10 @@ nvc0_grctx_generate_pagepool(struct nvc0_grctx *info)
}
void
-nvc0_grctx_generate_attrib(struct nvc0_grctx *info)
+gf100_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct nvc0_gr_priv *priv = info->priv;
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
+ struct gf100_gr_priv *priv = info->priv;
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
const u32 attrib = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
const u32 access = NV_MEM_ACCESS_RW;
@@ -1074,12 +1078,12 @@ nvc0_grctx_generate_attrib(struct nvc0_grctx *info)
}
void
-nvc0_grctx_generate_unkn(struct nvc0_gr_priv *priv)
+gf100_grctx_generate_unkn(struct gf100_gr_priv *priv)
{
}
void
-nvc0_grctx_generate_tpcid(struct nvc0_gr_priv *priv)
+gf100_grctx_generate_tpcid(struct gf100_gr_priv *priv)
{
int gpc, tpc, id;
@@ -1100,7 +1104,7 @@ nvc0_grctx_generate_tpcid(struct nvc0_gr_priv *priv)
}
void
-nvc0_grctx_generate_r406028(struct nvc0_gr_priv *priv)
+gf100_grctx_generate_r406028(struct gf100_gr_priv *priv)
{
u32 tmp[GPC_MAX / 8] = {}, i = 0;
for (i = 0; i < priv->gpc_nr; i++)
@@ -1112,7 +1116,7 @@ nvc0_grctx_generate_r406028(struct nvc0_gr_priv *priv)
}
void
-nvc0_grctx_generate_r4060a8(struct nvc0_gr_priv *priv)
+gf100_grctx_generate_r4060a8(struct gf100_gr_priv *priv)
{
u8 tpcnr[GPC_MAX], data[TPC_MAX];
int gpc, tpc, i;
@@ -1134,7 +1138,7 @@ nvc0_grctx_generate_r4060a8(struct nvc0_gr_priv *priv)
}
void
-nvc0_grctx_generate_r418bb8(struct nvc0_gr_priv *priv)
+gf100_grctx_generate_r418bb8(struct gf100_gr_priv *priv)
{
u32 data[6] = {}, data2[2] = {};
u8 tpcnr[GPC_MAX];
@@ -1192,7 +1196,7 @@ nvc0_grctx_generate_r418bb8(struct nvc0_gr_priv *priv)
}
void
-nvc0_grctx_generate_r406800(struct nvc0_gr_priv *priv)
+gf100_grctx_generate_r406800(struct gf100_gr_priv *priv)
{
u64 tpc_mask = 0, tpc_set = 0;
u8 tpcnr[GPC_MAX];
@@ -1225,17 +1229,17 @@ nvc0_grctx_generate_r406800(struct nvc0_gr_priv *priv)
}
void
-nvc0_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
+gf100_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
{
- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
- nvc0_gr_mmio(priv, oclass->hub);
- nvc0_gr_mmio(priv, oclass->gpc);
- nvc0_gr_mmio(priv, oclass->zcull);
- nvc0_gr_mmio(priv, oclass->tpc);
- nvc0_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(priv, oclass->hub);
+ gf100_gr_mmio(priv, oclass->gpc);
+ gf100_gr_mmio(priv, oclass->zcull);
+ gf100_gr_mmio(priv, oclass->tpc);
+ gf100_gr_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
@@ -1244,32 +1248,32 @@ nvc0_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
oclass->attrib(info);
oclass->unkn(priv);
- nvc0_grctx_generate_tpcid(priv);
- nvc0_grctx_generate_r406028(priv);
- nvc0_grctx_generate_r4060a8(priv);
- nvc0_grctx_generate_r418bb8(priv);
- nvc0_grctx_generate_r406800(priv);
+ gf100_grctx_generate_tpcid(priv);
+ gf100_grctx_generate_r406028(priv);
+ gf100_grctx_generate_r4060a8(priv);
+ gf100_grctx_generate_r418bb8(priv);
+ gf100_grctx_generate_r406800(priv);
- nvc0_gr_icmd(priv, oclass->icmd);
+ gf100_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
- nvc0_gr_mthd(priv, oclass->mthd);
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
+ gf100_gr_mthd(priv, oclass->mthd);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
}
int
-nvc0_grctx_generate(struct nvc0_gr_priv *priv)
+gf100_grctx_generate(struct gf100_gr_priv *priv)
{
- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
- struct nouveau_bar *bar = nouveau_bar(priv);
- struct nouveau_gpuobj *chan;
- struct nvc0_grctx info;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct nvkm_bar *bar = nvkm_bar(priv);
+ struct nvkm_gpuobj *chan;
+ struct gf100_grctx info;
int ret, i;
/* allocate memory to for a "channel", which we'll use to generate
* the default context values
*/
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size,
- 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size,
+ 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan);
if (ret) {
nv_error(priv, "failed to allocate channel memory, %d\n", ret);
return ret;
@@ -1353,34 +1357,34 @@ nvc0_grctx_generate(struct nvc0_gr_priv *priv)
}
done:
- nouveau_gpuobj_ref(NULL, &chan);
+ nvkm_gpuobj_ref(NULL, &chan);
return ret;
}
-struct nouveau_oclass *
-nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gf100_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nvc0_grctx_generate_main,
- .unkn = nvc0_grctx_generate_unkn,
- .hub = nvc0_grctx_pack_hub,
- .gpc = nvc0_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvc0_grctx_pack_tpc,
- .icmd = nvc0_grctx_pack_icmd,
- .mthd = nvc0_grctx_pack_mthd,
- .bundle = nvc0_grctx_generate_bundle,
+ .main = gf100_grctx_generate_main,
+ .unkn = gf100_grctx_generate_unkn,
+ .hub = gf100_grctx_pack_hub,
+ .gpc = gf100_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gf100_grctx_pack_tpc,
+ .icmd = gf100_grctx_pack_icmd,
+ .mthd = gf100_grctx_pack_mthd,
+ .bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
- .pagepool = nvc0_grctx_generate_pagepool,
+ .pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvc0_grctx_generate_attrib,
+ .attrib = gf100_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
new file mode 100644
index 000000000000..1166b1aa1525
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
@@ -0,0 +1,199 @@
+#ifndef __NVKM_GRCTX_NVC0_H__
+#define __NVKM_GRCTX_NVC0_H__
+#include "gf100.h"
+
+struct gf100_grctx {
+ struct gf100_gr_priv *priv;
+ struct gf100_gr_data *data;
+ struct gf100_gr_mmio *mmio;
+ int buffer_nr;
+ u64 buffer[4];
+ u64 addr;
+};
+
+int gf100_grctx_mmio_data(struct gf100_grctx *, u32 size, u32 align, u32 access);
+void gf100_grctx_mmio_item(struct gf100_grctx *, u32 addr, u32 data, int s, int);
+
+#define mmio_vram(a,b,c,d) gf100_grctx_mmio_data((a), (b), (c), (d))
+#define mmio_refn(a,b,c,d,e) gf100_grctx_mmio_item((a), (b), (c), (d), (e))
+#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1)
+#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1)
+
+struct gf100_grctx_oclass {
+ struct nvkm_oclass base;
+ /* main context generation function */
+ void (*main)(struct gf100_gr_priv *, struct gf100_grctx *);
+ /* context-specific modify-on-first-load list generation function */
+ void (*unkn)(struct gf100_gr_priv *);
+ /* mmio context data */
+ const struct gf100_gr_pack *hub;
+ const struct gf100_gr_pack *gpc;
+ const struct gf100_gr_pack *zcull;
+ const struct gf100_gr_pack *tpc;
+ const struct gf100_gr_pack *ppc;
+ /* indirect context data, generated with icmds/mthds */
+ const struct gf100_gr_pack *icmd;
+ const struct gf100_gr_pack *mthd;
+ /* bundle circular buffer */
+ void (*bundle)(struct gf100_grctx *);
+ u32 bundle_size;
+ u32 bundle_min_gpm_fifo_depth;
+ u32 bundle_token_limit;
+ /* pagepool */
+ void (*pagepool)(struct gf100_grctx *);
+ u32 pagepool_size;
+ /* attribute(/alpha) circular buffer */
+ void (*attrib)(struct gf100_grctx *);
+ u32 attrib_nr_max;
+ u32 attrib_nr;
+ u32 alpha_nr_max;
+ u32 alpha_nr;
+};
+
+static inline const struct gf100_grctx_oclass *
+gf100_grctx_impl(struct gf100_gr_priv *priv)
+{
+ return (void *)nv_engine(priv)->cclass;
+}
+
+extern struct nvkm_oclass *gf100_grctx_oclass;
+int gf100_grctx_generate(struct gf100_gr_priv *);
+void gf100_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
+void gf100_grctx_generate_bundle(struct gf100_grctx *);
+void gf100_grctx_generate_pagepool(struct gf100_grctx *);
+void gf100_grctx_generate_attrib(struct gf100_grctx *);
+void gf100_grctx_generate_unkn(struct gf100_gr_priv *);
+void gf100_grctx_generate_tpcid(struct gf100_gr_priv *);
+void gf100_grctx_generate_r406028(struct gf100_gr_priv *);
+void gf100_grctx_generate_r4060a8(struct gf100_gr_priv *);
+void gf100_grctx_generate_r418bb8(struct gf100_gr_priv *);
+void gf100_grctx_generate_r406800(struct gf100_gr_priv *);
+
+extern struct nvkm_oclass *gf108_grctx_oclass;
+void gf108_grctx_generate_attrib(struct gf100_grctx *);
+void gf108_grctx_generate_unkn(struct gf100_gr_priv *);
+
+extern struct nvkm_oclass *gf104_grctx_oclass;
+extern struct nvkm_oclass *gf110_grctx_oclass;
+
+extern struct nvkm_oclass *gf117_grctx_oclass;
+void gf117_grctx_generate_attrib(struct gf100_grctx *);
+
+extern struct nvkm_oclass *gf119_grctx_oclass;
+
+extern struct nvkm_oclass *gk104_grctx_oclass;
+extern struct nvkm_oclass *gk20a_grctx_oclass;
+void gk104_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
+void gk104_grctx_generate_bundle(struct gf100_grctx *);
+void gk104_grctx_generate_pagepool(struct gf100_grctx *);
+void gk104_grctx_generate_unkn(struct gf100_gr_priv *);
+void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *);
+
+extern struct nvkm_oclass *gk110_grctx_oclass;
+extern struct nvkm_oclass *gk110b_grctx_oclass;
+extern struct nvkm_oclass *gk208_grctx_oclass;
+extern struct nvkm_oclass *gm107_grctx_oclass;
+
+/* context init value lists */
+
+extern const struct gf100_gr_pack gf100_grctx_pack_icmd[];
+
+extern const struct gf100_gr_pack gf100_grctx_pack_mthd[];
+extern const struct gf100_gr_init gf100_grctx_init_902d_0[];
+extern const struct gf100_gr_init gf100_grctx_init_9039_0[];
+extern const struct gf100_gr_init gf100_grctx_init_90c0_0[];
+
+extern const struct gf100_gr_pack gf100_grctx_pack_hub[];
+extern const struct gf100_gr_init gf100_grctx_init_main_0[];
+extern const struct gf100_gr_init gf100_grctx_init_fe_0[];
+extern const struct gf100_gr_init gf100_grctx_init_pri_0[];
+extern const struct gf100_gr_init gf100_grctx_init_memfmt_0[];
+extern const struct gf100_gr_init gf100_grctx_init_rstr2d_0[];
+extern const struct gf100_gr_init gf100_grctx_init_scc_0[];
+
+extern const struct gf100_gr_pack gf100_grctx_pack_gpc[];
+extern const struct gf100_gr_init gf100_grctx_init_gpc_unk_0[];
+extern const struct gf100_gr_init gf100_grctx_init_prop_0[];
+extern const struct gf100_gr_init gf100_grctx_init_gpc_unk_1[];
+extern const struct gf100_gr_init gf100_grctx_init_zcull_0[];
+extern const struct gf100_gr_init gf100_grctx_init_crstr_0[];
+extern const struct gf100_gr_init gf100_grctx_init_gpm_0[];
+extern const struct gf100_gr_init gf100_grctx_init_gcc_0[];
+
+extern const struct gf100_gr_pack gf100_grctx_pack_zcull[];
+
+extern const struct gf100_gr_pack gf100_grctx_pack_tpc[];
+extern const struct gf100_gr_init gf100_grctx_init_pe_0[];
+extern const struct gf100_gr_init gf100_grctx_init_wwdx_0[];
+extern const struct gf100_gr_init gf100_grctx_init_mpc_0[];
+extern const struct gf100_gr_init gf100_grctx_init_tpccs_0[];
+
+extern const struct gf100_gr_init gf104_grctx_init_tex_0[];
+extern const struct gf100_gr_init gf104_grctx_init_l1c_0[];
+extern const struct gf100_gr_init gf104_grctx_init_sm_0[];
+
+extern const struct gf100_gr_init gf108_grctx_init_9097_0[];
+
+extern const struct gf100_gr_init gf108_grctx_init_gpm_0[];
+
+extern const struct gf100_gr_init gf108_grctx_init_pe_0[];
+extern const struct gf100_gr_init gf108_grctx_init_wwdx_0[];
+extern const struct gf100_gr_init gf108_grctx_init_tpccs_0[];
+
+extern const struct gf100_gr_init gf110_grctx_init_9197_0[];
+extern const struct gf100_gr_init gf110_grctx_init_9297_0[];
+
+extern const struct gf100_gr_pack gf119_grctx_pack_icmd[];
+
+extern const struct gf100_gr_pack gf119_grctx_pack_mthd[];
+
+extern const struct gf100_gr_init gf119_grctx_init_fe_0[];
+extern const struct gf100_gr_init gf119_grctx_init_be_0[];
+
+extern const struct gf100_gr_init gf119_grctx_init_prop_0[];
+extern const struct gf100_gr_init gf119_grctx_init_gpc_unk_1[];
+extern const struct gf100_gr_init gf119_grctx_init_crstr_0[];
+
+extern const struct gf100_gr_init gf119_grctx_init_sm_0[];
+
+extern const struct gf100_gr_init gf117_grctx_init_pe_0[];
+
+extern const struct gf100_gr_init gf117_grctx_init_wwdx_0[];
+
+extern const struct gf100_gr_init gk104_grctx_init_memfmt_0[];
+extern const struct gf100_gr_init gk104_grctx_init_ds_0[];
+extern const struct gf100_gr_init gk104_grctx_init_scc_0[];
+
+extern const struct gf100_gr_init gk104_grctx_init_gpm_0[];
+
+extern const struct gf100_gr_init gk104_grctx_init_pes_0[];
+
+extern const struct gf100_gr_pack gk104_grctx_pack_hub[];
+extern const struct gf100_gr_pack gk104_grctx_pack_gpc[];
+extern const struct gf100_gr_pack gk104_grctx_pack_tpc[];
+extern const struct gf100_gr_pack gk104_grctx_pack_ppc[];
+extern const struct gf100_gr_pack gk104_grctx_pack_icmd[];
+extern const struct gf100_gr_init gk104_grctx_init_a097_0[];
+
+extern const struct gf100_gr_pack gk110_grctx_pack_icmd[];
+
+extern const struct gf100_gr_pack gk110_grctx_pack_mthd[];
+
+extern const struct gf100_gr_pack gk110_grctx_pack_hub[];
+extern const struct gf100_gr_init gk110_grctx_init_pri_0[];
+extern const struct gf100_gr_init gk110_grctx_init_cwd_0[];
+
+extern const struct gf100_gr_pack gk110_grctx_pack_gpc[];
+extern const struct gf100_gr_init gk110_grctx_init_gpc_unk_2[];
+
+extern const struct gf100_gr_init gk110_grctx_init_tex_0[];
+extern const struct gf100_gr_init gk110_grctx_init_mpc_0[];
+extern const struct gf100_gr_init gk110_grctx_init_l1c_0[];
+
+extern const struct gf100_gr_pack gk110_grctx_pack_ppc[];
+
+extern const struct gf100_gr_init gk208_grctx_init_rstr2d_0[];
+
+extern const struct gf100_gr_init gk208_grctx_init_prop_0[];
+extern const struct gf100_gr_init gk208_grctx_init_crstr_0[];
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c
similarity index 68%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c
index c883e7229fd5..c5a8d55e2cac 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "ctxnvc0.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-const struct nvc0_gr_init
-nvc4_grctx_init_tex_0[] = {
+const struct gf100_gr_init
+gf104_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
@@ -42,16 +41,16 @@ nvc4_grctx_init_tex_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc4_grctx_init_l1c_0[] = {
+const struct gf100_gr_init
+gf104_grctx_init_l1c_0[] = {
{ 0x419cb0, 1, 0x04, 0x00020048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000183 },
{}
};
-const struct nvc0_gr_init
-nvc4_grctx_init_sm_0[] = {
+const struct gf100_gr_init
+gf104_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
@@ -64,15 +63,15 @@ nvc4_grctx_init_sm_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvc4_grctx_pack_tpc[] = {
- { nvc0_grctx_init_pe_0 },
- { nvc4_grctx_init_tex_0 },
- { nvc0_grctx_init_wwdx_0 },
- { nvc0_grctx_init_mpc_0 },
- { nvc4_grctx_init_l1c_0 },
- { nvc0_grctx_init_tpccs_0 },
- { nvc4_grctx_init_sm_0 },
+static const struct gf100_gr_pack
+gf104_grctx_pack_tpc[] = {
+ { gf100_grctx_init_pe_0 },
+ { gf104_grctx_init_tex_0 },
+ { gf100_grctx_init_wwdx_0 },
+ { gf100_grctx_init_mpc_0 },
+ { gf104_grctx_init_l1c_0 },
+ { gf100_grctx_init_tpccs_0 },
+ { gf104_grctx_init_sm_0 },
{}
};
@@ -80,30 +79,30 @@ nvc4_grctx_pack_tpc[] = {
* PGRAPH context implementation
******************************************************************************/
-struct nouveau_oclass *
-nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gf104_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc3),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nvc0_grctx_generate_main,
- .unkn = nvc0_grctx_generate_unkn,
- .hub = nvc0_grctx_pack_hub,
- .gpc = nvc0_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvc4_grctx_pack_tpc,
- .icmd = nvc0_grctx_pack_icmd,
- .mthd = nvc0_grctx_pack_mthd,
- .bundle = nvc0_grctx_generate_bundle,
+ .main = gf100_grctx_generate_main,
+ .unkn = gf100_grctx_generate_unkn,
+ .hub = gf100_grctx_pack_hub,
+ .gpc = gf100_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gf104_grctx_pack_tpc,
+ .icmd = gf100_grctx_pack_icmd,
+ .mthd = gf100_grctx_pack_mthd,
+ .bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
- .pagepool = nvc0_grctx_generate_pagepool,
+ .pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvc0_grctx_generate_attrib,
+ .attrib = gf100_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c
similarity index 89%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c
index b5ced99abce9..87c844a5f34b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c
@@ -21,15 +21,16 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "ctxgf100.h"
-#include "ctxnvc0.h"
+#include <subdev/fb.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvc1_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gf108_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
@@ -267,14 +268,14 @@ nvc1_grctx_init_icmd_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvc1_grctx_pack_icmd[] = {
- { nvc1_grctx_init_icmd_0 },
+static const struct gf100_gr_pack
+gf108_grctx_pack_icmd[] = {
+ { gf108_grctx_init_icmd_0 },
{}
};
-const struct nvc0_gr_init
-nvc1_grctx_init_9097_0[] = {
+const struct gf100_gr_init
+gf108_grctx_init_9097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
@@ -575,25 +576,25 @@ nvc1_grctx_init_9097_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvc1_grctx_init_9197_0[] = {
+static const struct gf100_gr_init
+gf108_grctx_init_9197_0[] = {
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{}
};
-static const struct nvc0_gr_pack
-nvc1_grctx_pack_mthd[] = {
- { nvc1_grctx_init_9097_0, 0x9097 },
- { nvc1_grctx_init_9197_0, 0x9197 },
- { nvc0_grctx_init_902d_0, 0x902d },
- { nvc0_grctx_init_9039_0, 0x9039 },
- { nvc0_grctx_init_90c0_0, 0x90c0 },
+static const struct gf100_gr_pack
+gf108_grctx_pack_mthd[] = {
+ { gf108_grctx_init_9097_0, 0x9097 },
+ { gf108_grctx_init_9197_0, 0x9197 },
+ { gf100_grctx_init_902d_0, 0x902d },
+ { gf100_grctx_init_9039_0, 0x9039 },
+ { gf100_grctx_init_90c0_0, 0x90c0 },
{}
};
-static const struct nvc0_gr_init
-nvc1_grctx_init_ds_0[] = {
+static const struct gf100_gr_init
+gf108_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180218 },
{ 0x405834, 2, 0x04, 0x00000000 },
@@ -604,8 +605,8 @@ nvc1_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvc1_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gf108_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -616,8 +617,8 @@ nvc1_grctx_init_pd_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvc1_grctx_init_be_0[] = {
+static const struct gf100_gr_init
+gf108_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
@@ -628,22 +629,22 @@ nvc1_grctx_init_be_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvc1_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nvc0_grctx_init_fe_0 },
- { nvc0_grctx_init_pri_0 },
- { nvc0_grctx_init_memfmt_0 },
- { nvc1_grctx_init_ds_0 },
- { nvc1_grctx_init_pd_0 },
- { nvc0_grctx_init_rstr2d_0 },
- { nvc0_grctx_init_scc_0 },
- { nvc1_grctx_init_be_0 },
+static const struct gf100_gr_pack
+gf108_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gf100_grctx_init_fe_0 },
+ { gf100_grctx_init_pri_0 },
+ { gf100_grctx_init_memfmt_0 },
+ { gf108_grctx_init_ds_0 },
+ { gf108_grctx_init_pd_0 },
+ { gf100_grctx_init_rstr2d_0 },
+ { gf100_grctx_init_scc_0 },
+ { gf108_grctx_init_be_0 },
{}
};
-static const struct nvc0_gr_init
-nvc1_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gf108_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
@@ -655,8 +656,8 @@ nvc1_grctx_init_setup_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc1_grctx_init_gpm_0[] = {
+const struct gf100_gr_init
+gf108_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c6c, 1, 0x04, 0x00000001 },
@@ -665,21 +666,21 @@ nvc1_grctx_init_gpm_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvc1_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvc0_grctx_init_prop_0 },
- { nvc0_grctx_init_gpc_unk_1 },
- { nvc1_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvc0_grctx_init_crstr_0 },
- { nvc1_grctx_init_gpm_0 },
- { nvc0_grctx_init_gcc_0 },
+static const struct gf100_gr_pack
+gf108_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf100_grctx_init_prop_0 },
+ { gf100_grctx_init_gpc_unk_1 },
+ { gf108_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf100_grctx_init_crstr_0 },
+ { gf108_grctx_init_gpm_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-const struct nvc0_gr_init
-nvc1_grctx_init_pe_0[] = {
+const struct gf100_gr_init
+gf108_grctx_init_pe_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
@@ -688,8 +689,8 @@ nvc1_grctx_init_pe_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc1_grctx_init_wwdx_0[] = {
+const struct gf100_gr_init
+gf108_grctx_init_wwdx_0[] = {
{ 0x419b00, 1, 0x04, 0x0a418820 },
{ 0x419b04, 1, 0x04, 0x062080e6 },
{ 0x419b08, 1, 0x04, 0x020398a4 },
@@ -702,23 +703,23 @@ nvc1_grctx_init_wwdx_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc1_grctx_init_tpccs_0[] = {
+const struct gf100_gr_init
+gf108_grctx_init_tpccs_0[] = {
{ 0x419d20, 1, 0x04, 0x12180000 },
{ 0x419d24, 1, 0x04, 0x00001fff },
{ 0x419d44, 1, 0x04, 0x02180218 },
{}
};
-static const struct nvc0_gr_pack
-nvc1_grctx_pack_tpc[] = {
- { nvc1_grctx_init_pe_0 },
- { nvc4_grctx_init_tex_0 },
- { nvc1_grctx_init_wwdx_0 },
- { nvc0_grctx_init_mpc_0 },
- { nvc4_grctx_init_l1c_0 },
- { nvc1_grctx_init_tpccs_0 },
- { nvc4_grctx_init_sm_0 },
+static const struct gf100_gr_pack
+gf108_grctx_pack_tpc[] = {
+ { gf108_grctx_init_pe_0 },
+ { gf104_grctx_init_tex_0 },
+ { gf108_grctx_init_wwdx_0 },
+ { gf100_grctx_init_mpc_0 },
+ { gf104_grctx_init_l1c_0 },
+ { gf108_grctx_init_tpccs_0 },
+ { gf104_grctx_init_sm_0 },
{}
};
@@ -727,10 +728,10 @@ nvc1_grctx_pack_tpc[] = {
******************************************************************************/
void
-nvc1_grctx_generate_attrib(struct nvc0_grctx *info)
+gf108_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct nvc0_gr_priv *priv = info->priv;
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
+ struct gf100_gr_priv *priv = info->priv;
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
const u32 alpha = impl->alpha_nr;
const u32 beta = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
@@ -764,7 +765,7 @@ nvc1_grctx_generate_attrib(struct nvc0_grctx *info)
}
void
-nvc1_grctx_generate_unkn(struct nvc0_gr_priv *priv)
+gf108_grctx_generate_unkn(struct gf100_gr_priv *priv)
{
nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
@@ -774,30 +775,30 @@ nvc1_grctx_generate_unkn(struct nvc0_gr_priv *priv)
nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
}
-struct nouveau_oclass *
-nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gf108_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc1),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nvc0_grctx_generate_main,
- .unkn = nvc1_grctx_generate_unkn,
- .hub = nvc1_grctx_pack_hub,
- .gpc = nvc1_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvc1_grctx_pack_tpc,
- .icmd = nvc1_grctx_pack_icmd,
- .mthd = nvc1_grctx_pack_mthd,
- .bundle = nvc0_grctx_generate_bundle,
+ .main = gf100_grctx_generate_main,
+ .unkn = gf108_grctx_generate_unkn,
+ .hub = gf108_grctx_pack_hub,
+ .gpc = gf108_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gf108_grctx_pack_tpc,
+ .icmd = gf108_grctx_pack_icmd,
+ .mthd = gf108_grctx_pack_mthd,
+ .bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
- .pagepool = nvc0_grctx_generate_pagepool,
+ .pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvc1_grctx_generate_attrib,
+ .attrib = gf108_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x324,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c
similarity index 87%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c
index 4876a9375803..b3acd931b978 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "ctxnvc0.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvc8_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gf110_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
@@ -268,20 +267,20 @@ nvc8_grctx_init_icmd_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvc8_grctx_pack_icmd[] = {
- { nvc8_grctx_init_icmd_0 },
+static const struct gf100_gr_pack
+gf110_grctx_pack_icmd[] = {
+ { gf110_grctx_init_icmd_0 },
{}
};
-const struct nvc0_gr_init
-nvc8_grctx_init_9197_0[] = {
+const struct gf100_gr_init
+gf110_grctx_init_9197_0[] = {
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{}
};
-const struct nvc0_gr_init
-nvc8_grctx_init_9297_0[] = {
+const struct gf100_gr_init
+gf110_grctx_init_9297_0[] = {
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x00036c, 2, 0x04, 0x00000000 },
{ 0x0007a4, 2, 0x04, 0x00000000 },
@@ -290,19 +289,19 @@ nvc8_grctx_init_9297_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvc8_grctx_pack_mthd[] = {
- { nvc1_grctx_init_9097_0, 0x9097 },
- { nvc8_grctx_init_9197_0, 0x9197 },
- { nvc8_grctx_init_9297_0, 0x9297 },
- { nvc0_grctx_init_902d_0, 0x902d },
- { nvc0_grctx_init_9039_0, 0x9039 },
- { nvc0_grctx_init_90c0_0, 0x90c0 },
+static const struct gf100_gr_pack
+gf110_grctx_pack_mthd[] = {
+ { gf108_grctx_init_9097_0, 0x9097 },
+ { gf110_grctx_init_9197_0, 0x9197 },
+ { gf110_grctx_init_9297_0, 0x9297 },
+ { gf100_grctx_init_902d_0, 0x902d },
+ { gf100_grctx_init_9039_0, 0x9039 },
+ { gf100_grctx_init_90c0_0, 0x90c0 },
{}
};
-static const struct nvc0_gr_init
-nvc8_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gf110_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
@@ -314,16 +313,16 @@ nvc8_grctx_init_setup_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvc8_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvc0_grctx_init_prop_0 },
- { nvc0_grctx_init_gpc_unk_1 },
- { nvc8_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvc0_grctx_init_crstr_0 },
- { nvc0_grctx_init_gpm_0 },
- { nvc0_grctx_init_gcc_0 },
+static const struct gf100_gr_pack
+gf110_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf100_grctx_init_prop_0 },
+ { gf100_grctx_init_gpc_unk_1 },
+ { gf110_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf100_grctx_init_crstr_0 },
+ { gf100_grctx_init_gpm_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
@@ -331,30 +330,30 @@ nvc8_grctx_pack_gpc[] = {
* PGRAPH context implementation
******************************************************************************/
-struct nouveau_oclass *
-nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gf110_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc8),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nvc0_grctx_generate_main,
- .unkn = nvc0_grctx_generate_unkn,
- .hub = nvc0_grctx_pack_hub,
- .gpc = nvc8_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvc0_grctx_pack_tpc,
- .icmd = nvc8_grctx_pack_icmd,
- .mthd = nvc8_grctx_pack_mthd,
- .bundle = nvc0_grctx_generate_bundle,
+ .main = gf100_grctx_generate_main,
+ .unkn = gf100_grctx_generate_unkn,
+ .hub = gf100_grctx_pack_hub,
+ .gpc = gf110_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gf100_grctx_pack_tpc,
+ .icmd = gf110_grctx_pack_icmd,
+ .mthd = gf110_grctx_pack_mthd,
+ .bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
- .pagepool = nvc0_grctx_generate_pagepool,
+ .pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvc0_grctx_generate_attrib,
+ .attrib = gf100_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
similarity index 63%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
index b53896c511d9..9bbe2c97552e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
@@ -21,15 +21,17 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "ctxgf100.h"
-#include "ctxnvc0.h"
+#include <subdev/fb.h>
+#include <subdev/mc.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvd7_grctx_init_ds_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180324 },
{ 0x405834, 1, 0x04, 0x08000000 },
@@ -41,8 +43,8 @@ nvd7_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvd7_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -54,22 +56,22 @@ nvd7_grctx_init_pd_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvd7_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nvd9_grctx_init_fe_0 },
- { nvc0_grctx_init_pri_0 },
- { nvc0_grctx_init_memfmt_0 },
- { nvd7_grctx_init_ds_0 },
- { nvd7_grctx_init_pd_0 },
- { nvc0_grctx_init_rstr2d_0 },
- { nvc0_grctx_init_scc_0 },
- { nvd9_grctx_init_be_0 },
+static const struct gf100_gr_pack
+gf117_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gf119_grctx_init_fe_0 },
+ { gf100_grctx_init_pri_0 },
+ { gf100_grctx_init_memfmt_0 },
+ { gf117_grctx_init_ds_0 },
+ { gf117_grctx_init_pd_0 },
+ { gf100_grctx_init_rstr2d_0 },
+ { gf100_grctx_init_scc_0 },
+ { gf119_grctx_init_be_0 },
{}
};
-static const struct nvc0_gr_init
-nvd7_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
@@ -81,29 +83,29 @@ nvd7_grctx_init_setup_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvd7_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvd9_grctx_init_prop_0 },
- { nvd9_grctx_init_gpc_unk_1 },
- { nvd7_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvd9_grctx_init_crstr_0 },
- { nvc1_grctx_init_gpm_0 },
- { nvc0_grctx_init_gcc_0 },
+static const struct gf100_gr_pack
+gf117_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf119_grctx_init_prop_0 },
+ { gf119_grctx_init_gpc_unk_1 },
+ { gf117_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf119_grctx_init_crstr_0 },
+ { gf108_grctx_init_gpm_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-const struct nvc0_gr_init
-nvd7_grctx_init_pe_0[] = {
+const struct gf100_gr_init
+gf117_grctx_init_pe_0[] = {
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
{ 0x419888, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
-nvd7_grctx_init_tex_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
@@ -116,8 +118,8 @@ nvd7_grctx_init_tex_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvd7_grctx_init_mpc_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
@@ -127,32 +129,32 @@ nvd7_grctx_init_mpc_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvd7_grctx_pack_tpc[] = {
- { nvd7_grctx_init_pe_0 },
- { nvd7_grctx_init_tex_0 },
- { nvd7_grctx_init_mpc_0 },
- { nvc4_grctx_init_l1c_0 },
- { nvd9_grctx_init_sm_0 },
+static const struct gf100_gr_pack
+gf117_grctx_pack_tpc[] = {
+ { gf117_grctx_init_pe_0 },
+ { gf117_grctx_init_tex_0 },
+ { gf117_grctx_init_mpc_0 },
+ { gf104_grctx_init_l1c_0 },
+ { gf119_grctx_init_sm_0 },
{}
};
-static const struct nvc0_gr_init
-nvd7_grctx_init_pes_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_pes_0[] = {
{ 0x41be24, 1, 0x04, 0x00000002 },
{}
};
-static const struct nvc0_gr_init
-nvd7_grctx_init_cbm_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x12180000 },
{ 0x41bec4, 1, 0x04, 0x00003fff },
{ 0x41bee4, 1, 0x04, 0x03240218 },
{}
};
-const struct nvc0_gr_init
-nvd7_grctx_init_wwdx_0[] = {
+const struct gf100_gr_init
+gf117_grctx_init_wwdx_0[] = {
{ 0x41bf00, 1, 0x04, 0x0a418820 },
{ 0x41bf04, 1, 0x04, 0x062080e6 },
{ 0x41bf08, 1, 0x04, 0x020398a4 },
@@ -165,11 +167,11 @@ nvd7_grctx_init_wwdx_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvd7_grctx_pack_ppc[] = {
- { nvd7_grctx_init_pes_0 },
- { nvd7_grctx_init_cbm_0 },
- { nvd7_grctx_init_wwdx_0 },
+static const struct gf100_gr_pack
+gf117_grctx_pack_ppc[] = {
+ { gf117_grctx_init_pes_0 },
+ { gf117_grctx_init_cbm_0 },
+ { gf117_grctx_init_wwdx_0 },
{}
};
@@ -178,10 +180,10 @@ nvd7_grctx_pack_ppc[] = {
******************************************************************************/
void
-nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
+gf117_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct nvc0_gr_priv *priv = info->priv;
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
+ struct gf100_gr_priv *priv = info->priv;
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
const u32 alpha = impl->alpha_nr;
const u32 beta = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
@@ -215,18 +217,18 @@ nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
}
void
-nvd7_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
+gf117_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
{
- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
int i;
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
- nvc0_gr_mmio(priv, oclass->hub);
- nvc0_gr_mmio(priv, oclass->gpc);
- nvc0_gr_mmio(priv, oclass->zcull);
- nvc0_gr_mmio(priv, oclass->tpc);
- nvc0_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(priv, oclass->hub);
+ gf100_gr_mmio(priv, oclass->gpc);
+ gf100_gr_mmio(priv, oclass->zcull);
+ gf100_gr_mmio(priv, oclass->tpc);
+ gf100_gr_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
@@ -235,46 +237,46 @@ nvd7_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
oclass->attrib(info);
oclass->unkn(priv);
- nvc0_grctx_generate_tpcid(priv);
- nvc0_grctx_generate_r406028(priv);
- nvc0_grctx_generate_r4060a8(priv);
- nve4_grctx_generate_r418bb8(priv);
- nvc0_grctx_generate_r406800(priv);
+ gf100_grctx_generate_tpcid(priv);
+ gf100_grctx_generate_r406028(priv);
+ gf100_grctx_generate_r4060a8(priv);
+ gk104_grctx_generate_r418bb8(priv);
+ gf100_grctx_generate_r406800(priv);
for (i = 0; i < 8; i++)
nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
- nvc0_gr_icmd(priv, oclass->icmd);
+ gf100_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
- nvc0_gr_mthd(priv, oclass->mthd);
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
+ gf100_gr_mthd(priv, oclass->mthd);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
}
-struct nouveau_oclass *
-nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gf117_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xd7),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nvd7_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
- .hub = nvd7_grctx_pack_hub,
- .gpc = nvd7_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvd7_grctx_pack_tpc,
- .ppc = nvd7_grctx_pack_ppc,
- .icmd = nvd9_grctx_pack_icmd,
- .mthd = nvd9_grctx_pack_mthd,
- .bundle = nvc0_grctx_generate_bundle,
+ .main = gf117_grctx_generate_main,
+ .unkn = gk104_grctx_generate_unkn,
+ .hub = gf117_grctx_pack_hub,
+ .gpc = gf117_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gf117_grctx_pack_tpc,
+ .ppc = gf117_grctx_pack_ppc,
+ .icmd = gf119_grctx_pack_icmd,
+ .mthd = gf119_grctx_pack_mthd,
+ .bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
- .pagepool = nvc0_grctx_generate_pagepool,
+ .pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvd7_grctx_generate_attrib,
+ .attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c
similarity index 84%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c
index adc69e247bf2..8d8761443809 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "ctxnvc0.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvd9_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
@@ -270,14 +269,14 @@ nvd9_grctx_init_icmd_0[] = {
{}
};
-const struct nvc0_gr_pack
-nvd9_grctx_pack_icmd[] = {
- { nvd9_grctx_init_icmd_0 },
+const struct gf100_gr_pack
+gf119_grctx_pack_icmd[] = {
+ { gf119_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_gr_init
-nvd9_grctx_init_90c0_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_90c0_0[] = {
{ 0x002700, 8, 0x20, 0x00000000 },
{ 0x002704, 8, 0x20, 0x00000000 },
{ 0x002708, 8, 0x20, 0x00000000 },
@@ -299,19 +298,19 @@ nvd9_grctx_init_90c0_0[] = {
{}
};
-const struct nvc0_gr_pack
-nvd9_grctx_pack_mthd[] = {
- { nvc1_grctx_init_9097_0, 0x9097 },
- { nvc8_grctx_init_9197_0, 0x9197 },
- { nvc8_grctx_init_9297_0, 0x9297 },
- { nvc0_grctx_init_902d_0, 0x902d },
- { nvc0_grctx_init_9039_0, 0x9039 },
- { nvd9_grctx_init_90c0_0, 0x90c0 },
+const struct gf100_gr_pack
+gf119_grctx_pack_mthd[] = {
+ { gf108_grctx_init_9097_0, 0x9097 },
+ { gf110_grctx_init_9197_0, 0x9197 },
+ { gf110_grctx_init_9297_0, 0x9297 },
+ { gf100_grctx_init_902d_0, 0x902d },
+ { gf100_grctx_init_9039_0, 0x9039 },
+ { gf119_grctx_init_90c0_0, 0x90c0 },
{}
};
-const struct nvc0_gr_init
-nvd9_grctx_init_fe_0[] = {
+const struct gf100_gr_init
+gf119_grctx_init_fe_0[] = {
{ 0x404004, 10, 0x04, 0x00000000 },
{ 0x404044, 1, 0x04, 0x00000000 },
{ 0x404094, 13, 0x04, 0x00000000 },
@@ -331,8 +330,8 @@ nvd9_grctx_init_fe_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvd9_grctx_init_ds_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180218 },
{ 0x405834, 1, 0x04, 0x08000000 },
@@ -344,8 +343,8 @@ nvd9_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvd9_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -356,8 +355,8 @@ nvd9_grctx_init_pd_0[] = {
{}
};
-const struct nvc0_gr_init
-nvd9_grctx_init_be_0[] = {
+const struct gf100_gr_init
+gf119_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1043e005 },
@@ -368,22 +367,22 @@ nvd9_grctx_init_be_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvd9_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nvd9_grctx_init_fe_0 },
- { nvc0_grctx_init_pri_0 },
- { nvc0_grctx_init_memfmt_0 },
- { nvd9_grctx_init_ds_0 },
- { nvd9_grctx_init_pd_0 },
- { nvc0_grctx_init_rstr2d_0 },
- { nvc0_grctx_init_scc_0 },
- { nvd9_grctx_init_be_0 },
+static const struct gf100_gr_pack
+gf119_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gf119_grctx_init_fe_0 },
+ { gf100_grctx_init_pri_0 },
+ { gf100_grctx_init_memfmt_0 },
+ { gf119_grctx_init_ds_0 },
+ { gf119_grctx_init_pd_0 },
+ { gf100_grctx_init_rstr2d_0 },
+ { gf100_grctx_init_scc_0 },
+ { gf119_grctx_init_be_0 },
{}
};
-const struct nvc0_gr_init
-nvd9_grctx_init_prop_0[] = {
+const struct gf100_gr_init
+gf119_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38004e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
{ 0x41840c, 1, 0x04, 0x00001008 },
@@ -395,8 +394,8 @@ nvd9_grctx_init_prop_0[] = {
{}
};
-const struct nvc0_gr_init
-nvd9_grctx_init_gpc_unk_1[] = {
+const struct gf100_gr_init
+gf119_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000001f },
{ 0x418684, 1, 0x04, 0x0000000f },
{ 0x418700, 1, 0x04, 0x00000002 },
@@ -405,8 +404,8 @@ nvd9_grctx_init_gpc_unk_1[] = {
{}
};
-static const struct nvc0_gr_init
-nvd9_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
@@ -418,8 +417,8 @@ nvd9_grctx_init_setup_0[] = {
{}
};
-const struct nvc0_gr_init
-nvd9_grctx_init_crstr_0[] = {
+const struct gf100_gr_init
+gf119_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x00000006 },
{ 0x418b08, 1, 0x04, 0x0a418820 },
{ 0x418b0c, 1, 0x04, 0x062080e6 },
@@ -431,21 +430,21 @@ nvd9_grctx_init_crstr_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvd9_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvd9_grctx_init_prop_0 },
- { nvd9_grctx_init_gpc_unk_1 },
- { nvd9_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvd9_grctx_init_crstr_0 },
- { nvc1_grctx_init_gpm_0 },
- { nvc0_grctx_init_gcc_0 },
+static const struct gf100_gr_pack
+gf119_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf119_grctx_init_prop_0 },
+ { gf119_grctx_init_gpc_unk_1 },
+ { gf119_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf119_grctx_init_crstr_0 },
+ { gf108_grctx_init_gpm_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-static const struct nvc0_gr_init
-nvd9_grctx_init_tex_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
@@ -458,8 +457,8 @@ nvd9_grctx_init_tex_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvd9_grctx_init_mpc_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
@@ -469,8 +468,8 @@ nvd9_grctx_init_mpc_0[] = {
{}
};
-const struct nvc0_gr_init
-nvd9_grctx_init_sm_0[] = {
+const struct gf100_gr_init
+gf119_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
@@ -483,15 +482,15 @@ nvd9_grctx_init_sm_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvd9_grctx_pack_tpc[] = {
- { nvc1_grctx_init_pe_0 },
- { nvd9_grctx_init_tex_0 },
- { nvc1_grctx_init_wwdx_0 },
- { nvd9_grctx_init_mpc_0 },
- { nvc4_grctx_init_l1c_0 },
- { nvc1_grctx_init_tpccs_0 },
- { nvd9_grctx_init_sm_0 },
+static const struct gf100_gr_pack
+gf119_grctx_pack_tpc[] = {
+ { gf108_grctx_init_pe_0 },
+ { gf119_grctx_init_tex_0 },
+ { gf108_grctx_init_wwdx_0 },
+ { gf119_grctx_init_mpc_0 },
+ { gf104_grctx_init_l1c_0 },
+ { gf108_grctx_init_tpccs_0 },
+ { gf119_grctx_init_sm_0 },
{}
};
@@ -499,30 +498,30 @@ nvd9_grctx_pack_tpc[] = {
* PGRAPH context implementation
******************************************************************************/
-struct nouveau_oclass *
-nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gf119_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xd9),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nvc0_grctx_generate_main,
- .unkn = nvc1_grctx_generate_unkn,
- .hub = nvd9_grctx_pack_hub,
- .gpc = nvd9_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvd9_grctx_pack_tpc,
- .icmd = nvd9_grctx_pack_icmd,
- .mthd = nvd9_grctx_pack_mthd,
- .bundle = nvc0_grctx_generate_bundle,
+ .main = gf100_grctx_generate_main,
+ .unkn = gf108_grctx_generate_unkn,
+ .hub = gf119_grctx_pack_hub,
+ .gpc = gf119_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gf119_grctx_pack_tpc,
+ .icmd = gf119_grctx_pack_icmd,
+ .mthd = gf119_grctx_pack_mthd,
+ .bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
- .pagepool = nvc0_grctx_generate_pagepool,
+ .pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvc1_grctx_generate_attrib,
+ .attrib = gf108_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x324,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
similarity index 87%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
index d78c7e7bbda0..b52300d8861a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
@@ -21,15 +21,17 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "ctxgf100.h"
-#include "ctxnvc0.h"
+#include <subdev/fb.h>
+#include <subdev/mc.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nve4_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
@@ -272,14 +274,14 @@ nve4_grctx_init_icmd_0[] = {
{}
};
-const struct nvc0_gr_pack
-nve4_grctx_pack_icmd[] = {
- { nve4_grctx_init_icmd_0 },
+const struct gf100_gr_pack
+gk104_grctx_pack_icmd[] = {
+ { gk104_grctx_init_icmd_0 },
{}
};
-const struct nvc0_gr_init
-nve4_grctx_init_a097_0[] = {
+const struct gf100_gr_init
+gk104_grctx_init_a097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
@@ -578,15 +580,15 @@ nve4_grctx_init_a097_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nve4_grctx_pack_mthd[] = {
- { nve4_grctx_init_a097_0, 0xa097 },
- { nvc0_grctx_init_902d_0, 0x902d },
+static const struct gf100_gr_pack
+gk104_grctx_pack_mthd[] = {
+ { gk104_grctx_init_a097_0, 0xa097 },
+ { gf100_grctx_init_902d_0, 0x902d },
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_fe_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_fe_0[] = {
{ 0x404010, 5, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
{ 0x404028, 1, 0x04, 0x00000000 },
@@ -606,8 +608,8 @@ nve4_grctx_init_fe_0[] = {
{}
};
-const struct nvc0_gr_init
-nve4_grctx_init_memfmt_0[] = {
+const struct gf100_gr_init
+gk104_grctx_init_memfmt_0[] = {
{ 0x404604, 1, 0x04, 0x00000014 },
{ 0x404608, 1, 0x04, 0x00000000 },
{ 0x40460c, 1, 0x04, 0x00003fff },
@@ -632,8 +634,8 @@ nve4_grctx_init_memfmt_0[] = {
{}
};
-const struct nvc0_gr_init
-nve4_grctx_init_ds_0[] = {
+const struct gf100_gr_init
+gk104_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180648 },
{ 0x405834, 1, 0x04, 0x08000000 },
@@ -645,15 +647,15 @@ nve4_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_cwd_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_cwd_0[] = {
{ 0x405b00, 1, 0x04, 0x00000000 },
{ 0x405b10, 1, 0x04, 0x00001000 },
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x004103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -667,14 +669,14 @@ nve4_grctx_init_pd_0[] = {
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_sked_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_sked_0[] = {
{ 0x407040, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nve4_grctx_init_scc_0[] = {
+const struct gf100_gr_init
+gk104_grctx_init_scc_0[] = {
{ 0x408000, 2, 0x04, 0x00000000 },
{ 0x408008, 1, 0x04, 0x00000030 },
{ 0x40800c, 2, 0x04, 0x00000000 },
@@ -684,8 +686,8 @@ nve4_grctx_init_scc_0[] = {
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_be_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1043e005 },
@@ -697,24 +699,24 @@ nve4_grctx_init_be_0[] = {
{}
};
-const struct nvc0_gr_pack
-nve4_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nve4_grctx_init_fe_0 },
- { nvc0_grctx_init_pri_0 },
- { nve4_grctx_init_memfmt_0 },
- { nve4_grctx_init_ds_0 },
- { nve4_grctx_init_cwd_0 },
- { nve4_grctx_init_pd_0 },
- { nve4_grctx_init_sked_0 },
- { nvc0_grctx_init_rstr2d_0 },
- { nve4_grctx_init_scc_0 },
- { nve4_grctx_init_be_0 },
+const struct gf100_gr_pack
+gk104_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gk104_grctx_init_fe_0 },
+ { gf100_grctx_init_pri_0 },
+ { gk104_grctx_init_memfmt_0 },
+ { gk104_grctx_init_ds_0 },
+ { gk104_grctx_init_cwd_0 },
+ { gk104_grctx_init_pd_0 },
+ { gk104_grctx_init_sked_0 },
+ { gf100_grctx_init_rstr2d_0 },
+ { gk104_grctx_init_scc_0 },
+ { gk104_grctx_init_be_0 },
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00000044 },
@@ -726,8 +728,8 @@ nve4_grctx_init_setup_0[] = {
{}
};
-const struct nvc0_gr_init
-nve4_grctx_init_gpm_0[] = {
+const struct gf100_gr_init
+gk104_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c40, 1, 0x04, 0xffffffff },
@@ -737,21 +739,21 @@ nve4_grctx_init_gpm_0[] = {
{}
};
-const struct nvc0_gr_pack
-nve4_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvd9_grctx_init_prop_0 },
- { nvd9_grctx_init_gpc_unk_1 },
- { nve4_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvd9_grctx_init_crstr_0 },
- { nve4_grctx_init_gpm_0 },
- { nvc0_grctx_init_gcc_0 },
+const struct gf100_gr_pack
+gk104_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf119_grctx_init_prop_0 },
+ { gf119_grctx_init_gpc_unk_1 },
+ { gk104_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf119_grctx_init_crstr_0 },
+ { gk104_grctx_init_gpm_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_tex_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000000f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000021 },
@@ -765,8 +767,8 @@ nve4_grctx_init_tex_0[] = {
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_mpc_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x80000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
@@ -776,15 +778,15 @@ nve4_grctx_init_mpc_0[] = {
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_l1c_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_l1c_0[] = {
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00003203 },
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_sm_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000402 },
{ 0x419e44, 1, 0x04, 0x0013eff2 },
@@ -802,35 +804,35 @@ nve4_grctx_init_sm_0[] = {
{}
};
-const struct nvc0_gr_pack
-nve4_grctx_pack_tpc[] = {
- { nvd7_grctx_init_pe_0 },
- { nve4_grctx_init_tex_0 },
- { nve4_grctx_init_mpc_0 },
- { nve4_grctx_init_l1c_0 },
- { nve4_grctx_init_sm_0 },
+const struct gf100_gr_pack
+gk104_grctx_pack_tpc[] = {
+ { gf117_grctx_init_pe_0 },
+ { gk104_grctx_init_tex_0 },
+ { gk104_grctx_init_mpc_0 },
+ { gk104_grctx_init_l1c_0 },
+ { gk104_grctx_init_sm_0 },
{}
};
-const struct nvc0_gr_init
-nve4_grctx_init_pes_0[] = {
+const struct gf100_gr_init
+gk104_grctx_init_pes_0[] = {
{ 0x41be24, 1, 0x04, 0x00000006 },
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_cbm_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x12180000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
{ 0x41bee4, 1, 0x04, 0x06480430 },
{}
};
-const struct nvc0_gr_pack
-nve4_grctx_pack_ppc[] = {
- { nve4_grctx_init_pes_0 },
- { nve4_grctx_init_cbm_0 },
- { nvd7_grctx_init_wwdx_0 },
+const struct gf100_gr_pack
+gk104_grctx_pack_ppc[] = {
+ { gk104_grctx_init_pes_0 },
+ { gk104_grctx_init_cbm_0 },
+ { gf117_grctx_init_wwdx_0 },
{}
};
@@ -839,9 +841,9 @@ nve4_grctx_pack_ppc[] = {
******************************************************************************/
void
-nve4_grctx_generate_bundle(struct nvc0_grctx *info)
+gk104_grctx_generate_bundle(struct gf100_grctx *info)
{
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
impl->bundle_size / 0x20);
const u32 token_limit = impl->bundle_token_limit;
@@ -856,9 +858,9 @@ nve4_grctx_generate_bundle(struct nvc0_grctx *info)
}
void
-nve4_grctx_generate_pagepool(struct nvc0_grctx *info)
+gk104_grctx_generate_pagepool(struct gf100_grctx *info)
{
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
@@ -870,7 +872,7 @@ nve4_grctx_generate_pagepool(struct nvc0_grctx *info)
}
void
-nve4_grctx_generate_unkn(struct nvc0_gr_priv *priv)
+gk104_grctx_generate_unkn(struct gf100_gr_priv *priv)
{
nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
@@ -881,7 +883,7 @@ nve4_grctx_generate_unkn(struct nvc0_gr_priv *priv)
}
void
-nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *priv)
+gk104_grctx_generate_r418bb8(struct gf100_gr_priv *priv)
{
u32 data[6] = {}, data2[2] = {};
u8 tpcnr[GPC_MAX];
@@ -939,18 +941,18 @@ nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *priv)
}
void
-nve4_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
+gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
{
- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
int i;
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
- nvc0_gr_mmio(priv, oclass->hub);
- nvc0_gr_mmio(priv, oclass->gpc);
- nvc0_gr_mmio(priv, oclass->zcull);
- nvc0_gr_mmio(priv, oclass->tpc);
- nvc0_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(priv, oclass->hub);
+ gf100_gr_mmio(priv, oclass->gpc);
+ gf100_gr_mmio(priv, oclass->zcull);
+ gf100_gr_mmio(priv, oclass->tpc);
+ gf100_gr_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
@@ -959,10 +961,10 @@ nve4_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
oclass->attrib(info);
oclass->unkn(priv);
- nvc0_grctx_generate_tpcid(priv);
- nvc0_grctx_generate_r406028(priv);
- nve4_grctx_generate_r418bb8(priv);
- nvc0_grctx_generate_r406800(priv);
+ gf100_grctx_generate_tpcid(priv);
+ gf100_grctx_generate_r406028(priv);
+ gk104_grctx_generate_r418bb8(priv);
+ gf100_grctx_generate_r406800(priv);
for (i = 0; i < 8; i++)
nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
@@ -977,42 +979,42 @@ nve4_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
}
nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
- nvc0_gr_icmd(priv, oclass->icmd);
+ gf100_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
- nvc0_gr_mthd(priv, oclass->mthd);
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
+ gf100_gr_mthd(priv, oclass->mthd);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
nv_mask(priv, 0x418800, 0x00200000, 0x00200000);
nv_mask(priv, 0x41be10, 0x00800000, 0x00800000);
}
-struct nouveau_oclass *
-nve4_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gk104_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xe4),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nve4_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
- .hub = nve4_grctx_pack_hub,
- .gpc = nve4_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nve4_grctx_pack_tpc,
- .ppc = nve4_grctx_pack_ppc,
- .icmd = nve4_grctx_pack_icmd,
- .mthd = nve4_grctx_pack_mthd,
- .bundle = nve4_grctx_generate_bundle,
+ .main = gk104_grctx_generate_main,
+ .unkn = gk104_grctx_generate_unkn,
+ .hub = gk104_grctx_pack_hub,
+ .gpc = gk104_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gk104_grctx_pack_tpc,
+ .ppc = gk104_grctx_pack_ppc,
+ .icmd = gk104_grctx_pack_icmd,
+ .mthd = gk104_grctx_pack_mthd,
+ .bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x600,
- .pagepool = nve4_grctx_generate_pagepool,
+ .pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvd7_grctx_generate_attrib,
+ .attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c
similarity index 90%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c
index f7444690b4d4..b3f58be04e9c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "ctxnvc0.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvf0_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
@@ -279,14 +278,14 @@ nvf0_grctx_init_icmd_0[] = {
{}
};
-const struct nvc0_gr_pack
-nvf0_grctx_pack_icmd[] = {
- { nvf0_grctx_init_icmd_0 },
+const struct gf100_gr_pack
+gk110_grctx_pack_icmd[] = {
+ { gk110_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_a197_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_a197_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
@@ -587,15 +586,15 @@ nvf0_grctx_init_a197_0[] = {
{}
};
-const struct nvc0_gr_pack
-nvf0_grctx_pack_mthd[] = {
- { nvf0_grctx_init_a197_0, 0xa197 },
- { nvc0_grctx_init_902d_0, 0x902d },
+const struct gf100_gr_pack
+gk110_grctx_pack_mthd[] = {
+ { gk110_grctx_init_a197_0, 0xa197 },
+ { gf100_grctx_init_902d_0, 0x902d },
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_fe_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
{ 0x404028, 8, 0x04, 0x00000000 },
@@ -620,8 +619,8 @@ nvf0_grctx_init_fe_0[] = {
{}
};
-const struct nvc0_gr_init
-nvf0_grctx_init_pri_0[] = {
+const struct gf100_gr_init
+gk110_grctx_init_pri_0[] = {
{ 0x404404, 12, 0x04, 0x00000000 },
{ 0x404438, 1, 0x04, 0x00000000 },
{ 0x404460, 2, 0x04, 0x00000000 },
@@ -632,16 +631,16 @@ nvf0_grctx_init_pri_0[] = {
{}
};
-const struct nvc0_gr_init
-nvf0_grctx_init_cwd_0[] = {
+const struct gf100_gr_init
+gk110_grctx_init_cwd_0[] = {
{ 0x405b00, 1, 0x04, 0x00000000 },
{ 0x405b10, 1, 0x04, 0x00001000 },
{ 0x405b20, 1, 0x04, 0x04000000 },
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x034103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -655,8 +654,8 @@ nvf0_grctx_init_pd_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_be_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x12802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
@@ -668,23 +667,23 @@ nvf0_grctx_init_be_0[] = {
{}
};
-const struct nvc0_gr_pack
-nvf0_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nvf0_grctx_init_fe_0 },
- { nvf0_grctx_init_pri_0 },
- { nve4_grctx_init_memfmt_0 },
- { nve4_grctx_init_ds_0 },
- { nvf0_grctx_init_cwd_0 },
- { nvf0_grctx_init_pd_0 },
- { nvc0_grctx_init_rstr2d_0 },
- { nve4_grctx_init_scc_0 },
- { nvf0_grctx_init_be_0 },
+const struct gf100_gr_pack
+gk110_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gk110_grctx_init_fe_0 },
+ { gk110_grctx_init_pri_0 },
+ { gk104_grctx_init_memfmt_0 },
+ { gk104_grctx_init_ds_0 },
+ { gk110_grctx_init_cwd_0 },
+ { gk110_grctx_init_pd_0 },
+ { gf100_grctx_init_rstr2d_0 },
+ { gk104_grctx_init_scc_0 },
+ { gk110_grctx_init_be_0 },
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 1, 0x04, 0x00000000 },
{ 0x41880c, 1, 0x04, 0x00000030 },
@@ -698,28 +697,28 @@ nvf0_grctx_init_setup_0[] = {
{}
};
-const struct nvc0_gr_init
-nvf0_grctx_init_gpc_unk_2[] = {
+const struct gf100_gr_init
+gk110_grctx_init_gpc_unk_2[] = {
{ 0x418d24, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_pack
-nvf0_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvd9_grctx_init_prop_0 },
- { nvd9_grctx_init_gpc_unk_1 },
- { nvf0_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvd9_grctx_init_crstr_0 },
- { nve4_grctx_init_gpm_0 },
- { nvf0_grctx_init_gpc_unk_2 },
- { nvc0_grctx_init_gcc_0 },
+const struct gf100_gr_pack
+gk110_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf119_grctx_init_prop_0 },
+ { gf119_grctx_init_gpc_unk_1 },
+ { gk110_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf119_grctx_init_crstr_0 },
+ { gk104_grctx_init_gpm_0 },
+ { gk110_grctx_init_gpc_unk_2 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-const struct nvc0_gr_init
-nvf0_grctx_init_tex_0[] = {
+const struct gf100_gr_init
+gk110_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000000f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000021 },
@@ -733,8 +732,8 @@ nvf0_grctx_init_tex_0[] = {
{}
};
-const struct nvc0_gr_init
-nvf0_grctx_init_mpc_0[] = {
+const struct gf100_gr_init
+gk110_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000001a },
{ 0x419c04, 1, 0x04, 0x80000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
@@ -744,15 +743,15 @@ nvf0_grctx_init_mpc_0[] = {
{}
};
-const struct nvc0_gr_init
-nvf0_grctx_init_l1c_0[] = {
+const struct gf100_gr_init
+gk110_grctx_init_l1c_0[] = {
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000203 },
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_sm_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
{ 0x419e0c, 1, 0x04, 0x00000000 },
@@ -779,29 +778,29 @@ nvf0_grctx_init_sm_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvf0_grctx_pack_tpc[] = {
- { nvd7_grctx_init_pe_0 },
- { nvf0_grctx_init_tex_0 },
- { nvf0_grctx_init_mpc_0 },
- { nvf0_grctx_init_l1c_0 },
- { nvf0_grctx_init_sm_0 },
+static const struct gf100_gr_pack
+gk110_grctx_pack_tpc[] = {
+ { gf117_grctx_init_pe_0 },
+ { gk110_grctx_init_tex_0 },
+ { gk110_grctx_init_mpc_0 },
+ { gk110_grctx_init_l1c_0 },
+ { gk110_grctx_init_sm_0 },
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_cbm_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x10000000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
{ 0x41bee4, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_pack
-nvf0_grctx_pack_ppc[] = {
- { nve4_grctx_init_pes_0 },
- { nvf0_grctx_init_cbm_0 },
- { nvd7_grctx_init_wwdx_0 },
+const struct gf100_gr_pack
+gk110_grctx_pack_ppc[] = {
+ { gk104_grctx_init_pes_0 },
+ { gk110_grctx_init_cbm_0 },
+ { gf117_grctx_init_wwdx_0 },
{}
};
@@ -809,33 +808,33 @@ nvf0_grctx_pack_ppc[] = {
* PGRAPH context implementation
******************************************************************************/
-struct nouveau_oclass *
-nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gk110_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xf0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nve4_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
- .hub = nvf0_grctx_pack_hub,
- .gpc = nvf0_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvf0_grctx_pack_tpc,
- .ppc = nvf0_grctx_pack_ppc,
- .icmd = nvf0_grctx_pack_icmd,
- .mthd = nvf0_grctx_pack_mthd,
- .bundle = nve4_grctx_generate_bundle,
+ .main = gk104_grctx_generate_main,
+ .unkn = gk104_grctx_generate_unkn,
+ .hub = gk110_grctx_pack_hub,
+ .gpc = gk110_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gk110_grctx_pack_tpc,
+ .ppc = gk110_grctx_pack_ppc,
+ .icmd = gk110_grctx_pack_icmd,
+ .mthd = gk110_grctx_pack_mthd,
+ .bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x7c0,
- .pagepool = nve4_grctx_generate_pagepool,
+ .pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvd7_grctx_generate_attrib,
+ .attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c
index 05a69ca48f25..b11c26794fde 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c
@@ -21,14 +21,13 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "ctxnvc0.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gk110b_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
@@ -56,12 +55,12 @@ gk110b_grctx_init_sm_0[] = {
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gk110b_grctx_pack_tpc[] = {
- { nvd7_grctx_init_pe_0 },
- { nvf0_grctx_init_tex_0 },
- { nvf0_grctx_init_mpc_0 },
- { nvf0_grctx_init_l1c_0 },
+ { gf117_grctx_init_pe_0 },
+ { gk110_grctx_init_tex_0 },
+ { gk110_grctx_init_mpc_0 },
+ { gk110_grctx_init_l1c_0 },
{ gk110b_grctx_init_sm_0 },
{}
};
@@ -70,33 +69,33 @@ gk110b_grctx_pack_tpc[] = {
* PGRAPH context implementation
******************************************************************************/
-struct nouveau_oclass *
-gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gk110b_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xf1),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nve4_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
- .hub = nvf0_grctx_pack_hub,
- .gpc = nvf0_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
+ .main = gk104_grctx_generate_main,
+ .unkn = gk104_grctx_generate_unkn,
+ .hub = gk110_grctx_pack_hub,
+ .gpc = gk110_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
.tpc = gk110b_grctx_pack_tpc,
- .ppc = nvf0_grctx_pack_ppc,
- .icmd = nvf0_grctx_pack_icmd,
- .mthd = nvf0_grctx_pack_mthd,
- .bundle = nve4_grctx_generate_bundle,
+ .ppc = gk110_grctx_pack_ppc,
+ .icmd = gk110_grctx_pack_icmd,
+ .mthd = gk110_grctx_pack_mthd,
+ .bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x600,
- .pagepool = nve4_grctx_generate_pagepool,
+ .pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvd7_grctx_generate_attrib,
+ .attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c
similarity index 85%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c
index f56d77e307c1..6e8ce9fc311a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "ctxnvc0.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nv108_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
@@ -278,14 +277,14 @@ nv108_grctx_init_icmd_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nv108_grctx_pack_icmd[] = {
- { nv108_grctx_init_icmd_0 },
+static const struct gf100_gr_pack
+gk208_grctx_pack_icmd[] = {
+ { gk208_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_fe_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
{ 0x404028, 8, 0x04, 0x00000000 },
@@ -311,8 +310,8 @@ nv108_grctx_init_fe_0[] = {
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_ds_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180648 },
{ 0x405834, 1, 0x04, 0x08000000 },
@@ -325,8 +324,8 @@ nv108_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x034103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -340,8 +339,8 @@ nv108_grctx_init_pd_0[] = {
{}
};
-const struct nvc0_gr_init
-nv108_grctx_init_rstr2d_0[] = {
+const struct gf100_gr_init
+gk208_grctx_init_rstr2d_0[] = {
{ 0x407804, 1, 0x04, 0x00000063 },
{ 0x40780c, 1, 0x04, 0x0a418820 },
{ 0x407810, 1, 0x04, 0x062080e6 },
@@ -353,8 +352,8 @@ nv108_grctx_init_rstr2d_0[] = {
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_be_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x32802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
@@ -366,23 +365,23 @@ nv108_grctx_init_be_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nv108_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nv108_grctx_init_fe_0 },
- { nvf0_grctx_init_pri_0 },
- { nve4_grctx_init_memfmt_0 },
- { nv108_grctx_init_ds_0 },
- { nvf0_grctx_init_cwd_0 },
- { nv108_grctx_init_pd_0 },
- { nv108_grctx_init_rstr2d_0 },
- { nve4_grctx_init_scc_0 },
- { nv108_grctx_init_be_0 },
+static const struct gf100_gr_pack
+gk208_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gk208_grctx_init_fe_0 },
+ { gk110_grctx_init_pri_0 },
+ { gk104_grctx_init_memfmt_0 },
+ { gk208_grctx_init_ds_0 },
+ { gk110_grctx_init_cwd_0 },
+ { gk208_grctx_init_pd_0 },
+ { gk208_grctx_init_rstr2d_0 },
+ { gk104_grctx_init_scc_0 },
+ { gk208_grctx_init_be_0 },
{}
};
-const struct nvc0_gr_init
-nv108_grctx_init_prop_0[] = {
+const struct gf100_gr_init
+gk208_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38005e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
{ 0x41840c, 1, 0x04, 0x00001008 },
@@ -394,8 +393,8 @@ nv108_grctx_init_prop_0[] = {
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_gpc_unk_1[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000007f },
{ 0x418684, 1, 0x04, 0x0000001f },
{ 0x418700, 1, 0x04, 0x00000002 },
@@ -404,8 +403,8 @@ nv108_grctx_init_gpc_unk_1[] = {
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006863a },
{ 0x418808, 1, 0x04, 0x00000000 },
{ 0x41880c, 1, 0x04, 0x00000030 },
@@ -419,8 +418,8 @@ nv108_grctx_init_setup_0[] = {
{}
};
-const struct nvc0_gr_init
-nv108_grctx_init_crstr_0[] = {
+const struct gf100_gr_init
+gk208_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x0000001e },
{ 0x418b08, 1, 0x04, 0x0a418820 },
{ 0x418b0c, 1, 0x04, 0x062080e6 },
@@ -432,8 +431,8 @@ nv108_grctx_init_crstr_0[] = {
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_gpm_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c40, 1, 0x04, 0xffffffff },
@@ -443,22 +442,22 @@ nv108_grctx_init_gpm_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nv108_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nv108_grctx_init_prop_0 },
- { nv108_grctx_init_gpc_unk_1 },
- { nv108_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nv108_grctx_init_crstr_0 },
- { nv108_grctx_init_gpm_0 },
- { nvf0_grctx_init_gpc_unk_2 },
- { nvc0_grctx_init_gcc_0 },
+static const struct gf100_gr_pack
+gk208_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gk208_grctx_init_prop_0 },
+ { gk208_grctx_init_gpc_unk_1 },
+ { gk208_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gk208_grctx_init_crstr_0 },
+ { gk208_grctx_init_gpm_0 },
+ { gk110_grctx_init_gpc_unk_2 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_tex_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000100f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000421 },
@@ -472,8 +471,8 @@ nv108_grctx_init_tex_0[] = {
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_sm_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
{ 0x419e0c, 1, 0x04, 0x00000000 },
@@ -500,18 +499,18 @@ nv108_grctx_init_sm_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nv108_grctx_pack_tpc[] = {
- { nvd7_grctx_init_pe_0 },
- { nv108_grctx_init_tex_0 },
- { nvf0_grctx_init_mpc_0 },
- { nvf0_grctx_init_l1c_0 },
- { nv108_grctx_init_sm_0 },
+static const struct gf100_gr_pack
+gk208_grctx_pack_tpc[] = {
+ { gf117_grctx_init_pe_0 },
+ { gk208_grctx_init_tex_0 },
+ { gk110_grctx_init_mpc_0 },
+ { gk110_grctx_init_l1c_0 },
+ { gk208_grctx_init_sm_0 },
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_cbm_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x10000000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
{ 0x41bee4, 1, 0x04, 0x00000000 },
@@ -519,11 +518,11 @@ nv108_grctx_init_cbm_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nv108_grctx_pack_ppc[] = {
- { nve4_grctx_init_pes_0 },
- { nv108_grctx_init_cbm_0 },
- { nvd7_grctx_init_wwdx_0 },
+static const struct gf100_gr_pack
+gk208_grctx_pack_ppc[] = {
+ { gk104_grctx_init_pes_0 },
+ { gk208_grctx_init_cbm_0 },
+ { gf117_grctx_init_wwdx_0 },
{}
};
@@ -531,33 +530,33 @@ nv108_grctx_pack_ppc[] = {
* PGRAPH context implementation
******************************************************************************/
-struct nouveau_oclass *
-nv108_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gk208_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0x08),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nve4_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
- .hub = nv108_grctx_pack_hub,
- .gpc = nv108_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nv108_grctx_pack_tpc,
- .ppc = nv108_grctx_pack_ppc,
- .icmd = nv108_grctx_pack_icmd,
- .mthd = nvf0_grctx_pack_mthd,
- .bundle = nve4_grctx_generate_bundle,
+ .main = gk104_grctx_generate_main,
+ .unkn = gk104_grctx_generate_unkn,
+ .hub = gk208_grctx_pack_hub,
+ .gpc = gk208_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gk208_grctx_pack_tpc,
+ .ppc = gk208_grctx_pack_ppc,
+ .icmd = gk208_grctx_pack_icmd,
+ .mthd = gk110_grctx_pack_mthd,
+ .bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0xc2,
.bundle_token_limit = 0x200,
- .pagepool = nve4_grctx_generate_pagepool,
+ .pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvd7_grctx_generate_attrib,
+ .attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
index 5aae94ced9ed..2f241f6f0f0a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
@@ -19,43 +19,42 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+#include "ctxgf100.h"
-#include "ctxnvc0.h"
-
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gk20a_grctx_pack_mthd[] = {
- { nve4_grctx_init_a097_0, 0xa297 },
- { nvc0_grctx_init_902d_0, 0x902d },
+ { gk104_grctx_init_a097_0, 0xa297 },
+ { gf100_grctx_init_902d_0, 0x902d },
{}
};
-struct nouveau_oclass *
-gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gk20a_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xea),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nve4_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
- .hub = nve4_grctx_pack_hub,
- .gpc = nve4_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nve4_grctx_pack_tpc,
- .ppc = nve4_grctx_pack_ppc,
- .icmd = nve4_grctx_pack_icmd,
+ .main = gk104_grctx_generate_main,
+ .unkn = gk104_grctx_generate_unkn,
+ .hub = gk104_grctx_pack_hub,
+ .gpc = gk104_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gk104_grctx_pack_tpc,
+ .ppc = gk104_grctx_pack_ppc,
+ .icmd = gk104_grctx_pack_icmd,
.mthd = gk20a_grctx_pack_mthd,
- .bundle = nve4_grctx_generate_bundle,
+ .bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x1800,
.bundle_min_gpm_fifo_depth = 0x62,
.bundle_token_limit = 0x100,
- .pagepool = nve4_grctx_generate_pagepool,
+ .pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvd7_grctx_generate_attrib,
+ .attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x240,
.attrib_nr = 0x240,
.alpha_nr_max = 0x648 + (0x648 / 2),
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
index cf6199fe3b59..956f4dce960c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
@@ -21,14 +21,16 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "ctxgf100.h"
-#include "ctxnvc0.h"
+#include <subdev/fb.h>
+#include <subdev/mc.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
@@ -287,13 +289,13 @@ gm107_grctx_init_icmd_0[] = {
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_grctx_pack_icmd[] = {
{ gm107_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_b097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
@@ -610,14 +612,14 @@ gm107_grctx_init_b097_0[] = {
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_grctx_pack_mthd[] = {
{ gm107_grctx_init_b097_0, 0xb097 },
- { nvc0_grctx_init_902d_0, 0x902d },
+ { gf100_grctx_init_902d_0, 0x902d },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
@@ -639,7 +641,7 @@ gm107_grctx_init_fe_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8001bf },
{ 0x405830, 1, 0x04, 0x0aa01000 },
@@ -653,7 +655,7 @@ gm107_grctx_init_ds_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x07410001 },
{ 0x406028, 4, 0x04, 0x00000001 },
@@ -669,7 +671,7 @@ gm107_grctx_init_pd_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x32802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
@@ -682,28 +684,28 @@ gm107_grctx_init_be_0[] = {
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
+ { gf100_grctx_init_main_0 },
{ gm107_grctx_init_fe_0 },
- { nvf0_grctx_init_pri_0 },
- { nve4_grctx_init_memfmt_0 },
+ { gk110_grctx_init_pri_0 },
+ { gk104_grctx_init_memfmt_0 },
{ gm107_grctx_init_ds_0 },
- { nvf0_grctx_init_cwd_0 },
+ { gk110_grctx_init_cwd_0 },
{ gm107_grctx_init_pd_0 },
- { nv108_grctx_init_rstr2d_0 },
- { nve4_grctx_init_scc_0 },
+ { gk208_grctx_init_rstr2d_0 },
+ { gk104_grctx_init_scc_0 },
{ gm107_grctx_init_be_0 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_gpc_unk_0[] = {
{ 0x418380, 1, 0x04, 0x00000056 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000007f },
{ 0x418684, 1, 0x04, 0x0000001f },
@@ -714,7 +716,7 @@ gm107_grctx_init_gpc_unk_1[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006863a },
{ 0x418810, 1, 0x04, 0x00000000 },
@@ -727,7 +729,7 @@ gm107_grctx_init_setup_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_gpc_unk_2[] = {
{ 0x418d24, 1, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x90000000 },
@@ -741,21 +743,21 @@ gm107_grctx_init_gpc_unk_2[] = {
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_grctx_pack_gpc[] = {
{ gm107_grctx_init_gpc_unk_0 },
- { nv108_grctx_init_prop_0 },
+ { gk208_grctx_init_prop_0 },
{ gm107_grctx_init_gpc_unk_1 },
{ gm107_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nv108_grctx_init_crstr_0 },
- { nve4_grctx_init_gpm_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gk208_grctx_init_crstr_0 },
+ { gk104_grctx_init_gpm_0 },
{ gm107_grctx_init_gpc_unk_2 },
- { nvc0_grctx_init_gcc_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000300f0 },
{ 0x419a04, 1, 0x04, 0x00000005 },
@@ -771,7 +773,7 @@ gm107_grctx_init_tex_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000001a },
{ 0x419c04, 1, 0x04, 0x80000006 },
@@ -785,13 +787,13 @@ gm107_grctx_init_mpc_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_l1c_0[] = {
{ 0x419c84, 1, 0x04, 0x00000020 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00001c02 },
@@ -812,9 +814,9 @@ gm107_grctx_init_sm_0[] = {
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_grctx_pack_tpc[] = {
- { nvd7_grctx_init_pe_0 },
+ { gf117_grctx_init_pe_0 },
{ gm107_grctx_init_tex_0 },
{ gm107_grctx_init_mpc_0 },
{ gm107_grctx_init_l1c_0 },
@@ -822,7 +824,7 @@ gm107_grctx_pack_tpc[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x00000000 },
{ 0x41bec4, 1, 0x04, 0x01050000 },
@@ -832,7 +834,7 @@ gm107_grctx_init_cbm_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_wwdx_0[] = {
{ 0x41bf00, 1, 0x04, 0x0a418820 },
{ 0x41bf04, 1, 0x04, 0x062080e6 },
@@ -846,9 +848,9 @@ gm107_grctx_init_wwdx_0[] = {
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_grctx_pack_ppc[] = {
- { nve4_grctx_init_pes_0 },
+ { gk104_grctx_init_pes_0 },
{ gm107_grctx_init_cbm_0 },
{ gm107_grctx_init_wwdx_0 },
{}
@@ -859,9 +861,9 @@ gm107_grctx_pack_ppc[] = {
******************************************************************************/
static void
-gm107_grctx_generate_bundle(struct nvc0_grctx *info)
+gm107_grctx_generate_bundle(struct gf100_grctx *info)
{
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
impl->bundle_size / 0x20);
const u32 token_limit = impl->bundle_token_limit;
@@ -876,9 +878,9 @@ gm107_grctx_generate_bundle(struct nvc0_grctx *info)
}
static void
-gm107_grctx_generate_pagepool(struct nvc0_grctx *info)
+gm107_grctx_generate_pagepool(struct gf100_grctx *info)
{
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
@@ -891,10 +893,10 @@ gm107_grctx_generate_pagepool(struct nvc0_grctx *info)
}
static void
-gm107_grctx_generate_attrib(struct nvc0_grctx *info)
+gm107_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct nvc0_gr_priv *priv = info->priv;
- const struct nvc0_grctx_oclass *impl = (void *)nvc0_grctx_impl(priv);
+ struct gf100_gr_priv *priv = info->priv;
+ const struct gf100_grctx_oclass *impl = (void *)gf100_grctx_impl(priv);
const u32 alpha = impl->alpha_nr;
const u32 attrib = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
@@ -930,7 +932,7 @@ gm107_grctx_generate_attrib(struct nvc0_grctx *info)
}
static void
-gm107_grctx_generate_tpcid(struct nvc0_gr_priv *priv)
+gm107_grctx_generate_tpcid(struct gf100_gr_priv *priv)
{
int gpc, tpc, id;
@@ -950,16 +952,16 @@ gm107_grctx_generate_tpcid(struct nvc0_gr_priv *priv)
}
static void
-gm107_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
+gm107_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
{
- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
int i;
- nvc0_gr_mmio(priv, oclass->hub);
- nvc0_gr_mmio(priv, oclass->gpc);
- nvc0_gr_mmio(priv, oclass->zcull);
- nvc0_gr_mmio(priv, oclass->tpc);
- nvc0_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(priv, oclass->hub);
+ gf100_gr_mmio(priv, oclass->gpc);
+ gf100_gr_mmio(priv, oclass->zcull);
+ gf100_gr_mmio(priv, oclass->tpc);
+ gf100_gr_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
@@ -969,9 +971,9 @@ gm107_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
oclass->unkn(priv);
gm107_grctx_generate_tpcid(priv);
- nvc0_grctx_generate_r406028(priv);
- nve4_grctx_generate_r418bb8(priv);
- nvc0_grctx_generate_r406800(priv);
+ gf100_grctx_generate_r406028(priv);
+ gk104_grctx_generate_r418bb8(priv);
+ gf100_grctx_generate_r406800(priv);
nv_wr32(priv, 0x4064d0, 0x00000001);
for (i = 1; i < 8; i++)
@@ -988,9 +990,9 @@ gm107_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
}
- nvc0_gr_icmd(priv, oclass->icmd);
+ gf100_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
- nvc0_gr_mthd(priv, oclass->mthd);
+ gf100_gr_mthd(priv, oclass->mthd);
nv_mask(priv, 0x419e00, 0x00808080, 0x00808080);
nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000);
@@ -998,22 +1000,22 @@ gm107_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
nv_mask(priv, 0x419f88, 0x80000000, 0x80000000);
}
-struct nouveau_oclass *
-gm107_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gm107_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0x08),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
.main = gm107_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
+ .unkn = gk104_grctx_generate_unkn,
.hub = gm107_grctx_pack_hub,
.gpc = gm107_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
+ .zcull = gf100_grctx_pack_zcull,
.tpc = gm107_grctx_pack_tpc,
.ppc = gm107_grctx_pack_ppc,
.icmd = gm107_grctx_pack_icmd,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c
index 9e311411f1b1..dc31462afe65 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c
@@ -22,8 +22,6 @@
* Authors: Ben Skeggs
*/
-#include <core/gpuobj.h>
-
/* NVIDIA context programs handle a number of other conditions which are
* not implemented in our versions. It's not clear why NVIDIA context
* programs have this code, nor whether it's strictly necessary for
@@ -111,15 +109,16 @@
#define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */
#define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */
+#include "ctxnv40.h"
#include "nv40.h"
-#include "ctx.h"
+#include <core/device.h>
/* TODO:
* - get vs count from 0x1540
*/
static int
-nv40_gr_vs_count(struct nouveau_device *device)
+nv40_gr_vs_count(struct nvkm_device *device)
{
switch (device->chipset) {
@@ -158,9 +157,9 @@ enum cp_label {
};
static void
-nv40_gr_construct_general(struct nouveau_grctx *ctx)
+nv40_gr_construct_general(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
cp_ctx(ctx, 0x4000a4, 1);
@@ -264,9 +263,9 @@ nv40_gr_construct_general(struct nouveau_grctx *ctx)
}
static void
-nv40_gr_construct_state3d(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
if (device->chipset == 0x40) {
@@ -369,9 +368,9 @@ nv40_gr_construct_state3d(struct nouveau_grctx *ctx)
}
static void
-nv40_gr_construct_state3d_2(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d_2(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
cp_ctx(ctx, 0x402000, 1);
@@ -533,7 +532,7 @@ nv40_gr_construct_state3d_2(struct nouveau_grctx *ctx)
}
static void
-nv40_gr_construct_state3d_3(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d_3(struct nvkm_grctx *ctx)
{
int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684;
@@ -548,10 +547,10 @@ nv40_gr_construct_state3d_3(struct nouveau_grctx *ctx)
}
static void
-nv40_gr_construct_shader(struct nouveau_grctx *ctx)
+nv40_gr_construct_shader(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
- struct nouveau_gpuobj *obj = ctx->data;
+ struct nvkm_device *device = ctx->device;
+ struct nvkm_gpuobj *obj = ctx->data;
int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset;
int offset, i;
@@ -579,7 +578,7 @@ nv40_gr_construct_shader(struct nouveau_grctx *ctx)
offset = ctx->ctxvals_pos;
ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len));
- if (ctx->mode != NOUVEAU_GRCTX_VALS)
+ if (ctx->mode != NVKM_GRCTX_VALS)
return;
offset += 0x0280/4;
@@ -595,7 +594,7 @@ nv40_gr_construct_shader(struct nouveau_grctx *ctx)
}
static void
-nv40_grctx_generate(struct nouveau_grctx *ctx)
+nv40_grctx_generate(struct nvkm_grctx *ctx)
{
/* decide whether we're loading/unloading the context */
cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
@@ -660,22 +659,22 @@ nv40_grctx_generate(struct nouveau_grctx *ctx)
}
void
-nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
+nv40_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem)
{
- nv40_grctx_generate(&(struct nouveau_grctx) {
+ nv40_grctx_generate(&(struct nvkm_grctx) {
.device = device,
- .mode = NOUVEAU_GRCTX_VALS,
+ .mode = NVKM_GRCTX_VALS,
.data = mem,
});
}
int
-nv40_grctx_init(struct nouveau_device *device, u32 *size)
+nv40_grctx_init(struct nvkm_device *device, u32 *size)
{
u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i;
- struct nouveau_grctx ctx = {
+ struct nvkm_grctx ctx = {
.device = device,
- .mode = NOUVEAU_GRCTX_PROG,
+ .mode = NVKM_GRCTX_PROG,
.data = ctxprog,
.ctxprog_max = 256,
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h
similarity index 74%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h
index e1947013d3bc..8a89961956af 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h
@@ -1,12 +1,13 @@
-#ifndef __NOUVEAU_GRCTX_H__
-#define __NOUVEAU_GRCTX_H__
+#ifndef __NVKM_GRCTX_H__
+#define __NVKM_GRCTX_H__
+#include <core/gpuobj.h>
-struct nouveau_grctx {
- struct nouveau_device *device;
+struct nvkm_grctx {
+ struct nvkm_device *device;
enum {
- NOUVEAU_GRCTX_PROG,
- NOUVEAU_GRCTX_VALS
+ NVKM_GRCTX_PROG,
+ NVKM_GRCTX_VALS
} mode;
void *data;
@@ -19,11 +20,11 @@ struct nouveau_grctx {
};
static inline void
-cp_out(struct nouveau_grctx *ctx, u32 inst)
+cp_out(struct nvkm_grctx *ctx, u32 inst)
{
u32 *ctxprog = ctx->data;
- if (ctx->mode != NOUVEAU_GRCTX_PROG)
+ if (ctx->mode != NVKM_GRCTX_PROG)
return;
BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max);
@@ -31,13 +32,13 @@ cp_out(struct nouveau_grctx *ctx, u32 inst)
}
static inline void
-cp_lsr(struct nouveau_grctx *ctx, u32 val)
+cp_lsr(struct nvkm_grctx *ctx, u32 val)
{
cp_out(ctx, CP_LOAD_SR | val);
}
static inline void
-cp_ctx(struct nouveau_grctx *ctx, u32 reg, u32 length)
+cp_ctx(struct nvkm_grctx *ctx, u32 reg, u32 length)
{
ctx->ctxprog_reg = (reg - 0x00400000) >> 2;
@@ -53,12 +54,12 @@ cp_ctx(struct nouveau_grctx *ctx, u32 reg, u32 length)
}
static inline void
-cp_name(struct nouveau_grctx *ctx, int name)
+cp_name(struct nvkm_grctx *ctx, int name)
{
u32 *ctxprog = ctx->data;
int i;
- if (ctx->mode != NOUVEAU_GRCTX_PROG)
+ if (ctx->mode != NVKM_GRCTX_PROG)
return;
ctx->ctxprog_label[name] = ctx->ctxprog_len;
@@ -73,7 +74,7 @@ cp_name(struct nouveau_grctx *ctx, int name)
}
static inline void
-_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name)
+_cp_bra(struct nvkm_grctx *ctx, u32 mod, int flag, int state, int name)
{
int ip = 0;
@@ -91,21 +92,21 @@ _cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name)
#define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)
static inline void
-_cp_wait(struct nouveau_grctx *ctx, int flag, int state)
+_cp_wait(struct nvkm_grctx *ctx, int flag, int state)
{
cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0));
}
#define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
static inline void
-_cp_set(struct nouveau_grctx *ctx, int flag, int state)
+_cp_set(struct nvkm_grctx *ctx, int flag, int state)
{
cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0));
}
#define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
static inline void
-cp_pos(struct nouveau_grctx *ctx, int offset)
+cp_pos(struct nvkm_grctx *ctx, int offset)
{
ctx->ctxvals_pos = offset;
ctx->ctxvals_base = ctx->ctxvals_pos;
@@ -115,9 +116,9 @@ cp_pos(struct nouveau_grctx *ctx, int offset)
}
static inline void
-gr_def(struct nouveau_grctx *ctx, u32 reg, u32 val)
+gr_def(struct nvkm_grctx *ctx, u32 reg, u32 val)
{
- if (ctx->mode != NOUVEAU_GRCTX_VALS)
+ if (ctx->mode != NVKM_GRCTX_VALS)
return;
reg = (reg - 0x00400000) / 4;
@@ -125,5 +126,4 @@ gr_def(struct nouveau_grctx *ctx, u32 reg, u32 val)
nv_wo32(ctx->data, reg * 4, val);
}
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
index 2798d26a8ca3..9c9528d2cd90 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
@@ -20,9 +20,6 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <core/device.h>
-#include <core/gpuobj.h>
-
#define CP_FLAG_CLEAR 0
#define CP_FLAG_SET 1
#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
@@ -108,14 +105,14 @@
#define CP_SEEK_1 0x00c000ff
#define CP_SEEK_2 0x00c800ff
-#include "nv50.h"
-#include "ctx.h"
+#include "ctxnv40.h"
+
+#include <core/device.h>
+#include <subdev/fb.h>
#define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf)
#define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac)
-#include <subdev/fb.h>
-
/*
* This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's
* the GPU itself that does context-switching, but it needs a special
@@ -170,14 +167,14 @@ enum cp_label {
cp_exit,
};
-static void nv50_gr_construct_mmio(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_xfer1(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_xfer2(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_mmio(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_xfer1(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_xfer2(struct nvkm_grctx *ctx);
/* Main function: construct the ctxprog skeleton, call the other functions. */
static int
-nv50_grctx_generate(struct nouveau_grctx *ctx)
+nv50_grctx_generate(struct nvkm_grctx *ctx)
{
cp_set (ctx, STATE, RUNNING);
cp_set (ctx, XFER_SWITCH, ENABLE);
@@ -256,22 +253,22 @@ nv50_grctx_generate(struct nouveau_grctx *ctx)
}
void
-nv50_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
+nv50_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem)
{
- nv50_grctx_generate(&(struct nouveau_grctx) {
+ nv50_grctx_generate(&(struct nvkm_grctx) {
.device = device,
- .mode = NOUVEAU_GRCTX_VALS,
+ .mode = NVKM_GRCTX_VALS,
.data = mem,
});
}
int
-nv50_grctx_init(struct nouveau_device *device, u32 *size)
+nv50_grctx_init(struct nvkm_device *device, u32 *size)
{
u32 *ctxprog = kmalloc(512 * 4, GFP_KERNEL), i;
- struct nouveau_grctx ctx = {
+ struct nvkm_grctx ctx = {
.device = device,
- .mode = NOUVEAU_GRCTX_PROG,
+ .mode = NVKM_GRCTX_PROG,
.data = ctxprog,
.ctxprog_max = 512,
};
@@ -294,12 +291,12 @@ nv50_grctx_init(struct nouveau_device *device, u32 *size)
*/
static void
-nv50_gr_construct_mmio_ddata(struct nouveau_grctx *ctx);
+nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx);
static void
-nv50_gr_construct_mmio(struct nouveau_grctx *ctx)
+nv50_gr_construct_mmio(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i, j;
int offset, base;
u32 units = nv_rd32 (ctx->device, 0x1540);
@@ -573,7 +570,7 @@ nv50_gr_construct_mmio(struct nouveau_grctx *ctx)
else if (device->chipset < 0xa0)
gr_def(ctx, 0x407d08, 0x00390040);
else {
- if (nouveau_fb(device)->ram->type != NV_MEM_TYPE_GDDR5)
+ if (nvkm_fb(device)->ram->type != NV_MEM_TYPE_GDDR5)
gr_def(ctx, 0x407d08, 0x003d0040);
else
gr_def(ctx, 0x407d08, 0x003c0040);
@@ -785,18 +782,18 @@ nv50_gr_construct_mmio(struct nouveau_grctx *ctx)
}
static void
-dd_emit(struct nouveau_grctx *ctx, int num, u32 val) {
+dd_emit(struct nvkm_grctx *ctx, int num, u32 val) {
int i;
- if (val && ctx->mode == NOUVEAU_GRCTX_VALS)
+ if (val && ctx->mode == NVKM_GRCTX_VALS)
for (i = 0; i < num; i++)
nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val);
ctx->ctxvals_pos += num;
}
static void
-nv50_gr_construct_mmio_ddata(struct nouveau_grctx *ctx)
+nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int base, num;
base = ctx->ctxvals_pos;
@@ -1157,9 +1154,9 @@ nv50_gr_construct_mmio_ddata(struct nouveau_grctx *ctx)
*/
static void
-xf_emit(struct nouveau_grctx *ctx, int num, u32 val) {
+xf_emit(struct nvkm_grctx *ctx, int num, u32 val) {
int i;
- if (val && ctx->mode == NOUVEAU_GRCTX_VALS)
+ if (val && ctx->mode == NVKM_GRCTX_VALS)
for (i = 0; i < num; i++)
nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val);
ctx->ctxvals_pos += num << 3;
@@ -1167,29 +1164,29 @@ xf_emit(struct nouveau_grctx *ctx, int num, u32 val) {
/* Gene declarations... */
-static void nv50_gr_construct_gene_dispatch(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_m2mf(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_ccache(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_unk10xx(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_unk14xx(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_zcull(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_clipid(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_unk24xx(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_vfetch(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_eng2d(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_csched(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_unk1cxx(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_strmout(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_unk34xx(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_ropm1(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_ropm2(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_ropc(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_xfer_tp(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_dispatch(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_m2mf(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_ccache(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_unk10xx(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_unk14xx(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_zcull(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_clipid(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_unk24xx(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_vfetch(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_eng2d(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_csched(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_unk1cxx(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_strmout(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_unk34xx(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_ropm1(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_ropm2(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_ropc(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_xfer_tp(struct nvkm_grctx *ctx);
static void
-nv50_gr_construct_xfer1(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer1(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
int offset;
int size = 0;
@@ -1350,10 +1347,10 @@ nv50_gr_construct_xfer1(struct nouveau_grctx *ctx)
*/
static void
-nv50_gr_construct_gene_dispatch(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_dispatch(struct nvkm_grctx *ctx)
{
/* start of strand 0 */
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* SEEK */
if (device->chipset == 0x50)
xf_emit(ctx, 5, 0);
@@ -1406,10 +1403,10 @@ nv50_gr_construct_gene_dispatch(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_m2mf(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_m2mf(struct nvkm_grctx *ctx)
{
/* Strand 0, right after dispatch */
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int smallm2mf = 0;
if (device->chipset < 0x92 || device->chipset == 0x98)
smallm2mf = 1;
@@ -1458,9 +1455,9 @@ nv50_gr_construct_gene_m2mf(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_ccache(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ccache(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
xf_emit(ctx, 2, 0); /* RO */
xf_emit(ctx, 0x800, 0); /* ffffffff */
switch (device->chipset) {
@@ -1526,9 +1523,9 @@ nv50_gr_construct_gene_ccache(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_unk10xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk10xx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
/* end of area 2 on pre-NVA0, area 1 on NVAx */
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
@@ -1586,9 +1583,9 @@ nv50_gr_construct_gene_unk10xx(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_unk34xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk34xx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* end of area 2 on pre-NVA0, area 1 on NVAx */
xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */
xf_emit(ctx, 1, 0); /* 00000003 VIEWPORT_CLIP_MODE */
@@ -1611,9 +1608,9 @@ nv50_gr_construct_gene_unk34xx(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_unk14xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk14xx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */
if (device->chipset != 0x50) {
xf_emit(ctx, 5, 0); /* ffffffff */
@@ -1722,9 +1719,9 @@ nv50_gr_construct_gene_unk14xx(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_zcull(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_zcull(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */
/* SEEK */
xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */
@@ -1783,7 +1780,7 @@ nv50_gr_construct_gene_zcull(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_clipid(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_clipid(struct nvkm_grctx *ctx)
{
/* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */
/* SEEK */
@@ -1803,9 +1800,9 @@ nv50_gr_construct_gene_clipid(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_unk24xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk24xx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
/* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */
/* SEEK */
@@ -1886,9 +1883,9 @@ nv50_gr_construct_gene_unk24xx(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_vfetch(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_vfetch(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int acnt = 0x10, rep, i;
/* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */
if (IS_NVA3F(device->chipset))
@@ -2072,9 +2069,9 @@ nv50_gr_construct_gene_vfetch(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_eng2d(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_eng2d(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */
/* SEEK */
xf_emit(ctx, 2, 0); /* 0001ffff CLIP_X, CLIP_Y */
@@ -2134,9 +2131,9 @@ nv50_gr_construct_gene_eng2d(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_csched(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_csched(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */
/* SEEK */
xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */
@@ -2233,9 +2230,9 @@ nv50_gr_construct_gene_csched(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk1cxx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */
xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
@@ -2329,9 +2326,9 @@ nv50_gr_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_strmout(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_strmout(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */
xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */
xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */
@@ -2371,9 +2368,9 @@ nv50_gr_construct_gene_strmout(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_ropm1(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ropm1(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */
xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */
xf_emit(ctx, 1, 0); /* 00000007 */
@@ -2384,9 +2381,9 @@ nv50_gr_construct_gene_ropm1(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_ropm2(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ropm2(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* SEEK */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */
xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
@@ -2410,9 +2407,9 @@ nv50_gr_construct_gene_ropm2(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_gene_ropc(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ropc(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int magic2;
if (device->chipset == 0x50) {
magic2 = 0x00003e60;
@@ -2645,9 +2642,9 @@ nv50_gr_construct_gene_ropc(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_unk84xx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int magic3;
switch (device->chipset) {
case 0x50:
@@ -2737,9 +2734,9 @@ nv50_gr_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_xfer_tprop(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_tprop(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int magic1, magic2;
if (device->chipset == 0x50) {
magic1 = 0x3ff;
@@ -3037,9 +3034,9 @@ nv50_gr_construct_xfer_tprop(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_xfer_tex(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_tex(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
xf_emit(ctx, 2, 0); /* 1 LINKED_TSC. yes, 2. */
if (device->chipset != 0x50)
xf_emit(ctx, 1, 0); /* 3 */
@@ -3083,9 +3080,9 @@ nv50_gr_construct_xfer_tex(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_unk8cxx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 2, 0); /* 7, ffff0ff3 */
@@ -3122,9 +3119,9 @@ nv50_gr_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_xfer_tp(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_tp(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
if (device->chipset < 0xa0) {
nv50_gr_construct_xfer_unk84xx(ctx);
nv50_gr_construct_xfer_tprop(ctx);
@@ -3139,9 +3136,9 @@ nv50_gr_construct_xfer_tp(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_xfer_mpc(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_mpc(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i, mpcnt = 2;
switch (device->chipset) {
case 0x98:
@@ -3271,9 +3268,9 @@ nv50_gr_construct_xfer_mpc(struct nouveau_grctx *ctx)
}
static void
-nv50_gr_construct_xfer2(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer2(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
u32 offset;
u32 units = nv_rd32 (ctx->device, 0x1540);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h
deleted file mode 100644
index 0dbcd5839252..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h
+++ /dev/null
@@ -1,202 +0,0 @@
-#ifndef __NVKM_GRCTX_NVC0_H__
-#define __NVKM_GRCTX_NVC0_H__
-
-#include "nvc0.h"
-
-struct nvc0_grctx {
- struct nvc0_gr_priv *priv;
- struct nvc0_gr_data *data;
- struct nvc0_gr_mmio *mmio;
- int buffer_nr;
- u64 buffer[4];
- u64 addr;
-};
-
-int nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access);
-void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int);
-
-#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d))
-#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e))
-#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1)
-#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1)
-
-struct nvc0_grctx_oclass {
- struct nouveau_oclass base;
- /* main context generation function */
- void (*main)(struct nvc0_gr_priv *, struct nvc0_grctx *);
- /* context-specific modify-on-first-load list generation function */
- void (*unkn)(struct nvc0_gr_priv *);
- /* mmio context data */
- const struct nvc0_gr_pack *hub;
- const struct nvc0_gr_pack *gpc;
- const struct nvc0_gr_pack *zcull;
- const struct nvc0_gr_pack *tpc;
- const struct nvc0_gr_pack *ppc;
- /* indirect context data, generated with icmds/mthds */
- const struct nvc0_gr_pack *icmd;
- const struct nvc0_gr_pack *mthd;
- /* bundle circular buffer */
- void (*bundle)(struct nvc0_grctx *);
- u32 bundle_size;
- u32 bundle_min_gpm_fifo_depth;
- u32 bundle_token_limit;
- /* pagepool */
- void (*pagepool)(struct nvc0_grctx *);
- u32 pagepool_size;
- /* attribute(/alpha) circular buffer */
- void (*attrib)(struct nvc0_grctx *);
- u32 attrib_nr_max;
- u32 attrib_nr;
- u32 alpha_nr_max;
- u32 alpha_nr;
-};
-
-static inline const struct nvc0_grctx_oclass *
-nvc0_grctx_impl(struct nvc0_gr_priv *priv)
-{
- return (void *)nv_engine(priv)->cclass;
-}
-
-extern struct nouveau_oclass *nvc0_grctx_oclass;
-int nvc0_grctx_generate(struct nvc0_gr_priv *);
-void nvc0_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *);
-void nvc0_grctx_generate_bundle(struct nvc0_grctx *);
-void nvc0_grctx_generate_pagepool(struct nvc0_grctx *);
-void nvc0_grctx_generate_attrib(struct nvc0_grctx *);
-void nvc0_grctx_generate_unkn(struct nvc0_gr_priv *);
-void nvc0_grctx_generate_tpcid(struct nvc0_gr_priv *);
-void nvc0_grctx_generate_r406028(struct nvc0_gr_priv *);
-void nvc0_grctx_generate_r4060a8(struct nvc0_gr_priv *);
-void nvc0_grctx_generate_r418bb8(struct nvc0_gr_priv *);
-void nvc0_grctx_generate_r406800(struct nvc0_gr_priv *);
-
-extern struct nouveau_oclass *nvc1_grctx_oclass;
-void nvc1_grctx_generate_attrib(struct nvc0_grctx *);
-void nvc1_grctx_generate_unkn(struct nvc0_gr_priv *);
-
-extern struct nouveau_oclass *nvc4_grctx_oclass;
-extern struct nouveau_oclass *nvc8_grctx_oclass;
-
-extern struct nouveau_oclass *nvd7_grctx_oclass;
-void nvd7_grctx_generate_attrib(struct nvc0_grctx *);
-
-extern struct nouveau_oclass *nvd9_grctx_oclass;
-
-extern struct nouveau_oclass *nve4_grctx_oclass;
-extern struct nouveau_oclass *gk20a_grctx_oclass;
-void nve4_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *);
-void nve4_grctx_generate_bundle(struct nvc0_grctx *);
-void nve4_grctx_generate_pagepool(struct nvc0_grctx *);
-void nve4_grctx_generate_unkn(struct nvc0_gr_priv *);
-void nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *);
-
-extern struct nouveau_oclass *nvf0_grctx_oclass;
-extern struct nouveau_oclass *gk110b_grctx_oclass;
-extern struct nouveau_oclass *nv108_grctx_oclass;
-extern struct nouveau_oclass *gm107_grctx_oclass;
-
-/* context init value lists */
-
-extern const struct nvc0_gr_pack nvc0_grctx_pack_icmd[];
-
-extern const struct nvc0_gr_pack nvc0_grctx_pack_mthd[];
-extern const struct nvc0_gr_init nvc0_grctx_init_902d_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_9039_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_90c0_0[];
-
-extern const struct nvc0_gr_pack nvc0_grctx_pack_hub[];
-extern const struct nvc0_gr_init nvc0_grctx_init_main_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_fe_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_pri_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_memfmt_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_rstr2d_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_scc_0[];
-
-extern const struct nvc0_gr_pack nvc0_grctx_pack_gpc[];
-extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_prop_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_1[];
-extern const struct nvc0_gr_init nvc0_grctx_init_zcull_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_crstr_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_gpm_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_gcc_0[];
-
-extern const struct nvc0_gr_pack nvc0_grctx_pack_zcull[];
-
-extern const struct nvc0_gr_pack nvc0_grctx_pack_tpc[];
-extern const struct nvc0_gr_init nvc0_grctx_init_pe_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_wwdx_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_mpc_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_tpccs_0[];
-
-extern const struct nvc0_gr_init nvc4_grctx_init_tex_0[];
-extern const struct nvc0_gr_init nvc4_grctx_init_l1c_0[];
-extern const struct nvc0_gr_init nvc4_grctx_init_sm_0[];
-
-extern const struct nvc0_gr_init nvc1_grctx_init_9097_0[];
-
-extern const struct nvc0_gr_init nvc1_grctx_init_gpm_0[];
-
-extern const struct nvc0_gr_init nvc1_grctx_init_pe_0[];
-extern const struct nvc0_gr_init nvc1_grctx_init_wwdx_0[];
-extern const struct nvc0_gr_init nvc1_grctx_init_tpccs_0[];
-
-extern const struct nvc0_gr_init nvc8_grctx_init_9197_0[];
-extern const struct nvc0_gr_init nvc8_grctx_init_9297_0[];
-
-extern const struct nvc0_gr_pack nvd9_grctx_pack_icmd[];
-
-extern const struct nvc0_gr_pack nvd9_grctx_pack_mthd[];
-
-extern const struct nvc0_gr_init nvd9_grctx_init_fe_0[];
-extern const struct nvc0_gr_init nvd9_grctx_init_be_0[];
-
-extern const struct nvc0_gr_init nvd9_grctx_init_prop_0[];
-extern const struct nvc0_gr_init nvd9_grctx_init_gpc_unk_1[];
-extern const struct nvc0_gr_init nvd9_grctx_init_crstr_0[];
-
-extern const struct nvc0_gr_init nvd9_grctx_init_sm_0[];
-
-extern const struct nvc0_gr_init nvd7_grctx_init_pe_0[];
-
-extern const struct nvc0_gr_init nvd7_grctx_init_wwdx_0[];
-
-extern const struct nvc0_gr_init nve4_grctx_init_memfmt_0[];
-extern const struct nvc0_gr_init nve4_grctx_init_ds_0[];
-extern const struct nvc0_gr_init nve4_grctx_init_scc_0[];
-
-extern const struct nvc0_gr_init nve4_grctx_init_gpm_0[];
-
-extern const struct nvc0_gr_init nve4_grctx_init_pes_0[];
-
-extern const struct nvc0_gr_pack nve4_grctx_pack_hub[];
-extern const struct nvc0_gr_pack nve4_grctx_pack_gpc[];
-extern const struct nvc0_gr_pack nve4_grctx_pack_tpc[];
-extern const struct nvc0_gr_pack nve4_grctx_pack_ppc[];
-extern const struct nvc0_gr_pack nve4_grctx_pack_icmd[];
-extern const struct nvc0_gr_init nve4_grctx_init_a097_0[];
-
-extern const struct nvc0_gr_pack nvf0_grctx_pack_icmd[];
-
-extern const struct nvc0_gr_pack nvf0_grctx_pack_mthd[];
-
-extern const struct nvc0_gr_pack nvf0_grctx_pack_hub[];
-extern const struct nvc0_gr_init nvf0_grctx_init_pri_0[];
-extern const struct nvc0_gr_init nvf0_grctx_init_cwd_0[];
-
-extern const struct nvc0_gr_pack nvf0_grctx_pack_gpc[];
-extern const struct nvc0_gr_init nvf0_grctx_init_gpc_unk_2[];
-
-extern const struct nvc0_gr_init nvf0_grctx_init_tex_0[];
-extern const struct nvc0_gr_init nvf0_grctx_init_mpc_0[];
-extern const struct nvc0_gr_init nvf0_grctx_init_l1c_0[];
-
-extern const struct nvc0_gr_pack nvf0_grctx_pack_ppc[];
-
-extern const struct nvc0_gr_init nv108_grctx_init_rstr2d_0[];
-
-extern const struct nvc0_gr_init nv108_grctx_init_prop_0[];
-extern const struct nvc0_gr_init nv108_grctx_init_crstr_0[];
-
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc
index e37d8106ae1a..64208bf954cf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc
@@ -1,4 +1,4 @@
-/* fuc microcode util functions for nvc0 PGRAPH
+/* fuc microcode util functions for gf100 PGRAPH
*
* Copyright 2011 Red Hat Inc.
*
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
index 7445f12b1d9e..eaed1599b90f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
@@ -1,4 +1,4 @@
-/* fuc microcode for nvc0 PGRAPH/GPC
+/* fuc microcode for gf100 PGRAPH/GPC
*
* Copyright 2011 Red Hat Inc.
*
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3
index 5ae06a2d64c9..7cf2bf9d95a2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3
@@ -27,13 +27,13 @@
#define CHIPSET GF100
#include "macros.fuc"
-.section #nvc0_grgpc_data
+.section #gf100_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
-.section #nvc0_grgpc_code
+.section #gf100_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h
index 325cc7b7b2fb..ea32f56c0a92 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvc0_grgpc_data[] = {
+uint32_t gf100_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x00000064,
/* 0x0004: gpc_mmio_list_tail */
@@ -36,7 +36,7 @@ uint32_t nvc0_grgpc_data[] = {
0x00000000,
};
-uint32_t nvc0_grgpc_code[] = {
+uint32_t gf100_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3
index c2f754edbd7d..c918f7d60004 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3
@@ -27,13 +27,13 @@
#define CHIPSET GF117
#include "macros.fuc"
-.section #nvd7_grgpc_data
+.section #gf117_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
-.section #nvd7_grgpc_code
+.section #gf117_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
index 855b220378f9..9a36d9cbb8a5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nve0_grgpc_data[] = {
+uint32_t gf117_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
@@ -40,7 +40,7 @@ uint32_t nve0_grgpc_data[] = {
0x00000000,
};
-uint32_t nve0_grgpc_code[] = {
+uint32_t gf117_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3
index 6b906cd2a31f..b80cdfd337a9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3
@@ -27,13 +27,13 @@
#define CHIPSET GK100
#include "macros.fuc"
-.section #nve0_grgpc_data
+.section #gk104_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
-.section #nve0_grgpc_code
+.section #gk104_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
index d1504a4059c6..49020fff4317 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvd7_grgpc_data[] = {
+uint32_t gk104_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
@@ -40,7 +40,7 @@ uint32_t nvd7_grgpc_data[] = {
0x00000000,
};
-uint32_t nvd7_grgpc_code[] = {
+uint32_t gk104_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3
index 90bbe525b626..98d85fe210e8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3
@@ -27,13 +27,13 @@
#define CHIPSET GK110
#include "macros.fuc"
-.section #nvf0_grgpc_data
+.section #gk110_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
-.section #nvf0_grgpc_code
+.section #gk110_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
index 1b803197d28b..c95b07e3bce5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvf0_grgpc_data[] = {
+uint32_t gk110_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
@@ -40,7 +40,7 @@ uint32_t nvf0_grgpc_data[] = {
0x00000000,
};
-uint32_t nvf0_grgpc_code[] = {
+uint32_t gk110_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5
index bd30262d635b..8f64299a3b91 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5
@@ -27,13 +27,13 @@
#define CHIPSET GK208
#include "macros.fuc"
-.section #nv108_grgpc_data
+.section #gk208_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
-.section #nv108_grgpc_code
+.section #gk208_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
index 31922707794f..7e1c28ee7591 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
@@ -1,4 +1,4 @@
-uint32_t nv108_grgpc_data[] = {
+uint32_t gk208_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
@@ -40,7 +40,7 @@ uint32_t nv108_grgpc_data[] = {
0x00000000,
};
-uint32_t nv108_grgpc_code[] = {
+uint32_t gk208_grgpc_code[] = {
0x03140ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc
index b4ad18bf5a26..87f99e38acbf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc
@@ -1,4 +1,4 @@
-/* fuc microcode for nvc0 PGRAPH/HUB
+/* fuc microcode for gf100 PGRAPH/HUB
*
* Copyright 2011 Red Hat Inc.
*
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3
index 3ff52badf932..2c28e7199b7f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3
@@ -25,13 +25,13 @@
#define CHIPSET GF100
#include "macros.fuc"
-.section #nvc0_grhub_data
+.section #gf100_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
-.section #nvc0_grhub_code
+.section #gf100_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h
index 62b0c7601d8b..f6acda505677 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvd7_grhub_data[] = {
+uint32_t gf100_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
@@ -205,7 +205,7 @@ uint32_t nvd7_grhub_data[] = {
0x0417e91c,
};
-uint32_t nvd7_grhub_code[] = {
+uint32_t gf100_grhub_code[] = {
0x039b0ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3
index afbe03ac9077..581b2d53ab0c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3
@@ -25,13 +25,13 @@
#define CHIPSET GF117
#include "macros.fuc"
-.section #nvd7_grhub_data
+.section #gf117_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
-.section #nvd7_grhub_code
+.section #gf117_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h
index 92dfe6a4ac87..7cb14e59dea1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvc0_grhub_data[] = {
+uint32_t gf117_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
@@ -205,7 +205,7 @@ uint32_t nvc0_grhub_data[] = {
0x0417e91c,
};
-uint32_t nvc0_grhub_code[] = {
+uint32_t gf117_grhub_code[] = {
0x039b0ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3
index d4840f1879fd..d977d393b679 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3
@@ -25,13 +25,13 @@
#define CHIPSET GK100
#include "macros.fuc"
-.section #nve0_grhub_data
+.section #gk104_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
-.section #nve0_grhub_code
+.section #gk104_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h
index 51c3797d8537..95ac15110049 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nve0_grhub_data[] = {
+uint32_t gk104_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
@@ -205,7 +205,7 @@ uint32_t nve0_grhub_data[] = {
0x0417e91c,
};
-uint32_t nve0_grhub_code[] = {
+uint32_t gk104_grhub_code[] = {
0x039b0ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3
index ec42ed29b50d..760b4632f22d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3
@@ -25,13 +25,13 @@
#define CHIPSET GK110
#include "macros.fuc"
-.section #nvf0_grhub_data
+.section #gk110_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
-.section #nvf0_grhub_code
+.section #gk110_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h
index a0af4b703a8e..89986878480f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvf0_grhub_data[] = {
+uint32_t gk110_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
@@ -205,7 +205,7 @@ uint32_t nvf0_grhub_data[] = {
0x0417e91c,
};
-uint32_t nvf0_grhub_code[] = {
+uint32_t gk110_grhub_code[] = {
0x039b0ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5
index 7c5d25630fa8..43243a35f6dc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5
@@ -25,13 +25,13 @@
#define CHIPSET GK208
#include "macros.fuc"
-.section #nv108_grhub_data
+.section #gk208_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
-.section #nv108_grhub_code
+.section #gk208_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h
index e49b5a877ae4..0e98fa4a386e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h
@@ -1,4 +1,4 @@
-uint32_t nv108_grhub_data[] = {
+uint32_t gk208_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
@@ -205,7 +205,7 @@ uint32_t nv108_grhub_data[] = {
0x0417e91c,
};
-uint32_t nv108_grhub_code[] = {
+uint32_t gk208_grhub_code[] = {
0x030e0ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
similarity index 72%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
index 8133650b2777..1dd482e9da77 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
@@ -21,16 +21,28 @@
*
* Authors: Ben Skeggs
*/
+#include "gf100.h"
+#include "ctxgf100.h"
+#include "fuc/os.h"
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <core/client.h>
+#include <core/device.h>
+#include <core/handle.h>
+#include <core/option.h>
+#include <engine/fifo.h>
+#include <subdev/fb.h>
+#include <subdev/mc.h>
+#include <subdev/timer.h>
+
+#include <nvif/class.h>
+#include <nvif/unpack.h>
/*******************************************************************************
* Zero Bandwidth Clear
******************************************************************************/
static void
-nvc0_gr_zbc_clear_color(struct nvc0_gr_priv *priv, int zbc)
+gf100_gr_zbc_clear_color(struct gf100_gr_priv *priv, int zbc)
{
if (priv->zbc_color[zbc].format) {
nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]);
@@ -44,10 +56,10 @@ nvc0_gr_zbc_clear_color(struct nvc0_gr_priv *priv, int zbc)
}
static int
-nvc0_gr_zbc_color_get(struct nvc0_gr_priv *priv, int format,
- const u32 ds[4], const u32 l2[4])
+gf100_gr_zbc_color_get(struct gf100_gr_priv *priv, int format,
+ const u32 ds[4], const u32 l2[4])
{
- struct nouveau_ltc *ltc = nouveau_ltc(priv);
+ struct nvkm_ltc *ltc = nvkm_ltc(priv);
int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
@@ -75,12 +87,12 @@ nvc0_gr_zbc_color_get(struct nvc0_gr_priv *priv, int format,
memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2));
priv->zbc_color[zbc].format = format;
ltc->zbc_color_get(ltc, zbc, l2);
- nvc0_gr_zbc_clear_color(priv, zbc);
+ gf100_gr_zbc_clear_color(priv, zbc);
return zbc;
}
static void
-nvc0_gr_zbc_clear_depth(struct nvc0_gr_priv *priv, int zbc)
+gf100_gr_zbc_clear_depth(struct gf100_gr_priv *priv, int zbc)
{
if (priv->zbc_depth[zbc].format)
nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds);
@@ -90,10 +102,10 @@ nvc0_gr_zbc_clear_depth(struct nvc0_gr_priv *priv, int zbc)
}
static int
-nvc0_gr_zbc_depth_get(struct nvc0_gr_priv *priv, int format,
- const u32 ds, const u32 l2)
+gf100_gr_zbc_depth_get(struct gf100_gr_priv *priv, int format,
+ const u32 ds, const u32 l2)
{
- struct nouveau_ltc *ltc = nouveau_ltc(priv);
+ struct nvkm_ltc *ltc = nvkm_ltc(priv);
int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
@@ -119,7 +131,7 @@ nvc0_gr_zbc_depth_get(struct nvc0_gr_priv *priv, int format,
priv->zbc_depth[zbc].ds = ds;
priv->zbc_depth[zbc].l2 = l2;
ltc->zbc_depth_get(ltc, zbc, l2);
- nvc0_gr_zbc_clear_depth(priv, zbc);
+ gf100_gr_zbc_clear_depth(priv, zbc);
return zbc;
}
@@ -128,9 +140,9 @@ nvc0_gr_zbc_depth_get(struct nvc0_gr_priv *priv, int format,
******************************************************************************/
static int
-nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size)
+gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
{
- struct nvc0_gr_priv *priv = (void *)object->engine;
+ struct gf100_gr_priv *priv = (void *)object->engine;
union {
struct fermi_a_zbc_color_v0 v0;
} *args = data;
@@ -157,9 +169,9 @@ nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size)
case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
- ret = nvc0_gr_zbc_color_get(priv, args->v0.format,
- args->v0.ds,
- args->v0.l2);
+ ret = gf100_gr_zbc_color_get(priv, args->v0.format,
+ args->v0.ds,
+ args->v0.l2);
if (ret >= 0) {
args->v0.index = ret;
return 0;
@@ -174,9 +186,9 @@ nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size)
}
static int
-nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size)
+gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
{
- struct nvc0_gr_priv *priv = (void *)object->engine;
+ struct gf100_gr_priv *priv = (void *)object->engine;
union {
struct fermi_a_zbc_depth_v0 v0;
} *args = data;
@@ -185,9 +197,9 @@ nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size)
if (nvif_unpack(args->v0, 0, 0, false)) {
switch (args->v0.format) {
case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
- ret = nvc0_gr_zbc_depth_get(priv, args->v0.format,
- args->v0.ds,
- args->v0.l2);
+ ret = gf100_gr_zbc_depth_get(priv, args->v0.format,
+ args->v0.ds,
+ args->v0.l2);
return (ret >= 0) ? 0 : -ENOSPC;
default:
return -EINVAL;
@@ -198,33 +210,33 @@ nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size)
}
static int
-nvc0_fermi_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size)
+gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
switch (mthd) {
case FERMI_A_ZBC_COLOR:
- return nvc0_fermi_mthd_zbc_color(object, data, size);
+ return gf100_fermi_mthd_zbc_color(object, data, size);
case FERMI_A_ZBC_DEPTH:
- return nvc0_fermi_mthd_zbc_depth(object, data, size);
+ return gf100_fermi_mthd_zbc_depth(object, data, size);
default:
break;
}
return -EINVAL;
}
-struct nouveau_ofuncs
-nvc0_fermi_ofuncs = {
- .ctor = _nouveau_object_ctor,
- .dtor = nouveau_object_destroy,
- .init = nouveau_object_init,
- .fini = nouveau_object_fini,
- .mthd = nvc0_fermi_mthd,
+struct nvkm_ofuncs
+gf100_fermi_ofuncs = {
+ .ctor = _nvkm_object_ctor,
+ .dtor = nvkm_object_destroy,
+ .init = nvkm_object_init,
+ .fini = nvkm_object_fini,
+ .mthd = gf100_fermi_mthd,
};
static int
-nvc0_gr_set_shader_exceptions(struct nouveau_object *object, u32 mthd,
- void *pdata, u32 size)
+gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd,
+ void *pdata, u32 size)
{
- struct nvc0_gr_priv *priv = (void *)nv_engine(object);
+ struct gf100_gr_priv *priv = (void *)nv_engine(object);
if (size >= sizeof(u32)) {
u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000;
nv_wr32(priv, 0x419e44, data);
@@ -234,24 +246,24 @@ nvc0_gr_set_shader_exceptions(struct nouveau_object *object, u32 mthd,
return -EINVAL;
}
-struct nouveau_omthds
-nvc0_gr_9097_omthds[] = {
- { 0x1528, 0x1528, nvc0_gr_set_shader_exceptions },
+struct nvkm_omthds
+gf100_gr_9097_omthds[] = {
+ { 0x1528, 0x1528, gf100_gr_set_shader_exceptions },
{}
};
-struct nouveau_omthds
-nvc0_gr_90c0_omthds[] = {
- { 0x1528, 0x1528, nvc0_gr_set_shader_exceptions },
+struct nvkm_omthds
+gf100_gr_90c0_omthds[] = {
+ { 0x1528, 0x1528, gf100_gr_set_shader_exceptions },
{}
};
-struct nouveau_oclass
-nvc0_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0x9039, &nouveau_object_ofuncs },
- { FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
+struct nvkm_oclass
+gf100_gr_sclass[] = {
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0x9039, &nvkm_object_ofuncs },
+ { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{}
};
@@ -260,22 +272,21 @@ nvc0_gr_sclass[] = {
******************************************************************************/
int
-nvc0_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *args, u32 size,
- struct nouveau_object **pobject)
+gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *args, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_vm *vm = nouveau_client(parent)->vm;
- struct nvc0_gr_priv *priv = (void *)engine;
- struct nvc0_gr_data *data = priv->mmio_data;
- struct nvc0_gr_mmio *mmio = priv->mmio_list;
- struct nvc0_gr_chan *chan;
+ struct nvkm_vm *vm = nvkm_client(parent)->vm;
+ struct gf100_gr_priv *priv = (void *)engine;
+ struct gf100_gr_data *data = priv->mmio_data;
+ struct gf100_gr_mmio *mmio = priv->mmio_list;
+ struct gf100_gr_chan *chan;
int ret, i;
/* allocate memory for context, and fill with default values */
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
- priv->size, 0x100,
- NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL,
+ priv->size, 0x100,
+ NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -284,26 +295,26 @@ nvc0_gr_context_ctor(struct nouveau_object *parent,
* fuc to modify some per-context register settings on first load
* of the context.
*/
- ret = nouveau_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0,
- &chan->mmio);
+ ret = nvkm_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0,
+ &chan->mmio);
if (ret)
return ret;
- ret = nouveau_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm,
- NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
- &chan->mmio_vma);
+ ret = nvkm_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm,
+ NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
+ &chan->mmio_vma);
if (ret)
return ret;
/* allocate buffers referenced by mmio list */
for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) {
- ret = nouveau_gpuobj_new(nv_object(chan), NULL, data->size,
- data->align, 0, &chan->data[i].mem);
+ ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size,
+ data->align, 0, &chan->data[i].mem);
if (ret)
return ret;
- ret = nouveau_gpuobj_map_vm(chan->data[i].mem, vm, data->access,
- &chan->data[i].vma);
+ ret = nvkm_gpuobj_map_vm(chan->data[i].mem, vm, data->access,
+ &chan->data[i].vma);
if (ret)
return ret;
@@ -347,28 +358,28 @@ nvc0_gr_context_ctor(struct nouveau_object *parent,
}
void
-nvc0_gr_context_dtor(struct nouveau_object *object)
+gf100_gr_context_dtor(struct nvkm_object *object)
{
- struct nvc0_gr_chan *chan = (void *)object;
+ struct gf100_gr_chan *chan = (void *)object;
int i;
for (i = 0; i < ARRAY_SIZE(chan->data); i++) {
- nouveau_gpuobj_unmap(&chan->data[i].vma);
- nouveau_gpuobj_ref(NULL, &chan->data[i].mem);
+ nvkm_gpuobj_unmap(&chan->data[i].vma);
+ nvkm_gpuobj_ref(NULL, &chan->data[i].mem);
}
- nouveau_gpuobj_unmap(&chan->mmio_vma);
- nouveau_gpuobj_ref(NULL, &chan->mmio);
+ nvkm_gpuobj_unmap(&chan->mmio_vma);
+ nvkm_gpuobj_ref(NULL, &chan->mmio);
- nouveau_gr_context_destroy(&chan->base);
+ nvkm_gr_context_destroy(&chan->base);
}
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_gr_init
-nvc0_gr_init_main_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x00006fe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
@@ -383,53 +394,53 @@ nvc0_gr_init_main_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_fe_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_fe_0[] = {
{ 0x40415c, 1, 0x04, 0x00000000 },
{ 0x404170, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_pri_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_pri_0[] = {
{ 0x404488, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_rstr2d_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_rstr2d_0[] = {
{ 0x407808, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_pd_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_pd_0[] = {
{ 0x406024, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_ds_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405908, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_scc_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_scc_0[] = {
{ 0x40803c, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_prop_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_prop_0[] = {
{ 0x4184a0, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_gpc_unk_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_gpc_unk_0[] = {
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x80000000 },
@@ -437,20 +448,20 @@ nvc0_gr_init_gpc_unk_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_setup_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_setup_0[] = {
{ 0x418814, 3, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_crstr_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_crstr_0[] = {
{ 0x418b04, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_setup_1[] = {
+const struct gf100_gr_init
+gf100_gr_init_setup_1[] = {
{ 0x4188c8, 1, 0x04, 0x80000000 },
{ 0x4188cc, 1, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
@@ -458,8 +469,8 @@ nvc0_gr_init_setup_1[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_zcull_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_zcull_0[] = {
{ 0x418910, 1, 0x04, 0x00010001 },
{ 0x418914, 1, 0x04, 0x00000301 },
{ 0x418918, 1, 0x04, 0x00800000 },
@@ -468,15 +479,15 @@ nvc0_gr_init_zcull_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_gpm_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_gpm_0[] = {
{ 0x418c04, 1, 0x04, 0x00000000 },
{ 0x418c88, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_gpc_unk_1[] = {
+const struct gf100_gr_init
+gf100_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000050 },
@@ -484,30 +495,30 @@ nvc0_gr_init_gpc_unk_1[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_gcc_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_gcc_0[] = {
{ 0x41900c, 1, 0x04, 0x00000000 },
{ 0x419018, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_tpccs_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_tpccs_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_tex_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_pe_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_pe_0[] = {
{ 0x41980c, 3, 0x04, 0x00000000 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc5 },
@@ -515,8 +526,8 @@ nvc0_gr_init_pe_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_l1c_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x80000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
@@ -526,27 +537,27 @@ nvc0_gr_init_l1c_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_wwdx_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_wwdx_0[] = {
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_tpccs_1[] = {
+const struct gf100_gr_init
+gf100_gr_init_tpccs_1[] = {
{ 0x419d2c, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_mpc_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_mpc_0[] = {
{ 0x419c0c, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
-nvc0_gr_init_sm_0[] = {
+static const struct gf100_gr_init
+gf100_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@@ -563,8 +574,8 @@ nvc0_gr_init_sm_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_be_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_be_0[] = {
{ 0x40880c, 1, 0x04, 0x00000000 },
{ 0x408910, 9, 0x04, 0x00000000 },
{ 0x408950, 1, 0x04, 0x00000000 },
@@ -575,47 +586,47 @@ nvc0_gr_init_be_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_fe_1[] = {
+const struct gf100_gr_init
+gf100_gr_init_fe_1[] = {
{ 0x4040f0, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_pe_1[] = {
+const struct gf100_gr_init
+gf100_gr_init_pe_1[] = {
{ 0x419880, 1, 0x04, 0x00000002 },
{}
};
-static const struct nvc0_gr_pack
-nvc0_gr_pack_mmio[] = {
- { nvc0_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvc0_gr_init_pd_0 },
- { nvc0_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvc0_gr_init_prop_0 },
- { nvc0_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc0_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvc0_gr_init_gpm_0 },
- { nvc0_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nvc0_gr_init_tpccs_0 },
- { nvc0_gr_init_tex_0 },
- { nvc0_gr_init_pe_0 },
- { nvc0_gr_init_l1c_0 },
- { nvc0_gr_init_wwdx_0 },
- { nvc0_gr_init_tpccs_1 },
- { nvc0_gr_init_mpc_0 },
- { nvc0_gr_init_sm_0 },
- { nvc0_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
- { nvc0_gr_init_pe_1 },
+static const struct gf100_gr_pack
+gf100_gr_pack_mmio[] = {
+ { gf100_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf100_gr_init_pd_0 },
+ { gf100_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gf100_gr_init_prop_0 },
+ { gf100_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf100_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf100_gr_init_gpm_0 },
+ { gf100_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gf100_gr_init_tpccs_0 },
+ { gf100_gr_init_tex_0 },
+ { gf100_gr_init_pe_0 },
+ { gf100_gr_init_l1c_0 },
+ { gf100_gr_init_wwdx_0 },
+ { gf100_gr_init_tpccs_1 },
+ { gf100_gr_init_mpc_0 },
+ { gf100_gr_init_sm_0 },
+ { gf100_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
+ { gf100_gr_init_pe_1 },
{}
};
@@ -624,7 +635,7 @@ nvc0_gr_pack_mmio[] = {
******************************************************************************/
void
-nvc0_gr_zbc_init(struct nvc0_gr_priv *priv)
+gf100_gr_zbc_init(struct gf100_gr_priv *priv)
{
const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000 };
@@ -634,29 +645,29 @@ nvc0_gr_zbc_init(struct nvc0_gr_priv *priv)
0x00000000, 0x00000000, 0x00000000, 0x00000000 };
const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
- struct nouveau_ltc *ltc = nouveau_ltc(priv);
+ struct nvkm_ltc *ltc = nvkm_ltc(priv);
int index;
if (!priv->zbc_color[0].format) {
- nvc0_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]);
- nvc0_gr_zbc_color_get(priv, 2, & one[0], &one[4]);
- nvc0_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]);
- nvc0_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]);
- nvc0_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000);
- nvc0_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000);
+ gf100_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]);
+ gf100_gr_zbc_color_get(priv, 2, & one[0], &one[4]);
+ gf100_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]);
+ gf100_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]);
+ gf100_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000);
+ gf100_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000);
}
for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
- nvc0_gr_zbc_clear_color(priv, index);
+ gf100_gr_zbc_clear_color(priv, index);
for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
- nvc0_gr_zbc_clear_depth(priv, index);
+ gf100_gr_zbc_clear_depth(priv, index);
}
void
-nvc0_gr_mmio(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
+gf100_gr_mmio(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
{
- const struct nvc0_gr_pack *pack;
- const struct nvc0_gr_init *init;
+ const struct gf100_gr_pack *pack;
+ const struct gf100_gr_init *init;
pack_for_each_init(init, pack, p) {
u32 next = init->addr + init->count * init->pitch;
@@ -669,10 +680,10 @@ nvc0_gr_mmio(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
}
void
-nvc0_gr_icmd(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
+gf100_gr_icmd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
{
- const struct nvc0_gr_pack *pack;
- const struct nvc0_gr_init *init;
+ const struct gf100_gr_pack *pack;
+ const struct gf100_gr_init *init;
u32 data = 0;
nv_wr32(priv, 0x400208, 0x80000000);
@@ -697,10 +708,10 @@ nvc0_gr_icmd(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
}
void
-nvc0_gr_mthd(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
+gf100_gr_mthd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
{
- const struct nvc0_gr_pack *pack;
- const struct nvc0_gr_init *init;
+ const struct gf100_gr_pack *pack;
+ const struct gf100_gr_init *init;
u32 data = 0;
pack_for_each_init(init, pack, p) {
@@ -721,9 +732,9 @@ nvc0_gr_mthd(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
}
u64
-nvc0_gr_units(struct nouveau_gr *gr)
+gf100_gr_units(struct nvkm_gr *gr)
{
- struct nvc0_gr_priv *priv = (void *)gr;
+ struct gf100_gr_priv *priv = (void *)gr;
u64 cfg;
cfg = (u32)priv->gpc_nr;
@@ -733,7 +744,7 @@ nvc0_gr_units(struct nouveau_gr *gr)
return cfg;
}
-static const struct nouveau_enum nve0_sked_error[] = {
+static const struct nvkm_enum gk104_sked_error[] = {
{ 7, "CONSTANT_BUFFER_SIZE" },
{ 9, "LOCAL_MEMORY_SIZE_POS" },
{ 10, "LOCAL_MEMORY_SIZE_NEG" },
@@ -748,7 +759,7 @@ static const struct nouveau_enum nve0_sked_error[] = {
{}
};
-static const struct nouveau_enum nvc0_gpc_rop_error[] = {
+static const struct nvkm_enum gf100_gpc_rop_error[] = {
{ 1, "RT_PITCH_OVERRUN" },
{ 4, "RT_WIDTH_OVERRUN" },
{ 5, "RT_HEIGHT_OVERRUN" },
@@ -759,7 +770,7 @@ static const struct nouveau_enum nvc0_gpc_rop_error[] = {
};
static void
-nvc0_gr_trap_gpc_rop(struct nvc0_gr_priv *priv, int gpc)
+gf100_gr_trap_gpc_rop(struct gf100_gr_priv *priv, int gpc)
{
u32 trap[4];
int i;
@@ -774,7 +785,7 @@ nvc0_gr_trap_gpc_rop(struct nvc0_gr_priv *priv, int gpc)
if (!(trap[0] & (1 << i)))
continue;
pr_cont(" ");
- nouveau_enum_print(nvc0_gpc_rop_error, i);
+ nvkm_enum_print(gf100_gpc_rop_error, i);
}
pr_cont("\n");
@@ -784,7 +795,7 @@ nvc0_gr_trap_gpc_rop(struct nvc0_gr_priv *priv, int gpc)
nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
}
-static const struct nouveau_enum nvc0_mp_warp_error[] = {
+static const struct nvkm_enum gf100_mp_warp_error[] = {
{ 0x00, "NO_ERROR" },
{ 0x01, "STACK_MISMATCH" },
{ 0x05, "MISALIGNED_PC" },
@@ -797,23 +808,23 @@ static const struct nouveau_enum nvc0_mp_warp_error[] = {
{}
};
-static const struct nouveau_bitfield nvc0_mp_global_error[] = {
+static const struct nvkm_bitfield gf100_mp_global_error[] = {
{ 0x00000004, "MULTIPLE_WARP_ERRORS" },
{ 0x00000008, "OUT_OF_STACK_SPACE" },
{}
};
static void
-nvc0_gr_trap_mp(struct nvc0_gr_priv *priv, int gpc, int tpc)
+gf100_gr_trap_mp(struct gf100_gr_priv *priv, int gpc, int tpc)
{
u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648));
u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650));
nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc);
- nouveau_bitfield_print(nvc0_mp_global_error, gerr);
+ nvkm_bitfield_print(gf100_mp_global_error, gerr);
if (werr) {
pr_cont(" ");
- nouveau_enum_print(nvc0_mp_warp_error, werr & 0xffff);
+ nvkm_enum_print(gf100_mp_warp_error, werr & 0xffff);
}
pr_cont("\n");
@@ -822,7 +833,7 @@ nvc0_gr_trap_mp(struct nvc0_gr_priv *priv, int gpc, int tpc)
}
static void
-nvc0_gr_trap_tpc(struct nvc0_gr_priv *priv, int gpc, int tpc)
+gf100_gr_trap_tpc(struct gf100_gr_priv *priv, int gpc, int tpc)
{
u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508));
@@ -834,7 +845,7 @@ nvc0_gr_trap_tpc(struct nvc0_gr_priv *priv, int gpc, int tpc)
}
if (stat & 0x00000002) {
- nvc0_gr_trap_mp(priv, gpc, tpc);
+ gf100_gr_trap_mp(priv, gpc, tpc);
stat &= ~0x00000002;
}
@@ -858,13 +869,13 @@ nvc0_gr_trap_tpc(struct nvc0_gr_priv *priv, int gpc, int tpc)
}
static void
-nvc0_gr_trap_gpc(struct nvc0_gr_priv *priv, int gpc)
+gf100_gr_trap_gpc(struct gf100_gr_priv *priv, int gpc)
{
u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90));
int tpc;
if (stat & 0x00000001) {
- nvc0_gr_trap_gpc_rop(priv, gpc);
+ gf100_gr_trap_gpc_rop(priv, gpc);
stat &= ~0x00000001;
}
@@ -892,7 +903,7 @@ nvc0_gr_trap_gpc(struct nvc0_gr_priv *priv, int gpc)
for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
u32 mask = 0x00010000 << tpc;
if (stat & mask) {
- nvc0_gr_trap_tpc(priv, gpc, tpc);
+ gf100_gr_trap_tpc(priv, gpc, tpc);
nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask);
stat &= ~mask;
}
@@ -904,7 +915,7 @@ nvc0_gr_trap_gpc(struct nvc0_gr_priv *priv, int gpc)
}
static void
-nvc0_gr_trap_intr(struct nvc0_gr_priv *priv)
+gf100_gr_trap_intr(struct gf100_gr_priv *priv)
{
u32 trap = nv_rd32(priv, 0x400108);
int rop, gpc, i;
@@ -965,7 +976,7 @@ nvc0_gr_trap_intr(struct nvc0_gr_priv *priv)
if (!(stat & (1 << i)))
continue;
pr_cont(" ");
- nouveau_enum_print(nve0_sked_error, i);
+ nvkm_enum_print(gk104_sked_error, i);
}
pr_cont("\n");
@@ -980,7 +991,7 @@ nvc0_gr_trap_intr(struct nvc0_gr_priv *priv)
for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) {
u32 mask = 0x00000001 << gpc;
if (stat & mask) {
- nvc0_gr_trap_gpc(priv, gpc);
+ gf100_gr_trap_gpc(priv, gpc);
nv_wr32(priv, 0x400118, mask);
stat &= ~mask;
}
@@ -1009,7 +1020,7 @@ nvc0_gr_trap_intr(struct nvc0_gr_priv *priv)
}
static void
-nvc0_gr_ctxctl_debug_unit(struct nvc0_gr_priv *priv, u32 base)
+gf100_gr_ctxctl_debug_unit(struct gf100_gr_priv *priv, u32 base)
{
nv_error(priv, "%06x - done 0x%08x\n", base,
nv_rd32(priv, base + 0x400));
@@ -1022,18 +1033,18 @@ nvc0_gr_ctxctl_debug_unit(struct nvc0_gr_priv *priv, u32 base)
}
void
-nvc0_gr_ctxctl_debug(struct nvc0_gr_priv *priv)
+gf100_gr_ctxctl_debug(struct gf100_gr_priv *priv)
{
u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff;
u32 gpc;
- nvc0_gr_ctxctl_debug_unit(priv, 0x409000);
+ gf100_gr_ctxctl_debug_unit(priv, 0x409000);
for (gpc = 0; gpc < gpcnr; gpc++)
- nvc0_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
+ gf100_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
}
static void
-nvc0_gr_ctxctl_isr(struct nvc0_gr_priv *priv)
+gf100_gr_ctxctl_isr(struct gf100_gr_priv *priv)
{
u32 stat = nv_rd32(priv, 0x409c18);
@@ -1059,26 +1070,26 @@ nvc0_gr_ctxctl_isr(struct nvc0_gr_priv *priv)
if (stat & 0x00080000) {
nv_error(priv, "FECS watchdog timeout\n");
- nvc0_gr_ctxctl_debug(priv);
+ gf100_gr_ctxctl_debug(priv);
nv_wr32(priv, 0x409c20, 0x00080000);
stat &= ~0x00080000;
}
if (stat) {
nv_error(priv, "FECS 0x%08x\n", stat);
- nvc0_gr_ctxctl_debug(priv);
+ gf100_gr_ctxctl_debug(priv);
nv_wr32(priv, 0x409c20, stat);
}
}
static void
-nvc0_gr_intr(struct nouveau_subdev *subdev)
+gf100_gr_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
- struct nouveau_engine *engine = nv_engine(subdev);
- struct nouveau_object *engctx;
- struct nouveau_handle *handle;
- struct nvc0_gr_priv *priv = (void *)subdev;
+ struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
+ struct nvkm_engine *engine = nv_engine(subdev);
+ struct nvkm_object *engctx;
+ struct nvkm_handle *handle;
+ struct gf100_gr_priv *priv = (void *)subdev;
u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff;
u32 stat = nv_rd32(priv, 0x400100);
u32 addr = nv_rd32(priv, 0x400704);
@@ -1089,18 +1100,18 @@ nvc0_gr_intr(struct nouveau_subdev *subdev)
u32 class = nv_rd32(priv, 0x404200 + (subc * 4));
int chid;
- engctx = nouveau_engctx_get(engine, inst);
+ engctx = nvkm_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
if (stat & 0x00000010) {
- handle = nouveau_handle_get_class(engctx, class);
+ handle = nvkm_handle_get_class(engctx, class);
if (!handle || nv_call(handle->object, mthd, data)) {
nv_error(priv,
"ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, inst << 12, nouveau_client_name(engctx),
+ chid, inst << 12, nvkm_client_name(engctx),
subc, class, mthd, data);
}
- nouveau_handle_put(handle);
+ nvkm_handle_put(handle);
nv_wr32(priv, 0x400100, 0x00000010);
stat &= ~0x00000010;
}
@@ -1108,7 +1119,7 @@ nvc0_gr_intr(struct nouveau_subdev *subdev)
if (stat & 0x00000020) {
nv_error(priv,
"ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, inst << 12, nouveau_client_name(engctx), subc,
+ chid, inst << 12, nvkm_client_name(engctx), subc,
class, mthd, data);
nv_wr32(priv, 0x400100, 0x00000020);
stat &= ~0x00000020;
@@ -1116,9 +1127,9 @@ nvc0_gr_intr(struct nouveau_subdev *subdev)
if (stat & 0x00100000) {
nv_error(priv, "DATA_ERROR [");
- nouveau_enum_print(nv50_data_error_names, code);
+ nvkm_enum_print(nv50_data_error_names, code);
pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, inst << 12, nouveau_client_name(engctx), subc,
+ chid, inst << 12, nvkm_client_name(engctx), subc,
class, mthd, data);
nv_wr32(priv, 0x400100, 0x00100000);
stat &= ~0x00100000;
@@ -1126,14 +1137,14 @@ nvc0_gr_intr(struct nouveau_subdev *subdev)
if (stat & 0x00200000) {
nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
- nouveau_client_name(engctx));
- nvc0_gr_trap_intr(priv);
+ nvkm_client_name(engctx));
+ gf100_gr_trap_intr(priv);
nv_wr32(priv, 0x400100, 0x00200000);
stat &= ~0x00200000;
}
if (stat & 0x00080000) {
- nvc0_gr_ctxctl_isr(priv);
+ gf100_gr_ctxctl_isr(priv);
nv_wr32(priv, 0x400100, 0x00080000);
stat &= ~0x00080000;
}
@@ -1144,12 +1155,12 @@ nvc0_gr_intr(struct nouveau_subdev *subdev)
}
nv_wr32(priv, 0x400500, 0x00010001);
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
void
-nvc0_gr_init_fw(struct nvc0_gr_priv *priv, u32 fuc_base,
- struct nvc0_gr_fuc *code, struct nvc0_gr_fuc *data)
+gf100_gr_init_fw(struct gf100_gr_priv *priv, u32 fuc_base,
+ struct gf100_gr_fuc *code, struct gf100_gr_fuc *data)
{
int i;
@@ -1170,12 +1181,12 @@ nvc0_gr_init_fw(struct nvc0_gr_priv *priv, u32 fuc_base,
}
static void
-nvc0_gr_init_csdata(struct nvc0_gr_priv *priv,
- const struct nvc0_gr_pack *pack,
- u32 falcon, u32 starstar, u32 base)
+gf100_gr_init_csdata(struct gf100_gr_priv *priv,
+ const struct gf100_gr_pack *pack,
+ u32 falcon, u32 starstar, u32 base)
{
- const struct nvc0_gr_pack *iter;
- const struct nvc0_gr_init *init;
+ const struct gf100_gr_pack *iter;
+ const struct gf100_gr_init *init;
u32 addr = ~0, prev = ~0, xfer = 0;
u32 star, temp;
@@ -1211,20 +1222,20 @@ nvc0_gr_init_csdata(struct nvc0_gr_priv *priv,
}
int
-nvc0_gr_init_ctxctl(struct nvc0_gr_priv *priv)
+gf100_gr_init_ctxctl(struct gf100_gr_priv *priv)
{
- struct nvc0_gr_oclass *oclass = (void *)nv_object(priv)->oclass;
- struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_gr_oclass *oclass = (void *)nv_object(priv)->oclass;
+ struct gf100_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
int i;
if (priv->firmware) {
/* load fuc microcode */
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
- nvc0_gr_init_fw(priv, 0x409000, &priv->fuc409c,
- &priv->fuc409d);
- nvc0_gr_init_fw(priv, 0x41a000, &priv->fuc41ac,
- &priv->fuc41ad);
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
+ gf100_gr_init_fw(priv, 0x409000, &priv->fuc409c,
+ &priv->fuc409d);
+ gf100_gr_init_fw(priv, 0x41a000, &priv->fuc41ac,
+ &priv->fuc41ad);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
/* start both of them running */
nv_wr32(priv, 0x409840, 0xffffffff);
@@ -1297,7 +1308,7 @@ nvc0_gr_init_ctxctl(struct nvc0_gr_priv *priv)
}
if (priv->data == NULL) {
- int ret = nvc0_grctx_generate(priv);
+ int ret = gf100_grctx_generate(priv);
if (ret) {
nv_error(priv, "failed to construct context\n");
return ret;
@@ -1311,7 +1322,7 @@ nvc0_gr_init_ctxctl(struct nvc0_gr_priv *priv)
}
/* load HUB microcode */
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
nv_wr32(priv, 0x4091c0, 0x01000000);
for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++)
nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]);
@@ -1334,26 +1345,26 @@ nvc0_gr_init_ctxctl(struct nvc0_gr_priv *priv)
nv_wr32(priv, 0x41a188, i >> 6);
nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]);
}
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
/* load register lists */
- nvc0_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000);
- nvc0_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000);
- nvc0_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800);
- nvc0_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00);
+ gf100_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000);
+ gf100_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000);
+ gf100_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800);
+ gf100_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00);
/* start HUB ucode running, it'll init the GPCs */
nv_wr32(priv, 0x40910c, 0x00000000);
nv_wr32(priv, 0x409100, 0x00000002);
if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
nv_error(priv, "HUB_INIT timed out\n");
- nvc0_gr_ctxctl_debug(priv);
+ gf100_gr_ctxctl_debug(priv);
return -EBUSY;
}
priv->size = nv_rd32(priv, 0x409804);
if (priv->data == NULL) {
- int ret = nvc0_grctx_generate(priv);
+ int ret = gf100_grctx_generate(priv);
if (ret) {
nv_error(priv, "failed to construct context\n");
return ret;
@@ -1364,17 +1375,17 @@ nvc0_gr_init_ctxctl(struct nvc0_gr_priv *priv)
}
int
-nvc0_gr_init(struct nouveau_object *object)
+gf100_gr_init(struct nvkm_object *object)
{
- struct nvc0_gr_oclass *oclass = (void *)object->oclass;
- struct nvc0_gr_priv *priv = (void *)object;
+ struct gf100_gr_oclass *oclass = (void *)object->oclass;
+ struct gf100_gr_priv *priv = (void *)object;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, rop;
int ret, i;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -1387,7 +1398,7 @@ nvc0_gr_init(struct nouveau_object *object)
nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
- nvc0_gr_mmio(priv, oclass->mmio);
+ gf100_gr_mmio(priv, oclass->mmio);
memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
@@ -1470,23 +1481,23 @@ nvc0_gr_init(struct nouveau_object *object)
nv_wr32(priv, 0x400054, 0x34ce3464);
- nvc0_gr_zbc_init(priv);
+ gf100_gr_zbc_init(priv);
- return nvc0_gr_init_ctxctl(priv);
+ return gf100_gr_init_ctxctl(priv);
}
static void
-nvc0_gr_dtor_fw(struct nvc0_gr_fuc *fuc)
+gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc)
{
kfree(fuc->data);
fuc->data = NULL;
}
int
-nvc0_gr_ctor_fw(struct nvc0_gr_priv *priv, const char *fwname,
- struct nvc0_gr_fuc *fuc)
+gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname,
+ struct gf100_gr_fuc *fuc)
{
- struct nouveau_device *device = nv_device(priv);
+ struct nvkm_device *device = nv_device(priv);
const struct firmware *fw;
char f[32];
int ret;
@@ -1509,65 +1520,65 @@ nvc0_gr_ctor_fw(struct nvc0_gr_priv *priv, const char *fwname,
}
void
-nvc0_gr_dtor(struct nouveau_object *object)
+gf100_gr_dtor(struct nvkm_object *object)
{
- struct nvc0_gr_priv *priv = (void *)object;
+ struct gf100_gr_priv *priv = (void *)object;
kfree(priv->data);
- nvc0_gr_dtor_fw(&priv->fuc409c);
- nvc0_gr_dtor_fw(&priv->fuc409d);
- nvc0_gr_dtor_fw(&priv->fuc41ac);
- nvc0_gr_dtor_fw(&priv->fuc41ad);
+ gf100_gr_dtor_fw(&priv->fuc409c);
+ gf100_gr_dtor_fw(&priv->fuc409d);
+ gf100_gr_dtor_fw(&priv->fuc41ac);
+ gf100_gr_dtor_fw(&priv->fuc41ad);
- nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
- nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
+ nvkm_gpuobj_ref(NULL, &priv->unk4188b8);
+ nvkm_gpuobj_ref(NULL, &priv->unk4188b4);
- nouveau_gr_destroy(&priv->base);
+ nvkm_gr_destroy(&priv->base);
}
int
-nvc0_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *bclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *bclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvc0_gr_oclass *oclass = (void *)bclass;
- struct nouveau_device *device = nv_device(parent);
- struct nvc0_gr_priv *priv;
+ struct gf100_gr_oclass *oclass = (void *)bclass;
+ struct nvkm_device *device = nv_device(parent);
+ struct gf100_gr_priv *priv;
bool use_ext_fw, enable;
int ret, i, j;
- use_ext_fw = nouveau_boolopt(device->cfgopt, "NvGrUseFW",
- oclass->fecs.ucode == NULL);
+ use_ext_fw = nvkm_boolopt(device->cfgopt, "NvGrUseFW",
+ oclass->fecs.ucode == NULL);
enable = use_ext_fw || oclass->fecs.ucode != NULL;
- ret = nouveau_gr_create(parent, engine, bclass, enable, &priv);
+ ret = nvkm_gr_create(parent, engine, bclass, enable, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x08001000;
- nv_subdev(priv)->intr = nvc0_gr_intr;
+ nv_subdev(priv)->intr = gf100_gr_intr;
- priv->base.units = nvc0_gr_units;
+ priv->base.units = gf100_gr_units;
if (use_ext_fw) {
nv_info(priv, "using external firmware\n");
- if (nvc0_gr_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
- nvc0_gr_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
- nvc0_gr_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
- nvc0_gr_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
+ if (gf100_gr_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
+ gf100_gr_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
+ gf100_gr_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
+ gf100_gr_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
return -ENODEV;
priv->firmware = true;
}
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
- &priv->unk4188b4);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
+ &priv->unk4188b4);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
- &priv->unk4188b8);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
+ &priv->unk4188b8);
if (ret)
return ret;
@@ -1630,38 +1641,38 @@ nvc0_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-#include "fuc/hubnvc0.fuc3.h"
+#include "fuc/hubgf100.fuc3.h"
-struct nvc0_gr_ucode
-nvc0_gr_fecs_ucode = {
- .code.data = nvc0_grhub_code,
- .code.size = sizeof(nvc0_grhub_code),
- .data.data = nvc0_grhub_data,
- .data.size = sizeof(nvc0_grhub_data),
+struct gf100_gr_ucode
+gf100_gr_fecs_ucode = {
+ .code.data = gf100_grhub_code,
+ .code.size = sizeof(gf100_grhub_code),
+ .data.data = gf100_grhub_data,
+ .data.size = sizeof(gf100_grhub_data),
};
-#include "fuc/gpcnvc0.fuc3.h"
+#include "fuc/gpcgf100.fuc3.h"
-struct nvc0_gr_ucode
-nvc0_gr_gpccs_ucode = {
- .code.data = nvc0_grgpc_code,
- .code.size = sizeof(nvc0_grgpc_code),
- .data.data = nvc0_grgpc_data,
- .data.size = sizeof(nvc0_grgpc_data),
+struct gf100_gr_ucode
+gf100_gr_gpccs_ucode = {
+ .code.data = gf100_grgpc_code,
+ .code.size = sizeof(gf100_grgpc_code),
+ .data.data = gf100_grgpc_data,
+ .data.size = sizeof(gf100_grgpc_data),
};
-struct nouveau_oclass *
-nvc0_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gf100_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nvc0_gr_init,
- .fini = _nouveau_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gf100_gr_init,
+ .fini = _nvkm_gr_fini,
},
- .cclass = &nvc0_grctx_oclass,
- .sclass = nvc0_gr_sclass,
- .mmio = nvc0_gr_pack_mmio,
- .fecs.ucode = &nvc0_gr_fecs_ucode,
- .gpccs.ucode = &nvc0_gr_gpccs_ucode,
+ .cclass = &gf100_grctx_oclass,
+ .sclass = gf100_gr_sclass,
+ .mmio = gf100_gr_pack_mmio,
+ .fecs.ucode = &gf100_gr_fecs_ucode,
+ .gpccs.ucode = &gf100_gr_gpccs_ucode,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
new file mode 100644
index 000000000000..aeeca1be9cf0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
@@ -0,0 +1,250 @@
+/*
+ * Copyright 2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+#ifndef __NVC0_GR_H__
+#define __NVC0_GR_H__
+#include <engine/gr.h>
+
+#include <subdev/ltc.h>
+
+#define GPC_MAX 32
+#define TPC_MAX (GPC_MAX * 8)
+
+#define ROP_BCAST(r) (0x408800 + (r))
+#define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r))
+#define GPC_BCAST(r) (0x418000 + (r))
+#define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r))
+#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r))
+#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
+
+struct gf100_gr_data {
+ u32 size;
+ u32 align;
+ u32 access;
+};
+
+struct gf100_gr_mmio {
+ u32 addr;
+ u32 data;
+ u32 shift;
+ int buffer;
+};
+
+struct gf100_gr_fuc {
+ u32 *data;
+ u32 size;
+};
+
+struct gf100_gr_zbc_color {
+ u32 format;
+ u32 ds[4];
+ u32 l2[4];
+};
+
+struct gf100_gr_zbc_depth {
+ u32 format;
+ u32 ds;
+ u32 l2;
+};
+
+struct gf100_gr_priv {
+ struct nvkm_gr base;
+
+ struct gf100_gr_fuc fuc409c;
+ struct gf100_gr_fuc fuc409d;
+ struct gf100_gr_fuc fuc41ac;
+ struct gf100_gr_fuc fuc41ad;
+ bool firmware;
+
+ struct gf100_gr_zbc_color zbc_color[NVKM_LTC_MAX_ZBC_CNT];
+ struct gf100_gr_zbc_depth zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
+
+ u8 rop_nr;
+ u8 gpc_nr;
+ u8 tpc_nr[GPC_MAX];
+ u8 tpc_total;
+ u8 ppc_nr[GPC_MAX];
+ u8 ppc_tpc_nr[GPC_MAX][4];
+
+ struct nvkm_gpuobj *unk4188b4;
+ struct nvkm_gpuobj *unk4188b8;
+
+ struct gf100_gr_data mmio_data[4];
+ struct gf100_gr_mmio mmio_list[4096/8];
+ u32 size;
+ u32 *data;
+
+ u8 magic_not_rop_nr;
+};
+
+struct gf100_gr_chan {
+ struct nvkm_gr_chan base;
+
+ struct nvkm_gpuobj *mmio;
+ struct nvkm_vma mmio_vma;
+ int mmio_nr;
+ struct {
+ struct nvkm_gpuobj *mem;
+ struct nvkm_vma vma;
+ } data[4];
+};
+
+int gf100_gr_context_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void gf100_gr_context_dtor(struct nvkm_object *);
+
+void gf100_gr_ctxctl_debug(struct gf100_gr_priv *);
+
+u64 gf100_gr_units(struct nvkm_gr *);
+int gf100_gr_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *data, u32 size,
+ struct nvkm_object **);
+void gf100_gr_dtor(struct nvkm_object *);
+int gf100_gr_init(struct nvkm_object *);
+void gf100_gr_zbc_init(struct gf100_gr_priv *);
+
+int gk104_gr_fini(struct nvkm_object *, bool);
+int gk104_gr_init(struct nvkm_object *);
+
+int gk110_gr_fini(struct nvkm_object *, bool);
+
+extern struct nvkm_ofuncs gf100_fermi_ofuncs;
+
+extern struct nvkm_oclass gf100_gr_sclass[];
+extern struct nvkm_omthds gf100_gr_9097_omthds[];
+extern struct nvkm_omthds gf100_gr_90c0_omthds[];
+extern struct nvkm_oclass gf110_gr_sclass[];
+extern struct nvkm_oclass gk110_gr_sclass[];
+
+struct gf100_gr_init {
+ u32 addr;
+ u8 count;
+ u8 pitch;
+ u32 data;
+};
+
+struct gf100_gr_pack {
+ const struct gf100_gr_init *init;
+ u32 type;
+};
+
+#define pack_for_each_init(init, pack, head) \
+ for (pack = head; pack && pack->init; pack++) \
+ for (init = pack->init; init && init->count; init++)
+
+struct gf100_gr_ucode {
+ struct gf100_gr_fuc code;
+ struct gf100_gr_fuc data;
+};
+
+extern struct gf100_gr_ucode gf100_gr_fecs_ucode;
+extern struct gf100_gr_ucode gf100_gr_gpccs_ucode;
+
+extern struct gf100_gr_ucode gk110_gr_fecs_ucode;
+extern struct gf100_gr_ucode gk110_gr_gpccs_ucode;
+
+struct gf100_gr_oclass {
+ struct nvkm_oclass base;
+ struct nvkm_oclass **cclass;
+ struct nvkm_oclass *sclass;
+ const struct gf100_gr_pack *mmio;
+ struct {
+ struct gf100_gr_ucode *ucode;
+ } fecs;
+ struct {
+ struct gf100_gr_ucode *ucode;
+ } gpccs;
+ int ppc_nr;
+};
+
+void gf100_gr_mmio(struct gf100_gr_priv *, const struct gf100_gr_pack *);
+void gf100_gr_icmd(struct gf100_gr_priv *, const struct gf100_gr_pack *);
+void gf100_gr_mthd(struct gf100_gr_priv *, const struct gf100_gr_pack *);
+int gf100_gr_init_ctxctl(struct gf100_gr_priv *);
+
+/* register init value lists */
+
+extern const struct gf100_gr_init gf100_gr_init_main_0[];
+extern const struct gf100_gr_init gf100_gr_init_fe_0[];
+extern const struct gf100_gr_init gf100_gr_init_pri_0[];
+extern const struct gf100_gr_init gf100_gr_init_rstr2d_0[];
+extern const struct gf100_gr_init gf100_gr_init_pd_0[];
+extern const struct gf100_gr_init gf100_gr_init_ds_0[];
+extern const struct gf100_gr_init gf100_gr_init_scc_0[];
+extern const struct gf100_gr_init gf100_gr_init_prop_0[];
+extern const struct gf100_gr_init gf100_gr_init_gpc_unk_0[];
+extern const struct gf100_gr_init gf100_gr_init_setup_0[];
+extern const struct gf100_gr_init gf100_gr_init_crstr_0[];
+extern const struct gf100_gr_init gf100_gr_init_setup_1[];
+extern const struct gf100_gr_init gf100_gr_init_zcull_0[];
+extern const struct gf100_gr_init gf100_gr_init_gpm_0[];
+extern const struct gf100_gr_init gf100_gr_init_gpc_unk_1[];
+extern const struct gf100_gr_init gf100_gr_init_gcc_0[];
+extern const struct gf100_gr_init gf100_gr_init_tpccs_0[];
+extern const struct gf100_gr_init gf100_gr_init_tex_0[];
+extern const struct gf100_gr_init gf100_gr_init_pe_0[];
+extern const struct gf100_gr_init gf100_gr_init_l1c_0[];
+extern const struct gf100_gr_init gf100_gr_init_wwdx_0[];
+extern const struct gf100_gr_init gf100_gr_init_tpccs_1[];
+extern const struct gf100_gr_init gf100_gr_init_mpc_0[];
+extern const struct gf100_gr_init gf100_gr_init_be_0[];
+extern const struct gf100_gr_init gf100_gr_init_fe_1[];
+extern const struct gf100_gr_init gf100_gr_init_pe_1[];
+
+extern const struct gf100_gr_init gf104_gr_init_ds_0[];
+extern const struct gf100_gr_init gf104_gr_init_tex_0[];
+extern const struct gf100_gr_init gf104_gr_init_sm_0[];
+
+extern const struct gf100_gr_init gf108_gr_init_gpc_unk_0[];
+extern const struct gf100_gr_init gf108_gr_init_setup_1[];
+
+extern const struct gf100_gr_init gf119_gr_init_pd_0[];
+extern const struct gf100_gr_init gf119_gr_init_ds_0[];
+extern const struct gf100_gr_init gf119_gr_init_prop_0[];
+extern const struct gf100_gr_init gf119_gr_init_gpm_0[];
+extern const struct gf100_gr_init gf119_gr_init_gpc_unk_1[];
+extern const struct gf100_gr_init gf119_gr_init_tex_0[];
+extern const struct gf100_gr_init gf119_gr_init_sm_0[];
+extern const struct gf100_gr_init gf119_gr_init_fe_1[];
+
+extern const struct gf100_gr_init gf117_gr_init_pes_0[];
+extern const struct gf100_gr_init gf117_gr_init_wwdx_0[];
+extern const struct gf100_gr_init gf117_gr_init_cbm_0[];
+
+extern const struct gf100_gr_init gk104_gr_init_main_0[];
+extern const struct gf100_gr_init gk104_gr_init_tpccs_0[];
+extern const struct gf100_gr_init gk104_gr_init_pe_0[];
+extern const struct gf100_gr_init gk104_gr_init_be_0[];
+extern const struct gf100_gr_pack gk104_gr_pack_mmio[];
+
+extern const struct gf100_gr_init gk110_gr_init_fe_0[];
+extern const struct gf100_gr_init gk110_gr_init_ds_0[];
+extern const struct gf100_gr_init gk110_gr_init_sked_0[];
+extern const struct gf100_gr_init gk110_gr_init_cwd_0[];
+extern const struct gf100_gr_init gk110_gr_init_gpc_unk_1[];
+extern const struct gf100_gr_init gk110_gr_init_tex_0[];
+extern const struct gf100_gr_init gk110_gr_init_sm_0[];
+
+extern const struct gf100_gr_init gk208_gr_init_gpc_unk_0[];
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
similarity index 65%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
index 0af6335efa50..20d3b85db3b5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
@@ -21,16 +21,15 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include "gf100.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_gr_init
-nvc4_gr_init_ds_0[] = {
+const struct gf100_gr_init
+gf104_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00002834 },
@@ -38,8 +37,8 @@ nvc4_gr_init_ds_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc4_gr_init_tex_0[] = {
+const struct gf100_gr_init
+gf104_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -47,8 +46,8 @@ nvc4_gr_init_tex_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvc4_gr_init_pe_0[] = {
+static const struct gf100_gr_init
+gf104_gr_init_pe_0[] = {
{ 0x41980c, 3, 0x04, 0x00000000 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc5 },
@@ -57,8 +56,8 @@ nvc4_gr_init_pe_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc4_gr_init_sm_0[] = {
+const struct gf100_gr_init
+gf104_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@@ -76,34 +75,34 @@ nvc4_gr_init_sm_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvc4_gr_pack_mmio[] = {
- { nvc0_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvc0_gr_init_pd_0 },
- { nvc4_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvc0_gr_init_prop_0 },
- { nvc0_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc0_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvc0_gr_init_gpm_0 },
- { nvc0_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nvc0_gr_init_tpccs_0 },
- { nvc4_gr_init_tex_0 },
- { nvc4_gr_init_pe_0 },
- { nvc0_gr_init_l1c_0 },
- { nvc0_gr_init_wwdx_0 },
- { nvc0_gr_init_tpccs_1 },
- { nvc0_gr_init_mpc_0 },
- { nvc4_gr_init_sm_0 },
- { nvc0_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
+static const struct gf100_gr_pack
+gf104_gr_pack_mmio[] = {
+ { gf100_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf100_gr_init_pd_0 },
+ { gf104_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gf100_gr_init_prop_0 },
+ { gf100_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf100_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf100_gr_init_gpm_0 },
+ { gf100_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gf100_gr_init_tpccs_0 },
+ { gf104_gr_init_tex_0 },
+ { gf104_gr_init_pe_0 },
+ { gf100_gr_init_l1c_0 },
+ { gf100_gr_init_wwdx_0 },
+ { gf100_gr_init_tpccs_1 },
+ { gf100_gr_init_mpc_0 },
+ { gf104_gr_init_sm_0 },
+ { gf100_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
{}
};
@@ -111,18 +110,18 @@ nvc4_gr_pack_mmio[] = {
* PGRAPH engine/subdev functions
******************************************************************************/
-struct nouveau_oclass *
-nvc4_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gf104_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xc3),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nvc0_gr_init,
- .fini = _nouveau_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gf100_gr_init,
+ .fini = _nvkm_gr_fini,
},
- .cclass = &nvc4_grctx_oclass,
- .sclass = nvc0_gr_sclass,
- .mmio = nvc4_gr_pack_mmio,
- .fecs.ucode = &nvc0_gr_fecs_ucode,
- .gpccs.ucode = &nvc0_gr_gpccs_ucode,
+ .cclass = &gf104_grctx_oclass,
+ .sclass = gf100_gr_sclass,
+ .mmio = gf104_gr_pack_mmio,
+ .fecs.ucode = &gf100_gr_fecs_ucode,
+ .gpccs.ucode = &gf100_gr_gpccs_ucode,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
similarity index 59%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
index 4a70ea30bae9..5362c8176e64 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
@@ -21,21 +21,22 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "gf100.h"
+#include "ctxgf100.h"
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <nvif/class.h>
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
-nvc1_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0x9039, &nouveau_object_ofuncs },
- { FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { FERMI_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
+static struct nvkm_oclass
+gf108_gr_sclass[] = {
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0x9039, &nvkm_object_ofuncs },
+ { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { FERMI_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{}
};
@@ -43,8 +44,8 @@ nvc1_gr_sclass[] = {
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_gr_init
-nvc1_gr_init_gpc_unk_0[] = {
+const struct gf100_gr_init
+gf108_gr_init_gpc_unk_0[] = {
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x00000000 },
@@ -52,16 +53,16 @@ nvc1_gr_init_gpc_unk_0[] = {
{}
};
-const struct nvc0_gr_init
-nvc1_gr_init_setup_1[] = {
+const struct gf100_gr_init
+gf108_gr_init_setup_1[] = {
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
{ 0x4188d4, 1, 0x04, 0x00000001 },
{}
};
-static const struct nvc0_gr_init
-nvc1_gr_init_gpc_unk_1[] = {
+static const struct gf100_gr_init
+gf108_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000003 },
@@ -69,8 +70,8 @@ nvc1_gr_init_gpc_unk_1[] = {
{}
};
-static const struct nvc0_gr_init
-nvc1_gr_init_pe_0[] = {
+static const struct gf100_gr_init
+gf108_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419810, 1, 0x04, 0x00000000 },
{ 0x419814, 1, 0x04, 0x00000004 },
@@ -81,34 +82,34 @@ nvc1_gr_init_pe_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvc1_gr_pack_mmio[] = {
- { nvc0_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvc0_gr_init_pd_0 },
- { nvc4_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvc0_gr_init_prop_0 },
- { nvc1_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvc0_gr_init_gpm_0 },
- { nvc1_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nvc0_gr_init_tpccs_0 },
- { nvc4_gr_init_tex_0 },
- { nvc1_gr_init_pe_0 },
- { nvc0_gr_init_l1c_0 },
- { nvc0_gr_init_wwdx_0 },
- { nvc0_gr_init_tpccs_1 },
- { nvc0_gr_init_mpc_0 },
- { nvc4_gr_init_sm_0 },
- { nvc0_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
+static const struct gf100_gr_pack
+gf108_gr_pack_mmio[] = {
+ { gf100_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf100_gr_init_pd_0 },
+ { gf104_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gf100_gr_init_prop_0 },
+ { gf108_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf100_gr_init_gpm_0 },
+ { gf108_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gf100_gr_init_tpccs_0 },
+ { gf104_gr_init_tex_0 },
+ { gf108_gr_init_pe_0 },
+ { gf100_gr_init_l1c_0 },
+ { gf100_gr_init_wwdx_0 },
+ { gf100_gr_init_tpccs_1 },
+ { gf100_gr_init_mpc_0 },
+ { gf104_gr_init_sm_0 },
+ { gf100_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
{}
};
@@ -116,18 +117,18 @@ nvc1_gr_pack_mmio[] = {
* PGRAPH engine/subdev functions
******************************************************************************/
-struct nouveau_oclass *
-nvc1_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gf108_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xc1),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nvc0_gr_init,
- .fini = _nouveau_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gf100_gr_init,
+ .fini = _nvkm_gr_fini,
},
- .cclass = &nvc1_grctx_oclass,
- .sclass = nvc1_gr_sclass,
- .mmio = nvc1_gr_pack_mmio,
- .fecs.ucode = &nvc0_gr_fecs_ucode,
- .gpccs.ucode = &nvc0_gr_gpccs_ucode,
+ .cclass = &gf108_grctx_oclass,
+ .sclass = gf108_gr_sclass,
+ .mmio = gf108_gr_pack_mmio,
+ .fecs.ucode = &gf100_gr_fecs_ucode,
+ .gpccs.ucode = &gf100_gr_gpccs_ucode,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
similarity index 58%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
index 692ee30855fb..88beb491b7b8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
@@ -21,22 +21,23 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "gf100.h"
+#include "ctxgf100.h"
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <nvif/class.h>
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-struct nouveau_oclass
-nvc8_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0x9039, &nouveau_object_ofuncs },
- { FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { FERMI_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { FERMI_C, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
+struct nvkm_oclass
+gf110_gr_sclass[] = {
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0x9039, &nvkm_object_ofuncs },
+ { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { FERMI_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { FERMI_C, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{}
};
@@ -44,8 +45,8 @@ nvc8_gr_sclass[] = {
* PGRAPH register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvc8_gr_init_sm_0[] = {
+static const struct gf100_gr_init
+gf110_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@@ -62,35 +63,35 @@ nvc8_gr_init_sm_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvc8_gr_pack_mmio[] = {
- { nvc0_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvc0_gr_init_pd_0 },
- { nvc0_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvc0_gr_init_prop_0 },
- { nvc0_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvc0_gr_init_gpm_0 },
- { nvc0_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nvc0_gr_init_tpccs_0 },
- { nvc0_gr_init_tex_0 },
- { nvc0_gr_init_pe_0 },
- { nvc0_gr_init_l1c_0 },
- { nvc0_gr_init_wwdx_0 },
- { nvc0_gr_init_tpccs_1 },
- { nvc0_gr_init_mpc_0 },
- { nvc8_gr_init_sm_0 },
- { nvc0_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
- { nvc0_gr_init_pe_1 },
+static const struct gf100_gr_pack
+gf110_gr_pack_mmio[] = {
+ { gf100_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf100_gr_init_pd_0 },
+ { gf100_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gf100_gr_init_prop_0 },
+ { gf100_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf100_gr_init_gpm_0 },
+ { gf100_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gf100_gr_init_tpccs_0 },
+ { gf100_gr_init_tex_0 },
+ { gf100_gr_init_pe_0 },
+ { gf100_gr_init_l1c_0 },
+ { gf100_gr_init_wwdx_0 },
+ { gf100_gr_init_tpccs_1 },
+ { gf100_gr_init_mpc_0 },
+ { gf110_gr_init_sm_0 },
+ { gf100_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
+ { gf100_gr_init_pe_1 },
{}
};
@@ -98,18 +99,18 @@ nvc8_gr_pack_mmio[] = {
* PGRAPH engine/subdev functions
******************************************************************************/
-struct nouveau_oclass *
-nvc8_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gf110_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xc8),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nvc0_gr_init,
- .fini = _nouveau_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gf100_gr_init,
+ .fini = _nvkm_gr_fini,
},
- .cclass = &nvc8_grctx_oclass,
- .sclass = nvc8_gr_sclass,
- .mmio = nvc8_gr_pack_mmio,
- .fecs.ucode = &nvc0_gr_fecs_ucode,
- .gpccs.ucode = &nvc0_gr_gpccs_ucode,
+ .cclass = &gf110_grctx_oclass,
+ .sclass = gf110_gr_sclass,
+ .mmio = gf110_gr_pack_mmio,
+ .fecs.ucode = &gf100_gr_fecs_ucode,
+ .gpccs.ucode = &gf100_gr_gpccs_ucode,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
similarity index 54%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
index a2371a9f21de..871ac5f806f6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
@@ -21,16 +21,15 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include "gf100.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvd7_gr_init_pe_0[] = {
+static const struct gf100_gr_init
+gf117_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc8 },
@@ -38,8 +37,8 @@ nvd7_gr_init_pe_0[] = {
{}
};
-const struct nvc0_gr_init
-nvd7_gr_init_pes_0[] = {
+const struct gf100_gr_init
+gf117_gr_init_pes_0[] = {
{ 0x41be04, 1, 0x04, 0x00000000 },
{ 0x41be08, 1, 0x04, 0x00000004 },
{ 0x41be0c, 1, 0x04, 0x00000000 },
@@ -48,50 +47,50 @@ nvd7_gr_init_pes_0[] = {
{}
};
-const struct nvc0_gr_init
-nvd7_gr_init_wwdx_0[] = {
+const struct gf100_gr_init
+gf117_gr_init_wwdx_0[] = {
{ 0x41bfd4, 1, 0x04, 0x00800000 },
{ 0x41bfdc, 1, 0x04, 0x00000000 },
{ 0x41bff8, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvd7_gr_init_cbm_0[] = {
+const struct gf100_gr_init
+gf117_gr_init_cbm_0[] = {
{ 0x41becc, 1, 0x04, 0x00000000 },
{ 0x41bee8, 2, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_pack
-nvd7_gr_pack_mmio[] = {
- { nvc0_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvd9_gr_init_pd_0 },
- { nvd9_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvd9_gr_init_prop_0 },
- { nvc1_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvd9_gr_init_gpm_0 },
- { nvd9_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nvc0_gr_init_tpccs_0 },
- { nvd9_gr_init_tex_0 },
- { nvd7_gr_init_pe_0 },
- { nvc0_gr_init_l1c_0 },
- { nvc0_gr_init_mpc_0 },
- { nvd9_gr_init_sm_0 },
- { nvd7_gr_init_pes_0 },
- { nvd7_gr_init_wwdx_0 },
- { nvd7_gr_init_cbm_0 },
- { nvc0_gr_init_be_0 },
- { nvd9_gr_init_fe_1 },
+static const struct gf100_gr_pack
+gf117_gr_pack_mmio[] = {
+ { gf100_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf119_gr_init_pd_0 },
+ { gf119_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gf119_gr_init_prop_0 },
+ { gf108_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf119_gr_init_gpm_0 },
+ { gf119_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gf100_gr_init_tpccs_0 },
+ { gf119_gr_init_tex_0 },
+ { gf117_gr_init_pe_0 },
+ { gf100_gr_init_l1c_0 },
+ { gf100_gr_init_mpc_0 },
+ { gf119_gr_init_sm_0 },
+ { gf117_gr_init_pes_0 },
+ { gf117_gr_init_wwdx_0 },
+ { gf117_gr_init_cbm_0 },
+ { gf100_gr_init_be_0 },
+ { gf119_gr_init_fe_1 },
{}
};
@@ -99,39 +98,39 @@ nvd7_gr_pack_mmio[] = {
* PGRAPH engine/subdev functions
******************************************************************************/
-#include "fuc/hubnvd7.fuc3.h"
+#include "fuc/hubgf117.fuc3.h"
-struct nvc0_gr_ucode
-nvd7_gr_fecs_ucode = {
- .code.data = nvd7_grhub_code,
- .code.size = sizeof(nvd7_grhub_code),
- .data.data = nvd7_grhub_data,
- .data.size = sizeof(nvd7_grhub_data),
+struct gf100_gr_ucode
+gf117_gr_fecs_ucode = {
+ .code.data = gf117_grhub_code,
+ .code.size = sizeof(gf117_grhub_code),
+ .data.data = gf117_grhub_data,
+ .data.size = sizeof(gf117_grhub_data),
};
-#include "fuc/gpcnvd7.fuc3.h"
+#include "fuc/gpcgf117.fuc3.h"
-struct nvc0_gr_ucode
-nvd7_gr_gpccs_ucode = {
- .code.data = nvd7_grgpc_code,
- .code.size = sizeof(nvd7_grgpc_code),
- .data.data = nvd7_grgpc_data,
- .data.size = sizeof(nvd7_grgpc_data),
+struct gf100_gr_ucode
+gf117_gr_gpccs_ucode = {
+ .code.data = gf117_grgpc_code,
+ .code.size = sizeof(gf117_grgpc_code),
+ .data.data = gf117_grgpc_data,
+ .data.size = sizeof(gf117_grgpc_data),
};
-struct nouveau_oclass *
-nvd7_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gf117_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xd7),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nvc0_gr_init,
- .fini = _nouveau_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gf100_gr_init,
+ .fini = _nvkm_gr_fini,
},
- .cclass = &nvd7_grctx_oclass,
- .sclass = nvc8_gr_sclass,
- .mmio = nvd7_gr_pack_mmio,
- .fecs.ucode = &nvd7_gr_fecs_ucode,
- .gpccs.ucode = &nvd7_gr_gpccs_ucode,
+ .cclass = &gf117_grctx_oclass,
+ .sclass = gf110_gr_sclass,
+ .mmio = gf117_gr_pack_mmio,
+ .fecs.ucode = &gf117_gr_fecs_ucode,
+ .gpccs.ucode = &gf117_gr_gpccs_ucode,
.ppc_nr = 1,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
similarity index 68%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
index 25f5905a2b78..e6dd651e2636 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
@@ -21,23 +21,22 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include "gf100.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_gr_init
-nvd9_gr_init_pd_0[] = {
+const struct gf100_gr_init
+gf119_gr_init_pd_0[] = {
{ 0x406024, 1, 0x04, 0x00000000 },
{ 0x4064f0, 3, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_ds_0[] = {
+const struct gf100_gr_init
+gf119_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00002834 },
@@ -46,15 +45,15 @@ nvd9_gr_init_ds_0[] = {
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_prop_0[] = {
+const struct gf100_gr_init
+gf119_gr_init_prop_0[] = {
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 3, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_gpm_0[] = {
+const struct gf100_gr_init
+gf119_gr_init_gpm_0[] = {
{ 0x418c04, 1, 0x04, 0x00000000 },
{ 0x418c64, 2, 0x04, 0x00000000 },
{ 0x418c88, 1, 0x04, 0x00000000 },
@@ -62,8 +61,8 @@ nvd9_gr_init_gpm_0[] = {
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_gpc_unk_1[] = {
+const struct gf100_gr_init
+gf119_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000000 },
@@ -75,8 +74,8 @@ nvd9_gr_init_gpc_unk_1[] = {
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_tex_0[] = {
+const struct gf100_gr_init
+gf119_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -85,8 +84,8 @@ nvd9_gr_init_tex_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvd9_gr_init_pe_0[] = {
+static const struct gf100_gr_init
+gf119_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419810, 1, 0x04, 0x00000000 },
{ 0x419814, 1, 0x04, 0x00000004 },
@@ -97,23 +96,23 @@ nvd9_gr_init_pe_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvd9_gr_init_wwdx_0[] = {
+static const struct gf100_gr_init
+gf119_gr_init_wwdx_0[] = {
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{ 0x419bf8, 2, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
-nvd9_gr_init_tpccs_1[] = {
+static const struct gf100_gr_init
+gf119_gr_init_tpccs_1[] = {
{ 0x419d2c, 1, 0x04, 0x00000000 },
{ 0x419d48, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_sm_0[] = {
+const struct gf100_gr_init
+gf119_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@@ -131,42 +130,42 @@ nvd9_gr_init_sm_0[] = {
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_fe_1[] = {
+const struct gf100_gr_init
+gf119_gr_init_fe_1[] = {
{ 0x40402c, 1, 0x04, 0x00000000 },
{ 0x4040f0, 1, 0x04, 0x00000000 },
{ 0x404174, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_pack
-nvd9_gr_pack_mmio[] = {
- { nvc0_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvd9_gr_init_pd_0 },
- { nvd9_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvd9_gr_init_prop_0 },
- { nvc1_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvd9_gr_init_gpm_0 },
- { nvd9_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nvc0_gr_init_tpccs_0 },
- { nvd9_gr_init_tex_0 },
- { nvd9_gr_init_pe_0 },
- { nvc0_gr_init_l1c_0 },
- { nvd9_gr_init_wwdx_0 },
- { nvd9_gr_init_tpccs_1 },
- { nvc0_gr_init_mpc_0 },
- { nvd9_gr_init_sm_0 },
- { nvc0_gr_init_be_0 },
- { nvd9_gr_init_fe_1 },
+static const struct gf100_gr_pack
+gf119_gr_pack_mmio[] = {
+ { gf100_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf119_gr_init_pd_0 },
+ { gf119_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gf119_gr_init_prop_0 },
+ { gf108_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf119_gr_init_gpm_0 },
+ { gf119_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gf100_gr_init_tpccs_0 },
+ { gf119_gr_init_tex_0 },
+ { gf119_gr_init_pe_0 },
+ { gf100_gr_init_l1c_0 },
+ { gf119_gr_init_wwdx_0 },
+ { gf119_gr_init_tpccs_1 },
+ { gf100_gr_init_mpc_0 },
+ { gf119_gr_init_sm_0 },
+ { gf100_gr_init_be_0 },
+ { gf119_gr_init_fe_1 },
{}
};
@@ -174,18 +173,18 @@ nvd9_gr_pack_mmio[] = {
* PGRAPH engine/subdev functions
******************************************************************************/
-struct nouveau_oclass *
-nvd9_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gf119_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xd9),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nvc0_gr_init,
- .fini = _nouveau_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gf100_gr_init,
+ .fini = _nvkm_gr_fini,
},
- .cclass = &nvd9_grctx_oclass,
- .sclass = nvc8_gr_sclass,
- .mmio = nvd9_gr_pack_mmio,
- .fecs.ucode = &nvc0_gr_fecs_ucode,
- .gpccs.ucode = &nvc0_gr_gpccs_ucode,
+ .cclass = &gf119_grctx_oclass,
+ .sclass = gf110_gr_sclass,
+ .mmio = gf119_gr_pack_mmio,
+ .fecs.ucode = &gf100_gr_fecs_ucode,
+ .gpccs.ucode = &gf100_gr_gpccs_ucode,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
similarity index 73%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
index f03ef38e8157..489fdd94b885 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
@@ -21,22 +21,23 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "gf100.h"
+#include "ctxgf100.h"
#include <subdev/pmu.h>
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <nvif/class.h>
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
-nve4_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0xa040, &nouveau_object_ofuncs },
- { KEPLER_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
+static struct nvkm_oclass
+gk104_gr_sclass[] = {
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0xa040, &nvkm_object_ofuncs },
+ { KEPLER_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{}
};
@@ -44,8 +45,8 @@ nve4_gr_sclass[] = {
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_gr_init
-nve4_gr_init_main_0[] = {
+const struct gf100_gr_init
+gk104_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x0001ffe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
@@ -60,8 +61,8 @@ nve4_gr_init_main_0[] = {
{}
};
-static const struct nvc0_gr_init
-nve4_gr_init_ds_0[] = {
+static const struct gf100_gr_init
+gk104_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x0000ff34 },
@@ -70,20 +71,20 @@ nve4_gr_init_ds_0[] = {
{}
};
-static const struct nvc0_gr_init
-nve4_gr_init_sked_0[] = {
+static const struct gf100_gr_init
+gk104_gr_init_sked_0[] = {
{ 0x407010, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
-nve4_gr_init_cwd_0[] = {
+static const struct gf100_gr_init
+gk104_gr_init_cwd_0[] = {
{ 0x405b50, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
-nve4_gr_init_gpc_unk_1[] = {
+static const struct gf100_gr_init
+gk104_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000000 },
@@ -95,15 +96,15 @@ nve4_gr_init_gpc_unk_1[] = {
{}
};
-const struct nvc0_gr_init
-nve4_gr_init_tpccs_0[] = {
+const struct gf100_gr_init
+gk104_gr_init_tpccs_0[] = {
{ 0x419d0c, 1, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{}
};
-const struct nvc0_gr_init
-nve4_gr_init_pe_0[] = {
+const struct gf100_gr_init
+gk104_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x419850, 1, 0x04, 0x00000004 },
@@ -111,8 +112,8 @@ nve4_gr_init_pe_0[] = {
{}
};
-static const struct nvc0_gr_init
-nve4_gr_init_l1c_0[] = {
+static const struct gf100_gr_init
+gk104_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
@@ -125,8 +126,8 @@ nve4_gr_init_l1c_0[] = {
{}
};
-static const struct nvc0_gr_init
-nve4_gr_init_sm_0[] = {
+static const struct gf100_gr_init
+gk104_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
@@ -139,8 +140,8 @@ nve4_gr_init_sm_0[] = {
{}
};
-const struct nvc0_gr_init
-nve4_gr_init_be_0[] = {
+const struct gf100_gr_init
+gk104_gr_init_be_0[] = {
{ 0x40880c, 1, 0x04, 0x00000000 },
{ 0x408850, 1, 0x04, 0x00000004 },
{ 0x408910, 9, 0x04, 0x00000000 },
@@ -153,37 +154,37 @@ nve4_gr_init_be_0[] = {
{}
};
-const struct nvc0_gr_pack
-nve4_gr_pack_mmio[] = {
- { nve4_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvd9_gr_init_pd_0 },
- { nve4_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nve4_gr_init_sked_0 },
- { nve4_gr_init_cwd_0 },
- { nvd9_gr_init_prop_0 },
- { nvc1_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvd9_gr_init_gpm_0 },
- { nve4_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nve4_gr_init_tpccs_0 },
- { nvd9_gr_init_tex_0 },
- { nve4_gr_init_pe_0 },
- { nve4_gr_init_l1c_0 },
- { nvc0_gr_init_mpc_0 },
- { nve4_gr_init_sm_0 },
- { nvd7_gr_init_pes_0 },
- { nvd7_gr_init_wwdx_0 },
- { nvd7_gr_init_cbm_0 },
- { nve4_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
+const struct gf100_gr_pack
+gk104_gr_pack_mmio[] = {
+ { gk104_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf119_gr_init_pd_0 },
+ { gk104_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gk104_gr_init_sked_0 },
+ { gk104_gr_init_cwd_0 },
+ { gf119_gr_init_prop_0 },
+ { gf108_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf119_gr_init_gpm_0 },
+ { gk104_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gk104_gr_init_tpccs_0 },
+ { gf119_gr_init_tex_0 },
+ { gk104_gr_init_pe_0 },
+ { gk104_gr_init_l1c_0 },
+ { gf100_gr_init_mpc_0 },
+ { gk104_gr_init_sm_0 },
+ { gf117_gr_init_pes_0 },
+ { gf117_gr_init_wwdx_0 },
+ { gf117_gr_init_cbm_0 },
+ { gk104_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
{}
};
@@ -192,11 +193,11 @@ nve4_gr_pack_mmio[] = {
******************************************************************************/
int
-nve4_gr_init(struct nouveau_object *object)
+gk104_gr_init(struct nvkm_object *object)
{
- struct nvc0_gr_oclass *oclass = (void *)object->oclass;
- struct nvc0_gr_priv *priv = (void *)object;
- struct nouveau_pmu *pmu = nouveau_pmu(priv);
+ struct gf100_gr_oclass *oclass = (void *)object->oclass;
+ struct gf100_gr_priv *priv = (void *)object;
+ struct nvkm_pmu *pmu = nvkm_pmu(priv);
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
@@ -206,7 +207,7 @@ nve4_gr_init(struct nouveau_object *object)
if (pmu)
pmu->pgob(pmu, false);
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -219,7 +220,7 @@ nve4_gr_init(struct nouveau_object *object)
nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
- nvc0_gr_mmio(priv, oclass->mmio);
+ gf100_gr_mmio(priv, oclass->mmio);
nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
@@ -304,44 +305,44 @@ nve4_gr_init(struct nouveau_object *object)
nv_wr32(priv, 0x400054, 0x34ce3464);
- nvc0_gr_zbc_init(priv);
+ gf100_gr_zbc_init(priv);
- return nvc0_gr_init_ctxctl(priv);
+ return gf100_gr_init_ctxctl(priv);
}
-#include "fuc/hubnve0.fuc3.h"
+#include "fuc/hubgk104.fuc3.h"
-static struct nvc0_gr_ucode
-nve4_gr_fecs_ucode = {
- .code.data = nve0_grhub_code,
- .code.size = sizeof(nve0_grhub_code),
- .data.data = nve0_grhub_data,
- .data.size = sizeof(nve0_grhub_data),
+static struct gf100_gr_ucode
+gk104_gr_fecs_ucode = {
+ .code.data = gk104_grhub_code,
+ .code.size = sizeof(gk104_grhub_code),
+ .data.data = gk104_grhub_data,
+ .data.size = sizeof(gk104_grhub_data),
};
-#include "fuc/gpcnve0.fuc3.h"
+#include "fuc/gpcgk104.fuc3.h"
-static struct nvc0_gr_ucode
-nve4_gr_gpccs_ucode = {
- .code.data = nve0_grgpc_code,
- .code.size = sizeof(nve0_grgpc_code),
- .data.data = nve0_grgpc_data,
- .data.size = sizeof(nve0_grgpc_data),
+static struct gf100_gr_ucode
+gk104_gr_gpccs_ucode = {
+ .code.data = gk104_grgpc_code,
+ .code.size = sizeof(gk104_grgpc_code),
+ .data.data = gk104_grgpc_data,
+ .data.size = sizeof(gk104_grgpc_data),
};
-struct nouveau_oclass *
-nve4_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gk104_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xe4),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nve4_gr_init,
- .fini = _nouveau_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gk104_gr_init,
+ .fini = _nvkm_gr_fini,
},
- .cclass = &nve4_grctx_oclass,
- .sclass = nve4_gr_sclass,
- .mmio = nve4_gr_pack_mmio,
- .fecs.ucode = &nve4_gr_fecs_ucode,
- .gpccs.ucode = &nve4_gr_gpccs_ucode,
+ .cclass = &gk104_grctx_oclass,
+ .sclass = gk104_gr_sclass,
+ .mmio = gk104_gr_pack_mmio,
+ .fecs.ucode = &gk104_gr_fecs_ucode,
+ .gpccs.ucode = &gk104_gr_gpccs_ucode,
.ppc_nr = 1,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
similarity index 64%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
index 84d4456503c2..78e03ab1608e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
@@ -21,20 +21,23 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "gf100.h"
+#include "ctxgf100.h"
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <subdev/timer.h>
+
+#include <nvif/class.h>
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-struct nouveau_oclass
-nvf0_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0xa140, &nouveau_object_ofuncs },
- { KEPLER_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { KEPLER_COMPUTE_B, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
+struct nvkm_oclass
+gk110_gr_sclass[] = {
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0xa140, &nvkm_object_ofuncs },
+ { KEPLER_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { KEPLER_COMPUTE_B, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{}
};
@@ -42,16 +45,16 @@ nvf0_gr_sclass[] = {
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_gr_init
-nvf0_gr_init_fe_0[] = {
+const struct gf100_gr_init
+gk110_gr_init_fe_0[] = {
{ 0x40415c, 1, 0x04, 0x00000000 },
{ 0x404170, 1, 0x04, 0x00000000 },
{ 0x4041b4, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvf0_gr_init_ds_0[] = {
+const struct gf100_gr_init
+gk110_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x0000ff00 },
@@ -60,23 +63,23 @@ nvf0_gr_init_ds_0[] = {
{}
};
-const struct nvc0_gr_init
-nvf0_gr_init_sked_0[] = {
+const struct gf100_gr_init
+gk110_gr_init_sked_0[] = {
{ 0x407010, 1, 0x04, 0x00000000 },
{ 0x407040, 1, 0x04, 0x80440424 },
{ 0x407048, 1, 0x04, 0x0000000a },
{}
};
-const struct nvc0_gr_init
-nvf0_gr_init_cwd_0[] = {
+const struct gf100_gr_init
+gk110_gr_init_cwd_0[] = {
{ 0x405b44, 1, 0x04, 0x00000000 },
{ 0x405b50, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvf0_gr_init_gpc_unk_1[] = {
+const struct gf100_gr_init
+gk110_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000400 },
@@ -88,8 +91,8 @@ nvf0_gr_init_gpc_unk_1[] = {
{}
};
-const struct nvc0_gr_init
-nvf0_gr_init_tex_0[] = {
+const struct gf100_gr_init
+gk110_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -100,8 +103,8 @@ nvf0_gr_init_tex_0[] = {
{}
};
-static const struct nvc0_gr_init
-nvf0_gr_init_l1c_0[] = {
+static const struct gf100_gr_init
+gk110_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
@@ -115,8 +118,8 @@ nvf0_gr_init_l1c_0[] = {
{}
};
-const struct nvc0_gr_init
-nvf0_gr_init_sm_0[] = {
+const struct gf100_gr_init
+gk110_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000080 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
@@ -132,37 +135,37 @@ nvf0_gr_init_sm_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nvf0_gr_pack_mmio[] = {
- { nve4_gr_init_main_0 },
- { nvf0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvd9_gr_init_pd_0 },
- { nvf0_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvf0_gr_init_sked_0 },
- { nvf0_gr_init_cwd_0 },
- { nvd9_gr_init_prop_0 },
- { nvc1_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvd9_gr_init_gpm_0 },
- { nvf0_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nve4_gr_init_tpccs_0 },
- { nvf0_gr_init_tex_0 },
- { nve4_gr_init_pe_0 },
- { nvf0_gr_init_l1c_0 },
- { nvc0_gr_init_mpc_0 },
- { nvf0_gr_init_sm_0 },
- { nvd7_gr_init_pes_0 },
- { nvd7_gr_init_wwdx_0 },
- { nvd7_gr_init_cbm_0 },
- { nve4_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
+static const struct gf100_gr_pack
+gk110_gr_pack_mmio[] = {
+ { gk104_gr_init_main_0 },
+ { gk110_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf119_gr_init_pd_0 },
+ { gk110_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gk110_gr_init_sked_0 },
+ { gk110_gr_init_cwd_0 },
+ { gf119_gr_init_prop_0 },
+ { gf108_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf119_gr_init_gpm_0 },
+ { gk110_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gk104_gr_init_tpccs_0 },
+ { gk110_gr_init_tex_0 },
+ { gk104_gr_init_pe_0 },
+ { gk110_gr_init_l1c_0 },
+ { gf100_gr_init_mpc_0 },
+ { gk110_gr_init_sm_0 },
+ { gf117_gr_init_pes_0 },
+ { gf117_gr_init_wwdx_0 },
+ { gf117_gr_init_cbm_0 },
+ { gk104_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
{}
};
@@ -171,9 +174,9 @@ nvf0_gr_pack_mmio[] = {
******************************************************************************/
int
-nvf0_gr_fini(struct nouveau_object *object, bool suspend)
+gk110_gr_fini(struct nvkm_object *object, bool suspend)
{
- struct nvc0_gr_priv *priv = (void *)object;
+ struct gf100_gr_priv *priv = (void *)object;
static const struct {
u32 addr;
u32 data;
@@ -204,42 +207,42 @@ nvf0_gr_fini(struct nouveau_object *object, bool suspend)
nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
}
- return nouveau_gr_fini(&priv->base, suspend);
+ return nvkm_gr_fini(&priv->base, suspend);
}
-#include "fuc/hubnvf0.fuc3.h"
+#include "fuc/hubgk110.fuc3.h"
-struct nvc0_gr_ucode
-nvf0_gr_fecs_ucode = {
- .code.data = nvf0_grhub_code,
- .code.size = sizeof(nvf0_grhub_code),
- .data.data = nvf0_grhub_data,
- .data.size = sizeof(nvf0_grhub_data),
+struct gf100_gr_ucode
+gk110_gr_fecs_ucode = {
+ .code.data = gk110_grhub_code,
+ .code.size = sizeof(gk110_grhub_code),
+ .data.data = gk110_grhub_data,
+ .data.size = sizeof(gk110_grhub_data),
};
-#include "fuc/gpcnvf0.fuc3.h"
+#include "fuc/gpcgk110.fuc3.h"
-struct nvc0_gr_ucode
-nvf0_gr_gpccs_ucode = {
- .code.data = nvf0_grgpc_code,
- .code.size = sizeof(nvf0_grgpc_code),
- .data.data = nvf0_grgpc_data,
- .data.size = sizeof(nvf0_grgpc_data),
+struct gf100_gr_ucode
+gk110_gr_gpccs_ucode = {
+ .code.data = gk110_grgpc_code,
+ .code.size = sizeof(gk110_grgpc_code),
+ .data.data = gk110_grgpc_data,
+ .data.size = sizeof(gk110_grgpc_data),
};
-struct nouveau_oclass *
-nvf0_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gk110_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xf0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nve4_gr_init,
- .fini = nvf0_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gk104_gr_init,
+ .fini = gk110_gr_fini,
},
- .cclass = &nvf0_grctx_oclass,
- .sclass = nvf0_gr_sclass,
- .mmio = nvf0_gr_pack_mmio,
- .fecs.ucode = &nvf0_gr_fecs_ucode,
- .gpccs.ucode = &nvf0_gr_gpccs_ucode,
+ .cclass = &gk110_grctx_oclass,
+ .sclass = gk110_gr_sclass,
+ .mmio = gk110_gr_pack_mmio,
+ .fecs.ucode = &gk110_gr_fecs_ucode,
+ .gpccs.ucode = &gk110_gr_gpccs_ucode,
.ppc_nr = 2,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
index 59d7d9bf7bb5..5292c5a9a38c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include "gf100.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gk110b_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
@@ -44,7 +43,7 @@ gk110b_gr_init_l1c_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gk110b_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000080 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
@@ -61,37 +60,37 @@ gk110b_gr_init_sm_0[] = {
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gk110b_gr_pack_mmio[] = {
- { nve4_gr_init_main_0 },
- { nvf0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvd9_gr_init_pd_0 },
- { nvf0_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvf0_gr_init_sked_0 },
- { nvf0_gr_init_cwd_0 },
- { nvd9_gr_init_prop_0 },
- { nvc1_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvd9_gr_init_gpm_0 },
- { nvf0_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nve4_gr_init_tpccs_0 },
- { nvf0_gr_init_tex_0 },
- { nve4_gr_init_pe_0 },
+ { gk104_gr_init_main_0 },
+ { gk110_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf119_gr_init_pd_0 },
+ { gk110_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gk110_gr_init_sked_0 },
+ { gk110_gr_init_cwd_0 },
+ { gf119_gr_init_prop_0 },
+ { gf108_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf119_gr_init_gpm_0 },
+ { gk110_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gk104_gr_init_tpccs_0 },
+ { gk110_gr_init_tex_0 },
+ { gk104_gr_init_pe_0 },
{ gk110b_gr_init_l1c_0 },
- { nvc0_gr_init_mpc_0 },
+ { gf100_gr_init_mpc_0 },
{ gk110b_gr_init_sm_0 },
- { nvd7_gr_init_pes_0 },
- { nvd7_gr_init_wwdx_0 },
- { nvd7_gr_init_cbm_0 },
- { nve4_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
+ { gf117_gr_init_pes_0 },
+ { gf117_gr_init_wwdx_0 },
+ { gf117_gr_init_cbm_0 },
+ { gk104_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
{}
};
@@ -99,19 +98,19 @@ gk110b_gr_pack_mmio[] = {
* PGRAPH engine/subdev functions
******************************************************************************/
-struct nouveau_oclass *
-gk110b_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gk110b_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xf1),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nve4_gr_init,
- .fini = nvf0_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gk104_gr_init,
+ .fini = gk110_gr_fini,
},
.cclass = &gk110b_grctx_oclass,
- .sclass = nvf0_gr_sclass,
+ .sclass = gk110_gr_sclass,
.mmio = gk110b_gr_pack_mmio,
- .fecs.ucode = &nvf0_gr_fecs_ucode,
- .gpccs.ucode = &nvf0_gr_gpccs_ucode,
+ .fecs.ucode = &gk110_gr_fecs_ucode,
+ .gpccs.ucode = &gk110_gr_gpccs_ucode,
.ppc_nr = 2,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
similarity index 62%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
index 669ee49ba58b..ae6b853173b6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
@@ -21,20 +21,23 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "gf100.h"
+#include "ctxgf100.h"
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <subdev/timer.h>
+
+#include <nvif/class.h>
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
-nv108_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0xa140, &nouveau_object_ofuncs },
- { KEPLER_B, &nvc0_fermi_ofuncs },
- { 0xa1c0, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+gk208_gr_sclass[] = {
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0xa140, &nvkm_object_ofuncs },
+ { KEPLER_B, &gf100_fermi_ofuncs },
+ { 0xa1c0, &nvkm_object_ofuncs },
{}
};
@@ -42,8 +45,8 @@ nv108_gr_sclass[] = {
* PGRAPH register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nv108_gr_init_main_0[] = {
+static const struct gf100_gr_init
+gk208_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x0001bfe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
@@ -58,8 +61,8 @@ nv108_gr_init_main_0[] = {
{}
};
-static const struct nvc0_gr_init
-nv108_gr_init_ds_0[] = {
+static const struct gf100_gr_init
+gk208_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00000000 },
@@ -68,8 +71,8 @@ nv108_gr_init_ds_0[] = {
{}
};
-const struct nvc0_gr_init
-nv108_gr_init_gpc_unk_0[] = {
+const struct gf100_gr_init
+gk208_gr_init_gpc_unk_0[] = {
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x00000000 },
@@ -77,16 +80,16 @@ nv108_gr_init_gpc_unk_0[] = {
{}
};
-static const struct nvc0_gr_init
-nv108_gr_init_setup_1[] = {
+static const struct gf100_gr_init
+gk208_gr_init_setup_1[] = {
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
{ 0x4188d4, 1, 0x04, 0x00000201 },
{}
};
-static const struct nvc0_gr_init
-nv108_gr_init_tex_0[] = {
+static const struct gf100_gr_init
+gk208_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -96,8 +99,8 @@ nv108_gr_init_tex_0[] = {
{}
};
-static const struct nvc0_gr_init
-nv108_gr_init_l1c_0[] = {
+static const struct gf100_gr_init
+gk208_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
@@ -111,37 +114,37 @@ nv108_gr_init_l1c_0[] = {
{}
};
-static const struct nvc0_gr_pack
-nv108_gr_pack_mmio[] = {
- { nv108_gr_init_main_0 },
- { nvf0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvd9_gr_init_pd_0 },
- { nv108_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvf0_gr_init_sked_0 },
- { nvf0_gr_init_cwd_0 },
- { nvd9_gr_init_prop_0 },
- { nv108_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nv108_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvd9_gr_init_gpm_0 },
- { nvf0_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nve4_gr_init_tpccs_0 },
- { nv108_gr_init_tex_0 },
- { nve4_gr_init_pe_0 },
- { nv108_gr_init_l1c_0 },
- { nvc0_gr_init_mpc_0 },
- { nvf0_gr_init_sm_0 },
- { nvd7_gr_init_pes_0 },
- { nvd7_gr_init_wwdx_0 },
- { nvd7_gr_init_cbm_0 },
- { nve4_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
+static const struct gf100_gr_pack
+gk208_gr_pack_mmio[] = {
+ { gk208_gr_init_main_0 },
+ { gk110_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf119_gr_init_pd_0 },
+ { gk208_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gk110_gr_init_sked_0 },
+ { gk110_gr_init_cwd_0 },
+ { gf119_gr_init_prop_0 },
+ { gk208_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gk208_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf119_gr_init_gpm_0 },
+ { gk110_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gk104_gr_init_tpccs_0 },
+ { gk208_gr_init_tex_0 },
+ { gk104_gr_init_pe_0 },
+ { gk208_gr_init_l1c_0 },
+ { gf100_gr_init_mpc_0 },
+ { gk110_gr_init_sm_0 },
+ { gf117_gr_init_pes_0 },
+ { gf117_gr_init_wwdx_0 },
+ { gf117_gr_init_cbm_0 },
+ { gk104_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
{}
};
@@ -150,9 +153,9 @@ nv108_gr_pack_mmio[] = {
******************************************************************************/
static int
-nv108_gr_fini(struct nouveau_object *object, bool suspend)
+gk208_gr_fini(struct nvkm_object *object, bool suspend)
{
- struct nvc0_gr_priv *priv = (void *)object;
+ struct gf100_gr_priv *priv = (void *)object;
static const struct {
u32 addr;
u32 data;
@@ -183,42 +186,42 @@ nv108_gr_fini(struct nouveau_object *object, bool suspend)
nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
}
- return nouveau_gr_fini(&priv->base, suspend);
+ return nvkm_gr_fini(&priv->base, suspend);
}
-#include "fuc/hubnv108.fuc5.h"
+#include "fuc/hubgk208.fuc5.h"
-static struct nvc0_gr_ucode
-nv108_gr_fecs_ucode = {
- .code.data = nv108_grhub_code,
- .code.size = sizeof(nv108_grhub_code),
- .data.data = nv108_grhub_data,
- .data.size = sizeof(nv108_grhub_data),
+static struct gf100_gr_ucode
+gk208_gr_fecs_ucode = {
+ .code.data = gk208_grhub_code,
+ .code.size = sizeof(gk208_grhub_code),
+ .data.data = gk208_grhub_data,
+ .data.size = sizeof(gk208_grhub_data),
};
-#include "fuc/gpcnv108.fuc5.h"
+#include "fuc/gpcgk208.fuc5.h"
-static struct nvc0_gr_ucode
-nv108_gr_gpccs_ucode = {
- .code.data = nv108_grgpc_code,
- .code.size = sizeof(nv108_grgpc_code),
- .data.data = nv108_grgpc_data,
- .data.size = sizeof(nv108_grgpc_data),
+static struct gf100_gr_ucode
+gk208_gr_gpccs_ucode = {
+ .code.data = gk208_grgpc_code,
+ .code.size = sizeof(gk208_grgpc_code),
+ .data.data = gk208_grgpc_data,
+ .data.size = sizeof(gk208_grgpc_data),
};
-struct nouveau_oclass *
-nv108_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gk208_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0x08),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nve4_gr_init,
- .fini = nv108_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gk104_gr_init,
+ .fini = gk208_gr_fini,
},
- .cclass = &nv108_grctx_oclass,
- .sclass = nv108_gr_sclass,
- .mmio = nv108_gr_pack_mmio,
- .fecs.ucode = &nv108_gr_fecs_ucode,
- .gpccs.ucode = &nv108_gr_gpccs_ucode,
+ .cclass = &gk208_grctx_oclass,
+ .sclass = gk208_gr_sclass,
+ .mmio = gk208_gr_pack_mmio,
+ .fecs.ucode = &gk208_gr_fecs_ucode,
+ .gpccs.ucode = &gk208_gr_gpccs_ucode,
.ppc_nr = 1,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
index 082ea9f08e1c..213755534084 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
@@ -19,30 +19,31 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+#include "gf100.h"
+#include "ctxgf100.h"
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <nvif/class.h>
-static struct nouveau_oclass
+static struct nvkm_oclass
gk20a_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0xa040, &nouveau_object_ofuncs },
- { KEPLER_C, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0xa040, &nvkm_object_ofuncs },
+ { KEPLER_C, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{}
};
-struct nouveau_oclass *
-gk20a_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gk20a_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xea),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nve4_gr_init,
- .fini = _nouveau_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gk104_gr_init,
+ .fini = _nvkm_gr_fini,
},
.cclass = &gk20a_grctx_oclass,
.sclass = gk20a_gr_sclass,
- .mmio = nve4_gr_pack_mmio,
+ .mmio = gk104_gr_pack_mmio,
.ppc_nr = 1,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
index 5a4669087a17..124492b8a2d6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
@@ -21,23 +21,24 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "gf100.h"
+#include "ctxgf100.h"
#include <subdev/bios.h>
#include <subdev/bios/P0260.h>
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <nvif/class.h>
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
gm107_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0xa140, &nouveau_object_ofuncs },
- { MAXWELL_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { MAXWELL_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0xa140, &nvkm_object_ofuncs },
+ { MAXWELL_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { MAXWELL_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{}
};
@@ -45,7 +46,7 @@ gm107_gr_sclass[] = {
* PGRAPH register lists
******************************************************************************/
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003003c2 },
{ 0x400088, 1, 0x04, 0x0001bfe7 },
@@ -61,7 +62,7 @@ gm107_gr_init_main_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
@@ -70,13 +71,13 @@ gm107_gr_init_ds_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_scc_0[] = {
{ 0x40803c, 1, 0x04, 0x00000010 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_sked_0[] = {
{ 0x407010, 1, 0x04, 0x00000000 },
{ 0x407040, 1, 0x04, 0x40440424 },
@@ -84,14 +85,14 @@ gm107_gr_init_sked_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_prop_0[] = {
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_setup_1[] = {
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
@@ -99,7 +100,7 @@ gm107_gr_init_setup_1[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_zcull_0[] = {
{ 0x418910, 1, 0x04, 0x00010001 },
{ 0x418914, 1, 0x04, 0x00000301 },
@@ -110,7 +111,7 @@ gm107_gr_init_zcull_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000400 },
@@ -119,7 +120,7 @@ gm107_gr_init_gpc_unk_1[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_tpccs_0[] = {
{ 0x419dc4, 1, 0x04, 0x00000000 },
{ 0x419dc8, 1, 0x04, 0x00000501 },
@@ -133,7 +134,7 @@ gm107_gr_init_tpccs_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -147,7 +148,7 @@ gm107_gr_init_tex_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_pe_0[] = {
{ 0x419900, 1, 0x04, 0x000000ff },
{ 0x41980c, 1, 0x04, 0x00000010 },
@@ -159,14 +160,14 @@ gm107_gr_init_pe_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_sm_0[] = {
{ 0x419e30, 1, 0x04, 0x000000ff },
{ 0x419e00, 1, 0x04, 0x00000000 },
@@ -185,7 +186,7 @@ gm107_gr_init_sm_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_l1c_1[] = {
{ 0x419ccc, 2, 0x04, 0x00000000 },
{ 0x419c80, 1, 0x04, 0x3f006022 },
@@ -193,7 +194,7 @@ gm107_gr_init_l1c_1[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_pes_0[] = {
{ 0x41be50, 1, 0x04, 0x000000ff },
{ 0x41be04, 1, 0x04, 0x00000000 },
@@ -205,20 +206,20 @@ gm107_gr_init_pes_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_wwdx_0[] = {
{ 0x41bfd4, 1, 0x04, 0x00800000 },
{ 0x41bfdc, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_cbm_0[] = {
{ 0x41becc, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_be_0[] = {
{ 0x408890, 1, 0x04, 0x000000ff },
{ 0x40880c, 1, 0x04, 0x00000000 },
@@ -244,38 +245,38 @@ gm107_gr_init_be_0[] = {
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_sm_1[] = {
{ 0x419e5c, 1, 0x04, 0x00000000 },
{ 0x419e58, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_gr_pack_mmio[] = {
{ gm107_gr_init_main_0 },
- { nvf0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvc0_gr_init_pd_0 },
+ { gk110_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf100_gr_init_pd_0 },
{ gm107_gr_init_ds_0 },
{ gm107_gr_init_scc_0 },
{ gm107_gr_init_sked_0 },
- { nvf0_gr_init_cwd_0 },
+ { gk110_gr_init_cwd_0 },
{ gm107_gr_init_prop_0 },
- { nv108_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
+ { gk208_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
{ gm107_gr_init_setup_1 },
{ gm107_gr_init_zcull_0 },
- { nvc0_gr_init_gpm_0 },
+ { gf100_gr_init_gpm_0 },
{ gm107_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
+ { gf100_gr_init_gcc_0 },
{ gm107_gr_init_tpccs_0 },
{ gm107_gr_init_tex_0 },
{ gm107_gr_init_pe_0 },
{ gm107_gr_init_l1c_0 },
- { nvc0_gr_init_mpc_0 },
+ { gf100_gr_init_mpc_0 },
{ gm107_gr_init_sm_0 },
{ gm107_gr_init_l1c_1 },
{ gm107_gr_init_pes_0 },
@@ -291,7 +292,7 @@ gm107_gr_pack_mmio[] = {
******************************************************************************/
static void
-gm107_gr_init_bios(struct nvc0_gr_priv *priv)
+gm107_gr_init_bios(struct gf100_gr_priv *priv)
{
static const struct {
u32 ctrl;
@@ -303,7 +304,7 @@ gm107_gr_init_bios(struct nvc0_gr_priv *priv)
{ 0x419af0, 0x419af4 },
{ 0x419af8, 0x419afc },
};
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_P0260E infoE;
struct nvbios_P0260X infoX;
int E = -1, X;
@@ -319,17 +320,17 @@ gm107_gr_init_bios(struct nvc0_gr_priv *priv)
}
int
-gm107_gr_init(struct nouveau_object *object)
+gm107_gr_init(struct nvkm_object *object)
{
- struct nvc0_gr_oclass *oclass = (void *)object->oclass;
- struct nvc0_gr_priv *priv = (void *)object;
+ struct gf100_gr_oclass *oclass = (void *)object->oclass;
+ struct gf100_gr_priv *priv = (void *)object;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, ppc, rop;
int ret, i;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -339,7 +340,7 @@ gm107_gr_init(struct nouveau_object *object)
nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
- nvc0_gr_mmio(priv, oclass->mmio);
+ gf100_gr_mmio(priv, oclass->mmio);
gm107_gr_init_bios(priv);
@@ -426,14 +427,14 @@ gm107_gr_init(struct nouveau_object *object)
nv_wr32(priv, 0x400054, 0x2c350f63);
- nvc0_gr_zbc_init(priv);
+ gf100_gr_zbc_init(priv);
- return nvc0_gr_init_ctxctl(priv);
+ return gf100_gr_init_ctxctl(priv);
}
#include "fuc/hubgm107.fuc5.h"
-static struct nvc0_gr_ucode
+static struct gf100_gr_ucode
gm107_gr_fecs_ucode = {
.code.data = gm107_grhub_code,
.code.size = sizeof(gm107_grhub_code),
@@ -443,7 +444,7 @@ gm107_gr_fecs_ucode = {
#include "fuc/gpcgm107.fuc5.h"
-static struct nvc0_gr_ucode
+static struct gf100_gr_ucode
gm107_gr_gpccs_ucode = {
.code.data = gm107_grgpc_code,
.code.size = sizeof(gm107_grgpc_code),
@@ -451,14 +452,14 @@ gm107_gr_gpccs_ucode = {
.data.size = sizeof(gm107_grgpc_data),
};
-struct nouveau_oclass *
-gm107_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gm107_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0x07),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
.init = gm107_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
.cclass = &gm107_grctx_oclass,
.sclass = gm107_gr_sclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
index 5dda6ed846ba..2614510c28d0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
@@ -21,22 +21,16 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+#include <engine/gr.h>
+#include "regs.h"
#include <core/client.h>
#include <core/device.h>
-#include <core/os.h>
#include <core/handle.h>
-#include <core/namedb.h>
-
-#include <subdev/fb.h>
+#include <engine/fifo.h>
#include <subdev/instmem.h>
#include <subdev/timer.h>
-#include <engine/fifo.h>
-#include <engine/gr.h>
-
-#include "regs.h"
-
static u32
nv04_gr_ctx_regs[] = {
0x0040053c,
@@ -353,13 +347,13 @@ nv04_gr_ctx_regs[] = {
};
struct nv04_gr_priv {
- struct nouveau_gr base;
+ struct nvkm_gr base;
struct nv04_gr_chan *chan[16];
spinlock_t lock;
};
struct nv04_gr_chan {
- struct nouveau_object base;
+ struct nvkm_object base;
int chid;
u32 nv04[ARRAY_SIZE(nv04_gr_ctx_regs)];
};
@@ -450,7 +444,7 @@ nv04_gr_priv(struct nv04_gr_chan *chan)
*/
static void
-nv04_gr_set_ctx1(struct nouveau_object *object, u32 mask, u32 value)
+nv04_gr_set_ctx1(struct nvkm_object *object, u32 mask, u32 value)
{
struct nv04_gr_priv *priv = (void *)object->engine;
int subc = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
@@ -466,7 +460,7 @@ nv04_gr_set_ctx1(struct nouveau_object *object, u32 mask, u32 value)
}
static void
-nv04_gr_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value)
+nv04_gr_set_ctx_val(struct nvkm_object *object, u32 mask, u32 value)
{
int class, op, valid = 1;
u32 tmp, ctx1;
@@ -514,8 +508,8 @@ nv04_gr_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value)
}
static int
-nv04_gr_mthd_set_operation(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_set_operation(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
u32 class = nv_ro32(object, 0) & 0xff;
u32 data = *(u32 *)args;
@@ -531,8 +525,8 @@ nv04_gr_mthd_set_operation(struct nouveau_object *object, u32 mthd,
}
static int
-nv04_gr_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_surf3d_clip_h(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv04_gr_priv *priv = (void *)object->engine;
u32 data = *(u32 *)args;
@@ -552,8 +546,8 @@ nv04_gr_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd,
}
static int
-nv04_gr_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_surf3d_clip_v(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv04_gr_priv *priv = (void *)object->engine;
u32 data = *(u32 *)args;
@@ -573,15 +567,15 @@ nv04_gr_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd,
}
static u16
-nv04_gr_mthd_bind_class(struct nouveau_object *object, u32 *args, u32 size)
+nv04_gr_mthd_bind_class(struct nvkm_object *object, u32 *args, u32 size)
{
- struct nouveau_instmem *imem = nouveau_instmem(object);
+ struct nvkm_instmem *imem = nvkm_instmem(object);
u32 inst = *(u32 *)args << 4;
return nv_ro32(imem, inst);
}
static int
-nv04_gr_mthd_bind_surf2d(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf2d(struct nvkm_object *object, u32 mthd,
void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
@@ -598,8 +592,8 @@ nv04_gr_mthd_bind_surf2d(struct nouveau_object *object, u32 mthd,
}
static int
-nv04_gr_mthd_bind_surf2d_swzsurf(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_surf2d_swzsurf(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -619,8 +613,8 @@ nv04_gr_mthd_bind_surf2d_swzsurf(struct nouveau_object *object, u32 mthd,
}
static int
-nv01_gr_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv01_gr_mthd_bind_patt(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -634,8 +628,8 @@ nv01_gr_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
}
static int
-nv04_gr_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_patt(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -649,8 +643,8 @@ nv04_gr_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
}
static int
-nv04_gr_mthd_bind_rop(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_rop(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -664,8 +658,8 @@ nv04_gr_mthd_bind_rop(struct nouveau_object *object, u32 mthd,
}
static int
-nv04_gr_mthd_bind_beta1(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_beta1(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -679,8 +673,8 @@ nv04_gr_mthd_bind_beta1(struct nouveau_object *object, u32 mthd,
}
static int
-nv04_gr_mthd_bind_beta4(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_beta4(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -694,8 +688,8 @@ nv04_gr_mthd_bind_beta4(struct nouveau_object *object, u32 mthd,
}
static int
-nv04_gr_mthd_bind_surf_dst(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_surf_dst(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -709,8 +703,8 @@ nv04_gr_mthd_bind_surf_dst(struct nouveau_object *object, u32 mthd,
}
static int
-nv04_gr_mthd_bind_surf_src(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_surf_src(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -724,8 +718,8 @@ nv04_gr_mthd_bind_surf_src(struct nouveau_object *object, u32 mthd,
}
static int
-nv04_gr_mthd_bind_surf_color(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_surf_color(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -739,8 +733,8 @@ nv04_gr_mthd_bind_surf_color(struct nouveau_object *object, u32 mthd,
}
static int
-nv04_gr_mthd_bind_surf_zeta(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_surf_zeta(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -754,8 +748,8 @@ nv04_gr_mthd_bind_surf_zeta(struct nouveau_object *object, u32 mthd,
}
static int
-nv01_gr_mthd_bind_clip(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv01_gr_mthd_bind_clip(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -769,8 +763,8 @@ nv01_gr_mthd_bind_clip(struct nouveau_object *object, u32 mthd,
}
static int
-nv01_gr_mthd_bind_chroma(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv01_gr_mthd_bind_chroma(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -786,7 +780,7 @@ nv01_gr_mthd_bind_chroma(struct nouveau_object *object, u32 mthd,
return 1;
}
-static struct nouveau_omthds
+static struct nvkm_omthds
nv03_gr_gdi_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_patt },
{ 0x0188, 0x0188, nv04_gr_mthd_bind_rop },
@@ -796,7 +790,7 @@ nv03_gr_gdi_omthds[] = {
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_gdi_omthds[] = {
{ 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
{ 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
@@ -807,7 +801,7 @@ nv04_gr_gdi_omthds[] = {
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv01_gr_blit_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
@@ -820,7 +814,7 @@ nv01_gr_blit_omthds[] = {
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_blit_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
@@ -833,7 +827,7 @@ nv04_gr_blit_omthds[] = {
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_iifc_omthds[] = {
{ 0x0188, 0x0188, nv01_gr_mthd_bind_chroma },
{ 0x018c, 0x018c, nv01_gr_mthd_bind_clip },
@@ -846,7 +840,7 @@ nv04_gr_iifc_omthds[] = {
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv01_gr_ifc_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
@@ -858,7 +852,7 @@ nv01_gr_ifc_omthds[] = {
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_ifc_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
@@ -871,7 +865,7 @@ nv04_gr_ifc_omthds[] = {
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv03_gr_sifc_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_gr_mthd_bind_patt },
@@ -882,7 +876,7 @@ nv03_gr_sifc_omthds[] = {
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_sifc_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
{ 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
@@ -894,7 +888,7 @@ nv04_gr_sifc_omthds[] = {
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv03_gr_sifm_omthds[] = {
{ 0x0188, 0x0188, nv01_gr_mthd_bind_patt },
{ 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
@@ -904,7 +898,7 @@ nv03_gr_sifm_omthds[] = {
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_sifm_omthds[] = {
{ 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
{ 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
@@ -915,14 +909,14 @@ nv04_gr_sifm_omthds[] = {
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_surf3d_omthds[] = {
{ 0x02f8, 0x02f8, nv04_gr_mthd_surf3d_clip_h },
{ 0x02fc, 0x02fc, nv04_gr_mthd_surf3d_clip_v },
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv03_gr_ttri_omthds[] = {
{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
{ 0x018c, 0x018c, nv04_gr_mthd_bind_surf_color },
@@ -930,7 +924,7 @@ nv03_gr_ttri_omthds[] = {
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv01_gr_prim_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_clip },
{ 0x0188, 0x0188, nv01_gr_mthd_bind_patt },
@@ -941,7 +935,7 @@ nv01_gr_prim_omthds[] = {
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_prim_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_clip },
{ 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
@@ -954,16 +948,15 @@ nv04_gr_prim_omthds[] = {
};
static int
-nv04_gr_object_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_gpuobj *obj;
+ struct nvkm_gpuobj *obj;
int ret;
- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
- 16, 16, 0, &obj);
+ ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
+ 16, 16, 0, &obj);
*pobject = nv_object(obj);
if (ret)
return ret;
@@ -978,17 +971,17 @@ nv04_gr_object_ctor(struct nouveau_object *parent,
return 0;
}
-struct nouveau_ofuncs
+struct nvkm_ofuncs
nv04_gr_ofuncs = {
.ctor = nv04_gr_object_ctor,
- .dtor = _nouveau_gpuobj_dtor,
- .init = _nouveau_gpuobj_init,
- .fini = _nouveau_gpuobj_fini,
- .rd32 = _nouveau_gpuobj_rd32,
- .wr32 = _nouveau_gpuobj_wr32,
+ .dtor = _nvkm_gpuobj_dtor,
+ .init = _nvkm_gpuobj_init,
+ .fini = _nvkm_gpuobj_fini,
+ .rd32 = _nvkm_gpuobj_rd32,
+ .wr32 = _nvkm_gpuobj_wr32,
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv04_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs }, /* beta1 */
{ 0x0017, &nv04_gr_ofuncs }, /* chroma */
@@ -1117,18 +1110,18 @@ static u32 *ctx_reg(struct nv04_gr_chan *chan, u32 reg)
}
static int
-nv04_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_gr_context_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fifo_chan *fifo = (void *)parent;
+ struct nvkm_fifo_chan *fifo = (void *)parent;
struct nv04_gr_priv *priv = (void *)engine;
struct nv04_gr_chan *chan;
unsigned long flags;
int ret;
- ret = nouveau_object_create(parent, engine, oclass, 0, &chan);
+ ret = nvkm_object_create(parent, engine, oclass, 0, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -1138,7 +1131,7 @@ nv04_gr_context_ctor(struct nouveau_object *parent,
*pobject = nv_object(priv->chan[fifo->chid]);
atomic_inc(&(*pobject)->refcount);
spin_unlock_irqrestore(&priv->lock, flags);
- nouveau_object_destroy(&chan->base);
+ nvkm_object_destroy(&chan->base);
return 1;
}
@@ -1151,7 +1144,7 @@ nv04_gr_context_ctor(struct nouveau_object *parent,
}
static void
-nv04_gr_context_dtor(struct nouveau_object *object)
+nv04_gr_context_dtor(struct nvkm_object *object)
{
struct nv04_gr_priv *priv = (void *)object->engine;
struct nv04_gr_chan *chan = (void *)object;
@@ -1161,11 +1154,11 @@ nv04_gr_context_dtor(struct nouveau_object *object)
priv->chan[chan->chid] = NULL;
spin_unlock_irqrestore(&priv->lock, flags);
- nouveau_object_destroy(&chan->base);
+ nvkm_object_destroy(&chan->base);
}
static int
-nv04_gr_context_fini(struct nouveau_object *object, bool suspend)
+nv04_gr_context_fini(struct nvkm_object *object, bool suspend)
{
struct nv04_gr_priv *priv = (void *)object->engine;
struct nv04_gr_chan *chan = (void *)object;
@@ -1178,16 +1171,16 @@ nv04_gr_context_fini(struct nouveau_object *object, bool suspend)
nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&priv->lock, flags);
- return nouveau_object_fini(&chan->base, suspend);
+ return nvkm_object_fini(&chan->base, suspend);
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv04_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x04),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_gr_context_ctor,
.dtor = nv04_gr_context_dtor,
- .init = nouveau_object_init,
+ .init = nvkm_object_init,
.fini = nv04_gr_context_fini,
},
};
@@ -1199,7 +1192,7 @@ nv04_gr_cclass = {
bool
nv04_gr_idle(void *obj)
{
- struct nouveau_gr *gr = nouveau_gr(obj);
+ struct nvkm_gr *gr = nvkm_gr(obj);
u32 mask = 0xffffffff;
if (nv_device(obj)->card_type == NV_40)
@@ -1214,13 +1207,13 @@ nv04_gr_idle(void *obj)
return true;
}
-static const struct nouveau_bitfield
+static const struct nvkm_bitfield
nv04_gr_intr_name[] = {
{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
{}
};
-static const struct nouveau_bitfield
+static const struct nvkm_bitfield
nv04_gr_nstatus[] = {
{ NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
{ NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
@@ -1229,7 +1222,7 @@ nv04_gr_nstatus[] = {
{}
};
-const struct nouveau_bitfield
+const struct nvkm_bitfield
nv04_gr_nsource[] = {
{ NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
{ NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
@@ -1254,12 +1247,12 @@ nv04_gr_nsource[] = {
};
static void
-nv04_gr_intr(struct nouveau_subdev *subdev)
+nv04_gr_intr(struct nvkm_subdev *subdev)
{
struct nv04_gr_priv *priv = (void *)subdev;
struct nv04_gr_chan *chan = NULL;
- struct nouveau_namedb *namedb = NULL;
- struct nouveau_handle *handle = NULL;
+ struct nvkm_namedb *namedb = NULL;
+ struct nvkm_handle *handle = NULL;
u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
@@ -1281,7 +1274,7 @@ nv04_gr_intr(struct nouveau_subdev *subdev)
if (stat & NV_PGRAPH_INTR_NOTIFY) {
if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) {
- handle = nouveau_namedb_get_vinst(namedb, inst);
+ handle = nvkm_namedb_get_vinst(namedb, inst);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~NV_PGRAPH_INTR_NOTIFY;
}
@@ -1299,30 +1292,30 @@ nv04_gr_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv04_gr_intr_name, show);
+ nvkm_bitfield_print(nv04_gr_intr_name, show);
pr_cont(" nsource:");
- nouveau_bitfield_print(nv04_gr_nsource, nsource);
+ nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
- nouveau_bitfield_print(nv04_gr_nstatus, nstatus);
+ nvkm_bitfield_print(nv04_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(priv,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, nouveau_client_name(chan), subc, class, mthd,
+ chid, nvkm_client_name(chan), subc, class, mthd,
data);
}
- nouveau_namedb_put(handle);
+ nvkm_namedb_put(handle);
}
static int
-nv04_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -1336,13 +1329,13 @@ nv04_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
static int
-nv04_gr_init(struct nouveau_object *object)
+nv04_gr_init(struct nvkm_object *object)
{
- struct nouveau_engine *engine = nv_engine(object);
+ struct nvkm_engine *engine = nv_engine(object);
struct nv04_gr_priv *priv = (void *)engine;
int ret;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -1377,13 +1370,13 @@ nv04_gr_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv04_gr_oclass = {
.handle = NV_ENGINE(GR, 0x04),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_gr_ctor,
- .dtor = _nouveau_gr_dtor,
+ .dtor = _nvkm_gr_dtor,
.init = nv04_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
index 6b3341f9a3f4..389904eb603f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
@@ -21,18 +21,14 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+#include <engine/gr.h>
+#include "regs.h"
#include <core/client.h>
#include <core/device.h>
-#include <core/os.h>
#include <core/handle.h>
-
-#include <subdev/fb.h>
-
#include <engine/fifo.h>
-#include <engine/gr.h>
-
-#include "regs.h"
+#include <subdev/fb.h>
struct pipe_state {
u32 pipe_0x0000[0x040/4];
@@ -391,13 +387,13 @@ static int nv17_gr_ctx_regs[] = {
};
struct nv10_gr_priv {
- struct nouveau_gr base;
+ struct nvkm_gr base;
struct nv10_gr_chan *chan[32];
spinlock_t lock;
};
struct nv10_gr_chan {
- struct nouveau_object base;
+ struct nvkm_object base;
int chid;
int nv10[ARRAY_SIZE(nv10_gr_ctx_regs)];
int nv17[ARRAY_SIZE(nv17_gr_ctx_regs)];
@@ -432,7 +428,7 @@ nv10_gr_priv(struct nv10_gr_chan *chan)
nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, state[__i]); \
} while (0)
-static struct nouveau_oclass
+static struct nvkm_oclass
nv10_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs }, /* clip */
@@ -455,7 +451,7 @@ nv10_gr_sclass[] = {
{},
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv15_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs }, /* clip */
@@ -479,8 +475,8 @@ nv15_gr_sclass[] = {
};
static int
-nv17_gr_mthd_lma_window(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv17_gr_mthd_lma_window(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv10_gr_chan *chan = (void *)object->parent;
struct nv10_gr_priv *priv = nv10_gr_priv(chan);
@@ -556,8 +552,8 @@ nv17_gr_mthd_lma_window(struct nouveau_object *object, u32 mthd,
}
static int
-nv17_gr_mthd_lma_enable(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv17_gr_mthd_lma_enable(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv10_gr_chan *chan = (void *)object->parent;
struct nv10_gr_priv *priv = nv10_gr_priv(chan);
@@ -569,7 +565,7 @@ nv17_gr_mthd_lma_enable(struct nouveau_object *object, u32 mthd,
return 0;
}
-static struct nouveau_omthds
+static struct nvkm_omthds
nv17_celcius_omthds[] = {
{ 0x1638, 0x1638, nv17_gr_mthd_lma_window },
{ 0x163c, 0x163c, nv17_gr_mthd_lma_window },
@@ -579,7 +575,7 @@ nv17_celcius_omthds[] = {
{}
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv17_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs }, /* clip */
@@ -1022,18 +1018,17 @@ nv10_gr_context_switch(struct nv10_gr_priv *priv)
} while (0)
static int
-nv10_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fifo_chan *fifo = (void *)parent;
+ struct nvkm_fifo_chan *fifo = (void *)parent;
struct nv10_gr_priv *priv = (void *)engine;
struct nv10_gr_chan *chan;
unsigned long flags;
int ret;
- ret = nouveau_object_create(parent, engine, oclass, 0, &chan);
+ ret = nvkm_object_create(parent, engine, oclass, 0, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -1043,7 +1038,7 @@ nv10_gr_context_ctor(struct nouveau_object *parent,
*pobject = nv_object(priv->chan[fifo->chid]);
atomic_inc(&(*pobject)->refcount);
spin_unlock_irqrestore(&priv->lock, flags);
- nouveau_object_destroy(&chan->base);
+ nvkm_object_destroy(&chan->base);
return 1;
}
@@ -1076,7 +1071,7 @@ nv10_gr_context_ctor(struct nouveau_object *parent,
}
static void
-nv10_gr_context_dtor(struct nouveau_object *object)
+nv10_gr_context_dtor(struct nvkm_object *object)
{
struct nv10_gr_priv *priv = (void *)object->engine;
struct nv10_gr_chan *chan = (void *)object;
@@ -1086,11 +1081,11 @@ nv10_gr_context_dtor(struct nouveau_object *object)
priv->chan[chan->chid] = NULL;
spin_unlock_irqrestore(&priv->lock, flags);
- nouveau_object_destroy(&chan->base);
+ nvkm_object_destroy(&chan->base);
}
static int
-nv10_gr_context_fini(struct nouveau_object *object, bool suspend)
+nv10_gr_context_fini(struct nvkm_object *object, bool suspend)
{
struct nv10_gr_priv *priv = (void *)object->engine;
struct nv10_gr_chan *chan = (void *)object;
@@ -1103,16 +1098,16 @@ nv10_gr_context_fini(struct nouveau_object *object, bool suspend)
nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&priv->lock, flags);
- return nouveau_object_fini(&chan->base, suspend);
+ return nvkm_object_fini(&chan->base, suspend);
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv10_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x10),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv10_gr_context_ctor,
.dtor = nv10_gr_context_dtor,
- .init = nouveau_object_init,
+ .init = nvkm_object_init,
.fini = nv10_gr_context_fini,
},
};
@@ -1122,10 +1117,10 @@ nv10_gr_cclass = {
******************************************************************************/
static void
-nv10_gr_tile_prog(struct nouveau_engine *engine, int i)
+nv10_gr_tile_prog(struct nvkm_engine *engine, int i)
{
- struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
- struct nouveau_fifo *pfifo = nouveau_fifo(engine);
+ struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
+ struct nvkm_fifo *pfifo = nvkm_fifo(engine);
struct nv10_gr_priv *priv = (void *)engine;
unsigned long flags;
@@ -1139,13 +1134,13 @@ nv10_gr_tile_prog(struct nouveau_engine *engine, int i)
pfifo->start(pfifo, &flags);
}
-const struct nouveau_bitfield nv10_gr_intr_name[] = {
+const struct nvkm_bitfield nv10_gr_intr_name[] = {
{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
{ NV_PGRAPH_INTR_ERROR, "ERROR" },
{}
};
-const struct nouveau_bitfield nv10_gr_nstatus[] = {
+const struct nvkm_bitfield nv10_gr_nstatus[] = {
{ NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
{ NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
{ NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
@@ -1154,12 +1149,12 @@ const struct nouveau_bitfield nv10_gr_nstatus[] = {
};
static void
-nv10_gr_intr(struct nouveau_subdev *subdev)
+nv10_gr_intr(struct nvkm_subdev *subdev)
{
struct nv10_gr_priv *priv = (void *)subdev;
struct nv10_gr_chan *chan = NULL;
- struct nouveau_namedb *namedb = NULL;
- struct nouveau_handle *handle = NULL;
+ struct nvkm_namedb *namedb = NULL;
+ struct nvkm_handle *handle = NULL;
u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
@@ -1180,7 +1175,7 @@ nv10_gr_intr(struct nouveau_subdev *subdev)
if (stat & NV_PGRAPH_INTR_ERROR) {
if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) {
- handle = nouveau_namedb_get_class(namedb, class);
+ handle = nvkm_namedb_get_class(namedb, class);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~NV_PGRAPH_INTR_ERROR;
}
@@ -1198,30 +1193,30 @@ nv10_gr_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv10_gr_intr_name, show);
+ nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
- nouveau_bitfield_print(nv04_gr_nsource, nsource);
+ nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
- nouveau_bitfield_print(nv10_gr_nstatus, nstatus);
+ nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(priv,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, nouveau_client_name(chan), subc, class, mthd,
+ chid, nvkm_client_name(chan), subc, class, mthd,
data);
}
- nouveau_namedb_put(handle);
+ nvkm_namedb_put(handle);
}
static int
-nv10_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv10_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv10_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -1245,21 +1240,21 @@ nv10_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
static void
-nv10_gr_dtor(struct nouveau_object *object)
+nv10_gr_dtor(struct nvkm_object *object)
{
struct nv10_gr_priv *priv = (void *)object;
- nouveau_gr_destroy(&priv->base);
+ nvkm_gr_destroy(&priv->base);
}
static int
-nv10_gr_init(struct nouveau_object *object)
+nv10_gr_init(struct nvkm_object *object)
{
- struct nouveau_engine *engine = nv_engine(object);
- struct nouveau_fb *pfb = nouveau_fb(object);
+ struct nvkm_engine *engine = nv_engine(object);
+ struct nvkm_fb *pfb = nvkm_fb(object);
struct nv10_gr_priv *priv = (void *)engine;
int ret, i;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -1302,16 +1297,16 @@ nv10_gr_init(struct nouveau_object *object)
}
static int
-nv10_gr_fini(struct nouveau_object *object, bool suspend)
+nv10_gr_fini(struct nvkm_object *object, bool suspend)
{
struct nv10_gr_priv *priv = (void *)object;
- return nouveau_gr_fini(&priv->base, suspend);
+ return nvkm_gr_fini(&priv->base, suspend);
}
-struct nouveau_oclass
+struct nvkm_oclass
nv10_gr_oclass = {
.handle = NV_ENGINE(GR, 0x10),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv10_gr_ctor,
.dtor = nv10_gr_dtor,
.init = nv10_gr_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
index 9841b4e5964d..1713ffb669e8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
@@ -1,24 +1,18 @@
-#include <core/client.h>
-#include <core/device.h>
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/handle.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/gr.h>
-#include <engine/fifo.h>
-
#include "nv20.h"
#include "regs.h"
+#include <core/client.h>
+#include <core/device.h>
+#include <core/handle.h>
+#include <engine/fifo.h>
+#include <subdev/fb.h>
+#include <subdev/timer.h>
+
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
nv20_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
@@ -43,22 +37,20 @@ nv20_gr_sclass[] = {
******************************************************************************/
static int
-nv20_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
- 0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC,
- &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- chan->chid = nouveau_fifo_chan(parent)->chid;
+ chan->chid = nvkm_fifo_chan(parent)->chid;
nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
nv_wo32(chan, 0x033c, 0xffff0000);
@@ -108,13 +100,13 @@ nv20_gr_context_ctor(struct nouveau_object *parent,
}
int
-nv20_gr_context_init(struct nouveau_object *object)
+nv20_gr_context_init(struct nvkm_object *object)
{
struct nv20_gr_priv *priv = (void *)object->engine;
struct nv20_gr_chan *chan = (void *)object;
int ret;
- ret = nouveau_gr_context_init(&chan->base);
+ ret = nvkm_gr_context_init(&chan->base);
if (ret)
return ret;
@@ -123,7 +115,7 @@ nv20_gr_context_init(struct nouveau_object *object)
}
int
-nv20_gr_context_fini(struct nouveau_object *object, bool suspend)
+nv20_gr_context_fini(struct nvkm_object *object, bool suspend)
{
struct nv20_gr_priv *priv = (void *)object->engine;
struct nv20_gr_chan *chan = (void *)object;
@@ -142,19 +134,19 @@ nv20_gr_context_fini(struct nouveau_object *object, bool suspend)
nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
- return nouveau_gr_context_fini(&chan->base, suspend);
+ return nvkm_gr_context_fini(&chan->base, suspend);
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv20_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x20),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv20_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
+ .dtor = _nvkm_gr_context_dtor,
.init = nv20_gr_context_init,
.fini = nv20_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -163,10 +155,10 @@ nv20_gr_cclass = {
******************************************************************************/
void
-nv20_gr_tile_prog(struct nouveau_engine *engine, int i)
+nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
{
- struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
- struct nouveau_fifo *pfifo = nouveau_fifo(engine);
+ struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
+ struct nvkm_fifo *pfifo = nvkm_fifo(engine);
struct nv20_gr_priv *priv = (void *)engine;
unsigned long flags;
@@ -194,11 +186,11 @@ nv20_gr_tile_prog(struct nouveau_engine *engine, int i)
}
void
-nv20_gr_intr(struct nouveau_subdev *subdev)
+nv20_gr_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_engine *engine = nv_engine(subdev);
- struct nouveau_object *engctx;
- struct nouveau_handle *handle;
+ struct nvkm_engine *engine = nv_engine(subdev);
+ struct nvkm_object *engctx;
+ struct nvkm_handle *handle;
struct nv20_gr_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
@@ -211,13 +203,13 @@ nv20_gr_intr(struct nouveau_subdev *subdev)
u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
u32 show = stat;
- engctx = nouveau_engctx_get(engine, chid);
+ engctx = nvkm_engctx_get(engine, chid);
if (stat & NV_PGRAPH_INTR_ERROR) {
if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
- handle = nouveau_handle_get_class(engctx, class);
+ handle = nvkm_handle_get_class(engctx, class);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~NV_PGRAPH_INTR_ERROR;
- nouveau_handle_put(handle);
+ nvkm_handle_put(handle);
}
}
@@ -226,36 +218,36 @@ nv20_gr_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv10_gr_intr_name, show);
+ nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
- nouveau_bitfield_print(nv04_gr_nsource, nsource);
+ nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
- nouveau_bitfield_print(nv10_gr_nstatus, nstatus);
+ nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(priv,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, nouveau_client_name(engctx), subc, class, mthd,
+ chid, nvkm_client_name(engctx), subc, class, mthd,
data);
}
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
static int
-nv20_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
if (ret)
return ret;
@@ -268,23 +260,23 @@ nv20_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
void
-nv20_gr_dtor(struct nouveau_object *object)
+nv20_gr_dtor(struct nvkm_object *object)
{
struct nv20_gr_priv *priv = (void *)object;
- nouveau_gpuobj_ref(NULL, &priv->ctxtab);
- nouveau_gr_destroy(&priv->base);
+ nvkm_gpuobj_ref(NULL, &priv->ctxtab);
+ nvkm_gr_destroy(&priv->base);
}
int
-nv20_gr_init(struct nouveau_object *object)
+nv20_gr_init(struct nvkm_object *object)
{
- struct nouveau_engine *engine = nv_engine(object);
+ struct nvkm_engine *engine = nv_engine(object);
struct nv20_gr_priv *priv = (void *)engine;
- struct nouveau_fb *pfb = nouveau_fb(object);
+ struct nvkm_fb *pfb = nvkm_fb(object);
u32 tmp, vramsz;
int ret, i;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -372,13 +364,13 @@ nv20_gr_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv20_gr_oclass = {
.handle = NV_ENGINE(GR, 0x20),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv20_gr_ctor,
.dtor = nv20_gr_dtor,
.init = nv20_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
index 9019eea4a613..ac4dc048fed1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
@@ -1,31 +1,26 @@
#ifndef __NV20_GR_H__
#define __NV20_GR_H__
-
-#include <core/enum.h>
-
#include <engine/gr.h>
-#include <engine/fifo.h>
struct nv20_gr_priv {
- struct nouveau_gr base;
- struct nouveau_gpuobj *ctxtab;
+ struct nvkm_gr base;
+ struct nvkm_gpuobj *ctxtab;
};
struct nv20_gr_chan {
- struct nouveau_gr_chan base;
+ struct nvkm_gr_chan base;
int chid;
};
-extern struct nouveau_oclass nv25_gr_sclass[];
-int nv20_gr_context_init(struct nouveau_object *);
-int nv20_gr_context_fini(struct nouveau_object *, bool);
+extern struct nvkm_oclass nv25_gr_sclass[];
+int nv20_gr_context_init(struct nvkm_object *);
+int nv20_gr_context_fini(struct nvkm_object *, bool);
-void nv20_gr_tile_prog(struct nouveau_engine *, int);
-void nv20_gr_intr(struct nouveau_subdev *);
+void nv20_gr_tile_prog(struct nvkm_engine *, int);
+void nv20_gr_intr(struct nvkm_subdev *);
-void nv20_gr_dtor(struct nouveau_object *);
-int nv20_gr_init(struct nouveau_object *);
-
-int nv30_gr_init(struct nouveau_object *);
+void nv20_gr_dtor(struct nvkm_object *);
+int nv20_gr_init(struct nvkm_object *);
+int nv30_gr_init(struct nvkm_object *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
index 903a2ec361ce..bc362519cebb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
@@ -1,20 +1,13 @@
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/gr.h>
-
#include "nv20.h"
#include "regs.h"
+#include <engine/fifo.h>
+
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-struct nouveau_oclass
+struct nvkm_oclass
nv25_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
@@ -39,21 +32,20 @@ nv25_gr_sclass[] = {
******************************************************************************/
static int
-nv25_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv25_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x3724,
- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x3724,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- chan->chid = nouveau_fifo_chan(parent)->chid;
+ chan->chid = nvkm_fifo_chan(parent)->chid;
nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
nv_wo32(chan, 0x035c, 0xffff0000);
@@ -111,16 +103,16 @@ nv25_gr_context_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv25_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x25),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv25_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
+ .dtor = _nvkm_gr_context_dtor,
.init = nv20_gr_context_init,
.fini = nv20_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -129,20 +121,20 @@ nv25_gr_cclass = {
******************************************************************************/
static int
-nv25_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
if (ret)
return ret;
@@ -154,13 +146,13 @@ nv25_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv25_gr_oclass = {
.handle = NV_ENGINE(GR, 0x25),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv25_gr_ctor,
.dtor = nv20_gr_dtor,
.init = nv20_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
index e31f6c766729..22a5096e283d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
@@ -1,35 +1,27 @@
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/gr.h>
-
#include "nv20.h"
#include "regs.h"
+#include <engine/fifo.h>
+
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static int
-nv2a_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv2a_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x36b0,
- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x36b0,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- chan->chid = nouveau_fifo_chan(parent)->chid;
+ chan->chid = nvkm_fifo_chan(parent)->chid;
nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
nv_wo32(chan, 0x033c, 0xffff0000);
@@ -78,16 +70,16 @@ nv2a_gr_context_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv2a_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x2a),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv2a_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
+ .dtor = _nvkm_gr_context_dtor,
.init = nv20_gr_context_init,
.fini = nv20_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -96,20 +88,20 @@ nv2a_gr_cclass = {
******************************************************************************/
static int
-nv2a_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
if (ret)
return ret;
@@ -121,13 +113,13 @@ nv2a_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv2a_gr_oclass = {
.handle = NV_ENGINE(GR, 0x2a),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv2a_gr_ctor,
.dtor = nv20_gr_dtor,
.init = nv20_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
index 6a8e0022f8af..dcc84eb54fb6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
@@ -1,21 +1,15 @@
-#include <core/os.h>
-#include <core/device.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/gr.h>
-
#include "nv20.h"
#include "regs.h"
+#include <core/device.h>
+#include <engine/fifo.h>
+#include <subdev/fb.h>
+
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
nv30_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
@@ -42,21 +36,20 @@ nv30_gr_sclass[] = {
******************************************************************************/
static int
-nv30_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x5f48,
- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x5f48,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- chan->chid = nouveau_fifo_chan(parent)->chid;
+ chan->chid = nvkm_fifo_chan(parent)->chid;
nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
nv_wo32(chan, 0x0410, 0x00000101);
@@ -113,16 +106,16 @@ nv30_gr_context_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv30_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x30),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv30_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
+ .dtor = _nvkm_gr_context_dtor,
.init = nv20_gr_context_init,
.fini = nv20_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -131,20 +124,20 @@ nv30_gr_cclass = {
******************************************************************************/
static int
-nv30_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
if (ret)
return ret;
@@ -157,14 +150,14 @@ nv30_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
int
-nv30_gr_init(struct nouveau_object *object)
+nv30_gr_init(struct nvkm_object *object)
{
- struct nouveau_engine *engine = nv_engine(object);
+ struct nvkm_engine *engine = nv_engine(object);
struct nv20_gr_priv *priv = (void *)engine;
- struct nouveau_fb *pfb = nouveau_fb(object);
+ struct nvkm_fb *pfb = nvkm_fb(object);
int ret, i;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -226,13 +219,13 @@ nv30_gr_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv30_gr_oclass = {
.handle = NV_ENGINE(GR, 0x30),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv30_gr_ctor,
.dtor = nv20_gr_dtor,
.init = nv30_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
index 5c2787056292..985b7f3306ae 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
@@ -1,20 +1,13 @@
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/gr.h>
-
#include "nv20.h"
#include "regs.h"
+#include <engine/fifo.h>
+
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
nv34_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
@@ -41,21 +34,20 @@ nv34_gr_sclass[] = {
******************************************************************************/
static int
-nv34_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv34_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x46dc,
- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x46dc,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- chan->chid = nouveau_fifo_chan(parent)->chid;
+ chan->chid = nvkm_fifo_chan(parent)->chid;
nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
nv_wo32(chan, 0x040c, 0x01000101);
@@ -112,16 +104,16 @@ nv34_gr_context_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv34_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x34),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv34_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
+ .dtor = _nvkm_gr_context_dtor,
.init = nv20_gr_context_init,
.fini = nv20_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -130,20 +122,20 @@ nv34_gr_cclass = {
******************************************************************************/
static int
-nv34_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
if (ret)
return ret;
@@ -155,13 +147,13 @@ nv34_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv34_gr_oclass = {
.handle = NV_ENGINE(GR, 0x34),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv34_gr_ctor,
.dtor = nv20_gr_dtor,
.init = nv30_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
index af3f914813e2..707625f19ff5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
@@ -1,18 +1,13 @@
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
#include "nv20.h"
#include "regs.h"
+#include <engine/fifo.h>
+
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
nv35_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
@@ -39,21 +34,20 @@ nv35_gr_sclass[] = {
******************************************************************************/
static int
-nv35_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv35_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x577c,
- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x577c,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- chan->chid = nouveau_fifo_chan(parent)->chid;
+ chan->chid = nvkm_fifo_chan(parent)->chid;
nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
nv_wo32(chan, 0x040c, 0x00000101);
@@ -110,16 +104,16 @@ nv35_gr_context_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv35_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x35),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv35_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
+ .dtor = _nvkm_gr_context_dtor,
.init = nv20_gr_context_init,
.fini = nv20_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -128,20 +122,20 @@ nv35_gr_cclass = {
******************************************************************************/
static int
-nv35_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
if (ret)
return ret;
@@ -153,13 +147,13 @@ nv35_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv35_gr_oclass = {
.handle = NV_ENGINE(GR, 0x35),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv35_gr_ctor,
.dtor = nv20_gr_dtor,
.init = nv30_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
index 6fadd830bc25..7e1937980e3f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
@@ -21,32 +21,26 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/client.h>
-#include <core/os.h>
-#include <core/handle.h>
-#include <core/engctx.h>
-
-#include <subdev/fb.h>
-#include <subdev/timer.h>
-
-#include <engine/gr.h>
-#include <engine/fifo.h>
-
#include "nv40.h"
#include "regs.h"
+#include <core/client.h>
+#include <core/handle.h>
+#include <subdev/fb.h>
+#include <subdev/timer.h>
+#include <engine/fifo.h>
+
struct nv40_gr_priv {
- struct nouveau_gr base;
+ struct nvkm_gr base;
u32 size;
};
struct nv40_gr_chan {
- struct nouveau_gr_chan base;
+ struct nvkm_gr_chan base;
};
static u64
-nv40_gr_units(struct nouveau_gr *gr)
+nv40_gr_units(struct nvkm_gr *gr)
{
struct nv40_gr_priv *priv = (void *)gr;
@@ -58,16 +52,15 @@ nv40_gr_units(struct nouveau_gr *gr)
******************************************************************************/
static int
-nv40_gr_object_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_gpuobj *obj;
+ struct nvkm_gpuobj *obj;
int ret;
- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
- 20, 16, 0, &obj);
+ ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
+ 20, 16, 0, &obj);
*pobject = nv_object(obj);
if (ret)
return ret;
@@ -83,17 +76,17 @@ nv40_gr_object_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
nv40_gr_ofuncs = {
.ctor = nv40_gr_object_ctor,
- .dtor = _nouveau_gpuobj_dtor,
- .init = _nouveau_gpuobj_init,
- .fini = _nouveau_gpuobj_fini,
- .rd32 = _nouveau_gpuobj_rd32,
- .wr32 = _nouveau_gpuobj_wr32,
+ .dtor = _nvkm_gpuobj_dtor,
+ .init = _nvkm_gpuobj_init,
+ .fini = _nvkm_gpuobj_fini,
+ .rd32 = _nvkm_gpuobj_rd32,
+ .wr32 = _nvkm_gpuobj_wr32,
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv40_gr_sclass[] = {
{ 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */
@@ -114,7 +107,7 @@ nv40_gr_sclass[] = {
{},
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv44_gr_sclass[] = {
{ 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */
@@ -140,18 +133,16 @@ nv44_gr_sclass[] = {
******************************************************************************/
static int
-nv40_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv40_gr_priv *priv = (void *)engine;
struct nv40_gr_chan *chan;
int ret;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
- priv->size, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -162,7 +153,7 @@ nv40_gr_context_ctor(struct nouveau_object *parent,
}
static int
-nv40_gr_context_fini(struct nouveau_object *object, bool suspend)
+nv40_gr_context_fini(struct nvkm_object *object, bool suspend)
{
struct nv40_gr_priv *priv = (void *)object->engine;
struct nv40_gr_chan *chan = (void *)object;
@@ -194,16 +185,16 @@ nv40_gr_context_fini(struct nouveau_object *object, bool suspend)
return ret;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv40_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x40),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
- .init = _nouveau_gr_context_init,
+ .dtor = _nvkm_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
.fini = nv40_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -212,10 +203,10 @@ nv40_gr_cclass = {
******************************************************************************/
static void
-nv40_gr_tile_prog(struct nouveau_engine *engine, int i)
+nv40_gr_tile_prog(struct nvkm_engine *engine, int i)
{
- struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
- struct nouveau_fifo *pfifo = nouveau_fifo(engine);
+ struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
+ struct nvkm_fifo *pfifo = nvkm_fifo(engine);
struct nv40_gr_priv *priv = (void *)engine;
unsigned long flags;
@@ -290,12 +281,12 @@ nv40_gr_tile_prog(struct nouveau_engine *engine, int i)
}
static void
-nv40_gr_intr(struct nouveau_subdev *subdev)
+nv40_gr_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
- struct nouveau_engine *engine = nv_engine(subdev);
- struct nouveau_object *engctx;
- struct nouveau_handle *handle = NULL;
+ struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
+ struct nvkm_engine *engine = nv_engine(subdev);
+ struct nvkm_object *engctx;
+ struct nvkm_handle *handle = NULL;
struct nv40_gr_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
@@ -309,15 +300,15 @@ nv40_gr_intr(struct nouveau_subdev *subdev)
u32 show = stat;
int chid;
- engctx = nouveau_engctx_get(engine, inst);
+ engctx = nvkm_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
if (stat & NV_PGRAPH_INTR_ERROR) {
if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
- handle = nouveau_handle_get_class(engctx, class);
+ handle = nvkm_handle_get_class(engctx, class);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~NV_PGRAPH_INTR_ERROR;
- nouveau_handle_put(handle);
+ nvkm_handle_put(handle);
}
if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
@@ -330,30 +321,30 @@ nv40_gr_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv10_gr_intr_name, show);
+ nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
- nouveau_bitfield_print(nv04_gr_nsource, nsource);
+ nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
- nouveau_bitfield_print(nv10_gr_nstatus, nstatus);
+ nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(priv,
"ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, inst << 4, nouveau_client_name(engctx), subc,
+ chid, inst << 4, nvkm_client_name(engctx), subc,
class, mthd, data);
}
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
static int
-nv40_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv40_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -372,15 +363,15 @@ nv40_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
static int
-nv40_gr_init(struct nouveau_object *object)
+nv40_gr_init(struct nvkm_object *object)
{
- struct nouveau_engine *engine = nv_engine(object);
- struct nouveau_fb *pfb = nouveau_fb(object);
+ struct nvkm_engine *engine = nv_engine(object);
+ struct nvkm_fb *pfb = nvkm_fb(object);
struct nv40_gr_priv *priv = (void *)engine;
int ret, i, j;
u32 vramsz;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -524,13 +515,13 @@ nv40_gr_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv40_gr_oclass = {
.handle = NV_ENGINE(GR, 0x40),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_gr_ctor,
- .dtor = _nouveau_gr_dtor,
+ .dtor = _nvkm_gr_dtor,
.init = nv40_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
index 40545f260c0d..131619bda22f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
@@ -1,8 +1,8 @@
#ifndef __NV40_GR_H__
#define __NV40_GR_H__
-
-#include <core/device.h>
-#include <core/gpuobj.h>
+#include <engine/gr.h>
+#include <engine/device.h>
+struct nvkm_gpuobj;
/* returns 1 if device is one of the nv4x using the 0x4497 object class,
* helpful to determine a number of other hardware features
@@ -10,7 +10,7 @@
static inline int
nv44_gr_class(void *priv)
{
- struct nouveau_device *device = nv_device(priv);
+ struct nvkm_device *device = nv_device(priv);
if ((device->chipset & 0xf0) == 0x60)
return 1;
@@ -18,7 +18,6 @@ nv44_gr_class(void *priv)
return !(0x0baf & (1 << (device->chipset & 0x0f)));
}
-int nv40_grctx_init(struct nouveau_device *, u32 *size);
-void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);
-
+int nv40_grctx_init(struct nvkm_device *, u32 *size);
+void nv40_grctx_fill(struct nvkm_device *, struct nvkm_gpuobj *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
index 9d7fcbd96522..270d7cd63fc7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
@@ -21,35 +21,26 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
-#include <core/os.h>
#include <core/client.h>
#include <core/device.h>
#include <core/handle.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/fb.h>
-#include <subdev/mmu.h>
+#include <engine/fifo.h>
#include <subdev/timer.h>
-#include <engine/fifo.h>
-#include <engine/gr.h>
-
-#include "nv50.h"
-
struct nv50_gr_priv {
- struct nouveau_gr base;
+ struct nvkm_gr base;
spinlock_t lock;
u32 size;
};
struct nv50_gr_chan {
- struct nouveau_gr_chan base;
+ struct nvkm_gr_chan base;
};
static u64
-nv50_gr_units(struct nouveau_gr *gr)
+nv50_gr_units(struct nvkm_gr *gr)
{
struct nv50_gr_priv *priv = (void *)gr;
@@ -61,16 +52,15 @@ nv50_gr_units(struct nouveau_gr *gr)
******************************************************************************/
static int
-nv50_gr_object_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_gpuobj *obj;
+ struct nvkm_gpuobj *obj;
int ret;
- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
- 16, 16, 0, &obj);
+ ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
+ 16, 16, 0, &obj);
*pobject = nv_object(obj);
if (ret)
return ret;
@@ -82,17 +72,17 @@ nv50_gr_object_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
nv50_gr_ofuncs = {
.ctor = nv50_gr_object_ctor,
- .dtor = _nouveau_gpuobj_dtor,
- .init = _nouveau_gpuobj_init,
- .fini = _nouveau_gpuobj_fini,
- .rd32 = _nouveau_gpuobj_rd32,
- .wr32 = _nouveau_gpuobj_wr32,
+ .dtor = _nvkm_gpuobj_dtor,
+ .init = _nvkm_gpuobj_init,
+ .fini = _nvkm_gpuobj_fini,
+ .rd32 = _nvkm_gpuobj_rd32,
+ .wr32 = _nvkm_gpuobj_wr32,
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv50_gr_sclass[] = {
{ 0x0030, &nv50_gr_ofuncs },
{ 0x502d, &nv50_gr_ofuncs },
@@ -102,8 +92,8 @@ nv50_gr_sclass[] = {
{}
};
-static struct nouveau_oclass
-nv84_gr_sclass[] = {
+static struct nvkm_oclass
+g84_gr_sclass[] = {
{ 0x0030, &nv50_gr_ofuncs },
{ 0x502d, &nv50_gr_ofuncs },
{ 0x5039, &nv50_gr_ofuncs },
@@ -112,8 +102,8 @@ nv84_gr_sclass[] = {
{}
};
-static struct nouveau_oclass
-nva0_gr_sclass[] = {
+static struct nvkm_oclass
+gt200_gr_sclass[] = {
{ 0x0030, &nv50_gr_ofuncs },
{ 0x502d, &nv50_gr_ofuncs },
{ 0x5039, &nv50_gr_ofuncs },
@@ -122,8 +112,8 @@ nva0_gr_sclass[] = {
{}
};
-static struct nouveau_oclass
-nva3_gr_sclass[] = {
+static struct nvkm_oclass
+gt215_gr_sclass[] = {
{ 0x0030, &nv50_gr_ofuncs },
{ 0x502d, &nv50_gr_ofuncs },
{ 0x5039, &nv50_gr_ofuncs },
@@ -133,8 +123,8 @@ nva3_gr_sclass[] = {
{}
};
-static struct nouveau_oclass
-nvaf_gr_sclass[] = {
+static struct nvkm_oclass
+mcp89_gr_sclass[] = {
{ 0x0030, &nv50_gr_ofuncs },
{ 0x502d, &nv50_gr_ofuncs },
{ 0x5039, &nv50_gr_ofuncs },
@@ -149,18 +139,16 @@ nvaf_gr_sclass[] = {
******************************************************************************/
static int
-nv50_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_gr_priv *priv = (void *)engine;
struct nv50_gr_chan *chan;
int ret;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
- priv->size, 0,
- NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size,
+ 0, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -169,16 +157,16 @@ nv50_gr_context_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv50_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .dtor = _nvkm_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -186,7 +174,7 @@ nv50_gr_cclass = {
* PGRAPH engine/subdev functions
******************************************************************************/
-static const struct nouveau_bitfield nv50_pgr_status[] = {
+static const struct nvkm_bitfield nv50_pgr_status[] = {
{ 0x00000001, "BUSY" }, /* set when any bit is set */
{ 0x00000002, "DISPATCH" },
{ 0x00000004, "UNK2" },
@@ -229,8 +217,9 @@ static const char *const nv50_pgr_vstatus_2[] = {
"ROP", NULL
};
-static void nouveau_pgr_vstatus_print(struct nv50_gr_priv *priv, int r,
- const char *const units[], u32 status)
+static void
+nvkm_pgr_vstatus_print(struct nv50_gr_priv *priv, int r,
+ const char *const units[], u32 status)
{
int i;
@@ -247,9 +236,9 @@ static void nouveau_pgr_vstatus_print(struct nv50_gr_priv *priv, int r,
}
static int
-nv84_gr_tlb_flush(struct nouveau_engine *engine)
+g84_gr_tlb_flush(struct nvkm_engine *engine)
{
- struct nouveau_timer *ptimer = nouveau_timer(engine);
+ struct nvkm_timer *ptimer = nvkm_timer(engine);
struct nv50_gr_priv *priv = (void *)engine;
bool idle, timeout = false;
unsigned long flags;
@@ -285,15 +274,15 @@ nv84_gr_tlb_flush(struct nouveau_engine *engine)
tmp = nv_rd32(priv, 0x400700);
nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp);
- nouveau_bitfield_print(nv50_pgr_status, tmp);
+ nvkm_bitfield_print(nv50_pgr_status, tmp);
pr_cont("\n");
- nouveau_pgr_vstatus_print(priv, 0, nv50_pgr_vstatus_0,
- nv_rd32(priv, 0x400380));
- nouveau_pgr_vstatus_print(priv, 1, nv50_pgr_vstatus_1,
- nv_rd32(priv, 0x400384));
- nouveau_pgr_vstatus_print(priv, 2, nv50_pgr_vstatus_2,
- nv_rd32(priv, 0x400388));
+ nvkm_pgr_vstatus_print(priv, 0, nv50_pgr_vstatus_0,
+ nv_rd32(priv, 0x400380));
+ nvkm_pgr_vstatus_print(priv, 1, nv50_pgr_vstatus_1,
+ nv_rd32(priv, 0x400384));
+ nvkm_pgr_vstatus_print(priv, 2, nv50_pgr_vstatus_2,
+ nv_rd32(priv, 0x400388));
}
@@ -305,7 +294,7 @@ nv84_gr_tlb_flush(struct nouveau_engine *engine)
return timeout ? -EBUSY : 0;
}
-static const struct nouveau_bitfield nv50_mp_exec_errors[] = {
+static const struct nvkm_bitfield nv50_mp_exec_errors[] = {
{ 0x01, "STACK_UNDERFLOW" },
{ 0x02, "STACK_MISMATCH" },
{ 0x04, "QUADON_ACTIVE" },
@@ -316,7 +305,7 @@ static const struct nouveau_bitfield nv50_mp_exec_errors[] = {
{}
};
-static const struct nouveau_bitfield nv50_mpc_traps[] = {
+static const struct nvkm_bitfield nv50_mpc_traps[] = {
{ 0x0000001, "LOCAL_LIMIT_READ" },
{ 0x0000010, "LOCAL_LIMIT_WRITE" },
{ 0x0000040, "STACK_LIMIT" },
@@ -330,7 +319,7 @@ static const struct nouveau_bitfield nv50_mpc_traps[] = {
{}
};
-static const struct nouveau_bitfield nv50_tex_traps[] = {
+static const struct nvkm_bitfield nv50_tex_traps[] = {
{ 0x00000001, "" }, /* any bit set? */
{ 0x00000002, "FAULT" },
{ 0x00000004, "STORAGE_TYPE_MISMATCH" },
@@ -339,30 +328,30 @@ static const struct nouveau_bitfield nv50_tex_traps[] = {
{}
};
-static const struct nouveau_bitfield nv50_gr_trap_m2mf[] = {
+static const struct nvkm_bitfield nv50_gr_trap_m2mf[] = {
{ 0x00000001, "NOTIFY" },
{ 0x00000002, "IN" },
{ 0x00000004, "OUT" },
{}
};
-static const struct nouveau_bitfield nv50_gr_trap_vfetch[] = {
+static const struct nvkm_bitfield nv50_gr_trap_vfetch[] = {
{ 0x00000001, "FAULT" },
{}
};
-static const struct nouveau_bitfield nv50_gr_trap_strmout[] = {
+static const struct nvkm_bitfield nv50_gr_trap_strmout[] = {
{ 0x00000001, "FAULT" },
{}
};
-static const struct nouveau_bitfield nv50_gr_trap_ccache[] = {
+static const struct nvkm_bitfield nv50_gr_trap_ccache[] = {
{ 0x00000001, "FAULT" },
{}
};
/* There must be a *lot* of these. Will take some time to gather them up. */
-const struct nouveau_enum nv50_data_error_names[] = {
+const struct nvkm_enum nv50_data_error_names[] = {
{ 0x00000003, "INVALID_OPERATION", NULL },
{ 0x00000004, "INVALID_VALUE", NULL },
{ 0x00000005, "INVALID_ENUM", NULL },
@@ -408,7 +397,7 @@ const struct nouveau_enum nv50_data_error_names[] = {
{}
};
-static const struct nouveau_bitfield nv50_gr_intr_name[] = {
+static const struct nvkm_bitfield nv50_gr_intr_name[] = {
{ 0x00000001, "NOTIFY" },
{ 0x00000002, "COMPUTE_QUERY" },
{ 0x00000010, "ILLEGAL_MTHD" },
@@ -422,7 +411,7 @@ static const struct nouveau_bitfield nv50_gr_intr_name[] = {
{}
};
-static const struct nouveau_bitfield nv50_gr_trap_prop[] = {
+static const struct nvkm_bitfield nv50_gr_trap_prop[] = {
{ 0x00000004, "SURF_WIDTH_OVERRUN" },
{ 0x00000008, "SURF_HEIGHT_OVERRUN" },
{ 0x00000010, "DST2D_FAULT" },
@@ -469,7 +458,7 @@ nv50_priv_prop_trap(struct nv50_gr_priv *priv,
}
if (ustatus) {
nv_error(priv, "TRAP_PROP - TP %d -", tp);
- nouveau_bitfield_print(nv50_gr_trap_prop, ustatus);
+ nvkm_bitfield_print(nv50_gr_trap_prop, ustatus);
pr_cont(" - Address %02x%08x\n", e14, e10);
}
nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
@@ -501,7 +490,7 @@ nv50_priv_mp_trap(struct nv50_gr_priv *priv, int tpid, int display)
ophigh = nv_rd32(priv, addr + 0x74);
nv_error(priv, "TRAP_MP_EXEC - "
"TP %d MP %d:", tpid, i);
- nouveau_bitfield_print(nv50_mp_exec_errors, status);
+ nvkm_bitfield_print(nv50_mp_exec_errors, status);
pr_cont(" at %06x warp %d, opcode %08x %08x\n",
pc&0xffffff, pc >> 24,
oplow, ophigh);
@@ -517,7 +506,7 @@ nv50_priv_mp_trap(struct nv50_gr_priv *priv, int tpid, int display)
static void
nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old,
- u32 ustatus_new, int display, const char *name)
+ u32 ustatus_new, int display, const char *name)
{
int tps = 0;
u32 units = nv_rd32(priv, 0x1540);
@@ -543,7 +532,7 @@ nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old,
nv_rd32(priv, r));
if (ustatus) {
nv_error(priv, "%s - TP%d:", name, i);
- nouveau_bitfield_print(nv50_tex_traps,
+ nvkm_bitfield_print(nv50_tex_traps,
ustatus);
pr_cont("\n");
ustatus = 0;
@@ -557,7 +546,7 @@ nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old,
}
if (ustatus && display) {
nv_error(priv, "%s - TP%d:", name, i);
- nouveau_bitfield_print(nv50_mpc_traps, ustatus);
+ nvkm_bitfield_print(nv50_mpc_traps, ustatus);
pr_cont("\n");
ustatus = 0;
}
@@ -582,7 +571,7 @@ nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old,
static int
nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display,
- int chid, u64 inst, struct nouveau_object *engctx)
+ int chid, u64 inst, struct nvkm_object *engctx)
{
u32 status = nv_rd32(priv, 0x400108);
u32 ustatus;
@@ -618,7 +607,7 @@ nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display,
nv_error(priv,
"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n",
chid, inst,
- nouveau_client_name(engctx), subc,
+ nvkm_client_name(engctx), subc,
class, mthd, datah, datal, addr, r848);
} else
if (display) {
@@ -643,7 +632,7 @@ nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display,
nv_error(priv,
"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n",
chid, inst,
- nouveau_client_name(engctx), subc,
+ nvkm_client_name(engctx), subc,
class, mthd, data, addr);
} else
if (display) {
@@ -671,7 +660,7 @@ nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display,
u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff;
if (display) {
nv_error(priv, "TRAP_M2MF");
- nouveau_bitfield_print(nv50_gr_trap_m2mf, ustatus);
+ nvkm_bitfield_print(nv50_gr_trap_m2mf, ustatus);
pr_cont("\n");
nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
@@ -692,7 +681,7 @@ nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display,
u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff;
if (display) {
nv_error(priv, "TRAP_VFETCH");
- nouveau_bitfield_print(nv50_gr_trap_vfetch, ustatus);
+ nvkm_bitfield_print(nv50_gr_trap_vfetch, ustatus);
pr_cont("\n");
nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
@@ -709,7 +698,7 @@ nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display,
ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff;
if (display) {
nv_error(priv, "TRAP_STRMOUT");
- nouveau_bitfield_print(nv50_gr_trap_strmout, ustatus);
+ nvkm_bitfield_print(nv50_gr_trap_strmout, ustatus);
pr_cont("\n");
nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
@@ -730,7 +719,7 @@ nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display,
ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff;
if (display) {
nv_error(priv, "TRAP_CCACHE");
- nouveau_bitfield_print(nv50_gr_trap_ccache, ustatus);
+ nvkm_bitfield_print(nv50_gr_trap_ccache, ustatus);
pr_cont("\n");
nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
" %08x %08x %08x\n",
@@ -792,12 +781,12 @@ nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display,
}
static void
-nv50_gr_intr(struct nouveau_subdev *subdev)
+nv50_gr_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
- struct nouveau_engine *engine = nv_engine(subdev);
- struct nouveau_object *engctx;
- struct nouveau_handle *handle = NULL;
+ struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
+ struct nvkm_engine *engine = nv_engine(subdev);
+ struct nvkm_object *engctx;
+ struct nvkm_handle *handle = NULL;
struct nv50_gr_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, 0x400100);
u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff;
@@ -809,27 +798,27 @@ nv50_gr_intr(struct nouveau_subdev *subdev)
u32 show = stat, show_bitfield = stat;
int chid;
- engctx = nouveau_engctx_get(engine, inst);
+ engctx = nvkm_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
if (stat & 0x00000010) {
- handle = nouveau_handle_get_class(engctx, class);
+ handle = nvkm_handle_get_class(engctx, class);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~0x00000010;
- nouveau_handle_put(handle);
+ nvkm_handle_put(handle);
}
if (show & 0x00100000) {
u32 ecode = nv_rd32(priv, 0x400110);
nv_error(priv, "DATA_ERROR ");
- nouveau_enum_print(nv50_data_error_names, ecode);
+ nvkm_enum_print(nv50_data_error_names, ecode);
pr_cont("\n");
show_bitfield &= ~0x00100000;
}
if (stat & 0x00200000) {
if (!nv50_gr_trap_handler(priv, show, chid, (u64)inst << 12,
- engctx))
+ engctx))
show &= ~0x00200000;
show_bitfield &= ~0x00200000;
}
@@ -841,30 +830,30 @@ nv50_gr_intr(struct nouveau_subdev *subdev)
show &= show_bitfield;
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv50_gr_intr_name, show);
+ nvkm_bitfield_print(nv50_gr_intr_name, show);
pr_cont("\n");
}
nv_error(priv,
"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, (u64)inst << 12, nouveau_client_name(engctx),
+ chid, (u64)inst << 12, nvkm_client_name(engctx),
subc, class, mthd, data);
}
if (nv_rd32(priv, 0x400824) & (1 << 31))
nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31));
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
static int
-nv50_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -885,20 +874,20 @@ nv50_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
case 0x94:
case 0x96:
case 0x98:
- nv_engine(priv)->sclass = nv84_gr_sclass;
+ nv_engine(priv)->sclass = g84_gr_sclass;
break;
case 0xa0:
case 0xaa:
case 0xac:
- nv_engine(priv)->sclass = nva0_gr_sclass;
+ nv_engine(priv)->sclass = gt200_gr_sclass;
break;
case 0xa3:
case 0xa5:
case 0xa8:
- nv_engine(priv)->sclass = nva3_gr_sclass;
+ nv_engine(priv)->sclass = gt215_gr_sclass;
break;
case 0xaf:
- nv_engine(priv)->sclass = nvaf_gr_sclass;
+ nv_engine(priv)->sclass = mcp89_gr_sclass;
break;
}
@@ -906,19 +895,19 @@ nv50_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
/* unfortunate hw bug workaround... */
if (nv_device(priv)->chipset != 0x50 &&
nv_device(priv)->chipset != 0xac)
- nv_engine(priv)->tlb_flush = nv84_gr_tlb_flush;
+ nv_engine(priv)->tlb_flush = g84_gr_tlb_flush;
spin_lock_init(&priv->lock);
return 0;
}
static int
-nv50_gr_init(struct nouveau_object *object)
+nv50_gr_init(struct nvkm_object *object)
{
struct nv50_gr_priv *priv = (void *)object;
int ret, units, i;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -998,13 +987,13 @@ nv50_gr_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv50_gr_oclass = {
.handle = NV_ENGINE(GR, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_gr_ctor,
- .dtor = _nouveau_gr_dtor,
+ .dtor = _nvkm_gr_dtor,
.init = nv50_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
index a5cdb43524cb..bcf786f6b731 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
@@ -1,7 +1,9 @@
#ifndef __NV50_GR_H__
#define __NV50_GR_H__
+#include <engine/gr.h>
struct nvkm_device;
+struct nvkm_gpuobj;
-int nv50_grctx_init(struct nouveau_device *, u32 *size);
-void nv50_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);
+int nv50_grctx_init(struct nvkm_device *, u32 *size);
+void nv50_grctx_fill(struct nvkm_device *, struct nvkm_gpuobj *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
deleted file mode 100644
index 2f2ed95fe936..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifndef __NVC0_GR_H__
-#define __NVC0_GR_H__
-
-#include <core/client.h>
-#include <core/device.h>
-#include <core/handle.h>
-#include <core/gpuobj.h>
-#include <core/option.h>
-
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/fb.h>
-#include <subdev/mmu.h>
-#include <subdev/bar.h>
-#include <subdev/timer.h>
-#include <subdev/mc.h>
-#include <subdev/ltc.h>
-
-#include <engine/fifo.h>
-#include <engine/gr.h>
-
-#include "fuc/os.h"
-
-#define GPC_MAX 32
-#define TPC_MAX (GPC_MAX * 8)
-
-#define ROP_BCAST(r) (0x408800 + (r))
-#define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r))
-#define GPC_BCAST(r) (0x418000 + (r))
-#define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r))
-#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r))
-#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
-
-struct nvc0_gr_data {
- u32 size;
- u32 align;
- u32 access;
-};
-
-struct nvc0_gr_mmio {
- u32 addr;
- u32 data;
- u32 shift;
- int buffer;
-};
-
-struct nvc0_gr_fuc {
- u32 *data;
- u32 size;
-};
-
-struct nvc0_gr_zbc_color {
- u32 format;
- u32 ds[4];
- u32 l2[4];
-};
-
-struct nvc0_gr_zbc_depth {
- u32 format;
- u32 ds;
- u32 l2;
-};
-
-struct nvc0_gr_priv {
- struct nouveau_gr base;
-
- struct nvc0_gr_fuc fuc409c;
- struct nvc0_gr_fuc fuc409d;
- struct nvc0_gr_fuc fuc41ac;
- struct nvc0_gr_fuc fuc41ad;
- bool firmware;
-
- struct nvc0_gr_zbc_color zbc_color[NVKM_LTC_MAX_ZBC_CNT];
- struct nvc0_gr_zbc_depth zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
-
- u8 rop_nr;
- u8 gpc_nr;
- u8 tpc_nr[GPC_MAX];
- u8 tpc_total;
- u8 ppc_nr[GPC_MAX];
- u8 ppc_tpc_nr[GPC_MAX][4];
-
- struct nouveau_gpuobj *unk4188b4;
- struct nouveau_gpuobj *unk4188b8;
-
- struct nvc0_gr_data mmio_data[4];
- struct nvc0_gr_mmio mmio_list[4096/8];
- u32 size;
- u32 *data;
-
- u8 magic_not_rop_nr;
-};
-
-struct nvc0_gr_chan {
- struct nouveau_gr_chan base;
-
- struct nouveau_gpuobj *mmio;
- struct nouveau_vma mmio_vma;
- int mmio_nr;
- struct {
- struct nouveau_gpuobj *mem;
- struct nouveau_vma vma;
- } data[4];
-};
-
-int nvc0_gr_context_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nvc0_gr_context_dtor(struct nouveau_object *);
-
-void nvc0_gr_ctxctl_debug(struct nvc0_gr_priv *);
-
-u64 nvc0_gr_units(struct nouveau_gr *);
-int nvc0_gr_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *data, u32 size,
- struct nouveau_object **);
-void nvc0_gr_dtor(struct nouveau_object *);
-int nvc0_gr_init(struct nouveau_object *);
-void nvc0_gr_zbc_init(struct nvc0_gr_priv *);
-
-int nve4_gr_fini(struct nouveau_object *, bool);
-int nve4_gr_init(struct nouveau_object *);
-
-int nvf0_gr_fini(struct nouveau_object *, bool);
-
-extern struct nouveau_ofuncs nvc0_fermi_ofuncs;
-
-extern struct nouveau_oclass nvc0_gr_sclass[];
-extern struct nouveau_omthds nvc0_gr_9097_omthds[];
-extern struct nouveau_omthds nvc0_gr_90c0_omthds[];
-extern struct nouveau_oclass nvc8_gr_sclass[];
-extern struct nouveau_oclass nvf0_gr_sclass[];
-
-struct nvc0_gr_init {
- u32 addr;
- u8 count;
- u8 pitch;
- u32 data;
-};
-
-struct nvc0_gr_pack {
- const struct nvc0_gr_init *init;
- u32 type;
-};
-
-#define pack_for_each_init(init, pack, head) \
- for (pack = head; pack && pack->init; pack++) \
- for (init = pack->init; init && init->count; init++)
-
-struct nvc0_gr_ucode {
- struct nvc0_gr_fuc code;
- struct nvc0_gr_fuc data;
-};
-
-extern struct nvc0_gr_ucode nvc0_gr_fecs_ucode;
-extern struct nvc0_gr_ucode nvc0_gr_gpccs_ucode;
-
-extern struct nvc0_gr_ucode nvf0_gr_fecs_ucode;
-extern struct nvc0_gr_ucode nvf0_gr_gpccs_ucode;
-
-struct nvc0_gr_oclass {
- struct nouveau_oclass base;
- struct nouveau_oclass **cclass;
- struct nouveau_oclass *sclass;
- const struct nvc0_gr_pack *mmio;
- struct {
- struct nvc0_gr_ucode *ucode;
- } fecs;
- struct {
- struct nvc0_gr_ucode *ucode;
- } gpccs;
- int ppc_nr;
-};
-
-void nvc0_gr_mmio(struct nvc0_gr_priv *, const struct nvc0_gr_pack *);
-void nvc0_gr_icmd(struct nvc0_gr_priv *, const struct nvc0_gr_pack *);
-void nvc0_gr_mthd(struct nvc0_gr_priv *, const struct nvc0_gr_pack *);
-int nvc0_gr_init_ctxctl(struct nvc0_gr_priv *);
-
-/* register init value lists */
-
-extern const struct nvc0_gr_init nvc0_gr_init_main_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_fe_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_pri_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_rstr2d_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_pd_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_ds_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_scc_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_prop_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_gpc_unk_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_setup_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_crstr_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_setup_1[];
-extern const struct nvc0_gr_init nvc0_gr_init_zcull_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_gpm_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_gpc_unk_1[];
-extern const struct nvc0_gr_init nvc0_gr_init_gcc_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_tpccs_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_tex_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_pe_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_l1c_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_wwdx_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_tpccs_1[];
-extern const struct nvc0_gr_init nvc0_gr_init_mpc_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_be_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_fe_1[];
-extern const struct nvc0_gr_init nvc0_gr_init_pe_1[];
-
-extern const struct nvc0_gr_init nvc4_gr_init_ds_0[];
-extern const struct nvc0_gr_init nvc4_gr_init_tex_0[];
-extern const struct nvc0_gr_init nvc4_gr_init_sm_0[];
-
-extern const struct nvc0_gr_init nvc1_gr_init_gpc_unk_0[];
-extern const struct nvc0_gr_init nvc1_gr_init_setup_1[];
-
-extern const struct nvc0_gr_init nvd9_gr_init_pd_0[];
-extern const struct nvc0_gr_init nvd9_gr_init_ds_0[];
-extern const struct nvc0_gr_init nvd9_gr_init_prop_0[];
-extern const struct nvc0_gr_init nvd9_gr_init_gpm_0[];
-extern const struct nvc0_gr_init nvd9_gr_init_gpc_unk_1[];
-extern const struct nvc0_gr_init nvd9_gr_init_tex_0[];
-extern const struct nvc0_gr_init nvd9_gr_init_sm_0[];
-extern const struct nvc0_gr_init nvd9_gr_init_fe_1[];
-
-extern const struct nvc0_gr_init nvd7_gr_init_pes_0[];
-extern const struct nvc0_gr_init nvd7_gr_init_wwdx_0[];
-extern const struct nvc0_gr_init nvd7_gr_init_cbm_0[];
-
-extern const struct nvc0_gr_init nve4_gr_init_main_0[];
-extern const struct nvc0_gr_init nve4_gr_init_tpccs_0[];
-extern const struct nvc0_gr_init nve4_gr_init_pe_0[];
-extern const struct nvc0_gr_init nve4_gr_init_be_0[];
-extern const struct nvc0_gr_pack nve4_gr_pack_mmio[];
-
-extern const struct nvc0_gr_init nvf0_gr_init_fe_0[];
-extern const struct nvc0_gr_init nvf0_gr_init_ds_0[];
-extern const struct nvc0_gr_init nvf0_gr_init_sked_0[];
-extern const struct nvc0_gr_init nvf0_gr_init_cwd_0[];
-extern const struct nvc0_gr_init nvf0_gr_init_gpc_unk_1[];
-extern const struct nvc0_gr_init nvf0_gr_init_tex_0[];
-extern const struct nvc0_gr_init nvf0_gr_init_sm_0[];
-
-extern const struct nvc0_gr_init nv108_gr_init_gpc_unk_0[];
-
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h
index de69c5995edd..90a9873ce522 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h
@@ -1,5 +1,5 @@
-#ifndef __NOUVEAU_GR_REGS_H__
-#define __NOUVEAU_GR_REGS_H__
+#ifndef __NVKM_GR_REGS_H__
+#define __NVKM_GR_REGS_H__
#define NV04_PGRAPH_DEBUG_0 0x00400080
#define NV04_PGRAPH_DEBUG_1 0x00400084
From e7c29683fd014dfb9a730086c2c564161264e1ea Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:29:56 +1000
Subject: [PATCH 77/86] drm/nouveau/mpeg: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/engine/mpeg.h | 101 ++++++++--------
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 14 +--
.../gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild | 2 +-
.../nvkm/engine/mpeg/{nv84.c => g84.c} | 62 +++++-----
.../gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c | 111 +++++++++---------
.../gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h | 6 +-
.../gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c | 35 +++---
.../gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c | 84 ++++++-------
.../gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c | 91 +++++++-------
9 files changed, 235 insertions(+), 271 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/mpeg/{nv84.c => g84.c} (65%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
index 9b0d938199f6..4e500b398064 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
@@ -1,63 +1,62 @@
-#ifndef __NOUVEAU_MPEG_H__
-#define __NOUVEAU_MPEG_H__
-
-#include <core/engine.h>
+#ifndef __NVKM_MPEG_H__
+#define __NVKM_MPEG_H__
#include <core/engctx.h>
-struct nouveau_mpeg_chan {
- struct nouveau_engctx base;
+struct nvkm_mpeg_chan {
+ struct nvkm_engctx base;
};
-#define nouveau_mpeg_context_create(p,e,c,g,s,a,f,d) \
- nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
-#define nouveau_mpeg_context_destroy(d) \
- nouveau_engctx_destroy(&(d)->base)
-#define nouveau_mpeg_context_init(d) \
- nouveau_engctx_init(&(d)->base)
-#define nouveau_mpeg_context_fini(d,s) \
- nouveau_engctx_fini(&(d)->base, (s))
+#define nvkm_mpeg_context_create(p,e,c,g,s,a,f,d) \
+ nvkm_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
+#define nvkm_mpeg_context_destroy(d) \
+ nvkm_engctx_destroy(&(d)->base)
+#define nvkm_mpeg_context_init(d) \
+ nvkm_engctx_init(&(d)->base)
+#define nvkm_mpeg_context_fini(d,s) \
+ nvkm_engctx_fini(&(d)->base, (s))
-#define _nouveau_mpeg_context_dtor _nouveau_engctx_dtor
-#define _nouveau_mpeg_context_init _nouveau_engctx_init
-#define _nouveau_mpeg_context_fini _nouveau_engctx_fini
-#define _nouveau_mpeg_context_rd32 _nouveau_engctx_rd32
-#define _nouveau_mpeg_context_wr32 _nouveau_engctx_wr32
+#define _nvkm_mpeg_context_dtor _nvkm_engctx_dtor
+#define _nvkm_mpeg_context_init _nvkm_engctx_init
+#define _nvkm_mpeg_context_fini _nvkm_engctx_fini
+#define _nvkm_mpeg_context_rd32 _nvkm_engctx_rd32
+#define _nvkm_mpeg_context_wr32 _nvkm_engctx_wr32
-struct nouveau_mpeg {
- struct nouveau_engine base;
+#include <core/engine.h>
+
+struct nvkm_mpeg {
+ struct nvkm_engine base;
};
-#define nouveau_mpeg_create(p,e,c,d) \
- nouveau_engine_create((p), (e), (c), true, "PMPEG", "mpeg", (d))
-#define nouveau_mpeg_destroy(d) \
- nouveau_engine_destroy(&(d)->base)
-#define nouveau_mpeg_init(d) \
- nouveau_engine_init(&(d)->base)
-#define nouveau_mpeg_fini(d,s) \
- nouveau_engine_fini(&(d)->base, (s))
+#define nvkm_mpeg_create(p,e,c,d) \
+ nvkm_engine_create((p), (e), (c), true, "PMPEG", "mpeg", (d))
+#define nvkm_mpeg_destroy(d) \
+ nvkm_engine_destroy(&(d)->base)
+#define nvkm_mpeg_init(d) \
+ nvkm_engine_init(&(d)->base)
+#define nvkm_mpeg_fini(d,s) \
+ nvkm_engine_fini(&(d)->base, (s))
-#define _nouveau_mpeg_dtor _nouveau_engine_dtor
-#define _nouveau_mpeg_init _nouveau_engine_init
-#define _nouveau_mpeg_fini _nouveau_engine_fini
+#define _nvkm_mpeg_dtor _nvkm_engine_dtor
+#define _nvkm_mpeg_init _nvkm_engine_init
+#define _nvkm_mpeg_fini _nvkm_engine_fini
-extern struct nouveau_oclass nv31_mpeg_oclass;
-extern struct nouveau_oclass nv40_mpeg_oclass;
-extern struct nouveau_oclass nv44_mpeg_oclass;
-extern struct nouveau_oclass nv50_mpeg_oclass;
-extern struct nouveau_oclass nv84_mpeg_oclass;
-extern struct nouveau_ofuncs nv31_mpeg_ofuncs;
-extern struct nouveau_oclass nv31_mpeg_cclass;
-extern struct nouveau_oclass nv31_mpeg_sclass[];
-extern struct nouveau_oclass nv40_mpeg_sclass[];
-void nv31_mpeg_intr(struct nouveau_subdev *);
-void nv31_mpeg_tile_prog(struct nouveau_engine *, int);
-int nv31_mpeg_init(struct nouveau_object *);
-
-extern struct nouveau_ofuncs nv50_mpeg_ofuncs;
-int nv50_mpeg_context_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nv50_mpeg_intr(struct nouveau_subdev *);
-int nv50_mpeg_init(struct nouveau_object *);
+extern struct nvkm_oclass nv31_mpeg_oclass;
+extern struct nvkm_oclass nv40_mpeg_oclass;
+extern struct nvkm_oclass nv44_mpeg_oclass;
+extern struct nvkm_oclass nv50_mpeg_oclass;
+extern struct nvkm_oclass g84_mpeg_oclass;
+extern struct nvkm_ofuncs nv31_mpeg_ofuncs;
+extern struct nvkm_oclass nv31_mpeg_cclass;
+extern struct nvkm_oclass nv31_mpeg_sclass[];
+extern struct nvkm_oclass nv40_mpeg_sclass[];
+void nv31_mpeg_intr(struct nvkm_subdev *);
+void nv31_mpeg_tile_prog(struct nvkm_engine *, int);
+int nv31_mpeg_init(struct nvkm_object *);
+extern struct nvkm_ofuncs nv50_mpeg_ofuncs;
+int nv50_mpeg_context_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void nv50_mpeg_intr(struct nvkm_subdev *);
+int nv50_mpeg_init(struct nvkm_object *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index f48fd5a22f26..2db202b1cc3a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -109,7 +109,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
+ device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
@@ -138,7 +138,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
+ device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
@@ -167,7 +167,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
+ device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
@@ -196,7 +196,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
+ device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
@@ -225,7 +225,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
+ device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
@@ -283,7 +283,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
+ device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
@@ -371,7 +371,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
+ device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild
index 39a045bcaf6e..61b7b5f98f3c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild
@@ -2,4 +2,4 @@ nvkm-y += nvkm/engine/mpeg/nv31.o
nvkm-y += nvkm/engine/mpeg/nv40.o
nvkm-y += nvkm/engine/mpeg/nv44.o
nvkm-y += nvkm/engine/mpeg/nv50.o
-nvkm-y += nvkm/engine/mpeg/nv84.o
+nvkm-y += nvkm/engine/mpeg/g84.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c
similarity index 65%
rename from drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c
index 97c8343e1a08..0df889fa2611 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c
@@ -21,30 +21,22 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/os.h>
-#include <core/engctx.h>
-
-#include <subdev/mmu.h>
-#include <subdev/bar.h>
-#include <subdev/timer.h>
-
#include <engine/mpeg.h>
-struct nv84_mpeg_priv {
- struct nouveau_mpeg base;
+struct g84_mpeg_priv {
+ struct nvkm_mpeg base;
};
-struct nv84_mpeg_chan {
- struct nouveau_mpeg_chan base;
+struct g84_mpeg_chan {
+ struct nvkm_mpeg_chan base;
};
/*******************************************************************************
* MPEG object classes
******************************************************************************/
-static struct nouveau_oclass
-nv84_mpeg_sclass[] = {
+static struct nvkm_oclass
+g84_mpeg_sclass[] = {
{ 0x8274, &nv50_mpeg_ofuncs },
{}
};
@@ -53,16 +45,16 @@ nv84_mpeg_sclass[] = {
* PMPEG context
******************************************************************************/
-static struct nouveau_oclass
-nv84_mpeg_cclass = {
+static struct nvkm_oclass
+g84_mpeg_cclass = {
.handle = NV_ENGCTX(MPEG, 0x84),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_mpeg_context_ctor,
- .dtor = _nouveau_mpeg_context_dtor,
- .init = _nouveau_mpeg_context_init,
- .fini = _nouveau_mpeg_context_fini,
- .rd32 = _nouveau_mpeg_context_rd32,
- .wr32 = _nouveau_mpeg_context_wr32,
+ .dtor = _nvkm_mpeg_context_dtor,
+ .init = _nvkm_mpeg_context_init,
+ .fini = _nvkm_mpeg_context_fini,
+ .rd32 = _nvkm_mpeg_context_rd32,
+ .wr32 = _nvkm_mpeg_context_wr32,
},
};
@@ -71,32 +63,32 @@ nv84_mpeg_cclass = {
******************************************************************************/
static int
-nv84_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g84_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nv84_mpeg_priv *priv;
+ struct g84_mpeg_priv *priv;
int ret;
- ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
+ ret = nvkm_mpeg_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000002;
nv_subdev(priv)->intr = nv50_mpeg_intr;
- nv_engine(priv)->cclass = &nv84_mpeg_cclass;
- nv_engine(priv)->sclass = nv84_mpeg_sclass;
+ nv_engine(priv)->cclass = &g84_mpeg_cclass;
+ nv_engine(priv)->sclass = g84_mpeg_sclass;
return 0;
}
-struct nouveau_oclass
-nv84_mpeg_oclass = {
+struct nvkm_oclass
+g84_mpeg_oclass = {
.handle = NV_ENGINE(MPEG, 0x84),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv84_mpeg_ctor,
- .dtor = _nouveau_mpeg_dtor,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g84_mpeg_ctor,
+ .dtor = _nvkm_mpeg_dtor,
.init = nv50_mpeg_init,
- .fini = _nouveau_mpeg_fini,
+ .fini = _nvkm_mpeg_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
index d88c700b2f69..b5bef0718359 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
@@ -21,35 +21,30 @@
*
* Authors: Ben Skeggs
*/
+#include "nv31.h"
#include <core/client.h>
-#include <core/os.h>
-#include <core/engctx.h>
#include <core/handle.h>
-
+#include <engine/fifo.h>
+#include <subdev/instmem.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
-#include <subdev/instmem.h>
-
-#include <engine/fifo.h>
-#include <engine/mpeg.h>
-#include <engine/mpeg/nv31.h>
/*******************************************************************************
* MPEG object classes
******************************************************************************/
static int
-nv31_mpeg_object_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv31_mpeg_object_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_gpuobj *obj;
+ struct nvkm_gpuobj *obj;
int ret;
- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
- 20, 16, 0, &obj);
+ ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
+ 20, 16, 0, &obj);
*pobject = nv_object(obj);
if (ret)
return ret;
@@ -62,9 +57,9 @@ nv31_mpeg_object_ctor(struct nouveau_object *parent,
}
static int
-nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
+nv31_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
{
- struct nouveau_instmem *imem = nouveau_instmem(object);
+ struct nvkm_instmem *imem = nvkm_instmem(object);
struct nv31_mpeg_priv *priv = (void *)object->engine;
u32 inst = *(u32 *)arg << 4;
u32 dma0 = nv_ro32(imem, inst + 0);
@@ -100,17 +95,17 @@ nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
return 0;
}
-struct nouveau_ofuncs
+struct nvkm_ofuncs
nv31_mpeg_ofuncs = {
.ctor = nv31_mpeg_object_ctor,
- .dtor = _nouveau_gpuobj_dtor,
- .init = _nouveau_gpuobj_init,
- .fini = _nouveau_gpuobj_fini,
- .rd32 = _nouveau_gpuobj_rd32,
- .wr32 = _nouveau_gpuobj_wr32,
+ .dtor = _nvkm_gpuobj_dtor,
+ .init = _nvkm_gpuobj_init,
+ .fini = _nvkm_gpuobj_fini,
+ .rd32 = _nvkm_gpuobj_rd32,
+ .wr32 = _nvkm_gpuobj_wr32,
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv31_mpeg_omthds[] = {
{ 0x0190, 0x0190, nv31_mpeg_mthd_dma },
{ 0x01a0, 0x01a0, nv31_mpeg_mthd_dma },
@@ -118,7 +113,7 @@ nv31_mpeg_omthds[] = {
{}
};
-struct nouveau_oclass
+struct nvkm_oclass
nv31_mpeg_sclass[] = {
{ 0x3174, &nv31_mpeg_ofuncs, nv31_mpeg_omthds },
{}
@@ -129,17 +124,17 @@ nv31_mpeg_sclass[] = {
******************************************************************************/
static int
-nv31_mpeg_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv31_mpeg_context_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv31_mpeg_priv *priv = (void *)engine;
struct nv31_mpeg_chan *chan;
unsigned long flags;
int ret;
- ret = nouveau_object_create(parent, engine, oclass, 0, &chan);
+ ret = nvkm_object_create(parent, engine, oclass, 0, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -147,7 +142,7 @@ nv31_mpeg_context_ctor(struct nouveau_object *parent,
spin_lock_irqsave(&nv_engine(priv)->lock, flags);
if (priv->chan) {
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
- nouveau_object_destroy(&chan->base);
+ nvkm_object_destroy(&chan->base);
*pobject = NULL;
return -EBUSY;
}
@@ -157,7 +152,7 @@ nv31_mpeg_context_ctor(struct nouveau_object *parent,
}
static void
-nv31_mpeg_context_dtor(struct nouveau_object *object)
+nv31_mpeg_context_dtor(struct nvkm_object *object)
{
struct nv31_mpeg_priv *priv = (void *)object->engine;
struct nv31_mpeg_chan *chan = (void *)object;
@@ -166,17 +161,17 @@ nv31_mpeg_context_dtor(struct nouveau_object *object)
spin_lock_irqsave(&nv_engine(priv)->lock, flags);
priv->chan = NULL;
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
- nouveau_object_destroy(&chan->base);
+ nvkm_object_destroy(&chan->base);
}
-struct nouveau_oclass
+struct nvkm_oclass
nv31_mpeg_cclass = {
.handle = NV_ENGCTX(MPEG, 0x31),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv31_mpeg_context_ctor,
.dtor = nv31_mpeg_context_dtor,
- .init = nouveau_object_init,
- .fini = nouveau_object_fini,
+ .init = nvkm_object_init,
+ .fini = nvkm_object_fini,
},
};
@@ -185,9 +180,9 @@ nv31_mpeg_cclass = {
******************************************************************************/
void
-nv31_mpeg_tile_prog(struct nouveau_engine *engine, int i)
+nv31_mpeg_tile_prog(struct nvkm_engine *engine, int i)
{
- struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
+ struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
struct nv31_mpeg_priv *priv = (void *)engine;
nv_wr32(priv, 0x00b008 + (i * 0x10), tile->pitch);
@@ -196,12 +191,12 @@ nv31_mpeg_tile_prog(struct nouveau_engine *engine, int i)
}
void
-nv31_mpeg_intr(struct nouveau_subdev *subdev)
+nv31_mpeg_intr(struct nvkm_subdev *subdev)
{
struct nv31_mpeg_priv *priv = (void *)subdev;
- struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
- struct nouveau_handle *handle;
- struct nouveau_object *engctx;
+ struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
+ struct nvkm_handle *handle;
+ struct nvkm_object *engctx;
u32 stat = nv_rd32(priv, 0x00b100);
u32 type = nv_rd32(priv, 0x00b230);
u32 mthd = nv_rd32(priv, 0x00b234);
@@ -220,10 +215,10 @@ nv31_mpeg_intr(struct nouveau_subdev *subdev)
}
if (type == 0x00000010 && engctx) {
- handle = nouveau_handle_get_class(engctx, 0x3174);
+ handle = nvkm_handle_get_class(engctx, 0x3174);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~0x01000000;
- nouveau_handle_put(handle);
+ nvkm_handle_put(handle);
}
}
@@ -233,21 +228,21 @@ nv31_mpeg_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
pfifo->chid(pfifo, engctx),
- nouveau_client_name(engctx), stat, type, mthd, data);
+ nvkm_client_name(engctx), stat, type, mthd, data);
}
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
}
static int
-nv31_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv31_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv31_mpeg_priv *priv;
int ret;
- ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
+ ret = nvkm_mpeg_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -261,14 +256,14 @@ nv31_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
int
-nv31_mpeg_init(struct nouveau_object *object)
+nv31_mpeg_init(struct nvkm_object *object)
{
- struct nouveau_engine *engine = nv_engine(object);
+ struct nvkm_engine *engine = nv_engine(object);
struct nv31_mpeg_priv *priv = (void *)object;
- struct nouveau_fb *pfb = nouveau_fb(object);
+ struct nvkm_fb *pfb = nvkm_fb(object);
int ret, i;
- ret = nouveau_mpeg_init(&priv->base);
+ ret = nvkm_mpeg_init(&priv->base);
if (ret)
return ret;
@@ -297,13 +292,13 @@ nv31_mpeg_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv31_mpeg_oclass = {
.handle = NV_ENGINE(MPEG, 0x31),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv31_mpeg_ctor,
- .dtor = _nouveau_mpeg_dtor,
+ .dtor = _nvkm_mpeg_dtor,
.init = nv31_mpeg_init,
- .fini = _nouveau_mpeg_fini,
+ .fini = _nvkm_mpeg_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h
index d08629d0b6ad..782b796d7458 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h
@@ -1,15 +1,13 @@
#ifndef __NV31_MPEG_H__
#define __NV31_MPEG_H__
-
#include <engine/mpeg.h>
struct nv31_mpeg_chan {
- struct nouveau_object base;
+ struct nvkm_object base;
};
struct nv31_mpeg_priv {
- struct nouveau_mpeg base;
+ struct nvkm_mpeg base;
struct nv31_mpeg_chan *chan;
};
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
index bdb2f20ff7b1..9508bf9e140f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
@@ -21,25 +21,18 @@
*
* Authors: Ben Skeggs
*/
+#include "nv31.h"
-#include <core/os.h>
-#include <core/engctx.h>
-
-#include <subdev/fb.h>
-#include <subdev/timer.h>
#include <subdev/instmem.h>
-#include <engine/mpeg.h>
-#include <engine/mpeg/nv31.h>
-
/*******************************************************************************
* MPEG object classes
******************************************************************************/
static int
-nv40_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
+nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
{
- struct nouveau_instmem *imem = nouveau_instmem(object);
+ struct nvkm_instmem *imem = nvkm_instmem(object);
struct nv31_mpeg_priv *priv = (void *)object->engine;
u32 inst = *(u32 *)arg << 4;
u32 dma0 = nv_ro32(imem, inst + 0);
@@ -75,7 +68,7 @@ nv40_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
return 0;
}
-static struct nouveau_omthds
+static struct nvkm_omthds
nv40_mpeg_omthds[] = {
{ 0x0190, 0x0190, nv40_mpeg_mthd_dma },
{ 0x01a0, 0x01a0, nv40_mpeg_mthd_dma },
@@ -83,7 +76,7 @@ nv40_mpeg_omthds[] = {
{}
};
-struct nouveau_oclass
+struct nvkm_oclass
nv40_mpeg_sclass[] = {
{ 0x3174, &nv31_mpeg_ofuncs, nv40_mpeg_omthds },
{}
@@ -94,7 +87,7 @@ nv40_mpeg_sclass[] = {
******************************************************************************/
static void
-nv40_mpeg_intr(struct nouveau_subdev *subdev)
+nv40_mpeg_intr(struct nvkm_subdev *subdev)
{
struct nv31_mpeg_priv *priv = (void *)subdev;
u32 stat;
@@ -109,14 +102,14 @@ nv40_mpeg_intr(struct nouveau_subdev *subdev)
}
static int
-nv40_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv31_mpeg_priv *priv;
int ret;
- ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
+ ret = nvkm_mpeg_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -129,13 +122,13 @@ nv40_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv40_mpeg_oclass = {
.handle = NV_ENGINE(MPEG, 0x40),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_mpeg_ctor,
- .dtor = _nouveau_mpeg_dtor,
+ .dtor = _nvkm_mpeg_dtor,
.init = nv31_mpeg_init,
- .fini = _nouveau_mpeg_fini,
+ .fini = _nvkm_mpeg_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
index 72c7f33fd29b..4720ac884468 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
@@ -21,25 +21,18 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/os.h>
-#include <core/client.h>
-#include <core/engctx.h>
-#include <core/handle.h>
-
-#include <subdev/fb.h>
-#include <subdev/timer.h>
-#include <subdev/instmem.h>
-
-#include <engine/fifo.h>
#include <engine/mpeg.h>
+#include <core/client.h>
+#include <core/handle.h>
+#include <engine/fifo.h>
+
struct nv44_mpeg_priv {
- struct nouveau_mpeg base;
+ struct nvkm_mpeg base;
};
struct nv44_mpeg_chan {
- struct nouveau_mpeg_chan base;
+ struct nvkm_mpeg_chan base;
};
/*******************************************************************************
@@ -47,17 +40,16 @@ struct nv44_mpeg_chan {
******************************************************************************/
static int
-nv44_mpeg_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv44_mpeg_context_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv44_mpeg_chan *chan;
int ret;
- ret = nouveau_mpeg_context_create(parent, engine, oclass, NULL,
- 264 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 264 * 4,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -67,7 +59,7 @@ nv44_mpeg_context_ctor(struct nouveau_object *parent,
}
static int
-nv44_mpeg_context_fini(struct nouveau_object *object, bool suspend)
+nv44_mpeg_context_fini(struct nvkm_object *object, bool suspend)
{
struct nv44_mpeg_priv *priv = (void *)object->engine;
@@ -81,16 +73,16 @@ nv44_mpeg_context_fini(struct nouveau_object *object, bool suspend)
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv44_mpeg_cclass = {
.handle = NV_ENGCTX(MPEG, 0x44),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv44_mpeg_context_ctor,
- .dtor = _nouveau_mpeg_context_dtor,
- .init = _nouveau_mpeg_context_init,
+ .dtor = _nvkm_mpeg_context_dtor,
+ .init = _nvkm_mpeg_context_init,
.fini = nv44_mpeg_context_fini,
- .rd32 = _nouveau_mpeg_context_rd32,
- .wr32 = _nouveau_mpeg_context_wr32,
+ .rd32 = _nvkm_mpeg_context_rd32,
+ .wr32 = _nvkm_mpeg_context_wr32,
},
};
@@ -99,12 +91,12 @@ nv44_mpeg_cclass = {
******************************************************************************/
static void
-nv44_mpeg_intr(struct nouveau_subdev *subdev)
+nv44_mpeg_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
- struct nouveau_engine *engine = nv_engine(subdev);
- struct nouveau_object *engctx;
- struct nouveau_handle *handle;
+ struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
+ struct nvkm_engine *engine = nv_engine(subdev);
+ struct nvkm_object *engctx;
+ struct nvkm_handle *handle;
struct nv44_mpeg_priv *priv = (void *)subdev;
u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff;
u32 stat = nv_rd32(priv, 0x00b100);
@@ -114,7 +106,7 @@ nv44_mpeg_intr(struct nouveau_subdev *subdev)
u32 show = stat;
int chid;
- engctx = nouveau_engctx_get(engine, inst);
+ engctx = nvkm_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
if (stat & 0x01000000) {
@@ -125,10 +117,10 @@ nv44_mpeg_intr(struct nouveau_subdev *subdev)
}
if (type == 0x00000010) {
- handle = nouveau_handle_get_class(engctx, 0x3174);
+ handle = nvkm_handle_get_class(engctx, 0x3174);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~0x01000000;
- nouveau_handle_put(handle);
+ nvkm_handle_put(handle);
}
}
@@ -138,15 +130,15 @@ nv44_mpeg_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv,
"ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
- chid, inst << 4, nouveau_client_name(engctx), stat,
+ chid, inst << 4, nvkm_client_name(engctx), stat,
type, mthd, data);
}
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
static void
-nv44_mpeg_me_intr(struct nouveau_subdev *subdev)
+nv44_mpeg_me_intr(struct nvkm_subdev *subdev)
{
struct nv44_mpeg_priv *priv = (void *)subdev;
u32 stat;
@@ -161,14 +153,14 @@ nv44_mpeg_me_intr(struct nouveau_subdev *subdev)
}
static int
-nv44_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv44_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv44_mpeg_priv *priv;
int ret;
- ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
+ ret = nvkm_mpeg_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -181,13 +173,13 @@ nv44_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv44_mpeg_oclass = {
.handle = NV_ENGINE(MPEG, 0x44),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv44_mpeg_ctor,
- .dtor = _nouveau_mpeg_dtor,
+ .dtor = _nvkm_mpeg_dtor,
.init = nv31_mpeg_init,
- .fini = _nouveau_mpeg_fini,
+ .fini = _nvkm_mpeg_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
index b62c301b31a1..b3463f3739ce 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
@@ -21,22 +21,17 @@
*
* Authors: Ben Skeggs
*/
+#include <engine/mpeg.h>
-#include <core/os.h>
-#include <core/engctx.h>
-
-#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/timer.h>
-#include <engine/mpeg.h>
-
struct nv50_mpeg_priv {
- struct nouveau_mpeg base;
+ struct nvkm_mpeg base;
};
struct nv50_mpeg_chan {
- struct nouveau_mpeg_chan base;
+ struct nvkm_mpeg_chan base;
};
/*******************************************************************************
@@ -44,16 +39,16 @@ struct nv50_mpeg_chan {
******************************************************************************/
static int
-nv50_mpeg_object_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_mpeg_object_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_gpuobj *obj;
+ struct nvkm_gpuobj *obj;
int ret;
- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
- 16, 16, 0, &obj);
+ ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
+ 16, 16, 0, &obj);
*pobject = nv_object(obj);
if (ret)
return ret;
@@ -65,17 +60,17 @@ nv50_mpeg_object_ctor(struct nouveau_object *parent,
return 0;
}
-struct nouveau_ofuncs
+struct nvkm_ofuncs
nv50_mpeg_ofuncs = {
.ctor = nv50_mpeg_object_ctor,
- .dtor = _nouveau_gpuobj_dtor,
- .init = _nouveau_gpuobj_init,
- .fini = _nouveau_gpuobj_fini,
- .rd32 = _nouveau_gpuobj_rd32,
- .wr32 = _nouveau_gpuobj_wr32,
+ .dtor = _nvkm_gpuobj_dtor,
+ .init = _nvkm_gpuobj_init,
+ .fini = _nvkm_gpuobj_fini,
+ .rd32 = _nvkm_gpuobj_rd32,
+ .wr32 = _nvkm_gpuobj_wr32,
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv50_mpeg_sclass[] = {
{ 0x3174, &nv50_mpeg_ofuncs },
{}
@@ -86,17 +81,17 @@ nv50_mpeg_sclass[] = {
******************************************************************************/
int
-nv50_mpeg_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_mpeg_context_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_bar *bar = nouveau_bar(parent);
+ struct nvkm_bar *bar = nvkm_bar(parent);
struct nv50_mpeg_chan *chan;
int ret;
- ret = nouveau_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4,
- 0, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4,
+ 0, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -107,16 +102,16 @@ nv50_mpeg_context_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv50_mpeg_cclass = {
.handle = NV_ENGCTX(MPEG, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_mpeg_context_ctor,
- .dtor = _nouveau_mpeg_context_dtor,
- .init = _nouveau_mpeg_context_init,
- .fini = _nouveau_mpeg_context_fini,
- .rd32 = _nouveau_mpeg_context_rd32,
- .wr32 = _nouveau_mpeg_context_wr32,
+ .dtor = _nvkm_mpeg_context_dtor,
+ .init = _nvkm_mpeg_context_init,
+ .fini = _nvkm_mpeg_context_fini,
+ .rd32 = _nvkm_mpeg_context_rd32,
+ .wr32 = _nvkm_mpeg_context_wr32,
},
};
@@ -125,7 +120,7 @@ nv50_mpeg_cclass = {
******************************************************************************/
void
-nv50_mpeg_intr(struct nouveau_subdev *subdev)
+nv50_mpeg_intr(struct nvkm_subdev *subdev)
{
struct nv50_mpeg_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, 0x00b100);
@@ -152,7 +147,7 @@ nv50_mpeg_intr(struct nouveau_subdev *subdev)
}
static void
-nv50_vpe_intr(struct nouveau_subdev *subdev)
+nv50_vpe_intr(struct nvkm_subdev *subdev)
{
struct nv50_mpeg_priv *priv = (void *)subdev;
@@ -167,14 +162,14 @@ nv50_vpe_intr(struct nouveau_subdev *subdev)
}
static int
-nv50_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_mpeg_priv *priv;
int ret;
- ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
+ ret = nvkm_mpeg_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -187,12 +182,12 @@ nv50_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
int
-nv50_mpeg_init(struct nouveau_object *object)
+nv50_mpeg_init(struct nvkm_object *object)
{
struct nv50_mpeg_priv *priv = (void *)object;
int ret;
- ret = nouveau_mpeg_init(&priv->base);
+ ret = nvkm_mpeg_init(&priv->base);
if (ret)
return ret;
@@ -218,13 +213,13 @@ nv50_mpeg_init(struct nouveau_object *object)
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv50_mpeg_oclass = {
.handle = NV_ENGINE(MPEG, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_mpeg_ctor,
- .dtor = _nouveau_mpeg_dtor,
+ .dtor = _nvkm_mpeg_dtor,
.init = nv50_mpeg_init,
- .fini = _nouveau_mpeg_fini,
+ .fini = _nvkm_mpeg_fini,
},
};
From e3332c20e016224f10e7ae3ccbaa630588c9004c Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:30:09 +1000
Subject: [PATCH 78/86] drm/nouveau/mspdec: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/engine/mspdec.h | 7 +-
.../drm/nouveau/nvkm/engine/device/gm100.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 14 ++--
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 ++---
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 ++--
.../gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild | 6 +-
.../nvkm/engine/mspdec/{nv98.c => g98.c} | 73 +++++++++----------
.../nvkm/engine/mspdec/{nvc0.c => gf100.c} | 73 +++++++++----------
.../nvkm/engine/mspdec/{nve0.c => gk104.c} | 73 +++++++++----------
9 files changed, 140 insertions(+), 142 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/mspdec/{nv98.c => g98.c} (61%)
rename drivers/gpu/drm/nouveau/nvkm/engine/mspdec/{nvc0.c => gf100.c} (61%)
rename drivers/gpu/drm/nouveau/nvkm/engine/mspdec/{nve0.c => gk104.c} (61%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
index 2457f871c2f7..54b7672eed9c 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
@@ -1,6 +1,7 @@
#ifndef __NVKM_MSPDEC_H__
#define __NVKM_MSPDEC_H__
-extern struct nouveau_oclass nv98_mspdec_oclass;
-extern struct nouveau_oclass nvc0_mspdec_oclass;
-extern struct nouveau_oclass nve0_mspdec_oclass;
+#include <core/engine.h>
+extern struct nvkm_oclass g98_mspdec_oclass;
+extern struct nvkm_oclass gf100_mspdec_oclass;
+extern struct nvkm_oclass gk104_mspdec_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index bcdc5bdd10cf..67db4e6ca489 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -95,7 +95,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
#if 0
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
#endif
break;
@@ -138,7 +138,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
#endif
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 2db202b1cc3a..9ea3a60ab417 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -254,7 +254,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
@@ -312,7 +312,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
@@ -341,7 +341,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
@@ -372,7 +372,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
@@ -402,7 +402,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
@@ -432,7 +432,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
@@ -462,7 +462,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 15ed4382e67e..ff39357a2bf2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -84,7 +84,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
@@ -117,7 +117,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
@@ -150,7 +150,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
@@ -182,7 +182,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
@@ -215,7 +215,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
@@ -247,7 +247,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
@@ -279,7 +279,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
@@ -312,7 +312,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
@@ -342,7 +342,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 6c3842ce034b..56c3e67b8962 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -89,7 +89,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
@@ -123,7 +123,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
@@ -157,7 +157,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
@@ -213,7 +213,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
@@ -247,7 +247,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
@@ -281,7 +281,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
break;
case 0x108:
@@ -314,7 +314,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild
index c05281cbd9b8..c59c83a67315 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild
@@ -1,3 +1,3 @@
-nvkm-y += nvkm/engine/mspdec/nv98.o
-nvkm-y += nvkm/engine/mspdec/nvc0.o
-nvkm-y += nvkm/engine/mspdec/nve0.o
+nvkm-y += nvkm/engine/mspdec/g98.o
+nvkm-y += nvkm/engine/mspdec/gf100.o
+nvkm-y += nvkm/engine/mspdec/gk104.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c
similarity index 61%
rename from drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c
index d47df06bb223..2174577793a4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c
@@ -21,22 +21,21 @@
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
-
-#include <engine/falcon.h>
#include <engine/mspdec.h>
+#include <engine/falcon.h>
-struct nv98_mspdec_priv {
- struct nouveau_falcon base;
+struct g98_mspdec_priv {
+ struct nvkm_falcon base;
};
/*******************************************************************************
* MSPDEC object classes
******************************************************************************/
-static struct nouveau_oclass
-nv98_mspdec_sclass[] = {
- { 0x88b2, &nouveau_object_ofuncs },
- { 0x85b2, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+g98_mspdec_sclass[] = {
+ { 0x88b2, &nvkm_object_ofuncs },
+ { 0x85b2, &nvkm_object_ofuncs },
{},
};
@@ -44,16 +43,16 @@ nv98_mspdec_sclass[] = {
* PMSPDEC context
******************************************************************************/
-static struct nouveau_oclass
-nv98_mspdec_cclass = {
+static struct nvkm_oclass
+g98_mspdec_cclass = {
.handle = NV_ENGCTX(MSPDEC, 0x98),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_falcon_context_ctor,
- .dtor = _nouveau_falcon_context_dtor,
- .init = _nouveau_falcon_context_init,
- .fini = _nouveau_falcon_context_fini,
- .rd32 = _nouveau_falcon_context_rd32,
- .wr32 = _nouveau_falcon_context_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_falcon_context_ctor,
+ .dtor = _nvkm_falcon_context_dtor,
+ .init = _nvkm_falcon_context_init,
+ .fini = _nvkm_falcon_context_fini,
+ .rd32 = _nvkm_falcon_context_rd32,
+ .wr32 = _nvkm_falcon_context_wr32,
},
};
@@ -62,12 +61,12 @@ nv98_mspdec_cclass = {
******************************************************************************/
static int
-nv98_mspdec_init(struct nouveau_object *object)
+g98_mspdec_init(struct nvkm_object *object)
{
- struct nv98_mspdec_priv *priv = (void *)object;
+ struct g98_mspdec_priv *priv = (void *)object;
int ret;
- ret = nouveau_falcon_init(&priv->base);
+ ret = nvkm_falcon_init(&priv->base);
if (ret)
return ret;
@@ -77,34 +76,34 @@ nv98_mspdec_init(struct nouveau_object *object)
}
static int
-nv98_mspdec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g98_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nv98_mspdec_priv *priv;
+ struct g98_mspdec_priv *priv;
int ret;
- ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,
- "PMSPDEC", "mspdec", &priv);
+ ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true,
+ "PMSPDEC", "mspdec", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x01020000;
- nv_engine(priv)->cclass = &nv98_mspdec_cclass;
- nv_engine(priv)->sclass = nv98_mspdec_sclass;
+ nv_engine(priv)->cclass = &g98_mspdec_cclass;
+ nv_engine(priv)->sclass = g98_mspdec_sclass;
return 0;
}
-struct nouveau_oclass
-nv98_mspdec_oclass = {
+struct nvkm_oclass
+g98_mspdec_oclass = {
.handle = NV_ENGINE(MSPDEC, 0x98),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv98_mspdec_ctor,
- .dtor = _nouveau_falcon_dtor,
- .init = nv98_mspdec_init,
- .fini = _nouveau_falcon_fini,
- .rd32 = _nouveau_falcon_rd32,
- .wr32 = _nouveau_falcon_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g98_mspdec_ctor,
+ .dtor = _nvkm_falcon_dtor,
+ .init = g98_mspdec_init,
+ .fini = _nvkm_falcon_fini,
+ .rd32 = _nvkm_falcon_rd32,
+ .wr32 = _nvkm_falcon_wr32,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c
similarity index 61%
rename from drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c
index c622010a6722..c814a5f65eb0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c
@@ -21,21 +21,20 @@
*
* Authors: Maarten Lankhorst
*/
-
-#include <engine/falcon.h>
#include <engine/mspdec.h>
+#include <engine/falcon.h>
-struct nvc0_mspdec_priv {
- struct nouveau_falcon base;
+struct gf100_mspdec_priv {
+ struct nvkm_falcon base;
};
/*******************************************************************************
* MSPDEC object classes
******************************************************************************/
-static struct nouveau_oclass
-nvc0_mspdec_sclass[] = {
- { 0x90b2, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+gf100_mspdec_sclass[] = {
+ { 0x90b2, &nvkm_object_ofuncs },
{},
};
@@ -43,16 +42,16 @@ nvc0_mspdec_sclass[] = {
* PMSPDEC context
******************************************************************************/
-static struct nouveau_oclass
-nvc0_mspdec_cclass = {
+static struct nvkm_oclass
+gf100_mspdec_cclass = {
.handle = NV_ENGCTX(MSPDEC, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_falcon_context_ctor,
- .dtor = _nouveau_falcon_context_dtor,
- .init = _nouveau_falcon_context_init,
- .fini = _nouveau_falcon_context_fini,
- .rd32 = _nouveau_falcon_context_rd32,
- .wr32 = _nouveau_falcon_context_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_falcon_context_ctor,
+ .dtor = _nvkm_falcon_context_dtor,
+ .init = _nvkm_falcon_context_init,
+ .fini = _nvkm_falcon_context_fini,
+ .rd32 = _nvkm_falcon_context_rd32,
+ .wr32 = _nvkm_falcon_context_wr32,
},
};
@@ -61,12 +60,12 @@ nvc0_mspdec_cclass = {
******************************************************************************/
static int
-nvc0_mspdec_init(struct nouveau_object *object)
+gf100_mspdec_init(struct nvkm_object *object)
{
- struct nvc0_mspdec_priv *priv = (void *)object;
+ struct gf100_mspdec_priv *priv = (void *)object;
int ret;
- ret = nouveau_falcon_init(&priv->base);
+ ret = nvkm_falcon_init(&priv->base);
if (ret)
return ret;
@@ -76,35 +75,35 @@ nvc0_mspdec_init(struct nouveau_object *object)
}
static int
-nvc0_mspdec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvc0_mspdec_priv *priv;
+ struct gf100_mspdec_priv *priv;
int ret;
- ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,
- "PMSPDEC", "mspdec", &priv);
+ ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true,
+ "PMSPDEC", "mspdec", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00020000;
- nv_subdev(priv)->intr = nouveau_falcon_intr;
- nv_engine(priv)->cclass = &nvc0_mspdec_cclass;
- nv_engine(priv)->sclass = nvc0_mspdec_sclass;
+ nv_subdev(priv)->intr = nvkm_falcon_intr;
+ nv_engine(priv)->cclass = &gf100_mspdec_cclass;
+ nv_engine(priv)->sclass = gf100_mspdec_sclass;
return 0;
}
-struct nouveau_oclass
-nvc0_mspdec_oclass = {
+struct nvkm_oclass
+gf100_mspdec_oclass = {
.handle = NV_ENGINE(MSPDEC, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_mspdec_ctor,
- .dtor = _nouveau_falcon_dtor,
- .init = nvc0_mspdec_init,
- .fini = _nouveau_falcon_fini,
- .rd32 = _nouveau_falcon_rd32,
- .wr32 = _nouveau_falcon_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_mspdec_ctor,
+ .dtor = _nvkm_falcon_dtor,
+ .init = gf100_mspdec_init,
+ .fini = _nvkm_falcon_fini,
+ .rd32 = _nvkm_falcon_rd32,
+ .wr32 = _nvkm_falcon_wr32,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c
similarity index 61%
rename from drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c
index 84108b5728f9..979920650dbd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c
@@ -21,21 +21,20 @@
*
* Authors: Ben Skeggs
*/
-
-#include <engine/falcon.h>
#include <engine/mspdec.h>
+#include <engine/falcon.h>
-struct nve0_mspdec_priv {
- struct nouveau_falcon base;
+struct gk104_mspdec_priv {
+ struct nvkm_falcon base;
};
/*******************************************************************************
* MSPDEC object classes
******************************************************************************/
-static struct nouveau_oclass
-nve0_mspdec_sclass[] = {
- { 0x95b2, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+gk104_mspdec_sclass[] = {
+ { 0x95b2, &nvkm_object_ofuncs },
{},
};
@@ -43,16 +42,16 @@ nve0_mspdec_sclass[] = {
* PMSPDEC context
******************************************************************************/
-static struct nouveau_oclass
-nve0_mspdec_cclass = {
+static struct nvkm_oclass
+gk104_mspdec_cclass = {
.handle = NV_ENGCTX(MSPDEC, 0xe0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_falcon_context_ctor,
- .dtor = _nouveau_falcon_context_dtor,
- .init = _nouveau_falcon_context_init,
- .fini = _nouveau_falcon_context_fini,
- .rd32 = _nouveau_falcon_context_rd32,
- .wr32 = _nouveau_falcon_context_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_falcon_context_ctor,
+ .dtor = _nvkm_falcon_context_dtor,
+ .init = _nvkm_falcon_context_init,
+ .fini = _nvkm_falcon_context_fini,
+ .rd32 = _nvkm_falcon_context_rd32,
+ .wr32 = _nvkm_falcon_context_wr32,
},
};
@@ -61,12 +60,12 @@ nve0_mspdec_cclass = {
******************************************************************************/
static int
-nve0_mspdec_init(struct nouveau_object *object)
+gk104_mspdec_init(struct nvkm_object *object)
{
- struct nve0_mspdec_priv *priv = (void *)object;
+ struct gk104_mspdec_priv *priv = (void *)object;
int ret;
- ret = nouveau_falcon_init(&priv->base);
+ ret = nvkm_falcon_init(&priv->base);
if (ret)
return ret;
@@ -76,35 +75,35 @@ nve0_mspdec_init(struct nouveau_object *object)
}
static int
-nve0_mspdec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk104_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nve0_mspdec_priv *priv;
+ struct gk104_mspdec_priv *priv;
int ret;
- ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,
- "PMSPDEC", "mspdec", &priv);
+ ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true,
+ "PMSPDEC", "mspdec", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00020000;
- nv_subdev(priv)->intr = nouveau_falcon_intr;
- nv_engine(priv)->cclass = &nve0_mspdec_cclass;
- nv_engine(priv)->sclass = nve0_mspdec_sclass;
+ nv_subdev(priv)->intr = nvkm_falcon_intr;
+ nv_engine(priv)->cclass = &gk104_mspdec_cclass;
+ nv_engine(priv)->sclass = gk104_mspdec_sclass;
return 0;
}
-struct nouveau_oclass
-nve0_mspdec_oclass = {
+struct nvkm_oclass
+gk104_mspdec_oclass = {
.handle = NV_ENGINE(MSPDEC, 0xe0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_mspdec_ctor,
- .dtor = _nouveau_falcon_dtor,
- .init = nve0_mspdec_init,
- .fini = _nouveau_falcon_fini,
- .rd32 = _nouveau_falcon_rd32,
- .wr32 = _nouveau_falcon_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_mspdec_ctor,
+ .dtor = _nvkm_falcon_dtor,
+ .init = gk104_mspdec_init,
+ .fini = _nvkm_falcon_fini,
+ .rd32 = _nvkm_falcon_rd32,
+ .wr32 = _nvkm_falcon_wr32,
},
};
From 87a876579abd1df8479ad90974492ec0a145d165 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:30:22 +1000
Subject: [PATCH 79/86] drm/nouveau/msppp: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/engine/msppp.h | 11 ++-
.../drm/nouveau/nvkm/engine/device/gm100.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 14 ++--
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 ++---
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 ++--
.../gpu/drm/nouveau/nvkm/engine/msppp/Kbuild | 4 +-
.../nvkm/engine/msppp/{nv98.c => g98.c} | 73 +++++++++----------
.../nvkm/engine/msppp/{nvc0.c => gf100.c} | 73 +++++++++----------
8 files changed, 104 insertions(+), 107 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/msppp/{nv98.c => g98.c} (62%)
rename drivers/gpu/drm/nouveau/nvkm/engine/msppp/{nvc0.c => gf100.c} (61%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
index 5f2f82ed9598..c6c69d0a8d01 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
@@ -1,7 +1,6 @@
-#ifndef __NOUVEAU_MSPPP_H__
-#define __NOUVEAU_MSPPP_H__
-
-extern struct nouveau_oclass nv98_msppp_oclass;
-extern struct nouveau_oclass nvc0_msppp_oclass;
-
+#ifndef __NVKM_MSPPP_H__
+#define __NVKM_MSPPP_H__
+#include <core/engine.h>
+extern struct nvkm_oclass g98_msppp_oclass;
+extern struct nvkm_oclass gf100_msppp_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 67db4e6ca489..a5a9c8bf8f0d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -96,7 +96,7 @@ gm100_identify(struct nouveau_device *device)
#if 0
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
#endif
break;
case 0x124:
@@ -139,7 +139,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
#endif
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 9ea3a60ab417..a7838a7c1901 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -257,7 +257,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@@ -315,7 +315,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@@ -344,7 +344,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@@ -374,7 +374,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
@@ -404,7 +404,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
@@ -434,7 +434,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
@@ -464,7 +464,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index ff39357a2bf2..83dd982b1c4c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -86,7 +86,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@@ -119,7 +119,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@@ -152,7 +152,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
@@ -184,7 +184,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@@ -217,7 +217,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
@@ -249,7 +249,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
@@ -281,7 +281,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@@ -314,7 +314,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
@@ -344,7 +344,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 56c3e67b8962..5676a0251c79 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -90,7 +90,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
case 0xe7:
@@ -124,7 +124,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
case 0xe6:
@@ -158,7 +158,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
case 0xea:
@@ -214,7 +214,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
case 0xf1:
@@ -248,7 +248,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
case 0x106:
@@ -282,7 +282,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
break;
case 0x108:
device->cname = "GK208";
@@ -315,7 +315,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
break;
default:
nv_fatal(device, "unknown Kepler chipset\n");
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
index 9b90ce948425..4576a9eee39d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
@@ -1,2 +1,2 @@
-nvkm-y += nvkm/engine/msppp/nv98.o
-nvkm-y += nvkm/engine/msppp/nvc0.o
+nvkm-y += nvkm/engine/msppp/g98.o
+nvkm-y += nvkm/engine/msppp/gf100.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c
similarity index 62%
rename from drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c
index c044943c3fc7..7a602a2dec94 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c
@@ -21,22 +21,21 @@
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
-
-#include <engine/falcon.h>
#include <engine/msppp.h>
+#include <engine/falcon.h>
-struct nv98_msppp_priv {
- struct nouveau_falcon base;
+struct g98_msppp_priv {
+ struct nvkm_falcon base;
};
/*******************************************************************************
* MSPPP object classes
******************************************************************************/
-static struct nouveau_oclass
-nv98_msppp_sclass[] = {
- { 0x88b3, &nouveau_object_ofuncs },
- { 0x85b3, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+g98_msppp_sclass[] = {
+ { 0x88b3, &nvkm_object_ofuncs },
+ { 0x85b3, &nvkm_object_ofuncs },
{},
};
@@ -44,16 +43,16 @@ nv98_msppp_sclass[] = {
* PMSPPP context
******************************************************************************/
-static struct nouveau_oclass
-nv98_msppp_cclass = {
+static struct nvkm_oclass
+g98_msppp_cclass = {
.handle = NV_ENGCTX(MSPPP, 0x98),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_falcon_context_ctor,
- .dtor = _nouveau_falcon_context_dtor,
- .init = _nouveau_falcon_context_init,
- .fini = _nouveau_falcon_context_fini,
- .rd32 = _nouveau_falcon_context_rd32,
- .wr32 = _nouveau_falcon_context_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_falcon_context_ctor,
+ .dtor = _nvkm_falcon_context_dtor,
+ .init = _nvkm_falcon_context_init,
+ .fini = _nvkm_falcon_context_fini,
+ .rd32 = _nvkm_falcon_context_rd32,
+ .wr32 = _nvkm_falcon_context_wr32,
},
};
@@ -62,12 +61,12 @@ nv98_msppp_cclass = {
******************************************************************************/
static int
-nv98_msppp_init(struct nouveau_object *object)
+g98_msppp_init(struct nvkm_object *object)
{
- struct nv98_msppp_priv *priv = (void *)object;
+ struct g98_msppp_priv *priv = (void *)object;
int ret;
- ret = nouveau_falcon_init(&priv->base);
+ ret = nvkm_falcon_init(&priv->base);
if (ret)
return ret;
@@ -77,34 +76,34 @@ nv98_msppp_init(struct nouveau_object *object)
}
static int
-nv98_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g98_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nv98_msppp_priv *priv;
+ struct g98_msppp_priv *priv;
int ret;
- ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
- "PMSPPP", "msppp", &priv);
+ ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true,
+ "PMSPPP", "msppp", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00400002;
- nv_engine(priv)->cclass = &nv98_msppp_cclass;
- nv_engine(priv)->sclass = nv98_msppp_sclass;
+ nv_engine(priv)->cclass = &g98_msppp_cclass;
+ nv_engine(priv)->sclass = g98_msppp_sclass;
return 0;
}
-struct nouveau_oclass
-nv98_msppp_oclass = {
+struct nvkm_oclass
+g98_msppp_oclass = {
.handle = NV_ENGINE(MSPPP, 0x98),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv98_msppp_ctor,
- .dtor = _nouveau_falcon_dtor,
- .init = nv98_msppp_init,
- .fini = _nouveau_falcon_fini,
- .rd32 = _nouveau_falcon_rd32,
- .wr32 = _nouveau_falcon_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g98_msppp_ctor,
+ .dtor = _nvkm_falcon_dtor,
+ .init = g98_msppp_init,
+ .fini = _nvkm_falcon_fini,
+ .rd32 = _nvkm_falcon_rd32,
+ .wr32 = _nvkm_falcon_wr32,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c
similarity index 61%
rename from drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c
index 91398e639395..6047baee1f75 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c
@@ -21,21 +21,20 @@
*
* Authors: Maarten Lankhorst
*/
-
-#include <engine/falcon.h>
#include <engine/msppp.h>
+#include <engine/falcon.h>
-struct nvc0_msppp_priv {
- struct nouveau_falcon base;
+struct gf100_msppp_priv {
+ struct nvkm_falcon base;
};
/*******************************************************************************
* MSPPP object classes
******************************************************************************/
-static struct nouveau_oclass
-nvc0_msppp_sclass[] = {
- { 0x90b3, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+gf100_msppp_sclass[] = {
+ { 0x90b3, &nvkm_object_ofuncs },
{},
};
@@ -43,16 +42,16 @@ nvc0_msppp_sclass[] = {
* PMSPPP context
******************************************************************************/
-static struct nouveau_oclass
-nvc0_msppp_cclass = {
+static struct nvkm_oclass
+gf100_msppp_cclass = {
.handle = NV_ENGCTX(MSPPP, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_falcon_context_ctor,
- .dtor = _nouveau_falcon_context_dtor,
- .init = _nouveau_falcon_context_init,
- .fini = _nouveau_falcon_context_fini,
- .rd32 = _nouveau_falcon_context_rd32,
- .wr32 = _nouveau_falcon_context_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_falcon_context_ctor,
+ .dtor = _nvkm_falcon_context_dtor,
+ .init = _nvkm_falcon_context_init,
+ .fini = _nvkm_falcon_context_fini,
+ .rd32 = _nvkm_falcon_context_rd32,
+ .wr32 = _nvkm_falcon_context_wr32,
},
};
@@ -61,12 +60,12 @@ nvc0_msppp_cclass = {
******************************************************************************/
static int
-nvc0_msppp_init(struct nouveau_object *object)
+gf100_msppp_init(struct nvkm_object *object)
{
- struct nvc0_msppp_priv *priv = (void *)object;
+ struct gf100_msppp_priv *priv = (void *)object;
int ret;
- ret = nouveau_falcon_init(&priv->base);
+ ret = nvkm_falcon_init(&priv->base);
if (ret)
return ret;
@@ -76,35 +75,35 @@ nvc0_msppp_init(struct nouveau_object *object)
}
static int
-nvc0_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvc0_msppp_priv *priv;
+ struct gf100_msppp_priv *priv;
int ret;
- ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
- "PMSPPP", "msppp", &priv);
+ ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true,
+ "PMSPPP", "msppp", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000002;
- nv_subdev(priv)->intr = nouveau_falcon_intr;
- nv_engine(priv)->cclass = &nvc0_msppp_cclass;
- nv_engine(priv)->sclass = nvc0_msppp_sclass;
+ nv_subdev(priv)->intr = nvkm_falcon_intr;
+ nv_engine(priv)->cclass = &gf100_msppp_cclass;
+ nv_engine(priv)->sclass = gf100_msppp_sclass;
return 0;
}
-struct nouveau_oclass
-nvc0_msppp_oclass = {
+struct nvkm_oclass
+gf100_msppp_oclass = {
.handle = NV_ENGINE(MSPPP, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_msppp_ctor,
- .dtor = _nouveau_falcon_dtor,
- .init = nvc0_msppp_init,
- .fini = _nouveau_falcon_fini,
- .rd32 = _nouveau_falcon_rd32,
- .wr32 = _nouveau_falcon_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_msppp_ctor,
+ .dtor = _nvkm_falcon_dtor,
+ .init = gf100_msppp_init,
+ .fini = _nvkm_falcon_fini,
+ .rd32 = _nvkm_falcon_rd32,
+ .wr32 = _nvkm_falcon_wr32,
},
};
From 87c33f4e9f962f7facab0077f45b2cb21f46d03a Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:30:40 +1000
Subject: [PATCH 80/86] drm/nouveau/msvld: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drm/nouveau/include/nvkm/engine/msvld.h | 7 +-
.../drm/nouveau/nvkm/engine/device/gm100.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 14 ++--
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 ++---
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 14 ++--
.../gpu/drm/nouveau/nvkm/engine/msvld/Kbuild | 6 +-
.../nvkm/engine/msvld/{nv98.c => g98.c} | 75 +++++++++----------
.../nvkm/engine/msvld/{nvc0.c => gf100.c} | 73 +++++++++---------
.../nvkm/engine/msvld/{nve0.c => gk104.c} | 73 +++++++++---------
9 files changed, 141 insertions(+), 143 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/msvld/{nv98.c => g98.c} (61%)
rename drivers/gpu/drm/nouveau/nvkm/engine/msvld/{nvc0.c => gf100.c} (63%)
rename drivers/gpu/drm/nouveau/nvkm/engine/msvld/{nve0.c => gk104.c} (61%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
index f031bb9de74c..1f193b7bd6c5 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
@@ -1,6 +1,7 @@
#ifndef __NVKM_MSVLD_H__
#define __NVKM_MSVLD_H__
-extern struct nouveau_oclass nv98_msvld_oclass;
-extern struct nouveau_oclass nvc0_msvld_oclass;
-extern struct nouveau_oclass nve0_msvld_oclass;
+#include <core/engine.h>
+extern struct nvkm_oclass g98_msvld_oclass;
+extern struct nvkm_oclass gf100_msvld_oclass;
+extern struct nvkm_oclass gk104_msvld_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index a5a9c8bf8f0d..4c45f57e81d4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -94,7 +94,7 @@ gm100_identify(struct nouveau_device *device)
#endif
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
#if 0
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
#endif
@@ -137,7 +137,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index a7838a7c1901..ef87c7ec5812 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -256,7 +256,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
@@ -314,7 +314,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
@@ -343,7 +343,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
@@ -373,7 +373,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@@ -403,7 +403,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@@ -433,7 +433,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@@ -463,7 +463,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 83dd982b1c4c..c8ac22e98c87 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -85,7 +85,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
@@ -118,7 +118,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
@@ -151,7 +151,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@@ -183,7 +183,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
@@ -216,7 +216,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@@ -248,7 +248,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@@ -280,7 +280,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
@@ -313,7 +313,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
@@ -343,7 +343,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 5676a0251c79..d0894674be44 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -88,7 +88,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
@@ -122,7 +122,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
@@ -156,7 +156,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
@@ -212,7 +212,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
@@ -246,7 +246,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
@@ -280,7 +280,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
break;
@@ -313,7 +313,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
- device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
+ device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild
index 1deb463a2b0b..0c9811009e28 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild
@@ -1,3 +1,3 @@
-nvkm-y += nvkm/engine/msvld/nv98.o
-nvkm-y += nvkm/engine/msvld/nvc0.o
-nvkm-y += nvkm/engine/msvld/nve0.o
+nvkm-y += nvkm/engine/msvld/g98.o
+nvkm-y += nvkm/engine/msvld/gf100.o
+nvkm-y += nvkm/engine/msvld/gk104.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c
similarity index 61%
rename from drivers/gpu/drm/nouveau/nvkm/engine/msvld/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c
index 4bafba59226c..c8a6b4ef52a1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c
@@ -21,23 +21,22 @@
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
-
-#include <engine/falcon.h>
#include <engine/msvld.h>
+#include <engine/falcon.h>
-struct nv98_msvld_priv {
- struct nouveau_falcon base;
+struct g98_msvld_priv {
+ struct nvkm_falcon base;
};
/*******************************************************************************
* MSVLD object classes
******************************************************************************/
-static struct nouveau_oclass
-nv98_msvld_sclass[] = {
- { 0x88b1, &nouveau_object_ofuncs },
- { 0x85b1, &nouveau_object_ofuncs },
- { 0x86b1, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+g98_msvld_sclass[] = {
+ { 0x88b1, &nvkm_object_ofuncs },
+ { 0x85b1, &nvkm_object_ofuncs },
+ { 0x86b1, &nvkm_object_ofuncs },
{},
};
@@ -45,16 +44,16 @@ nv98_msvld_sclass[] = {
* PMSVLD context
******************************************************************************/
-static struct nouveau_oclass
-nv98_msvld_cclass = {
+static struct nvkm_oclass
+g98_msvld_cclass = {
.handle = NV_ENGCTX(MSVLD, 0x98),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_falcon_context_ctor,
- .dtor = _nouveau_falcon_context_dtor,
- .init = _nouveau_falcon_context_init,
- .fini = _nouveau_falcon_context_fini,
- .rd32 = _nouveau_falcon_context_rd32,
- .wr32 = _nouveau_falcon_context_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_falcon_context_ctor,
+ .dtor = _nvkm_falcon_context_dtor,
+ .init = _nvkm_falcon_context_init,
+ .fini = _nvkm_falcon_context_fini,
+ .rd32 = _nvkm_falcon_context_rd32,
+ .wr32 = _nvkm_falcon_context_wr32,
},
};
@@ -63,12 +62,12 @@ nv98_msvld_cclass = {
******************************************************************************/
static int
-nv98_msvld_init(struct nouveau_object *object)
+g98_msvld_init(struct nvkm_object *object)
{
- struct nv98_msvld_priv *priv = (void *)object;
+ struct g98_msvld_priv *priv = (void *)object;
int ret;
- ret = nouveau_falcon_init(&priv->base);
+ ret = nvkm_falcon_init(&priv->base);
if (ret)
return ret;
@@ -78,34 +77,34 @@ nv98_msvld_init(struct nouveau_object *object)
}
static int
-nv98_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g98_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nv98_msvld_priv *priv;
+ struct g98_msvld_priv *priv;
int ret;
- ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
- "PMSVLD", "msvld", &priv);
+ ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true,
+ "PMSVLD", "msvld", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x04008000;
- nv_engine(priv)->cclass = &nv98_msvld_cclass;
- nv_engine(priv)->sclass = nv98_msvld_sclass;
+ nv_engine(priv)->cclass = &g98_msvld_cclass;
+ nv_engine(priv)->sclass = g98_msvld_sclass;
return 0;
}
-struct nouveau_oclass
-nv98_msvld_oclass = {
+struct nvkm_oclass
+g98_msvld_oclass = {
.handle = NV_ENGINE(MSVLD, 0x98),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv98_msvld_ctor,
- .dtor = _nouveau_falcon_dtor,
- .init = nv98_msvld_init,
- .fini = _nouveau_falcon_fini,
- .rd32 = _nouveau_falcon_rd32,
- .wr32 = _nouveau_falcon_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g98_msvld_ctor,
+ .dtor = _nvkm_falcon_dtor,
+ .init = g98_msvld_init,
+ .fini = _nvkm_falcon_fini,
+ .rd32 = _nvkm_falcon_rd32,
+ .wr32 = _nvkm_falcon_wr32,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c
similarity index 63%
rename from drivers/gpu/drm/nouveau/nvkm/engine/msvld/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c
index fd2ac0d620c6..b8d1e0f521ef 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c
@@ -21,21 +21,20 @@
*
* Authors: Maarten Lankhorst
*/
-
-#include <engine/falcon.h>
#include <engine/msvld.h>
+#include <engine/falcon.h>
-struct nvc0_msvld_priv {
- struct nouveau_falcon base;
+struct gf100_msvld_priv {
+ struct nvkm_falcon base;
};
/*******************************************************************************
* MSVLD object classes
******************************************************************************/
-static struct nouveau_oclass
-nvc0_msvld_sclass[] = {
- { 0x90b1, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+gf100_msvld_sclass[] = {
+ { 0x90b1, &nvkm_object_ofuncs },
{},
};
@@ -43,16 +42,16 @@ nvc0_msvld_sclass[] = {
* PMSVLD context
******************************************************************************/
-static struct nouveau_oclass
-nvc0_msvld_cclass = {
+static struct nvkm_oclass
+gf100_msvld_cclass = {
.handle = NV_ENGCTX(MSVLD, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_falcon_context_ctor,
- .dtor = _nouveau_falcon_context_dtor,
- .init = _nouveau_falcon_context_init,
- .fini = _nouveau_falcon_context_fini,
- .rd32 = _nouveau_falcon_context_rd32,
- .wr32 = _nouveau_falcon_context_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_falcon_context_ctor,
+ .dtor = _nvkm_falcon_context_dtor,
+ .init = _nvkm_falcon_context_init,
+ .fini = _nvkm_falcon_context_fini,
+ .rd32 = _nvkm_falcon_context_rd32,
+ .wr32 = _nvkm_falcon_context_wr32,
},
};
@@ -61,12 +60,12 @@ nvc0_msvld_cclass = {
******************************************************************************/
static int
-nvc0_msvld_init(struct nouveau_object *object)
+gf100_msvld_init(struct nvkm_object *object)
{
- struct nvc0_msvld_priv *priv = (void *)object;
+ struct gf100_msvld_priv *priv = (void *)object;
int ret;
- ret = nouveau_falcon_init(&priv->base);
+ ret = nvkm_falcon_init(&priv->base);
if (ret)
return ret;
@@ -76,35 +75,35 @@ nvc0_msvld_init(struct nouveau_object *object)
}
static int
-nvc0_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvc0_msvld_priv *priv;
+ struct gf100_msvld_priv *priv;
int ret;
- ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
- "PMSVLD", "msvld", &priv);
+ ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true,
+ "PMSVLD", "msvld", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00008000;
- nv_subdev(priv)->intr = nouveau_falcon_intr;
- nv_engine(priv)->cclass = &nvc0_msvld_cclass;
- nv_engine(priv)->sclass = nvc0_msvld_sclass;
+ nv_subdev(priv)->intr = nvkm_falcon_intr;
+ nv_engine(priv)->cclass = &gf100_msvld_cclass;
+ nv_engine(priv)->sclass = gf100_msvld_sclass;
return 0;
}
-struct nouveau_oclass
-nvc0_msvld_oclass = {
+struct nvkm_oclass
+gf100_msvld_oclass = {
.handle = NV_ENGINE(MSVLD, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_msvld_ctor,
- .dtor = _nouveau_falcon_dtor,
- .init = nvc0_msvld_init,
- .fini = _nouveau_falcon_fini,
- .rd32 = _nouveau_falcon_rd32,
- .wr32 = _nouveau_falcon_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_msvld_ctor,
+ .dtor = _nvkm_falcon_dtor,
+ .init = gf100_msvld_init,
+ .fini = _nvkm_falcon_fini,
+ .rd32 = _nvkm_falcon_rd32,
+ .wr32 = _nvkm_falcon_wr32,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c
similarity index 61%
rename from drivers/gpu/drm/nouveau/nvkm/engine/msvld/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c
index 4b3d3ca80eff..a0b0927834df 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c
@@ -21,21 +21,20 @@
*
* Authors: Ben Skeggs
*/
-
-#include <engine/falcon.h>
#include <engine/msvld.h>
+#include <engine/falcon.h>
-struct nve0_msvld_priv {
- struct nouveau_falcon base;
+struct gk104_msvld_priv {
+ struct nvkm_falcon base;
};
/*******************************************************************************
* MSVLD object classes
******************************************************************************/
-static struct nouveau_oclass
-nve0_msvld_sclass[] = {
- { 0x95b1, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+gk104_msvld_sclass[] = {
+ { 0x95b1, &nvkm_object_ofuncs },
{},
};
@@ -43,16 +42,16 @@ nve0_msvld_sclass[] = {
* PMSVLD context
******************************************************************************/
-static struct nouveau_oclass
-nve0_msvld_cclass = {
+static struct nvkm_oclass
+gk104_msvld_cclass = {
.handle = NV_ENGCTX(MSVLD, 0xe0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_falcon_context_ctor,
- .dtor = _nouveau_falcon_context_dtor,
- .init = _nouveau_falcon_context_init,
- .fini = _nouveau_falcon_context_fini,
- .rd32 = _nouveau_falcon_context_rd32,
- .wr32 = _nouveau_falcon_context_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_falcon_context_ctor,
+ .dtor = _nvkm_falcon_context_dtor,
+ .init = _nvkm_falcon_context_init,
+ .fini = _nvkm_falcon_context_fini,
+ .rd32 = _nvkm_falcon_context_rd32,
+ .wr32 = _nvkm_falcon_context_wr32,
},
};
@@ -61,12 +60,12 @@ nve0_msvld_cclass = {
******************************************************************************/
static int
-nve0_msvld_init(struct nouveau_object *object)
+gk104_msvld_init(struct nvkm_object *object)
{
- struct nve0_msvld_priv *priv = (void *)object;
+ struct gk104_msvld_priv *priv = (void *)object;
int ret;
- ret = nouveau_falcon_init(&priv->base);
+ ret = nvkm_falcon_init(&priv->base);
if (ret)
return ret;
@@ -76,35 +75,35 @@ nve0_msvld_init(struct nouveau_object *object)
}
static int
-nve0_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk104_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nve0_msvld_priv *priv;
+ struct gk104_msvld_priv *priv;
int ret;
- ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
- "PMSVLD", "msvld", &priv);
+ ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true,
+ "PMSVLD", "msvld", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00008000;
- nv_subdev(priv)->intr = nouveau_falcon_intr;
- nv_engine(priv)->cclass = &nve0_msvld_cclass;
- nv_engine(priv)->sclass = nve0_msvld_sclass;
+ nv_subdev(priv)->intr = nvkm_falcon_intr;
+ nv_engine(priv)->cclass = &gk104_msvld_cclass;
+ nv_engine(priv)->sclass = gk104_msvld_sclass;
return 0;
}
-struct nouveau_oclass
-nve0_msvld_oclass = {
+struct nvkm_oclass
+gk104_msvld_oclass = {
.handle = NV_ENGINE(MSVLD, 0xe0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_msvld_ctor,
- .dtor = _nouveau_falcon_dtor,
- .init = nve0_msvld_init,
- .fini = _nouveau_falcon_fini,
- .rd32 = _nouveau_falcon_rd32,
- .wr32 = _nouveau_falcon_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_msvld_ctor,
+ .dtor = _nvkm_falcon_dtor,
+ .init = gk104_msvld_init,
+ .fini = _nvkm_falcon_fini,
+ .rd32 = _nvkm_falcon_rd32,
+ .wr32 = _nvkm_falcon_wr32,
},
};
From 4d34686eb607037dafffb9d66d9e50b4648cfda4 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:31:13 +1000
Subject: [PATCH 81/86] drm/nouveau/pm: namespace + nvidia gpu names (no binary
change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/engine/pm.h | 34 ++-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 26 +--
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +-
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 12 +-
drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild | 10 +-
drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c | 203 +++++++++---------
.../gpu/drm/nouveau/nvkm/engine/pm/daemon.c | 31 ++-
.../nouveau/nvkm/engine/pm/{nv84.c => g84.c} | 47 ++--
.../nvkm/engine/pm/{nvc0.c => gf100.c} | 106 ++++-----
.../gpu/drm/nouveau/nvkm/engine/pm/gf100.h | 15 ++
.../gpu/drm/nouveau/nvkm/engine/pm/gk104.c | 148 +++++++++++++
.../nvkm/engine/pm/{nvf0.c => gk110.c} | 46 ++--
.../nvkm/engine/pm/{nva3.c => gt215.c} | 59 ++---
drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c | 61 +++---
drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h | 18 +-
drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c | 35 +--
drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.h | 17 --
drivers/gpu/drm/nouveau/nvkm/engine/pm/nve0.c | 162 --------------
drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h | 95 ++++----
19 files changed, 516 insertions(+), 627 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/pm/{nv84.c => g84.c} (56%)
rename drivers/gpu/drm/nouveau/nvkm/engine/pm/{nvc0.c => gf100.c} (52%)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h
create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c
rename drivers/gpu/drm/nouveau/nvkm/engine/pm/{nvf0.c => gk110.c} (52%)
rename drivers/gpu/drm/nouveau/nvkm/engine/pm/{nva3.c => gt215.c} (53%)
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.h
delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/pm/nve0.c
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
index c9ffe2c70746..93181bbf0f63 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
@@ -1,16 +1,13 @@
#ifndef __NVKM_PM_H__
#define __NVKM_PM_H__
-
-#include <core/device.h>
#include <core/engine.h>
-#include <core/engctx.h>
-struct nouveau_perfdom;
-struct nouveau_perfctr;
-struct nouveau_pm {
- struct nouveau_engine base;
+struct nvkm_perfdom;
+struct nvkm_perfctr;
+struct nvkm_pm {
+ struct nvkm_engine base;
- struct nouveau_perfctx *context;
+ struct nvkm_perfctx *context;
void *profile_data;
struct list_head domains;
@@ -21,18 +18,17 @@ struct nouveau_pm {
u32 last;
};
-static inline struct nouveau_pm *
-nouveau_pm(void *obj)
+static inline struct nvkm_pm *
+nvkm_pm(void *obj)
{
- return (void *)nouveau_engine(obj, NVDEV_ENGINE_PM);
+ return (void *)nvkm_engine(obj, NVDEV_ENGINE_PM);
}
-extern struct nouveau_oclass *nv40_pm_oclass;
-extern struct nouveau_oclass *nv50_pm_oclass;
-extern struct nouveau_oclass *nv84_pm_oclass;
-extern struct nouveau_oclass *nva3_pm_oclass;
-extern struct nouveau_oclass nvc0_pm_oclass;
-extern struct nouveau_oclass nve0_pm_oclass;
-extern struct nouveau_oclass nvf0_pm_oclass;
-
+extern struct nvkm_oclass *nv40_pm_oclass;
+extern struct nvkm_oclass *nv50_pm_oclass;
+extern struct nvkm_oclass *g84_pm_oclass;
+extern struct nvkm_oclass *gt215_pm_oclass;
+extern struct nvkm_oclass gf100_pm_oclass;
+extern struct nvkm_oclass gk104_pm_oclass;
+extern struct nvkm_oclass gk110_pm_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index ef87c7ec5812..4bbd6b7ac997 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -114,7 +114,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x86:
device->cname = "G86";
@@ -143,7 +143,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x92:
device->cname = "G92";
@@ -172,7 +172,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x94:
device->cname = "G94";
@@ -201,7 +201,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x96:
device->cname = "G96";
@@ -230,7 +230,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x98:
device->cname = "G98";
@@ -259,7 +259,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa0:
device->cname = "G200";
@@ -288,7 +288,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xaa:
device->cname = "MCP77/MCP78";
@@ -317,7 +317,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xac:
device->cname = "MCP79/MCP7A";
@@ -346,7 +346,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa3:
device->cname = "GT215";
@@ -377,7 +377,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa5:
device->cname = "GT216";
@@ -407,7 +407,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa8:
device->cname = "GT218";
@@ -437,7 +437,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xaf:
device->cname = "MCP89";
@@ -467,7 +467,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
default:
nv_fatal(device, "unknown Tesla chipset\n");
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index c8ac22e98c87..a97671c4338e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -90,7 +90,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xc4:
device->cname = "GF104";
@@ -123,7 +123,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xc3:
device->cname = "GF106";
@@ -155,7 +155,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xce:
device->cname = "GF114";
@@ -188,7 +188,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xcf:
device->cname = "GF116";
@@ -220,7 +220,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xc1:
device->cname = "GF108";
@@ -252,7 +252,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xc8:
device->cname = "GF110";
@@ -285,7 +285,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xd9:
device->cname = "GF119";
@@ -317,7 +317,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
case 0xd7:
device->cname = "GF117";
@@ -347,7 +347,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
break;
default:
nv_fatal(device, "unknown Fermi chipset\n");
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index d0894674be44..c6e6e6635c93 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -91,7 +91,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass;
break;
case 0xe7:
device->cname = "GK107";
@@ -125,7 +125,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass;
break;
case 0xe6:
device->cname = "GK106";
@@ -159,7 +159,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass;
break;
case 0xea:
device->cname = "GK20A";
@@ -179,7 +179,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass;
break;
@@ -215,7 +215,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0xf1:
device->cname = "GK110B";
@@ -249,7 +249,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
+ device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0x106:
device->cname = "GK208B";
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild
index fde0dc250b55..413b6091e256 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild
@@ -2,8 +2,8 @@ nvkm-y += nvkm/engine/pm/base.o
nvkm-y += nvkm/engine/pm/daemon.o
nvkm-y += nvkm/engine/pm/nv40.o
nvkm-y += nvkm/engine/pm/nv50.o
-nvkm-y += nvkm/engine/pm/nv84.o
-nvkm-y += nvkm/engine/pm/nva3.o
-nvkm-y += nvkm/engine/pm/nvc0.o
-nvkm-y += nvkm/engine/pm/nve0.o
-nvkm-y += nvkm/engine/pm/nvf0.o
+nvkm-y += nvkm/engine/pm/g84.o
+nvkm-y += nvkm/engine/pm/gt215.o
+nvkm-y += nvkm/engine/pm/gf100.o
+nvkm-y += nvkm/engine/pm/gk104.o
+nvkm-y += nvkm/engine/pm/gk110.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
index 5efb308e5d1c..2006c445938d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
@@ -21,22 +21,21 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <core/client.h>
+#include <core/device.h>
#include <core/option.h>
-#include <nvif/unpack.h>
+
#include <nvif/class.h>
#include <nvif/ioctl.h>
-
-#include <subdev/clk.h>
-
-#include "priv.h"
+#include <nvif/unpack.h>
#define QUAD_MASK 0x0f
#define QUAD_FREE 0x01
-static struct nouveau_perfsig *
-nouveau_perfsig_find_(struct nouveau_perfdom *dom, const char *name, u32 size)
+static struct nvkm_perfsig *
+nvkm_perfsig_find_(struct nvkm_perfdom *dom, const char *name, u32 size)
{
char path[64];
int i;
@@ -58,16 +57,16 @@ nouveau_perfsig_find_(struct nouveau_perfdom *dom, const char *name, u32 size)
return NULL;
}
-struct nouveau_perfsig *
-nouveau_perfsig_find(struct nouveau_pm *ppm, const char *name, u32 size,
- struct nouveau_perfdom **pdom)
+struct nvkm_perfsig *
+nvkm_perfsig_find(struct nvkm_pm *ppm, const char *name, u32 size,
+ struct nvkm_perfdom **pdom)
{
- struct nouveau_perfdom *dom = *pdom;
- struct nouveau_perfsig *sig;
+ struct nvkm_perfdom *dom = *pdom;
+ struct nvkm_perfsig *sig;
if (dom == NULL) {
list_for_each_entry(dom, &ppm->domains, head) {
- sig = nouveau_perfsig_find_(dom, name, size);
+ sig = nvkm_perfsig_find_(dom, name, size);
if (sig) {
*pdom = dom;
return sig;
@@ -77,17 +76,17 @@ nouveau_perfsig_find(struct nouveau_pm *ppm, const char *name, u32 size,
return NULL;
}
- return nouveau_perfsig_find_(dom, name, size);
+ return nvkm_perfsig_find_(dom, name, size);
}
-struct nouveau_perfctr *
-nouveau_perfsig_wrap(struct nouveau_pm *ppm, const char *name,
- struct nouveau_perfdom **pdom)
+struct nvkm_perfctr *
+nvkm_perfsig_wrap(struct nvkm_pm *ppm, const char *name,
+ struct nvkm_perfdom **pdom)
{
- struct nouveau_perfsig *sig;
- struct nouveau_perfctr *ctr;
+ struct nvkm_perfsig *sig;
+ struct nvkm_perfctr *ctr;
- sig = nouveau_perfsig_find(ppm, name, strlen(name), pdom);
+ sig = nvkm_perfsig_find(ppm, name, strlen(name), pdom);
if (!sig)
return NULL;
@@ -104,16 +103,16 @@ nouveau_perfsig_wrap(struct nouveau_pm *ppm, const char *name,
* Perfmon object classes
******************************************************************************/
static int
-nouveau_perfctr_query(struct nouveau_object *object, void *data, u32 size)
+nvkm_perfctr_query(struct nvkm_object *object, void *data, u32 size)
{
union {
struct nvif_perfctr_query_v0 v0;
} *args = data;
- struct nouveau_device *device = nv_device(object);
- struct nouveau_pm *ppm = (void *)object->engine;
- struct nouveau_perfdom *dom = NULL, *chk;
- const bool all = nouveau_boolopt(device->cfgopt, "NvPmShowAll", false);
- const bool raw = nouveau_boolopt(device->cfgopt, "NvPmUnnamed", all);
+ struct nvkm_device *device = nv_device(object);
+ struct nvkm_pm *ppm = (void *)object->engine;
+ struct nvkm_perfdom *dom = NULL, *chk;
+ const bool all = nvkm_boolopt(device->cfgopt, "NvPmShowAll", false);
+ const bool raw = nvkm_boolopt(device->cfgopt, "NvPmUnnamed", all);
const char *name;
int tmp = 0, di, si;
int ret;
@@ -163,14 +162,14 @@ nouveau_perfctr_query(struct nouveau_object *object, void *data, u32 size)
}
static int
-nouveau_perfctr_sample(struct nouveau_object *object, void *data, u32 size)
+nvkm_perfctr_sample(struct nvkm_object *object, void *data, u32 size)
{
union {
struct nvif_perfctr_sample none;
} *args = data;
- struct nouveau_pm *ppm = (void *)object->engine;
- struct nouveau_perfctr *ctr, *tmp;
- struct nouveau_perfdom *dom;
+ struct nvkm_pm *ppm = (void *)object->engine;
+ struct nvkm_perfctr *ctr, *tmp;
+ struct nvkm_perfdom *dom;
int ret;
nv_ioctl(object, "perfctr sample size %d\n", size);
@@ -187,7 +186,7 @@ nouveau_perfctr_sample(struct nouveau_object *object, void *data, u32 size)
tmp = NULL;
while (!list_empty(&dom->list)) {
ctr = list_first_entry(&dom->list,
- typeof(*ctr), head);
+ typeof(*ctr), head);
if (ctr->slot < 0) break;
if ( tmp && tmp == ctr) break;
if (!tmp) tmp = ctr;
@@ -216,12 +215,12 @@ nouveau_perfctr_sample(struct nouveau_object *object, void *data, u32 size)
}
static int
-nouveau_perfctr_read(struct nouveau_object *object, void *data, u32 size)
+nvkm_perfctr_read(struct nvkm_object *object, void *data, u32 size)
{
union {
struct nvif_perfctr_read_v0 v0;
} *args = data;
- struct nouveau_perfctr *ctr = (void *)object;
+ struct nvkm_perfctr *ctr = (void *)object;
int ret;
nv_ioctl(object, "perfctr read size %d\n", size);
@@ -239,16 +238,15 @@ nouveau_perfctr_read(struct nouveau_object *object, void *data, u32 size)
}
static int
-nouveau_perfctr_mthd(struct nouveau_object *object, u32 mthd,
- void *data, u32 size)
+nvkm_perfctr_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
switch (mthd) {
case NVIF_PERFCTR_V0_QUERY:
- return nouveau_perfctr_query(object, data, size);
+ return nvkm_perfctr_query(object, data, size);
case NVIF_PERFCTR_V0_SAMPLE:
- return nouveau_perfctr_sample(object, data, size);
+ return nvkm_perfctr_sample(object, data, size);
case NVIF_PERFCTR_V0_READ:
- return nouveau_perfctr_read(object, data, size);
+ return nvkm_perfctr_read(object, data, size);
default:
break;
}
@@ -256,27 +254,26 @@ nouveau_perfctr_mthd(struct nouveau_object *object, u32 mthd,
}
static void
-nouveau_perfctr_dtor(struct nouveau_object *object)
+nvkm_perfctr_dtor(struct nvkm_object *object)
{
- struct nouveau_perfctr *ctr = (void *)object;
+ struct nvkm_perfctr *ctr = (void *)object;
if (ctr->head.next)
list_del(&ctr->head);
- nouveau_object_destroy(&ctr->base);
+ nvkm_object_destroy(&ctr->base);
}
static int
-nouveau_perfctr_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nvkm_perfctr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nvif_perfctr_v0 v0;
} *args = data;
- struct nouveau_pm *ppm = (void *)engine;
- struct nouveau_perfdom *dom = NULL;
- struct nouveau_perfsig *sig[4] = {};
- struct nouveau_perfctr *ctr;
+ struct nvkm_pm *ppm = (void *)engine;
+ struct nvkm_perfdom *dom = NULL;
+ struct nvkm_perfsig *sig[4] = {};
+ struct nvkm_perfctr *ctr;
int ret, i;
nv_ioctl(parent, "create perfctr size %d\n", size);
@@ -287,15 +284,15 @@ nouveau_perfctr_ctor(struct nouveau_object *parent,
return ret;
for (i = 0; i < ARRAY_SIZE(args->v0.name) && args->v0.name[i][0]; i++) {
- sig[i] = nouveau_perfsig_find(ppm, args->v0.name[i],
- strnlen(args->v0.name[i],
- sizeof(args->v0.name[i])),
- &dom);
+ sig[i] = nvkm_perfsig_find(ppm, args->v0.name[i],
+ strnlen(args->v0.name[i],
+ sizeof(args->v0.name[i])),
+ &dom);
if (!sig[i])
return -EINVAL;
}
- ret = nouveau_object_create(parent, engine, oclass, 0, &ctr);
+ ret = nvkm_object_create(parent, engine, oclass, 0, &ctr);
*pobject = nv_object(ctr);
if (ret)
return ret;
@@ -311,19 +308,19 @@ nouveau_perfctr_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_ofuncs
-nouveau_perfctr_ofuncs = {
- .ctor = nouveau_perfctr_ctor,
- .dtor = nouveau_perfctr_dtor,
- .init = nouveau_object_init,
- .fini = nouveau_object_fini,
- .mthd = nouveau_perfctr_mthd,
+static struct nvkm_ofuncs
+nvkm_perfctr_ofuncs = {
+ .ctor = nvkm_perfctr_ctor,
+ .dtor = nvkm_perfctr_dtor,
+ .init = nvkm_object_init,
+ .fini = nvkm_object_fini,
+ .mthd = nvkm_perfctr_mthd,
};
-struct nouveau_oclass
-nouveau_pm_sclass[] = {
+struct nvkm_oclass
+nvkm_pm_sclass[] = {
{ .handle = NVIF_IOCTL_NEW_V0_PERFCTR,
- .ofuncs = &nouveau_perfctr_ofuncs,
+ .ofuncs = &nvkm_perfctr_ofuncs,
},
{},
};
@@ -332,27 +329,25 @@ nouveau_pm_sclass[] = {
* PPM context
******************************************************************************/
static void
-nouveau_perfctx_dtor(struct nouveau_object *object)
+nvkm_perfctx_dtor(struct nvkm_object *object)
{
- struct nouveau_pm *ppm = (void *)object->engine;
+ struct nvkm_pm *ppm = (void *)object->engine;
mutex_lock(&nv_subdev(ppm)->mutex);
- nouveau_engctx_destroy(&ppm->context->base);
+ nvkm_engctx_destroy(&ppm->context->base);
ppm->context = NULL;
mutex_unlock(&nv_subdev(ppm)->mutex);
}
static int
-nouveau_perfctx_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nvkm_perfctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_pm *ppm = (void *)engine;
- struct nouveau_perfctx *ctx;
+ struct nvkm_pm *ppm = (void *)engine;
+ struct nvkm_perfctx *ctx;
int ret;
- ret = nouveau_engctx_create(parent, engine, oclass, NULL,
- 0, 0, 0, &ctx);
+ ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0, 0, 0, &ctx);
*pobject = nv_object(ctx);
if (ret)
return ret;
@@ -368,14 +363,14 @@ nouveau_perfctx_ctor(struct nouveau_object *parent,
return 0;
}
-struct nouveau_oclass
-nouveau_pm_cclass = {
+struct nvkm_oclass
+nvkm_pm_cclass = {
.handle = NV_ENGCTX(PM, 0x00),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nouveau_perfctx_ctor,
- .dtor = nouveau_perfctx_dtor,
- .init = _nouveau_engctx_init,
- .fini = _nouveau_engctx_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = nvkm_perfctx_ctor,
+ .dtor = nvkm_perfctx_dtor,
+ .init = _nvkm_engctx_init,
+ .fini = _nvkm_engctx_fini,
},
};
@@ -383,13 +378,13 @@ nouveau_pm_cclass = {
* PPM engine/subdev functions
******************************************************************************/
int
-nouveau_perfdom_new(struct nouveau_pm *ppm, const char *name, u32 mask,
- u32 base, u32 size_unit, u32 size_domain,
- const struct nouveau_specdom *spec)
+nvkm_perfdom_new(struct nvkm_pm *ppm, const char *name, u32 mask,
+ u32 base, u32 size_unit, u32 size_domain,
+ const struct nvkm_specdom *spec)
{
- const struct nouveau_specdom *sdom;
- const struct nouveau_specsig *ssig;
- struct nouveau_perfdom *dom;
+ const struct nvkm_specdom *sdom;
+ const struct nvkm_specsig *ssig;
+ struct nvkm_perfdom *dom;
int i;
for (i = 0; i == 0 || mask; i++) {
@@ -436,44 +431,42 @@ nouveau_perfdom_new(struct nouveau_pm *ppm, const char *name, u32 mask,
}
int
-_nouveau_pm_fini(struct nouveau_object *object, bool suspend)
+_nvkm_pm_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_pm *ppm = (void *)object;
- return nouveau_engine_fini(&ppm->base, suspend);
+ struct nvkm_pm *ppm = (void *)object;
+ return nvkm_engine_fini(&ppm->base, suspend);
}
int
-_nouveau_pm_init(struct nouveau_object *object)
+_nvkm_pm_init(struct nvkm_object *object)
{
- struct nouveau_pm *ppm = (void *)object;
- return nouveau_engine_init(&ppm->base);
+ struct nvkm_pm *ppm = (void *)object;
+ return nvkm_engine_init(&ppm->base);
}
void
-_nouveau_pm_dtor(struct nouveau_object *object)
+_nvkm_pm_dtor(struct nvkm_object *object)
{
- struct nouveau_pm *ppm = (void *)object;
- struct nouveau_perfdom *dom, *tmp;
+ struct nvkm_pm *ppm = (void *)object;
+ struct nvkm_perfdom *dom, *tmp;
list_for_each_entry_safe(dom, tmp, &ppm->domains, head) {
list_del(&dom->head);
kfree(dom);
}
- nouveau_engine_destroy(&ppm->base);
+ nvkm_engine_destroy(&ppm->base);
}
int
-nouveau_pm_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass,
- int length, void **pobject)
+nvkm_pm_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
- struct nouveau_pm *ppm;
+ struct nvkm_pm *ppm;
int ret;
- ret = nouveau_engine_create_(parent, engine, oclass, true, "PPM",
- "pm", length, pobject);
+ ret = nvkm_engine_create_(parent, engine, oclass, true, "PPM",
+ "pm", length, pobject);
ppm = *pobject;
if (ret)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c
index 1fd51b815707..a7a5f3a3c91b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c
@@ -21,12 +21,11 @@
*
* Authors: Ben Skeggs
*/
-
#include "priv.h"
static void
-pwr_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
- struct nouveau_perfctr *ctr)
+pwr_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
+ struct nvkm_perfctr *ctr)
{
u32 mask = 0x00000000;
u32 ctrl = 0x00000001;
@@ -41,15 +40,15 @@ pwr_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
}
static void
-pwr_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
- struct nouveau_perfctr *ctr)
+pwr_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
+ struct nvkm_perfctr *ctr)
{
ctr->ctr = ppm->pwr[ctr->slot];
ctr->clk = ppm->pwr[ppm->last];
}
static void
-pwr_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
+pwr_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom)
{
int i;
@@ -59,16 +58,16 @@ pwr_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
}
}
-static const struct nouveau_funcdom
+static const struct nvkm_funcdom
pwr_perfctr_func = {
.init = pwr_perfctr_init,
.read = pwr_perfctr_read,
.next = pwr_perfctr_next,
};
-const struct nouveau_specdom
-nva3_pm_pwr[] = {
- { 0x20, (const struct nouveau_specsig[]) {
+const struct nvkm_specdom
+gt215_pm_pwr[] = {
+ { 0x20, (const struct nvkm_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
@@ -79,9 +78,9 @@ nva3_pm_pwr[] = {
{}
};
-const struct nouveau_specdom
-nvc0_pm_pwr[] = {
- { 0x20, (const struct nouveau_specsig[]) {
+const struct nvkm_specdom
+gf100_pm_pwr[] = {
+ { 0x20, (const struct nvkm_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
@@ -93,9 +92,9 @@ nvc0_pm_pwr[] = {
{}
};
-const struct nouveau_specdom
-nve0_pm_pwr[] = {
- { 0x20, (const struct nouveau_specsig[]) {
+const struct nvkm_specdom
+gk104_pm_pwr[] = {
+ { 0x20, (const struct nvkm_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c
similarity index 56%
rename from drivers/gpu/drm/nouveau/nvkm/engine/pm/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c
index 37a4fc9c346b..d54c6705ba17 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c
@@ -21,58 +21,45 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv40.h"
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_specdom
-nv84_pm[] = {
- { 0x20, (const struct nouveau_specsig[]) {
+static const struct nvkm_specdom
+g84_pm[] = {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
-struct nouveau_oclass *
-nv84_pm_oclass = &(struct nv40_pm_oclass) {
+struct nvkm_oclass *
+g84_pm_oclass = &(struct nv40_pm_oclass) {
.base.handle = NV_ENGINE(PM, 0x84),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_pm_ctor,
- .dtor = _nouveau_pm_dtor,
- .init = _nouveau_pm_init,
- .fini = _nouveau_pm_fini,
+ .dtor = _nvkm_pm_dtor,
+ .init = _nvkm_pm_init,
+ .fini = _nvkm_pm_fini,
},
- .doms = nv84_pm,
+ .doms = g84_pm,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c
similarity index 52%
rename from drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c
index fb00e82bbed0..008fed73dd82 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c
@@ -21,42 +21,29 @@
*
* Authors: Ben Skeggs
*/
+#include "gf100.h"
-#include "nvc0.h"
-
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_specdom
-nvc0_pm_hub[] = {
+static const struct nvkm_specdom
+gf100_pm_hub[] = {
{}
};
-static const struct nouveau_specdom
-nvc0_pm_gpc[] = {
+static const struct nvkm_specdom
+gf100_pm_gpc[] = {
{}
};
-static const struct nouveau_specdom
-nvc0_pm_part[] = {
+static const struct nvkm_specdom
+gf100_pm_part[] = {
{}
};
static void
-nvc0_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
- struct nouveau_perfctr *ctr)
+gf100_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
+ struct nvkm_perfctr *ctr)
{
- struct nvc0_pm_priv *priv = (void *)ppm;
- struct nvc0_pm_cntr *cntr = (void *)ctr;
+ struct gf100_pm_priv *priv = (void *)ppm;
+ struct gf100_pm_cntr *cntr = (void *)ctr;
u32 log = ctr->logic_op;
u32 src = 0x00000000;
int i;
@@ -71,11 +58,11 @@ nvc0_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
}
static void
-nvc0_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
- struct nouveau_perfctr *ctr)
+gf100_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
+ struct nvkm_perfctr *ctr)
{
- struct nvc0_pm_priv *priv = (void *)ppm;
- struct nvc0_pm_cntr *cntr = (void *)ctr;
+ struct gf100_pm_priv *priv = (void *)ppm;
+ struct gf100_pm_cntr *cntr = (void *)ctr;
switch (cntr->base.slot) {
case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break;
@@ -87,51 +74,50 @@ nvc0_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
}
static void
-nvc0_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
+gf100_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom)
{
- struct nvc0_pm_priv *priv = (void *)ppm;
+ struct gf100_pm_priv *priv = (void *)ppm;
nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27);
nv_wr32(priv, dom->addr + 0x0ec, 0x00000011);
}
-const struct nouveau_funcdom
-nvc0_perfctr_func = {
- .init = nvc0_perfctr_init,
- .read = nvc0_perfctr_read,
- .next = nvc0_perfctr_next,
+const struct nvkm_funcdom
+gf100_perfctr_func = {
+ .init = gf100_perfctr_init,
+ .read = gf100_perfctr_read,
+ .next = gf100_perfctr_next,
};
int
-nvc0_pm_fini(struct nouveau_object *object, bool suspend)
+gf100_pm_fini(struct nvkm_object *object, bool suspend)
{
- struct nvc0_pm_priv *priv = (void *)object;
+ struct gf100_pm_priv *priv = (void *)object;
nv_mask(priv, 0x000200, 0x10000000, 0x00000000);
nv_mask(priv, 0x000200, 0x10000000, 0x10000000);
- return nouveau_pm_fini(&priv->base, suspend);
+ return nvkm_pm_fini(&priv->base, suspend);
}
static int
-nvc0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvc0_pm_priv *priv;
+ struct gf100_pm_priv *priv;
u32 mask;
int ret;
- ret = nouveau_pm_create(parent, engine, oclass, &priv);
+ ret = nvkm_pm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
- nvc0_pm_pwr);
+ ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gf100_pm_pwr);
if (ret)
return ret;
/* HUB */
- ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
- nvc0_pm_hub);
+ ret = nvkm_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
+ gf100_pm_hub);
if (ret)
return ret;
@@ -140,8 +126,8 @@ nvc0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
mask &= ~nv_rd32(priv, 0x022504);
mask &= ~nv_rd32(priv, 0x022584);
- ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
- 0x1000, 0x200, nvc0_pm_gpc);
+ ret = nvkm_perfdom_new(&priv->base, "gpc", mask, 0x180000,
+ 0x1000, 0x200, gf100_pm_gpc);
if (ret)
return ret;
@@ -150,24 +136,24 @@ nvc0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
mask &= ~nv_rd32(priv, 0x022548);
mask &= ~nv_rd32(priv, 0x0225c8);
- ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
- 0x1000, 0x200, nvc0_pm_part);
+ ret = nvkm_perfdom_new(&priv->base, "part", mask, 0x1a0000,
+ 0x1000, 0x200, gf100_pm_part);
if (ret)
return ret;
- nv_engine(priv)->cclass = &nouveau_pm_cclass;
- nv_engine(priv)->sclass = nouveau_pm_sclass;
+ nv_engine(priv)->cclass = &nvkm_pm_cclass;
+ nv_engine(priv)->sclass = nvkm_pm_sclass;
priv->base.last = 7;
return 0;
}
-struct nouveau_oclass
-nvc0_pm_oclass = {
+struct nvkm_oclass
+gf100_pm_oclass = {
.handle = NV_ENGINE(PM, 0xc0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_pm_ctor,
- .dtor = _nouveau_pm_dtor,
- .init = _nouveau_pm_init,
- .fini = nvc0_pm_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_pm_ctor,
+ .dtor = _nvkm_pm_dtor,
+ .init = _nvkm_pm_init,
+ .fini = gf100_pm_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h
new file mode 100644
index 000000000000..6a01fc7fec6f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h
@@ -0,0 +1,15 @@
+#ifndef __NVKM_PM_NVC0_H__
+#define __NVKM_PM_NVC0_H__
+#include "priv.h"
+
+struct gf100_pm_priv {
+ struct nvkm_pm base;
+};
+
+struct gf100_pm_cntr {
+ struct nvkm_perfctr base;
+};
+
+extern const struct nvkm_funcdom gf100_perfctr_func;
+int gf100_pm_fini(struct nvkm_object *, bool);
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c
new file mode 100644
index 000000000000..75b9ff3d1a2c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+#include "gf100.h"
+
+static const struct nvkm_specdom
+gk104_pm_hub[] = {
+ { 0x60, (const struct nvkm_specsig[]) {
+ { 0x47, "hub00_user_0" },
+ {}
+ }, &gf100_perfctr_func },
+ { 0x40, (const struct nvkm_specsig[]) {
+ { 0x27, "hub01_user_0" },
+ {}
+ }, &gf100_perfctr_func },
+ { 0x60, (const struct nvkm_specsig[]) {
+ { 0x47, "hub02_user_0" },
+ {}
+ }, &gf100_perfctr_func },
+ { 0x60, (const struct nvkm_specsig[]) {
+ { 0x47, "hub03_user_0" },
+ {}
+ }, &gf100_perfctr_func },
+ { 0x40, (const struct nvkm_specsig[]) {
+ { 0x03, "host_mmio_rd" },
+ { 0x27, "hub04_user_0" },
+ {}
+ }, &gf100_perfctr_func },
+ { 0x60, (const struct nvkm_specsig[]) {
+ { 0x47, "hub05_user_0" },
+ {}
+ }, &gf100_perfctr_func },
+ { 0xc0, (const struct nvkm_specsig[]) {
+ { 0x74, "host_fb_rd3x" },
+ { 0x75, "host_fb_rd3x_2" },
+ { 0xa7, "hub06_user_0" },
+ {}
+ }, &gf100_perfctr_func },
+ { 0x60, (const struct nvkm_specsig[]) {
+ { 0x47, "hub07_user_0" },
+ {}
+ }, &gf100_perfctr_func },
+ {}
+};
+
+static const struct nvkm_specdom
+gk104_pm_gpc[] = {
+ { 0xe0, (const struct nvkm_specsig[]) {
+ { 0xc7, "gpc00_user_0" },
+ {}
+ }, &gf100_perfctr_func },
+ {}
+};
+
+static const struct nvkm_specdom
+gk104_pm_part[] = {
+ { 0x60, (const struct nvkm_specsig[]) {
+ { 0x47, "part00_user_0" },
+ {}
+ }, &gf100_perfctr_func },
+ { 0x60, (const struct nvkm_specsig[]) {
+ { 0x47, "part01_user_0" },
+ {}
+ }, &gf100_perfctr_func },
+ {}
+};
+
+static int
+gk104_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
+{
+ struct gf100_pm_priv *priv;
+ u32 mask;
+ int ret;
+
+ ret = nvkm_pm_create(parent, engine, oclass, &priv);
+ *pobject = nv_object(priv);
+ if (ret)
+ return ret;
+
+ /* PDAEMON */
+ ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gk104_pm_pwr);
+ if (ret)
+ return ret;
+
+ /* HUB */
+ ret = nvkm_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
+ gk104_pm_hub);
+ if (ret)
+ return ret;
+
+ /* GPC */
+ mask = (1 << nv_rd32(priv, 0x022430)) - 1;
+ mask &= ~nv_rd32(priv, 0x022504);
+ mask &= ~nv_rd32(priv, 0x022584);
+
+ ret = nvkm_perfdom_new(&priv->base, "gpc", mask, 0x180000,
+ 0x1000, 0x200, gk104_pm_gpc);
+ if (ret)
+ return ret;
+
+ /* PART */
+ mask = (1 << nv_rd32(priv, 0x022438)) - 1;
+ mask &= ~nv_rd32(priv, 0x022548);
+ mask &= ~nv_rd32(priv, 0x0225c8);
+
+ ret = nvkm_perfdom_new(&priv->base, "part", mask, 0x1a0000,
+ 0x1000, 0x200, gk104_pm_part);
+ if (ret)
+ return ret;
+
+ nv_engine(priv)->cclass = &nvkm_pm_cclass;
+ nv_engine(priv)->sclass = nvkm_pm_sclass;
+ priv->base.last = 7;
+ return 0;
+}
+
+struct nvkm_oclass
+gk104_pm_oclass = {
+ .handle = NV_ENGINE(PM, 0xe0),
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk104_pm_ctor,
+ .dtor = _nvkm_pm_dtor,
+ .init = _nvkm_pm_init,
+ .fini = gf100_pm_fini,
+ },
+};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk110.c
similarity index 52%
rename from drivers/gpu/drm/nouveau/nvkm/engine/pm/nvf0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/gk110.c
index 7d5a8dddae9d..6820176e5f78 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvf0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk110.c
@@ -21,51 +21,37 @@
*
* Authors: Ben Skeggs
*/
-
-#include "nvc0.h"
-
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
+#include "gf100.h"
static int
-nvf0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gk110_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvc0_pm_priv *priv;
+ struct gf100_pm_priv *priv;
int ret;
- ret = nouveau_pm_create(parent, engine, oclass, &priv);
+ ret = nvkm_pm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
- nve0_pm_pwr);
+ ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gk104_pm_pwr);
if (ret)
return ret;
- nv_engine(priv)->cclass = &nouveau_pm_cclass;
- nv_engine(priv)->sclass = nouveau_pm_sclass;
+ nv_engine(priv)->cclass = &nvkm_pm_cclass;
+ nv_engine(priv)->sclass = nvkm_pm_sclass;
return 0;
}
-struct nouveau_oclass
-nvf0_pm_oclass = {
+struct nvkm_oclass
+gk110_pm_oclass = {
.handle = NV_ENGINE(PM, 0xf0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvf0_pm_ctor,
- .dtor = _nouveau_pm_dtor,
- .init = _nouveau_pm_init,
- .fini = nvc0_pm_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gk110_pm_ctor,
+ .dtor = _nvkm_pm_dtor,
+ .init = _nvkm_pm_init,
+ .fini = gf100_pm_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c
similarity index 53%
rename from drivers/gpu/drm/nouveau/nvkm/engine/pm/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c
index d54dc57c4e61..d065bfc59bbf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c
@@ -21,60 +21,47 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv40.h"
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_specdom
-nva3_pm[] = {
- { 0x20, (const struct nouveau_specsig[]) {
+static const struct nvkm_specdom
+gt215_pm[] = {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
static int
-nva3_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **object)
+gt215_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **object)
{
int ret = nv40_pm_ctor(parent, engine, oclass, data, size, object);
if (ret == 0) {
struct nv40_pm_priv *priv = (void *)*object;
- ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
- nva3_pm_pwr);
+ ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
+ gt215_pm_pwr);
if (ret)
return ret;
@@ -83,14 +70,14 @@ nva3_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
}
-struct nouveau_oclass *
-nva3_pm_oclass = &(struct nv40_pm_oclass) {
+struct nvkm_oclass *
+gt215_pm_oclass = &(struct nv40_pm_oclass) {
.base.handle = NV_ENGINE(PM, 0xa3),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nva3_pm_ctor,
- .dtor = _nouveau_pm_dtor,
- .init = _nouveau_pm_init,
- .fini = _nouveau_pm_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gt215_pm_ctor,
+ .dtor = _nvkm_pm_dtor,
+ .init = _nvkm_pm_init,
+ .fini = _nvkm_pm_fini,
},
- .doms = nva3_pm,
+ .doms = gt215_pm,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c
index 82a1777a3e11..ff22f06b22b8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c
@@ -21,24 +21,11 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv40.h"
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-
static void
-nv40_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
- struct nouveau_perfctr *ctr)
+nv40_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
+ struct nvkm_perfctr *ctr)
{
struct nv40_pm_priv *priv = (void *)ppm;
struct nv40_pm_cntr *cntr = (void *)ctr;
@@ -55,8 +42,8 @@ nv40_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
}
static void
-nv40_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
- struct nouveau_perfctr *ctr)
+nv40_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
+ struct nvkm_perfctr *ctr)
{
struct nv40_pm_priv *priv = (void *)ppm;
struct nv40_pm_cntr *cntr = (void *)ctr;
@@ -71,7 +58,7 @@ nv40_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
}
static void
-nv40_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
+nv40_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom)
{
struct nv40_pm_priv *priv = (void *)ppm;
if (priv->sequence != ppm->sequence) {
@@ -80,64 +67,64 @@ nv40_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
}
}
-const struct nouveau_funcdom
+const struct nvkm_funcdom
nv40_perfctr_func = {
.init = nv40_perfctr_init,
.read = nv40_perfctr_read,
.next = nv40_perfctr_next,
};
-static const struct nouveau_specdom
+static const struct nvkm_specdom
nv40_pm[] = {
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x20, (const struct nouveau_specsig[]) {
+ { 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
int
-nv40_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv40_pm_oclass *mclass = (void *)oclass;
struct nv40_pm_priv *priv;
int ret;
- ret = nouveau_pm_create(parent, engine, oclass, &priv);
+ ret = nvkm_pm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms);
+ ret = nvkm_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms);
if (ret)
return ret;
- nv_engine(priv)->cclass = &nouveau_pm_cclass;
- nv_engine(priv)->sclass = nouveau_pm_sclass;
+ nv_engine(priv)->cclass = &nvkm_pm_cclass;
+ nv_engine(priv)->sclass = nvkm_pm_sclass;
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv40_pm_oclass = &(struct nv40_pm_oclass) {
.base.handle = NV_ENGINE(PM, 0x40),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_pm_ctor,
- .dtor = _nouveau_pm_dtor,
- .init = _nouveau_pm_init,
- .fini = _nouveau_pm_fini,
+ .dtor = _nvkm_pm_dtor,
+ .init = _nvkm_pm_init,
+ .fini = _nvkm_pm_fini,
},
.doms = nv40_pm,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h
index e83a0efd5d89..2338e150420e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h
@@ -1,26 +1,24 @@
#ifndef __NVKM_PM_NV40_H__
#define __NVKM_PM_NV40_H__
-
#include "priv.h"
struct nv40_pm_oclass {
- struct nouveau_oclass base;
- const struct nouveau_specdom *doms;
+ struct nvkm_oclass base;
+ const struct nvkm_specdom *doms;
};
struct nv40_pm_priv {
- struct nouveau_pm base;
+ struct nvkm_pm base;
u32 sequence;
};
-int nv40_pm_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *data, u32 size,
- struct nouveau_object **pobject);
+int nv40_pm_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *data, u32 size,
+ struct nvkm_object **pobject);
struct nv40_pm_cntr {
- struct nouveau_perfctr base;
+ struct nvkm_perfctr base;
};
-extern const struct nouveau_funcdom nv40_perfctr_func;
-
+extern const struct nvkm_funcdom nv40_perfctr_func;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c
index db2f9a17abb5..6af83b5d1b11 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c
@@ -21,50 +21,37 @@
*
* Authors: Ben Skeggs
*/
-
#include "nv40.h"
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_specdom
+static const struct nvkm_specdom
nv50_pm[] = {
- { 0x040, (const struct nouveau_specsig[]) {
+ { 0x040, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x100, (const struct nouveau_specsig[]) {
+ { 0x100, (const struct nvkm_specsig[]) {
{ 0xc8, "gr_idle" },
{}
}, &nv40_perfctr_func },
- { 0x100, (const struct nouveau_specsig[]) {
+ { 0x100, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x020, (const struct nouveau_specsig[]) {
+ { 0x020, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
- { 0x040, (const struct nouveau_specsig[]) {
+ { 0x040, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
-struct nouveau_oclass *
+struct nvkm_oclass *
nv50_pm_oclass = &(struct nv40_pm_oclass) {
.base.handle = NV_ENGINE(PM, 0x50),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_pm_ctor,
- .dtor = _nouveau_pm_dtor,
- .init = _nouveau_pm_init,
- .fini = _nouveau_pm_fini,
+ .dtor = _nvkm_pm_dtor,
+ .init = _nvkm_pm_init,
+ .fini = _nvkm_pm_fini,
},
.doms = nv50_pm,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.h
deleted file mode 100644
index e0e0e02600d4..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __NVKM_PM_NVC0_H__
-#define __NVKM_PM_NVC0_H__
-
-#include "priv.h"
-
-struct nvc0_pm_priv {
- struct nouveau_pm base;
-};
-
-struct nvc0_pm_cntr {
- struct nouveau_perfctr base;
-};
-
-extern const struct nouveau_funcdom nvc0_perfctr_func;
-int nvc0_pm_fini(struct nouveau_object *, bool);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nve0.c
deleted file mode 100644
index 11b17cced966..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nve0.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nvc0.h"
-
-/*******************************************************************************
- * Perfmon object classes
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM context
- ******************************************************************************/
-
-/*******************************************************************************
- * PPM engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_specdom
-nve0_pm_hub[] = {
- { 0x60, (const struct nouveau_specsig[]) {
- { 0x47, "hub00_user_0" },
- {}
- }, &nvc0_perfctr_func },
- { 0x40, (const struct nouveau_specsig[]) {
- { 0x27, "hub01_user_0" },
- {}
- }, &nvc0_perfctr_func },
- { 0x60, (const struct nouveau_specsig[]) {
- { 0x47, "hub02_user_0" },
- {}
- }, &nvc0_perfctr_func },
- { 0x60, (const struct nouveau_specsig[]) {
- { 0x47, "hub03_user_0" },
- {}
- }, &nvc0_perfctr_func },
- { 0x40, (const struct nouveau_specsig[]) {
- { 0x03, "host_mmio_rd" },
- { 0x27, "hub04_user_0" },
- {}
- }, &nvc0_perfctr_func },
- { 0x60, (const struct nouveau_specsig[]) {
- { 0x47, "hub05_user_0" },
- {}
- }, &nvc0_perfctr_func },
- { 0xc0, (const struct nouveau_specsig[]) {
- { 0x74, "host_fb_rd3x" },
- { 0x75, "host_fb_rd3x_2" },
- { 0xa7, "hub06_user_0" },
- {}
- }, &nvc0_perfctr_func },
- { 0x60, (const struct nouveau_specsig[]) {
- { 0x47, "hub07_user_0" },
- {}
- }, &nvc0_perfctr_func },
- {}
-};
-
-static const struct nouveau_specdom
-nve0_pm_gpc[] = {
- { 0xe0, (const struct nouveau_specsig[]) {
- { 0xc7, "gpc00_user_0" },
- {}
- }, &nvc0_perfctr_func },
- {}
-};
-
-static const struct nouveau_specdom
-nve0_pm_part[] = {
- { 0x60, (const struct nouveau_specsig[]) {
- { 0x47, "part00_user_0" },
- {}
- }, &nvc0_perfctr_func },
- { 0x60, (const struct nouveau_specsig[]) {
- { 0x47, "part01_user_0" },
- {}
- }, &nvc0_perfctr_func },
- {}
-};
-
-static int
-nve0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
-{
- struct nvc0_pm_priv *priv;
- u32 mask;
- int ret;
-
- ret = nouveau_pm_create(parent, engine, oclass, &priv);
- *pobject = nv_object(priv);
- if (ret)
- return ret;
-
- /* PDAEMON */
- ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
- nve0_pm_pwr);
- if (ret)
- return ret;
-
- /* HUB */
- ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
- nve0_pm_hub);
- if (ret)
- return ret;
-
- /* GPC */
- mask = (1 << nv_rd32(priv, 0x022430)) - 1;
- mask &= ~nv_rd32(priv, 0x022504);
- mask &= ~nv_rd32(priv, 0x022584);
-
- ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
- 0x1000, 0x200, nve0_pm_gpc);
- if (ret)
- return ret;
-
- /* PART */
- mask = (1 << nv_rd32(priv, 0x022438)) - 1;
- mask &= ~nv_rd32(priv, 0x022548);
- mask &= ~nv_rd32(priv, 0x0225c8);
-
- ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
- 0x1000, 0x200, nve0_pm_part);
- if (ret)
- return ret;
-
- nv_engine(priv)->cclass = &nouveau_pm_cclass;
- nv_engine(priv)->sclass = nouveau_pm_sclass;
- priv->base.last = 7;
- return 0;
-}
-
-struct nouveau_oclass
-nve0_pm_oclass = {
- .handle = NV_ENGINE(PM, 0xe0),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_pm_ctor,
- .dtor = _nouveau_pm_dtor,
- .init = _nouveau_pm_init,
- .fini = nvc0_pm_fini,
- },
-};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
index af3938fb19e0..1e6eff2a6d79 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
@@ -1,91 +1,90 @@
#ifndef __NVKM_PM_PRIV_H__
#define __NVKM_PM_PRIV_H__
-
#include <engine/pm.h>
-struct nouveau_perfctr {
- struct nouveau_object base;
+struct nvkm_perfctr {
+ struct nvkm_object base;
struct list_head head;
- struct nouveau_perfsig *signal[4];
+ struct nvkm_perfsig *signal[4];
int slot;
u32 logic_op;
u32 clk;
u32 ctr;
};
-extern struct nouveau_oclass nouveau_pm_sclass[];
+extern struct nvkm_oclass nvkm_pm_sclass[];
-struct nouveau_perfctx {
- struct nouveau_engctx base;
+#include <core/engctx.h>
+
+struct nvkm_perfctx {
+ struct nvkm_engctx base;
};
-extern struct nouveau_oclass nouveau_pm_cclass;
+extern struct nvkm_oclass nvkm_pm_cclass;
-struct nouveau_specsig {
+struct nvkm_specsig {
u8 signal;
const char *name;
};
-struct nouveau_perfsig {
+struct nvkm_perfsig {
const char *name;
};
-struct nouveau_perfdom;
-struct nouveau_perfctr *
-nouveau_perfsig_wrap(struct nouveau_pm *, const char *,
- struct nouveau_perfdom **);
+struct nvkm_perfdom;
+struct nvkm_perfctr *
+nvkm_perfsig_wrap(struct nvkm_pm *, const char *, struct nvkm_perfdom **);
-struct nouveau_specdom {
+struct nvkm_specdom {
u16 signal_nr;
- const struct nouveau_specsig *signal;
- const struct nouveau_funcdom *func;
+ const struct nvkm_specsig *signal;
+ const struct nvkm_funcdom *func;
};
-extern const struct nouveau_specdom nva3_pm_pwr[];
-extern const struct nouveau_specdom nvc0_pm_pwr[];
-extern const struct nouveau_specdom nve0_pm_pwr[];
+extern const struct nvkm_specdom gt215_pm_pwr[];
+extern const struct nvkm_specdom gf100_pm_pwr[];
+extern const struct nvkm_specdom gk104_pm_pwr[];
-struct nouveau_perfdom {
+struct nvkm_perfdom {
struct list_head head;
struct list_head list;
- const struct nouveau_funcdom *func;
+ const struct nvkm_funcdom *func;
char name[32];
u32 addr;
u8 quad;
u32 signal_nr;
- struct nouveau_perfsig signal[];
+ struct nvkm_perfsig signal[];
};
-struct nouveau_funcdom {
- void (*init)(struct nouveau_pm *, struct nouveau_perfdom *,
- struct nouveau_perfctr *);
- void (*read)(struct nouveau_pm *, struct nouveau_perfdom *,
- struct nouveau_perfctr *);
- void (*next)(struct nouveau_pm *, struct nouveau_perfdom *);
+struct nvkm_funcdom {
+ void (*init)(struct nvkm_pm *, struct nvkm_perfdom *,
+ struct nvkm_perfctr *);
+ void (*read)(struct nvkm_pm *, struct nvkm_perfdom *,
+ struct nvkm_perfctr *);
+ void (*next)(struct nvkm_pm *, struct nvkm_perfdom *);
};
-int nouveau_perfdom_new(struct nouveau_pm *, const char *, u32,
- u32, u32, u32, const struct nouveau_specdom *);
+int nvkm_perfdom_new(struct nvkm_pm *, const char *, u32, u32, u32, u32,
+ const struct nvkm_specdom *);
-#define nouveau_pm_create(p,e,o,d) \
- nouveau_pm_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_pm_dtor(p) ({ \
- struct nouveau_pm *c = (p); \
- _nouveau_pm_dtor(nv_object(c)); \
+#define nvkm_pm_create(p,e,o,d) \
+ nvkm_pm_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_pm_dtor(p) ({ \
+ struct nvkm_pm *c = (p); \
+ _nvkm_pm_dtor(nv_object(c)); \
})
-#define nouveau_pm_init(p) ({ \
- struct nouveau_pm *c = (p); \
- _nouveau_pm_init(nv_object(c)); \
+#define nvkm_pm_init(p) ({ \
+ struct nvkm_pm *c = (p); \
+ _nvkm_pm_init(nv_object(c)); \
})
-#define nouveau_pm_fini(p,s) ({ \
- struct nouveau_pm *c = (p); \
- _nouveau_pm_fini(nv_object(c), (s)); \
+#define nvkm_pm_fini(p,s) ({ \
+ struct nvkm_pm *c = (p); \
+ _nvkm_pm_fini(nv_object(c), (s)); \
})
-int nouveau_pm_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-void _nouveau_pm_dtor(struct nouveau_object *);
-int _nouveau_pm_init(struct nouveau_object *);
-int _nouveau_pm_fini(struct nouveau_object *, bool);
-
+int nvkm_pm_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+void _nvkm_pm_dtor(struct nvkm_object *);
+int _nvkm_pm_init(struct nvkm_object *);
+int _nvkm_pm_fini(struct nvkm_object *, bool);
#endif
From 25a6402557d3903e5082fc1afb2f97706abd9a6c Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:31:24 +1000
Subject: [PATCH 82/86] drm/nouveau/sec: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/engine/sec.h | 3 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 6 +-
.../gpu/drm/nouveau/nvkm/engine/sec/Kbuild | 2 +-
.../engine/sec/fuc/{nv98.fuc0s => g98.fuc0s} | 6 +-
.../sec/fuc/{nv98.fuc0s.h => g98.fuc0s.h} | 4 +-
.../nouveau/nvkm/engine/sec/{nv98.c => g98.c} | 105 ++++++++----------
6 files changed, 60 insertions(+), 66 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/{nv98.fuc0s => g98.fuc0s} (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/{nv98.fuc0s.h => g98.fuc0s.h} (99%)
rename drivers/gpu/drm/nouveau/nvkm/engine/sec/{nv98.c => g98.c} (59%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h
index 32cd4cb0744c..44590a2a479d 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h
@@ -1,4 +1,5 @@
#ifndef __NVKM_SEC_H__
#define __NVKM_SEC_H__
-extern struct nouveau_oclass nv98_sec_oclass;
+#include <core/engine.h>
+extern struct nvkm_oclass g98_sec_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 4bbd6b7ac997..bf3998b96bc4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -255,7 +255,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
+ device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
@@ -313,7 +313,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
+ device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
@@ -342,7 +342,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
- device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
+ device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild
index 5ce7a5073c97..552d40a4641f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild
@@ -1 +1 @@
-nvkm-y += nvkm/engine/sec/nv98.o
+nvkm-y += nvkm/engine/sec/g98.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s
rename to drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s
index 0b9e77782a57..06ee06071104 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s
@@ -1,5 +1,5 @@
/*
- * fuc microcode for nv98 psec engine
+ * fuc microcode for g98 psec engine
* Copyright (C) 2010 Marcin Kościelnicki
*
* This program is free software; you can redistribute it and/or modify
@@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-.section #nv98_psec_data
+.section #g98_psec_data
ctx_dma:
ctx_dma_query: .b32 0
@@ -94,7 +94,7 @@ sec_dtable:
.align 0x100
-.section #nv98_psec_code
+.section #g98_psec_code
// $r0 is always set to 0 in our code - this allows some space savings.
clear b32 $r0
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s.h b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h
index f7e1e135b59b..5d65c4fbb087 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h
@@ -1,4 +1,4 @@
-uint32_t nv98_psec_data[] = {
+uint32_t g98_psec_data[] = {
/* 0x0000: ctx_dma */
/* 0x0000: ctx_dma_query */
0x00000000,
@@ -150,7 +150,7 @@ uint32_t nv98_psec_data[] = {
0x00000000,
};
-uint32_t nv98_psec_code[] = {
+uint32_t g98_psec_code[] = {
0x17f004bd,
0x0010fe35,
0xf10004fe,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c
similarity index 59%
rename from drivers/gpu/drm/nouveau/nvkm/engine/sec/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c
index 10d0d1ff2694..9d5c1b8b1f8c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c
@@ -21,32 +21,25 @@
*
* Authors: Ben Skeggs
*/
+#include <engine/sec.h>
+#include <engine/falcon.h>
+#include "fuc/g98.fuc0s.h"
#include <core/client.h>
-#include <core/os.h>
#include <core/enum.h>
-#include <core/engctx.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/falcon.h>
#include <engine/fifo.h>
-#include <engine/sec.h>
-#include "fuc/nv98.fuc0s.h"
-
-struct nv98_sec_priv {
- struct nouveau_falcon base;
+struct g98_sec_priv {
+ struct nvkm_falcon base;
};
/*******************************************************************************
* Crypt object classes
******************************************************************************/
-static struct nouveau_oclass
-nv98_sec_sclass[] = {
- { 0x88b4, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+g98_sec_sclass[] = {
+ { 0x88b4, &nvkm_object_ofuncs },
{},
};
@@ -54,16 +47,16 @@ nv98_sec_sclass[] = {
* PSEC context
******************************************************************************/
-static struct nouveau_oclass
-nv98_sec_cclass = {
+static struct nvkm_oclass
+g98_sec_cclass = {
.handle = NV_ENGCTX(SEC, 0x98),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_falcon_context_ctor,
- .dtor = _nouveau_falcon_context_dtor,
- .init = _nouveau_falcon_context_init,
- .fini = _nouveau_falcon_context_fini,
- .rd32 = _nouveau_falcon_context_rd32,
- .wr32 = _nouveau_falcon_context_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_falcon_context_ctor,
+ .dtor = _nvkm_falcon_context_dtor,
+ .init = _nvkm_falcon_context_init,
+ .fini = _nvkm_falcon_context_fini,
+ .rd32 = _nvkm_falcon_context_rd32,
+ .wr32 = _nvkm_falcon_context_wr32,
},
};
@@ -71,7 +64,7 @@ nv98_sec_cclass = {
* PSEC engine/subdev functions
******************************************************************************/
-static const struct nouveau_enum nv98_sec_isr_error_name[] = {
+static const struct nvkm_enum g98_sec_isr_error_name[] = {
{ 0x0000, "ILLEGAL_MTHD" },
{ 0x0001, "INVALID_BITFIELD" },
{ 0x0002, "INVALID_ENUM" },
@@ -80,12 +73,12 @@ static const struct nouveau_enum nv98_sec_isr_error_name[] = {
};
static void
-nv98_sec_intr(struct nouveau_subdev *subdev)
+g98_sec_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
- struct nouveau_engine *engine = nv_engine(subdev);
- struct nouveau_object *engctx;
- struct nv98_sec_priv *priv = (void *)subdev;
+ struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
+ struct nvkm_engine *engine = nv_engine(subdev);
+ struct nvkm_object *engctx;
+ struct g98_sec_priv *priv = (void *)subdev;
u32 disp = nv_rd32(priv, 0x08701c);
u32 stat = nv_rd32(priv, 0x087008) & disp & ~(disp >> 16);
u32 inst = nv_rd32(priv, 0x087050) & 0x3fffffff;
@@ -96,14 +89,14 @@ nv98_sec_intr(struct nouveau_subdev *subdev)
u32 data = nv_rd32(priv, 0x087044);
int chid;
- engctx = nouveau_engctx_get(engine, inst);
+ engctx = nvkm_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
if (stat & 0x00000040) {
nv_error(priv, "DISPATCH_ERROR [");
- nouveau_enum_print(nv98_sec_isr_error_name, ssta);
+ nvkm_enum_print(g98_sec_isr_error_name, ssta);
pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
- chid, (u64)inst << 12, nouveau_client_name(engctx),
+ chid, (u64)inst << 12, nvkm_client_name(engctx),
subc, mthd, data);
nv_wr32(priv, 0x087004, 0x00000040);
stat &= ~0x00000040;
@@ -114,43 +107,43 @@ nv98_sec_intr(struct nouveau_subdev *subdev)
nv_wr32(priv, 0x087004, stat);
}
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
static int
-nv98_sec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g98_sec_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nv98_sec_priv *priv;
+ struct g98_sec_priv *priv;
int ret;
- ret = nouveau_falcon_create(parent, engine, oclass, 0x087000, true,
- "PSEC", "sec", &priv);
+ ret = nvkm_falcon_create(parent, engine, oclass, 0x087000, true,
+ "PSEC", "sec", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00004000;
- nv_subdev(priv)->intr = nv98_sec_intr;
- nv_engine(priv)->cclass = &nv98_sec_cclass;
- nv_engine(priv)->sclass = nv98_sec_sclass;
- nv_falcon(priv)->code.data = nv98_psec_code;
- nv_falcon(priv)->code.size = sizeof(nv98_psec_code);
- nv_falcon(priv)->data.data = nv98_psec_data;
- nv_falcon(priv)->data.size = sizeof(nv98_psec_data);
+ nv_subdev(priv)->intr = g98_sec_intr;
+ nv_engine(priv)->cclass = &g98_sec_cclass;
+ nv_engine(priv)->sclass = g98_sec_sclass;
+ nv_falcon(priv)->code.data = g98_psec_code;
+ nv_falcon(priv)->code.size = sizeof(g98_psec_code);
+ nv_falcon(priv)->data.data = g98_psec_data;
+ nv_falcon(priv)->data.size = sizeof(g98_psec_data);
return 0;
}
-struct nouveau_oclass
-nv98_sec_oclass = {
+struct nvkm_oclass
+g98_sec_oclass = {
.handle = NV_ENGINE(SEC, 0x98),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv98_sec_ctor,
- .dtor = _nouveau_falcon_dtor,
- .init = _nouveau_falcon_init,
- .fini = _nouveau_falcon_fini,
- .rd32 = _nouveau_falcon_rd32,
- .wr32 = _nouveau_falcon_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g98_sec_ctor,
+ .dtor = _nvkm_falcon_dtor,
+ .init = _nvkm_falcon_init,
+ .fini = _nvkm_falcon_fini,
+ .rd32 = _nvkm_falcon_rd32,
+ .wr32 = _nvkm_falcon_wr32,
},
};
From f84aff4ed4942add5c3bafd8464746209bc1f51c Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:32:15 +1000
Subject: [PATCH 83/86] drm/nouveau/sw: namespace + nvidia gpu names (no binary
change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/core/os.h | 2 +
.../gpu/drm/nouveau/include/nvkm/engine/sw.h | 71 +++++++-------
.../drm/nouveau/nvkm/engine/device/gm100.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 ++--
.../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 16 ++--
drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild | 2 +-
.../nvkm/engine/sw/{nvc0.c => gf100.c} | 68 ++++++--------
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c | 65 ++++++-------
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c | 56 +++++------
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c | 92 +++++++++----------
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h | 35 ++++---
11 files changed, 200 insertions(+), 229 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/sw/{nvc0.c => gf100.c} (73%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 2fe75c15e5ac..0b35ba672265 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -251,5 +251,7 @@
#define nouveau_fifo_chan nvkm_fifo_chan
#define nouveau_fifo nvkm_fifo
#define nouveau_gr nvkm_gr
+#define nouveau_sw nvkm_sw
+#define nouveau_sw_chan nvkm_sw_chan
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
index 4c61a39222bb..a529013c92ab 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
@@ -1,51 +1,50 @@
-#ifndef __NOUVEAU_SW_H__
-#define __NOUVEAU_SW_H__
-
-#include <core/engine.h>
+#ifndef __NVKM_SW_H__
+#define __NVKM_SW_H__
#include <core/engctx.h>
-struct nouveau_sw_chan {
- struct nouveau_engctx base;
+struct nvkm_sw_chan {
+ struct nvkm_engctx base;
int (*flip)(void *);
void *flip_data;
};
-#define nouveau_sw_context_create(p,e,c,d) \
- nouveau_engctx_create((p), (e), (c), (p), 0, 0, 0, (d))
-#define nouveau_sw_context_destroy(d) \
- nouveau_engctx_destroy(&(d)->base)
-#define nouveau_sw_context_init(d) \
- nouveau_engctx_init(&(d)->base)
-#define nouveau_sw_context_fini(d,s) \
- nouveau_engctx_fini(&(d)->base, (s))
+#define nvkm_sw_context_create(p,e,c,d) \
+ nvkm_engctx_create((p), (e), (c), (p), 0, 0, 0, (d))
+#define nvkm_sw_context_destroy(d) \
+ nvkm_engctx_destroy(&(d)->base)
+#define nvkm_sw_context_init(d) \
+ nvkm_engctx_init(&(d)->base)
+#define nvkm_sw_context_fini(d,s) \
+ nvkm_engctx_fini(&(d)->base, (s))
-#define _nouveau_sw_context_dtor _nouveau_engctx_dtor
-#define _nouveau_sw_context_init _nouveau_engctx_init
-#define _nouveau_sw_context_fini _nouveau_engctx_fini
+#define _nvkm_sw_context_dtor _nvkm_engctx_dtor
+#define _nvkm_sw_context_init _nvkm_engctx_init
+#define _nvkm_sw_context_fini _nvkm_engctx_fini
-struct nouveau_sw {
- struct nouveau_engine base;
+#include <core/engine.h>
+
+struct nvkm_sw {
+ struct nvkm_engine base;
};
-#define nouveau_sw_create(p,e,c,d) \
- nouveau_engine_create((p), (e), (c), true, "SW", "software", (d))
-#define nouveau_sw_destroy(d) \
- nouveau_engine_destroy(&(d)->base)
-#define nouveau_sw_init(d) \
- nouveau_engine_init(&(d)->base)
-#define nouveau_sw_fini(d,s) \
- nouveau_engine_fini(&(d)->base, (s))
+#define nvkm_sw_create(p,e,c,d) \
+ nvkm_engine_create((p), (e), (c), true, "SW", "software", (d))
+#define nvkm_sw_destroy(d) \
+ nvkm_engine_destroy(&(d)->base)
+#define nvkm_sw_init(d) \
+ nvkm_engine_init(&(d)->base)
+#define nvkm_sw_fini(d,s) \
+ nvkm_engine_fini(&(d)->base, (s))
-#define _nouveau_sw_dtor _nouveau_engine_dtor
-#define _nouveau_sw_init _nouveau_engine_init
-#define _nouveau_sw_fini _nouveau_engine_fini
+#define _nvkm_sw_dtor _nvkm_engine_dtor
+#define _nvkm_sw_init _nvkm_engine_init
+#define _nvkm_sw_fini _nvkm_engine_fini
-extern struct nouveau_oclass *nv04_sw_oclass;
-extern struct nouveau_oclass *nv10_sw_oclass;
-extern struct nouveau_oclass *nv50_sw_oclass;
-extern struct nouveau_oclass *nvc0_sw_oclass;
-
-void nv04_sw_intr(struct nouveau_subdev *);
+extern struct nvkm_oclass *nv04_sw_oclass;
+extern struct nvkm_oclass *nv10_sw_oclass;
+extern struct nvkm_oclass *nv50_sw_oclass;
+extern struct nvkm_oclass *gf100_sw_oclass;
+void nv04_sw_intr(struct nvkm_subdev *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 4c45f57e81d4..ffa2da42f397 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -85,7 +85,7 @@ gm100_identify(struct nouveau_device *device)
#endif
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
@@ -129,7 +129,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
#if 0
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
#endif
device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index a97671c4338e..887ec05d0c3c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -82,7 +82,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
@@ -115,7 +115,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
@@ -148,7 +148,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
@@ -180,7 +180,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
@@ -213,7 +213,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
@@ -245,7 +245,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
@@ -277,7 +277,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
@@ -310,7 +310,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
@@ -340,7 +340,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index c6e6e6635c93..faaf87b462a6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -82,7 +82,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
@@ -116,7 +116,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
@@ -150,7 +150,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
@@ -176,7 +176,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass;
@@ -206,7 +206,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
@@ -240,7 +240,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
@@ -274,7 +274,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
@@ -307,7 +307,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild
index b8d215900fce..bdc3a05907d5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild
@@ -1,4 +1,4 @@
nvkm-y += nvkm/engine/sw/nv04.o
nvkm-y += nvkm/engine/sw/nv10.o
nvkm-y += nvkm/engine/sw/nv50.o
-nvkm-y += nvkm/engine/sw/nvc0.o
+nvkm-y += nvkm/engine/sw/gf100.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
similarity index 73%
rename from drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
index dcb056eae471..533d5d8ed363 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
@@ -21,25 +21,17 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/event.h>
+#include "nv50.h"
#include <subdev/bar.h>
-#include <engine/sw.h>
-#include <engine/disp.h>
-
-#include "nv50.h"
-
/*******************************************************************************
* software object classes
******************************************************************************/
static int
-nvc0_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+gf100_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
u64 data = *(u32 *)args;
@@ -54,8 +46,8 @@ nvc0_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
}
static int
-nvc0_sw_mthd_mp_control(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+gf100_sw_mthd_mp_control(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
@@ -79,22 +71,22 @@ nvc0_sw_mthd_mp_control(struct nouveau_object *object, u32 mthd,
return 0;
}
-static struct nouveau_omthds
-nvc0_sw_omthds[] = {
- { 0x0400, 0x0400, nvc0_sw_mthd_vblsem_offset },
- { 0x0404, 0x0404, nvc0_sw_mthd_vblsem_offset },
+static struct nvkm_omthds
+gf100_sw_omthds[] = {
+ { 0x0400, 0x0400, gf100_sw_mthd_vblsem_offset },
+ { 0x0404, 0x0404, gf100_sw_mthd_vblsem_offset },
{ 0x0408, 0x0408, nv50_sw_mthd_vblsem_value },
{ 0x040c, 0x040c, nv50_sw_mthd_vblsem_release },
{ 0x0500, 0x0500, nv50_sw_mthd_flip },
- { 0x0600, 0x0600, nvc0_sw_mthd_mp_control },
- { 0x0644, 0x0644, nvc0_sw_mthd_mp_control },
- { 0x06ac, 0x06ac, nvc0_sw_mthd_mp_control },
+ { 0x0600, 0x0600, gf100_sw_mthd_mp_control },
+ { 0x0644, 0x0644, gf100_sw_mthd_mp_control },
+ { 0x06ac, 0x06ac, gf100_sw_mthd_mp_control },
{}
};
-static struct nouveau_oclass
-nvc0_sw_sclass[] = {
- { 0x906e, &nouveau_object_ofuncs, nvc0_sw_omthds },
+static struct nvkm_oclass
+gf100_sw_sclass[] = {
+ { 0x906e, &nvkm_object_ofuncs, gf100_sw_omthds },
{}
};
@@ -103,12 +95,12 @@ nvc0_sw_sclass[] = {
******************************************************************************/
static int
-nvc0_sw_vblsem_release(struct nvkm_notify *notify)
+gf100_sw_vblsem_release(struct nvkm_notify *notify)
{
struct nv50_sw_chan *chan =
container_of(notify, typeof(*chan), vblank.notify[notify->index]);
struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
- struct nouveau_bar *bar = nouveau_bar(priv);
+ struct nvkm_bar *bar = nvkm_bar(priv);
nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
bar->flush(bar);
@@ -120,30 +112,30 @@ nvc0_sw_vblsem_release(struct nvkm_notify *notify)
}
static struct nv50_sw_cclass
-nvc0_sw_cclass = {
+gf100_sw_cclass = {
.base.handle = NV_ENGCTX(SW, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_sw_context_ctor,
.dtor = nv50_sw_context_dtor,
- .init = _nouveau_sw_context_init,
- .fini = _nouveau_sw_context_fini,
+ .init = _nvkm_sw_context_init,
+ .fini = _nvkm_sw_context_fini,
},
- .vblank = nvc0_sw_vblsem_release,
+ .vblank = gf100_sw_vblsem_release,
};
/*******************************************************************************
* software engine/subdev functions
******************************************************************************/
-struct nouveau_oclass *
-nvc0_sw_oclass = &(struct nv50_sw_oclass) {
+struct nvkm_oclass *
+gf100_sw_oclass = &(struct nv50_sw_oclass) {
.base.handle = NV_ENGINE(SW, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_sw_ctor,
- .dtor = _nouveau_sw_dtor,
- .init = _nouveau_sw_init,
- .fini = _nouveau_sw_fini,
+ .dtor = _nvkm_sw_dtor,
+ .init = _nvkm_sw_init,
+ .fini = _nvkm_sw_fini,
},
- .cclass = &nvc0_sw_cclass.base,
- .sclass = nvc0_sw_sclass,
+ .cclass = &gf100_sw_cclass.base,
+ .sclass = gf100_sw_sclass,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
index 3d0e4bc76389..897024421d36 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
@@ -21,19 +21,15 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/os.h>
-#include <core/engctx.h>
-
#include <engine/sw.h>
#include <engine/fifo.h>
struct nv04_sw_priv {
- struct nouveau_sw base;
+ struct nvkm_sw base;
};
struct nv04_sw_chan {
- struct nouveau_sw_chan base;
+ struct nvkm_sw_chan base;
};
/*******************************************************************************
@@ -41,18 +37,16 @@ struct nv04_sw_chan {
******************************************************************************/
static int
-nv04_sw_set_ref(struct nouveau_object *object, u32 mthd,
- void *data, u32 size)
+nv04_sw_set_ref(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
- struct nouveau_object *channel = (void *)nv_engctx(object->parent);
- struct nouveau_fifo_chan *fifo = (void *)channel->parent;
+ struct nvkm_object *channel = (void *)nv_engctx(object->parent);
+ struct nvkm_fifo_chan *fifo = (void *)channel->parent;
atomic_set(&fifo->refcnt, *(u32*)data);
return 0;
}
static int
-nv04_sw_flip(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
{
struct nv04_sw_chan *chan = (void *)nv_engctx(object->parent);
if (chan->base.flip)
@@ -60,16 +54,16 @@ nv04_sw_flip(struct nouveau_object *object, u32 mthd,
return -EINVAL;
}
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_sw_omthds[] = {
{ 0x0150, 0x0150, nv04_sw_set_ref },
{ 0x0500, 0x0500, nv04_sw_flip },
{}
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv04_sw_sclass[] = {
- { 0x006e, &nouveau_object_ofuncs, nv04_sw_omthds },
+ { 0x006e, &nvkm_object_ofuncs, nv04_sw_omthds },
{}
};
@@ -78,15 +72,14 @@ nv04_sw_sclass[] = {
******************************************************************************/
static int
-nv04_sw_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_sw_chan *chan;
int ret;
- ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
+ ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -94,14 +87,14 @@ nv04_sw_context_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv04_sw_cclass = {
.handle = NV_ENGCTX(SW, 0x04),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_sw_context_ctor,
- .dtor = _nouveau_sw_context_dtor,
- .init = _nouveau_sw_context_init,
- .fini = _nouveau_sw_context_fini,
+ .dtor = _nvkm_sw_context_dtor,
+ .init = _nvkm_sw_context_init,
+ .fini = _nvkm_sw_context_fini,
},
};
@@ -110,20 +103,20 @@ nv04_sw_cclass = {
******************************************************************************/
void
-nv04_sw_intr(struct nouveau_subdev *subdev)
+nv04_sw_intr(struct nvkm_subdev *subdev)
{
nv_mask(subdev, 0x000100, 0x80000000, 0x00000000);
}
static int
-nv04_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_sw_priv *priv;
int ret;
- ret = nouveau_sw_create(parent, engine, oclass, &priv);
+ ret = nvkm_sw_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -134,13 +127,13 @@ nv04_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
-nv04_sw_oclass = &(struct nouveau_oclass) {
+struct nvkm_oclass *
+nv04_sw_oclass = &(struct nvkm_oclass) {
.handle = NV_ENGINE(SW, 0x04),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_sw_ctor,
- .dtor = _nouveau_sw_dtor,
- .init = _nouveau_sw_init,
- .fini = _nouveau_sw_fini,
+ .dtor = _nvkm_sw_dtor,
+ .init = _nvkm_sw_init,
+ .fini = _nvkm_sw_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
index 12775cdbde70..c61153a3fb8b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
@@ -21,18 +21,14 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/os.h>
-#include <core/engctx.h>
-
#include <engine/sw.h>
struct nv10_sw_priv {
- struct nouveau_sw base;
+ struct nvkm_sw base;
};
struct nv10_sw_chan {
- struct nouveau_sw_chan base;
+ struct nvkm_sw_chan base;
};
/*******************************************************************************
@@ -40,8 +36,7 @@ struct nv10_sw_chan {
******************************************************************************/
static int
-nv10_sw_flip(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv10_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
{
struct nv10_sw_chan *chan = (void *)nv_engctx(object->parent);
if (chan->base.flip)
@@ -49,15 +44,15 @@ nv10_sw_flip(struct nouveau_object *object, u32 mthd,
return -EINVAL;
}
-static struct nouveau_omthds
+static struct nvkm_omthds
nv10_sw_omthds[] = {
{ 0x0500, 0x0500, nv10_sw_flip },
{}
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv10_sw_sclass[] = {
- { 0x016e, &nouveau_object_ofuncs, nv10_sw_omthds },
+ { 0x016e, &nvkm_object_ofuncs, nv10_sw_omthds },
{}
};
@@ -66,15 +61,14 @@ nv10_sw_sclass[] = {
******************************************************************************/
static int
-nv10_sw_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv10_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv10_sw_chan *chan;
int ret;
- ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
+ ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -82,14 +76,14 @@ nv10_sw_context_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv10_sw_cclass = {
.handle = NV_ENGCTX(SW, 0x04),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv10_sw_context_ctor,
- .dtor = _nouveau_sw_context_dtor,
- .init = _nouveau_sw_context_init,
- .fini = _nouveau_sw_context_fini,
+ .dtor = _nvkm_sw_context_dtor,
+ .init = _nvkm_sw_context_init,
+ .fini = _nvkm_sw_context_fini,
},
};
@@ -98,14 +92,14 @@ nv10_sw_cclass = {
******************************************************************************/
static int
-nv10_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv10_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv10_sw_priv *priv;
int ret;
- ret = nouveau_sw_create(parent, engine, oclass, &priv);
+ ret = nvkm_sw_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -116,13 +110,13 @@ nv10_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
-nv10_sw_oclass = &(struct nouveau_oclass) {
+struct nvkm_oclass *
+nv10_sw_oclass = &(struct nvkm_oclass) {
.handle = NV_ENGINE(SW, 0x10),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv10_sw_ctor,
- .dtor = _nouveau_sw_dtor,
- .init = _nouveau_sw_init,
- .fini = _nouveau_sw_fini,
+ .dtor = _nvkm_sw_dtor,
+ .init = _nvkm_sw_init,
+ .fini = _nvkm_sw_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
index 6833e00827c2..401fcd73086b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
@@ -21,51 +21,45 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
-#include <core/os.h>
#include <core/device.h>
-#include <core/engctx.h>
-#include <core/namedb.h>
#include <core/handle.h>
-#include <core/gpuobj.h>
-#include <core/event.h>
-#include <nvif/event.h>
-
+#include <core/namedb.h>
+#include <engine/disp.h>
#include <subdev/bar.h>
-#include <engine/disp.h>
-
-#include "nv50.h"
+#include <nvif/event.h>
/*******************************************************************************
* software object classes
******************************************************************************/
static int
-nv50_sw_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv50_sw_mthd_dma_vblsem(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
- struct nouveau_fifo_chan *fifo = (void *)nv_object(chan)->parent;
- struct nouveau_handle *handle;
+ struct nvkm_fifo_chan *fifo = (void *)nv_object(chan)->parent;
+ struct nvkm_handle *handle;
int ret = -EINVAL;
- handle = nouveau_namedb_get(nv_namedb(fifo), *(u32 *)args);
+ handle = nvkm_namedb_get(nv_namedb(fifo), *(u32 *)args);
if (!handle)
return -ENOENT;
if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
- struct nouveau_gpuobj *gpuobj = nv_gpuobj(handle->object);
+ struct nvkm_gpuobj *gpuobj = nv_gpuobj(handle->object);
chan->vblank.ctxdma = gpuobj->node->offset >> 4;
ret = 0;
}
- nouveau_namedb_put(handle);
+ nvkm_namedb_put(handle);
return ret;
}
static int
-nv50_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv50_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
chan->vblank.offset = *(u32 *)args;
@@ -73,8 +67,8 @@ nv50_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
}
int
-nv50_sw_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv50_sw_mthd_vblsem_value(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
chan->vblank.value = *(u32 *)args;
@@ -82,12 +76,12 @@ nv50_sw_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
}
int
-nv50_sw_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv50_sw_mthd_vblsem_release(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
u32 head = *(u32 *)args;
- if (head >= nouveau_disp(chan)->vblank.index_nr)
+ if (head >= nvkm_disp(chan)->vblank.index_nr)
return -EINVAL;
nvkm_notify_get(&chan->vblank.notify[head]);
@@ -95,8 +89,7 @@ nv50_sw_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
}
int
-nv50_sw_mthd_flip(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv50_sw_mthd_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
{
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
if (chan->base.flip)
@@ -104,7 +97,7 @@ nv50_sw_mthd_flip(struct nouveau_object *object, u32 mthd,
return -EINVAL;
}
-static struct nouveau_omthds
+static struct nvkm_omthds
nv50_sw_omthds[] = {
{ 0x018c, 0x018c, nv50_sw_mthd_dma_vblsem },
{ 0x0400, 0x0400, nv50_sw_mthd_vblsem_offset },
@@ -114,9 +107,9 @@ nv50_sw_omthds[] = {
{}
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv50_sw_sclass[] = {
- { 0x506e, &nouveau_object_ofuncs, nv50_sw_omthds },
+ { 0x506e, &nvkm_object_ofuncs, nv50_sw_omthds },
{}
};
@@ -130,7 +123,7 @@ nv50_sw_vblsem_release(struct nvkm_notify *notify)
struct nv50_sw_chan *chan =
container_of(notify, typeof(*chan), vblank.notify[notify->index]);
struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
- struct nouveau_bar *bar = nouveau_bar(priv);
+ struct nvkm_bar *bar = nvkm_bar(priv);
nv_wr32(priv, 0x001704, chan->vblank.channel);
nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
@@ -148,7 +141,7 @@ nv50_sw_vblsem_release(struct nvkm_notify *notify)
}
void
-nv50_sw_context_dtor(struct nouveau_object *object)
+nv50_sw_context_dtor(struct nvkm_object *object)
{
struct nv50_sw_chan *chan = (void *)object;
int i;
@@ -156,21 +149,20 @@ nv50_sw_context_dtor(struct nouveau_object *object)
for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++)
nvkm_notify_fini(&chan->vblank.notify[i]);
- nouveau_sw_context_destroy(&chan->base);
+ nvkm_sw_context_destroy(&chan->base);
}
int
-nv50_sw_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_disp *pdisp = nouveau_disp(parent);
+ struct nvkm_disp *pdisp = nvkm_disp(parent);
struct nv50_sw_cclass *pclass = (void *)oclass;
struct nv50_sw_chan *chan;
int ret, i;
- ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
+ ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -195,11 +187,11 @@ nv50_sw_context_ctor(struct nouveau_object *parent,
static struct nv50_sw_cclass
nv50_sw_cclass = {
.base.handle = NV_ENGCTX(SW, 0x50),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_sw_context_ctor,
.dtor = nv50_sw_context_dtor,
- .init = _nouveau_sw_context_init,
- .fini = _nouveau_sw_context_fini,
+ .init = _nvkm_sw_context_init,
+ .fini = _nvkm_sw_context_fini,
},
.vblank = nv50_sw_vblsem_release,
};
@@ -209,15 +201,15 @@ nv50_sw_cclass = {
******************************************************************************/
int
-nv50_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_sw_oclass *pclass = (void *)oclass;
struct nv50_sw_priv *priv;
int ret;
- ret = nouveau_sw_create(parent, engine, oclass, &priv);
+ ret = nvkm_sw_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -228,14 +220,14 @@ nv50_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass *
+struct nvkm_oclass *
nv50_sw_oclass = &(struct nv50_sw_oclass) {
.base.handle = NV_ENGINE(SW, 0x50),
- .base.ofuncs = &(struct nouveau_ofuncs) {
+ .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_sw_ctor,
- .dtor = _nouveau_sw_dtor,
- .init = _nouveau_sw_init,
- .fini = _nouveau_sw_fini,
+ .dtor = _nvkm_sw_dtor,
+ .init = _nvkm_sw_init,
+ .fini = _nvkm_sw_fini,
},
.cclass = &nv50_sw_cclass.base,
.sclass = nv50_sw_sclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
index fa0a236004d6..d8adc1108467 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
@@ -4,26 +4,26 @@
#include <core/notify.h>
struct nv50_sw_oclass {
- struct nouveau_oclass base;
- struct nouveau_oclass *cclass;
- struct nouveau_oclass *sclass;
+ struct nvkm_oclass base;
+ struct nvkm_oclass *cclass;
+ struct nvkm_oclass *sclass;
};
struct nv50_sw_priv {
- struct nouveau_sw base;
+ struct nvkm_sw base;
};
-int nv50_sw_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
+int nv50_sw_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
struct nv50_sw_cclass {
- struct nouveau_oclass base;
+ struct nvkm_oclass base;
int (*vblank)(struct nvkm_notify *);
};
struct nv50_sw_chan {
- struct nouveau_sw_chan base;
+ struct nvkm_sw_chan base;
struct {
struct nvkm_notify notify[4];
u32 channel;
@@ -33,14 +33,13 @@ struct nv50_sw_chan {
} vblank;
};
-int nv50_sw_context_ctor(struct nouveau_object *,
- struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nv50_sw_context_dtor(struct nouveau_object *);
-
-int nv50_sw_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32);
-int nv50_sw_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32);
-int nv50_sw_mthd_flip(struct nouveau_object *, u32, void *, u32);
+int nv50_sw_context_ctor(struct nvkm_object *,
+ struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void nv50_sw_context_dtor(struct nvkm_object *);
+int nv50_sw_mthd_vblsem_value(struct nvkm_object *, u32, void *, u32);
+int nv50_sw_mthd_vblsem_release(struct nvkm_object *, u32, void *, u32);
+int nv50_sw_mthd_flip(struct nvkm_object *, u32, void *, u32);
#endif
From a56866a9809d276e3bf9aee27466cee385d2b5e6 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:32:28 +1000
Subject: [PATCH 84/86] drm/nouveau/vp: namespace + nvidia gpu names (no binary
change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../gpu/drm/nouveau/include/nvkm/engine/vp.h | 7 ++-
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 12 ++--
drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild | 2 +-
.../nouveau/nvkm/engine/vp/{nv84.c => g84.c} | 61 +++++++++----------
4 files changed, 41 insertions(+), 41 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/vp/{nv84.c => g84.c} (66%)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
index 7175e6e032cc..7851f18c5add 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
@@ -1,4 +1,5 @@
-#ifndef __NOUVEAU_VP_H__
-#define __NOUVEAU_VP_H__
-extern struct nouveau_oclass nv84_vp_oclass;
+#ifndef __NVKM_VP_H__
+#define __NVKM_VP_H__
+#include <core/engine.h>
+extern struct nvkm_oclass g84_vp_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index bf3998b96bc4..36944babbb53 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -110,7 +110,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
+ device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
@@ -139,7 +139,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
+ device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
@@ -168,7 +168,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
+ device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
@@ -197,7 +197,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
+ device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
@@ -226,7 +226,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
+ device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
@@ -284,7 +284,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
+ device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
index e4bfb6eb3d21..6b390eb92b0e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
@@ -1 +1 @@
-nvkm-y += nvkm/engine/vp/nv84.o
+nvkm-y += nvkm/engine/vp/g84.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c
similarity index 66%
rename from drivers/gpu/drm/nouveau/nvkm/engine/vp/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c
index 9caa037b7a6b..45f4e186befc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c
@@ -21,9 +21,8 @@
*
* Authors: Ben Skeggs, Ilia Mirkin
*/
-
-#include <engine/xtensa.h>
#include <engine/vp.h>
+#include <engine/xtensa.h>
#include <core/engctx.h>
@@ -31,9 +30,9 @@
* VP object classes
******************************************************************************/
-static struct nouveau_oclass
-nv84_vp_sclass[] = {
- { 0x7476, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+g84_vp_sclass[] = {
+ { 0x7476, &nvkm_object_ofuncs },
{},
};
@@ -41,16 +40,16 @@ nv84_vp_sclass[] = {
* PVP context
******************************************************************************/
-static struct nouveau_oclass
-nv84_vp_cclass = {
+static struct nvkm_oclass
+g84_vp_cclass = {
.handle = NV_ENGCTX(VP, 0x84),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = _nouveau_xtensa_engctx_ctor,
- .dtor = _nouveau_engctx_dtor,
- .init = _nouveau_engctx_init,
- .fini = _nouveau_engctx_fini,
- .rd32 = _nouveau_engctx_rd32,
- .wr32 = _nouveau_engctx_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = _nvkm_xtensa_engctx_ctor,
+ .dtor = _nvkm_engctx_dtor,
+ .init = _nvkm_engctx_init,
+ .fini = _nvkm_engctx_fini,
+ .rd32 = _nvkm_engctx_rd32,
+ .wr32 = _nvkm_engctx_wr32,
},
};
@@ -59,36 +58,36 @@ nv84_vp_cclass = {
******************************************************************************/
static int
-nv84_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+g84_vp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_xtensa *priv;
+ struct nvkm_xtensa *priv;
int ret;
- ret = nouveau_xtensa_create(parent, engine, oclass, 0xf000, true,
- "PVP", "vp", &priv);
+ ret = nvkm_xtensa_create(parent, engine, oclass, 0xf000, true,
+ "PVP", "vp", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x01020000;
- nv_engine(priv)->cclass = &nv84_vp_cclass;
- nv_engine(priv)->sclass = nv84_vp_sclass;
+ nv_engine(priv)->cclass = &g84_vp_cclass;
+ nv_engine(priv)->sclass = g84_vp_sclass;
priv->fifo_val = 0x111;
priv->unkd28 = 0x9c544;
return 0;
}
-struct nouveau_oclass
-nv84_vp_oclass = {
+struct nvkm_oclass
+g84_vp_oclass = {
.handle = NV_ENGINE(VP, 0x84),
- .ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv84_vp_ctor,
- .dtor = _nouveau_xtensa_dtor,
- .init = _nouveau_xtensa_init,
- .fini = _nouveau_xtensa_fini,
- .rd32 = _nouveau_xtensa_rd32,
- .wr32 = _nouveau_xtensa_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = g84_vp_ctor,
+ .dtor = _nvkm_xtensa_dtor,
+ .init = _nvkm_xtensa_init,
+ .fini = _nvkm_xtensa_fini,
+ .rd32 = _nvkm_xtensa_rd32,
+ .wr32 = _nvkm_xtensa_wr32,
},
};
From 9719047b4d985ca7a46819956047cca04213d63e Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:35:00 +1000
Subject: [PATCH 85/86] drm/nouveau/device: namespace + nvidia gpu names (no
binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/include/nvif/device.h | 2 +-
.../drm/nouveau/include/nvkm/core/device.h | 14 +
.../gpu/drm/nouveau/include/nvkm/core/os.h | 2 +
drivers/gpu/drm/nouveau/nouveau_drm.c | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/Kbuild | 4 +-
.../gpu/drm/nouveau/nvkm/engine/device/acpi.c | 9 +-
.../gpu/drm/nouveau/nvkm/engine/device/acpi.h | 9 +-
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 249 +++++++++---------
.../gpu/drm/nouveau/nvkm/engine/device/ctrl.c | 72 +++--
.../nvkm/engine/device/{nvc0.c => gf100.c} | 24 +-
.../nvkm/engine/device/{nve0.c => gk104.c} | 18 +-
.../drm/nouveau/nvkm/engine/device/gm100.c | 8 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv04.c | 8 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv10.c | 20 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv20.c | 12 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv30.c | 14 +-
.../gpu/drm/nouveau/nvkm/engine/device/nv40.c | 36 +--
.../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 32 +--
.../gpu/drm/nouveau/nvkm/engine/device/priv.h | 14 +-
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h | 3 +-
20 files changed, 283 insertions(+), 271 deletions(-)
rename drivers/gpu/drm/nouveau/nvkm/engine/device/{nvc0.c => gf100.c} (96%)
rename drivers/gpu/drm/nouveau/nvkm/engine/device/{nve0.c => gk104.c} (96%)
diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h
index 1d186e21d123..1fafcac299d3 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/device.h
@@ -50,7 +50,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
#define nvxx_wait_cb(a,b,c) nv_wait_cb(nvxx_timer(a), (b), (c))
#define nvxx_therm(a) nouveau_therm(nvxx_device(a))
-#include <engine/device.h>
+#include <core/device.h>
#include <engine/fifo.h>
#include <engine/gr.h>
#include <engine/sw.h>
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 9c2f13694a57..333db33a162c 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -84,4 +84,18 @@ nv_device_resource_len(struct nvkm_device *device, unsigned int bar);
int
nv_device_get_irq(struct nvkm_device *device, bool stall);
+
+struct platform_device;
+
+enum nv_bus_type {
+ NVKM_BUS_PCI,
+ NVKM_BUS_PLATFORM,
+};
+
+#define nvkm_device_create(p,t,n,s,c,d,u) \
+ nvkm_device_create_((void *)(p), (t), (n), (s), (c), (d), \
+ sizeof(**u), (void **)u)
+int nvkm_device_create_(void *, enum nv_bus_type type, u64 name,
+ const char *sname, const char *cfg, const char *dbg,
+ int, void **);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 0b35ba672265..537db3a512c8 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -253,5 +253,7 @@
#define nouveau_gr nvkm_gr
#define nouveau_sw nvkm_sw
#define nouveau_sw_chan nvkm_sw_chan
+#define nouveau_device_create nvkm_device_create
+#define nouveau_device_create_ nvkm_device_create_
#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 1de82ec6c276..f4ac7b5af85e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -318,7 +318,7 @@ static int nouveau_drm_probe(struct pci_dev *pdev,
remove_conflicting_framebuffers(aper, "nouveaufb", boot);
kfree(aper);
- ret = nouveau_device_create(pdev, NOUVEAU_BUS_PCI,
+ ret = nouveau_device_create(pdev, NVKM_BUS_PCI,
nouveau_pci_name(pdev), pci_name(pdev),
nouveau_config, nouveau_debug, &device);
if (ret)
@@ -1056,7 +1056,7 @@ nouveau_platform_device_create_(struct platform_device *pdev, int size,
struct drm_device *drm;
int err;
- err = nouveau_device_create_(pdev, NOUVEAU_BUS_PLATFORM,
+ err = nouveau_device_create_(pdev, NVKM_BUS_PLATFORM,
nouveau_platform_name(pdev),
dev_name(&pdev->dev), nouveau_config,
nouveau_debug, size, pobject);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild
index 77d06d46eff4..de1bf092b2b2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild
@@ -7,6 +7,6 @@ nvkm-y += nvkm/engine/device/nv20.o
nvkm-y += nvkm/engine/device/nv30.o
nvkm-y += nvkm/engine/device/nv40.o
nvkm-y += nvkm/engine/device/nv50.o
-nvkm-y += nvkm/engine/device/nvc0.o
-nvkm-y += nvkm/engine/device/nve0.o
+nvkm-y += nvkm/engine/device/gf100.o
+nvkm-y += nvkm/engine/device/gk104.o
nvkm-y += nvkm/engine/device/gm100.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c
index 4dbf0ba89e5c..f42706e1d5db 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c
@@ -21,14 +21,15 @@
*
* Authors: Ben Skeggs
*/
-
#include "acpi.h"
+#include <core/device.h>
+
#ifdef CONFIG_ACPI
static int
nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data)
{
- struct nouveau_device *device =
+ struct nvkm_device *device =
container_of(nb, typeof(*device), acpi.nb);
struct acpi_bus_event *info = data;
@@ -40,7 +41,7 @@ nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data)
#endif
int
-nvkm_acpi_fini(struct nouveau_device *device, bool suspend)
+nvkm_acpi_fini(struct nvkm_device *device, bool suspend)
{
#ifdef CONFIG_ACPI
unregister_acpi_notifier(&device->acpi.nb);
@@ -49,7 +50,7 @@ nvkm_acpi_fini(struct nouveau_device *device, bool suspend)
}
int
-nvkm_acpi_init(struct nouveau_device *device)
+nvkm_acpi_init(struct nvkm_device *device)
{
#ifdef CONFIG_ACPI
device->acpi.nb.notifier_call = nvkm_acpi_ntfy;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h
index cc49f4f568cd..82dd359ddfa4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h
@@ -1,9 +1,8 @@
#ifndef __NVKM_DEVICE_ACPI_H__
#define __NVKM_DEVICE_ACPI_H__
+#include <core/os.h>
+struct nvkm_device;
-#include <engine/device.h>
-
-int nvkm_acpi_init(struct nouveau_device *);
-int nvkm_acpi_fini(struct nouveau_device *, bool);
-
+int nvkm_acpi_init(struct nvkm_device *);
+int nvkm_acpi_fini(struct nvkm_device *, bool);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index ae2ad8b4e5df..29bd539af183 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -21,29 +21,27 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
+#include "acpi.h"
-#include <core/notify.h>
-#include <core/object.h>
-#include <core/device.h>
#include <core/client.h>
#include <core/option.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
+#include <core/notify.h>
+#include <core/parent.h>
#include <subdev/bios.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
-#include "priv.h"
-#include "acpi.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
static DEFINE_MUTEX(nv_devices_mutex);
static LIST_HEAD(nv_devices);
-struct nouveau_device *
-nouveau_device_find(u64 name)
+struct nvkm_device *
+nvkm_device_find(u64 name)
{
- struct nouveau_device *device, *match = NULL;
+ struct nvkm_device *device, *match = NULL;
mutex_lock(&nv_devices_mutex);
list_for_each_entry(device, &nv_devices, head) {
if (device->handle == name) {
@@ -56,9 +54,9 @@ nouveau_device_find(u64 name)
}
int
-nouveau_device_list(u64 *name, int size)
+nvkm_device_list(u64 *name, int size)
{
- struct nouveau_device *device;
+ struct nvkm_device *device;
int nr = 0;
mutex_lock(&nv_devices_mutex);
list_for_each_entry(device, &nv_devices, head) {
@@ -70,20 +68,20 @@ nouveau_device_list(u64 *name, int size)
}
/******************************************************************************
- * nouveau_devobj (0x0080): class implementation
+ * nvkm_devobj (0x0080): class implementation
*****************************************************************************/
-struct nouveau_devobj {
- struct nouveau_parent base;
- struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
+struct nvkm_devobj {
+ struct nvkm_parent base;
+ struct nvkm_object *subdev[NVDEV_SUBDEV_NR];
};
static int
-nouveau_devobj_info(struct nouveau_object *object, void *data, u32 size)
+nvkm_devobj_info(struct nvkm_object *object, void *data, u32 size)
{
- struct nouveau_device *device = nv_device(object);
- struct nouveau_fb *pfb = nouveau_fb(device);
- struct nouveau_instmem *imem = nouveau_instmem(device);
+ struct nvkm_device *device = nv_device(object);
+ struct nvkm_fb *pfb = nvkm_fb(device);
+ struct nvkm_instmem *imem = nvkm_instmem(device);
union {
struct nv_device_info_v0 v0;
} *args = data;
@@ -148,12 +146,11 @@ nouveau_devobj_info(struct nouveau_object *object, void *data, u32 size)
}
static int
-nouveau_devobj_mthd(struct nouveau_object *object, u32 mthd,
- void *data, u32 size)
+nvkm_devobj_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
switch (mthd) {
case NV_DEVICE_V0_INFO:
- return nouveau_devobj_info(object, data, size);
+ return nvkm_devobj_info(object, data, size);
default:
break;
}
@@ -161,45 +158,45 @@ nouveau_devobj_mthd(struct nouveau_object *object, u32 mthd,
}
static u8
-nouveau_devobj_rd08(struct nouveau_object *object, u64 addr)
+nvkm_devobj_rd08(struct nvkm_object *object, u64 addr)
{
return nv_rd08(object->engine, addr);
}
static u16
-nouveau_devobj_rd16(struct nouveau_object *object, u64 addr)
+nvkm_devobj_rd16(struct nvkm_object *object, u64 addr)
{
return nv_rd16(object->engine, addr);
}
static u32
-nouveau_devobj_rd32(struct nouveau_object *object, u64 addr)
+nvkm_devobj_rd32(struct nvkm_object *object, u64 addr)
{
return nv_rd32(object->engine, addr);
}
static void
-nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data)
+nvkm_devobj_wr08(struct nvkm_object *object, u64 addr, u8 data)
{
nv_wr08(object->engine, addr, data);
}
static void
-nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data)
+nvkm_devobj_wr16(struct nvkm_object *object, u64 addr, u16 data)
{
nv_wr16(object->engine, addr, data);
}
static void
-nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
+nvkm_devobj_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
nv_wr32(object->engine, addr, data);
}
static int
-nouveau_devobj_map(struct nouveau_object *object, u64 *addr, u32 *size)
+nvkm_devobj_map(struct nvkm_object *object, u64 *addr, u32 *size)
{
- struct nouveau_device *device = nv_device(object);
+ struct nvkm_device *device = nv_device(object);
*addr = nv_device_resource_start(device, 0);
*size = nv_device_resource_len(device, 0);
return 0;
@@ -248,47 +245,46 @@ static const u64 disable_map[] = {
};
static void
-nouveau_devobj_dtor(struct nouveau_object *object)
+nvkm_devobj_dtor(struct nvkm_object *object)
{
- struct nouveau_devobj *devobj = (void *)object;
+ struct nvkm_devobj *devobj = (void *)object;
int i;
for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--)
- nouveau_object_ref(NULL, &devobj->subdev[i]);
+ nvkm_object_ref(NULL, &devobj->subdev[i]);
- nouveau_parent_destroy(&devobj->base);
+ nvkm_parent_destroy(&devobj->base);
}
-static struct nouveau_oclass
-nouveau_devobj_oclass_super = {
+static struct nvkm_oclass
+nvkm_devobj_oclass_super = {
.handle = NV_DEVICE,
- .ofuncs = &(struct nouveau_ofuncs) {
- .dtor = nouveau_devobj_dtor,
- .init = _nouveau_parent_init,
- .fini = _nouveau_parent_fini,
- .mthd = nouveau_devobj_mthd,
- .map = nouveau_devobj_map,
- .rd08 = nouveau_devobj_rd08,
- .rd16 = nouveau_devobj_rd16,
- .rd32 = nouveau_devobj_rd32,
- .wr08 = nouveau_devobj_wr08,
- .wr16 = nouveau_devobj_wr16,
- .wr32 = nouveau_devobj_wr32,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .dtor = nvkm_devobj_dtor,
+ .init = _nvkm_parent_init,
+ .fini = _nvkm_parent_fini,
+ .mthd = nvkm_devobj_mthd,
+ .map = nvkm_devobj_map,
+ .rd08 = nvkm_devobj_rd08,
+ .rd16 = nvkm_devobj_rd16,
+ .rd32 = nvkm_devobj_rd32,
+ .wr08 = nvkm_devobj_wr08,
+ .wr16 = nvkm_devobj_wr16,
+ .wr32 = nvkm_devobj_wr32,
}
};
static int
-nouveau_devobj_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
union {
struct nv_device_v0 v0;
} *args = data;
- struct nouveau_client *client = nv_client(parent);
- struct nouveau_device *device;
- struct nouveau_devobj *devobj;
+ struct nvkm_client *client = nv_client(parent);
+ struct nvkm_device *device;
+ struct nvkm_devobj *devobj;
u32 boot0, strap;
u64 disable, mmio_base, mmio_size;
void __iomem *map;
@@ -305,22 +301,22 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
/* give priviledged clients register access */
if (client->super)
- oclass = &nouveau_devobj_oclass_super;
+ oclass = &nvkm_devobj_oclass_super;
/* find the device subdev that matches what the client requested */
device = nv_device(client->device);
if (args->v0.device != ~0) {
- device = nouveau_device_find(args->v0.device);
+ device = nvkm_device_find(args->v0.device);
if (!device)
return -ENODEV;
}
- ret = nouveau_parent_create(parent, nv_object(device), oclass, 0,
- nouveau_control_oclass,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_FIFO) |
- (1ULL << NVDEV_ENGINE_DISP) |
- (1ULL << NVDEV_ENGINE_PM ), &devobj);
+ ret = nvkm_parent_create(parent, nv_object(device), oclass, 0,
+ nvkm_control_oclass,
+ (1ULL << NVDEV_ENGINE_DMAOBJ) |
+ (1ULL << NVDEV_ENGINE_FIFO) |
+ (1ULL << NVDEV_ENGINE_DISP) |
+ (1ULL << NVDEV_ENGINE_PM), &devobj);
*pobject = nv_object(devobj);
if (ret)
return ret;
@@ -403,8 +399,8 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
case NV_30: ret = nv30_identify(device); break;
case NV_40: ret = nv40_identify(device); break;
case NV_50: ret = nv50_identify(device); break;
- case NV_C0: ret = nvc0_identify(device); break;
- case NV_E0: ret = nve0_identify(device); break;
+ case NV_C0: ret = gf100_identify(device); break;
+ case NV_E0: ret = gk104_identify(device); break;
case GM100: ret = gm100_identify(device); break;
default:
ret = -EINVAL;
@@ -439,7 +435,7 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
} else
if ( (args->v0.disable & NV_DEVICE_V0_DISABLE_IDENTIFY)) {
device->cname = "NULL";
- device->oclass[NVDEV_SUBDEV_VBIOS] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS] = &nvkm_bios_oclass;
}
if (!(args->v0.disable & NV_DEVICE_V0_DISABLE_MMIO) &&
@@ -457,14 +453,12 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
continue;
if (device->subdev[i]) {
- nouveau_object_ref(device->subdev[i],
- &devobj->subdev[i]);
+ nvkm_object_ref(device->subdev[i], &devobj->subdev[i]);
continue;
}
- ret = nouveau_object_ctor(nv_object(device), NULL,
- oclass, NULL, i,
- &devobj->subdev[i]);
+ ret = nvkm_object_ctor(nv_object(device), NULL, oclass,
+ NULL, i, &devobj->subdev[i]);
if (ret == -ENODEV)
continue;
if (ret)
@@ -482,15 +476,15 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
* subdev in turn as they're created.
*/
while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) {
- struct nouveau_object *subdev = devobj->subdev[c++];
+ struct nvkm_object *subdev = devobj->subdev[c++];
if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) {
- ret = nouveau_object_inc(subdev);
+ ret = nvkm_object_inc(subdev);
if (ret)
return ret;
atomic_dec(&nv_object(device)->usecount);
} else
if (subdev) {
- nouveau_subdev_reset(subdev);
+ nvkm_subdev_reset(subdev);
}
}
}
@@ -498,23 +492,23 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
return 0;
}
-static struct nouveau_ofuncs
-nouveau_devobj_ofuncs = {
- .ctor = nouveau_devobj_ctor,
- .dtor = nouveau_devobj_dtor,
- .init = _nouveau_parent_init,
- .fini = _nouveau_parent_fini,
- .mthd = nouveau_devobj_mthd,
+static struct nvkm_ofuncs
+nvkm_devobj_ofuncs = {
+ .ctor = nvkm_devobj_ctor,
+ .dtor = nvkm_devobj_dtor,
+ .init = _nvkm_parent_init,
+ .fini = _nvkm_parent_fini,
+ .mthd = nvkm_devobj_mthd,
};
/******************************************************************************
- * nouveau_device: engine functions
+ * nvkm_device: engine functions
*****************************************************************************/
-struct nouveau_device *
+struct nvkm_device *
nv_device(void *obj)
{
- struct nouveau_object *device = nv_object(obj);
+ struct nvkm_object *device = nv_object(obj);
if (device->engine == NULL) {
while (device && device->parent)
device = device->parent;
@@ -530,15 +524,15 @@ nv_device(void *obj)
return (void *)device;
}
-static struct nouveau_oclass
-nouveau_device_sclass[] = {
- { 0x0080, &nouveau_devobj_ofuncs },
+static struct nvkm_oclass
+nvkm_device_sclass[] = {
+ { 0x0080, &nvkm_devobj_ofuncs },
{}
};
static int
-nouveau_device_event_ctor(struct nouveau_object *object, void *data, u32 size,
- struct nvkm_notify *notify)
+nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size,
+ struct nvkm_notify *notify)
{
if (!WARN_ON(size != 0)) {
notify->size = 0;
@@ -550,21 +544,21 @@ nouveau_device_event_ctor(struct nouveau_object *object, void *data, u32 size,
}
static const struct nvkm_event_func
-nouveau_device_event_func = {
- .ctor = nouveau_device_event_ctor,
+nvkm_device_event_func = {
+ .ctor = nvkm_device_event_ctor,
};
static int
-nouveau_device_fini(struct nouveau_object *object, bool suspend)
+nvkm_device_fini(struct nvkm_object *object, bool suspend)
{
- struct nouveau_device *device = (void *)object;
- struct nouveau_object *subdev;
+ struct nvkm_device *device = (void *)object;
+ struct nvkm_object *subdev;
int ret, i;
for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
if ((subdev = device->subdev[i])) {
if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
- ret = nouveau_object_dec(subdev, suspend);
+ ret = nvkm_object_dec(subdev, suspend);
if (ret && suspend)
goto fail;
}
@@ -576,7 +570,7 @@ fail:
for (; ret && i < NVDEV_SUBDEV_NR; i++) {
if ((subdev = device->subdev[i])) {
if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
- ret = nouveau_object_inc(subdev);
+ ret = nvkm_object_inc(subdev);
if (ret) {
/* XXX */
}
@@ -588,10 +582,10 @@ fail:
}
static int
-nouveau_device_init(struct nouveau_object *object)
+nvkm_device_init(struct nvkm_object *object)
{
- struct nouveau_device *device = (void *)object;
- struct nouveau_object *subdev;
+ struct nvkm_device *device = (void *)object;
+ struct nvkm_object *subdev;
int ret, i = 0;
ret = nvkm_acpi_init(device);
@@ -601,11 +595,11 @@ nouveau_device_init(struct nouveau_object *object)
for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
if ((subdev = device->subdev[i])) {
if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
- ret = nouveau_object_inc(subdev);
+ ret = nvkm_object_inc(subdev);
if (ret)
goto fail;
} else {
- nouveau_subdev_reset(subdev);
+ nvkm_subdev_reset(subdev);
}
}
}
@@ -615,7 +609,7 @@ fail:
for (--i; ret && i >= 0; i--) {
if ((subdev = device->subdev[i])) {
if (!nv_iclass(subdev, NV_ENGINE_CLASS))
- nouveau_object_dec(subdev, false);
+ nvkm_object_dec(subdev, false);
}
}
@@ -625,9 +619,9 @@ fail:
}
static void
-nouveau_device_dtor(struct nouveau_object *object)
+nvkm_device_dtor(struct nvkm_object *object)
{
- struct nouveau_device *device = (void *)object;
+ struct nvkm_device *device = (void *)object;
nvkm_event_fini(&device->event);
@@ -638,11 +632,11 @@ nouveau_device_dtor(struct nouveau_object *object)
if (nv_subdev(device)->mmio)
iounmap(nv_subdev(device)->mmio);
- nouveau_engine_destroy(&device->engine);
+ nvkm_engine_destroy(&device->engine);
}
resource_size_t
-nv_device_resource_start(struct nouveau_device *device, unsigned int bar)
+nv_device_resource_start(struct nvkm_device *device, unsigned int bar)
{
if (nv_device_is_pci(device)) {
return pci_resource_start(device->pdev, bar);
@@ -657,7 +651,7 @@ nv_device_resource_start(struct nouveau_device *device, unsigned int bar)
}
resource_size_t
-nv_device_resource_len(struct nouveau_device *device, unsigned int bar)
+nv_device_resource_len(struct nvkm_device *device, unsigned int bar)
{
if (nv_device_is_pci(device)) {
return pci_resource_len(device->pdev, bar);
@@ -672,7 +666,7 @@ nv_device_resource_len(struct nouveau_device *device, unsigned int bar)
}
int
-nv_device_get_irq(struct nouveau_device *device, bool stall)
+nv_device_get_irq(struct nvkm_device *device, bool stall)
{
if (nv_device_is_pci(device)) {
return device->pdev->irq;
@@ -682,22 +676,22 @@ nv_device_get_irq(struct nouveau_device *device, bool stall)
}
}
-static struct nouveau_oclass
-nouveau_device_oclass = {
+static struct nvkm_oclass
+nvkm_device_oclass = {
.handle = NV_ENGINE(DEVICE, 0x00),
- .ofuncs = &(struct nouveau_ofuncs) {
- .dtor = nouveau_device_dtor,
- .init = nouveau_device_init,
- .fini = nouveau_device_fini,
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .dtor = nvkm_device_dtor,
+ .init = nvkm_device_init,
+ .fini = nvkm_device_fini,
},
};
int
-nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name,
- const char *sname, const char *cfg, const char *dbg,
- int length, void **pobject)
+nvkm_device_create_(void *dev, enum nv_bus_type type, u64 name,
+ const char *sname, const char *cfg, const char *dbg,
+ int length, void **pobject)
{
- struct nouveau_device *device;
+ struct nvkm_device *device;
int ret = -EEXIST;
mutex_lock(&nv_devices_mutex);
@@ -706,17 +700,17 @@ nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name,
goto done;
}
- ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true,
- "DEVICE", "device", length, pobject);
+ ret = nvkm_engine_create_(NULL, NULL, &nvkm_device_oclass, true,
+ "DEVICE", "device", length, pobject);
device = *pobject;
if (ret)
goto done;
switch (type) {
- case NOUVEAU_BUS_PCI:
+ case NVKM_BUS_PCI:
device->pdev = dev;
break;
- case NOUVEAU_BUS_PLATFORM:
+ case NVKM_BUS_PLATFORM:
device->platformdev = dev;
break;
}
@@ -725,12 +719,11 @@ nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name,
device->dbgopt = dbg;
device->name = sname;
- nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE");
- nv_engine(device)->sclass = nouveau_device_sclass;
+ nv_subdev(device)->debug = nvkm_dbgopt(device->dbgopt, "DEVICE");
+ nv_engine(device)->sclass = nvkm_device_sclass;
list_add(&device->head, &nv_devices);
- ret = nvkm_event_init(&nouveau_device_event_func, 1, 1,
- &device->event);
+ ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event);
done:
mutex_unlock(&nv_devices_mutex);
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
index 7a7632e65c77..0b794b13cec3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
@@ -21,25 +21,22 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include <core/client.h>
-#include <core/object.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <nvif/ioctl.h>
-
-#include <subdev/clk.h>
-
#include "priv.h"
+#include <core/client.h>
+#include <subdev/clk.h>
+
+#include <nvif/class.h>
+#include <nvif/ioctl.h>
+#include <nvif/unpack.h>
+
static int
-nouveau_control_mthd_pstate_info(struct nouveau_object *object,
- void *data, u32 size)
+nvkm_control_mthd_pstate_info(struct nvkm_object *object, void *data, u32 size)
{
union {
struct nvif_control_pstate_info_v0 v0;
} *args = data;
- struct nouveau_clk *clk = nouveau_clk(object);
+ struct nvkm_clk *clk = nvkm_clk(object);
int ret;
nv_ioctl(object, "control pstate info size %d\n", size);
@@ -67,16 +64,15 @@ nouveau_control_mthd_pstate_info(struct nouveau_object *object,
}
static int
-nouveau_control_mthd_pstate_attr(struct nouveau_object *object,
- void *data, u32 size)
+nvkm_control_mthd_pstate_attr(struct nvkm_object *object, void *data, u32 size)
{
union {
struct nvif_control_pstate_attr_v0 v0;
} *args = data;
- struct nouveau_clk *clk = nouveau_clk(object);
- struct nouveau_domain *domain;
- struct nouveau_pstate *pstate;
- struct nouveau_cstate *cstate;
+ struct nvkm_clk *clk = nvkm_clk(object);
+ struct nvkm_domain *domain;
+ struct nvkm_pstate *pstate;
+ struct nvkm_cstate *cstate;
int i = 0, j = -1;
u32 lo, hi;
int ret;
@@ -141,13 +137,12 @@ nouveau_control_mthd_pstate_attr(struct nouveau_object *object,
}
static int
-nouveau_control_mthd_pstate_user(struct nouveau_object *object,
- void *data, u32 size)
+nvkm_control_mthd_pstate_user(struct nvkm_object *object, void *data, u32 size)
{
union {
struct nvif_control_pstate_user_v0 v0;
} *args = data;
- struct nouveau_clk *clk = nouveau_clk(object);
+ struct nvkm_clk *clk = nvkm_clk(object);
int ret;
nv_ioctl(object, "control pstate user size %d\n", size);
@@ -161,45 +156,44 @@ nouveau_control_mthd_pstate_user(struct nouveau_object *object,
return ret;
if (args->v0.pwrsrc >= 0) {
- ret |= nouveau_clk_ustate(clk, args->v0.ustate, args->v0.pwrsrc);
+ ret |= nvkm_clk_ustate(clk, args->v0.ustate, args->v0.pwrsrc);
} else {
- ret |= nouveau_clk_ustate(clk, args->v0.ustate, 0);
- ret |= nouveau_clk_ustate(clk, args->v0.ustate, 1);
+ ret |= nvkm_clk_ustate(clk, args->v0.ustate, 0);
+ ret |= nvkm_clk_ustate(clk, args->v0.ustate, 1);
}
return ret;
}
static int
-nouveau_control_mthd(struct nouveau_object *object, u32 mthd,
- void *data, u32 size)
+nvkm_control_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
switch (mthd) {
case NVIF_CONTROL_PSTATE_INFO:
- return nouveau_control_mthd_pstate_info(object, data, size);
+ return nvkm_control_mthd_pstate_info(object, data, size);
case NVIF_CONTROL_PSTATE_ATTR:
- return nouveau_control_mthd_pstate_attr(object, data, size);
+ return nvkm_control_mthd_pstate_attr(object, data, size);
case NVIF_CONTROL_PSTATE_USER:
- return nouveau_control_mthd_pstate_user(object, data, size);
+ return nvkm_control_mthd_pstate_user(object, data, size);
default:
break;
}
return -EINVAL;
}
-static struct nouveau_ofuncs
-nouveau_control_ofuncs = {
- .ctor = _nouveau_object_ctor,
- .dtor = nouveau_object_destroy,
- .init = nouveau_object_init,
- .fini = nouveau_object_fini,
- .mthd = nouveau_control_mthd,
+static struct nvkm_ofuncs
+nvkm_control_ofuncs = {
+ .ctor = _nvkm_object_ctor,
+ .dtor = nvkm_object_destroy,
+ .init = nvkm_object_init,
+ .fini = nvkm_object_fini,
+ .mthd = nvkm_control_mthd,
};
-struct nouveau_oclass
-nouveau_control_oclass[] = {
+struct nvkm_oclass
+nvkm_control_oclass[] = {
{ .handle = NVIF_IOCTL_NEW_V0_CONTROL,
- .ofuncs = &nouveau_control_ofuncs
+ .ofuncs = &nvkm_control_ofuncs
},
{}
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
index 887ec05d0c3c..82b38d7e9730 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
@@ -21,6 +21,7 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
@@ -42,7 +43,6 @@
#include <subdev/pmu.h>
#include <subdev/volt.h>
-#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
@@ -56,12 +56,12 @@
#include <engine/pm.h>
int
-nvc0_identify(struct nouveau_device *device)
+gf100_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0xc0:
device->cname = "GF100";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -94,7 +94,7 @@ nvc0_identify(struct nouveau_device *device)
break;
case 0xc4:
device->cname = "GF104";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -127,7 +127,7 @@ nvc0_identify(struct nouveau_device *device)
break;
case 0xc3:
device->cname = "GF106";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -159,7 +159,7 @@ nvc0_identify(struct nouveau_device *device)
break;
case 0xce:
device->cname = "GF114";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -192,7 +192,7 @@ nvc0_identify(struct nouveau_device *device)
break;
case 0xcf:
device->cname = "GF116";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -224,7 +224,7 @@ nvc0_identify(struct nouveau_device *device)
break;
case 0xc1:
device->cname = "GF108";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -256,7 +256,7 @@ nvc0_identify(struct nouveau_device *device)
break;
case 0xc8:
device->cname = "GF110";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -289,7 +289,7 @@ nvc0_identify(struct nouveau_device *device)
break;
case 0xd9:
device->cname = "GF119";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -321,7 +321,7 @@ nvc0_identify(struct nouveau_device *device)
break;
case 0xd7:
device->cname = "GF117";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -355,4 +355,4 @@ nvc0_identify(struct nouveau_device *device)
}
return 0;
- }
+}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
index faaf87b462a6..bf5893458a47 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
@@ -21,6 +21,7 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
@@ -42,7 +43,6 @@
#include <subdev/pmu.h>
#include <subdev/volt.h>
-#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
@@ -56,12 +56,12 @@
#include <engine/pm.h>
int
-nve0_identify(struct nouveau_device *device)
+gk104_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0xe4:
device->cname = "GK104";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -95,7 +95,7 @@ nve0_identify(struct nouveau_device *device)
break;
case 0xe7:
device->cname = "GK107";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -129,7 +129,7 @@ nve0_identify(struct nouveau_device *device)
break;
case 0xe6:
device->cname = "GK106";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -185,7 +185,7 @@ nve0_identify(struct nouveau_device *device)
break;
case 0xf0:
device->cname = "GK110";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -219,7 +219,7 @@ nve0_identify(struct nouveau_device *device)
break;
case 0xf1:
device->cname = "GK110B";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -253,7 +253,7 @@ nve0_identify(struct nouveau_device *device)
break;
case 0x106:
device->cname = "GK208B";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -286,7 +286,7 @@ nve0_identify(struct nouveau_device *device)
break;
case 0x108:
device->cname = "GK208";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index ffa2da42f397..539561ed3281 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -21,6 +21,7 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
@@ -42,7 +43,6 @@
#include <subdev/pmu.h>
#include <subdev/volt.h>
-#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
@@ -56,12 +56,12 @@
#include <engine/pm.h>
int
-gm100_identify(struct nouveau_device *device)
+gm100_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x117:
device->cname = "GM107";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
@@ -101,7 +101,7 @@ gm100_identify(struct nouveau_device *device)
break;
case 0x124:
device->cname = "GM204";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index 1d409af560da..5a2ae043b478 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -21,6 +21,7 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
@@ -33,7 +34,6 @@
#include <subdev/instmem.h>
#include <subdev/mmu.h>
-#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
@@ -41,12 +41,12 @@
#include <engine/disp.h>
int
-nv04_identify(struct nouveau_device *device)
+nv04_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x04:
device->cname = "NV04";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass;
@@ -64,7 +64,7 @@ nv04_identify(struct nouveau_device *device)
break;
case 0x05:
device->cname = "NV05";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index 66d8c338ae98..94a1ca45e94a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -21,6 +21,7 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
@@ -34,7 +35,6 @@
#include <subdev/instmem.h>
#include <subdev/mmu.h>
-#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
@@ -42,12 +42,12 @@
#include <engine/disp.h>
int
-nv10_identify(struct nouveau_device *device)
+nv10_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x10:
device->cname = "NV10";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -64,7 +64,7 @@ nv10_identify(struct nouveau_device *device)
break;
case 0x15:
device->cname = "NV15";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -83,7 +83,7 @@ nv10_identify(struct nouveau_device *device)
break;
case 0x16:
device->cname = "NV16";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -102,7 +102,7 @@ nv10_identify(struct nouveau_device *device)
break;
case 0x1a:
device->cname = "nForce";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -121,7 +121,7 @@ nv10_identify(struct nouveau_device *device)
break;
case 0x11:
device->cname = "NV11";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -140,7 +140,7 @@ nv10_identify(struct nouveau_device *device)
break;
case 0x17:
device->cname = "NV17";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -159,7 +159,7 @@ nv10_identify(struct nouveau_device *device)
break;
case 0x1f:
device->cname = "nForce2";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -178,7 +178,7 @@ nv10_identify(struct nouveau_device *device)
break;
case 0x18:
device->cname = "NV18";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index 59cefdd46897..d5ec8937df68 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -21,6 +21,7 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
@@ -35,7 +36,6 @@
#include <subdev/instmem.h>
#include <subdev/mmu.h>
-#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
@@ -43,12 +43,12 @@
#include <engine/disp.h>
int
-nv20_identify(struct nouveau_device *device)
+nv20_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x20:
device->cname = "NV20";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -67,7 +67,7 @@ nv20_identify(struct nouveau_device *device)
break;
case 0x25:
device->cname = "NV25";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -86,7 +86,7 @@ nv20_identify(struct nouveau_device *device)
break;
case 0x28:
device->cname = "NV28";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -105,7 +105,7 @@ nv20_identify(struct nouveau_device *device)
break;
case 0x2a:
device->cname = "NV2A";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index dfb610f837b0..dda09621e898 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -21,6 +21,7 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
@@ -34,7 +35,6 @@
#include <subdev/instmem.h>
#include <subdev/mmu.h>
-#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
@@ -43,12 +43,12 @@
#include <engine/disp.h>
int
-nv30_identify(struct nouveau_device *device)
+nv30_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x30:
device->cname = "NV30";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -67,7 +67,7 @@ nv30_identify(struct nouveau_device *device)
break;
case 0x35:
device->cname = "NV35";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -86,7 +86,7 @@ nv30_identify(struct nouveau_device *device)
break;
case 0x31:
device->cname = "NV31";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -106,7 +106,7 @@ nv30_identify(struct nouveau_device *device)
break;
case 0x36:
device->cname = "NV36";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -126,7 +126,7 @@ nv30_identify(struct nouveau_device *device)
break;
case 0x34:
device->cname = "NV34";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index 7bdb7d6729b7..c6301361d14f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -21,6 +21,7 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
@@ -37,7 +38,6 @@
#include <subdev/mmu.h>
#include <subdev/volt.h>
-#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
@@ -47,12 +47,12 @@
#include <engine/pm.h>
int
-nv40_identify(struct nouveau_device *device)
+nv40_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x40:
device->cname = "NV40";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -75,7 +75,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x41:
device->cname = "NV41";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -98,7 +98,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x42:
device->cname = "NV42";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -121,7 +121,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x43:
device->cname = "NV43";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -144,7 +144,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x45:
device->cname = "NV45";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -167,7 +167,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x47:
device->cname = "G70";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -190,7 +190,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x49:
device->cname = "G71";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -213,7 +213,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x4b:
device->cname = "G73";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -236,7 +236,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x44:
device->cname = "NV44";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -259,7 +259,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x46:
device->cname = "G72";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -282,7 +282,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x4a:
device->cname = "NV44A";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -305,7 +305,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x4c:
device->cname = "C61";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -328,7 +328,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x4e:
device->cname = "C51";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -351,7 +351,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x63:
device->cname = "C73";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -374,7 +374,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x67:
device->cname = "C67";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@@ -397,7 +397,7 @@ nv40_identify(struct nouveau_device *device)
break;
case 0x68:
device->cname = "C68";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 36944babbb53..249b84454612 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -21,6 +21,7 @@
*
* Authors: Ben Skeggs
*/
+#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
@@ -40,7 +41,6 @@
#include <subdev/pmu.h>
#include <subdev/volt.h>
-#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
@@ -58,12 +58,12 @@
#include <engine/pm.h>
int
-nv50_identify(struct nouveau_device *device)
+nv50_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x50:
device->cname = "G80";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@@ -89,7 +89,7 @@ nv50_identify(struct nouveau_device *device)
break;
case 0x84:
device->cname = "G84";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@@ -118,7 +118,7 @@ nv50_identify(struct nouveau_device *device)
break;
case 0x86:
device->cname = "G86";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@@ -147,7 +147,7 @@ nv50_identify(struct nouveau_device *device)
break;
case 0x92:
device->cname = "G92";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@@ -176,7 +176,7 @@ nv50_identify(struct nouveau_device *device)
break;
case 0x94:
device->cname = "G94";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@@ -205,7 +205,7 @@ nv50_identify(struct nouveau_device *device)
break;
case 0x96:
device->cname = "G96";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@@ -234,7 +234,7 @@ nv50_identify(struct nouveau_device *device)
break;
case 0x98:
device->cname = "G98";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@@ -263,7 +263,7 @@ nv50_identify(struct nouveau_device *device)
break;
case 0xa0:
device->cname = "G200";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@@ -292,7 +292,7 @@ nv50_identify(struct nouveau_device *device)
break;
case 0xaa:
device->cname = "MCP77/MCP78";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@@ -321,7 +321,7 @@ nv50_identify(struct nouveau_device *device)
break;
case 0xac:
device->cname = "MCP79/MCP7A";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@@ -350,7 +350,7 @@ nv50_identify(struct nouveau_device *device)
break;
case 0xa3:
device->cname = "GT215";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@@ -381,7 +381,7 @@ nv50_identify(struct nouveau_device *device)
break;
case 0xa5:
device->cname = "GT216";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@@ -411,7 +411,7 @@ nv50_identify(struct nouveau_device *device)
break;
case 0xa8:
device->cname = "GT218";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@@ -441,7 +441,7 @@ nv50_identify(struct nouveau_device *device)
break;
case 0xaf:
device->cname = "MCP89";
- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+ device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
index 035fd5b9cfc3..8d3590e7bd87 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
@@ -1,8 +1,16 @@
#ifndef __NVKM_DEVICE_PRIV_H__
#define __NVKM_DEVICE_PRIV_H__
+#include <core/device.h>
-#include <engine/device.h>
-
-extern struct nouveau_oclass nouveau_control_oclass[];
+extern struct nvkm_oclass nvkm_control_oclass[];
+int nv04_identify(struct nvkm_device *);
+int nv10_identify(struct nvkm_device *);
+int nv20_identify(struct nvkm_device *);
+int nv30_identify(struct nvkm_device *);
+int nv40_identify(struct nvkm_device *);
+int nv50_identify(struct nvkm_device *);
+int gf100_identify(struct nvkm_device *);
+int gk104_identify(struct nvkm_device *);
+int gm100_identify(struct nvkm_device *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
index 131619bda22f..d852bd6de571 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
@@ -1,7 +1,8 @@
#ifndef __NV40_GR_H__
#define __NV40_GR_H__
#include <engine/gr.h>
-#include <engine/device.h>
+
+#include <core/device.h>
struct nvkm_gpuobj;
/* returns 1 if device is one of the nv4x using the 0x4497 object class,
From be83cd4ef9a2a56bd35550bf96146b7b837daf02 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 14 Jan 2015 15:36:34 +1000
Subject: [PATCH 86/86] drm/nouveau: finalise nvkm namespace switch (no binary
change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
drivers/gpu/drm/nouveau/dispnv04/crtc.c | 6 +-
drivers/gpu/drm/nouveau/dispnv04/dac.c | 22 +-
drivers/gpu/drm/nouveau/dispnv04/dfp.c | 6 +-
drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +-
drivers/gpu/drm/nouveau/dispnv04/disp.h | 4 +-
drivers/gpu/drm/nouveau/dispnv04/hw.c | 24 +-
drivers/gpu/drm/nouveau/dispnv04/hw.h | 4 +-
drivers/gpu/drm/nouveau/dispnv04/tvnv04.c | 8 +-
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c | 4 +-
drivers/gpu/drm/nouveau/include/nvif/client.h | 2 +-
drivers/gpu/drm/nouveau/include/nvif/device.h | 24 +-
drivers/gpu/drm/nouveau/include/nvif/object.h | 2 +-
.../gpu/drm/nouveau/include/nvkm/core/os.h | 255 ------------------
.../gpu/drm/nouveau/include/nvkm/subdev/mxm.h | 43 ++-
drivers/gpu/drm/nouveau/nouveau_abi16.c | 16 +-
drivers/gpu/drm/nouveau/nouveau_abi16.h | 6 +-
drivers/gpu/drm/nouveau/nouveau_bios.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_bo.c | 92 +++----
drivers/gpu/drm/nouveau/nouveau_bo.h | 12 +-
drivers/gpu/drm/nouveau/nouveau_chan.c | 6 +-
drivers/gpu/drm/nouveau/nouveau_chan.h | 2 +-
drivers/gpu/drm/nouveau/nouveau_connector.c | 10 +-
drivers/gpu/drm/nouveau/nouveau_connector.h | 2 +-
drivers/gpu/drm/nouveau/nouveau_display.h | 2 +-
drivers/gpu/drm/nouveau/nouveau_dma.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_dp.c | 4 +-
drivers/gpu/drm/nouveau/nouveau_drm.c | 48 ++--
drivers/gpu/drm/nouveau/nouveau_drm.h | 4 +-
drivers/gpu/drm/nouveau/nouveau_encoder.h | 4 +-
drivers/gpu/drm/nouveau/nouveau_fence.h | 6 +-
drivers/gpu/drm/nouveau/nouveau_gem.c | 20 +-
drivers/gpu/drm/nouveau/nouveau_hwmon.c | 54 ++--
drivers/gpu/drm/nouveau/nouveau_nvif.c | 14 +-
drivers/gpu/drm/nouveau/nouveau_platform.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_platform.h | 2 +-
drivers/gpu/drm/nouveau/nouveau_sgdma.c | 10 +-
drivers/gpu/drm/nouveau/nouveau_ttm.c | 52 ++--
drivers/gpu/drm/nouveau/nv04_fence.c | 2 +-
drivers/gpu/drm/nouveau/nv50_display.c | 8 +-
drivers/gpu/drm/nouveau/nv84_fence.c | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/mxm/base.c | 55 ++--
.../gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c | 20 +-
.../gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h | 18 +-
.../gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c | 40 ++-
44 files changed, 329 insertions(+), 594 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
index f32eecbe3c95..542bb266a0ab 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
@@ -112,12 +112,12 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod
{
struct drm_device *dev = crtc->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_bios *bios = nvxx_bios(&drm->device);
- struct nouveau_clk *clk = nvxx_clk(&drm->device);
+ struct nvkm_bios *bios = nvxx_bios(&drm->device);
+ struct nvkm_clk *clk = nvxx_clk(&drm->device);
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
- struct nouveau_pll_vals *pv = ®p->pllvals;
+ struct nvkm_pll_vals *pv = ®p->pllvals;
struct nvbios_pll pll_lim;
if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,
diff --git a/drivers/gpu/drm/nouveau/dispnv04/dac.c b/drivers/gpu/drm/nouveau/dispnv04/dac.c
index 043e07b01fd0..d7b495a5f30c 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/dac.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/dac.c
@@ -66,7 +66,7 @@ int nv04_dac_output_offset(struct drm_encoder *encoder)
static int sample_load_twice(struct drm_device *dev, bool sense[2])
{
struct nvif_device *device = &nouveau_drm(dev)->device;
- struct nouveau_timer *ptimer = nvxx_timer(device);
+ struct nvkm_timer *ptimer = nvxx_timer(device);
int i;
for (i = 0; i < 2; i++) {
@@ -80,17 +80,17 @@ static int sample_load_twice(struct drm_device *dev, bool sense[2])
* use a 10ms timeout (guards against crtc being inactive, in
* which case blank state would never change)
*/
- if (!nouveau_timer_wait_eq(ptimer, 10000000,
- NV_PRMCIO_INP0__COLOR,
- 0x00000001, 0x00000000))
+ if (!nvkm_timer_wait_eq(ptimer, 10000000,
+ NV_PRMCIO_INP0__COLOR,
+ 0x00000001, 0x00000000))
return -EBUSY;
- if (!nouveau_timer_wait_eq(ptimer, 10000000,
- NV_PRMCIO_INP0__COLOR,
- 0x00000001, 0x00000001))
+ if (!nvkm_timer_wait_eq(ptimer, 10000000,
+ NV_PRMCIO_INP0__COLOR,
+ 0x00000001, 0x00000001))
return -EBUSY;
- if (!nouveau_timer_wait_eq(ptimer, 10000000,
- NV_PRMCIO_INP0__COLOR,
- 0x00000001, 0x00000000))
+ if (!nvkm_timer_wait_eq(ptimer, 10000000,
+ NV_PRMCIO_INP0__COLOR,
+ 0x00000001, 0x00000000))
return -EBUSY;
udelay(100);
@@ -232,7 +232,7 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
struct drm_device *dev = encoder->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &nouveau_drm(dev)->device;
- struct nouveau_gpio *gpio = nvxx_gpio(device);
+ struct nvkm_gpio *gpio = nvxx_gpio(device);
struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
diff --git a/drivers/gpu/drm/nouveau/dispnv04/dfp.c b/drivers/gpu/drm/nouveau/dispnv04/dfp.c
index a326f374e37c..f6ca343fd34a 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/dfp.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/dfp.c
@@ -623,9 +623,9 @@ static void nv04_tmds_slave_init(struct drm_encoder *encoder)
struct drm_device *dev = encoder->dev;
struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
- struct nouveau_i2c_port *port = i2c->find(i2c, 2);
- struct nouveau_i2c_board_info info[] = {
+ struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
+ struct nvkm_i2c_port *port = i2c->find(i2c, 2);
+ struct nvkm_i2c_board_info info[] = {
{
{
.type = "sil164",
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c
index 3373a15eab5d..f96237ef2a6b 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c
@@ -35,7 +35,7 @@ int
nv04_display_create(struct drm_device *dev)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
+ struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
struct dcb_table *dcb = &drm->vbios.dcb;
struct drm_connector *connector, *ct;
struct drm_encoder *encoder;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h b/drivers/gpu/drm/nouveau/dispnv04/disp.h
index fe4901cfae27..c910c5d5c662 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/disp.h
+++ b/drivers/gpu/drm/nouveau/dispnv04/disp.h
@@ -36,7 +36,7 @@ struct nv04_crtc_reg {
/* PRAMDAC regs */
uint32_t nv10_cursync;
- struct nouveau_pll_vals pllvals;
+ struct nvkm_pll_vals pllvals;
uint32_t ramdac_gen_ctrl;
uint32_t ramdac_630;
uint32_t ramdac_634;
@@ -170,7 +170,7 @@ nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
struct dcb_output *outp, int crtc)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_bios *bios = nvxx_bios(&drm->device);
+ struct nvkm_bios *bios = nvxx_bios(&drm->device);
struct nvbios_init init = {
.subdev = nv_subdev(bios),
.bios = bios,
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
index a930c1e71148..42e07afc4c2b 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -130,7 +130,7 @@ NVBlankScreen(struct drm_device *dev, int head, bool blank)
static void
nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
- uint32_t pll2, struct nouveau_pll_vals *pllvals)
+ uint32_t pll2, struct nvkm_pll_vals *pllvals)
{
struct nouveau_drm *drm = nouveau_drm(dev);
@@ -162,11 +162,11 @@ nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
int
nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
- struct nouveau_pll_vals *pllvals)
+ struct nvkm_pll_vals *pllvals)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
- struct nouveau_bios *bios = nvxx_bios(device);
+ struct nvkm_bios *bios = nvxx_bios(device);
uint32_t reg1, pll1, pll2 = 0;
struct nvbios_pll pll_lim;
int ret;
@@ -202,7 +202,7 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
}
int
-nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv)
+nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv)
{
/* Avoid divide by zero if called at an inappropriate time */
if (!pv->M1 || !pv->M2)
@@ -214,7 +214,7 @@ nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv)
int
nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
{
- struct nouveau_pll_vals pllvals;
+ struct nvkm_pll_vals pllvals;
int ret;
if (plltype == PLL_MEMORY &&
@@ -253,10 +253,10 @@ nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
- struct nouveau_clk *clk = nvxx_clk(device);
- struct nouveau_bios *bios = nvxx_bios(device);
+ struct nvkm_clk *clk = nvxx_clk(device);
+ struct nvkm_bios *bios = nvxx_bios(device);
struct nvbios_pll pll_lim;
- struct nouveau_pll_vals pv;
+ struct nvkm_pll_vals pv;
enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0;
if (nvbios_pll_parse(bios, pll, &pll_lim))
@@ -463,7 +463,7 @@ nv_load_state_ramdac(struct drm_device *dev, int head,
struct nv04_mode_state *state)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_clk *clk = nvxx_clk(&drm->device);
+ struct nvkm_clk *clk = nvxx_clk(&drm->device);
struct nv04_crtc_reg *regp = &state->crtc_reg[head];
uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
int i;
@@ -661,7 +661,7 @@ nv_load_state_ext(struct drm_device *dev, int head,
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
- struct nouveau_timer *ptimer = nvxx_timer(device);
+ struct nvkm_timer *ptimer = nvxx_timer(device);
struct nv04_crtc_reg *regp = &state->crtc_reg[head];
uint32_t reg900;
int i;
@@ -741,8 +741,8 @@ nv_load_state_ext(struct drm_device *dev, int head,
if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) {
/* Not waiting for vertical retrace before modifying
CRE_53/CRE_54 causes lockups. */
- nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
- nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
+ nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
+ nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
}
wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.h b/drivers/gpu/drm/nouveau/dispnv04/hw.h
index 7f53c571f31f..6c796178bf0c 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.h
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.h
@@ -42,8 +42,8 @@ uint8_t NVReadVgaGr(struct drm_device *, int head, uint8_t index);
void NVSetOwner(struct drm_device *, int owner);
void NVBlankScreen(struct drm_device *, int head, bool blank);
int nouveau_hw_get_pllvals(struct drm_device *, enum nvbios_pll_type plltype,
- struct nouveau_pll_vals *pllvals);
-int nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pllvals);
+ struct nvkm_pll_vals *pllvals);
+int nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pllvals);
int nouveau_hw_get_clock(struct drm_device *, enum nvbios_pll_type plltype);
void nouveau_hw_save_vga_fonts(struct drm_device *, bool save);
void nouveau_hw_save_state(struct drm_device *, int head,
diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c
index 38a8196d1e92..d9664b37def1 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c
@@ -35,7 +35,7 @@
#include <drm/i2c/ch7006.h>
-static struct nouveau_i2c_board_info nv04_tv_encoder_info[] = {
+static struct nvkm_i2c_board_info nv04_tv_encoder_info[] = {
{
{
I2C_BOARD_INFO("ch7006", 0x75),
@@ -54,7 +54,7 @@ static struct nouveau_i2c_board_info nv04_tv_encoder_info[] = {
int nv04_tv_identify(struct drm_device *dev, int i2c_index)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
+ struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
return i2c->identify(i2c, i2c_index, "TV encoder",
nv04_tv_encoder_info, NULL, NULL);
@@ -204,8 +204,8 @@ nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry)
struct drm_encoder *encoder;
struct drm_device *dev = connector->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
- struct nouveau_i2c_port *port = i2c->find(i2c, entry->i2c_index);
+ struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
+ struct nvkm_i2c_port *port = i2c->find(i2c, entry->i2c_index);
int type, ret;
/* Ensure that we can talk to this encoder */
diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
index b86e36b4077d..731d74efc1e5 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
@@ -46,7 +46,7 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_gpio *gpio = nvxx_gpio(&drm->device);
+ struct nvkm_gpio *gpio = nvxx_gpio(&drm->device);
uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
@@ -370,7 +370,7 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
{
struct drm_device *dev = encoder->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_gpio *gpio = nvxx_gpio(&drm->device);
+ struct nvkm_gpio *gpio = nvxx_gpio(&drm->device);
struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
diff --git a/drivers/gpu/drm/nouveau/include/nvif/client.h b/drivers/gpu/drm/nouveau/include/nvif/client.h
index 97694738abcf..eca648ef0f7a 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/client.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/client.h
@@ -33,7 +33,7 @@ int nvif_client_resume(struct nvif_client *);
#include <core/client.h>
#define nvxx_client(a) ({ \
struct nvif_client *_client = nvif_client(nvif_object(a)); \
- nouveau_client(_client->base.priv); \
+ nvkm_client(_client->base.priv); \
})
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h
index 1fafcac299d3..88553a741ab7 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/device.h
@@ -38,24 +38,24 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
#include <subdev/therm.h>
#define nvxx_device(a) nv_device(nvxx_object((a)))
-#define nvxx_bios(a) nouveau_bios(nvxx_device(a))
-#define nvxx_fb(a) nouveau_fb(nvxx_device(a))
-#define nvxx_mmu(a) nouveau_mmu(nvxx_device(a))
-#define nvxx_bar(a) nouveau_bar(nvxx_device(a))
-#define nvxx_gpio(a) nouveau_gpio(nvxx_device(a))
-#define nvxx_clk(a) nouveau_clk(nvxx_device(a))
-#define nvxx_i2c(a) nouveau_i2c(nvxx_device(a))
-#define nvxx_timer(a) nouveau_timer(nvxx_device(a))
+#define nvxx_bios(a) nvkm_bios(nvxx_device(a))
+#define nvxx_fb(a) nvkm_fb(nvxx_device(a))
+#define nvxx_mmu(a) nvkm_mmu(nvxx_device(a))
+#define nvxx_bar(a) nvkm_bar(nvxx_device(a))
+#define nvxx_gpio(a) nvkm_gpio(nvxx_device(a))
+#define nvxx_clk(a) nvkm_clk(nvxx_device(a))
+#define nvxx_i2c(a) nvkm_i2c(nvxx_device(a))
+#define nvxx_timer(a) nvkm_timer(nvxx_device(a))
#define nvxx_wait(a,b,c,d) nv_wait(nvxx_timer(a), (b), (c), (d))
#define nvxx_wait_cb(a,b,c) nv_wait_cb(nvxx_timer(a), (b), (c))
-#define nvxx_therm(a) nouveau_therm(nvxx_device(a))
+#define nvxx_therm(a) nvkm_therm(nvxx_device(a))
#include <core/device.h>
#include <engine/fifo.h>
#include <engine/gr.h>
#include <engine/sw.h>
-#define nvxx_fifo(a) nouveau_fifo(nvxx_device(a))
-#define nvxx_fifo_chan(a) ((struct nouveau_fifo_chan *)nvxx_object(a))
-#define nvxx_gr(a) ((struct nouveau_gr *)nouveau_engine(nvxx_object(a), NVDEV_ENGINE_GR))
+#define nvxx_fifo(a) nvkm_fifo(nvxx_device(a))
+#define nvxx_fifo_chan(a) ((struct nvkm_fifo_chan *)nvxx_object(a))
+#define nvxx_gr(a) ((struct nvkm_gr *)nvkm_engine(nvxx_object(a), NVDEV_ENGINE_GR))
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/object.h b/drivers/gpu/drm/nouveau/include/nvif/object.h
index d47f5693cb5b..04c874707b96 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/object.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/object.h
@@ -70,6 +70,6 @@ void nvif_object_unmap(struct nvif_object *);
/*XXX*/
#include <core/object.h>
-#define nvxx_object(a) ((struct nouveau_object *)nvif_object(a)->priv)
+#define nvxx_object(a) ((struct nvkm_object *)nvif_object(a)->priv)
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 537db3a512c8..cd57e238ddd3 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -1,259 +1,4 @@
#ifndef __NVKM_OS_H__
#define __NVKM_OS_H__
#include <nvif/os.h>
-
-#define nouveau_client nvkm_client
-#define nouveau_client_name nvkm_client_name
-#define nouveau_client_create nvkm_client_create
-#define nouveau_client_init nvkm_client_init
-#define nouveau_client_fini nvkm_client_fini
-#define nouveau_engctx nvkm_engctx
-#define nouveau_engctx_create nvkm_engctx_create
-#define nouveau_engctx_create_ nvkm_engctx_create_
-#define nouveau_engctx_destroy nvkm_engctx_destroy
-#define nouveau_engctx_init nvkm_engctx_init
-#define nouveau_engctx_fini nvkm_engctx_fini
-#define _nouveau_engctx_ctor _nvkm_engctx_ctor
-#define _nouveau_engctx_dtor _nvkm_engctx_dtor
-#define _nouveau_engctx_init _nvkm_engctx_init
-#define _nouveau_engctx_fini _nvkm_engctx_fini
-#define _nouveau_engctx_rd32 _nvkm_engctx_rd32
-#define _nouveau_engctx_wr32 _nvkm_engctx_wr32
-#define nouveau_engctx_get nvkm_engctx_get
-#define nouveau_engctx_put nvkm_engctx_put
-#define nouveau_engine nvkm_engine
-#define nouveau_engine_create nvkm_engine_create
-#define nouveau_engine_create_ nvkm_engine_create_
-#define nouveau_engine_destroy nvkm_engine_destroy
-#define nouveau_engine_init nvkm_engine_init
-#define nouveau_engine_fini nvkm_engine_fini
-#define _nouveau_engine_ctor _nvkm_engine_ctor
-#define _nouveau_engine_dtor _nvkm_engine_dtor
-#define _nouveau_engine_init _nvkm_engine_init
-#define _nouveau_engine_fini _nvkm_engine_fini
-#define nouveau_enum nvkm_enum
-#define nouveau_gpuobj nvkm_gpuobj
-#define nouveau_gpuobj_create nvkm_gpuobj_create
-#define nouveau_gpuobj_destroy nvkm_gpuobj_destroy
-#define _nouveau_gpuobj_ctor _nvkm_gpuobj_ctor
-#define _nouveau_gpuobj_dtor _nvkm_gpuobj_dtor
-#define _nouveau_gpuobj_init _nvkm_gpuobj_init
-#define _nouveau_gpuobj_fini _nvkm_gpuobj_fini
-#define _nouveau_gpuobj_rd32 _nvkm_gpuobj_rd32
-#define _nouveau_gpuobj_wr32 _nvkm_gpuobj_wr32
-#define nouveau_gpuobj_new nvkm_gpuobj_new
-#define nouveau_gpuobj_dup nvkm_gpuobj_dup
-#define nouveau_gpuobj_ref nvkm_gpuobj_ref
-#define nouveau_gpuobj_map nvkm_gpuobj_map
-#define nouveau_gpuobj_map_vm nvkm_gpuobj_map_vm
-#define nouveau_gpuobj_unmap nvkm_gpuobj_unmap
-#define nouveau_handle nvkm_handle
-#define nouveau_handle_ref nvkm_handle_ref
-#define nouveau_handle_put nvkm_handle_put
-#define nouveau_handle_get_class nvkm_handle_get_class
-#define nouveau_handle_get_vinst nvkm_handle_get_vinst
-#define nouveau_handle_get_cinst nvkm_handle_get_cinst
-#define nouveau_mm nvkm_mm
-#define nouveau_mm_node nvkm_mm_node
-#define nouveau_mm_init nvkm_mm_init
-#define nouveau_mm_fini nvkm_mm_fini
-#define nouveau_mm_head nvkm_mm_head
-#define nouveau_mm_tail nvkm_mm_tail
-#define nouveau_mm_free nvkm_mm_free
-#define nouveau_mm_initialised nvkm_mm_initialised
-#define nouveau_namedb nvkm_namedb
-#define nouveau_namedb_create nvkm_namedb_create
-#define nouveau_namedb_create_ nvkm_namedb_create_
-#define nouveau_namedb_destroy nvkm_namedb_destroy
-#define nouveau_namedb_init nvkm_namedb_init
-#define nouveau_namedb_fini nvkm_namedb_fini
-#define _nouveau_namedb_ctor _nvkm_namedb_ctor
-#define _nouveau_namedb_dtor _nvkm_namedb_dtor
-#define _nouveau_namedb_init _nvkm_namedb_init
-#define _nouveau_namedb_fini _nvkm_namedb_fini
-#define nouveau_namedb_ref nvkm_namedb_ref
-#define nouveau_namedb_put nvkm_namedb_put
-#define nouveau_namedb_get nvkm_namedb_get
-#define nouveau_namedb_get_class nvkm_namedb_get_class
-#define nouveau_namedb_get_vinst nvkm_namedb_get_vinst
-#define nouveau_namedb_get_cinst nvkm_namedb_get_cinst
-#define nouveau_object_debug nvkm_object_debug
-#define nouveau_object nvkm_object
-#define nouveau_object_create nvkm_object_create
-#define nouveau_object_create_ nvkm_object_create_
-#define nouveau_object_destroy nvkm_object_destroy
-#define nouveau_object_init nvkm_object_init
-#define nouveau_object_fini nvkm_object_fini
-#define _nouveau_object_ctor _nvkm_object_ctor
-#define nouveau_object_ctor nvkm_object_ctor
-#define nouveau_object_ref nvkm_object_ref
-#define nouveau_object_ofuncs nvkm_object_ofuncs
-#define nouveau_object_inc nvkm_object_inc
-#define nouveau_object_dec nvkm_object_dec
-#define nouveau_ofuncs nvkm_ofuncs
-#define nouveau_oclass nvkm_oclass
-#define nouveau_omthds nvkm_omthds
-#define nouveau_parent nvkm_parent
-#define nouveau_parent_create nvkm_parent_create
-#define nouveau_parent_create_ nvkm_parent_create_
-#define nouveau_parent_destroy nvkm_parent_destroy
-#define nouveau_parent_init nvkm_parent_init
-#define nouveau_parent_fini nvkm_parent_fini
-#define _nouveau_parent_ctor _nvkm_parent_ctor
-#define _nouveau_parent_dtor _nvkm_parent_dtor
-#define _nouveau_parent_init _nvkm_parent_init
-#define _nouveau_parent_fini _nvkm_parent_fini
-#define nouveau_printk nvkm_printk
-#define nouveau_ramht nvkm_ramht
-#define nouveau_ramht_new nvkm_ramht_new
-#define nouveau_ramht_ref nvkm_ramht_ref
-#define nouveau_ramht_insert nvkm_ramht_insert
-#define nouveau_ramht_remove nvkm_ramht_remove
-#define nouveau_subdev nvkm_subdev
-#define nouveau_subdev_create nvkm_subdev_create
-#define nouveau_subdev_create_ nvkm_subdev_create_
-#define nouveau_subdev_destroy nvkm_subdev_destroy
-#define nouveau_subdev_init nvkm_subdev_init
-#define nouveau_subdev_fini nvkm_subdev_fini
-#define _nouveau_subdev_ctor _nvkm_subdev_ctor
-#define _nouveau_subdev_dtor _nvkm_subdev_dtor
-#define _nouveau_subdev_init _nvkm_subdev_init
-#define _nouveau_subdev_fini _nvkm_subdev_fini
-#define nouveau_subdev_reset nvkm_subdev_reset
-#define nouveau_bitfield nvkm_bitfield
-#define nouveau_bitfield_print nvkm_bitfield_print
-#define nouveau_enum nvkm_enum
-#define nouveau_enum_find nvkm_enum_find
-#define nouveau_enum_print nvkm_enum_print
-#define nouveau_stropt nvkm_stropt
-#define nouveau_boolopt nvkm_boolopt
-#define nouveau_dbgopt nvkm_dbgopt
-#define nouveau_device nvkm_device
-#define nouveau_device_find nvkm_device_find
-#define nouveau_device_list nvkm_device_list
-#define nouveau_vma nvkm_vma
-#define nouveau_vm nvkm_vm
-#define nouveau_vm_get nvkm_vm_get
-#define nouveau_vm_put nvkm_vm_put
-#define nouveau_vm_map nvkm_vm_map
-#define nouveau_vm_unmap nvkm_vm_unmap
-#define nouveau_vm_new nvkm_vm_new
-#define nouveau_vm_ref nvkm_vm_ref
-#define nouveau_instmem nvkm_instmem
-#define nouveau_instobj nvkm_instobj
-#define nouveau_mem nvkm_mem
-#define nouveau_bar nvkm_bar
-#define nouveau_falcon nvkm_falcon
-#define nouveau_falcon_create nvkm_falcon_create
-#define nouveau_falcon_create_ nvkm_falcon_create_
-#define nouveau_falcon_destroy nvkm_falcon_destroy
-#define nouveau_falcon_init nvkm_falcon_init
-#define nouveau_falcon_fini nvkm_falcon_fini
-#define _nouveau_falcon_ctor _nvkm_falcon_ctor
-#define _nouveau_falcon_dtor _nvkm_falcon_dtor
-#define _nouveau_falcon_init _nvkm_falcon_init
-#define _nouveau_falcon_fini _nvkm_falcon_fini
-#define _nouveau_falcon_rd32 _nvkm_falcon_rd32
-#define _nouveau_falcon_wr32 _nvkm_falcon_wr32
-#define nouveau_falcon_context nvkm_falcon_context
-#define nouveau_falcon_context_create nvkm_falcon_context_create
-#define nouveau_falcon_context_create_ nvkm_falcon_context_create_
-#define nouveau_falcon_context_destroy nvkm_falcon_context_destroy
-#define nouveau_falcon_context_init nvkm_falcon_context_init
-#define nouveau_falcon_context_fini nvkm_falcon_context_fini
-#define _nouveau_falcon_context_ctor _nvkm_falcon_context_ctor
-#define _nouveau_falcon_context_dtor _nvkm_falcon_context_dtor
-#define _nouveau_falcon_context_init _nvkm_falcon_context_init
-#define _nouveau_falcon_context_fini _nvkm_falcon_context_fini
-#define _nouveau_falcon_context_rd32 _nvkm_falcon_context_rd32
-#define _nouveau_falcon_context_wr32 _nvkm_falcon_context_wr32
-#define nouveau_falcon_intr nvkm_falcon_intr
-#define nouveau_xtensa nvkm_xtensa
-#define nouveau_xtensa_create nvkm_xtensa_create
-#define nouveau_xtensa_create_ nvkm_xtensa_create_
-#define nouveau_xtensa_destroy nvkm_xtensa_destroy
-#define nouveau_xtensa_init nvkm_xtensa_init
-#define nouveau_xtensa_fini nvkm_xtensa_fini
-#define _nouveau_xtensa_ctor _nvkm_xtensa_ctor
-#define _nouveau_xtensa_dtor _nvkm_xtensa_dtor
-#define _nouveau_xtensa_init _nvkm_xtensa_init
-#define _nouveau_xtensa_fini _nvkm_xtensa_fini
-#define _nouveau_xtensa_rd32 _nvkm_xtensa_rd32
-#define _nouveau_xtensa_wr32 _nvkm_xtensa_wr32
-#define nouveau_xtensa_context nvkm_xtensa_context
-#define nouveau_xtensa_context_create nvkm_xtensa_context_create
-#define nouveau_xtensa_context_create_ nvkm_xtensa_context_create_
-#define nouveau_xtensa_context_destroy nvkm_xtensa_context_destroy
-#define nouveau_xtensa_context_init nvkm_xtensa_context_init
-#define nouveau_xtensa_context_fini nvkm_xtensa_context_fini
-#define _nouveau_xtensa_engctx_ctor _nvkm_xtensa_engctx_ctor
-#define _nouveau_xtensa_context_dtor _nvkm_xtensa_context_dtor
-#define _nouveau_xtensa_context_init _nvkm_xtensa_context_init
-#define _nouveau_xtensa_context_fini _nvkm_xtensa_context_fini
-#define _nouveau_xtensa_context_rd32 _nvkm_xtensa_context_rd32
-#define _nouveau_xtensa_context_wr32 _nvkm_xtensa_context_wr32
-#define nouveau_xtensa_intr nvkm_xtensa_intr
-#define nouveau_gpio nvkm_gpio
-#define nouveau_i2c nvkm_i2c
-#define nouveau_i2c_port nvkm_i2c_port
-#define nouveau_i2c_board_info nvkm_i2c_board_info
-#define nouveau_devinit nvkm_devinit
-#define nouveau_bios nvkm_bios
-#define nouveau_bios_oclass nvkm_bios_oclass
-#define nouveau_pll_vals nvkm_pll_vals
-#define nouveau_therm_trip_point nvkm_therm_trip_point
-#define nouveau_fb nvkm_fb
-#define nouveau_fifo nvkm_fifo
-#define nouveau_therm nvkm_therm
-#define nouveau_therm_cstate nvkm_therm_cstate
-#define nouveau_volt nvkm_volt
-#define nouveau_timer nvkm_timer
-#define nouveau_timer_wait_eq nvkm_timer_wait_eq
-#define nouveau_timer_alarm nvkm_timer_alarm
-#define nouveau_alarm nvkm_alarm
-#define nouveau_timer_alarm_cancel nvkm_timer_alarm_cancel
-#define nouveau_alarm_init nvkm_alarm_init
-#define nva3_pll_calc gt215_pll_calc
-#define nouveau_clk nvkm_clk
-#define nouveau_domain nvkm_domain
-#define nouveau_cstate nvkm_cstate
-#define nouveau_pstate nvkm_pstate
-#define nouveau_clk_astate nvkm_clk_astate
-#define nouveau_clk_ustate nvkm_clk_ustate
-#define nva3_clk_pre gt215_clk_pre
-#define nva3_clk_post gt215_clk_post
-#define nva3_clk_info gt215_clk_info
-#define nva3_pll_info gt215_pll_info
-#define nouveau_ibus nvkm_ibus
-#define nouveau_memx nvkm_memx
-#define nouveau_memx_block nvkm_memx_block
-#define nouveau_memx_unblock nvkm_memx_unblock
-#define nouveau_memx_train nvkm_memx_train
-#define nouveau_memx_train_result nvkm_memx_train_result
-#define nouveau_memx_wait_vblank nvkm_memx_wait_vblank
-#define nouveau_memx_rd32 nvkm_memx_rd32
-#define nouveau_memx_wr32 nvkm_memx_wr32
-#define nouveau_memx_wait nvkm_memx_wait
-#define nouveau_memx_init nvkm_memx_init
-#define nouveau_memx_fini nvkm_memx_fini
-#define nouveau_memx_nsec nvkm_memx_nsec
-#define nouveau_ltc nvkm_ltc
-#define nouveau_pmu nvkm_pmu
-#define nouveau_fb nvkm_fb
-#define nouveau_fb_tile nvkm_fb_tile
-#define nvc0_pte_storage_type_map gf100_pte_storage_type_map
-#define nouveau_fuse nvkm_fuse
-#define nouveau_mc nvkm_mc
-#define nouveau_mmu nvkm_mmu
-#define nouveau_dmaeng nvkm_dmaeng
-#define nouveau_dmaobj nvkm_dmaobj
-#define nouveau_disp nvkm_disp
-#define nouveau_fifo_chan nvkm_fifo_chan
-#define nouveau_fifo nvkm_fifo
-#define nouveau_gr nvkm_gr
-#define nouveau_sw nvkm_sw
-#define nouveau_sw_chan nvkm_sw_chan
-#define nouveau_device_create nvkm_device_create
-#define nouveau_device_create_ nvkm_device_create_
-
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h
index 94b8af23c33e..fba613477b1a 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h
@@ -1,37 +1,34 @@
-#ifndef __NOUVEAU_MXM_H__
-#define __NOUVEAU_MXM_H__
-
+#ifndef __NVKM_MXM_H__
+#define __NVKM_MXM_H__
#include <core/subdev.h>
-#include <core/device.h>
#define MXM_SANITISE_DCB 0x00000001
-struct nouveau_mxm {
- struct nouveau_subdev base;
+struct nvkm_mxm {
+ struct nvkm_subdev base;
u32 action;
u8 *mxms;
};
-static inline struct nouveau_mxm *
-nouveau_mxm(void *obj)
+static inline struct nvkm_mxm *
+nvkm_mxm(void *obj)
{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MXM);
+ return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MXM);
}
-#define nouveau_mxm_create(p,e,o,d) \
- nouveau_mxm_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_mxm_init(p) \
- nouveau_subdev_init(&(p)->base)
-#define nouveau_mxm_fini(p,s) \
- nouveau_subdev_fini(&(p)->base, (s))
-int nouveau_mxm_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, int, void **);
-void nouveau_mxm_destroy(struct nouveau_mxm *);
+#define nvkm_mxm_create(p,e,o,d) \
+ nvkm_mxm_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nvkm_mxm_init(p) \
+ nvkm_subdev_init(&(p)->base)
+#define nvkm_mxm_fini(p,s) \
+ nvkm_subdev_fini(&(p)->base, (s))
+int nvkm_mxm_create_(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, int, void **);
+void nvkm_mxm_destroy(struct nvkm_mxm *);
-#define _nouveau_mxm_dtor _nouveau_subdev_dtor
-#define _nouveau_mxm_init _nouveau_subdev_init
-#define _nouveau_mxm_fini _nouveau_subdev_fini
-
-extern struct nouveau_oclass nv50_mxm_oclass;
+#define _nvkm_mxm_dtor _nvkm_subdev_dtor
+#define _nvkm_mxm_init _nvkm_subdev_init
+#define _nvkm_mxm_fini _nvkm_subdev_fini
+extern struct nvkm_oclass nv50_mxm_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index 9322b515d305..d8b0891a141c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -100,7 +100,7 @@ static void
nouveau_abi16_ntfy_fini(struct nouveau_abi16_chan *chan,
struct nouveau_abi16_ntfy *ntfy)
{
- nouveau_mm_free(&chan->heap, &ntfy->node);
+ nvkm_mm_free(&chan->heap, &ntfy->node);
list_del(&ntfy->head);
kfree(ntfy);
}
@@ -128,7 +128,7 @@ nouveau_abi16_chan_fini(struct nouveau_abi16 *abi16,
}
if (chan->heap.block_size)
- nouveau_mm_fini(&chan->heap);
+ nvkm_mm_fini(&chan->heap);
/* destroy channel object, all children will be killed too */
if (chan->chan) {
@@ -164,8 +164,8 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
struct nouveau_cli *cli = nouveau_cli(file_priv);
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
- struct nouveau_timer *ptimer = nvxx_timer(device);
- struct nouveau_gr *gr = nvxx_gr(device);
+ struct nvkm_timer *ptimer = nvxx_timer(device);
+ struct nvkm_gr *gr = nvxx_gr(device);
struct drm_nouveau_getparam *getparam = data;
switch (getparam->param) {
@@ -324,7 +324,7 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS)
if (ret)
goto done;
- ret = nouveau_mm_init(&chan->heap, 0, PAGE_SIZE, 1);
+ ret = nvkm_mm_init(&chan->heap, 0, PAGE_SIZE, 1);
done:
if (ret)
nouveau_abi16_chan_fini(abi16, chan);
@@ -448,8 +448,8 @@ nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS)
list_add(&ntfy->head, &chan->notifiers);
ntfy->handle = info->handle;
- ret = nouveau_mm_head(&chan->heap, 0, 1, info->size, info->size, 1,
- &ntfy->node);
+ ret = nvkm_mm_head(&chan->heap, 0, 1, info->size, info->size, 1,
+ &ntfy->node);
if (ret)
goto done;
@@ -527,7 +527,7 @@ nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS)
/* cleanup extra state if this object was a notifier */
list_for_each_entry(ntfy, &chan->notifiers, head) {
if (ntfy->handle == fini->handle) {
- nouveau_mm_free(&chan->heap, &ntfy->node);
+ nvkm_mm_free(&chan->heap, &ntfy->node);
list_del(&ntfy->head);
break;
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.h b/drivers/gpu/drm/nouveau/nouveau_abi16.h
index 39844e6bfbff..86eb1caf4957 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.h
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.h
@@ -14,7 +14,7 @@ int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);
struct nouveau_abi16_ntfy {
struct list_head head;
- struct nouveau_mm_node *node;
+ struct nvkm_mm_node *node;
u32 handle;
};
@@ -23,8 +23,8 @@ struct nouveau_abi16_chan {
struct nouveau_channel *chan;
struct list_head notifiers;
struct nouveau_bo *ntfy;
- struct nouveau_vma ntfy_vma;
- struct nouveau_mm heap;
+ struct nvkm_vma ntfy_vma;
+ struct nvkm_mm heap;
};
struct nouveau_abi16 {
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 8058b68b0e3b..0190b69bbe25 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -2009,7 +2009,7 @@ uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
static bool NVInitVBIOS(struct drm_device *dev)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_bios *bios = nvxx_bios(&drm->device);
+ struct nvkm_bios *bios = nvxx_bios(&drm->device);
struct nvbios *legacy = &drm->vbios;
memset(legacy, 0, sizeof(struct nvbios));
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 902d93fd72cc..77326e344dad 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -48,9 +48,9 @@ nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
{
struct nouveau_drm *drm = nouveau_drm(dev);
int i = reg - drm->tile.reg;
- struct nouveau_fb *pfb = nvxx_fb(&drm->device);
- struct nouveau_fb_tile *tile = &pfb->tile.region[i];
- struct nouveau_engine *engine;
+ struct nvkm_fb *pfb = nvxx_fb(&drm->device);
+ struct nvkm_fb_tile *tile = &pfb->tile.region[i];
+ struct nvkm_engine *engine;
nouveau_fence_unref(®->fence);
@@ -62,9 +62,9 @@ nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
pfb->tile.prog(pfb, i, tile);
- if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR)))
+ if ((engine = nvkm_engine(pfb, NVDEV_ENGINE_GR)))
engine->tile_prog(engine, i);
- if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG)))
+ if ((engine = nvkm_engine(pfb, NVDEV_ENGINE_MPEG)))
engine->tile_prog(engine, i);
}
@@ -105,7 +105,7 @@ nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
u32 size, u32 pitch, u32 flags)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_fb *pfb = nvxx_fb(&drm->device);
+ struct nvkm_fb *pfb = nvxx_fb(&drm->device);
struct nouveau_drm_tile *tile, *found = NULL;
int i;
@@ -325,7 +325,7 @@ nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig)
memtype == TTM_PL_FLAG_VRAM && contig) {
if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) {
if (bo->mem.mem_type == TTM_PL_VRAM) {
- struct nouveau_mem *mem = bo->mem.mm_node;
+ struct nvkm_mem *mem = bo->mem.mm_node;
if (!list_is_singular(&mem->regions))
evict = true;
}
@@ -459,7 +459,7 @@ void
nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
{
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
- struct nouveau_device *device = nvxx_device(&drm->device);
+ struct nvkm_device *device = nvxx_device(&drm->device);
struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
int i;
@@ -479,7 +479,7 @@ void
nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
{
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
- struct nouveau_device *device = nvxx_device(&drm->device);
+ struct nvkm_device *device = nvxx_device(&drm->device);
struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
int i;
@@ -695,7 +695,7 @@ static int
nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
{
- struct nouveau_mem *node = old_mem->mm_node;
+ struct nvkm_mem *node = old_mem->mm_node;
int ret = RING_SPACE(chan, 10);
if (ret == 0) {
BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
@@ -727,7 +727,7 @@ static int
nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
{
- struct nouveau_mem *node = old_mem->mm_node;
+ struct nvkm_mem *node = old_mem->mm_node;
u64 src_offset = node->vma[0].offset;
u64 dst_offset = node->vma[1].offset;
u32 page_count = new_mem->num_pages;
@@ -765,7 +765,7 @@ static int
nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
{
- struct nouveau_mem *node = old_mem->mm_node;
+ struct nvkm_mem *node = old_mem->mm_node;
u64 src_offset = node->vma[0].offset;
u64 dst_offset = node->vma[1].offset;
u32 page_count = new_mem->num_pages;
@@ -804,7 +804,7 @@ static int
nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
{
- struct nouveau_mem *node = old_mem->mm_node;
+ struct nvkm_mem *node = old_mem->mm_node;
u64 src_offset = node->vma[0].offset;
u64 dst_offset = node->vma[1].offset;
u32 page_count = new_mem->num_pages;
@@ -842,7 +842,7 @@ static int
nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
{
- struct nouveau_mem *node = old_mem->mm_node;
+ struct nvkm_mem *node = old_mem->mm_node;
int ret = RING_SPACE(chan, 7);
if (ret == 0) {
BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
@@ -860,7 +860,7 @@ static int
nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
{
- struct nouveau_mem *node = old_mem->mm_node;
+ struct nvkm_mem *node = old_mem->mm_node;
int ret = RING_SPACE(chan, 7);
if (ret == 0) {
BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
@@ -894,12 +894,12 @@ static int
nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
{
- struct nouveau_mem *node = old_mem->mm_node;
+ struct nvkm_mem *node = old_mem->mm_node;
u64 length = (new_mem->num_pages << PAGE_SHIFT);
u64 src_offset = node->vma[0].offset;
u64 dst_offset = node->vma[1].offset;
int src_tiled = !!node->memtype;
- int dst_tiled = !!((struct nouveau_mem *)new_mem->mm_node)->memtype;
+ int dst_tiled = !!((struct nvkm_mem *)new_mem->mm_node)->memtype;
int ret;
while (length) {
@@ -1036,25 +1036,25 @@ static int
nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
struct ttm_mem_reg *mem)
{
- struct nouveau_mem *old_node = bo->mem.mm_node;
- struct nouveau_mem *new_node = mem->mm_node;
+ struct nvkm_mem *old_node = bo->mem.mm_node;
+ struct nvkm_mem *new_node = mem->mm_node;
u64 size = (u64)mem->num_pages << PAGE_SHIFT;
int ret;
- ret = nouveau_vm_get(drm->client.vm, size, old_node->page_shift,
- NV_MEM_ACCESS_RW, &old_node->vma[0]);
+ ret = nvkm_vm_get(drm->client.vm, size, old_node->page_shift,
+ NV_MEM_ACCESS_RW, &old_node->vma[0]);
if (ret)
return ret;
- ret = nouveau_vm_get(drm->client.vm, size, new_node->page_shift,
- NV_MEM_ACCESS_RW, &old_node->vma[1]);
+ ret = nvkm_vm_get(drm->client.vm, size, new_node->page_shift,
+ NV_MEM_ACCESS_RW, &old_node->vma[1]);
if (ret) {
- nouveau_vm_put(&old_node->vma[0]);
+ nvkm_vm_put(&old_node->vma[0]);
return ret;
}
- nouveau_vm_map(&old_node->vma[0], old_node);
- nouveau_vm_map(&old_node->vma[1], new_node);
+ nvkm_vm_map(&old_node->vma[0], old_node);
+ nvkm_vm_map(&old_node->vma[1], new_node);
return 0;
}
@@ -1069,7 +1069,7 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
int ret;
/* create temporary vmas for the transfer and attach them to the
- * old nouveau_mem node, these will get cleaned up after ttm has
+ * old nvkm_mem node, these will get cleaned up after ttm has
* destroyed the ttm_mem_reg
*/
if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
@@ -1231,7 +1231,7 @@ static void
nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
{
struct nouveau_bo *nvbo = nouveau_bo(bo);
- struct nouveau_vma *vma;
+ struct nvkm_vma *vma;
/* ttm can now (stupidly) pass the driver bos it didn't create... */
if (bo->destroy != nouveau_bo_del_ttm)
@@ -1241,9 +1241,9 @@ nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
(new_mem->mem_type == TTM_PL_VRAM ||
nvbo->page_shift != vma->vm->mmu->lpg_shift)) {
- nouveau_vm_map(vma, new_mem->mm_node);
+ nvkm_vm_map(vma, new_mem->mm_node);
} else {
- nouveau_vm_unmap(vma);
+ nvkm_vm_unmap(vma);
}
}
}
@@ -1354,7 +1354,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
{
struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
struct nouveau_drm *drm = nouveau_bdev(bdev);
- struct nouveau_mem *node = mem->mm_node;
+ struct nvkm_mem *node = mem->mm_node;
int ret;
mem->bus.addr = NULL;
@@ -1385,7 +1385,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
mem->bus.base = nv_device_resource_start(nvxx_device(&drm->device), 1);
mem->bus.is_iomem = true;
if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
- struct nouveau_bar *bar = nvxx_bar(&drm->device);
+ struct nvkm_bar *bar = nvxx_bar(&drm->device);
ret = bar->umap(bar, node, NV_MEM_ACCESS_RW,
&node->bar_vma);
@@ -1405,8 +1405,8 @@ static void
nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
{
struct nouveau_drm *drm = nouveau_bdev(bdev);
- struct nouveau_bar *bar = nvxx_bar(&drm->device);
- struct nouveau_mem *node = mem->mm_node;
+ struct nvkm_bar *bar = nvxx_bar(&drm->device);
+ struct nvkm_mem *node = mem->mm_node;
if (!node->bar_vma.node)
return;
@@ -1465,7 +1465,7 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm)
{
struct ttm_dma_tt *ttm_dma = (void *)ttm;
struct nouveau_drm *drm;
- struct nouveau_device *device;
+ struct nvkm_device *device;
struct drm_device *dev;
struct device *pdev;
unsigned i;
@@ -1539,7 +1539,7 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
{
struct ttm_dma_tt *ttm_dma = (void *)ttm;
struct nouveau_drm *drm;
- struct nouveau_device *device;
+ struct nvkm_device *device;
struct drm_device *dev;
struct device *pdev;
unsigned i;
@@ -1613,10 +1613,10 @@ struct ttm_bo_driver nouveau_bo_driver = {
.io_mem_free = &nouveau_ttm_io_mem_free,
};
-struct nouveau_vma *
-nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
+struct nvkm_vma *
+nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nvkm_vm *vm)
{
- struct nouveau_vma *vma;
+ struct nvkm_vma *vma;
list_for_each_entry(vma, &nvbo->vma_list, head) {
if (vma->vm == vm)
return vma;
@@ -1626,13 +1626,13 @@ nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
}
int
-nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
- struct nouveau_vma *vma)
+nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nvkm_vm *vm,
+ struct nvkm_vma *vma)
{
const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
int ret;
- ret = nouveau_vm_get(vm, size, nvbo->page_shift,
+ ret = nvkm_vm_get(vm, size, nvbo->page_shift,
NV_MEM_ACCESS_RW, vma);
if (ret)
return ret;
@@ -1640,7 +1640,7 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
(nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
nvbo->page_shift != vma->vm->mmu->lpg_shift))
- nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
+ nvkm_vm_map(vma, nvbo->bo.mem.mm_node);
list_add_tail(&vma->head, &nvbo->vma_list);
vma->refcount = 1;
@@ -1648,12 +1648,12 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
}
void
-nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
+nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nvkm_vma *vma)
{
if (vma->node) {
if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
- nouveau_vm_unmap(vma);
- nouveau_vm_put(vma);
+ nvkm_vm_unmap(vma);
+ nvkm_vm_put(vma);
list_del(&vma->head);
}
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h
index 302aa63b81a4..e42360983229 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.h
@@ -5,7 +5,7 @@
struct nouveau_channel;
struct nouveau_fence;
-struct nouveau_vma;
+struct nvkm_vma;
struct nouveau_bo {
struct ttm_buffer_object bo;
@@ -87,12 +87,12 @@ int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
void nouveau_bo_sync_for_device(struct nouveau_bo *nvbo);
void nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo);
-struct nouveau_vma *
-nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
+struct nvkm_vma *
+nouveau_bo_vma_find(struct nouveau_bo *, struct nvkm_vm *);
-int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *,
- struct nouveau_vma *);
-void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);
+int nouveau_bo_vma_add(struct nouveau_bo *, struct nvkm_vm *,
+ struct nvkm_vma *);
+void nouveau_bo_vma_del(struct nouveau_bo *, struct nvkm_vma *);
/* TODO: submit equivalent to TTM generic API upstream? */
static inline void __iomem *
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c
index 3bcbbd329cf2..e581f63cbf25 100644
--- a/drivers/gpu/drm/nouveau/nouveau_chan.c
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.c
@@ -88,7 +88,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
u32 handle, u32 size, struct nouveau_channel **pchan)
{
struct nouveau_cli *cli = (void *)nvif_client(&device->base);
- struct nouveau_mmu *mmu = nvxx_mmu(device);
+ struct nvkm_mmu *mmu = nvxx_mmu(device);
struct nv_dma_v0 args = {};
struct nouveau_channel *chan;
u32 target;
@@ -281,8 +281,8 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
{
struct nvif_device *device = chan->device;
struct nouveau_cli *cli = (void *)nvif_client(&device->base);
- struct nouveau_mmu *mmu = nvxx_mmu(device);
- struct nouveau_sw_chan *swch;
+ struct nvkm_mmu *mmu = nvxx_mmu(device);
+ struct nvkm_sw_chan *swch;
struct nv_dma_v0 args = {};
int ret, i;
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.h b/drivers/gpu/drm/nouveau/nouveau_chan.h
index 8309c24ee698..8b3640f69e4f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_chan.h
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.h
@@ -16,7 +16,7 @@ struct nouveau_channel {
struct {
struct nouveau_bo *buffer;
- struct nouveau_vma vma;
+ struct nvkm_vma vma;
struct nvif_object ctxdma;
} push;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 4ab6340b0dac..db7095ae4ebb 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -115,7 +115,7 @@ nouveau_connector_ddc_detect(struct drm_connector *connector)
struct drm_device *dev = connector->dev;
struct nouveau_connector *nv_connector = nouveau_connector(connector);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_gpio *gpio = nvxx_gpio(&drm->device);
+ struct nvkm_gpio *gpio = nvxx_gpio(&drm->device);
struct nouveau_encoder *nv_encoder;
struct drm_encoder *encoder;
int i, panel = -ENODEV;
@@ -241,7 +241,7 @@ nouveau_connector_detect(struct drm_connector *connector, bool force)
struct nouveau_connector *nv_connector = nouveau_connector(connector);
struct nouveau_encoder *nv_encoder = NULL;
struct nouveau_encoder *nv_partner;
- struct nouveau_i2c_port *i2c;
+ struct nvkm_i2c_port *i2c;
int type;
int ret;
enum drm_connector_status conn_status = connector_status_disconnected;
@@ -985,7 +985,7 @@ nouveau_connector_aux_xfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
struct nouveau_connector *nv_connector =
container_of(aux, typeof(*nv_connector), aux);
struct nouveau_encoder *nv_encoder;
- struct nouveau_i2c_port *port;
+ struct nvkm_i2c_port *port;
int ret;
nv_encoder = find_encoder(&nv_connector->base, DCB_OUTPUT_DP);
@@ -996,13 +996,13 @@ nouveau_connector_aux_xfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
if (msg->size == 0)
return msg->size;
- ret = nouveau_i2c(port)->acquire(port, 0);
+ ret = nvkm_i2c(port)->acquire(port, 0);
if (ret)
return ret;
ret = port->func->aux(port, false, msg->request, msg->address,
msg->buffer, msg->size);
- nouveau_i2c(port)->release(port);
+ nvkm_i2c(port)->release(port);
if (ret >= 0) {
msg->reply = ret;
return msg->size;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h
index a2d099142d96..7446ee66ea04 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.h
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.h
@@ -33,7 +33,7 @@
#include <drm/drm_dp_helper.h>
#include "nouveau_crtc.h"
-struct nouveau_i2c_port;
+struct nvkm_i2c_port;
enum nouveau_underscan_type {
UNDERSCAN_OFF,
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h
index a94dcdaccf59..a6213e2425c5 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.h
+++ b/drivers/gpu/drm/nouveau/nouveau_display.h
@@ -8,7 +8,7 @@
struct nouveau_framebuffer {
struct drm_framebuffer base;
struct nouveau_bo *nvbo;
- struct nouveau_vma vma;
+ struct nvkm_vma vma;
u32 r_handle;
u32 r_format;
u32 r_pitch;
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c
index 8508603cc8c3..6d9245aa81a6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.c
@@ -84,7 +84,7 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
{
struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base);
struct nouveau_bo *pb = chan->push.buffer;
- struct nouveau_vma *vma;
+ struct nvkm_vma *vma;
int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;
u64 offset;
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index c5137cccce7d..c3ef30b3a5ec 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -31,7 +31,7 @@
#include "nouveau_crtc.h"
static void
-nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch,
+nouveau_dp_probe_oui(struct drm_device *dev, struct nvkm_i2c_port *auxch,
u8 *dpcd)
{
struct nouveau_drm *drm = nouveau_drm(dev);
@@ -55,7 +55,7 @@ nouveau_dp_detect(struct nouveau_encoder *nv_encoder)
{
struct drm_device *dev = nv_encoder->base.base.dev;
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_i2c_port *auxch;
+ struct nvkm_i2c_port *auxch;
u8 *dpcd = nv_encoder->dp.dpcd;
int ret;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index f4ac7b5af85e..8763deb5188b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -124,7 +124,7 @@ nouveau_cli_create(u64 name, const char *sname,
static void
nouveau_cli_destroy(struct nouveau_cli *cli)
{
- nouveau_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL);
+ nvkm_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL);
nvif_client_fini(&cli->base);
usif_client_fini(cli);
}
@@ -134,7 +134,7 @@ nouveau_accel_fini(struct nouveau_drm *drm)
{
nouveau_channel_del(&drm->channel);
nvif_object_fini(&drm->ntfy);
- nouveau_gpuobj_ref(NULL, &drm->notify);
+ nvkm_gpuobj_ref(NULL, &drm->notify);
nvif_object_fini(&drm->nvsw);
nouveau_channel_del(&drm->cechan);
nvif_object_fini(&drm->ttm.copy);
@@ -231,7 +231,7 @@ nouveau_accel_init(struct nouveau_drm *drm)
ret = nvif_object_init(drm->channel->object, NULL, NVDRM_NVSW,
nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw);
if (ret == 0) {
- struct nouveau_sw_chan *swch;
+ struct nvkm_sw_chan *swch;
ret = RING_SPACE(drm->channel, 2);
if (ret == 0) {
if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
@@ -255,8 +255,8 @@ nouveau_accel_init(struct nouveau_drm *drm)
}
if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
- ret = nouveau_gpuobj_new(nvxx_object(&drm->device), NULL, 32,
- 0, 0, &drm->notify);
+ ret = nvkm_gpuobj_new(nvxx_object(&drm->device), NULL, 32,
+ 0, 0, &drm->notify);
if (ret) {
NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
nouveau_accel_fini(drm);
@@ -285,7 +285,7 @@ nouveau_accel_init(struct nouveau_drm *drm)
static int nouveau_drm_probe(struct pci_dev *pdev,
const struct pci_device_id *pent)
{
- struct nouveau_device *device;
+ struct nvkm_device *device;
struct apertures_struct *aper;
bool boot = false;
int ret;
@@ -318,9 +318,9 @@ static int nouveau_drm_probe(struct pci_dev *pdev,
remove_conflicting_framebuffers(aper, "nouveaufb", boot);
kfree(aper);
- ret = nouveau_device_create(pdev, NVKM_BUS_PCI,
- nouveau_pci_name(pdev), pci_name(pdev),
- nouveau_config, nouveau_debug, &device);
+ ret = nvkm_device_create(pdev, NVKM_BUS_PCI,
+ nouveau_pci_name(pdev), pci_name(pdev),
+ nouveau_config, nouveau_debug, &device);
if (ret)
return ret;
@@ -328,7 +328,7 @@ static int nouveau_drm_probe(struct pci_dev *pdev,
ret = drm_get_pci_dev(pdev, pent, &driver_pci);
if (ret) {
- nouveau_object_ref(NULL, (struct nouveau_object **)&device);
+ nvkm_object_ref(NULL, (struct nvkm_object **)&device);
return ret;
}
@@ -380,7 +380,7 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
dev->dev_private = drm;
drm->dev = dev;
nvxx_client(&drm->client.base)->debug =
- nouveau_dbgopt(nouveau_debug, "DRM");
+ nvkm_dbgopt(nouveau_debug, "DRM");
INIT_LIST_HEAD(&drm->clients);
spin_lock_init(&drm->tile.lock);
@@ -435,8 +435,8 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
nouveau_agp_init(drm);
if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
- ret = nouveau_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
- 0x1000, &drm->client.vm);
+ ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
+ 0x1000, &drm->client.vm);
if (ret)
goto fail_device;
@@ -523,16 +523,16 @@ void
nouveau_drm_device_remove(struct drm_device *dev)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_client *client;
- struct nouveau_object *device;
+ struct nvkm_client *client;
+ struct nvkm_object *device;
dev->irq_enabled = false;
client = nvxx_client(&drm->client.base);
device = client->device;
drm_put_dev(dev);
- nouveau_object_ref(NULL, &device);
- nouveau_object_debug();
+ nvkm_object_ref(NULL, &device);
+ nvkm_object_debug();
}
static void
@@ -831,8 +831,8 @@ nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
cli->base.super = false;
if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
- ret = nouveau_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
- 0x1000, &cli->vm);
+ ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
+ 0x1000, &cli->vm);
if (ret) {
nouveau_cli_destroy(cli);
goto out_suspend;
@@ -1056,10 +1056,10 @@ nouveau_platform_device_create_(struct platform_device *pdev, int size,
struct drm_device *drm;
int err;
- err = nouveau_device_create_(pdev, NVKM_BUS_PLATFORM,
- nouveau_platform_name(pdev),
- dev_name(&pdev->dev), nouveau_config,
- nouveau_debug, size, pobject);
+ err = nvkm_device_create_(pdev, NVKM_BUS_PLATFORM,
+ nouveau_platform_name(pdev),
+ dev_name(&pdev->dev), nouveau_config,
+ nouveau_debug, size, pobject);
if (err)
return ERR_PTR(err);
@@ -1079,7 +1079,7 @@ nouveau_platform_device_create_(struct platform_device *pdev, int size,
return drm;
err_free:
- nouveau_object_ref(NULL, (struct nouveau_object **)pobject);
+ nvkm_object_ref(NULL, (struct nvkm_object **)pobject);
return ERR_PTR(err);
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h
index 8ae36f265fb8..fc68f0973f9e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.h
@@ -80,7 +80,7 @@ enum nouveau_drm_handle {
struct nouveau_cli {
struct nvif_client base;
- struct nouveau_vm *vm; /*XXX*/
+ struct nvkm_vm *vm; /*XXX*/
struct list_head head;
struct mutex mutex;
void *abi16;
@@ -142,7 +142,7 @@ struct nouveau_drm {
/* context for accelerated drm-internal operations */
struct nouveau_channel *cechan;
struct nouveau_channel *channel;
- struct nouveau_gpuobj *notify;
+ struct nvkm_gpuobj *notify;
struct nouveau_fbdev *fbcon;
struct nvif_object nvsw;
struct nvif_object ntfy;
diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h
index 5f0e37fc2849..c57a37e8e1eb 100644
--- a/drivers/gpu/drm/nouveau/nouveau_encoder.h
+++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h
@@ -34,14 +34,14 @@
#define NV_DPMS_CLEARED 0x80
-struct nouveau_i2c_port;
+struct nvkm_i2c_port;
struct nouveau_encoder {
struct drm_encoder_slave base;
struct dcb_output *dcb;
int or;
- struct nouveau_i2c_port *i2c;
+ struct nvkm_i2c_port *i2c;
/* different to drm_encoder.crtc, this reflects what's
* actually programmed on the hw, not the proposed crtc */
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.h b/drivers/gpu/drm/nouveau/nouveau_fence.h
index 96e461c6f68f..d9241d8247fb 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.h
@@ -89,9 +89,9 @@ int nouveau_flip_complete(void *chan);
struct nv84_fence_chan {
struct nouveau_fence_chan base;
- struct nouveau_vma vma;
- struct nouveau_vma vma_gart;
- struct nouveau_vma dispc_vma[4];
+ struct nvkm_vma vma;
+ struct nvkm_vma vma_gart;
+ struct nvkm_vma dispc_vma[4];
};
struct nv84_fence_priv {
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 8453d1aac0e2..7c077fced1d1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -64,7 +64,7 @@ nouveau_gem_object_open(struct drm_gem_object *gem, struct drm_file *file_priv)
struct nouveau_cli *cli = nouveau_cli(file_priv);
struct nouveau_bo *nvbo = nouveau_gem_object(gem);
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
- struct nouveau_vma *vma;
+ struct nvkm_vma *vma;
struct device *dev = drm->dev->dev;
int ret;
@@ -105,14 +105,14 @@ out:
static void
nouveau_gem_object_delete(void *data)
{
- struct nouveau_vma *vma = data;
- nouveau_vm_unmap(vma);
- nouveau_vm_put(vma);
+ struct nvkm_vma *vma = data;
+ nvkm_vm_unmap(vma);
+ nvkm_vm_put(vma);
kfree(vma);
}
static void
-nouveau_gem_object_unmap(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
+nouveau_gem_object_unmap(struct nouveau_bo *nvbo, struct nvkm_vma *vma)
{
const bool mapped = nvbo->bo.mem.mem_type != TTM_PL_SYSTEM;
struct reservation_object *resv = nvbo->bo.resv;
@@ -135,8 +135,8 @@ nouveau_gem_object_unmap(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
nouveau_fence_work(fence, nouveau_gem_object_delete, vma);
} else {
if (mapped)
- nouveau_vm_unmap(vma);
- nouveau_vm_put(vma);
+ nvkm_vm_unmap(vma);
+ nvkm_vm_put(vma);
kfree(vma);
}
}
@@ -148,7 +148,7 @@ nouveau_gem_object_close(struct drm_gem_object *gem, struct drm_file *file_priv)
struct nouveau_bo *nvbo = nouveau_gem_object(gem);
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
struct device *dev = drm->dev->dev;
- struct nouveau_vma *vma;
+ struct nvkm_vma *vma;
int ret;
if (!cli->vm)
@@ -222,7 +222,7 @@ nouveau_gem_info(struct drm_file *file_priv, struct drm_gem_object *gem,
{
struct nouveau_cli *cli = nouveau_cli(file_priv);
struct nouveau_bo *nvbo = nouveau_gem_object(gem);
- struct nouveau_vma *vma;
+ struct nvkm_vma *vma;
if (nvbo->bo.mem.mem_type == TTM_PL_TT)
rep->domain = NOUVEAU_GEM_DOMAIN_GART;
@@ -251,7 +251,7 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data,
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_cli *cli = nouveau_cli(file_priv);
- struct nouveau_fb *pfb = nvxx_fb(&drm->device);
+ struct nvkm_fb *pfb = nvxx_fb(&drm->device);
struct drm_nouveau_gem_new *req = data;
struct nouveau_bo *nvbo = NULL;
int ret = 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c b/drivers/gpu/drm/nouveau/nouveau_hwmon.c
index b5c445e02bfc..0dbe0060f86e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_hwmon.c
@@ -40,7 +40,7 @@ nouveau_hwmon_show_temp(struct device *d, struct device_attribute *a, char *buf)
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
int temp = therm->temp_get(therm);
if (temp < 0)
@@ -66,7 +66,7 @@ nouveau_hwmon_temp1_auto_point1_temp(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST) * 1000);
@@ -78,7 +78,7 @@ nouveau_hwmon_set_temp1_auto_point1_temp(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -99,7 +99,7 @@ nouveau_hwmon_temp1_auto_point1_temp_hyst(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST) * 1000);
@@ -111,7 +111,7 @@ nouveau_hwmon_set_temp1_auto_point1_temp_hyst(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -131,7 +131,7 @@ nouveau_hwmon_max_temp(struct device *d, struct device_attribute *a, char *buf)
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK) * 1000);
@@ -142,7 +142,7 @@ nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -162,7 +162,7 @@ nouveau_hwmon_max_temp_hyst(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST) * 1000);
@@ -173,7 +173,7 @@ nouveau_hwmon_set_max_temp_hyst(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -194,7 +194,7 @@ nouveau_hwmon_critical_temp(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NVKM_THERM_ATTR_THRS_CRITICAL) * 1000);
@@ -206,7 +206,7 @@ nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -227,7 +227,7 @@ nouveau_hwmon_critical_temp_hyst(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NVKM_THERM_ATTR_THRS_CRITICAL_HYST) * 1000);
@@ -240,7 +240,7 @@ nouveau_hwmon_set_critical_temp_hyst(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -260,7 +260,7 @@ nouveau_hwmon_emergency_temp(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN) * 1000);
@@ -272,7 +272,7 @@ nouveau_hwmon_set_emergency_temp(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -293,7 +293,7 @@ nouveau_hwmon_emergency_temp_hyst(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n",
therm->attr_get(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST) * 1000);
@@ -306,7 +306,7 @@ nouveau_hwmon_set_emergency_temp_hyst(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
long value;
if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -346,7 +346,7 @@ nouveau_hwmon_show_fan1_input(struct device *d, struct device_attribute *attr,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
return snprintf(buf, PAGE_SIZE, "%d\n", therm->fan_sense(therm));
}
@@ -359,7 +359,7 @@ nouveau_hwmon_get_pwm1_enable(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
int ret;
ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MODE);
@@ -375,7 +375,7 @@ nouveau_hwmon_set_pwm1_enable(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
long value;
int ret;
@@ -398,7 +398,7 @@ nouveau_hwmon_get_pwm1(struct device *d, struct device_attribute *a, char *buf)
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
int ret;
ret = therm->fan_get(therm);
@@ -414,7 +414,7 @@ nouveau_hwmon_set_pwm1(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
int ret = -ENODEV;
long value;
@@ -438,7 +438,7 @@ nouveau_hwmon_get_pwm1_min(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
int ret;
ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MIN_DUTY);
@@ -454,7 +454,7 @@ nouveau_hwmon_set_pwm1_min(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
long value;
int ret;
@@ -478,7 +478,7 @@ nouveau_hwmon_get_pwm1_max(struct device *d,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
int ret;
ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MAX_DUTY);
@@ -494,7 +494,7 @@ nouveau_hwmon_set_pwm1_max(struct device *d, struct device_attribute *a,
{
struct drm_device *dev = dev_get_drvdata(d);
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
long value;
int ret;
@@ -561,7 +561,7 @@ nouveau_hwmon_init(struct drm_device *dev)
{
#if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE))
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_therm *therm = nvxx_therm(&drm->device);
+ struct nvkm_therm *therm = nvxx_therm(&drm->device);
struct nouveau_hwmon *hwmon;
struct device *hwmon_dev;
int ret = 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_nvif.c b/drivers/gpu/drm/nouveau/nouveau_nvif.c
index 7f7bd329425e..ca0ad9d1563d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_nvif.c
+++ b/drivers/gpu/drm/nouveau/nouveau_nvif.c
@@ -60,22 +60,22 @@ nvkm_client_ioctl(void *priv, bool super, void *data, u32 size, void **hack)
static int
nvkm_client_resume(void *priv)
{
- return nouveau_client_init(priv);
+ return nvkm_client_init(priv);
}
static int
nvkm_client_suspend(void *priv)
{
- return nouveau_client_fini(priv, true);
+ return nvkm_client_fini(priv, true);
}
static void
nvkm_client_driver_fini(void *priv)
{
- struct nouveau_object *client = priv;
- nouveau_client_fini(nv_client(client), false);
+ struct nvkm_object *client = priv;
+ nvkm_client_fini(nv_client(client), false);
atomic_set(&client->refcount, 1);
- nouveau_object_ref(NULL, &client);
+ nvkm_object_ref(NULL, &client);
}
static int
@@ -110,10 +110,10 @@ static int
nvkm_client_driver_init(const char *name, u64 device, const char *cfg,
const char *dbg, void **ppriv)
{
- struct nouveau_client *client;
+ struct nvkm_client *client;
int ret;
- ret = nouveau_client_create(name, device, cfg, dbg, &client);
+ ret = nvkm_client_create(name, device, cfg, dbg, &client);
*ppriv = client;
if (ret)
return ret;
diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.c b/drivers/gpu/drm/nouveau/nouveau_platform.c
index 5e6a2c90b8e2..dc5900bf54ff 100644
--- a/drivers/gpu/drm/nouveau/nouveau_platform.c
+++ b/drivers/gpu/drm/nouveau/nouveau_platform.c
@@ -152,7 +152,7 @@ static int nouveau_platform_remove(struct platform_device *pdev)
{
struct drm_device *drm_dev = platform_get_drvdata(pdev);
struct nouveau_drm *drm = nouveau_drm(drm_dev);
- struct nouveau_device *device = nvxx_device(&drm->device);
+ struct nvkm_device *device = nvxx_device(&drm->device);
struct nouveau_platform_gpu *gpu = nv_device_to_platform(device)->gpu;
nouveau_drm_device_remove(drm_dev);
diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.h b/drivers/gpu/drm/nouveau/nouveau_platform.h
index ca22c525329a..268bb7213681 100644
--- a/drivers/gpu/drm/nouveau/nouveau_platform.h
+++ b/drivers/gpu/drm/nouveau/nouveau_platform.h
@@ -39,7 +39,7 @@ struct nouveau_platform_gpu {
};
struct nouveau_platform_device {
- struct nouveau_device device;
+ struct nvkm_device device;
struct nouveau_platform_gpu *gpu;
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index 23c377a6c761..8c3053a177d6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -9,7 +9,7 @@ struct nouveau_sgdma_be {
* nouve_bo.c works properly, otherwise have to move them here
*/
struct ttm_dma_tt ttm;
- struct nouveau_mem *node;
+ struct nvkm_mem *node;
};
static void
@@ -27,7 +27,7 @@ static int
nv04_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
{
struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm;
- struct nouveau_mem *node = mem->mm_node;
+ struct nvkm_mem *node = mem->mm_node;
if (ttm->sg) {
node->sg = ttm->sg;
@@ -38,7 +38,7 @@ nv04_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
}
node->size = (mem->num_pages << PAGE_SHIFT) >> 12;
- nouveau_vm_map(&node->vma[0], node);
+ nvkm_vm_map(&node->vma[0], node);
nvbe->node = node;
return 0;
}
@@ -47,7 +47,7 @@ static int
nv04_sgdma_unbind(struct ttm_tt *ttm)
{
struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm;
- nouveau_vm_unmap(&nvbe->node->vma[0]);
+ nvkm_vm_unmap(&nvbe->node->vma[0]);
return 0;
}
@@ -61,7 +61,7 @@ static int
nv50_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
{
struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm;
- struct nouveau_mem *node = mem->mm_node;
+ struct nvkm_mem *node = mem->mm_node;
/* noop: bound in move_notify() */
if (ttm->sg) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index 7149f6d1fb43..273e50110ec3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -33,7 +33,7 @@ static int
nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
struct nouveau_drm *drm = nouveau_bdev(man->bdev);
- struct nouveau_fb *pfb = nvxx_fb(&drm->device);
+ struct nvkm_fb *pfb = nvxx_fb(&drm->device);
man->priv = pfb;
return 0;
}
@@ -46,16 +46,16 @@ nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
}
static inline void
-nouveau_mem_node_cleanup(struct nouveau_mem *node)
+nvkm_mem_node_cleanup(struct nvkm_mem *node)
{
if (node->vma[0].node) {
- nouveau_vm_unmap(&node->vma[0]);
- nouveau_vm_put(&node->vma[0]);
+ nvkm_vm_unmap(&node->vma[0]);
+ nvkm_vm_put(&node->vma[0]);
}
if (node->vma[1].node) {
- nouveau_vm_unmap(&node->vma[1]);
- nouveau_vm_put(&node->vma[1]);
+ nvkm_vm_unmap(&node->vma[1]);
+ nvkm_vm_put(&node->vma[1]);
}
}
@@ -64,9 +64,9 @@ nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
struct ttm_mem_reg *mem)
{
struct nouveau_drm *drm = nouveau_bdev(man->bdev);
- struct nouveau_fb *pfb = nvxx_fb(&drm->device);
- nouveau_mem_node_cleanup(mem->mm_node);
- pfb->ram->put(pfb, (struct nouveau_mem **)&mem->mm_node);
+ struct nvkm_fb *pfb = nvxx_fb(&drm->device);
+ nvkm_mem_node_cleanup(mem->mm_node);
+ pfb->ram->put(pfb, (struct nvkm_mem **)&mem->mm_node);
}
static int
@@ -76,9 +76,9 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
struct ttm_mem_reg *mem)
{
struct nouveau_drm *drm = nouveau_bdev(man->bdev);
- struct nouveau_fb *pfb = nvxx_fb(&drm->device);
+ struct nvkm_fb *pfb = nvxx_fb(&drm->device);
struct nouveau_bo *nvbo = nouveau_bo(bo);
- struct nouveau_mem *node;
+ struct nvkm_mem *node;
u32 size_nc = 0;
int ret;
@@ -103,9 +103,9 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
static void
nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
{
- struct nouveau_fb *pfb = man->priv;
- struct nouveau_mm *mm = &pfb->vram;
- struct nouveau_mm_node *r;
+ struct nvkm_fb *pfb = man->priv;
+ struct nvkm_mm *mm = &pfb->vram;
+ struct nvkm_mm_node *r;
u32 total = 0, free = 0;
mutex_lock(&nv_subdev(pfb)->mutex);
@@ -150,7 +150,7 @@ static void
nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
struct ttm_mem_reg *mem)
{
- nouveau_mem_node_cleanup(mem->mm_node);
+ nvkm_mem_node_cleanup(mem->mm_node);
kfree(mem->mm_node);
mem->mm_node = NULL;
}
@@ -163,7 +163,7 @@ nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
{
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
struct nouveau_bo *nvbo = nouveau_bo(bo);
- struct nouveau_mem *node;
+ struct nvkm_mem *node;
node = kzalloc(sizeof(*node), GFP_KERNEL);
if (!node)
@@ -208,10 +208,10 @@ static int
nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
struct nouveau_drm *drm = nouveau_bdev(man->bdev);
- struct nouveau_mmu *mmu = nvxx_mmu(&drm->device);
+ struct nvkm_mmu *mmu = nvxx_mmu(&drm->device);
struct nv04_mmu_priv *priv = (void *)mmu;
- struct nouveau_vm *vm = NULL;
- nouveau_vm_ref(priv->vm, &vm, NULL);
+ struct nvkm_vm *vm = NULL;
+ nvkm_vm_ref(priv->vm, &vm, NULL);
man->priv = vm;
return 0;
}
@@ -219,8 +219,8 @@ nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
static int
nv04_gart_manager_fini(struct ttm_mem_type_manager *man)
{
- struct nouveau_vm *vm = man->priv;
- nouveau_vm_ref(NULL, &vm, NULL);
+ struct nvkm_vm *vm = man->priv;
+ nvkm_vm_ref(NULL, &vm, NULL);
man->priv = NULL;
return 0;
}
@@ -228,9 +228,9 @@ nv04_gart_manager_fini(struct ttm_mem_type_manager *man)
static void
nv04_gart_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem)
{
- struct nouveau_mem *node = mem->mm_node;
+ struct nvkm_mem *node = mem->mm_node;
if (node->vma[0].node)
- nouveau_vm_put(&node->vma[0]);
+ nvkm_vm_put(&node->vma[0]);
kfree(mem->mm_node);
mem->mm_node = NULL;
}
@@ -241,7 +241,7 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man,
const struct ttm_place *place,
struct ttm_mem_reg *mem)
{
- struct nouveau_mem *node;
+ struct nvkm_mem *node;
int ret;
node = kzalloc(sizeof(*node), GFP_KERNEL);
@@ -250,8 +250,8 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man,
node->page_shift = 12;
- ret = nouveau_vm_get(man->priv, mem->num_pages << 12, node->page_shift,
- NV_MEM_ACCESS_RW, &node->vma[0]);
+ ret = nvkm_vm_get(man->priv, mem->num_pages << 12, node->page_shift,
+ NV_MEM_ACCESS_RW, &node->vma[0]);
if (ret) {
kfree(node);
return ret;
diff --git a/drivers/gpu/drm/nouveau/nv04_fence.c b/drivers/gpu/drm/nouveau/nv04_fence.c
index af0eaa7bcb33..c2e05e64cd6f 100644
--- a/drivers/gpu/drm/nouveau/nv04_fence.c
+++ b/drivers/gpu/drm/nouveau/nv04_fence.c
@@ -57,7 +57,7 @@ nv04_fence_sync(struct nouveau_fence *fence,
static u32
nv04_fence_read(struct nouveau_channel *chan)
{
- struct nouveau_fifo_chan *fifo = nvxx_fifo_chan(chan);;
+ struct nvkm_fifo_chan *fifo = nvxx_fifo_chan(chan);;
return atomic_read(&fifo->refcnt);
}
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index bba84448144e..7da7958556a3 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -1677,7 +1677,7 @@ static int
nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
{
struct nouveau_drm *drm = nouveau_drm(connector->dev);
- struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
+ struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
struct nouveau_encoder *nv_encoder;
struct drm_encoder *encoder;
int type = DRM_MODE_ENCODER_DAC;
@@ -2062,7 +2062,7 @@ static int
nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
{
struct nouveau_drm *drm = nouveau_drm(connector->dev);
- struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
+ struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
struct nouveau_encoder *nv_encoder;
struct drm_encoder *encoder;
int type;
@@ -2233,8 +2233,8 @@ static int
nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
{
struct nouveau_drm *drm = nouveau_drm(connector->dev);
- struct nouveau_i2c *i2c = nvxx_i2c(&drm->device);
- struct nouveau_i2c_port *ddc = NULL;
+ struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
+ struct nvkm_i2c_port *ddc = NULL;
struct nouveau_encoder *nv_encoder;
struct drm_encoder *encoder;
int type;
diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c
index 46fe1fb5c9be..bf429cabbaa8 100644
--- a/drivers/gpu/drm/nouveau/nv84_fence.c
+++ b/drivers/gpu/drm/nouveau/nv84_fence.c
@@ -213,7 +213,7 @@ nv84_fence_destroy(struct nouveau_drm *drm)
int
nv84_fence_create(struct nouveau_drm *drm)
{
- struct nouveau_fifo *pfifo = nvxx_fifo(&drm->device);
+ struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device);
struct nv84_fence_priv *priv;
int ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
index 51fcf7960417..0ca9dcabb6d3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
@@ -21,18 +21,16 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/option.h>
-
-#include <subdev/i2c.h>
-#include <subdev/mxm.h>
-#include <subdev/bios.h>
-#include <subdev/bios/mxm.h>
-
#include "mxms.h"
+#include <core/device.h>
+#include <core/option.h>
+#include <subdev/bios.h>
+#include <subdev/bios/mxm.h>
+#include <subdev/i2c.h>
+
static bool
-mxm_shadow_rom_fetch(struct nouveau_i2c_port *i2c, u8 addr,
+mxm_shadow_rom_fetch(struct nvkm_i2c_port *i2c, u8 addr,
u8 offset, u8 size, u8 *data)
{
struct i2c_msg msgs[] = {
@@ -44,11 +42,11 @@ mxm_shadow_rom_fetch(struct nouveau_i2c_port *i2c, u8 addr,
}
static bool
-mxm_shadow_rom(struct nouveau_mxm *mxm, u8 version)
+mxm_shadow_rom(struct nvkm_mxm *mxm, u8 version)
{
- struct nouveau_bios *bios = nouveau_bios(mxm);
- struct nouveau_i2c *i2c = nouveau_i2c(mxm);
- struct nouveau_i2c_port *port = NULL;
+ struct nvkm_bios *bios = nvkm_bios(mxm);
+ struct nvkm_i2c *i2c = nvkm_i2c(mxm);
+ struct nvkm_i2c_port *port = NULL;
u8 i2cidx, mxms[6], addr, size;
i2cidx = mxm_ddc_map(bios, 1 /* LVDS_DDC */) & 0x0f;
@@ -79,9 +77,9 @@ mxm_shadow_rom(struct nouveau_mxm *mxm, u8 version)
#if defined(CONFIG_ACPI)
static bool
-mxm_shadow_dsm(struct nouveau_mxm *mxm, u8 version)
+mxm_shadow_dsm(struct nvkm_mxm *mxm, u8 version)
{
- struct nouveau_device *device = nv_device(mxm);
+ struct nvkm_device *device = nv_device(mxm);
static char muid[] = {
0x00, 0xA4, 0x04, 0x40, 0x7D, 0x91, 0xF2, 0x4C,
0xB8, 0x9C, 0x79, 0xB6, 0x2F, 0xD5, 0x56, 0x65
@@ -129,7 +127,7 @@ mxm_shadow_dsm(struct nouveau_mxm *mxm, u8 version)
#define WMI_WMMX_GUID "F6CB5C3C-9CAE-4EBD-B577-931EA32A2CC0"
static u8
-wmi_wmmx_mxmi(struct nouveau_mxm *mxm, u8 version)
+wmi_wmmx_mxmi(struct nvkm_mxm *mxm, u8 version)
{
u32 mxmi_args[] = { 0x494D584D /* MXMI */, version, 0 };
struct acpi_buffer args = { sizeof(mxmi_args), mxmi_args };
@@ -158,7 +156,7 @@ wmi_wmmx_mxmi(struct nouveau_mxm *mxm, u8 version)
}
static bool
-mxm_shadow_wmi(struct nouveau_mxm *mxm, u8 version)
+mxm_shadow_wmi(struct nvkm_mxm *mxm, u8 version)
{
u32 mxms_args[] = { 0x534D584D /* MXMS */, version, 0 };
struct acpi_buffer args = { sizeof(mxms_args), mxms_args };
@@ -186,7 +184,7 @@ mxm_shadow_wmi(struct nouveau_mxm *mxm, u8 version)
obj = retn.pointer;
if (obj->type == ACPI_TYPE_BUFFER) {
mxm->mxms = kmemdup(obj->buffer.pointer,
- obj->buffer.length, GFP_KERNEL);
+ obj->buffer.length, GFP_KERNEL);
}
kfree(obj);
@@ -196,7 +194,7 @@ mxm_shadow_wmi(struct nouveau_mxm *mxm, u8 version)
static struct mxm_shadow_h {
const char *name;
- bool (*exec)(struct nouveau_mxm *, u8 version);
+ bool (*exec)(struct nvkm_mxm *, u8 version);
} _mxm_shadow[] = {
{ "ROM", mxm_shadow_rom },
#if defined(CONFIG_ACPI)
@@ -209,7 +207,7 @@ static struct mxm_shadow_h {
};
static int
-mxm_shadow(struct nouveau_mxm *mxm, u8 version)
+mxm_shadow(struct nvkm_mxm *mxm, u8 version)
{
struct mxm_shadow_h *shadow = _mxm_shadow;
do {
@@ -225,19 +223,18 @@ mxm_shadow(struct nouveau_mxm *mxm, u8 version)
}
int
-nouveau_mxm_create_(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, int length, void **pobject)
+nvkm_mxm_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, int length, void **pobject)
{
- struct nouveau_device *device = nv_device(parent);
- struct nouveau_bios *bios = nouveau_bios(device);
- struct nouveau_mxm *mxm;
+ struct nvkm_device *device = nv_device(parent);
+ struct nvkm_bios *bios = nvkm_bios(device);
+ struct nvkm_mxm *mxm;
u8 ver, len;
u16 data;
int ret;
- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "MXM", "mxm",
- length, pobject);
+ ret = nvkm_subdev_create_(parent, engine, oclass, 0, "MXM", "mxm",
+ length, pobject);
mxm = *pobject;
if (ret)
return ret;
@@ -268,7 +265,7 @@ nouveau_mxm_create_(struct nouveau_object *parent,
mxms_version(mxm) >> 8, mxms_version(mxm) & 0xff);
mxms_foreach(mxm, 0, NULL, NULL);
- if (nouveau_boolopt(device->cfgopt, "NvMXMDCB", true))
+ if (nvkm_boolopt(device->cfgopt, "NvMXMDCB", true))
mxm->action |= MXM_SANITISE_DCB;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c
index 4bde7f7f7b81..a9b1d63fed58 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c
@@ -21,22 +21,20 @@
*
* Authors: Ben Skeggs
*/
-
-#include <subdev/mxm.h>
#include "mxms.h"
#define ROM16(x) le16_to_cpu(*(u16 *)&(x))
#define ROM32(x) le32_to_cpu(*(u32 *)&(x))
static u8 *
-mxms_data(struct nouveau_mxm *mxm)
+mxms_data(struct nvkm_mxm *mxm)
{
return mxm->mxms;
}
u16
-mxms_version(struct nouveau_mxm *mxm)
+mxms_version(struct nvkm_mxm *mxm)
{
u8 *mxms = mxms_data(mxm);
u16 version = (mxms[4] << 8) | mxms[5];
@@ -54,19 +52,19 @@ mxms_version(struct nouveau_mxm *mxm)
}
u16
-mxms_headerlen(struct nouveau_mxm *mxm)
+mxms_headerlen(struct nvkm_mxm *mxm)
{
return 8;
}
u16
-mxms_structlen(struct nouveau_mxm *mxm)
+mxms_structlen(struct nvkm_mxm *mxm)
{
return *(u16 *)&mxms_data(mxm)[6];
}
bool
-mxms_checksum(struct nouveau_mxm *mxm)
+mxms_checksum(struct nvkm_mxm *mxm)
{
u16 size = mxms_headerlen(mxm) + mxms_structlen(mxm);
u8 *mxms = mxms_data(mxm), sum = 0;
@@ -80,7 +78,7 @@ mxms_checksum(struct nouveau_mxm *mxm)
}
bool
-mxms_valid(struct nouveau_mxm *mxm)
+mxms_valid(struct nvkm_mxm *mxm)
{
u8 *mxms = mxms_data(mxm);
if (*(u32 *)mxms != 0x5f4d584d) {
@@ -95,8 +93,8 @@ mxms_valid(struct nouveau_mxm *mxm)
}
bool
-mxms_foreach(struct nouveau_mxm *mxm, u8 types,
- bool (*exec)(struct nouveau_mxm *, u8 *, void *), void *info)
+mxms_foreach(struct nvkm_mxm *mxm, u8 types,
+ bool (*exec)(struct nvkm_mxm *, u8 *, void *), void *info)
{
u8 *mxms = mxms_data(mxm);
u8 *desc = mxms + mxms_headerlen(mxm);
@@ -180,7 +178,7 @@ mxms_foreach(struct nouveau_mxm *mxm, u8 types,
}
void
-mxms_output_device(struct nouveau_mxm *mxm, u8 *pdata, struct mxms_odev *desc)
+mxms_output_device(struct nvkm_mxm *mxm, u8 *pdata, struct mxms_odev *desc)
{
u64 data = ROM32(pdata[0]);
if (mxms_version(mxm) >= 0x0300)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h
index 5e0be0c591ca..4ef804012d06 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h
@@ -1,5 +1,6 @@
#ifndef __NVMXM_MXMS_H__
#define __NVMXM_MXMS_H__
+#include <subdev/mxm.h>
struct mxms_odev {
u8 outp_type;
@@ -8,15 +9,14 @@ struct mxms_odev {
u8 dig_conn;
};
-void mxms_output_device(struct nouveau_mxm *, u8 *, struct mxms_odev *);
+void mxms_output_device(struct nvkm_mxm *, u8 *, struct mxms_odev *);
-u16 mxms_version(struct nouveau_mxm *);
-u16 mxms_headerlen(struct nouveau_mxm *);
-u16 mxms_structlen(struct nouveau_mxm *);
-bool mxms_checksum(struct nouveau_mxm *);
-bool mxms_valid(struct nouveau_mxm *);
-
-bool mxms_foreach(struct nouveau_mxm *, u8,
- bool (*)(struct nouveau_mxm *, u8 *, void *), void *);
+u16 mxms_version(struct nvkm_mxm *);
+u16 mxms_headerlen(struct nvkm_mxm *);
+u16 mxms_structlen(struct nvkm_mxm *);
+bool mxms_checksum(struct nvkm_mxm *);
+bool mxms_valid(struct nvkm_mxm *);
+bool mxms_foreach(struct nvkm_mxm *, u8,
+ bool (*)(struct nvkm_mxm *, u8 *, void *), void *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c
index fcaabe8456e3..42cac13ca629 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c
@@ -21,17 +21,15 @@
*
* Authors: Ben Skeggs
*/
+#include "mxms.h"
-#include <subdev/mxm.h>
#include <subdev/bios.h>
#include <subdev/bios/conn.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/mxm.h>
-#include "mxms.h"
-
struct nv50_mxm_priv {
- struct nouveau_mxm base;
+ struct nvkm_mxm base;
};
struct context {
@@ -40,7 +38,7 @@ struct context {
};
static bool
-mxm_match_tmds_partner(struct nouveau_mxm *mxm, u8 *data, void *info)
+mxm_match_tmds_partner(struct nvkm_mxm *mxm, u8 *data, void *info)
{
struct context *ctx = info;
struct mxms_odev desc;
@@ -53,9 +51,9 @@ mxm_match_tmds_partner(struct nouveau_mxm *mxm, u8 *data, void *info)
}
static bool
-mxm_match_dcb(struct nouveau_mxm *mxm, u8 *data, void *info)
+mxm_match_dcb(struct nvkm_mxm *mxm, u8 *data, void *info)
{
- struct nouveau_bios *bios = nouveau_bios(mxm);
+ struct nvkm_bios *bios = nvkm_bios(mxm);
struct context *ctx = info;
u64 desc = *(u64 *)data;
@@ -98,9 +96,9 @@ mxm_match_dcb(struct nouveau_mxm *mxm, u8 *data, void *info)
}
static int
-mxm_dcb_sanitise_entry(struct nouveau_bios *bios, void *data, int idx, u16 pdcb)
+mxm_dcb_sanitise_entry(struct nvkm_bios *bios, void *data, int idx, u16 pdcb)
{
- struct nouveau_mxm *mxm = data;
+ struct nvkm_mxm *mxm = data;
struct context ctx = { .outp = (u32 *)(bios->data + pdcb) };
u8 type, i2cidx, link, ver, len;
u8 *conn;
@@ -180,7 +178,7 @@ mxm_dcb_sanitise_entry(struct nouveau_bios *bios, void *data, int idx, u16 pdcb)
}
static bool
-mxm_show_unmatched(struct nouveau_mxm *mxm, u8 *data, void *info)
+mxm_show_unmatched(struct nvkm_mxm *mxm, u8 *data, void *info)
{
u64 desc = *(u64 *)data;
if ((desc & 0xf0) != 0xf0)
@@ -189,9 +187,9 @@ mxm_show_unmatched(struct nouveau_mxm *mxm, u8 *data, void *info)
}
static void
-mxm_dcb_sanitise(struct nouveau_mxm *mxm)
+mxm_dcb_sanitise(struct nvkm_mxm *mxm)
{
- struct nouveau_bios *bios = nouveau_bios(mxm);
+ struct nvkm_bios *bios = nvkm_bios(mxm);
u8 ver, hdr, cnt, len;
u16 dcb = dcb_table(bios, &ver, &hdr, &cnt, &len);
if (dcb == 0x0000 || ver != 0x40) {
@@ -204,14 +202,14 @@ mxm_dcb_sanitise(struct nouveau_mxm *mxm)
}
static int
-nv50_mxm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_mxm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_mxm_priv *priv;
int ret;
- ret = nouveau_mxm_create(parent, engine, oclass, &priv);
+ ret = nvkm_mxm_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -221,13 +219,13 @@ nv50_mxm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv50_mxm_oclass = {
.handle = NV_SUBDEV(MXM, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_mxm_ctor,
- .dtor = _nouveau_mxm_dtor,
- .init = _nouveau_mxm_init,
- .fini = _nouveau_mxm_fini,
+ .dtor = _nvkm_mxm_dtor,
+ .init = _nvkm_mxm_init,
+ .fini = _nvkm_mxm_fini,
},
};