staging: comedi: s626: remove RR7146 macro
This macro relies on a local variable having a specific name its also just a wrapper around a readl() call. Remove the macro and just call readl() directly. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
25f8fd5e11
commit
be008602e6
1 changed files with 43 additions and 51 deletions
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@ -169,10 +169,6 @@ static bool s626_mc_test(struct comedi_device *dev,
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return (val & cmd) ? true : false;
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}
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/* #define RR7146(REGARDS)
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readl((uint32_t)(devpriv->base_addr+(REGARDS))) */
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#define RR7146(REGARDS) readl(devpriv->base_addr+(REGARDS))
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#define BUGFIX_STREG(REGADRS) (REGADRS - 4)
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/* Write a time slot control record to TSL2. */
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@ -206,8 +202,8 @@ static void DEBItransfer(struct comedi_device *dev)
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while (!s626_mc_test(dev, MC2_UPLD_DEBI, P_MC2))
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;
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/* Wait until DEBI transfer is done. */
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while (RR7146(P_PSR) & PSR_DEBI_S)
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/* Wait until DEBI transfer is done */
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while (readl(devpriv->base_addr + P_PSR) & PSR_DEBI_S)
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;
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}
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@ -216,7 +212,6 @@ static void DEBItransfer(struct comedi_device *dev)
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static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr)
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{
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struct s626_private *devpriv = dev->private;
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uint16_t retval;
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/* Set up DEBI control register value in shadow RAM */
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writel(DEBI_CMD_RDWORD | addr, devpriv->base_addr + P_DEBICMD);
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@ -224,11 +219,7 @@ static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr)
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/* Execute the DEBI transfer. */
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DEBItransfer(dev);
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/* Fetch target register value. */
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retval = (uint16_t) RR7146(P_DEBIAD);
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/* Return register value. */
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return retval;
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return readl(devpriv->base_addr + P_DEBIAD);
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}
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/* Write a value to a gate array register. */
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@ -252,19 +243,17 @@ static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask,
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uint16_t wdata)
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{
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struct s626_private *devpriv = dev->private;
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unsigned int val;
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/* Copy target gate array register into P_DEBIAD register */
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writel(DEBI_CMD_RDWORD | addr, devpriv->base_addr + P_DEBICMD);
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/* Set up DEBI control reg value in shadow RAM. */
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DEBItransfer(dev); /* Execute the DEBI Read transfer. */
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DEBItransfer(dev);
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/* Write back the modified image */
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writel(DEBI_CMD_WRWORD | addr, devpriv->base_addr + P_DEBICMD);
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/* Set up DEBI control reg value in shadow RAM */
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writel(wdata | ((uint16_t) RR7146(P_DEBIAD) & mask),
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devpriv->base_addr + P_DEBIAD);
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/* Modify the register image. */
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DEBItransfer(dev); /* Execute the DEBI Write transfer. */
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val = readl(devpriv->base_addr + P_DEBIAD);
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val &= mask;
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val |= wdata;
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writel(val, devpriv->base_addr + P_DEBIAD);
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DEBItransfer(dev);
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}
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/* ************** EEPROM ACCESS FUNCTIONS ************** */
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@ -272,6 +261,7 @@ static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask,
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static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val)
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{
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struct s626_private *devpriv = dev->private;
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unsigned int ctrl;
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/* Write I2C command to I2C Transfer Control shadow register */
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writel(val, devpriv->base_addr + P_I2CCTRL);
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@ -284,20 +274,19 @@ static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val)
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while (!s626_mc_test(dev, MC2_UPLD_IIC, P_MC2))
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;
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/* Wait until I2C bus transfer is finished or an error occurs. */
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while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY)
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;
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/* Return non-zero if I2C error occurred. */
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return RR7146(P_I2CCTRL) & I2C_ERR;
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/* Wait until I2C bus transfer is finished or an error occurs */
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do {
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ctrl = readl(devpriv->base_addr + P_I2CCTRL);
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} while ((ctrl & (I2C_BUSY | I2C_ERR)) == I2C_BUSY);
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/* Return non-zero if I2C error occurred */
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return ctrl & I2C_ERR;
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}
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/* Read uint8_t from EEPROM. */
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static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr)
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{
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struct s626_private *devpriv = dev->private;
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uint8_t rtnval;
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/* Send EEPROM target address. */
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if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CW)
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@ -325,9 +314,8 @@ static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr)
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/* Abort function and declare error if handshake failed. */
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return 0;
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}
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/* Return copy of EEPROM value. */
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rtnval = (uint8_t) (RR7146(P_I2CCTRL) >> 16);
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return rtnval;
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return (readl(devpriv->base_addr + P_I2CCTRL) >> 16) & 0xff;
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}
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/* *********** DAC FUNCTIONS *********** */
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@ -393,7 +381,7 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* Done by polling the DMAC enable flag; this flag is automatically
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* cleared when the transfer has finished.
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*/
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while ((RR7146(P_MC1) & MC1_A2OUT) != 0)
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while (readl(devpriv->base_addr + P_MC1) & MC1_A2OUT)
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;
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/* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
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@ -411,7 +399,7 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* finished transferring the DAC's data DWORD from the output FIFO
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* to the output buffer register.
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*/
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while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0)
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while (!(readl(devpriv->base_addr + P_SSR) & SSR_AF2_OUT))
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;
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/* Set up to trap execution at slot 0 when the TSL sequencer cycles
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@ -442,14 +430,14 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If
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* the TSL has not yet finished executing slot 5 ...
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*/
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if ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) {
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if (readl(devpriv->base_addr + P_FB_BUFFER2) & 0xff000000) {
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/* The trap was set on time and we are still executing somewhere
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* in slots 2-5, so we now wait for slot 0 to execute and trap
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* TSL execution. This is detected when FB_BUFFER2 MSB changes
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* from 0xFF to 0x00, which slot 0 causes to happen by shifting
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* out/in on SD2 the 0x00 that is always referenced by slot 5.
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*/
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while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0)
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while (readl(devpriv->base_addr + P_FB_BUFFER2) & 0xff000000)
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;
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}
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/* Either (1) we were too late setting the slot 0 trap; the TSL
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@ -466,7 +454,7 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* the next DAC write. This is detected when FB_BUFFER2 MSB changes
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* from 0x00 to 0xFF.
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*/
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while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0)
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while (!(readl(devpriv->base_addr + P_FB_BUFFER2) & 0xff000000))
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;
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}
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@ -1173,6 +1161,7 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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uint16_t range = CR_RANGE(insn->chanspec);
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uint16_t AdcSpec = 0;
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uint32_t GpioImage;
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int tmp;
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int n;
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/* interrupt call test */
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@ -1200,8 +1189,8 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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/* Delay 10 microseconds for analog input settling. */
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udelay(10);
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/* Start ADC by pulsing GPIO1 low. */
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GpioImage = RR7146(P_GPIO);
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/* Start ADC by pulsing GPIO1 low */
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GpioImage = readl(devpriv->base_addr + P_GPIO);
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/* Assert ADC Start command */
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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/* and stretch it out */
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@ -1214,13 +1203,15 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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/* ADC not busy) and for data from previous conversion to */
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/* shift into FB BUFFER 1 register. */
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/* Wait for ADC done. */
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while (!(RR7146(P_PSR) & PSR_GPIO2))
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/* Wait for ADC done */
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while (!(readl(devpriv->base_addr + P_PSR) & PSR_GPIO2))
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;
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/* Fetch ADC data. */
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if (n != 0)
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data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
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/* Fetch ADC data */
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if (n != 0) {
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tmp = readl(devpriv->base_addr + P_FB_BUFFER1);
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data[n - 1] = s626_ai_reg_to_uint(tmp);
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}
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/* Allow the ADC to stabilize for 4 microseconds before
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* starting the next (final) conversion. This delay is
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@ -1235,8 +1226,7 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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/* Start a dummy conversion to cause the data from the
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* previous conversion to be shifted in. */
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GpioImage = RR7146(P_GPIO);
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GpioImage = readl(devpriv->base_addr + P_GPIO);
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/* Assert ADC Start command */
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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/* and stretch it out */
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@ -1247,15 +1237,17 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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/* Wait for the data to arrive in FB BUFFER 1 register. */
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/* Wait for ADC done. */
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while (!(RR7146(P_PSR) & PSR_GPIO2))
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/* Wait for ADC done */
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while (!(readl(devpriv->base_addr + P_PSR) & PSR_GPIO2))
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;
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/* Fetch ADC data from audio interface's input shift register. */
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/* Fetch ADC data. */
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if (n != 0)
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data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
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/* Fetch ADC data */
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if (n != 0) {
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tmp = readl(devpriv->base_addr + P_FB_BUFFER1);
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data[n - 1] = s626_ai_reg_to_uint(tmp);
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}
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return n;
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}
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@ -2422,7 +2414,7 @@ static void s626_initialize(struct comedi_device *dev)
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*/
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writel(I2C_CLKSEL | I2C_ABORT, devpriv->base_addr + P_I2CSTAT);
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s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
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while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
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while (!(readl(devpriv->base_addr + P_MC2) & MC2_UPLD_IIC))
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;
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/*
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