ARM: dts: msm: Modify QRD interposer dts file for msm8998
Update regulators for clocks and usb phy. CRs-Fixed: 1096674 Change-Id: Ib205ccebaec612fd9d1d6bb1a02a4f14be8f21c1 Signed-off-by: Zhenhua Huang <zhenhuah@codeaurora.org>
This commit is contained in:
Zhenhua Huang
Gerrit - the friendly Code Review server
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69352ff8b4
commit
be5a91fa22
2 changed files with 55 additions and 153 deletions
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@ -14,6 +14,9 @@
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/dts-v1/;
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/dts-v1/;
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#include "msm8998-v2.1-interposer-msmfalcon-qrd.dtsi"
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#include "msm8998-v2.1-interposer-msmfalcon-qrd.dtsi"
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#include "msm8998-interposer-pmfalcon.dtsi"
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#include "msm8998-interposer-msmfalcon-audio.dtsi"
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#include "msm8998-interposer-camera-sensor-mtp.dtsi"
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/ {
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/ {
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model =
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model =
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@ -41,174 +44,72 @@
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};
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};
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&clock_gcc {
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&clock_gcc {
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/delete-property/vdd_dig-supply;
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vdd_dig-supply = <&pm2falcon_s3_level>;
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/delete-property/vdd_dig_ao-supply;
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vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>;
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};
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};
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&clock_mmss {
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&clock_mmss {
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/delete-property/vdd_dig-supply;
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vdd_dig-supply = <&pm2falcon_s3_level>;
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/delete-property/vdd_mmsscc_mx-supply;
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vdd_mmsscc_mx-supply = <&pm2falcon_s5_level>;
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};
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};
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&clock_gpu {
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&clock_gpu {
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/delete-property/vdd_dig-supply;
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vdd_dig-supply = <&pm2falcon_s3_level>;
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};
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};
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&clock_gfx {
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&clock_gfx {
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/delete-property/vdd_mx-supply;
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/* GFX Rail = CX */
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/delete-property/vdd_gpu_mx-supply;
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vdd_gpucc-supply = <&pm2falcon_s3_level>;
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vdd_mx-supply = <&pm2falcon_s5_level>;
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vdd_gpu_mx-supply = <&pm2falcon_s5_level>;
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qcom,gfxfreq-speedbin0 =
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< 0 0 0 >,
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< 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS
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RPM_SMD_REGULATOR_LEVEL_SVS >,
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< 257000000 RPM_SMD_REGULATOR_LEVEL_LOW_SVS
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RPM_SMD_REGULATOR_LEVEL_SVS >,
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< 342000000 RPM_SMD_REGULATOR_LEVEL_SVS
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RPM_SMD_REGULATOR_LEVEL_SVS >,
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< 414000000 RPM_SMD_REGULATOR_LEVEL_SVS_PLUS
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RPM_SMD_REGULATOR_LEVEL_SVS >,
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< 515000000 RPM_SMD_REGULATOR_LEVEL_NOM
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RPM_SMD_REGULATOR_LEVEL_NOM >,
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< 596000000 RPM_SMD_REGULATOR_LEVEL_NOM_PLUS
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RPM_SMD_REGULATOR_LEVEL_NOM >,
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< 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO
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RPM_SMD_REGULATOR_LEVEL_TURBO >,
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< 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO
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RPM_SMD_REGULATOR_LEVEL_TURBO >;
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qcom,gfxfreq-mx-speedbin0 =
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< 0 0 >,
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< 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
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< 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
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< 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
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< 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
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< 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
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< 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
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< 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >,
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< 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >;
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};
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};
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&pcie0 {
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&gdsc_gpu_gx {
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/delete-property/vreg-1.8-supply;
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clock-names = "core_root_clk";
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/delete-property/vreg-0.9-supply;
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clocks = <&clock_gfx clk_gfx3d_clk_src>;
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/delete-property/vreg-cx-supply;
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qcom,force-enable-root-clk;
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/* GFX Rail = CX */
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parent-supply = <&pm2falcon_s3_level>;
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status = "ok";
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};
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};
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&qusb_phy0 {
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&qusb_phy0 {
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/delete-property/vdd-supply;
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vdd-supply = <&pm2falcon_l1>;
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/delete-property/vdda18-supply;
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vdda18-supply = <&pmfalcon_l10>;
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/delete-property/vdda33-supply;
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qcom,vdd-voltage-level = <0 925000 925000>;
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vdda33-supply = <&pm2falcon_l7>;
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};
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};
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&ssphy {
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&ssphy {
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/delete-property/vdd-supply;
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vdd-supply = <&pm2falcon_l1>;
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/delete-property/core-supply;
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qcom,vdd-voltage-level = <0 925000 925000>;
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core-supply = <&pmfalcon_l1>;
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};
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};
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&usb3 {
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/delete-property/extcon;
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};
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&mdss_dsi {
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/delete-property/vdda-1p2-supply;
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/delete-property/vdda-0p9-supply;
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};
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&mdss_dsi0 {
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/delete-property/wqhd-vddio-supply;
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/delete-property/lab-supply;
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/delete-property/ibb-supply;
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};
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&mdss_dsi1 {
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/delete-property/wqhd-vddio-supply;
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/delete-property/lab-supply;
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/delete-property/ibb-supply;
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};
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&mdss_hdmi_pll {
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/delete-property/vdda-pll-supply;
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/delete-property/vdda-phy-supply;
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};
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&mdss_dp_ctrl {
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/delete-property/vdda-1p2-supply;
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/delete-property/vdda-0p9-supply;
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/delete-property/qcom,dp-usbpd-detection;
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};
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&apc0_cpr {
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/* disable aging and closed-loop */
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/delete-property/vdd-supply;
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/delete-property/qcom,cpr-enable;
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/delete-property/qcom,cpr-hw-closed-loop;
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/delete-property/qcom,cpr-aging-ref-voltage;
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};
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&apc0_pwrcl_vreg {
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/delete-property/qcom,cpr-aging-max-voltage-adjustment;
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/delete-property/qcom,cpr-aging-ref-corner;
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/delete-property/qcom,cpr-aging-ro-scaling-factor;
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/delete-property/qcom,allow-aging-voltage-adjustment;
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/delete-property/qcom,allow-aging-open-loop-voltage-adjustment;
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};
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&apc1_cpr {
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/* disable aging and closed-loop */
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/delete-property/vdd-supply;
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/delete-property/qcom,cpr-enable;
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/delete-property/qcom,cpr-hw-closed-loop;
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/delete-property/qcom,cpr-aging-ref-voltage;
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};
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&apc1_perfcl_vreg {
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/delete-property/qcom,cpr-aging-max-voltage-adjustment;
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/delete-property/qcom,cpr-aging-ref-corner;
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/delete-property/qcom,cpr-aging-ro-scaling-factor;
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/delete-property/qcom,allow-aging-voltage-adjustment;
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/delete-property/qcom,allow-aging-open-loop-voltage-adjustment;
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};
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&gfx_cpr {
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reg = <0x05061000 0x4000>,
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<0x00784000 0x1000>;
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reg-names = "cpr_ctrl", "fuse_base";
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/* disable aging and closed-loop */
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/delete-property/vdd-supply;
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/delete-property/qcom,cpr-enable;
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/delete-property/qcom,cpr-aging-ref-voltage;
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/delete-property/qcom,cpr-aging-allowed-reg-mask;
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/delete-property/qcom,cpr-aging-allowed-reg-value;
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};
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&gfx_vreg {
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/delete-property/qcom,cpr-aging-max-voltage-adjustment;
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/delete-property/qcom,cpr-aging-ref-corner;
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/delete-property/qcom,cpr-aging-ro-scaling-factor;
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/delete-property/qcom,allow-aging-voltage-adjustment;
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/delete-property/qcom,allow-aging-open-loop-voltage-adjustment;
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};
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&clock_audio {
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/delete-property/qcom,audio-ref-clk-gpio;
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};
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&soc {
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/delete-node/qcom,csid@ca30000;
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/delete-node/qcom,csid@ca30400;
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/delete-node/qcom,csid@ca30800;
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/delete-node/qcom,csid@ca30c00;
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/delete-node/qcom,lpass@17300000;
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/delete-node/qcom,mss@4080000;
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/delete-node/qcom,spss@1d00000;
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/delete-node/qcom,bcl;
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/delete-node/qcom,msm-thermal;
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/delete-node/qcom,ssc@5c00000;
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/delete-node/qcom,icnss@18800000;
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/delete-node/qcom,wil6210;
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/delete-node/qcom,rpm-smd;
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/delete-node/qcom,spmi@800f000;
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rpm_bus: qcom,rpm-smd {
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compatible = "qcom,rpm-glink";
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qcom,glink-edge = "rpm";
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rpm-channel-name = "rpm_requests";
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};
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spmi_bus: qcom,spmi@800f000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x800f000 0x1000>,
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<0x8400000 0x1000000>,
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<0x9400000 0x1000000>,
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<0xa400000 0x220000>,
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<0x800a000 0x3000>;
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reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
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interrupt-names = "periph_irq";
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interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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cell-index = <0>;
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};
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};
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#include "msm-pmfalcon.dtsi"
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#include "msm-pm2falcon.dtsi"
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#include "msmfalcon-regulator.dtsi"
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@ -12,6 +12,7 @@
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "msm8998-v2.1-interposer-msmfalcon.dtsi"
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#include "msm8998-v2.1-interposer-msmfalcon.dtsi"
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#include "msm8998-camera-sensor-mtp.dtsi"
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/ {
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/ {
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bluetooth: bt_wcn3990 {
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bluetooth: bt_wcn3990 {
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