Merge "power: qpnp-fg-gen3: synchronize ESR extraction control configuration"
This commit is contained in:
commit
bf0fbeead5
2 changed files with 38 additions and 12 deletions
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@ -403,6 +403,7 @@ struct fg_chip {
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struct mutex bus_lock;
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struct mutex bus_lock;
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struct mutex sram_rw_lock;
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struct mutex sram_rw_lock;
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struct mutex charge_full_lock;
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struct mutex charge_full_lock;
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struct mutex qnovo_esr_ctrl_lock;
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u32 batt_soc_base;
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u32 batt_soc_base;
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u32 batt_info_base;
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u32 batt_info_base;
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u32 mem_if_base;
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u32 mem_if_base;
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@ -435,6 +436,7 @@ struct fg_chip {
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bool esr_flt_cold_temp_en;
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bool esr_flt_cold_temp_en;
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bool slope_limit_en;
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bool slope_limit_en;
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bool use_ima_single_mode;
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bool use_ima_single_mode;
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bool qnovo_enable;
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struct completion soc_update;
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struct completion soc_update;
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struct completion soc_ready;
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struct completion soc_ready;
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struct delayed_work profile_load_work;
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struct delayed_work profile_load_work;
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@ -3298,20 +3298,21 @@ static int fg_force_esr_meas(struct fg_chip *chip)
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int rc;
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int rc;
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int esr_uohms;
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int esr_uohms;
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mutex_lock(&chip->qnovo_esr_ctrl_lock);
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/* force esr extraction enable */
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/* force esr extraction enable */
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rc = fg_sram_masked_write(chip, ESR_EXTRACTION_ENABLE_WORD,
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rc = fg_sram_masked_write(chip, ESR_EXTRACTION_ENABLE_WORD,
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ESR_EXTRACTION_ENABLE_OFFSET, BIT(0), BIT(0),
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ESR_EXTRACTION_ENABLE_OFFSET, BIT(0), BIT(0),
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FG_IMA_DEFAULT);
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FG_IMA_DEFAULT);
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if (rc < 0) {
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if (rc < 0) {
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pr_err("failed to enable esr extn rc=%d\n", rc);
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pr_err("failed to enable esr extn rc=%d\n", rc);
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return rc;
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goto out;
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}
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}
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rc = fg_masked_write(chip, BATT_INFO_QNOVO_CFG(chip),
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rc = fg_masked_write(chip, BATT_INFO_QNOVO_CFG(chip),
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LD_REG_CTRL_BIT, 0);
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LD_REG_CTRL_BIT, 0);
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if (rc < 0) {
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if (rc < 0) {
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pr_err("Error in configuring qnovo_cfg rc=%d\n", rc);
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pr_err("Error in configuring qnovo_cfg rc=%d\n", rc);
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return rc;
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goto out;
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}
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}
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rc = fg_masked_write(chip, BATT_INFO_TM_MISC1(chip),
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rc = fg_masked_write(chip, BATT_INFO_TM_MISC1(chip),
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@ -3319,24 +3320,36 @@ static int fg_force_esr_meas(struct fg_chip *chip)
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ESR_REQ_CTL_BIT | ESR_REQ_CTL_EN_BIT);
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ESR_REQ_CTL_BIT | ESR_REQ_CTL_EN_BIT);
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if (rc < 0) {
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if (rc < 0) {
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pr_err("Error in configuring force ESR rc=%d\n", rc);
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pr_err("Error in configuring force ESR rc=%d\n", rc);
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return rc;
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goto out;
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}
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}
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/*
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* Release and grab the lock again after 1.5 seconds so that prepare
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* callback can succeed if the request comes in between.
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*/
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mutex_unlock(&chip->qnovo_esr_ctrl_lock);
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/* wait 1.5 seconds for hw to measure ESR */
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/* wait 1.5 seconds for hw to measure ESR */
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msleep(1500);
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msleep(1500);
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mutex_lock(&chip->qnovo_esr_ctrl_lock);
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rc = fg_masked_write(chip, BATT_INFO_TM_MISC1(chip),
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rc = fg_masked_write(chip, BATT_INFO_TM_MISC1(chip),
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ESR_REQ_CTL_BIT | ESR_REQ_CTL_EN_BIT,
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ESR_REQ_CTL_BIT | ESR_REQ_CTL_EN_BIT,
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0);
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0);
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if (rc < 0) {
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if (rc < 0) {
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pr_err("Error in restoring force ESR rc=%d\n", rc);
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pr_err("Error in restoring force ESR rc=%d\n", rc);
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return rc;
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goto out;
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}
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}
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/* If qnovo is disabled, then leave ESR extraction enabled */
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if (!chip->qnovo_enable)
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goto done;
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rc = fg_masked_write(chip, BATT_INFO_QNOVO_CFG(chip),
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rc = fg_masked_write(chip, BATT_INFO_QNOVO_CFG(chip),
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LD_REG_CTRL_BIT, LD_REG_CTRL_BIT);
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LD_REG_CTRL_BIT, LD_REG_CTRL_BIT);
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if (rc < 0) {
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if (rc < 0) {
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pr_err("Error in restoring qnovo_cfg rc=%d\n", rc);
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pr_err("Error in restoring qnovo_cfg rc=%d\n", rc);
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return rc;
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goto out;
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}
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}
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/* force esr extraction disable */
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/* force esr extraction disable */
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@ -3345,36 +3358,46 @@ static int fg_force_esr_meas(struct fg_chip *chip)
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FG_IMA_DEFAULT);
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FG_IMA_DEFAULT);
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if (rc < 0) {
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if (rc < 0) {
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pr_err("failed to disable esr extn rc=%d\n", rc);
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pr_err("failed to disable esr extn rc=%d\n", rc);
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return rc;
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goto out;
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}
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}
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done:
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fg_get_battery_resistance(chip, &esr_uohms);
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fg_get_battery_resistance(chip, &esr_uohms);
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fg_dbg(chip, FG_STATUS, "ESR uohms = %d\n", esr_uohms);
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fg_dbg(chip, FG_STATUS, "ESR uohms = %d\n", esr_uohms);
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out:
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mutex_unlock(&chip->qnovo_esr_ctrl_lock);
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return rc;
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return rc;
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}
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}
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static int fg_prepare_for_qnovo(struct fg_chip *chip, int qnovo_enable)
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static int fg_prepare_for_qnovo(struct fg_chip *chip, int qnovo_enable)
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{
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{
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int rc;
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int rc = 0;
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mutex_lock(&chip->qnovo_esr_ctrl_lock);
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/* force esr extraction disable when qnovo enables */
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/* force esr extraction disable when qnovo enables */
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rc = fg_sram_masked_write(chip, ESR_EXTRACTION_ENABLE_WORD,
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rc = fg_sram_masked_write(chip, ESR_EXTRACTION_ENABLE_WORD,
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ESR_EXTRACTION_ENABLE_OFFSET,
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ESR_EXTRACTION_ENABLE_OFFSET,
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BIT(0), qnovo_enable ? 0 : BIT(0),
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BIT(0), qnovo_enable ? 0 : BIT(0),
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FG_IMA_DEFAULT);
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FG_IMA_DEFAULT);
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if (rc < 0)
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if (rc < 0) {
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pr_err("Error in configuring esr extraction rc=%d\n", rc);
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pr_err("Error in configuring esr extraction rc=%d\n", rc);
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goto out;
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}
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rc = fg_masked_write(chip, BATT_INFO_QNOVO_CFG(chip),
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rc = fg_masked_write(chip, BATT_INFO_QNOVO_CFG(chip),
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LD_REG_CTRL_BIT,
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LD_REG_CTRL_BIT,
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qnovo_enable ? LD_REG_CTRL_BIT : 0);
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qnovo_enable ? LD_REG_CTRL_BIT : 0);
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if (rc < 0) {
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if (rc < 0) {
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pr_err("Error in configuring qnovo_cfg rc=%d\n", rc);
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pr_err("Error in configuring qnovo_cfg rc=%d\n", rc);
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return rc;
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goto out;
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}
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}
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fg_dbg(chip, FG_STATUS, "Prepared for Qnovo\n");
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return 0;
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fg_dbg(chip, FG_STATUS, "%s for Qnovo\n",
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qnovo_enable ? "Prepared" : "Unprepared");
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chip->qnovo_enable = qnovo_enable;
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out:
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mutex_unlock(&chip->qnovo_esr_ctrl_lock);
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return rc;
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}
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}
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static void ttf_work(struct work_struct *work)
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static void ttf_work(struct work_struct *work)
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@ -5006,6 +5029,7 @@ static int fg_gen3_probe(struct platform_device *pdev)
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mutex_init(&chip->cl.lock);
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mutex_init(&chip->cl.lock);
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mutex_init(&chip->ttf.lock);
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mutex_init(&chip->ttf.lock);
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mutex_init(&chip->charge_full_lock);
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mutex_init(&chip->charge_full_lock);
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mutex_init(&chip->qnovo_esr_ctrl_lock);
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init_completion(&chip->soc_update);
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init_completion(&chip->soc_update);
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init_completion(&chip->soc_ready);
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init_completion(&chip->soc_ready);
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INIT_DELAYED_WORK(&chip->profile_load_work, profile_load_work);
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INIT_DELAYED_WORK(&chip->profile_load_work, profile_load_work);
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