From b858dc4085f1387e0a8e26e8fd4fb30561e3f442 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 15 Dec 2016 14:58:47 +0530 Subject: [PATCH] clk: qcom: mmcc: Update the DSI PLL parent names The byte and pixel clocks RCG sources from their dsi byte/pixel PLLs, update the parent names so that those parents could be requested. Change-Id: Ie92df31a5cdfa176e872d721a84475a37172a2dd Signed-off-by: Taniya Das --- drivers/clk/qcom/mmcc-msmfalcon.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msmfalcon.c b/drivers/clk/qcom/mmcc-msmfalcon.c index 1d874f6db464..ef4c8c264078 100644 --- a/drivers/clk/qcom/mmcc-msmfalcon.c +++ b/drivers/clk/qcom/mmcc-msmfalcon.c @@ -112,8 +112,8 @@ static const struct parent_map mmcc_parent_map_1[] = { static const char * const mmcc_parent_names_1[] = { "xo", - "dsi0_phy_pll_out_byteclk", - "dsi1_phy_pll_out_byteclk", + "dsi0pll_byte_clk_mux", + "dsi1pll_byte_clk_mux", "core_bi_pll_test_se", }; @@ -240,8 +240,8 @@ static const struct parent_map mmcc_parent_map_8[] = { static const char * const mmcc_parent_names_8[] = { "xo", - "dsi0_phy_pll_out_dsiclk", - "dsi1_phy_pll_out_dsiclk", + "dsi0pll_pixel_clk_mux", + "dsi1pll_pixel_clk_mux", "core_bi_pll_test_se", };