Merge "clk: mdss: adjust PLL disable sequence to avoid glitch"
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1 changed files with 100 additions and 12 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -38,41 +38,76 @@
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/* Register Offsets from PLL base address */
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#define PLL_ANALOG_CONTROLS_ONE 0x000
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#define PLL_ANALOG_CONTROLS_TWO 0x004
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#define PLL_INT_LOOP_SETTINGS 0x008
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#define PLL_INT_LOOP_SETTINGS_TWO 0x00c
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#define PLL_ANALOG_CONTROLS_THREE 0x010
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#define PLL_DSM_DIVIDER 0x01c
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#define PLL_ANALOG_CONTROLS_FOUR 0x014
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#define PLL_INT_LOOP_CONTROLS 0x018
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#define PLL_DSM_DIVIDER 0x01c
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#define PLL_FEEDBACK_DIVIDER 0x020
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#define PLL_SYSTEM_MUXES 0x024
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#define PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x028
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#define PLL_CMODE 0x02c
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#define PLL_CALIBRATION_SETTINGS 0x030
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#define PLL_BAND_SEL_CAL_TIMER_LOW 0x034
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#define PLL_BAND_SEL_CAL_TIMER_HIGH 0x038
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#define PLL_BAND_SEL_CAL_SETTINGS 0x03c
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#define PLL_BAND_SEL_MIN 0x040
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#define PLL_BAND_SEL_MAX 0x044
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#define PLL_BAND_SEL_PFILT 0x048
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#define PLL_BAND_SEL_IFILT 0x04c
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#define PLL_BAND_SEL_CAL_SETTINGS_TWO 0x050
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#define PLL_BAND_SEL_CAL_SETTINGS_THREE 0x054
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#define PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x058
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#define PLL_BAND_SEL_ICODE_HIGH 0x05c
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#define PLL_BAND_SEL_ICODE_LOW 0x060
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#define PLL_FREQ_DETECT_SETTINGS_ONE 0x064
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#define PLL_PFILT 0x07c
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#define PLL_IFILT 0x080
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#define PLL_GAIN 0x084
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#define PLL_ICODE_LOW 0x088
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#define PLL_ICODE_HIGH 0x08c
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#define PLL_LOCKDET 0x090
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#define PLL_OUTDIV 0x094
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#define PLL_CORE_OVERRIDE 0x0a4
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#define PLL_FASTLOCK_CONTROL 0x098
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#define PLL_PASS_OUT_OVERRIDE_ONE 0x09c
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#define PLL_PASS_OUT_OVERRIDE_TWO 0x0a0
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#define PLL_CORE_OVERRIDE 0x0a4
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#define PLL_CORE_INPUT_OVERRIDE 0x0a8
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#define PLL_RATE_CHANGE 0x0ac
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#define PLL_PLL_DIGITAL_TIMERS 0x0b0
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#define PLL_PLL_DIGITAL_TIMERS_TWO 0x0b4
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#define PLL_DEC_FRAC_MUXES 0x0c8
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#define PLL_DECIMAL_DIV_START_1 0x0cc
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#define PLL_FRAC_DIV_START_LOW_1 0x0d0
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#define PLL_FRAC_DIV_START_MID_1 0x0d4
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#define PLL_FRAC_DIV_START_HIGH_1 0x0d8
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#define PLL_MASH_CONTROL 0x0ec
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#define PLL_SSC_MUX_CONTROL 0x108
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#define PLL_SSC_STEPSIZE_LOW_1 0x10c
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#define PLL_SSC_STEPSIZE_HIGH_1 0x110
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#define PLL_SSC_DIV_PER_LOW_1 0x114
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#define PLL_SSC_DIV_PER_HIGH_1 0x118
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#define PLL_SSC_DIV_ADJPER_LOW_1 0x11c
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#define PLL_SSC_DIV_ADJPER_HIGH_1 0x120
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#define PLL_SSC_CONTROL 0x13c
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#define PLL_PLL_OUTDIV_RATE 0x140
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#define PLL_SSC_CONTROL 0x13c
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#define PLL_PLL_OUTDIV_RATE 0x140
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#define PLL_PLL_LOCKDET_RATE_1 0x144
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#define PLL_PLL_PROP_GAIN_RATE_1 0x14c
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#define PLL_PLL_BAND_SET_RATE_1 0x154
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#define PLL_PLL_INT_GAIN_IFILT_BAND_1 0x15c
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#define PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x164
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#define PLL_PLL_LOCK_OVERRIDE 0x180
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#define PLL_PLL_LOCK_DELAY 0x184
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#define PLL_CLOCK_INVERTERS 0x18c
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#define PLL_COMMON_STATUS_ONE 0x1a0
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#define PLL_FASTLOCK_EN_BAND 0x16c
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#define PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x17c
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#define PLL_PLL_LOCK_OVERRIDE 0x180
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#define PLL_PLL_LOCK_DELAY 0x184
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#define PLL_PLL_LOCK_MIN_DELAY 0x188
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#define PLL_CLOCK_INVERTERS 0x18c
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#define PLL_SPARE_AND_JPC_OVERRIDES 0x190
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#define PLL_BIAS_CONTROL_1 0x194
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#define PLL_BIAS_CONTROL_2 0x198
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#define PLL_ALOG_OBSV_BUS_CTRL_1 0x19c
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#define PLL_COMMON_STATUS_ONE 0x1a0
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/* Register Offsets from PHY base address */
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#define PHY_CMN_CLK_CFG0 0x010
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@ -384,6 +419,49 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_8998 *pll,
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MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x3f);
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}
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static void dsi_pll_init_val(struct mdss_pll_resources *rsc)
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{
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void __iomem *pll_base = rsc->pll_base;
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MDSS_PLL_REG_W(pll_base, PLL_CORE_INPUT_OVERRIDE, 0x10);
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MDSS_PLL_REG_W(pll_base, PLL_INT_LOOP_SETTINGS, 0x3f);
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MDSS_PLL_REG_W(pll_base, PLL_INT_LOOP_SETTINGS_TWO, 0x0);
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MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FOUR, 0x0);
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MDSS_PLL_REG_W(pll_base, PLL_INT_LOOP_CONTROLS, 0x80);
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MDSS_PLL_REG_W(pll_base, PLL_FREQ_UPDATE_CONTROL_OVERRIDES, 0x0);
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MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_TIMER_LOW, 0x0);
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MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_TIMER_HIGH, 0x02);
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MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS, 0x82);
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MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_MIN, 0x00);
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MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_MAX, 0xff);
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MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_PFILT, 0x00);
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MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_IFILT, 0x00);
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MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS_TWO, 0x25);
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MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS_FOUR, 0x4f);
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MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_ICODE_HIGH, 0x0a);
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MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_ICODE_LOW, 0x0);
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MDSS_PLL_REG_W(pll_base, PLL_GAIN, 0x42);
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MDSS_PLL_REG_W(pll_base, PLL_ICODE_LOW, 0x00);
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MDSS_PLL_REG_W(pll_base, PLL_ICODE_HIGH, 0x00);
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MDSS_PLL_REG_W(pll_base, PLL_LOCKDET, 0x30);
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MDSS_PLL_REG_W(pll_base, PLL_FASTLOCK_CONTROL, 0x04);
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MDSS_PLL_REG_W(pll_base, PLL_PASS_OUT_OVERRIDE_ONE, 0x00);
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MDSS_PLL_REG_W(pll_base, PLL_PASS_OUT_OVERRIDE_TWO, 0x00);
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MDSS_PLL_REG_W(pll_base, PLL_RATE_CHANGE, 0x01);
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MDSS_PLL_REG_W(pll_base, PLL_PLL_DIGITAL_TIMERS, 0x08);
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MDSS_PLL_REG_W(pll_base, PLL_DEC_FRAC_MUXES, 0x00);
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MDSS_PLL_REG_W(pll_base, PLL_MASH_CONTROL, 0x03);
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MDSS_PLL_REG_W(pll_base, PLL_SSC_MUX_CONTROL, 0x0);
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MDSS_PLL_REG_W(pll_base, PLL_SSC_CONTROL, 0x0);
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MDSS_PLL_REG_W(pll_base, PLL_FASTLOCK_EN_BAND, 0x03);
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MDSS_PLL_REG_W(pll_base, PLL_FREQ_TUNE_ACCUM_INIT_MUX, 0x0);
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MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_MIN_DELAY, 0x19);
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MDSS_PLL_REG_W(pll_base, PLL_SPARE_AND_JPC_OVERRIDES, 0x0);
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MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_1, 0x40);
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MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_2, 0x20);
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MDSS_PLL_REG_W(pll_base, PLL_ALOG_OBSV_BUS_CTRL_1, 0x0);
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}
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static void dsi_pll_commit(struct dsi_pll_8998 *pll,
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struct mdss_pll_resources *rsc)
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{
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@ -440,6 +518,8 @@ static int vco_8998_set_rate(struct clk *c, unsigned long rate)
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return rc;
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}
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dsi_pll_init_val(rsc);
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dsi_pll_setup_config(pll, rsc);
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dsi_pll_calc_dec_frac(pll, rsc);
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@ -554,7 +634,6 @@ error:
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static void dsi_pll_disable_sub(struct mdss_pll_resources *rsc)
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{
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dsi_pll_disable_global_clk(rsc);
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MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_RBUF_CTRL, 0);
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dsi_pll_disable_pll_bias(rsc);
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}
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@ -573,11 +652,20 @@ static void dsi_pll_disable(struct dsi_pll_vco_clk *vco)
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pr_debug("stop PLL (%d)\n", rsc->index);
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/*
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* To avoid any stray glitches while
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* abruptly powering down the PLL
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* make sure to gate the clock using
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* the clock enable bit before powering
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* down the PLL
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**/
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dsi_pll_disable_global_clk(rsc);
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MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_PLL_CNTRL, 0);
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dsi_pll_disable_sub(rsc);
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if (rsc->slave)
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if (rsc->slave) {
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dsi_pll_disable_global_clk(rsc->slave);
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dsi_pll_disable_sub(rsc->slave);
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}
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/* flush, ensure all register writes are done*/
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wmb();
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rsc->pll_on = false;
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