From c1a40a76ecd1f8b04b869240ad1d405ed871dbba Mon Sep 17 00:00:00 2001 From: Mitchel Humpherys Date: Thu, 4 Dec 2014 12:11:44 -0800 Subject: [PATCH] iommu/arm-smmu: do a single 64-bit write for ATOS Hardware requires that the ATOS command be issued with a single 64-bit write instead of two 32-bit writes as we're currently doing. Fix this. Change-Id: I43104c89c2f27b75d1176c8cbcd214666321244f Signed-off-by: Mitchel Humpherys --- drivers/iommu/arm-smmu.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 7bc54ef2e560..61558f2f14bf 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1902,10 +1902,8 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, u32 reg = iova & ~0xfff; writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO); } else { - u32 reg = iova & ~0xfff; - writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO); - reg = (iova & ~0xfff) >> 32; - writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_HI); + u64 reg = iova & ~0xfff; + writeq_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO); } if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,