msm: mdss: Add mdp clock optimization for mdp3 targets
For the panels of resolution less than qHD, ppp can work in SVS when there is no scaling involved. Optimize the clock rates based on this for 8909 target. Change-Id: I0357edcb3f1bc9e4f821a897b6740ac60b4fd44a Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
This commit is contained in:
Shivaraj Shetty
David Keitel
parent
0507b2f2e2
commit
c1de9aefa2
4 changed files with 44 additions and 8 deletions
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@ -558,7 +558,7 @@ static int mdp3_clk_setup(void)
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if (rc)
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return rc;
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rc = mdp3_clk_set_rate(MDP3_CLK_MDP_SRC, MDP_CORE_CLK_RATE,
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rc = mdp3_clk_set_rate(MDP3_CLK_MDP_SRC, MDP_CORE_CLK_RATE_SVS,
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MDP3_CLIENT_DMA_P);
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if (rc)
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pr_err("%s: Error setting max clock during probe\n", __func__);
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@ -1632,7 +1632,7 @@ static int mdp3_continuous_splash_on(struct mdss_panel_data *pdata)
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mdp3_clk_set_rate(MDP3_CLK_VSYNC, MDP_VSYNC_CLK_RATE,
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MDP3_CLIENT_DMA_P);
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mdp3_clk_set_rate(MDP3_CLK_MDP_SRC, MDP_CORE_CLK_RATE,
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mdp3_clk_set_rate(MDP3_CLK_MDP_SRC, MDP_CORE_CLK_RATE_SVS,
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MDP3_CLIENT_DMA_P);
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bus_handle = &mdp3_res->bus_handle[MDP3_BUS_HANDLE];
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@ -26,7 +26,12 @@
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#include "mdss.h"
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#define MDP_VSYNC_CLK_RATE 19200000
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#define MDP_CORE_CLK_RATE 307200000
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#define MDP_CORE_CLK_RATE_SVS 150000000
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#define MDP_CORE_CLK_RATE_MAX 307200000
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/* PPP cant work at SVS for panel res above qHD */
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#define SVS_MAX_PIXEL (540 * 960)
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#define KOFF_TIMEOUT msecs_to_jiffies(84)
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enum {
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@ -367,7 +367,7 @@ static int mdp3_ctrl_res_req_clk(struct msm_fb_data_type *mfd, int status)
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int rc = 0;
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if (status) {
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mdp3_clk_set_rate(MDP3_CLK_MDP_SRC, MDP_CORE_CLK_RATE,
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mdp3_clk_set_rate(MDP3_CLK_MDP_SRC, MDP_CORE_CLK_RATE_SVS,
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MDP3_CLIENT_DMA_P);
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mdp3_clk_set_rate(MDP3_CLK_VSYNC, MDP_VSYNC_CLK_RATE,
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MDP3_CLIENT_DMA_P);
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@ -34,7 +34,7 @@
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#define MDP_IS_IMGTYPE_BAD(x) ((x) >= MDP_IMGTYPE_LIMIT)
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#define MDP_RELEASE_BW_TIMEOUT 50
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#define MDP_BLIT_CLK_RATE 200000000
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#define MDP_PPP_MAX_BPP 4
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#define MDP_PPP_DYNAMIC_FACTOR 3
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#define MDP_PPP_MAX_READ_WRITE 3
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@ -102,6 +102,7 @@ struct ppp_status {
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struct work_struct free_bw_work;
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bool bw_on;
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bool bw_optimal;
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u32 mdp_clk;
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};
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static struct ppp_status *ppp_stat;
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@ -328,16 +329,38 @@ void mdp3_ppp_kickoff(void)
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mdp3_irq_disable(MDP3_PPP_DONE);
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}
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u32 mdp3_clk_calc(struct msm_fb_data_type *mfd, struct blit_req_list *lreq)
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{
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struct mdss_panel_info *panel_info = mfd->panel_info;
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int i, lcount = 0;
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struct mdp_blit_req *req;
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u32 total_pixel;
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u32 mdp_clk_rate = MDP_CORE_CLK_RATE_SVS;
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total_pixel = panel_info->xres * panel_info->yres;
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if (total_pixel > SVS_MAX_PIXEL)
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return MDP_CORE_CLK_RATE_MAX;
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for (i = 0; i < lcount; i++) {
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req = &(lreq->req_list[i]);
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if (req->src_rect.h != req->dst_rect.h ||
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req->src_rect.w != req->dst_rect.w) {
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mdp_clk_rate = MDP_CORE_CLK_RATE_MAX;
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break;
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}
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}
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return mdp_clk_rate;
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}
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int mdp3_ppp_vote_update(struct msm_fb_data_type *mfd)
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{
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struct mdss_panel_info *panel_info = mfd->panel_info;
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uint64_t req_bw = 0, ab = 0, ib = 0;
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int rate = 0;
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int rc = 0;
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if (!ppp_stat->bw_on)
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pr_err("%s: PPP vote update in wrong state\n", __func__);
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rate = MDP_BLIT_CLK_RATE;
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req_bw = panel_info->xres * panel_info->yres *
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panel_info->mipi.frame_rate *
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MDP_PPP_MAX_BPP *
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@ -365,7 +388,7 @@ int mdp3_ppp_turnon(struct msm_fb_data_type *mfd, int on_off)
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int rc;
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if (on_off) {
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rate = MDP_BLIT_CLK_RATE;
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rate = MDP_CORE_CLK_RATE_SVS;
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req_bw = panel_info->xres * panel_info->yres *
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panel_info->mipi.frame_rate *
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MDP_PPP_MAX_BPP *
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@ -390,6 +413,7 @@ int mdp3_ppp_turnon(struct msm_fb_data_type *mfd, int on_off)
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return rc;
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}
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ppp_stat->bw_on = on_off;
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ppp_stat->mdp_clk = MDP_CORE_CLK_RATE_SVS;
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return 0;
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}
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@ -1035,6 +1059,7 @@ static void mdp3_ppp_blit_wq_handler(struct work_struct *work)
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struct msm_fb_data_type *mfd = ppp_stat->mfd;
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struct blit_req_list *req;
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int i, rc = 0;
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u32 new_clk_rate;
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mutex_lock(&ppp_stat->config_ppp_mutex);
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req = mdp3_ppp_next_req(&ppp_stat->req_q);
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@ -1054,6 +1079,12 @@ static void mdp3_ppp_blit_wq_handler(struct work_struct *work)
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}
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while (req) {
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mdp3_ppp_wait_for_fence(req);
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new_clk_rate = mdp3_clk_calc(mfd, req);
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if (new_clk_rate != ppp_stat->mdp_clk) {
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ppp_stat->mdp_clk = new_clk_rate;
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mdp3_clk_set_rate(MDP3_CLK_MDP_SRC, new_clk_rate,
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MDP3_CLIENT_PPP);
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}
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for (i = 0; i < req->count; i++) {
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if (!(req->req_list[i].flags & MDP_NO_BLIT)) {
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/* Do the actual blit. */
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