ASoC: wcd934x: fix default value for FLL threshold
The default value of CPE FLL threshold register needs to be updated to 0x20 as per the hardware specification. Change fixes this by adding this register to the codec register defaults. CRs-Fixed: 1083199 Change-Id: Ib19d78f0834803c75b255ee3a119e043ffb8a988 Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
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@ -8005,6 +8005,7 @@ static const struct tavil_reg_mask_val tavil_codec_reg_defaults[] = {
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{WCD934X_HPH_OCP_CTL, 0xFF, 0x3A}, /* OCP current limit */
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{WCD934X_HPH_L_TEST, 0x01, 0x01},
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{WCD934X_HPH_R_TEST, 0x01, 0x01},
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{WCD934X_CPE_FLL_CONFIG_CTL_2, 0xFF, 0x20},
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};
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static const struct tavil_reg_mask_val tavil_codec_reg_init_1_1_val[] = {
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