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ARM: dts: msm: Add bus bandwidth entry for ICNSS

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Add bus bandwidth entry for ICNSS. It will be used to vote for
aggre2_noc_clk for SMMU.

CRs-Fixed: 1053538
Change-Id: Ic7523e68d65634f28babac6d17e0b02311d7ad79
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
This commit is contained in:
Yuanyuan Liu 2016-08-11 14:58:23 -07:00
parent a207e02a1d
commit c2a2da2c97
1 changed files with 5 additions and 2 deletions
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7
arch/arm/boot/dts/qcom/msmcobalt.dtsi
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@ -2732,8 +2732,6 @@
<0xb0000000 0x10000>;
reg-names = "membase", "mpm_config",
"smmu_iova_base", "smmu_iova_ipa";
clocks = <&clock_gcc clk_aggre2_noc_clk>;
clock-names = "smmu_aggre2_noc_clk";
iommus = <&anoc2_smmu 0x1900>,
<&anoc2_smmu 0x1901>;
interrupts = <0 413 0 /* CE0 */ >,
@ -2751,6 +2749,11 @@
qcom,wlan-msa-memory = <0x100000>;
vdd-io-supply = <&pmcobalt_l5>;
qcom,vdd-io-voltage-level = <800000 800000>;
qcom,msm-bus,name = "msm-icnss";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <81 10065 0 0>,
<81 10065 0 16000>;
};
wil6210: qcom,wil6210 {