staging: most: fix buffer size for DIM2
This patch reduces the DBR buffer size to prevent an overflow in the DIM2 module. It is needed, because the MediaLB hardware has problems with DBR buffers that exceed the size of 255 messages. Signed-off-by: Andrey Shvetsov <andrey.shvetsov@k2l.de> Signed-off-by: Christian Gromm <christian.gromm@microchip.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 2 additions and 2 deletions
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@ -766,14 +766,14 @@ u8 DIM_InitControl(struct dim_channel *ch, u8 is_tx, u16 ch_address,
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u16 max_buffer_size)
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u16 max_buffer_size)
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{
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{
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return init_ctrl_async(ch, CAT_CT_VAL_CONTROL, is_tx, ch_address,
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return init_ctrl_async(ch, CAT_CT_VAL_CONTROL, is_tx, ch_address,
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max_buffer_size * 2);
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max_buffer_size);
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}
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}
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u8 DIM_InitAsync(struct dim_channel *ch, u8 is_tx, u16 ch_address,
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u8 DIM_InitAsync(struct dim_channel *ch, u8 is_tx, u16 ch_address,
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u16 max_buffer_size)
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u16 max_buffer_size)
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{
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{
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return init_ctrl_async(ch, CAT_CT_VAL_ASYNC, is_tx, ch_address,
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return init_ctrl_async(ch, CAT_CT_VAL_ASYNC, is_tx, ch_address,
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max_buffer_size * 2);
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max_buffer_size);
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}
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}
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u8 DIM_InitIsoc(struct dim_channel *ch, u8 is_tx, u16 ch_address,
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u8 DIM_InitIsoc(struct dim_channel *ch, u8 is_tx, u16 ch_address,
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