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Merge "ARM: dts: msm: Add pin control settings for UFS reset on SDM660"

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Linux Build Service Account 2018-10-03 19:21:07 -07:00 • committed by Gerrit - the friendly Code Review server
commit c40d5678db
2 changed files with 50 additions and 0 deletions
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46
arch/arm/boot/dts/qcom/sdm660-pinctrl.dtsi
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@ -75,6 +75,52 @@
}; };
}; };
ufs_dev_reset_assert: ufs_dev_reset_assert {
config {
pins = "ufs_reset";
bias-pull-down; /* default: pull down */
/*
* UFS_RESET driver strengths are having
* different values/steps compared to typical
* GPIO drive strengths.
*
* Following table clarifies:
*
* HDRV value | UFS_RESET | Typical GPIO
* (dec) | (mA) | (mA)
* 0 | 0.8 | 2
* 1 | 1.55 | 4
* 2 | 2.35 | 6
* 3 | 3.1 | 8
* 4 | 3.9 | 10
* 5 | 4.65 | 12
* 6 | 5.4 | 14
* 7 | 6.15 | 16
*
* POR value for UFS_RESET HDRV is 3 which means
* 3.1mA and we want to use that. Hence just
* specify 8mA to "drive-strength" binding and
* that should result into writing 3 to HDRV
* field.
*/
drive-strength = <8>; /* default: 3.1 mA */
output-low; /* active low reset */
};
};
ufs_dev_reset_deassert: ufs_dev_reset_deassert {
config {
pins = "ufs_reset";
bias-pull-down; /* default: pull down */
/*
* default: 3.1 mA
* check comments under ufs_dev_reset_assert
*/
drive-strength = <8>;
output-high; /* active low reset */
};
};
/* SDC pin type */ /* SDC pin type */
sdc1_clk_on: sdc1_clk_on { sdc1_clk_on: sdc1_clk_on {
config { config {

4
arch/arm/boot/dts/qcom/sdm660.dtsi
View file

@ -2407,6 +2407,10 @@
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
"MAX"; "MAX";
pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
pinctrl-0 = <&ufs_dev_reset_assert>;
pinctrl-1 = <&ufs_dev_reset_deassert>;
resets = <&clock_gcc GCC_UFS_BCR>; resets = <&clock_gcc GCC_UFS_BCR>;
reset-names = "core_reset"; reset-names = "core_reset";