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Merge "ASoC: msm: Group mi2s driver support for msm8996"

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Linux Build Service Account 2018-12-19 15:20:24 -08:00 • committed by Gerrit - the friendly Code Review server
commit c434e9712c
8 changed files with 4311 additions and 8 deletions
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138
include/sound/apr_audio-v2.h
View file

@ -1489,11 +1489,35 @@ struct adm_cmd_connect_afe_port_v5 {
#define AFE_PORT_ID_PRIMARY_MI2S_RX 0x1000
#define AFE_PORT_ID_PRIMARY_MI2S_TX 0x1001
#define AFE_PORT_ID_SECONDARY_MI2S_RX 0x1002
#define AFE_PORT_ID_SECONDARY_MI2S_RX_1 0x1040
#define AFE_PORT_ID_SECONDARY_MI2S_RX_2 0x1042
#define AFE_PORT_ID_SECONDARY_MI2S_RX_3 0x1044
#define AFE_PORT_ID_SECONDARY_MI2S_RX_4 0x1046
#define AFE_PORT_ID_SECONDARY_MI2S_TX 0x1003
#define AFE_PORT_ID_SECONDARY_MI2S_TX_1 0x1041
#define AFE_PORT_ID_SECONDARY_MI2S_TX_2 0x1043
#define AFE_PORT_ID_SECONDARY_MI2S_TX_3 0x1045
#define AFE_PORT_ID_SECONDARY_MI2S_TX_4 0x1047
#define AFE_PORT_ID_TERTIARY_MI2S_RX 0x1004
#define AFE_PORT_ID_TERTIARY_MI2S_RX_1 0x1048
#define AFE_PORT_ID_TERTIARY_MI2S_RX_2 0x104A
#define AFE_PORT_ID_TERTIARY_MI2S_RX_3 0x104C
#define AFE_PORT_ID_TERTIARY_MI2S_RX_4 0x104E
#define AFE_PORT_ID_TERTIARY_MI2S_TX 0x1005
#define AFE_PORT_ID_TERTIARY_MI2S_TX_1 0x1049
#define AFE_PORT_ID_TERTIARY_MI2S_TX_2 0x104B
#define AFE_PORT_ID_TERTIARY_MI2S_TX_3 0x104D
#define AFE_PORT_ID_TERTIARY_MI2S_TX_4 0x104F
#define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006
#define AFE_PORT_ID_QUATERNARY_MI2S_RX_1 0x1020
#define AFE_PORT_ID_QUATERNARY_MI2S_RX_2 0x1022
#define AFE_PORT_ID_QUATERNARY_MI2S_RX_3 0x1024
#define AFE_PORT_ID_QUATERNARY_MI2S_RX_4 0x1026
#define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007
#define AFE_PORT_ID_QUATERNARY_MI2S_TX_1 0x1021
#define AFE_PORT_ID_QUATERNARY_MI2S_TX_2 0x1023
#define AFE_PORT_ID_QUATERNARY_MI2S_TX_3 0x1025
#define AFE_PORT_ID_QUATERNARY_MI2S_TX_4 0x1027
#define AUDIO_PORT_ID_I2S_RX 0x1008
#define AFE_PORT_ID_DIGITAL_MIC_TX 0x1009
#define AFE_PORT_ID_PRIMARY_PCM_RX 0x100A
@ -10886,6 +10910,7 @@ struct afe_port_cmd_set_aanc_acdb_table {
#define AFE_PARAM_ID_GROUP_DEVICE_CFG 0x00010255
#define AFE_PARAM_ID_GROUP_DEVICE_ENABLE 0x00010256
#define AFE_GROUP_DEVICE_ID_SECONDARY_MI2S_RX 0x1102
#define AFE_PARAM_ID_GROUP_DEVICE_I2S_CONFIG 0x00010286
/* Payload of the #AFE_PARAM_ID_GROUP_DEVICE_CFG
* parameter, which configures max of 8 AFE ports
@ -11069,6 +11094,119 @@ struct afe_param_id_group_device_tdm_cfg {
@values 1 to 2^32 -1 */
} __packed;
#define AFE_GROUP_DEVICE_ID_SECONDARY_MI2S_TX \
(AFE_PORT_ID_SECONDARY_MI2S_TX + 0x100)
#define AFE_GROUP_DEVICE_ID_TERTIARY_MI2S_RX \
(AFE_PORT_ID_TERTIARY_MI2S_RX + 0x100)
#define AFE_GROUP_DEVICE_ID_TERTIARY_MI2S_TX \
(AFE_PORT_ID_TERTIARY_MI2S_TX + 0x100)
#define AFE_GROUP_DEVICE_ID_QUATERNARY_MI2S_RX \
(AFE_PORT_ID_QUATERNARY_MI2S_RX + 0x100)
#define AFE_GROUP_DEVICE_ID_QUATERNARY_MI2S_TX \
(AFE_PORT_ID_QUATERNARY_MI2S_TX + 0x100)
#define AFE_API_VERSION_GROUP_DEVICE_I2S_CONFIG 0x1
/* Payload of the AFE_PARAM_ID_GROUP_DEVICE_I2S_CONFIG parameter ID
* used by AFE_MODULE_GROUP_DEVICE.
*/
struct afe_param_id_group_device_i2s_cfg_v1 {
u32 minor_version;
/**< Minor version used to track group device configuration.
* @values #AFE_API_VERSION_GROUP_DEVICE_I2S_CONFIG
*/
u16 group_id;
/**< ID for the group device.
* @values
* - #AFE_GROUP_DEVICE_ID_SECONDARY_MI2S_RX
* - #AFE_GROUP_DEVICE_ID_SECONDARY_MI2S_TX
* - #AFE_GROUP_DEVICE_ID_TERTIARY_MI2S_RX
* - #AFE_GROUP_DEVICE_ID_TERTIARY_MI2S_TX
* - #AFE_GROUP_DEVICE_ID_QUATERNARY_MI2S_RX
* - #AFE_GROUP_DEVICE_ID_QUATERNARY_MI2S_RX
*/
u16 channel_mode;
/**< Group line channel mode
* @values
* - #AFE_PORT_I2S_SD0
* - #AFE_PORT_I2S_SD1
* - #AFE_PORT_I2S_SD2
* - #AFE_PORT_I2S_SD3
* - #AFE_PORT_I2S_QUAD01
* - #AFE_PORT_I2S_QUAD23
* - #AFE_PORT_I2S_6CHS
* - #AFE_PORT_I2S_8CHS
*/
u32 sample_rate;
/**< Sampling rate of the port.
* @values
* - #AFE_PORT_SAMPLE_RATE_8K
* - #AFE_PORT_SAMPLE_RATE_16K
* - #AFE_PORT_SAMPLE_RATE_24K
* - #AFE_PORT_SAMPLE_RATE_32K
*/
u16 port_id[AFE_GROUP_DEVICE_NUM_PORTS];
/**< Array of member port IDs of this group.
* @values
* - #AFE_PORT_ID_SECONDARY_MI2S_RX_1
* - #AFE_PORT_ID_SECONDARY_MI2S_RX_2
* - #AFE_PORT_ID_SECONDARY_MI2S_RX_3
* - #AFE_PORT_ID_SECONDARY_MI2S_RX_4
* - #AFE_PORT_ID_SECONDARY_MI2S_TX_1
* - #AFE_PORT_ID_SECONDARY_MI2S_TX_2
* - #AFE_PORT_ID_SECONDARY_MI2S_TX_3
* - #AFE_PORT_ID_SECONDARY_MI2S_TX_4
* - #AFE_PORT_ID_TERTIARY_MI2S_RX_1
* - #AFE_PORT_ID_TERTIARY_MI2S_RX_2
* - #AFE_PORT_ID_TERTIARY_MI2S_RX_3
* - #AFE_PORT_ID_TERTIARY_MI2S_RX_4
* - #AFE_PORT_ID_TERTIARY_MI2S_TX_1
* - #AFE_PORT_ID_TERTIARY_MI2S_TX_2
* - #AFE_PORT_ID_TERTIARY_MI2S_TX_3
* - #AFE_PORT_ID_TERTIARY_MI2S_TX_4
* - #AFE_PORT_ID_QUATERNARY_MI2S_RX_1
* - #AFE_PORT_ID_QUATERNARY_MI2S_RX_2
* - #AFE_PORT_ID_QUATERNARY_MI2S_RX_3
* - #AFE_PORT_ID_QUATERNARY_MI2S_RX_4
* - #AFE_PORT_ID_QUATERNARY_MI2S_TX_1
* - #AFE_PORT_ID_QUATERNARY_MI2S_TX_2
* - #AFE_PORT_ID_QUATERNARY_MI2S_TX_3
* - #AFE_PORT_ID_QUATERNARY_MI2S_TX_4
* @tablebulletend
*/
u16 bit_width;
/**< Bit width of the sample.
* @values 16, 24, (32)
*/
u16 reserved;
} __packed;
struct afe_param_id_group_device_enable {
u16 group_id;
u16 enable;
} __packed;
union afe_port_group_mi2s_config {
struct afe_param_id_group_device_i2s_cfg_v1 i2s_cfg;
struct afe_param_id_group_device_enable group_enable;
} __packed;
struct afe_i2s_port_config {
struct afe_param_id_i2s_cfg i2s_cfg;
struct afe_param_id_slot_mapping_cfg slot_mapping;
} __packed;
/* Payload of the #AFE_PARAM_ID_GROUP_DEVICE_ENABLE
* parameter, which enables or
* disables any module.

70
include/sound/q6afe-v2.h
View file

@ -208,6 +208,33 @@ enum {
IDX_AFE_PORT_ID_INT5_MI2S_TX,
IDX_AFE_PORT_ID_INT6_MI2S_RX,
IDX_AFE_PORT_ID_INT6_MI2S_TX,
/* IDX 143 -> 150 */
IDX_AFE_PORT_ID_SECONDARY_MI2S_RX_1,
IDX_AFE_PORT_ID_SECONDARY_MI2S_RX_2,
IDX_AFE_PORT_ID_SECONDARY_MI2S_RX_3,
IDX_AFE_PORT_ID_SECONDARY_MI2S_RX_4,
IDX_AFE_PORT_ID_SECONDARY_MI2S_TX_1,
IDX_AFE_PORT_ID_SECONDARY_MI2S_TX_2,
IDX_AFE_PORT_ID_SECONDARY_MI2S_TX_3,
IDX_AFE_PORT_ID_SECONDARY_MI2S_TX_4,
/* IDX 151 -> 158 */
IDX_AFE_PORT_ID_TERTIARY_MI2S_RX_1,
IDX_AFE_PORT_ID_TERTIARY_MI2S_RX_2,
IDX_AFE_PORT_ID_TERTIARY_MI2S_RX_3,
IDX_AFE_PORT_ID_TERTIARY_MI2S_RX_4,
IDX_AFE_PORT_ID_TERTIARY_MI2S_TX_1,
IDX_AFE_PORT_ID_TERTIARY_MI2S_TX_2,
IDX_AFE_PORT_ID_TERTIARY_MI2S_TX_3,
IDX_AFE_PORT_ID_TERTIARY_MI2S_TX_4,
/* IDX 159 -> 166 */
IDX_AFE_PORT_ID_QUATERNARY_MI2S_RX_1,
IDX_AFE_PORT_ID_QUATERNARY_MI2S_RX_2,
IDX_AFE_PORT_ID_QUATERNARY_MI2S_RX_3,
IDX_AFE_PORT_ID_QUATERNARY_MI2S_RX_4,
IDX_AFE_PORT_ID_QUATERNARY_MI2S_TX_1,
IDX_AFE_PORT_ID_QUATERNARY_MI2S_TX_2,
IDX_AFE_PORT_ID_QUATERNARY_MI2S_TX_3,
IDX_AFE_PORT_ID_QUATERNARY_MI2S_TX_4,
AFE_MAX_PORTS
};
@ -292,6 +319,44 @@ enum {
IDX_GROUP_TDM_MAX,
};
enum {
IDX_SECONDARY_MI2S_RX_1,
IDX_SECONDARY_MI2S_RX_2,
IDX_SECONDARY_MI2S_RX_3,
IDX_SECONDARY_MI2S_RX_4,
IDX_SECONDARY_MI2S_TX_1,
IDX_SECONDARY_MI2S_TX_2,
IDX_SECONDARY_MI2S_TX_3,
IDX_SECONDARY_MI2S_TX_4,
IDX_TERTIARY_MI2S_RX_1,
IDX_TERTIARY_MI2S_RX_2,
IDX_TERTIARY_MI2S_RX_3,
IDX_TERTIARY_MI2S_RX_4,
IDX_TERTIARY_MI2S_TX_1,
IDX_TERTIARY_MI2S_TX_2,
IDX_TERTIARY_MI2S_TX_3,
IDX_TERTIARY_MI2S_TX_4,
IDX_QUATERNARY_MI2S_RX_1,
IDX_QUATERNARY_MI2S_RX_2,
IDX_QUATERNARY_MI2S_RX_3,
IDX_QUATERNARY_MI2S_RX_4,
IDX_QUATERNARY_MI2S_TX_1,
IDX_QUATERNARY_MI2S_TX_2,
IDX_QUATERNARY_MI2S_TX_3,
IDX_QUATERNARY_MI2S_TX_4,
IDX_GROUP_MI2S_PORT_MAX,
};
enum {
IDX_GROUP_SECONDARY_MI2S_RX,
IDX_GROUP_SECONDARY_MI2S_TX,
IDX_GROUP_TERTIARY_MI2S_RX,
IDX_GROUP_TERTIARY_MI2S_TX,
IDX_GROUP_QUATERNARY_MI2S_RX,
IDX_GROUP_QUATERNARY_MI2S_TX,
IDX_GROUP_MI2S_MAX,
};
enum afe_mad_type {
MAD_HW_NONE = 0x00,
MAD_HW_AUDIO = 0x01,
@ -458,4 +523,9 @@ int afe_request_dma_resources(uint8_t dma_type, uint8_t num_read_dma_channels,
int afe_get_dma_idx(bool **ret_rddma_idx,
bool **ret_wrdma_idx);
int afe_release_all_dma_resources(void);
int afe_i2s_port_start(u16 port_id, struct afe_i2s_port_config *i2s_port,
u32 rate, u16 num_groups);
int afe_port_group_mi2s_enable(u16 group_id,
union afe_port_group_mi2s_config *afe_group_config,
u16 enable);
#endif /* __Q6AFE_V2_H__ */

710
sound/soc/msm/apq8096-auto.c
View file

@ -160,6 +160,42 @@ static int msm_tert_tdm_slot_num = 8;
static int msm_quat_tdm_slot_width = 32;
static int msm_quat_tdm_slot_num = 8;
/* Group_MI2S default port channels */
static int msm_sec_group_mi2s_rx_1_ch = 2;
static int msm_sec_group_mi2s_rx_2_ch = 2;
static int msm_sec_group_mi2s_rx_3_ch = 2;
static int msm_sec_group_mi2s_rx_4_ch = 2;
static int msm_sec_group_mi2s_tx_1_ch = 2;
static int msm_sec_group_mi2s_tx_2_ch = 2;
static int msm_sec_group_mi2s_tx_3_ch = 2;
static int msm_sec_group_mi2s_tx_4_ch = 2;
static int msm_tert_group_mi2s_rx_1_ch = 2;
static int msm_tert_group_mi2s_rx_2_ch = 2;
static int msm_tert_group_mi2s_rx_3_ch = 2;
static int msm_tert_group_mi2s_rx_4_ch = 2;
static int msm_tert_group_mi2s_tx_1_ch = 2;
static int msm_tert_group_mi2s_tx_2_ch = 2;
static int msm_tert_group_mi2s_tx_3_ch = 2;
static int msm_tert_group_mi2s_tx_4_ch = 2;
static int msm_quat_group_mi2s_rx_1_ch = 2;
static int msm_quat_group_mi2s_rx_2_ch = 2;
static int msm_quat_group_mi2s_rx_3_ch = 2;
static int msm_quat_group_mi2s_rx_4_ch = 2;
static int msm_quat_group_mi2s_tx_1_ch = 2;
static int msm_quat_group_mi2s_tx_2_ch = 2;
static int msm_quat_group_mi2s_tx_3_ch = 2;
static int msm_quat_group_mi2s_tx_4_ch = 2;
/* Group MI2S default sample rate*/
static int msm_sec_group_mi2s_rate = SAMPLING_RATE_48KHZ;
static int msm_tert_group_mi2s_rate = SAMPLING_RATE_48KHZ;
static int msm_quat_group_mi2s_rate = SAMPLING_RATE_48KHZ;
/* Group MI2S slot width bit format */
static int msm_sec_group_mi2s_bit_format = SNDRV_PCM_FORMAT_S24_LE;
static int msm_tert_group_mi2s_bit_format = SNDRV_PCM_FORMAT_S24_LE;
static int msm_quat_group_mi2s_bit_format = SNDRV_PCM_FORMAT_S24_LE;
/* EC Reference default values are set in mixer_paths.xml */
static int msm_ec_ref_ch = 4;
static int msm_ec_ref_bit_format = SNDRV_PCM_FORMAT_S16_LE;
@ -172,6 +208,41 @@ static void *adsp_state_notifier;
static bool dummy_device_registered;
static struct snd_soc_card *sndcard;
#define GROUP_MI2S_SLOT_OFFSET_MAX 8
static unsigned int group_mi2s_slot_offset
[IDX_GROUP_MI2S_PORT_MAX][GROUP_MI2S_SLOT_OFFSET_MAX] = {
/* GROUP_SEC_MI2S_RX */
{0, 4, 0xFFFF},
{0, 4, 0xFFFF},
{0xFFFF},
{0xFFFF},
/* GROUP_SEC_MI2S_TX */
{0, 4, 0xFFFF},
{0, 4, 0xFFFF},
{0xFFFF},
{0xFFFF},
/* GROUP_TERT_MI2S_RX */
{0, 4, 0xFFFF},
{0, 4, 0xFFFF},
{0xFFFF},
{0xFFFF},
/* GROUP_TERT_MI2S_TX */
{0, 4, 0xFFFF},
{0, 4, 0xFFFF},
{0xFFFF},
{0xFFFF},
/* GROUP_QUAT_MI2S_RX */
{0, 4, 0xFFFF},
{0, 4, 0xFFFF},
{0, 4, 0xFFFF},
{0, 4, 0xFFFF},
/* GROUP_QUAT_MI2S_TX */
{0, 4, 0xFFFF},
{0, 4, 0xFFFF},
{0, 4, 0xFFFF},
{0, 4, 0xFFFF},
};
enum {
QUATERNARY_TDM_RX_0,
QUATERNARY_TDM_RX_1,
@ -3307,6 +3378,173 @@ static int msm_mi2s_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
return 0;
}
static int msm_group_mi2s_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
struct snd_interval *rate =
hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels =
hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
switch (cpu_dai->id) {
case AFE_PORT_ID_SECONDARY_MI2S_RX_1:
channels->min = channels->max = msm_sec_group_mi2s_rx_1_ch;
rate->min = rate->max = msm_sec_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_sec_group_mi2s_bit_format);
break;
case AFE_PORT_ID_SECONDARY_MI2S_RX_2:
channels->min = channels->max = msm_sec_group_mi2s_rx_2_ch;
rate->min = rate->max = msm_sec_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_sec_group_mi2s_bit_format);
break;
case AFE_PORT_ID_SECONDARY_MI2S_RX_3:
channels->min = channels->max = msm_sec_group_mi2s_rx_3_ch;
rate->min = rate->max = msm_sec_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_sec_group_mi2s_bit_format);
break;
case AFE_PORT_ID_SECONDARY_MI2S_RX_4:
channels->min = channels->max = msm_sec_group_mi2s_rx_4_ch;
rate->min = rate->max = msm_sec_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_sec_group_mi2s_bit_format);
break;
case AFE_PORT_ID_SECONDARY_MI2S_TX_1:
channels->min = channels->max = msm_sec_group_mi2s_tx_1_ch;
rate->min = rate->max = msm_sec_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_sec_group_mi2s_bit_format);
break;
case AFE_PORT_ID_SECONDARY_MI2S_TX_2:
channels->min = channels->max = msm_sec_group_mi2s_tx_2_ch;
rate->min = rate->max = msm_sec_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_sec_group_mi2s_bit_format);
break;
case AFE_PORT_ID_SECONDARY_MI2S_TX_3:
channels->min = channels->max = msm_sec_group_mi2s_tx_3_ch;
rate->min = rate->max = msm_sec_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_sec_group_mi2s_bit_format);
break;
case AFE_PORT_ID_SECONDARY_MI2S_TX_4:
channels->min = channels->max = msm_sec_group_mi2s_tx_4_ch;
rate->min = rate->max = msm_sec_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_sec_group_mi2s_bit_format);
break;
case AFE_PORT_ID_TERTIARY_MI2S_RX_1:
channels->min = channels->max = msm_tert_group_mi2s_rx_1_ch;
rate->min = rate->max = msm_tert_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_tert_group_mi2s_bit_format);
break;
case AFE_PORT_ID_TERTIARY_MI2S_RX_2:
channels->min = channels->max = msm_tert_group_mi2s_rx_2_ch;
rate->min = rate->max = msm_tert_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_tert_group_mi2s_bit_format);
break;
case AFE_PORT_ID_TERTIARY_MI2S_RX_3:
channels->min = channels->max = msm_tert_group_mi2s_rx_3_ch;
rate->min = rate->max = msm_tert_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_tert_group_mi2s_bit_format);
break;
case AFE_PORT_ID_TERTIARY_MI2S_RX_4:
channels->min = channels->max = msm_tert_group_mi2s_rx_4_ch;
rate->min = rate->max = msm_tert_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_tert_group_mi2s_bit_format);
break;
case AFE_PORT_ID_TERTIARY_MI2S_TX_1:
channels->min = channels->max = msm_tert_group_mi2s_tx_1_ch;
rate->min = rate->max = msm_tert_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_tert_group_mi2s_bit_format);
break;
case AFE_PORT_ID_TERTIARY_MI2S_TX_2:
channels->min = channels->max = msm_tert_group_mi2s_tx_2_ch;
rate->min = rate->max = msm_tert_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_tert_group_mi2s_bit_format);
break;
case AFE_PORT_ID_TERTIARY_MI2S_TX_3:
channels->min = channels->max = msm_tert_group_mi2s_tx_3_ch;
rate->min = rate->max = msm_tert_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_tert_group_mi2s_bit_format);
break;
case AFE_PORT_ID_TERTIARY_MI2S_TX_4:
channels->min = channels->max = msm_tert_group_mi2s_tx_4_ch;
rate->min = rate->max = msm_tert_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_tert_group_mi2s_bit_format);
break;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_1:
channels->min = channels->max = msm_quat_group_mi2s_rx_1_ch;
rate->min = rate->max = msm_quat_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_quat_group_mi2s_bit_format);
break;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_2:
channels->min = channels->max = msm_quat_group_mi2s_rx_2_ch;
rate->min = rate->max = msm_quat_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_quat_group_mi2s_bit_format);
break;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_3:
channels->min = channels->max = msm_quat_group_mi2s_rx_3_ch;
rate->min = rate->max = msm_quat_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_quat_group_mi2s_bit_format);
break;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_4:
channels->min = channels->max = msm_quat_group_mi2s_rx_4_ch;
rate->min = rate->max = msm_quat_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_quat_group_mi2s_bit_format);
break;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_1:
channels->min = channels->max = msm_quat_group_mi2s_tx_1_ch;
rate->min = rate->max = msm_quat_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_quat_group_mi2s_bit_format);
break;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_2:
channels->min = channels->max = msm_quat_group_mi2s_tx_2_ch;
rate->min = rate->max = msm_quat_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_quat_group_mi2s_bit_format);
break;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_3:
channels->min = channels->max = msm_quat_group_mi2s_tx_3_ch;
rate->min = rate->max = msm_quat_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_quat_group_mi2s_bit_format);
break;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_4:
channels->min = channels->max = msm_quat_group_mi2s_tx_4_ch;
rate->min = rate->max = msm_quat_group_mi2s_rate;
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
msm_quat_group_mi2s_bit_format);
break;
default:
pr_err("%s: dai id 0x%x not supported\n",
__func__, cpu_dai->id);
return -EINVAL;
}
pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
__func__, cpu_dai->id, channels->max, rate->max,
params_format(params));
return 0;
}
static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
@ -4085,6 +4323,142 @@ static struct snd_soc_ops apq8096_tdm_be_ops = {
.hw_params = apq8096_tdm_snd_hw_params,
};
static int apq8096_group_mi2s_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
int ret = 0;
int channels, rate;
unsigned int *slot_offset;
int offset_channels = 0;
int i;
rate = params_rate(params);
channels = params_channels(params);
switch (cpu_dai->id) {
case AFE_PORT_ID_SECONDARY_MI2S_RX_1:
slot_offset = group_mi2s_slot_offset[IDX_SECONDARY_MI2S_RX_1];
break;
case AFE_PORT_ID_SECONDARY_MI2S_RX_2:
slot_offset = group_mi2s_slot_offset[IDX_SECONDARY_MI2S_RX_2];
break;
case AFE_PORT_ID_SECONDARY_MI2S_RX_3:
slot_offset = group_mi2s_slot_offset[IDX_SECONDARY_MI2S_RX_3];
break;
case AFE_PORT_ID_SECONDARY_MI2S_RX_4:
slot_offset = group_mi2s_slot_offset[IDX_SECONDARY_MI2S_RX_4];
break;
case AFE_PORT_ID_SECONDARY_MI2S_TX_1:
slot_offset = group_mi2s_slot_offset[IDX_SECONDARY_MI2S_TX_1];
break;
case AFE_PORT_ID_SECONDARY_MI2S_TX_2:
slot_offset = group_mi2s_slot_offset[IDX_SECONDARY_MI2S_TX_2];
break;
case AFE_PORT_ID_SECONDARY_MI2S_TX_3:
slot_offset = group_mi2s_slot_offset[IDX_SECONDARY_MI2S_TX_3];
break;
case AFE_PORT_ID_SECONDARY_MI2S_TX_4:
slot_offset = group_mi2s_slot_offset[IDX_SECONDARY_MI2S_TX_4];
break;
case AFE_PORT_ID_TERTIARY_MI2S_RX_1:
slot_offset = group_mi2s_slot_offset[IDX_TERTIARY_MI2S_RX_1];
break;
case AFE_PORT_ID_TERTIARY_MI2S_RX_2:
slot_offset = group_mi2s_slot_offset[IDX_TERTIARY_MI2S_RX_2];
break;
case AFE_PORT_ID_TERTIARY_MI2S_RX_3:
slot_offset = group_mi2s_slot_offset[IDX_TERTIARY_MI2S_RX_3];
break;
case AFE_PORT_ID_TERTIARY_MI2S_RX_4:
slot_offset = group_mi2s_slot_offset[IDX_TERTIARY_MI2S_RX_4];
break;
case AFE_PORT_ID_TERTIARY_MI2S_TX_1:
slot_offset = group_mi2s_slot_offset[IDX_TERTIARY_MI2S_TX_1];
break;
case AFE_PORT_ID_TERTIARY_MI2S_TX_2:
slot_offset = group_mi2s_slot_offset[IDX_TERTIARY_MI2S_TX_2];
break;
case AFE_PORT_ID_TERTIARY_MI2S_TX_3:
slot_offset = group_mi2s_slot_offset[IDX_TERTIARY_MI2S_TX_3];
break;
case AFE_PORT_ID_TERTIARY_MI2S_TX_4:
slot_offset = group_mi2s_slot_offset[IDX_TERTIARY_MI2S_TX_4];
break;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_1:
slot_offset = group_mi2s_slot_offset[IDX_QUATERNARY_MI2S_RX_1];
break;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_2:
slot_offset = group_mi2s_slot_offset[IDX_QUATERNARY_MI2S_RX_2];
break;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_3:
slot_offset = group_mi2s_slot_offset[IDX_QUATERNARY_MI2S_RX_3];
break;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_4:
slot_offset = group_mi2s_slot_offset[IDX_QUATERNARY_MI2S_RX_4];
break;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_1:
slot_offset = group_mi2s_slot_offset[IDX_QUATERNARY_MI2S_TX_1];
break;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_2:
slot_offset = group_mi2s_slot_offset[IDX_QUATERNARY_MI2S_TX_2];
break;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_3:
slot_offset = group_mi2s_slot_offset[IDX_QUATERNARY_MI2S_TX_3];
break;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_4:
slot_offset = group_mi2s_slot_offset[IDX_QUATERNARY_MI2S_TX_4];
break;
default:
pr_err("%s: dai id 0x%x not supported\n",
__func__, cpu_dai->id);
return -EINVAL;
}
for (i = 0; i < GROUP_MI2S_SLOT_OFFSET_MAX; i++) {
if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID)
offset_channels++;
}
if (offset_channels == 0) {
pr_err("%s: slot offset not supported, offset_channels %d\n",
__func__, offset_channels);
return -EINVAL;
}
if (channels > offset_channels) {
pr_err("%s: channels %d and offset_channels %d not match\n",
__func__, channels, offset_channels);
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL,
channels, slot_offset);
if (ret < 0) {
pr_err("%s: failed to set channel map, err:%d\n",
__func__, ret);
goto end;
}
} else {
ret = snd_soc_dai_set_channel_map(cpu_dai,
channels, slot_offset,
0, NULL);
if (ret < 0) {
pr_err("%s: failed to set channel map, err:%d\n",
__func__, ret);
goto end;
}
}
end:
return ret;
}
static struct snd_soc_ops apq8096_group_mi2s_be_ops = {
.hw_params = apq8096_group_mi2s_snd_hw_params,
};
static const struct soc_enum msm_snd_enum[] = {
SOC_ENUM_SINGLE_EXT(2, auxpcm_rate_text),
SOC_ENUM_SINGLE_EXT(7, hdmi_rx_ch_text),
@ -6546,6 +6920,342 @@ static struct snd_soc_dai_link apq8096_auto_be_dai_links[] = {
.be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
.ops = &apq8096_tdm_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_SEC_MI2S_TX_1,
.stream_name = "Secondary MI2S1 Capture",
.cpu_dai_name = "msm-dai-q6-mi2s.4161",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-tx",
.no_pcm = 1,
.dpcm_capture = 1,
.be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX_1,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_SEC_MI2S_TX_2,
.stream_name = "Secondary MI2S2 Capture",
.cpu_dai_name = "msm-dai-q6-mi2s.4163",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-tx",
.no_pcm = 1,
.dpcm_capture = 1,
.be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX_2,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_SEC_MI2S_TX_3,
.stream_name = "Secondary MI2S3 Capture",
.cpu_dai_name = "msm-dai-q6-mi2s.4165",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-tx",
.no_pcm = 1,
.dpcm_capture = 1,
.be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX_3,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_SEC_MI2S_TX_4,
.stream_name = "Secondary MI2S4 Capture",
.cpu_dai_name = "msm-dai-q6-mi2s.4167",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-tx",
.no_pcm = 1,
.dpcm_capture = 1,
.be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX_4,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_TERT_MI2S_TX_1,
.stream_name = "Tertiary MI2S1 Capture",
.cpu_dai_name = "msm-dai-q6-mi2s.4169",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-tx",
.no_pcm = 1,
.dpcm_capture = 1,
.be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX_1,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_TERT_MI2S_TX_2,
.stream_name = "Tertiary MI2S2 Capture",
.cpu_dai_name = "msm-dai-q6-mi2s.4171",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-tx",
.no_pcm = 1,
.dpcm_capture = 1,
.be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX_2,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_TERT_MI2S_TX_3,
.stream_name = "Tertiary MI2S3 Capture",
.cpu_dai_name = "msm-dai-q6-mi2s.4173",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-tx",
.no_pcm = 1,
.dpcm_capture = 1,
.be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX_3,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_TERT_MI2S_TX_4,
.stream_name = "Tertiary MI2S4 Capture",
.cpu_dai_name = "msm-dai-q6-mi2s.4175",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-tx",
.no_pcm = 1,
.dpcm_capture = 1,
.be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX_4,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_QUAT_MI2S_TX_1,
.stream_name = "Quaternary MI2S1 Capture",
.cpu_dai_name = "msm-dai-q6-mi2s.4129",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-tx",
.no_pcm = 1,
.dpcm_capture = 1,
.be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX_1,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_QUAT_MI2S_TX_2,
.stream_name = "Quaternary MI2S2 Capture",
.cpu_dai_name = "msm-dai-q6-mi2s.4131",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-tx",
.no_pcm = 1,
.dpcm_capture = 1,
.be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX_2,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_QUAT_MI2S_TX_3,
.stream_name = "Quaternary MI2S3 Capture",
.cpu_dai_name = "msm-dai-q6-mi2s.4133",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-tx",
.no_pcm = 1,
.dpcm_capture = 1,
.be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX_3,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_QUAT_MI2S_TX_4,
.stream_name = "Quaternary MI2S4 Capture",
.cpu_dai_name = "msm-dai-q6-mi2s.4135",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-tx",
.no_pcm = 1,
.dpcm_capture = 1,
.be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX_4,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_SEC_MI2S_RX_1,
.stream_name = "Secondary MI2S1 Playback",
.cpu_dai_name = "msm-dai-q6-mi2s.4160",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-rx",
.no_pcm = 1,
.dpcm_playback = 1,
.be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX_1,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_SEC_MI2S_RX_2,
.stream_name = "Secondary MI2S2 Playback",
.cpu_dai_name = "msm-dai-q6-mi2s.4162",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-rx",
.no_pcm = 1,
.dpcm_playback = 1,
.be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX_2,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_SEC_MI2S_RX_3,
.stream_name = "Secondary MI2S3 Playback",
.cpu_dai_name = "msm-dai-q6-mi2s.4164",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-rx",
.no_pcm = 1,
.dpcm_playback = 1,
.be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX_3,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_SEC_MI2S_RX_4,
.stream_name = "Secondary MI2S4 Playback",
.cpu_dai_name = "msm-dai-q6-mi2s.4166",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-rx",
.no_pcm = 1,
.dpcm_playback = 1,
.be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX_4,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_TERT_MI2S_RX_1,
.stream_name = "Tertiary MI2S1 Playback",
.cpu_dai_name = "msm-dai-q6-mi2s.4168",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-rx",
.no_pcm = 1,
.dpcm_playback = 1,
.be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX_1,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_TERT_MI2S_RX_2,
.stream_name = "Tertiary MI2S2 Playback",
.cpu_dai_name = "msm-dai-q6-mi2s.4170",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-rx",
.no_pcm = 1,
.dpcm_playback = 1,
.be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX_2,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_TERT_MI2S_RX_3,
.stream_name = "Tertiary MI2S3 Playback",
.cpu_dai_name = "msm-dai-q6-mi2s.4172",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-rx",
.no_pcm = 1,
.dpcm_playback = 1,
.be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX_3,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_TERT_MI2S_RX_4,
.stream_name = "Tertiary MI2S4 Playback",
.cpu_dai_name = "msm-dai-q6-mi2s.4174",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-rx",
.no_pcm = 1,
.dpcm_playback = 1,
.be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX_4,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_QUAT_MI2S_RX_1,
.stream_name = "Quaternary MI2S1 Playback",
.cpu_dai_name = "msm-dai-q6-mi2s.4128",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-rx",
.no_pcm = 1,
.dpcm_playback = 1,
.be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX_1,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_QUAT_MI2S_RX_2,
.stream_name = "Quaternary MI2S2 Playback",
.cpu_dai_name = "msm-dai-q6-mi2s.4130",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-rx",
.no_pcm = 1,
.dpcm_playback = 1,
.be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX_2,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_QUAT_MI2S_RX_3,
.stream_name = "Quaternary MI2S3 Playback",
.cpu_dai_name = "msm-dai-q6-mi2s.4132",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-rx",
.no_pcm = 1,
.dpcm_playback = 1,
.be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX_3,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
},
{
.name = LPASS_BE_QUAT_MI2S_RX_4,
.stream_name = "Quaternary MI2S4 Playback",
.cpu_dai_name = "msm-dai-q6-mi2s.4134",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-rx",
.no_pcm = 1,
.dpcm_playback = 1,
.be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX_4,
.be_hw_params_fixup = msm_group_mi2s_be_hw_params_fixup,
.ops = &apq8096_group_mi2s_be_ops,
.ignore_suspend = 1,
}
};

1382
sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c
View file

File diff suppressed because it is too large Load diff

1491
sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c
View file

File diff suppressed because it is too large Load diff

52
sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h
View file

@ -167,6 +167,34 @@
#define LPASS_BE_INT5_MI2S_TX "INT5_MI2S_TX"
#define LPASS_BE_INT6_MI2S_RX "INT6_MI2S_RX"
#define LPASS_BE_INT6_MI2S_TX "INT6_MI2S_TX"
#define LPASS_BE_SEC_MI2S_RX_1 "SEC_MI2S_RX_1"
#define LPASS_BE_SEC_MI2S_RX_2 "SEC_MI2S_RX_2"
#define LPASS_BE_SEC_MI2S_RX_3 "SEC_MI2S_RX_3"
#define LPASS_BE_SEC_MI2S_RX_4 "SEC_MI2S_RX_4"
#define LPASS_BE_SEC_MI2S_TX_1 "SEC_MI2S_TX_1"
#define LPASS_BE_SEC_MI2S_TX_2 "SEC_MI2S_TX_2"
#define LPASS_BE_SEC_MI2S_TX_3 "SEC_MI2S_TX_3"
#define LPASS_BE_SEC_MI2S_TX_4 "SEC_MI2S_TX_4"
#define LPASS_BE_TERT_MI2S_RX_1 "TERT_MI2S_RX_1"
#define LPASS_BE_TERT_MI2S_RX_2 "TERT_MI2S_RX_2"
#define LPASS_BE_TERT_MI2S_RX_3 "TERT_MI2S_RX_3"
#define LPASS_BE_TERT_MI2S_RX_4 "TERT_MI2S_RX_4"
#define LPASS_BE_TERT_MI2S_TX_1 "TERT_MI2S_TX_1"
#define LPASS_BE_TERT_MI2S_TX_2 "TERT_MI2S_TX_2"
#define LPASS_BE_TERT_MI2S_TX_3 "TERT_MI2S_TX_3"
#define LPASS_BE_TERT_MI2S_TX_4 "TERT_MI2S_TX_4"
#define LPASS_BE_QUAT_MI2S_RX_1 "QUAT_MI2S_RX_1"
#define LPASS_BE_QUAT_MI2S_RX_2 "QUAT_MI2S_RX_2"
#define LPASS_BE_QUAT_MI2S_RX_3 "QUAT_MI2S_RX_3"
#define LPASS_BE_QUAT_MI2S_RX_4 "QUAT_MI2S_RX_4"
#define LPASS_BE_QUAT_MI2S_TX_1 "QUAT_MI2S_TX_1"
#define LPASS_BE_QUAT_MI2S_TX_2 "QUAT_MI2S_TX_2"
#define LPASS_BE_QUAT_MI2S_TX_3 "QUAT_MI2S_TX_3"
#define LPASS_BE_QUAT_MI2S_TX_4 "QUAT_MI2S_TX_4"
/* For multimedia front-ends, asm session is allocated dynamically.
* Hence, asm session/multimedia front-end mapping has to be maintained.
* Due to this reason, additional multimedia front-end must be placed before
@ -373,6 +401,30 @@ enum {
MSM_BACKEND_DAI_INT5_MI2S_TX,
MSM_BACKEND_DAI_INT6_MI2S_RX,
MSM_BACKEND_DAI_INT6_MI2S_TX,
MSM_BACKEND_DAI_SECONDARY_MI2S_RX_1,
MSM_BACKEND_DAI_SECONDARY_MI2S_RX_2,
MSM_BACKEND_DAI_SECONDARY_MI2S_RX_3,
MSM_BACKEND_DAI_SECONDARY_MI2S_RX_4,
MSM_BACKEND_DAI_SECONDARY_MI2S_TX_1,
MSM_BACKEND_DAI_SECONDARY_MI2S_TX_2,
MSM_BACKEND_DAI_SECONDARY_MI2S_TX_3,
MSM_BACKEND_DAI_SECONDARY_MI2S_TX_4,
MSM_BACKEND_DAI_TERTIARY_MI2S_RX_1,
MSM_BACKEND_DAI_TERTIARY_MI2S_RX_2,
MSM_BACKEND_DAI_TERTIARY_MI2S_RX_3,
MSM_BACKEND_DAI_TERTIARY_MI2S_RX_4,
MSM_BACKEND_DAI_TERTIARY_MI2S_TX_1,
MSM_BACKEND_DAI_TERTIARY_MI2S_TX_2,
MSM_BACKEND_DAI_TERTIARY_MI2S_TX_3,
MSM_BACKEND_DAI_TERTIARY_MI2S_TX_4,
MSM_BACKEND_DAI_QUATERNARY_MI2S_RX_1,
MSM_BACKEND_DAI_QUATERNARY_MI2S_RX_2,
MSM_BACKEND_DAI_QUATERNARY_MI2S_RX_3,
MSM_BACKEND_DAI_QUATERNARY_MI2S_RX_4,
MSM_BACKEND_DAI_QUATERNARY_MI2S_TX_1,
MSM_BACKEND_DAI_QUATERNARY_MI2S_TX_2,
MSM_BACKEND_DAI_QUATERNARY_MI2S_TX_3,
MSM_BACKEND_DAI_QUATERNARY_MI2S_TX_4,
MSM_BACKEND_DAI_MAX,
};

332
sound/soc/msm/qdsp6v2/q6afe.c
View file

@ -785,6 +785,18 @@ int afe_get_port_type(u16 port_id)
case AFE_PORT_ID_INT4_MI2S_RX:
case AFE_PORT_ID_INT5_MI2S_RX:
case AFE_PORT_ID_INT6_MI2S_RX:
case AFE_PORT_ID_SECONDARY_MI2S_RX_1:
case AFE_PORT_ID_SECONDARY_MI2S_RX_2:
case AFE_PORT_ID_SECONDARY_MI2S_RX_3:
case AFE_PORT_ID_SECONDARY_MI2S_RX_4:
case AFE_PORT_ID_TERTIARY_MI2S_RX_1:
case AFE_PORT_ID_TERTIARY_MI2S_RX_2:
case AFE_PORT_ID_TERTIARY_MI2S_RX_3:
case AFE_PORT_ID_TERTIARY_MI2S_RX_4:
case AFE_PORT_ID_QUATERNARY_MI2S_RX_1:
case AFE_PORT_ID_QUATERNARY_MI2S_RX_2:
case AFE_PORT_ID_QUATERNARY_MI2S_RX_3:
case AFE_PORT_ID_QUATERNARY_MI2S_RX_4:
ret = MSM_AFE_PORT_TYPE_RX;
break;
@ -856,6 +868,18 @@ int afe_get_port_type(u16 port_id)
case AFE_PORT_ID_INT4_MI2S_TX:
case AFE_PORT_ID_INT5_MI2S_TX:
case AFE_PORT_ID_INT6_MI2S_TX:
case AFE_PORT_ID_SECONDARY_MI2S_TX_1:
case AFE_PORT_ID_SECONDARY_MI2S_TX_2:
case AFE_PORT_ID_SECONDARY_MI2S_TX_3:
case AFE_PORT_ID_SECONDARY_MI2S_TX_4:
case AFE_PORT_ID_TERTIARY_MI2S_TX_1:
case AFE_PORT_ID_TERTIARY_MI2S_TX_2:
case AFE_PORT_ID_TERTIARY_MI2S_TX_3:
case AFE_PORT_ID_TERTIARY_MI2S_TX_4:
case AFE_PORT_ID_QUATERNARY_MI2S_TX_1:
case AFE_PORT_ID_QUATERNARY_MI2S_TX_2:
case AFE_PORT_ID_QUATERNARY_MI2S_TX_3:
case AFE_PORT_ID_QUATERNARY_MI2S_TX_4:
ret = MSM_AFE_PORT_TYPE_TX;
break;
@ -2734,6 +2758,118 @@ int afe_send_custom_tdm_header_cfg(
return ret;
}
int afe_i2s_port_start(u16 port_id, struct afe_i2s_port_config *i2s_port,
u32 rate, u16 num_groups)
{
struct param_hdr_v3 param_hdr = {0};
int index = 0;
uint16_t port_index = 0;
enum afe_mad_type mad_type = MAD_HW_NONE;
int ret = 0;
if (!i2s_port) {
pr_err("%s: Error, no configuration data\n", __func__);
return -EINVAL;
}
pr_debug("%s: port id: 0x%x\n", __func__, port_id);
index = q6audio_get_port_index(port_id);
if (index < 0 || index >= AFE_MAX_PORTS) {
pr_err("%s: AFE port index[%d] invalid!\n",
__func__, index);
return -EINVAL;
}
ret = q6audio_validate_port(port_id);
if (ret < 0) {
pr_err("%s: port id: 0x%x ret %d\n", __func__, port_id, ret);
return -EINVAL;
}
ret = afe_q6_interface_prepare();
if (ret != 0) {
pr_err("%s: Q6 interface prepare failed %d\n", __func__, ret);
return ret;
}
if ((index >= 0) && (index < AFE_MAX_PORTS)) {
this_afe.afe_sample_rates[index] = rate;
if (this_afe.rt_cb)
this_afe.dev_acdb_id[index] = this_afe.rt_cb(port_id);
}
/* Also send the topology id here if multiple ports: */
port_index = afe_get_port_index(port_id);
if (!(this_afe.afe_cal_mode[port_index] == AFE_CAL_MODE_NONE) &&
num_groups > 1) {
/* One time call: only for first time */
afe_send_custom_topology();
afe_send_port_topology_id(port_id);
afe_send_cal(port_id);
afe_send_hw_delay(port_id, rate);
}
/* Start SW MAD module */
mad_type = afe_port_get_mad_type(port_id);
pr_debug("%s: port_id 0x%x, mad_type %d\n", __func__, port_id,
mad_type);
if (mad_type != MAD_HW_NONE && mad_type != MAD_SW_AUDIO) {
if (!afe_has_config(AFE_CDC_REGISTERS_CONFIG) ||
!afe_has_config(AFE_SLIMBUS_SLAVE_CONFIG)) {
pr_err("%s: AFE isn't configured yet for\n"
"HW MAD try Again\n", __func__);
ret = -EAGAIN;
goto fail_cmd;
}
ret = afe_turn_onoff_hw_mad(mad_type, true);
if (ret) {
pr_err("%s: afe_turn_onoff_hw_mad failed %d\n",
__func__, ret);
goto fail_cmd;
}
}
param_hdr.module_id = AFE_MODULE_AUDIO_DEV_INTERFACE;
param_hdr.instance_id = INSTANCE_ID_0;
param_hdr.param_id = AFE_PARAM_ID_I2S_CONFIG;
param_hdr.param_size = sizeof(struct afe_param_id_i2s_cfg);
ret = q6afe_pack_and_set_param_in_band(port_id,
q6audio_get_port_index(port_id),
param_hdr,
(u8 *) &i2s_port->i2s_cfg);
if (ret) {
pr_err("%s: AFE enable for port 0x%x failed ret = %d\n",
__func__, port_id, ret);
goto fail_cmd;
}
port_index = afe_get_port_index(port_id);
if ((port_index >= 0) && (port_index < AFE_MAX_PORTS)) {
this_afe.afe_sample_rates[port_index] = rate;
} else {
pr_err("%s: Invalid port index %d\n", __func__, port_index);
ret = -EINVAL;
goto fail_cmd;
}
/* slot mapping is not need if there is only one group */
if (num_groups > 1) {
ret = afe_send_slot_mapping_cfg(
&i2s_port->slot_mapping,
port_id);
if (ret < 0) {
pr_err("%s: afe send failed %d\n", __func__, ret);
goto fail_cmd;
}
}
ret = afe_send_cmd_port_start(port_id);
fail_cmd:
return ret;
}
int afe_tdm_port_start(u16 port_id, struct afe_tdm_port_config *tdm_port,
u32 rate, u16 num_groups)
{
@ -3598,6 +3734,54 @@ int afe_get_port_index(u16 port_id)
return IDX_AFE_PORT_ID_INT6_MI2S_RX;
case AFE_PORT_ID_INT6_MI2S_TX:
return IDX_AFE_PORT_ID_INT6_MI2S_TX;
case AFE_PORT_ID_SECONDARY_MI2S_TX_1:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_TX_1;
case AFE_PORT_ID_SECONDARY_MI2S_TX_2:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_TX_2;
case AFE_PORT_ID_SECONDARY_MI2S_TX_3:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_TX_3;
case AFE_PORT_ID_SECONDARY_MI2S_TX_4:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_TX_4;
case AFE_PORT_ID_TERTIARY_MI2S_TX_1:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_TX_1;
case AFE_PORT_ID_TERTIARY_MI2S_TX_2:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_TX_2;
case AFE_PORT_ID_TERTIARY_MI2S_TX_3:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_TX_3;
case AFE_PORT_ID_TERTIARY_MI2S_TX_4:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_TX_4;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_1:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_TX_1;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_2:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_TX_2;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_3:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_TX_3;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_4:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_TX_4;
case AFE_PORT_ID_SECONDARY_MI2S_RX_1:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_RX_1;
case AFE_PORT_ID_SECONDARY_MI2S_RX_2:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_RX_2;
case AFE_PORT_ID_SECONDARY_MI2S_RX_3:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_RX_3;
case AFE_PORT_ID_SECONDARY_MI2S_RX_4:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_RX_4;
case AFE_PORT_ID_TERTIARY_MI2S_RX_1:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_RX_1;
case AFE_PORT_ID_TERTIARY_MI2S_RX_2:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_RX_2;
case AFE_PORT_ID_TERTIARY_MI2S_RX_3:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_RX_3;
case AFE_PORT_ID_TERTIARY_MI2S_RX_4:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_RX_4;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_1:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_RX_1;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_2:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_RX_2;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_3:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_RX_3;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_4:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_RX_4;
default:
pr_err("%s: port 0x%x\n", __func__, port_id);
return -EINVAL;
@ -4022,6 +4206,154 @@ int afe_port_group_set_param(u16 group_id,
return ret;
}
static int afe_port_group_mi2s_set_param(u16 group_id,
struct afe_param_id_group_device_i2s_cfg_v1 *afe_group_config)
{
struct param_hdr_v3 param_hdr = {0};
int cfg_type;
int ret;
if (!afe_group_config) {
pr_err("%s: Error, no configuration data\n", __func__);
return -EINVAL;
}
pr_debug("%s: group id: 0x%x\n", __func__, group_id);
ret = afe_q6_interface_prepare();
if (ret != 0) {
pr_err("%s: Q6 interface prepare failed %d\n", __func__, ret);
return ret;
}
switch (group_id) {
case AFE_GROUP_DEVICE_ID_SECONDARY_MI2S_RX:
case AFE_GROUP_DEVICE_ID_SECONDARY_MI2S_TX:
case AFE_GROUP_DEVICE_ID_TERTIARY_MI2S_RX:
case AFE_GROUP_DEVICE_ID_TERTIARY_MI2S_TX:
case AFE_GROUP_DEVICE_ID_QUATERNARY_MI2S_RX:
case AFE_GROUP_DEVICE_ID_QUATERNARY_MI2S_TX:
cfg_type = AFE_PARAM_ID_GROUP_DEVICE_I2S_CONFIG;
break;
default:
pr_err("%s: Invalid group id 0x%x\n", __func__, group_id);
return -EINVAL;
}
param_hdr.module_id = AFE_MODULE_GROUP_DEVICE;
param_hdr.instance_id = INSTANCE_ID_0;
param_hdr.param_id = cfg_type;
param_hdr.param_size =
sizeof(struct afe_param_id_group_device_i2s_cfg_v1);
ret = q6afe_svc_pack_and_set_param_in_band(IDX_GLOBAL_CFG, param_hdr,
(u8 *) afe_group_config);
if (ret)
pr_err("%s: AFE_PARAM_ID_GROUP_DEVICE_CFG failed %d\n",
__func__, ret);
return ret;
}
static atomic_t mi2s_gp_en_ref[IDX_GROUP_MI2S_MAX];
static int afe_get_mi2s_group_idx(u16 group_id)
{
int gp_idx = -1;
switch (group_id) {
case AFE_GROUP_DEVICE_ID_SECONDARY_MI2S_RX:
gp_idx = IDX_GROUP_SECONDARY_MI2S_RX;
break;
case AFE_GROUP_DEVICE_ID_SECONDARY_MI2S_TX:
gp_idx = IDX_GROUP_SECONDARY_MI2S_TX;
break;
case AFE_GROUP_DEVICE_ID_TERTIARY_MI2S_RX:
gp_idx = IDX_GROUP_TERTIARY_MI2S_RX;
break;
case AFE_GROUP_DEVICE_ID_TERTIARY_MI2S_TX:
gp_idx = IDX_GROUP_TERTIARY_MI2S_TX;
break;
case AFE_GROUP_DEVICE_ID_QUATERNARY_MI2S_RX:
gp_idx = IDX_GROUP_QUATERNARY_MI2S_RX;
break;
case AFE_GROUP_DEVICE_ID_QUATERNARY_MI2S_TX:
gp_idx = IDX_GROUP_QUATERNARY_MI2S_TX;
break;
default:
break;
}
return gp_idx;
}
int afe_port_group_mi2s_enable(u16 group_id,
union afe_port_group_mi2s_config *afe_group_config,
u16 enable)
{
struct afe_param_id_group_device_enable group_enable = {0};
struct param_hdr_v3 param_hdr = {0};
int ret = 0;
int gp_idx;
pr_debug("%s: group id: 0x%x enable: %d\n", __func__,
group_id, enable);
gp_idx = afe_get_mi2s_group_idx(group_id);
if ((gp_idx >= 0) && (gp_idx < IDX_GROUP_MI2S_MAX)) {
atomic_t *gp_ref = &mi2s_gp_en_ref[gp_idx];
if (enable)
atomic_inc(gp_ref);
else
atomic_dec(gp_ref);
if ((enable) && (atomic_read(gp_ref) > 1)) {
pr_err("%s: this TDM group is enabled already %d refs_cnt %d\n",
__func__, group_id, atomic_read(gp_ref));
goto rtn;
}
if ((!enable) && (atomic_read(gp_ref) > 0)) {
pr_err("%s: this TDM group will be disabled in last call %d refs_cnt %d\n",
__func__, group_id, atomic_read(gp_ref));
goto rtn;
}
}
ret = afe_q6_interface_prepare();
if (ret != 0) {
pr_err("%s: Q6 interface prepare failed %d\n", __func__, ret);
return ret;
}
if (enable) {
ret = afe_port_group_mi2s_set_param(
group_id, &afe_group_config->i2s_cfg);
if (ret < 0) {
pr_err("%s: afe send failed %d\n", __func__, ret);
return ret;
}
}
param_hdr.module_id = AFE_MODULE_GROUP_DEVICE;
param_hdr.instance_id = INSTANCE_ID_0;
param_hdr.param_id = AFE_PARAM_ID_GROUP_DEVICE_ENABLE;
param_hdr.param_size = sizeof(struct afe_group_device_enable);
group_enable.group_id = group_id;
group_enable.enable = enable;
ret = q6afe_svc_pack_and_set_param_in_band(IDX_GLOBAL_CFG, param_hdr,
(u8 *) &group_enable);
if (ret)
pr_err("%s: AFE_PARAM_ID_GROUP_DEVICE_ENABLE failed %d\n",
__func__, ret);
rtn:
return ret;
}
int afe_port_group_enable(u16 group_id,
union afe_port_group_config *afe_group_config,
u16 enable)

144
sound/soc/msm/qdsp6v2/q6audio-v2.c
View file

@ -95,6 +95,54 @@ int q6audio_get_port_index(u16 port_id)
return IDX_AFE_PORT_ID_TERTIARY_MI2S_RX;
case AFE_PORT_ID_TERTIARY_MI2S_TX:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_TX;
case AFE_PORT_ID_SECONDARY_MI2S_TX_1:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_TX_1;
case AFE_PORT_ID_SECONDARY_MI2S_TX_2:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_TX_2;
case AFE_PORT_ID_SECONDARY_MI2S_TX_3:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_TX_3;
case AFE_PORT_ID_SECONDARY_MI2S_TX_4:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_TX_4;
case AFE_PORT_ID_TERTIARY_MI2S_TX_1:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_TX_1;
case AFE_PORT_ID_TERTIARY_MI2S_TX_2:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_TX_2;
case AFE_PORT_ID_TERTIARY_MI2S_TX_3:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_TX_3;
case AFE_PORT_ID_TERTIARY_MI2S_TX_4:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_TX_4;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_1:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_TX_1;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_2:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_TX_2;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_3:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_TX_3;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_4:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_TX_4;
case AFE_PORT_ID_SECONDARY_MI2S_RX_1:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_RX_1;
case AFE_PORT_ID_SECONDARY_MI2S_RX_2:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_RX_2;
case AFE_PORT_ID_SECONDARY_MI2S_RX_3:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_RX_3;
case AFE_PORT_ID_SECONDARY_MI2S_RX_4:
return IDX_AFE_PORT_ID_SECONDARY_MI2S_RX_4;
case AFE_PORT_ID_TERTIARY_MI2S_RX_1:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_RX_1;
case AFE_PORT_ID_TERTIARY_MI2S_RX_2:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_RX_2;
case AFE_PORT_ID_TERTIARY_MI2S_RX_3:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_RX_3;
case AFE_PORT_ID_TERTIARY_MI2S_RX_4:
return IDX_AFE_PORT_ID_TERTIARY_MI2S_RX_4;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_1:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_RX_1;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_2:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_RX_2;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_3:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_RX_3;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_4:
return IDX_AFE_PORT_ID_QUATERNARY_MI2S_RX_4;
case AUDIO_PORT_ID_I2S_RX:
return IDX_AUDIO_PORT_ID_I2S_RX;
case AFE_PORT_ID_SECONDARY_MI2S_RX_SD1:
@ -342,6 +390,54 @@ int q6audio_get_port_id(u16 port_id)
return AFE_PORT_ID_TERTIARY_MI2S_RX;
case AFE_PORT_ID_TERTIARY_MI2S_TX:
return AFE_PORT_ID_TERTIARY_MI2S_TX;
case AFE_PORT_ID_SECONDARY_MI2S_TX_1:
return AFE_PORT_ID_SECONDARY_MI2S_TX_1;
case AFE_PORT_ID_SECONDARY_MI2S_TX_2:
return AFE_PORT_ID_SECONDARY_MI2S_TX_2;
case AFE_PORT_ID_SECONDARY_MI2S_TX_3:
return AFE_PORT_ID_SECONDARY_MI2S_TX_3;
case AFE_PORT_ID_SECONDARY_MI2S_TX_4:
return AFE_PORT_ID_SECONDARY_MI2S_TX_4;
case AFE_PORT_ID_TERTIARY_MI2S_TX_1:
return AFE_PORT_ID_TERTIARY_MI2S_TX_1;
case AFE_PORT_ID_TERTIARY_MI2S_TX_2:
return AFE_PORT_ID_TERTIARY_MI2S_TX_2;
case AFE_PORT_ID_TERTIARY_MI2S_TX_3:
return AFE_PORT_ID_TERTIARY_MI2S_TX_3;
case AFE_PORT_ID_TERTIARY_MI2S_TX_4:
return AFE_PORT_ID_TERTIARY_MI2S_TX_4;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_1:
return AFE_PORT_ID_QUATERNARY_MI2S_TX_1;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_2:
return AFE_PORT_ID_QUATERNARY_MI2S_TX_2;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_3:
return AFE_PORT_ID_QUATERNARY_MI2S_TX_3;
case AFE_PORT_ID_QUATERNARY_MI2S_TX_4:
return AFE_PORT_ID_QUATERNARY_MI2S_TX_4;
case AFE_PORT_ID_SECONDARY_MI2S_RX_1:
return AFE_PORT_ID_SECONDARY_MI2S_RX_1;
case AFE_PORT_ID_SECONDARY_MI2S_RX_2:
return AFE_PORT_ID_SECONDARY_MI2S_RX_2;
case AFE_PORT_ID_SECONDARY_MI2S_RX_3:
return AFE_PORT_ID_SECONDARY_MI2S_RX_3;
case AFE_PORT_ID_SECONDARY_MI2S_RX_4:
return AFE_PORT_ID_SECONDARY_MI2S_RX_4;
case AFE_PORT_ID_TERTIARY_MI2S_RX_1:
return AFE_PORT_ID_TERTIARY_MI2S_RX_1;
case AFE_PORT_ID_TERTIARY_MI2S_RX_2:
return AFE_PORT_ID_TERTIARY_MI2S_RX_2;
case AFE_PORT_ID_TERTIARY_MI2S_RX_3:
return AFE_PORT_ID_TERTIARY_MI2S_RX_3;
case AFE_PORT_ID_TERTIARY_MI2S_RX_4:
return AFE_PORT_ID_TERTIARY_MI2S_RX_4;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_1:
return AFE_PORT_ID_QUATERNARY_MI2S_RX_1;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_2:
return AFE_PORT_ID_QUATERNARY_MI2S_RX_2;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_3:
return AFE_PORT_ID_QUATERNARY_MI2S_RX_3;
case AFE_PORT_ID_QUATERNARY_MI2S_RX_4:
return AFE_PORT_ID_QUATERNARY_MI2S_RX_4;
case AUDIO_PORT_ID_I2S_RX:
return AUDIO_PORT_ID_I2S_RX;
case AFE_PORT_ID_SECONDARY_MI2S_RX_SD1:
@ -642,6 +738,30 @@ int q6audio_is_digital_pcm_interface(u16 port_id)
case AFE_PORT_ID_INT5_MI2S_TX:
case AFE_PORT_ID_INT6_MI2S_RX:
case AFE_PORT_ID_INT6_MI2S_TX:
case AFE_PORT_ID_SECONDARY_MI2S_RX_1:
case AFE_PORT_ID_SECONDARY_MI2S_RX_2:
case AFE_PORT_ID_SECONDARY_MI2S_RX_3:
case AFE_PORT_ID_SECONDARY_MI2S_RX_4:
case AFE_PORT_ID_TERTIARY_MI2S_RX_1:
case AFE_PORT_ID_TERTIARY_MI2S_RX_2:
case AFE_PORT_ID_TERTIARY_MI2S_RX_3:
case AFE_PORT_ID_TERTIARY_MI2S_RX_4:
case AFE_PORT_ID_QUATERNARY_MI2S_RX_1:
case AFE_PORT_ID_QUATERNARY_MI2S_RX_2:
case AFE_PORT_ID_QUATERNARY_MI2S_RX_3:
case AFE_PORT_ID_QUATERNARY_MI2S_RX_4:
case AFE_PORT_ID_SECONDARY_MI2S_TX_1:
case AFE_PORT_ID_SECONDARY_MI2S_TX_2:
case AFE_PORT_ID_SECONDARY_MI2S_TX_3:
case AFE_PORT_ID_SECONDARY_MI2S_TX_4:
case AFE_PORT_ID_TERTIARY_MI2S_TX_1:
case AFE_PORT_ID_TERTIARY_MI2S_TX_2:
case AFE_PORT_ID_TERTIARY_MI2S_TX_3:
case AFE_PORT_ID_TERTIARY_MI2S_TX_4:
case AFE_PORT_ID_QUATERNARY_MI2S_TX_1:
case AFE_PORT_ID_QUATERNARY_MI2S_TX_2:
case AFE_PORT_ID_QUATERNARY_MI2S_TX_3:
case AFE_PORT_ID_QUATERNARY_MI2S_TX_4:
break;
default:
ret = -EINVAL;
@ -795,6 +915,30 @@ int q6audio_validate_port(u16 port_id)
case AFE_PORT_ID_INT6_MI2S_RX:
case AFE_PORT_ID_INT6_MI2S_TX:
case AFE_PORT_ID_MULTICHAN_HDMI_RX:
case AFE_PORT_ID_SECONDARY_MI2S_RX_1:
case AFE_PORT_ID_SECONDARY_MI2S_RX_2:
case AFE_PORT_ID_SECONDARY_MI2S_RX_3:
case AFE_PORT_ID_SECONDARY_MI2S_RX_4:
case AFE_PORT_ID_SECONDARY_MI2S_TX_1:
case AFE_PORT_ID_SECONDARY_MI2S_TX_2:
case AFE_PORT_ID_SECONDARY_MI2S_TX_3:
case AFE_PORT_ID_SECONDARY_MI2S_TX_4:
case AFE_PORT_ID_TERTIARY_MI2S_RX_1:
case AFE_PORT_ID_TERTIARY_MI2S_RX_2:
case AFE_PORT_ID_TERTIARY_MI2S_RX_3:
case AFE_PORT_ID_TERTIARY_MI2S_RX_4:
case AFE_PORT_ID_TERTIARY_MI2S_TX_1:
case AFE_PORT_ID_TERTIARY_MI2S_TX_2:
case AFE_PORT_ID_TERTIARY_MI2S_TX_3:
case AFE_PORT_ID_TERTIARY_MI2S_TX_4:
case AFE_PORT_ID_QUATERNARY_MI2S_RX_1:
case AFE_PORT_ID_QUATERNARY_MI2S_RX_2:
case AFE_PORT_ID_QUATERNARY_MI2S_RX_3:
case AFE_PORT_ID_QUATERNARY_MI2S_RX_4:
case AFE_PORT_ID_QUATERNARY_MI2S_TX_1:
case AFE_PORT_ID_QUATERNARY_MI2S_TX_2:
case AFE_PORT_ID_QUATERNARY_MI2S_TX_3:
case AFE_PORT_ID_QUATERNARY_MI2S_TX_4:
{
ret = 0;
break;