staging: octeon-usb: eliminate 64-bit register access wrappers
Eliminate 64-bit register access wrappers. Since we don't implement register-level debugging outputs, these are useless. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Aaro Koskinen
Greg Kroah-Hartman
parent
607078fcb1
commit
c4bdbdd916
1 changed files with 33 additions and 75 deletions
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@ -581,38 +581,6 @@ static inline void __cvmx_usb_write_csr32(struct cvmx_usb_state *usb,
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cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
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}
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/**
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* Read a USB 64bit CSR. It logs the value in a readable format if
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* debugging is on.
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*
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* @usb: USB block this access is for
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* @address: 64bit address to read
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*
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* Returns: Result of the read
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*/
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static inline uint64_t __cvmx_usb_read_csr64(struct cvmx_usb_state *usb,
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uint64_t address)
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{
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uint64_t result = cvmx_read64_uint64(address);
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return result;
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}
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/**
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* Write a USB 64bit CSR. It logs the value in a readable format
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* if debugging is on.
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*
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* @usb: USB block this access is for
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* @address: 64bit address to write
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* @value: Value to write
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*/
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static inline void __cvmx_usb_write_csr64(struct cvmx_usb_state *usb,
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uint64_t address, uint64_t value)
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{
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cvmx_write64_uint64(address, value);
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}
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/**
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* Return non zero if this pipe connects to a non HIGH speed
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* device through a high speed hub.
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@ -683,8 +651,7 @@ static int cvmx_usb_initialize(struct cvmx_usb_state *usb,
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* 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
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* USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
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*/
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usbn_clk_ctl.u64 =
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__cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
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usbn_clk_ctl.u64 = cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb->index));
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usbn_clk_ctl.s.por = 1;
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usbn_clk_ctl.s.hrst = 0;
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usbn_clk_ctl.s.prst = 0;
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@ -747,12 +714,10 @@ static int cvmx_usb_initialize(struct cvmx_usb_state *usb,
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usbn_clk_ctl.s.divide = divisor;
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usbn_clk_ctl.s.divide2 = 0;
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}
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__cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
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usbn_clk_ctl.u64);
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cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
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/* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
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usbn_clk_ctl.s.hclk_rst = 1;
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__cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
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usbn_clk_ctl.u64);
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cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
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/* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
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cvmx_wait(64);
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/*
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@ -761,8 +726,7 @@ static int cvmx_usb_initialize(struct cvmx_usb_state *usb,
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* USBN_CLK_CTL[POR] = 0
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*/
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usbn_clk_ctl.s.por = 0;
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__cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
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usbn_clk_ctl.u64);
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cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
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/* 4. Wait 1 ms for PHY clock to start */
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mdelay(1);
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/*
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@ -770,11 +734,11 @@ static int cvmx_usb_initialize(struct cvmx_usb_state *usb,
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* USBP control and status register:
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* USBN_USBP_CTL_STATUS[ATE_RESET] = 1
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*/
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usbn_usbp_ctl_status.u64 = __cvmx_usb_read_csr64(usb,
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CVMX_USBNX_USBP_CTL_STATUS(usb->index));
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usbn_usbp_ctl_status.u64 =
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cvmx_read64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index));
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usbn_usbp_ctl_status.s.ate_reset = 1;
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__cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
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usbn_usbp_ctl_status.u64);
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cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index),
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usbn_usbp_ctl_status.u64);
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/* 6. Wait 10 cycles */
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cvmx_wait(10);
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/*
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@ -782,23 +746,22 @@ static int cvmx_usb_initialize(struct cvmx_usb_state *usb,
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* USBN_USBP_CTL_STATUS[ATE_RESET] = 0
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*/
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usbn_usbp_ctl_status.s.ate_reset = 0;
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__cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
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usbn_usbp_ctl_status.u64);
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cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index),
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usbn_usbp_ctl_status.u64);
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/*
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* 8. Program the PHY reset field in the USBN clock-control register:
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* USBN_CLK_CTL[PRST] = 1
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*/
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usbn_clk_ctl.s.prst = 1;
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__cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
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usbn_clk_ctl.u64);
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cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
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/*
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* 9. Program the USBP control and status register to select host or
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* device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
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* device
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*/
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usbn_usbp_ctl_status.s.hst_mode = 0;
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__cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
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usbn_usbp_ctl_status.u64);
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cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index),
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usbn_usbp_ctl_status.u64);
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/* 10. Wait 1 us */
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udelay(1);
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/*
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@ -806,12 +769,10 @@ static int cvmx_usb_initialize(struct cvmx_usb_state *usb,
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* USBN_CLK_CTL[HRST] = 1
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*/
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usbn_clk_ctl.s.hrst = 1;
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__cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
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usbn_clk_ctl.u64);
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cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
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/* 12. Proceed to USB core initialization */
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usbn_clk_ctl.s.enable = 1;
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__cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
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usbn_clk_ctl.u64);
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cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
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udelay(1);
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/*
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@ -969,15 +930,13 @@ static int cvmx_usb_shutdown(struct cvmx_usb_state *usb)
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return -EBUSY;
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/* Disable the clocks and put them in power on reset */
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usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb,
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CVMX_USBNX_CLK_CTL(usb->index));
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usbn_clk_ctl.u64 = cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb->index));
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usbn_clk_ctl.s.enable = 1;
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usbn_clk_ctl.s.por = 1;
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usbn_clk_ctl.s.hclk_rst = 1;
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usbn_clk_ctl.s.prst = 0;
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usbn_clk_ctl.s.hrst = 0;
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__cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
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usbn_clk_ctl.u64);
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cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
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return 0;
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}
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@ -1286,13 +1245,12 @@ static void __cvmx_usb_poll_rx_fifo(struct cvmx_usb_state *usb)
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return;
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/* Get where the DMA engine would have written this data */
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address = __cvmx_usb_read_csr64(usb,
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CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8);
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address = cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) +
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channel * 8);
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ptr = cvmx_phys_to_ptr(address);
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__cvmx_usb_write_csr64(usb,
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CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8,
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address + bytes);
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cvmx_write64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel * 8,
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address + bytes);
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/* Loop writing the FIFO data for this packet into memory */
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while (bytes > 0) {
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@ -1448,8 +1406,9 @@ static void __cvmx_usb_fill_tx_fifo(struct cvmx_usb_state *usb, int channel)
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fifo = &usb->nonperiodic;
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fifo->entry[fifo->head].channel = channel;
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fifo->entry[fifo->head].address = __cvmx_usb_read_csr64(usb,
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CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8);
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fifo->entry[fifo->head].address =
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cvmx_read64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) +
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channel * 8);
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fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize+3)>>2;
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fifo->head++;
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if (fifo->head > MAX_CHANNELS)
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@ -1503,9 +1462,9 @@ static void __cvmx_usb_start_channel_control(struct cvmx_usb_state *usb,
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* Setup send the control header instead of the buffer data. The
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* buffer data will be used in the next stage
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*/
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__cvmx_usb_write_csr64(usb,
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CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8,
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transaction->control_header);
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cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) +
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channel * 8,
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transaction->control_header);
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break;
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case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
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usbc_hctsiz.s.pid = 3; /* Setup */
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@ -1696,13 +1655,12 @@ static void __cvmx_usb_start_channel(struct cvmx_usb_state *usb,
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transaction->iso_packets[0].offset +
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transaction->actual_bytes;
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__cvmx_usb_write_csr64(usb,
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CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8,
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dma_address);
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__cvmx_usb_write_csr64(usb,
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CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8,
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dma_address);
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cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) +
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channel * 8,
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dma_address);
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cvmx_write64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) +
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channel * 8,
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dma_address);
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}
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/* Setup both the size of the transfer and the SPLIT characteristics */
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