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Revert KVM: MIPS: Drop other CPU ASIDs on guest MMU changes

Browse source 
This reverts commit d450527ad0 which was
commit 91e4f1b6073dd680d86cdb7e42d7cccca9db39d8 upstream as it was
incorrect.  A fixed version will be forthcoming.

Reported-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman 2016-11-13 12:16:15 +01:00
parent e28a472742
commit c57deabd2b
1 changed files with 10 additions and 53 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

63
arch/mips/kvm/emulate.c
View file

@ -807,47 +807,6 @@ enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu)
return EMULATE_FAIL; return EMULATE_FAIL;
} }
/**
* kvm_mips_invalidate_guest_tlb() - Indicates a change in guest MMU map.
* @vcpu: VCPU with changed mappings.
* @tlb: TLB entry being removed.
*
* This is called to indicate a single change in guest MMU mappings, so that we
* can arrange TLB flushes on this and other CPUs.
*/
static void kvm_mips_invalidate_guest_tlb(struct kvm_vcpu *vcpu,
struct kvm_mips_tlb *tlb)
{
int cpu, i;
bool user;
/* No need to flush for entries which are already invalid */
if (!((tlb->tlb_lo[0] | tlb->tlb_lo[1]) & ENTRYLO_V))
return;
/* User address space doesn't need flushing for KSeg2/3 changes */
user = tlb->tlb_hi < KVM_GUEST_KSEG0;
preempt_disable();
/*
* Probe the shadow host TLB for the entry being overwritten, if one
* matches, invalidate it
*/
kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
/* Invalidate the whole ASID on other CPUs */
cpu = smp_processor_id();
for_each_possible_cpu(i) {
if (i == cpu)
continue;
if (user)
vcpu->arch.guest_user_asid[i] = 0;
vcpu->arch.guest_kernel_asid[i] = 0;
}
preempt_enable();
}
/* Write Guest TLB Entry @ Index */ /* Write Guest TLB Entry @ Index */
enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu) enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu)
{ {
@ -867,8 +826,11 @@ enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu)
} }
tlb = &vcpu->arch.guest_tlb[index]; tlb = &vcpu->arch.guest_tlb[index];
/*
kvm_mips_invalidate_guest_tlb(vcpu, tlb); * Probe the shadow host TLB for the entry being overwritten, if one
* matches, invalidate it
*/
kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0); tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0); tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
@ -897,7 +859,11 @@ enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu)
tlb = &vcpu->arch.guest_tlb[index]; tlb = &vcpu->arch.guest_tlb[index];
kvm_mips_invalidate_guest_tlb(vcpu, tlb); /*
* Probe the shadow host TLB for the entry being overwritten, if one
* matches, invalidate it
*/
kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0); tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0); tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
@ -1016,7 +982,6 @@ enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, uint32_t *opc,
int32_t rt, rd, copz, sel, co_bit, op; int32_t rt, rd, copz, sel, co_bit, op;
uint32_t pc = vcpu->arch.pc; uint32_t pc = vcpu->arch.pc;
unsigned long curr_pc; unsigned long curr_pc;
int cpu, i;
/* /*
* Update PC and hold onto current PC in case there is * Update PC and hold onto current PC in case there is
@ -1124,16 +1089,8 @@ enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, uint32_t *opc,
vcpu->arch.gprs[rt] vcpu->arch.gprs[rt]
& ASID_MASK); & ASID_MASK);
preempt_disable();
/* Blow away the shadow host TLBs */ /* Blow away the shadow host TLBs */
kvm_mips_flush_host_tlb(1); kvm_mips_flush_host_tlb(1);
cpu = smp_processor_id();
for_each_possible_cpu(i)
if (i != cpu) {
vcpu->arch.guest_user_asid[i] = 0;
vcpu->arch.guest_kernel_asid[i] = 0;
}
preempt_enable();
} }
kvm_write_c0_guest_entryhi(cop0, kvm_write_c0_guest_entryhi(cop0,
vcpu->arch.gprs[rt]); vcpu->arch.gprs[rt]);