From c6d31e71765063aa00fee91b69eb064aa0d8065c Mon Sep 17 00:00:00 2001 From: Abhijit Kulkarni Date: Thu, 28 Jan 2016 17:56:18 -0800 Subject: [PATCH] ARM: dts: msm: add mdss device tree for msmcobalt Change adds mdss device tree for msmcobalt which provides mdss HW offsets for this chipset. CRs-fixed: 1000739 Change-Id: Ibb12e0179a66e89ca675f4ae35fc2f77c050da2c Signed-off-by: Gopikrishnaiah Anandan Signed-off-by: Abhijit Kulkarni --- arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi | 215 +++++++++++++++++++++ arch/arm/boot/dts/qcom/msmcobalt.dtsi | 1 + 2 files changed, 216 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi new file mode 100644 index 000000000000..914b5587b2b0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi @@ -0,0 +1,215 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + mdss_mdp: qcom,mdss_mdp@c900000 { + compatible = "qcom,mdss_mdp"; + reg = <0x0c900000 0x90000>, + <0x0c9b0000 0x1040>; + reg-names = "mdp_phys", "vbif_phys"; + interrupts = <0 83 0>; + vdd-supply = <&gdsc_mdss>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_mdp"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, <23 512 0 0>, + <22 512 0 6400000>, <23 512 0 6400000>, + <22 512 0 6400000>, <23 512 0 6400000>; + + /* Fudge factors */ + qcom,mdss-ab-factor = <1 1>; /* 1 time */ + qcom,mdss-ib-factor = <1 1>; /* 1 time */ + qcom,mdss-clk-factor = <105 100>; /* 1.05 times */ + + qcom,max-mixer-width = <2560>; + qcom,max-pipe-width = <2560>; + + /* VBIF QoS remapper settings*/ + qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>; + + qcom,mdss-has-panic-ctrl; + qcom,mdss-per-pipe-panic-luts = <0x000f>, + <0xffff>, + <0xfffc>, + <0xff00>; + + qcom,mdss-mdp-reg-offset = <0x00001000>; + qcom,max-bandwidth-low-kbps = <9600000>; + qcom,max-bandwidth-high-kbps = <9600000>; + qcom,max-bandwidth-per-pipe-kbps = <4500000>; + qcom,max-clk-rate = <412500000>; + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <16>; + qcom,mdss-dram-channels = <2>; + + qcom,mdss-pipe-vig-off = <0x00005000 0x00007000 + 0x00009000 0x0000b000>; + qcom,mdss-pipe-dma-off = <0x00025000 0x00027000>; + qcom,mdss-pipe-cursor-off = <0x00035000 0x00037000>; + + qcom,mdss-pipe-vig-xin-id = <0 4 8 12>; + qcom,mdss-pipe-dma-xin-id = <1 5>; + qcom,mdss-pipe-cursor-xin-id = <2 10>; + + /* These Offsets are relative to + * "mdp_phys + mdp-reg-offset" address + */ + qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2ac 0 0>, + <0x2b4 0 0>, + <0x2bc 0 0>, + <0x2c4 0 0>; + qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2ac 8 12>, + <0x2b4 8 12>; + qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3a8 16 15>, + <0x3b0 16 15>; + + qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400 + 0x00002600 0x00002800>; + qcom,mdss-mixer-intf-off = <0x00045000 0x00046000 + 0x00047000 0x0004a000>; + qcom,mdss-dspp-off = <0x00055000 0x00057000>; + qcom,mdss-wb-off = <0x00066000>; + qcom,mdss-intf-off = <0x0006b000 0x0006b800 + 0x0006c000 0x0006c800>; + qcom,mdss-pingpong-off = <0x00071000 0x00071800 + 0x00072000 0x00072800>; + qcom,mdss-slave-pingpong-off = <0x00073000>; + qcom,mdss-ppb-off = <0x00000330 0x00000338>; + qcom,mdss-has-pingpong-split; + qcom,mdss-has-separate-rotator; + + qcom,mdss-ad-off = <0x0079000 0x00079800 0x0007a000>; + qcom,mdss-cdm-off = <0x0007a200>; + qcom,mdss-dsc-off = <0x00081000 0x00081400>; + qcom,mdss-wfd-mode = "intf"; + qcom,mdss-has-source-split; + qcom,mdss-highest-bank-bit = <0x2>; + qcom,mdss-has-decimation; + qcom,mdss-idle-power-collapse-enabled; + clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>, + <&clock_mmss clk_mmss_mdss_axi_clk>, + <&clock_mmss clk_mdp_clk_src>, + <&clock_mmss clk_mmss_mdss_vsync_clk>; + clock-names = "iface_clk", "bus_clk", "core_clk_src", + "core_clk", "vsync_clk"; + + qcom,regs-dump-mdp = <0x01000 0x01454>, + <0x02000 0x02064>, + <0x02200 0x02264>, + <0x02400 0x02464>, + <0x02600 0x02664>, + <0x02800 0x02864>, + <0x05000 0x05150>, + <0x05200 0x05230>, + <0x07000 0x07150>, + <0x07200 0x07230>, + <0x09000 0x09150>, + <0x09200 0x09230>, + <0x0b000 0x0b150>, + <0x0b200 0x0b230>, + <0x25000 0x25150>, + <0x27000 0x27150>, + <0x35000 0x35150>, + <0x37000 0x37150>, + <0x45000 0x452bc>, + <0x46000 0x462bc>, + <0x47000 0x472bc>, + <0x48000 0x482bc>, + <0x49000 0x492bc>, + <0x4a000 0x4a2bc>, + <0x55000 0x5522c>, + <0x57000 0x5722c>, + <0x66000 0x662c0>, + <0x6b000 0x6b268>, + <0x6b800 0x6ba68>, + <0x6c000 0x6c268>, + <0x6c800 0x6ca68>, + <0x71000 0x710d4>, + <0x71800 0x718d4>, + <0x73000 0x730d4>, + <0x81000 0x81140>, + <0x81400 0x81540>; + + qcom,regs-dump-names-mdp = "MDP", + "CTL_0", "CTL_1", "CTL_2", "CTL_3", "CTL_4", + "VIG0_SSPP", "VIG0", "VIG1_SSPP", "VIG1", + "VIG2_SSPP", "VIG2", "VIG3_SSPP", "VIG3", + "DMA0_SSPP", "DMA1_SSPP", + "CURSOR0_SSPP", "CURSOR1_SSPP", + "LAYER_0", "LAYER_1", "LAYER_2", + "LAYER_3", "LAYER_4", "LAYER_5", + "DSPP_0", "DSPP_1", + "WB_2", + "INTF_0", "INTF_1", "INTF_2", "INTF_3", + "PP_0", "PP_1", "PP_4", + "DSC_0", "DSC_1"; + + /* buffer parameters to calculate prefill bandwidth */ + qcom,mdss-prefill-outstanding-buffer-bytes = <0>; + qcom,mdss-prefill-y-buffer-bytes = <0>; + qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>; + qcom,mdss-prefill-scaler-buffer-lines-caf = <4>; + qcom,mdss-prefill-post-scaler-buffer-pixels = <2560>; + qcom,mdss-prefill-pingpong-buffer-pixels = <5120>; + + qcom,mdss-pp-offsets { + qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>; + qcom,mdss-sspp-vig-pcc-off = <0x1780>; + qcom,mdss-sspp-rgb-pcc-off = <0x380>; + qcom,mdss-sspp-dma-pcc-off = <0x380>; + qcom,mdss-lm-pgc-off = <0x3c0>; + qcom,mdss-dspp-gamut-off = <0x1600>; + qcom,mdss-dspp-pcc-off = <0x1700>; + qcom,mdss-dspp-pgc-off = <0x17c0>; + }; + + smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb { + compatible = "qcom,smmu_mdp_unsec"; + iommus = <&mmss_smmu 0>; + gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>; + clocks = <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>; + clock-names = "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk"; + }; + + smmu_mdp_sec: qcom,smmu_mdp_sec_cb { + compatible = "qcom,smmu_mdp_sec"; + iommus = <&mmss_smmu 1>; + gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>; + clocks = <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>; + clock-names = "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk"; + }; + + mdss_fb0: qcom,mdss_fb_primary { + cell-index = <0>; + compatible = "qcom,mdss-fb"; + }; + + mdss_fb1: qcom,mdss_fb_wfd { + cell-index = <1>; + compatible = "qcom,mdss-fb"; + }; + + }; + + qcom,mdss_wb_panel { + compatible = "qcom,mdss_wb"; + qcom,mdss_pan_res = <640 480>; + qcom,mdss_pan_bpp = <24>; + qcom,mdss-fb-map = <&mdss_fb1>; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 36a7eb9a2469..8c3f0348eebb 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -2224,3 +2224,4 @@ #include "msmcobalt-pinctrl.dtsi" #include "msm-audio-lpass.dtsi" #include "msmcobalt-audio.dtsi" +#include "msmcobalt-mdss.dtsi"