UPSTREAM: arm64: spinlock: fix spin_unlock_wait for LSE atomics
Commit d86b8da04dfa ("arm64: spinlock: serialise spin_unlock_wait against concurrent lockers") fixed spin_unlock_wait for LL/SC-based atomics under the premise that the LSE atomics (in particular, the LDADDA instruction) are indivisible. Unfortunately, these instructions are only indivisible when used with the -AL (full ordering) suffix and, consequently, the same issue can theoretically be observed with LSE atomics, where a later (in program order) load can be speculated before the write portion of the atomic operation. This patch fixes the issue by performing a CAS of the lock once we've established that it's unlocked, in much the same way as the LL/SC code. Fixes: d86b8da04dfa ("arm64: spinlock: serialise spin_unlock_wait against concurrent lockers") Signed-off-by: Will Deacon <will.deacon@arm.com> Bug: 30369029 Patchset: kaslr-arm64-4.4 (cherry picked from commit 3a5facd09da848193f5bcb0dea098a298bc1a29d) Signed-off-by: Jeff Vander Stoep <jeffv@google.com> Change-Id: Icedaa4c508784bf43d0b5787586480fd668ccc49
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1 changed files with 7 additions and 3 deletions
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@ -37,13 +37,17 @@ static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
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"2: ldaxr %w0, %2\n"
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" eor %w1, %w0, %w0, ror #16\n"
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" cbnz %w1, 1b\n"
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/* Serialise against any concurrent lockers */
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ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" stxr %w1, %w0, %2\n"
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" cbnz %w1, 2b\n", /* Serialise against any concurrent lockers */
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/* LSE atomics */
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" nop\n"
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" nop\n")
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" nop\n",
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/* LSE atomics */
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" mov %w1, %w0\n"
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" cas %w0, %w0, %2\n"
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" eor %w1, %w1, %w0\n")
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" cbnz %w1, 2b\n"
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: "=&r" (lockval), "=&r" (tmp), "+Q" (*lock)
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:
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: "memory");
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