Merge "regulator: spm-regulator: Add additional settling delay for FTS2.5 SMPS" into dev/msm-4.4-8996au
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commit
c8b2f82770
1 changed files with 18 additions and 2 deletions
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@ -1,4 +1,4 @@
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/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -118,6 +118,12 @@ static const struct voltage_range hf_range1 = {1550000, 1550000, 3125000,
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#define QPNP_FTS2_STEP_MARGIN_NUM 4
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#define QPNP_FTS2_STEP_MARGIN_DEN 5
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/*
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* Settling delay for FTS2.5
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* Warm-up=20uS, 0-10% & 90-100% non-linear V-ramp delay = 50uS
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*/
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#define FTS2P5_SETTLING_DELAY_US 70
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/* VSET value to decide the range of ULT SMPS */
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#define ULT_SMPS_RANGE_SPLIT 0x60
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@ -268,6 +274,7 @@ static int spm_regulator_write_voltage(struct spm_vreg *vreg, int uV)
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unsigned vlevel = spm_regulator_uv_to_vlevel(vreg, uV);
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bool spm_failed = false;
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int rc = 0;
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u32 slew_delay;
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u8 reg;
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if (likely(!vreg->bypass_spm)) {
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@ -295,7 +302,16 @@ static int spm_regulator_write_voltage(struct spm_vreg *vreg, int uV)
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if (uV > vreg->last_set_uV) {
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/* Wait for voltage stepping to complete. */
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udelay(DIV_ROUND_UP(uV - vreg->last_set_uV, vreg->step_rate));
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slew_delay = DIV_ROUND_UP(vreg->uV - vreg->last_set_uV,
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vreg->step_rate);
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if (vreg->regulator_type == QPNP_TYPE_FTS2p5)
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slew_delay += FTS2P5_SETTLING_DELAY_US;
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udelay(slew_delay);
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} else if (vreg->regulator_type == QPNP_TYPE_FTS2p5) {
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/* add the ramp-down delay */
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slew_delay = DIV_ROUND_UP(vreg->last_set_uV - vreg->uV,
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vreg->step_rate) + FTS2P5_SETTLING_DELAY_US;
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udelay(slew_delay);
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}
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vreg->last_set_uV = uV;
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