msm: mhi: Enable M2 exit through CLKREQ assertion
Enable M2 power state transition exit through CLKREQ GPIO assertion due to MHI doorbell write. CRs-Fixed: 733370 Change-Id: I27b425ee305fc9c044812a8b15c76970987a5dae Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
This commit is contained in:
parent
8d7c29c161
commit
c966ff457f
6 changed files with 111 additions and 155 deletions
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@ -395,6 +395,7 @@ struct mhi_flags {
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atomic_t pending_ssr;
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atomic_t pending_powerup;
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int stop_threads;
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atomic_t device_wake;
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u32 ssr;
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};
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@ -453,8 +454,10 @@ struct mhi_device_ctxt {
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u32 outbound_evmod_rate;
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struct mhi_counters counters;
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struct mhi_flags flags;
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u32 device_wake_asserted;
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rwlock_t xfer_lock;
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atomic_t m2_transition;
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struct hrtimer m1_timer;
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ktime_t m1_timeout;
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ktime_t ul_acc_tmr_timeout;
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@ -115,6 +115,7 @@ static enum MHI_STATUS mhi_init_sync(struct mhi_device_ctxt *mhi_dev_ctxt)
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rwlock_init(&mhi_dev_ctxt->xfer_lock);
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mutex_init(&mhi_dev_ctxt->mhi_link_state);
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mutex_init(&mhi_dev_ctxt->pm_lock);
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atomic_set(&mhi_dev_ctxt->m2_transition, 0);
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return MHI_STATUS_SUCCESS;
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db_write_lock_free:
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@ -368,14 +369,6 @@ static enum MHI_STATUS mhi_cmd_ring_init(struct mhi_cmd_ctxt *cmd_ctxt,
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static enum MHI_STATUS mhi_init_timers(struct mhi_device_ctxt *mhi_dev_ctxt)
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{
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hrtimer_init(&mhi_dev_ctxt->m1_timer,
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CLOCK_MONOTONIC,
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HRTIMER_MODE_REL);
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mhi_dev_ctxt->m1_timeout =
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ktime_set(0, MHI_M1_ENTRY_DELAY_MS * 1E6L);
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mhi_dev_ctxt->m1_timer.function = mhi_initiate_m1;
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mhi_log(MHI_MSG_CRITICAL | MHI_DBG_POWER,
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"Starting M1 timer\n");
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return MHI_STATUS_SUCCESS;
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}
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@ -15,6 +15,7 @@
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#define MHI_IPC_LOG_PAGES (100)
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#define MHI_LOG_SIZE 0x1000
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#define MHI_LINK_STABILITY_WAIT_MS 100
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#define MHI_DEVICE_WAKE_DBOUNCE_TIMEOUT_MS 10
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#define MHI_MAX_LINK_RETRIES 9
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#define DT_WAIT_RETRIES 30
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#define MHI_MAX_SUSPEND_RETRIES 1000
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@ -54,10 +55,12 @@
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#define MHI_DATA_SEG_WINDOW_START_ADDR 0x0ULL
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#define MHI_DATA_SEG_WINDOW_END_ADDR 0x3E800000ULL
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#define MHI_M1_ENTRY_DELAY_MS 100
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#define MHI_M2_DEBOUNCE_TMR_MS 10
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#define MHI_XFER_DB_INTERVAL 8
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#define MHI_EV_DB_INTERVAL 32
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#define MHI_DEV_WAKE_DB 127
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#define MHI_HANDLE_MAGIC 0x12344321
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/* PCIe Device Info */
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@ -497,6 +497,28 @@ void mhi_update_chan_db(struct mhi_device_ctxt *mhi_dev_ctxt,
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chan, db_value);
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}
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}
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enum MHI_STATUS mhi_check_m2_transition(struct mhi_device_ctxt *mhi_dev_ctxt)
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{
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enum MHI_STATUS ret_val = MHI_STATUS_SUCCESS;
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mhi_log(MHI_MSG_VERBOSE, "state = %d\n", mhi_dev_ctxt->mhi_state);
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if (mhi_dev_ctxt->mhi_state == MHI_STATE_M2) {
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mhi_log(MHI_MSG_INFO, "M2 Transition flag value = %d\n",
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(atomic_read(&mhi_dev_ctxt->m2_transition)));
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if ((atomic_read(&mhi_dev_ctxt->m2_transition)) == 0) {
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if (mhi_dev_ctxt->flags.link_up) {
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mhi_assert_device_wake(mhi_dev_ctxt);
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ret_val = MHI_STATUS_CHAN_NOT_READY;
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}
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} else{
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mhi_log(MHI_MSG_INFO, "m2_transition flag is set\n");
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ret_val = MHI_STATUS_CHAN_NOT_READY;
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}
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} else {
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ret_val = MHI_STATUS_SUCCESS;
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}
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return ret_val;
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}
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static inline enum MHI_STATUS mhi_queue_tre(struct mhi_device_ctxt
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*mhi_dev_ctxt,
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@ -516,11 +538,12 @@ static inline enum MHI_STATUS mhi_queue_tre(struct mhi_device_ctxt
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"Queued outbound pkt. Pending Acks %d\n",
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atomic_read(&mhi_dev_ctxt->counters.outbound_acks));
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}
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if (likely((((
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(mhi_dev_ctxt->mhi_state == MHI_STATE_M0) ||
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(mhi_dev_ctxt->mhi_state == MHI_STATE_M1)) &&
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ret_val = mhi_check_m2_transition(mhi_dev_ctxt);
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if (likely(((ret_val == MHI_STATUS_SUCCESS) &&
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(((mhi_dev_ctxt->mhi_state == MHI_STATE_M0) ||
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(mhi_dev_ctxt->mhi_state == MHI_STATE_M1))) &&
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(chan_ctxt->mhi_chan_state != MHI_CHAN_STATE_ERROR)) &&
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(!mhi_dev_ctxt->flags.pending_M3)))) {
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(!mhi_dev_ctxt->flags.pending_M3))) {
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if (likely(type == MHI_RING_TYPE_XFER_RING)) {
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spin_lock_irqsave(&mhi_dev_ctxt->db_write_lock[chan],
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flags);
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@ -574,14 +597,6 @@ enum MHI_STATUS mhi_queue_xfer(struct mhi_client_handle *client_handle,
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chan = client_handle->chan;
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pm_runtime_get(&mhi_dev_ctxt->dev_info->plat_dev->dev);
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/* Bump up the vote for pending data */
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read_lock_irqsave(&mhi_dev_ctxt->xfer_lock, flags);
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atomic_inc(&mhi_dev_ctxt->flags.data_pending);
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if (mhi_dev_ctxt->flags.link_up)
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mhi_assert_device_wake(mhi_dev_ctxt);
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read_unlock_irqrestore(&mhi_dev_ctxt->xfer_lock, flags);
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pkt_loc = mhi_dev_ctxt->mhi_local_chan_ctxt[chan].wp;
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pkt_loc->data_tx_pkt.buffer_ptr = buf;
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pkt_loc->type.info = mhi_flags;
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@ -602,19 +617,20 @@ enum MHI_STATUS mhi_queue_xfer(struct mhi_client_handle *client_handle,
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ret_val = ctxt_add_element(&mhi_dev_ctxt->mhi_local_chan_ctxt[chan],
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(void *)&pkt_loc);
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if (unlikely(MHI_STATUS_SUCCESS != ret_val)) {
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mhi_log(MHI_MSG_CRITICAL,
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mhi_log(MHI_MSG_VERBOSE,
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"Failed to insert trb in xfer ring\n");
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goto error;
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}
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read_lock_irqsave(&mhi_dev_ctxt->xfer_lock, flags);
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atomic_inc(&mhi_dev_ctxt->flags.data_pending);
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ret_val = mhi_queue_tre(mhi_dev_ctxt, chan, MHI_RING_TYPE_XFER_RING);
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if (unlikely(MHI_STATUS_SUCCESS != ret_val))
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mhi_log(MHI_MSG_VERBOSE, "Failed queue TRE.\n");
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atomic_dec(&mhi_dev_ctxt->flags.data_pending);
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read_unlock_irqrestore(&mhi_dev_ctxt->xfer_lock, flags);
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error:
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atomic_dec(&mhi_dev_ctxt->flags.data_pending);
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pm_runtime_mark_last_busy(&mhi_dev_ctxt->dev_info->plat_dev->dev);
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pm_runtime_put_noidle(&mhi_dev_ctxt->dev_info->plat_dev->dev);
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return ret_val;
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@ -645,18 +661,18 @@ enum MHI_STATUS mhi_send_cmd(struct mhi_device_ctxt *mhi_dev_ctxt,
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mhi_dev_ctxt->dev_exec_env,
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chan, cmd);
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mhi_assert_device_wake(mhi_dev_ctxt);
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atomic_inc(&mhi_dev_ctxt->flags.data_pending);
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pm_runtime_get(&mhi_dev_ctxt->dev_info->plat_dev->dev);
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/*
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* If there is a cmd pending a device confirmation,
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* do not send anymore for this channel
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*/
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if (MHI_CMD_PENDING == mhi_dev_ctxt->mhi_chan_pend_cmd_ack[chan]) {
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mhi_log(MHI_MSG_ERROR, "Cmd Pending on chan %d", chan);
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ret_val = MHI_STATUS_CMD_PENDING;
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goto error_invalid;
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}
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atomic_inc(&mhi_dev_ctxt->flags.data_pending);
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from_state =
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mhi_dev_ctxt->mhi_ctrl_seg->mhi_cc_list[chan].mhi_chan_state;
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@ -1341,21 +1357,38 @@ int mhi_get_epid(struct mhi_client_handle *client_handle)
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int mhi_assert_device_wake(struct mhi_device_ctxt *mhi_dev_ctxt)
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{
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mhi_log(MHI_MSG_VERBOSE, "GPIO %d\n",
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mhi_dev_ctxt->dev_props->device_wake_gpio);
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gpio_direction_output(mhi_dev_ctxt->dev_props->device_wake_gpio, 1);
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if ((mhi_dev_ctxt->channel_db_addr) &&
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(mhi_dev_ctxt->flags.link_up)) {
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mhi_log(MHI_MSG_VERBOSE, "LPM %d\n",
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mhi_dev_ctxt->enable_lpm);
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atomic_set(&mhi_dev_ctxt->flags.device_wake, 1);
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mhi_write_db(mhi_dev_ctxt,
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mhi_dev_ctxt->channel_db_addr,
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MHI_DEV_WAKE_DB, 1);
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mhi_dev_ctxt->device_wake_asserted = 1;
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} else {
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mhi_log(MHI_MSG_VERBOSE, "LPM %d\n", mhi_dev_ctxt->enable_lpm);
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}
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return 0;
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}
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inline int mhi_deassert_device_wake(struct mhi_device_ctxt *mhi_dev_ctxt)
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{
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mhi_log(MHI_MSG_VERBOSE, "GPIO %d\n",
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mhi_dev_ctxt->dev_props->device_wake_gpio);
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if (mhi_dev_ctxt->enable_lpm)
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gpio_direction_output(
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mhi_dev_ctxt->dev_props->device_wake_gpio, 0);
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else
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mhi_log(MHI_MSG_VERBOSE, "LPM Enabled\n");
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if ((mhi_dev_ctxt->enable_lpm) &&
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(atomic_read(&mhi_dev_ctxt->flags.device_wake)) &&
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(mhi_dev_ctxt->channel_db_addr != NULL) &&
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(mhi_dev_ctxt->flags.link_up)) {
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mhi_log(MHI_MSG_VERBOSE, "LPM %d\n", mhi_dev_ctxt->enable_lpm);
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atomic_set(&mhi_dev_ctxt->flags.device_wake, 0);
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mhi_write_db(mhi_dev_ctxt, mhi_dev_ctxt->channel_db_addr,
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MHI_DEV_WAKE_DB, 0);
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mhi_dev_ctxt->device_wake_asserted = 0;
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} else {
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mhi_log(MHI_MSG_VERBOSE, "LPM %d DEV_WAKE %d link %d\n",
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mhi_dev_ctxt->enable_lpm,
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atomic_read(&mhi_dev_ctxt->flags.device_wake),
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mhi_dev_ctxt->flags.link_up);
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}
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return 0;
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}
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@ -113,46 +113,6 @@ exit:
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return r;
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}
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enum hrtimer_restart mhi_initiate_m1(struct hrtimer *timer)
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{
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int ret_val = 0;
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unsigned long flags;
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ktime_t curr_time, timer_inc;
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struct mhi_device_ctxt *mhi_dev_ctxt = container_of(timer,
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struct mhi_device_ctxt,
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m1_timer);
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write_lock_irqsave(&mhi_dev_ctxt->xfer_lock, flags);
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/*
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* We will allow M1 if no data is pending, the current
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* state is M0 and no M3 transition is pending
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*/
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if ((0 == atomic_read(&mhi_dev_ctxt->flags.data_pending)) &&
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(MHI_STATE_M1 == mhi_dev_ctxt->mhi_state ||
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MHI_STATE_M0 == mhi_dev_ctxt->mhi_state) &&
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(0 == mhi_dev_ctxt->flags.pending_M3) &&
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mhi_dev_ctxt->flags.mhi_initialized &&
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(0 == atomic_read(
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&mhi_dev_ctxt->counters.outbound_acks))) {
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mhi_dev_ctxt->mhi_state = MHI_STATE_M1;
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ret_val = mhi_deassert_device_wake(mhi_dev_ctxt);
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mhi_dev_ctxt->counters.m0_m1++;
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if (ret_val)
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mhi_log(MHI_MSG_ERROR,
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"Could not set DEVICE WAKE GPIO LOW\n");
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}
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write_unlock_irqrestore(&mhi_dev_ctxt->xfer_lock, flags);
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if (mhi_dev_ctxt->mhi_state == MHI_STATE_M0 ||
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mhi_dev_ctxt->mhi_state == MHI_STATE_M1 ||
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mhi_dev_ctxt->mhi_state == MHI_STATE_READY) {
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curr_time = ktime_get();
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timer_inc = ktime_set(0, MHI_M1_ENTRY_DELAY_MS * 1E6L);
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hrtimer_forward(timer, curr_time, timer_inc);
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return HRTIMER_RESTART;
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}
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return HRTIMER_NORESTART;
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}
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int mhi_init_pm_sysfs(struct device *dev)
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{
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return sysfs_create_group(&dev->kobj, &mhi_attribute_group);
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@ -122,11 +122,13 @@ static enum MHI_STATUS process_m0_transition(
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} else if (mhi_dev_ctxt->mhi_state == MHI_STATE_READY) {
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mhi_log(MHI_MSG_INFO,
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"Transitioning from READY.\n");
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} else if (mhi_dev_ctxt->mhi_state == MHI_STATE_M1) {
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mhi_log(MHI_MSG_INFO,
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"Transitioning from M1.\n");
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} else {
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mhi_log(MHI_MSG_INFO,
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"MHI State %d link state %d. Quitting\n",
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mhi_dev_ctxt->mhi_state, mhi_dev_ctxt->flags.link_up);
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goto exit;
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}
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read_lock_irqsave(&mhi_dev_ctxt->xfer_lock, flags);
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@ -147,20 +149,20 @@ static enum MHI_STATUS process_m0_transition(
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"Could not set bus frequency ret: %d\n",
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ret_val);
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mhi_dev_ctxt->flags.pending_M0 = 0;
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wake_up_interruptible(mhi_dev_ctxt->M0_event);
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if (ret_val == -ERESTARTSYS)
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mhi_log(MHI_MSG_CRITICAL,
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"Pending restart detected\n");
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ret_val = hrtimer_start(&mhi_dev_ctxt->m1_timer,
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mhi_dev_ctxt->m1_timeout,
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HRTIMER_MODE_REL);
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if (atomic_read(&mhi_dev_ctxt->flags.pending_powerup)) {
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atomic_set(&mhi_dev_ctxt->flags.pending_ssr, 0);
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atomic_set(&mhi_dev_ctxt->flags.pending_powerup, 0);
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}
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mhi_log(MHI_MSG_VERBOSE, "Starting M1 timer, ret %d\n", ret_val);
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exit:
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wake_up_interruptible(mhi_dev_ctxt->M0_event);
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if (ret_val == -ERESTARTSYS)
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mhi_log(MHI_MSG_CRITICAL,
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"Pending restart detected\n");
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write_lock_irqsave(&mhi_dev_ctxt->xfer_lock, flags);
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if ((!mhi_dev_ctxt->flags.pending_M3) &&
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(mhi_dev_ctxt->flags.link_up))
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mhi_deassert_device_wake(mhi_dev_ctxt);
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write_unlock_irqrestore(&mhi_dev_ctxt->xfer_lock, flags);
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mhi_log(MHI_MSG_INFO, "Exited\n");
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return MHI_STATUS_SUCCESS;
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}
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@ -176,25 +178,10 @@ static enum MHI_STATUS process_m1_transition(
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"Processing M1 state transition from state %d\n",
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mhi_dev_ctxt->mhi_state);
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mhi_dev_ctxt->counters.m0_m1++;
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mhi_log(MHI_MSG_VERBOSE,
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"Cancelling Inactivity timer\n");
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switch (hrtimer_try_to_cancel(&mhi_dev_ctxt->m1_timer)) {
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case 0:
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mhi_log(MHI_MSG_VERBOSE,
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"Timer was not active\n");
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break;
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case 1:
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mhi_log(MHI_MSG_VERBOSE,
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"Timer was active\n");
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break;
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case -1:
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mhi_log(MHI_MSG_VERBOSE,
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"Timer executing and can't stop\n");
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break;
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}
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write_lock_irqsave(&mhi_dev_ctxt->xfer_lock, flags);
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if (!mhi_dev_ctxt->flags.pending_M3) {
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mhi_log(MHI_MSG_INFO, "Setting M2 Transition flag\n");
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atomic_inc(&mhi_dev_ctxt->m2_transition);
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mhi_dev_ctxt->mhi_state = MHI_STATE_M2;
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mhi_log(MHI_MSG_INFO, "Allowing transition to M2\n");
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mhi_reg_write_field(mhi_dev_ctxt,
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@ -206,24 +193,32 @@ static enum MHI_STATUS process_m1_transition(
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mhi_dev_ctxt->counters.m1_m2++;
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}
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write_unlock_irqrestore(&mhi_dev_ctxt->xfer_lock, flags);
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ret_val =
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mhi_set_bus_request(mhi_dev_ctxt,
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0);
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ret_val = mhi_set_bus_request(mhi_dev_ctxt, 0);
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if (ret_val)
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mhi_log(MHI_MSG_INFO, "Failed to update bus request\n");
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mhi_log(MHI_MSG_INFO, "Start Deferred Suspend usage_count: %d\n",
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atomic_read(
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&mhi_dev_ctxt->dev_info->plat_dev->dev.power.usage_count));
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mhi_log(MHI_MSG_INFO, "Debouncing M2\n");
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msleep(MHI_M2_DEBOUNCE_TMR_MS);
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||||
pm_runtime_mark_last_busy(&mhi_dev_ctxt->dev_info->plat_dev->dev);
|
||||
r = pm_request_autosuspend(&mhi_dev_ctxt->dev_info->plat_dev->dev);
|
||||
if (r) {
|
||||
mhi_log(MHI_MSG_ERROR, "Failed to remove counter ret %d\n", r);
|
||||
mhi_log(MHI_MSG_ERROR, "Usage counter is %d\n",
|
||||
atomic_read(
|
||||
&mhi_dev_ctxt->dev_info->plat_dev->dev.power.usage_count));
|
||||
write_lock_irqsave(&mhi_dev_ctxt->xfer_lock, flags);
|
||||
mhi_log(MHI_MSG_INFO, "Pending acks %d\n",
|
||||
atomic_read(&mhi_dev_ctxt->counters.outbound_acks));
|
||||
if (atomic_read(&mhi_dev_ctxt->counters.outbound_acks) ||
|
||||
mhi_dev_ctxt->flags.pending_M3) {
|
||||
mhi_assert_device_wake(mhi_dev_ctxt);
|
||||
} else {
|
||||
pm_runtime_mark_last_busy(
|
||||
&mhi_dev_ctxt->dev_info->plat_dev->dev);
|
||||
r = pm_request_autosuspend(
|
||||
&mhi_dev_ctxt->dev_info->plat_dev->dev);
|
||||
if (r) {
|
||||
mhi_log(MHI_MSG_ERROR,
|
||||
"Failed to remove counter ret %d\n", r);
|
||||
}
|
||||
}
|
||||
atomic_set(&mhi_dev_ctxt->m2_transition, 0);
|
||||
mhi_log(MHI_MSG_INFO, "M2 transition complete.\n");
|
||||
write_unlock_irqrestore(&mhi_dev_ctxt->xfer_lock, flags);
|
||||
|
||||
return MHI_STATUS_SUCCESS;
|
||||
}
|
||||
|
@ -235,19 +230,6 @@ static enum MHI_STATUS process_m3_transition(
|
|||
unsigned long flags;
|
||||
mhi_log(MHI_MSG_INFO,
|
||||
"Processing M3 state transition\n");
|
||||
switch (hrtimer_try_to_cancel(&mhi_dev_ctxt->m1_timer)) {
|
||||
case 0:
|
||||
mhi_log(MHI_MSG_VERBOSE,
|
||||
"Timer was not active\n");
|
||||
break;
|
||||
case 1:
|
||||
mhi_log(MHI_MSG_VERBOSE,
|
||||
"Timer was active\n");
|
||||
break;
|
||||
case -1:
|
||||
mhi_log(MHI_MSG_VERBOSE,
|
||||
"Timer executing and can't stop\n");
|
||||
}
|
||||
write_lock_irqsave(&mhi_dev_ctxt->xfer_lock, flags);
|
||||
mhi_dev_ctxt->mhi_state = MHI_STATE_M3;
|
||||
mhi_dev_ctxt->flags.pending_M3 = 0;
|
||||
|
@ -284,19 +266,6 @@ static enum MHI_STATUS mhi_process_link_down(
|
|||
msleep(20);
|
||||
}
|
||||
|
||||
switch (hrtimer_try_to_cancel(&mhi_dev_ctxt->m1_timer)) {
|
||||
case 0:
|
||||
mhi_log(MHI_MSG_CRITICAL,
|
||||
"Timer was not active\n");
|
||||
break;
|
||||
case 1:
|
||||
mhi_log(MHI_MSG_CRITICAL,
|
||||
"Timer was active\n");
|
||||
break;
|
||||
case -1:
|
||||
mhi_log(MHI_MSG_CRITICAL,
|
||||
"Timer executing and can't stop\n");
|
||||
}
|
||||
r = mhi_set_bus_request(mhi_dev_ctxt, 0);
|
||||
if (r)
|
||||
mhi_log(MHI_MSG_INFO,
|
||||
|
@ -578,6 +547,7 @@ static void enable_clients(struct mhi_device_ctxt *mhi_dev_ctxt,
|
|||
mhi_dev_ctxt->client_handle_list[i];
|
||||
mhi_notify_client(client_handle,
|
||||
MHI_CB_MHI_ENABLED);
|
||||
mhi_deassert_device_wake(mhi_dev_ctxt);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
@ -897,7 +867,11 @@ int mhi_initiate_m3(struct mhi_device_ctxt *mhi_dev_ctxt)
|
|||
"Triggering wake out of M2\n");
|
||||
write_lock_irqsave(&mhi_dev_ctxt->xfer_lock, flags);
|
||||
mhi_dev_ctxt->flags.pending_M3 = 1;
|
||||
mhi_assert_device_wake(mhi_dev_ctxt);
|
||||
if ((atomic_read(&mhi_dev_ctxt->m2_transition)) == 0) {
|
||||
mhi_log(MHI_MSG_INFO,
|
||||
"M2_transition not set\n");
|
||||
mhi_assert_device_wake(mhi_dev_ctxt);
|
||||
}
|
||||
write_unlock_irqrestore(&mhi_dev_ctxt->xfer_lock, flags);
|
||||
r = wait_event_interruptible_timeout(*mhi_dev_ctxt->M0_event,
|
||||
mhi_dev_ctxt->mhi_state == MHI_STATE_M0 ||
|
||||
|
@ -943,12 +917,6 @@ int mhi_initiate_m3(struct mhi_device_ctxt *mhi_dev_ctxt)
|
|||
r = -EAGAIN;
|
||||
goto exit;
|
||||
}
|
||||
r = hrtimer_cancel(&mhi_dev_ctxt->m1_timer);
|
||||
if (r)
|
||||
mhi_log(MHI_MSG_INFO, "Cancelled M1 timer, timer was active\n");
|
||||
else
|
||||
mhi_log(MHI_MSG_INFO,
|
||||
"Cancelled M1 timer, timer was not active\n");
|
||||
write_lock_irqsave(&mhi_dev_ctxt->xfer_lock, flags);
|
||||
if (mhi_dev_ctxt->flags.pending_M0) {
|
||||
write_unlock_irqrestore(&mhi_dev_ctxt->xfer_lock, flags);
|
||||
|
@ -974,17 +942,12 @@ int mhi_initiate_m3(struct mhi_device_ctxt *mhi_dev_ctxt)
|
|||
mhi_dev_ctxt->flags.pending_M3 = 0;
|
||||
goto exit;
|
||||
break;
|
||||
case -ERESTARTSYS:
|
||||
mhi_log(MHI_MSG_CRITICAL,
|
||||
"Going Down...\n");
|
||||
goto exit;
|
||||
break;
|
||||
|
||||
default:
|
||||
mhi_log(MHI_MSG_INFO,
|
||||
"M3 completion received\n");
|
||||
break;
|
||||
}
|
||||
mhi_deassert_device_wake(mhi_dev_ctxt);
|
||||
mhi_turn_off_pcie_link(mhi_dev_ctxt);
|
||||
r = mhi_set_bus_request(mhi_dev_ctxt, 0);
|
||||
if (r)
|
||||
|
@ -996,6 +959,7 @@ exit:
|
|||
write_unlock_irqrestore(&mhi_dev_ctxt->xfer_lock, flags);
|
||||
ring_all_chan_dbs(mhi_dev_ctxt);
|
||||
atomic_dec(&mhi_dev_ctxt->flags.data_pending);
|
||||
mhi_deassert_device_wake(mhi_dev_ctxt);
|
||||
}
|
||||
mhi_dev_ctxt->flags.pending_M3 = 0;
|
||||
mutex_unlock(&mhi_dev_ctxt->pm_lock);
|
||||
|
|
Loading…
Add table
Reference in a new issue