clk: msm: clock: Support peripheral clocks on MSMHAMSTER

Add support for controlling the peripheral clocks on
MSM HAMSTER.

CRs-Fixed: 1004885
Change-Id: If77ad3d662fbba145374abe38ea14a1a6e540fee
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
This commit is contained in:
Deepak Katragadda 2016-04-19 10:49:21 -07:00 committed by Kyle Yan
parent b45c4f19d9
commit c96bf51dfb
4 changed files with 23 additions and 0 deletions

View file

@ -64,6 +64,7 @@ Required properties:
"qcom,gcc-mdm9607" "qcom,gcc-mdm9607"
"qcom,cc-debug-mdm9607" "qcom,cc-debug-mdm9607"
"qcom,gcc-cobalt" "qcom,gcc-cobalt"
"qcom,gcc-hamster"
"qcom,cc-debug-cobalt" "qcom,cc-debug-cobalt"
"qcom,gpucc-cobalt" "qcom,gpucc-cobalt"
"qcom,gfxcc-cobalt" "qcom,gfxcc-cobalt"

View file

@ -2004,6 +2004,18 @@ static struct gate_clk gcc_ufs_rx_symbol_0_clk = {
}, },
}; };
static struct gate_clk gcc_ufs_rx_symbol_1_clk = {
.en_reg = GCC_UFS_RX_SYMBOL_1_CBCR,
.en_mask = BIT(0),
.delay_us = 500,
.base = &virt_base,
.c = {
.dbg_name = "gcc_ufs_rx_symbol_1_clk",
.ops = &clk_ops_gate,
CLK_INIT(gcc_ufs_rx_symbol_1_clk.c),
},
};
static struct gate_clk gcc_ufs_tx_symbol_0_clk = { static struct gate_clk gcc_ufs_tx_symbol_0_clk = {
.en_reg = GCC_UFS_TX_SYMBOL_0_CBCR, .en_reg = GCC_UFS_TX_SYMBOL_0_CBCR,
.en_mask = BIT(0), .en_mask = BIT(0),
@ -2345,6 +2357,7 @@ static struct mux_clk gcc_debug_mux = {
{ &gcc_ufs_ahb_clk.c, 0x00eb }, { &gcc_ufs_ahb_clk.c, 0x00eb },
{ &gcc_ufs_tx_symbol_0_clk.c, 0x00ec }, { &gcc_ufs_tx_symbol_0_clk.c, 0x00ec },
{ &gcc_ufs_rx_symbol_0_clk.c, 0x00ed }, { &gcc_ufs_rx_symbol_0_clk.c, 0x00ed },
{ &gcc_ufs_rx_symbol_1_clk.c, 0x0162 },
{ &gcc_ufs_unipro_core_clk.c, 0x00f0 }, { &gcc_ufs_unipro_core_clk.c, 0x00f0 },
{ &gcc_ufs_ice_core_clk.c, 0x00f1 }, { &gcc_ufs_ice_core_clk.c, 0x00f1 },
{ &gcc_dcc_ahb_clk.c, 0x0119 }, { &gcc_dcc_ahb_clk.c, 0x0119 },
@ -2578,6 +2591,7 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = {
CLK_LIST(gcc_ufs_ice_core_clk), CLK_LIST(gcc_ufs_ice_core_clk),
CLK_LIST(gcc_ufs_phy_aux_clk), CLK_LIST(gcc_ufs_phy_aux_clk),
CLK_LIST(gcc_ufs_rx_symbol_0_clk), CLK_LIST(gcc_ufs_rx_symbol_0_clk),
CLK_LIST(gcc_ufs_rx_symbol_1_clk),
CLK_LIST(gcc_ufs_tx_symbol_0_clk), CLK_LIST(gcc_ufs_tx_symbol_0_clk),
CLK_LIST(gcc_ufs_unipro_core_clk), CLK_LIST(gcc_ufs_unipro_core_clk),
CLK_LIST(gcc_usb30_master_clk), CLK_LIST(gcc_usb30_master_clk),
@ -2611,6 +2625,7 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev)
struct resource *res; struct resource *res;
u32 regval; u32 regval;
int ret; int ret;
bool is_vq = 0;
ret = vote_bimc(&bimc_clk, INT_MAX); ret = vote_bimc(&bimc_clk, INT_MAX);
if (ret < 0) if (ret < 0)
@ -2659,6 +2674,10 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev)
if (ret < 0) if (ret < 0)
return ret; return ret;
is_vq = of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-hamster");
if (!is_vq)
gcc_ufs_rx_symbol_1_clk.c.ops = &clk_ops_dummy;
ret = of_msm_clock_register(pdev->dev.of_node, msm_clocks_gcc_cobalt, ret = of_msm_clock_register(pdev->dev.of_node, msm_clocks_gcc_cobalt,
ARRAY_SIZE(msm_clocks_gcc_cobalt)); ARRAY_SIZE(msm_clocks_gcc_cobalt));
if (ret) if (ret)
@ -2687,6 +2706,7 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev)
static struct of_device_id msm_clock_gcc_match_table[] = { static struct of_device_id msm_clock_gcc_match_table[] = {
{ .compatible = "qcom,gcc-cobalt" }, { .compatible = "qcom,gcc-cobalt" },
{ .compatible = "qcom,gcc-hamster" },
{} {}
}; };

View file

@ -230,6 +230,7 @@
#define clk_gcc_ufs_ice_core_clk 0x310b0710 #define clk_gcc_ufs_ice_core_clk 0x310b0710
#define clk_gcc_ufs_phy_aux_clk 0x17acc8fb #define clk_gcc_ufs_phy_aux_clk 0x17acc8fb
#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c #define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c
#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde
#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a #define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a
#define clk_ufs_tx_symbol_0_clk 0xb3fcd0f7 #define clk_ufs_tx_symbol_0_clk 0xb3fcd0f7
#define clk_ufs_rx_symbol_0_clk 0x17a0f1cd #define clk_ufs_rx_symbol_0_clk 0x17a0f1cd

View file

@ -198,6 +198,7 @@
#define GCC_UFS_AHB_CBCR 0x7500C #define GCC_UFS_AHB_CBCR 0x7500C
#define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010 #define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010
#define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014 #define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014
#define GCC_UFS_RX_SYMBOL_1_CBCR 0x7605C
#define GCC_UFS_UNIPRO_CORE_CBCR 0x76008 #define GCC_UFS_UNIPRO_CORE_CBCR 0x76008
#define GCC_UFS_ICE_CORE_CBCR 0x7600C #define GCC_UFS_ICE_CORE_CBCR 0x7600C
#define GCC_UFS_PHY_AUX_CBCR 0x76040 #define GCC_UFS_PHY_AUX_CBCR 0x76040