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Merge "clk: qcom: gcc: Cleanup code for GCC clocks"

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Linux Build Service Account 2016-11-07 22:29:01 -08:00 • committed by Gerrit - the friendly Code Review server
commit c98650b20a
2 changed files with 29 additions and 28 deletions
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15
drivers/clk/qcom/gcc-msmfalcon.c
View file

@ -35,8 +35,8 @@
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
static DEFINE_VDD_REGULATORS(vdd_dig_ao, VDD_DIG_NUM, 1, vdd_corner, NULL);
static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_dig_ao, VDD_DIG_NUM, 1, vdd_corner);
enum {
P_CORE_BI_PLL_TEST_SE,
@ -2201,7 +2201,7 @@ static struct clk_branch gcc_ufs_axi_hw_ctl_clk = {
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_hw_ctl_ops,
.ops = &clk_branch2_ops,
},
},
};
@ -2249,7 +2249,7 @@ static struct clk_branch gcc_ufs_ice_core_hw_ctl_clk = {
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_hw_ctl_ops,
.ops = &clk_branch2_ops,
},
},
};
@ -2284,7 +2284,7 @@ static struct clk_branch gcc_ufs_phy_aux_hw_ctl_clk = {
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_hw_ctl_ops,
.ops = &clk_branch2_ops,
},
},
};
@ -2355,7 +2355,7 @@ static struct clk_branch gcc_ufs_unipro_core_hw_ctl_clk = {
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_hw_ctl_ops,
.ops = &clk_branch2_ops,
},
},
};
@ -2753,9 +2753,8 @@ MODULE_DEVICE_TABLE(of, gcc_falcon_match_table);
static int gcc_falcon_probe(struct platform_device *pdev)
{
int ret = 0, i;
int ret = 0;
struct regmap *regmap;
struct clk *clk;
regmap = qcom_cc_map(pdev, &gcc_falcon_desc);
if (IS_ERR(regmap))

42
drivers/clk/qcom/vdd-level-falcon.h
View file

@ -19,50 +19,52 @@
#define VDD_DIG_FMAX_MAP1(l1, f1) \
.vdd_class = &vdd_dig, \
.fmax = (unsigned long[VDD_DIG_NUM]) { \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
}, \
.num_fmax = VDD_DIG_NUM
.num_rate_max = VDD_DIG_NUM
#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
.vdd_class = &vdd_dig, \
.fmax = (unsigned long[VDD_DIG_NUM]) { \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
}, \
.num_fmax = VDD_DIG_NUM
.num_rate_max = VDD_DIG_NUM
#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
.vdd_class = &vdd_dig, \
.fmax = (unsigned long[VDD_DIG_NUM]) { \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
[VDD_DIG_##l3] = (f3), \
}, \
.num_fmax = VDD_DIG_NUM
.num_rate_max = VDD_DIG_NUM
#define VDD_DIG_FMAX_MAP4(l1, f1, l2, f2, l3, f3, l4, f4) \
.vdd_class = &vdd_dig, \
.fmax = (unsigned long[VDD_DIG_NUM]) { \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
[VDD_DIG_##l3] = (f3), \
[VDD_DIG_##l4] = (f4), \
}, \
.num_fmax = VDD_DIG_NUM
.num_rate_max = VDD_DIG_NUM
#define VDD_DIG_FMAX_MAP5(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5) \
.vdd_class = &vdd_dig, \
.fmax = (unsigned long[VDD_DIG_NUM]) { \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
[VDD_DIG_##l3] = (f3), \
[VDD_DIG_##l4] = (f4), \
[VDD_DIG_##l5] = (f5), \
}, \
.num_fmax = VDD_DIG_NUM
.num_rate_max = VDD_DIG_NUM
#define VDD_DIG_FMAX_MAP6(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6) \
.vdd_class = &vdd_dig, \
.fmax = (unsigned long[VDD_DIG_NUM]) { \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
[VDD_DIG_##l3] = (f3), \
@ -70,12 +72,12 @@
[VDD_DIG_##l5] = (f5), \
[VDD_DIG_##l6] = (f6), \
}, \
.num_fmax = VDD_DIG_NUM
.num_rate_max = VDD_DIG_NUM
#define VDD_DIG_FMAX_MAP7(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6, \
l7, f7) \
.vdd_class = &vdd_dig, \
.fmax = (unsigned long[VDD_DIG_NUM]) { \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
[VDD_DIG_##l3] = (f3), \
@ -84,27 +86,27 @@
[VDD_DIG_##l6] = (f6), \
[VDD_DIG_##l7] = (f7), \
}, \
.num_fmax = VDD_DIG_NUM
.num_rate_max = VDD_DIG_NUM
#define VDD_DIG_FMAX_MAP1_AO(l1, f1) \
.vdd_class = &vdd_dig_ao, \
.fmax = (unsigned long[VDD_DIG_NUM]) { \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
}, \
.num_fmax = VDD_DIG_NUM
.num_rate_max = VDD_DIG_NUM
#define VDD_DIG_FMAX_MAP3_AO(l1, f1, l2, f2, l3, f3) \
.vdd_class = &vdd_dig_ao, \
.fmax = (unsigned long[VDD_DIG_NUM]) { \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
[VDD_DIG_##l3] = (f3), \
}, \
.num_fmax = VDD_DIG_NUM
.num_rate_max = VDD_DIG_NUM
#define VDD_GPU_PLL_FMAX_MAP6(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6) \
.vdd_class = &vdd_mx, \
.fmax = (unsigned long[VDD_DIG_NUM]) { \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
[VDD_DIG_##l3] = (f3), \
@ -112,7 +114,7 @@
[VDD_DIG_##l5] = (f5), \
[VDD_DIG_##l6] = (f6), \
}, \
.num_fmax = VDD_DIG_NUM
.num_rate_max = VDD_DIG_NUM
enum vdd_dig_levels {
VDD_DIG_NONE,