From c9deb68c63e3ca36a71473ed336e03aea07a0c99 Mon Sep 17 00:00:00 2001 From: Padmanabhan Komanduru Date: Wed, 25 Jan 2017 13:26:33 +0530 Subject: [PATCH] msm: mdss: dp: add support for DP PHY register offset property Add a DT property to specify DP PHY register offset for display port. There is a register offset difference for a few DP PHY registers between msm8998 and SDM660 and hence this is needed. Add changes to program DP PHY registers by accounting for this register offset difference wherever applicable. Change-Id: I515432830ae6c3fa3223f0c97af7b0a3965afc40 Signed-off-by: Padmanabhan Komanduru --- .../devicetree/bindings/fb/mdss-dp.txt | 2 ++ drivers/video/fbdev/msm/mdss_dp.c | 13 ++++++-- drivers/video/fbdev/msm/mdss_dp.h | 1 + drivers/video/fbdev/msm/mdss_dp_util.c | 33 ++++++++++--------- drivers/video/fbdev/msm/mdss_dp_util.h | 5 +-- 5 files changed, 34 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/fb/mdss-dp.txt b/Documentation/devicetree/bindings/fb/mdss-dp.txt index c9c882154c39..7bf7b9bacb60 100644 --- a/Documentation/devicetree/bindings/fb/mdss-dp.txt +++ b/Documentation/devicetree/bindings/fb/mdss-dp.txt @@ -53,6 +53,7 @@ Optional properties: controller. These pin configurations are installed in the pinctrl device node. Refer to pinctrl-bindings.txt - qcom,logical2physical-lane-map: An array that specifies the DP logical to physical lane map setting. +- qcom,phy-register-offset: An integer specifying the offset value of DP PHY register space. Example: mdss_dp_ctrl: qcom,dp_ctrl@c990000 { @@ -87,6 +88,7 @@ Example: qcom,aux-cfg-settings = [00 13 00 10 0a 26 0a 03 8b 03]; qcom,logical2physical-lane-map = [02 03 01 00]; + qcom,phy-register-offset = <0x4>; qcom,core-supply-entries { #address-cells = <1>; diff --git a/drivers/video/fbdev/msm/mdss_dp.c b/drivers/video/fbdev/msm/mdss_dp.c index 16ec948df5a9..c932384ebad0 100644 --- a/drivers/video/fbdev/msm/mdss_dp.c +++ b/drivers/video/fbdev/msm/mdss_dp.c @@ -1383,7 +1383,8 @@ static int mdss_dp_on_irq(struct mdss_dp_drv_pdata *dp_drv, bool lt_needed) mdss_dp_phy_share_lane_config(&dp_drv->phy_io, dp_drv->orientation, - dp_drv->dpcd.max_lane_count); + dp_drv->dpcd.max_lane_count, + dp_drv->phy_reg_offset); if (lt_needed) { /* @@ -1465,7 +1466,7 @@ int mdss_dp_on_hpd(struct mdss_dp_drv_pdata *dp_drv) } mdss_dp_phy_share_lane_config(&dp_drv->phy_io, dp_drv->orientation, - dp_drv->dpcd.max_lane_count); + dp_drv->dpcd.max_lane_count, dp_drv->phy_reg_offset); ret = mdss_dp_enable_mainlink_clocks(dp_drv); if (ret) @@ -1735,7 +1736,8 @@ static int mdss_dp_host_init(struct mdss_panel_data *pdata) mdss_dp_get_ctrl_hw_version(&dp_drv->ctrl_io), mdss_dp_get_phy_hw_version(&dp_drv->phy_io)); - mdss_dp_phy_aux_setup(&dp_drv->phy_io, dp_drv->aux_cfg); + mdss_dp_phy_aux_setup(&dp_drv->phy_io, dp_drv->aux_cfg, + dp_drv->phy_reg_offset); mdss_dp_irq_enable(dp_drv); dp_drv->dp_initialized = true; @@ -2789,6 +2791,11 @@ static int mdss_retrieve_dp_ctrl_resources(struct platform_device *pdev, return rc; } + rc = of_property_read_u32(pdev->dev.of_node, + "qcom,phy-register-offset", &dp_drv->phy_reg_offset); + if (rc) + dp_drv->phy_reg_offset = 0; + rc = msm_dss_ioremap_byname(pdev, &dp_drv->tcsr_reg_io, "tcsr_regs"); if (rc) { diff --git a/drivers/video/fbdev/msm/mdss_dp.h b/drivers/video/fbdev/msm/mdss_dp.h index 76ad0b6e6061..0ff2522a2195 100644 --- a/drivers/video/fbdev/msm/mdss_dp.h +++ b/drivers/video/fbdev/msm/mdss_dp.h @@ -462,6 +462,7 @@ struct mdss_dp_drv_pdata { struct dss_io_data dp_cc_io; struct dss_io_data qfprom_io; struct dss_io_data hdcp_io; + u32 phy_reg_offset; int base_size; unsigned char *mmss_cc_base; bool override_config; diff --git a/drivers/video/fbdev/msm/mdss_dp_util.c b/drivers/video/fbdev/msm/mdss_dp_util.c index 98e76a578c08..f89b86f72b52 100644 --- a/drivers/video/fbdev/msm/mdss_dp_util.c +++ b/drivers/video/fbdev/msm/mdss_dp_util.c @@ -871,23 +871,26 @@ void mdss_dp_ctrl_lane_mapping(struct dss_io_data *ctrl_io, char *l_map) ctrl_io->base + DP_LOGICAL2PHYSCIAL_LANE_MAPPING); } -void mdss_dp_phy_aux_setup(struct dss_io_data *phy_io, u32 *aux_cfg) +void mdss_dp_phy_aux_setup(struct dss_io_data *phy_io, u32 *aux_cfg, + u32 phy_reg_offset) { - writel_relaxed(0x3d, phy_io->base + DP_PHY_PD_CTL); + void __iomem *adjusted_phy_io_base = phy_io->base + phy_reg_offset; + + writel_relaxed(0x3d, adjusted_phy_io_base + DP_PHY_PD_CTL); /* DP AUX CFG register programming */ - writel_relaxed(aux_cfg[0], phy_io->base + DP_PHY_AUX_CFG0); - writel_relaxed(aux_cfg[1], phy_io->base + DP_PHY_AUX_CFG1); - writel_relaxed(aux_cfg[2], phy_io->base + DP_PHY_AUX_CFG2); - writel_relaxed(aux_cfg[3], phy_io->base + DP_PHY_AUX_CFG3); - writel_relaxed(aux_cfg[4], phy_io->base + DP_PHY_AUX_CFG4); - writel_relaxed(aux_cfg[5], phy_io->base + DP_PHY_AUX_CFG5); - writel_relaxed(aux_cfg[6], phy_io->base + DP_PHY_AUX_CFG6); - writel_relaxed(aux_cfg[7], phy_io->base + DP_PHY_AUX_CFG7); - writel_relaxed(aux_cfg[8], phy_io->base + DP_PHY_AUX_CFG8); - writel_relaxed(aux_cfg[9], phy_io->base + DP_PHY_AUX_CFG9); + writel_relaxed(aux_cfg[0], adjusted_phy_io_base + DP_PHY_AUX_CFG0); + writel_relaxed(aux_cfg[1], adjusted_phy_io_base + DP_PHY_AUX_CFG1); + writel_relaxed(aux_cfg[2], adjusted_phy_io_base + DP_PHY_AUX_CFG2); + writel_relaxed(aux_cfg[3], adjusted_phy_io_base + DP_PHY_AUX_CFG3); + writel_relaxed(aux_cfg[4], adjusted_phy_io_base + DP_PHY_AUX_CFG4); + writel_relaxed(aux_cfg[5], adjusted_phy_io_base + DP_PHY_AUX_CFG5); + writel_relaxed(aux_cfg[6], adjusted_phy_io_base + DP_PHY_AUX_CFG6); + writel_relaxed(aux_cfg[7], adjusted_phy_io_base + DP_PHY_AUX_CFG7); + writel_relaxed(aux_cfg[8], adjusted_phy_io_base + DP_PHY_AUX_CFG8); + writel_relaxed(aux_cfg[9], adjusted_phy_io_base + DP_PHY_AUX_CFG9); - writel_relaxed(0x1f, phy_io->base + DP_PHY_AUX_INTERRUPT_MASK); + writel_relaxed(0x1f, adjusted_phy_io_base + DP_PHY_AUX_INTERRUPT_MASK); } int mdss_dp_irq_setup(struct mdss_dp_drv_pdata *dp_drv) @@ -1040,14 +1043,14 @@ u32 mdss_dp_usbpd_gen_config_pkt(struct mdss_dp_drv_pdata *dp) } void mdss_dp_phy_share_lane_config(struct dss_io_data *phy_io, - u8 orientation, u8 ln_cnt) + u8 orientation, u8 ln_cnt, u32 phy_reg_offset) { u32 info = 0x0; info |= (ln_cnt & 0x0F); info |= ((orientation & 0x0F) << 4); pr_debug("Shared Info = 0x%x\n", info); - writel_relaxed(info, phy_io->base + DP_PHY_SPARE0); + writel_relaxed(info, phy_io->base + phy_reg_offset + DP_PHY_SPARE0); } void mdss_dp_config_audio_acr_ctrl(struct dss_io_data *ctrl_io, char link_rate) diff --git a/drivers/video/fbdev/msm/mdss_dp_util.h b/drivers/video/fbdev/msm/mdss_dp_util.h index e944b8b78d7f..b3b15a3579fa 100644 --- a/drivers/video/fbdev/msm/mdss_dp_util.h +++ b/drivers/video/fbdev/msm/mdss_dp_util.h @@ -285,7 +285,8 @@ void mdss_dp_assert_phy_reset(struct dss_io_data *ctrl_io, bool assert); void mdss_dp_setup_tr_unit(struct dss_io_data *ctrl_io, u8 link_rate, u8 ln_cnt, u32 res, struct mdss_panel_info *pinfo); void mdss_dp_config_misc(struct mdss_dp_drv_pdata *dp, u32 bd, u32 cc); -void mdss_dp_phy_aux_setup(struct dss_io_data *phy_io, u32 *aux_cfg); +void mdss_dp_phy_aux_setup(struct dss_io_data *phy_io, u32 *aux_cfg, + u32 phy_reg_offset); void mdss_dp_hpd_configure(struct dss_io_data *ctrl_io, bool enable); void mdss_dp_aux_ctrl(struct dss_io_data *ctrl_io, bool enable); void mdss_dp_mainlink_ctrl(struct dss_io_data *ctrl_io, bool enable); @@ -304,7 +305,7 @@ void mdss_dp_usbpd_ext_capabilities(struct usbpd_dp_capabilities *dp_cap); void mdss_dp_usbpd_ext_dp_status(struct usbpd_dp_status *dp_status); u32 mdss_dp_usbpd_gen_config_pkt(struct mdss_dp_drv_pdata *dp); void mdss_dp_phy_share_lane_config(struct dss_io_data *phy_io, - u8 orientation, u8 ln_cnt); + u8 orientation, u8 ln_cnt, u32 phy_reg_offset); void mdss_dp_config_audio_acr_ctrl(struct dss_io_data *ctrl_io, char link_rate); void mdss_dp_audio_setup_sdps(struct dss_io_data *ctrl_io, u32 num_of_channels);