From ca20ea97a9f198007763dda5bc86314cebf35f45 Mon Sep 17 00:00:00 2001 From: Vijay kumar Tumati Date: Wed, 2 Dec 2015 16:28:28 +0530 Subject: [PATCH] msm: camera: Enable ov2685 on msm8937 Changing csiphy clock lane setting and removing a register write in combo mode to enable ov2685 on msm8937. Change-Id: I8e6d987a8072a0c2679f7b53bfd3522b8dfa5297 Signed-off-by: Vijay kumar Tumati --- .../sensor/csiphy/include/msm_csiphy_3_4_2_hwreg.h | 1 + .../camera_v2/sensor/csiphy/include/msm_csiphy_3_5_hwreg.h | 1 + .../platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c | 7 ++++--- .../platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h | 1 + 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_4_2_hwreg.h b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_4_2_hwreg.h index cfcf8cadd91b..aa8a6b9cf3a3 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_4_2_hwreg.h +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_4_2_hwreg.h @@ -22,6 +22,7 @@ struct csiphy_reg_parms_t csiphy_v3_4_2 = { .mipi_csiphy_interrupt_status0_addr = 0x8B0, .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .combo_clk_mask = 0x10, }; struct csiphy_reg_3ph_parms_t csiphy_v3_4_2_3ph = { diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_5_hwreg.h b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_5_hwreg.h index 4521d46f5d6c..d6ee08a1f246 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_5_hwreg.h +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_5_hwreg.h @@ -22,6 +22,7 @@ struct csiphy_reg_parms_t csiphy_v3_5 = { .mipi_csiphy_interrupt_status0_addr = 0x8B0, .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .combo_clk_mask = 0x8, }; struct csiphy_reg_3ph_parms_t csiphy_v3_5_3ph = { diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c index 380df2c18eea..3c6cfe4a3803 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c @@ -332,8 +332,8 @@ static int msm_csiphy_2phase_lane_config( if (csiphy_params->combo_mode == 1) { val |= 0xA; - if (mask == 0x8) { - /* lane 6 is second clock lane for combo mode */ + if (mask == csiphy_dev->ctrl_reg-> + csiphy_reg.combo_clk_mask) { val |= 0x4; clk_lane = 1; } @@ -422,7 +422,8 @@ static int msm_csiphy_2phase_lane_config( } mask <<= 1; } - if (csiphy_dev->hw_version == CSIPHY_VERSION_V342) { + if (csiphy_dev->hw_version == CSIPHY_VERSION_V342 && + csiphy_params->combo_mode != 1) { msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg. mipi_csiphy_3ph_cmn_ctrl0.data, csiphy_dev->base + csiphy_dev->ctrl_reg->csiphy_3ph_reg. diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h index 1b2bddb94550..8106ffd10106 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h @@ -56,6 +56,7 @@ struct csiphy_reg_parms_t { uint32_t mipi_csiphy_glbl_t_init_cfg0_addr; uint32_t mipi_csiphy_t_wakeup_cfg0_addr; uint32_t csiphy_version; + uint32_t combo_clk_mask; }; struct csiphy_reg_3ph_parms_t {