From cb73786a28d02c662b8276546fd08664eb8d0376 Mon Sep 17 00:00:00 2001 From: Runmin Wang Date: Mon, 14 Mar 2016 14:28:12 -0700 Subject: [PATCH] ARM: dts: qcom: Update the uart clock to upstream clock Update the compatible string and clock name to upstream. Change-Id: I693dd6df9e272a09748d74d7ed9d76fe294ec7ee Signed-off-by: Runmin Wang --- arch/arm/boot/dts/qcom/msmcobalt.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 472d64653c57..205d311d0c4f 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -296,23 +296,23 @@ }; uartblsp1dm1: serial@0c170000 { - compatible = "qcom,msm-lsuart-v14", "qcom,msm-uartdm"; + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xc170000 0x1000>; interrupts = <0 108 0>; status = "disabled"; clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; - clock-names = "core_clk", "iface_clk"; + clock-names = "core", "iface"; }; uartblsp2dm1: serial@0c1b0000 { - compatible = "qcom,msm-lsuart-v14", "qcom,msm-uartdm"; + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xc1b0000 0x1000>; interrupts = <0 114 0>; status = "disabled"; clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>, <&clock_gcc clk_gcc_blsp2_ahb_clk>; - clock-names = "core_clk", "iface_clk"; + clock-names = "core", "iface"; }; timer@17920000 {