From f7e6b7a1bcc8ae3bd4e54f5815d5882aaa57b4c6 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 5 Aug 2016 18:16:50 +0530 Subject: [PATCH 1/2] clk: qcom: Add support for dummy reset controller The consumers of the dummy clock provider would require support for dummy resets, which would make a dummy assert/deassert reset signals. The dummy reset controller registers for 0-100 reset signals. The consumers node would have the reset phandle and reset specific pairs and the reset signal names. test_node { .... resets = <&clock_gcc GCC_PHY_BCR>; reset-names = "phy_reset"; }; Change-Id: I242d2f36a6b4af53c658dbaa7a0f32e46cd3af33 Signed-off-by: Taniya Das --- .../arm/msm/clock-controller-dummy.txt | 5 ++ drivers/clk/qcom/clk-dummy.c | 49 +++++++++++++++++-- 2 files changed, 50 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/clock-controller-dummy.txt b/Documentation/devicetree/bindings/arm/msm/clock-controller-dummy.txt index fff8c9e20a1b..c6db837fa137 100644 --- a/Documentation/devicetree/bindings/arm/msm/clock-controller-dummy.txt +++ b/Documentation/devicetree/bindings/arm/msm/clock-controller-dummy.txt @@ -9,9 +9,14 @@ Required properties: - #clock_cells: Must be <1>. This will allow the common clock device tree framework to recognize _this_ device node as a clock provider. +Optional properties: +- #reset-cells: Must be <1>. This will allow the common reset device + tree framework to recognize _this_ device node as a + reset controller provider. Example: clock_rpm: qcom,rpmcc { compatible = "qcom,dummycc"; #clock-cells = <1>; + #reset-cells = <1>; }; diff --git a/drivers/clk/qcom/clk-dummy.c b/drivers/clk/qcom/clk-dummy.c index 3205fbc6b8ba..b62277e74f68 100644 --- a/drivers/clk/qcom/clk-dummy.c +++ b/drivers/clk/qcom/clk-dummy.c @@ -15,14 +15,18 @@ #include #include #include +#include struct clk_dummy { struct clk_hw hw; + struct reset_controller_dev reset; unsigned long rrate; }; #define to_clk_dummy(_hw) container_of(_hw, struct clk_dummy, hw) +#define RESET_MAX 100 + static int dummy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -58,15 +62,35 @@ struct clk_ops clk_dummy_ops = { }; EXPORT_SYMBOL_GPL(clk_dummy_ops); +static int dummy_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + pr_debug("%s\n", __func__); + return 0; +} + +static int dummy_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + pr_debug("%s\n", __func__); + return 0; +} + +static struct reset_control_ops dummy_reset_ops = { + .assert = dummy_reset_assert, + .deassert = dummy_reset_deassert, +}; + /** * clk_register_dummy - register dummy clock with the * clock framework * @dev: device that is registering this clock * @name: name of this clock * @flags: framework-specific flags + * @node: device node */ static struct clk *clk_register_dummy(struct device *dev, const char *name, - unsigned long flags) + unsigned long flags, struct device_node *node) { struct clk_dummy *dummy; struct clk *clk; @@ -85,8 +109,20 @@ static struct clk *clk_register_dummy(struct device *dev, const char *name, /* register the clock */ clk = clk_register(dev, &dummy->hw); - if (IS_ERR(clk)) + if (IS_ERR(clk)) { kfree(dummy); + return clk; + } + + dummy->reset.of_node = node; + dummy->reset.ops = &dummy_reset_ops; + dummy->reset.nr_resets = RESET_MAX; + + if (reset_controller_register(&dummy->reset)) + pr_err("Failed to register reset controller for %s\n", name); + else + pr_info("Successfully registered a dummy reset controller for %s\n", + name); return clk; } @@ -101,10 +137,15 @@ static void of_dummy_clk_setup(struct device_node *node) of_property_read_string(node, "clock-output-names", &clk_name); - clk = clk_register_dummy(NULL, clk_name, 0); + clk = clk_register_dummy(NULL, clk_name, 0, node); if (!IS_ERR(clk)) of_clk_add_provider(node, of_clk_src_simple_get, clk); + else { + pr_err("Failed to register dummy clock controller for %s\n", + clk_name); + return; + } - pr_info("%s: Dummy clock registered\n", clk_name); + pr_info("Successfully registered dummy clock for %s\n", clk_name); } CLK_OF_DECLARE(dummy_clk, "qcom,dummycc", of_dummy_clk_setup); From c6d8725f07e5beda309606ff0787acfeb635213e Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 14 Jul 2016 11:57:53 +0530 Subject: [PATCH 2/2] clk: qcom: Add support for clk_set_flags for branch and dummy clock Add support to allow setting various flags on the branch clock pertaining to PERIPH, RETAIN_PERIPH, RETAIN_MEM set and clear by clients which require this support. Change-Id: I59ddc1b3b677bd0d7fa838afc9a6cbfc10f98409 Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-branch.c | 48 +++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-branch.h | 9 +++++++ drivers/clk/qcom/clk-dummy.c | 6 +++++ 3 files changed, 63 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index 76310e249fb2..0987c8e7f807 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -125,15 +125,62 @@ static int clk_branch_enable(struct clk_hw *hw) return clk_branch_toggle(hw, true, clk_branch_check_halt); } +static int clk_cbcr_set_flags(struct regmap *regmap, unsigned int reg, + unsigned long flags) +{ + u32 cbcr_val; + + regmap_read(regmap, reg, &cbcr_val); + + switch (flags) { + case CLKFLAG_PERIPH_OFF_SET: + cbcr_val |= BIT(12); + break; + case CLKFLAG_PERIPH_OFF_CLEAR: + cbcr_val &= ~BIT(12); + break; + case CLKFLAG_RETAIN_PERIPH: + cbcr_val |= BIT(13); + break; + case CLKFLAG_NORETAIN_PERIPH: + cbcr_val &= ~BIT(13); + break; + case CLKFLAG_RETAIN_MEM: + cbcr_val |= BIT(14); + break; + case CLKFLAG_NORETAIN_MEM: + cbcr_val &= ~BIT(14); + break; + default: + return -EINVAL; + } + + regmap_write(regmap, reg, cbcr_val); + + /* Make sure power is enabled/disabled before returning. */ + mb(); + udelay(1); + + return 0; +} + static void clk_branch_disable(struct clk_hw *hw) { clk_branch_toggle(hw, false, clk_branch_check_halt); } +static int clk_branch_set_flags(struct clk_hw *hw, unsigned flags) +{ + struct clk_branch *br = to_clk_branch(hw); + + return clk_cbcr_set_flags(br->clkr.regmap, br->halt_reg, flags); +} + const struct clk_ops clk_branch_ops = { .enable = clk_branch_enable, .disable = clk_branch_disable, .is_enabled = clk_is_enabled_regmap, + .set_flags = clk_branch_set_flags, }; EXPORT_SYMBOL_GPL(clk_branch_ops); @@ -151,6 +198,7 @@ const struct clk_ops clk_branch2_ops = { .enable = clk_branch2_enable, .disable = clk_branch2_disable, .is_enabled = clk_is_enabled_regmap, + .set_flags = clk_branch_set_flags, }; EXPORT_SYMBOL_GPL(clk_branch2_ops); diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 915c54f9351f..331f58d651e5 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -73,4 +73,13 @@ extern const struct clk_ops clk_branch_simple_ops; #define to_clk_gate2(_hw) \ container_of(to_clk_regmap(_hw), struct clk_gate2, clkr) +enum branch_mem_flags { + CLKFLAG_RETAIN_PERIPH, + CLKFLAG_NORETAIN_PERIPH, + CLKFLAG_RETAIN_MEM, + CLKFLAG_NORETAIN_MEM, + CLKFLAG_PERIPH_OFF_SET, + CLKFLAG_PERIPH_OFF_CLEAR, +}; + #endif diff --git a/drivers/clk/qcom/clk-dummy.c b/drivers/clk/qcom/clk-dummy.c index b62277e74f68..e06a829e508c 100644 --- a/drivers/clk/qcom/clk-dummy.c +++ b/drivers/clk/qcom/clk-dummy.c @@ -55,10 +55,16 @@ static unsigned long dummy_clk_recalc_rate(struct clk_hw *hw, return dummy->rrate; } +static int dummy_clk_set_flags(struct clk_hw *hw, unsigned flags) +{ + return 0; +} + struct clk_ops clk_dummy_ops = { .set_rate = dummy_clk_set_rate, .round_rate = dummy_clk_round_rate, .recalc_rate = dummy_clk_recalc_rate, + .set_flags = dummy_clk_set_flags, }; EXPORT_SYMBOL_GPL(clk_dummy_ops);