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Merge "icnss: Avoid DOMAIN_ATTR_ATOMIC setting during S1 bypass"

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Linux Build Service Account 2017-02-09 22:09:23 -08:00 • committed by Gerrit - the friendly Code Review server
commit cbbf109dc4
4 changed files with 19 additions and 7 deletions
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2
Documentation/devicetree/bindings/cnss/icnss.txt
View file

@ -19,6 +19,7 @@ Required properties:
Optional properties: Optional properties:
- qcom,icnss-vadc: VADC handle for vph_pwr read APIs. - qcom,icnss-vadc: VADC handle for vph_pwr read APIs.
- qcom,icnss-adc_tm: VADC handle for vph_pwr notification APIs. - qcom,icnss-adc_tm: VADC handle for vph_pwr notification APIs.
- qcom,smmu-s1-bypass: Boolean context flag to set SMMU to S1 bypass
Example: Example:
@ -43,4 +44,5 @@ Example:
<0 140 0 /* CE10 */ >, <0 140 0 /* CE10 */ >,
<0 141 0 /* CE11 */ >; <0 141 0 /* CE11 */ >;
qcom,wlan-msa-memory = <0x200000>; qcom,wlan-msa-memory = <0x200000>;
qcom,smmu-s1-bypass;
}; };

1
arch/arm/boot/dts/qcom/sdm630.dtsi
View file

@ -1458,6 +1458,7 @@
<0 424 0>, /* CE10 */ <0 424 0>, /* CE10 */
<0 425 0>; /* CE11 */ <0 425 0>; /* CE11 */
qcom,wlan-msa-memory = <0x100000>; qcom,wlan-msa-memory = <0x100000>;
qcom,smmu-s1-bypass;
}; };
qcom,lpass@15700000 { qcom,lpass@15700000 {

1
arch/arm/boot/dts/qcom/sdm660.dtsi
View file

@ -1891,6 +1891,7 @@
<0 424 0>, /* CE10 */ <0 424 0>, /* CE10 */
<0 425 0>; /* CE11 */ <0 425 0>; /* CE11 */
qcom,wlan-msa-memory = <0x100000>; qcom,wlan-msa-memory = <0x100000>;
qcom,smmu-s1-bypass;
}; };
qcom,lpass@15700000 { qcom,lpass@15700000 {

22
drivers/soc/qcom/icnss.c
View file

@ -334,6 +334,7 @@ static struct icnss_priv {
struct ramdump_device *msa0_dump_dev; struct ramdump_device *msa0_dump_dev;
bool is_wlan_mac_set; bool is_wlan_mac_set;
struct icnss_wlan_mac_addr wlan_mac_addr; struct icnss_wlan_mac_addr wlan_mac_addr;
bool bypass_s1_smmu;
} *penv; } *penv;
static void icnss_pm_stay_awake(struct icnss_priv *priv) static void icnss_pm_stay_awake(struct icnss_priv *priv)
@ -2914,13 +2915,15 @@ static int icnss_smmu_init(struct icnss_priv *priv)
goto map_fail; goto map_fail;
} }
ret = iommu_domain_set_attr(mapping->domain, if (!priv->bypass_s1_smmu) {
DOMAIN_ATTR_ATOMIC, ret = iommu_domain_set_attr(mapping->domain,
&atomic_ctx); DOMAIN_ATTR_ATOMIC,
if (ret < 0) { &atomic_ctx);
icnss_pr_err("Set atomic_ctx attribute failed, err = %d\n", if (ret < 0) {
ret); icnss_pr_err("Set atomic_ctx attribute failed, err = %d\n",
goto set_attr_fail; ret);
goto set_attr_fail;
}
} }
ret = iommu_domain_set_attr(mapping->domain, ret = iommu_domain_set_attr(mapping->domain,
@ -3666,6 +3669,11 @@ static int icnss_probe(struct platform_device *pdev)
if (ret == -EPROBE_DEFER) if (ret == -EPROBE_DEFER)
goto out; goto out;
if (of_property_read_bool(pdev->dev.of_node, "qcom,smmu-s1-bypass"))
priv->bypass_s1_smmu = true;
icnss_pr_dbg("SMMU S1 BYPASS = %d\n", priv->bypass_s1_smmu);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase"); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase");
if (!res) { if (!res) {
icnss_pr_err("Memory base not found in DT\n"); icnss_pr_err("Memory base not found in DT\n");