ARM: dts: msm: Update ufs clks and regulators for msmcobalt
Update the correct clocks and regulators used for UFS. CRs-Fixed: 994739 Change-Id: Id545c5b8f567e7ccdab1c07af9637848366b49a5 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This commit is contained in:
Venkat Gopalakrishnan
Bryan Huntsman
parent
439ef7b343
commit
cbda86d806
4 changed files with 45 additions and 41 deletions
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@ -20,21 +20,29 @@
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reg = <0x1da7000 0xda8>, /* PHY regs */
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<0x1db8000 0x100>; /* U11 user regs */
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reg-names = "phy_mem", "u11_user";
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vdda-phy-supply = <&pmcobalt_l28>;
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vdda-phy-supply = <&pmcobalt_l1>;
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vdda-pll-supply = <&pmcobalt_l2>;
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vddp-ref-clk-supply = <&pmcobalt_l26>;
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vdda-phy-max-microamp = <51400>;
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vdda-pll-max-microamp = <14600>;
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vddp-ref-clk-max-microamp = <100>;
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vddp-ref-clk-always-on;
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status = "ok";
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};
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&ufs1 {
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vdd-hba-supply = <&gdsc_ufs>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pmcobalt_l20>;
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vccq-supply = <&pmcobalt_l26>;
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vccq2-supply = <&pmcobalt_s4>;
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vcc-max-microamp = <750000>;
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vccq-max-microamp = <560000>;
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vccq2-max-microamp = <750000>;
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qcom,disable-lpm;
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rpm-level = <0>;
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spm-level = <0>;
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status = "ok";
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};
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@ -33,18 +33,6 @@
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qcom,xo-clk-rate = <19200000>;
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};
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&ufsphy1 {
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status = "ok";
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};
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&ufs1 {
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status = "ok";
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};
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&ufs_ice {
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status = "ok";
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};
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&qusb_phy0 {
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compatible = "usb-nop-xceiv";
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};
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@ -18,6 +18,33 @@
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pinctrl-0 = <&uart_console_active>;
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};
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&ufsphy1 {
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vdda-phy-supply = <&pmcobalt_l1>;
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vdda-pll-supply = <&pmcobalt_l2>;
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vddp-ref-clk-supply = <&pmcobalt_l26>;
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vdda-phy-max-microamp = <51400>;
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vdda-pll-max-microamp = <14600>;
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vddp-ref-clk-max-microamp = <100>;
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vddp-ref-clk-always-on;
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status = "ok";
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};
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&ufs1 {
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vdd-hba-supply = <&gdsc_ufs>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pmcobalt_l20>;
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vccq-supply = <&pmcobalt_l26>;
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vccq2-supply = <&pmcobalt_s4>;
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vcc-max-microamp = <750000>;
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vccq-max-microamp = <560000>;
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vccq2-max-microamp = <750000>;
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status = "ok";
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};
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&ufs_ice {
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status = "ok";
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};
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&sdhc_2 {
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vdd-supply = <&pmcobalt_l21>;
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qcom,vdd-voltage-level = <2950000 2960000>;
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@ -1079,14 +1079,12 @@
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reg = <0x1da7000 0xda8>;
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reg-names = "phy_mem";
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#phy-cells = <0>;
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vdda-phy-max-microamp = <51430>;
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vdda-pll-max-microamp = <14170>;
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vddp-ref-clk-max-microamp = <100>;
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vddp-ref-clk-always-on;
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clock-names = "ref_clk_src",
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"ref_clk";
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"ref_clk",
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"ref_aux_clk";
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clocks = <&clock_gcc clk_ln_bb_clk1>,
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<&clock_gcc clk_gcc_ufs_clkref_clk>;
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<&clock_gcc clk_gcc_ufs_clkref_clk>,
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<&clock_gcc clk_gcc_ufs_phy_aux_clk>;
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status = "disabled";
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};
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@ -1094,24 +1092,18 @@
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compatible = "qcom,ice";
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reg = <0x1db0000 0x8000>;
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qcom,enable-ice-clk;
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clock-names = "ufs_core_clk_src",
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"ufs_core_clk",
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clock-names = "ufs_core_clk",
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"bus_clk",
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"iface_clk",
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"ice_core_clk_src",
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"ice_core_clk";
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clocks = <&clock_gcc clk_ufs_axi_clk_src>,
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<&clock_gcc clk_gcc_ufs_axi_clk>,
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clocks = <&clock_gcc clk_gcc_ufs_axi_clk>,
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<&clock_gcc clk_gcc_aggre1_ufs_axi_clk>,
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<&clock_gcc clk_gcc_ufs_ahb_clk>,
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<&clock_gcc clk_ufs_ice_core_clk_src>,
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<&clock_gcc clk_gcc_ufs_ice_core_clk>;
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qcom,op-freq-hz = <0>,
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<0>,
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<0>,
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<0>,
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<300000000>,
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<0>;
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<300000000>;
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vdd-hba-supply = <&gdsc_ufs>;
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qcom,msm-bus,name = "ufs_ice_noc";
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qcom,msm-bus,num-cases = <2>;
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@ -1131,30 +1123,21 @@
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interrupts = <0 265 0>;
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phys = <&ufsphy1>;
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phy-names = "ufsphy";
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vdd-hba-supply = <&gdsc_ufs>;
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vdd-hba-fixed-regulator;
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vcc-max-microamp = <750000>;
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vccq-max-microamp = <450000>;
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vccq2-max-microamp = <750000>;
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ufs-qcom-crypto = <&ufs_ice>;
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clock-names =
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"core_clk_src",
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"core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro_src",
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"core_clk_unipro",
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"core_clk_ice",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk";
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clocks =
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<&clock_gcc clk_ufs_axi_clk_src>,
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<&clock_gcc clk_gcc_ufs_axi_clk>,
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<&clock_gcc clk_gcc_aggre1_ufs_axi_clk>,
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<&clock_gcc clk_gcc_ufs_ahb_clk>,
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<&clock_gcc clk_ufs_ice_core_clk_src>,
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<&clock_gcc clk_gcc_ufs_unipro_core_clk>,
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<&clock_gcc clk_gcc_ufs_ice_core_clk>,
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<&clock_gcc clk_ln_bb_clk1>,
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@ -1164,12 +1147,10 @@
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<100000000 200000000>,
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<0 0>,
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<0 0>,
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<0 0>,
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<75000000 150000000>,
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<150000000 300000000>,
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<0 0>,
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<0 0>,
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<0 0>,
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<0 0>,
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<0 0>;
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lanes-per-direction = <1>;
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