From cc4f1763f08b782b170c23a1cf5bd40b2ef952be Mon Sep 17 00:00:00 2001 From: Mitchel Humpherys Date: Tue, 4 Nov 2014 10:40:00 -0800 Subject: [PATCH] iommu/arm-smmu: add and use definitions for the TTBCR2.SEP field Currently we're repurposing the definitions used for the TTBCR2.PASize field for TTBCR2.SEP since they conveniently have the same values. However, this might look like a bug at first glance to the casual passer-by, appearing that we're using the wrong bit definitions for the field. For example, we're using TTBCR2_ADDR_32 to indicate that the Sign Extension Bit should live at 31 (not 32 as the name of the macro might imply). Reduce cumulative human cognitive load by adding some definitions specifically for the SEP field. Change-Id: Ia406951499453e2badca42a1cc4cdbc566af4dab Signed-off-by: Mitchel Humpherys --- drivers/iommu/arm-smmu.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 7cbf4b1fa5e9..4ee43038b545 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -309,6 +309,13 @@ #define TTBCR2_ADDR_44 4 #define TTBCR2_ADDR_48 5 +#define TTBCR2_SEP_31 0 +#define TTBCR2_SEP_35 1 +#define TTBCR2_SEP_39 2 +#define TTBCR2_SEP_41 3 +#define TTBCR2_SEP_43 4 +#define TTBCR2_SEP_47 5 + #define TTBRn_HI_ASID_SHIFT 16 #define MAIR_ATTR_SHIFT(n) ((n) << 3) @@ -940,23 +947,23 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) /* TTBCR2 */ switch (smmu->s1_input_size) { case 32: - reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT); + reg = (TTBCR2_SEP_31 << TTBCR2_SEP_SHIFT); break; case 36: - reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT); + reg = (TTBCR2_SEP_35 << TTBCR2_SEP_SHIFT); break; case 39: case 40: - reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT); + reg = (TTBCR2_SEP_39 << TTBCR2_SEP_SHIFT); break; case 42: - reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT); + reg = (TTBCR2_SEP_41 << TTBCR2_SEP_SHIFT); break; case 44: - reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT); + reg = (TTBCR2_SEP_43 << TTBCR2_SEP_SHIFT); break; case 48: - reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT); + reg = (TTBCR2_SEP_47 << TTBCR2_SEP_SHIFT); break; }