From cc6df31db6b39446b338b61932b0fc8f614baf89 Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Fri, 12 Feb 2016 16:53:04 +0530 Subject: [PATCH] mmc: core: fix issue with devfreq clock scaling Due to recent DDR52 lower bus speed mode in clock scaling, there is a mismatch between the clock frequencies used by the devfreq framework and the MMC driver. Due to this, SDCC clock is sometimes running at DDR25 and ICE clock is running at 100MHz causing the power regression. Fix this mismatch by initializing the frequencies properly during MMC resume based on the current ios.clock. CRs-Fixed: 974940 Change-Id: I09fe888d0fbd1fde3f6a6f32806315ddbb5bf6e1 Signed-off-by: Sahitya Tummala --- drivers/mmc/core/core.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index e65e16bf92ea..d93b57670a69 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -774,6 +774,9 @@ EXPORT_SYMBOL(mmc_suspend_clk_scaling); int mmc_resume_clk_scaling(struct mmc_host *host) { int err = 0; + u32 max_clk_idx = 0; + u32 devfreq_max_clk = 0; + u32 devfreq_min_clk = 0; if (!host) { WARN(1, "bad host parameter\n"); @@ -790,7 +793,15 @@ int mmc_resume_clk_scaling(struct mmc_host *host) } atomic_set(&host->clk_scaling.devfreq_abort, 0); - host->clk_scaling.curr_freq = host->ios.clock; + + max_clk_idx = host->clk_scaling.freq_table_sz - 1; + devfreq_max_clk = host->clk_scaling.freq_table[max_clk_idx]; + devfreq_min_clk = host->clk_scaling.freq_table[0]; + + host->clk_scaling.curr_freq = devfreq_max_clk; + if (host->ios.clock < host->card->clk_scaling_highest) + host->clk_scaling.curr_freq = devfreq_min_clk; + host->clk_scaling.clk_scaling_in_progress = false; host->clk_scaling.need_freq_change = false;