msm: mdss: correct the flush bit for TIMING_2 interface for 8939
On 8939, the flush bit for TIMING_2 interface is BIT-31 whereas, it is BIT-29 for other targets. Add change to take care of this. Also the CTL flush bit for timing interfaces should be based on ctx->intf_num variable rather than ctl->intf_num. This is to handle cases related to destination split. Change-Id: I8c750714ca931341e179057f5c53edce0ad2803e Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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1 changed files with 9 additions and 2 deletions
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@ -129,8 +129,10 @@ static int mdss_mdp_video_timegen_setup(struct mdss_mdp_ctl *ctl,
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u32 den_polarity, hsync_polarity, vsync_polarity;
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u32 den_polarity, hsync_polarity, vsync_polarity;
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u32 display_hctl, active_hctl, hsync_ctl, polarity_ctl;
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u32 display_hctl, active_hctl, hsync_ctl, polarity_ctl;
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struct mdss_mdp_video_ctx *ctx;
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struct mdss_mdp_video_ctx *ctx;
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struct mdss_data_type *mdata;
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ctx = ctl->priv_data;
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ctx = ctl->priv_data;
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mdata = ctl->mdata;
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hsync_period = p->hsync_pulse_width + p->h_back_porch +
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hsync_period = p->hsync_pulse_width + p->h_back_porch +
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p->width + p->h_front_porch;
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p->width + p->h_front_porch;
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vsync_period = p->vsync_pulse_width + p->v_back_porch +
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vsync_period = p->vsync_pulse_width + p->v_back_porch +
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@ -146,8 +148,13 @@ static int mdss_mdp_video_timegen_setup(struct mdss_mdp_ctl *ctl,
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display_v_end -= p->h_front_porch;
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display_v_end -= p->h_front_porch;
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}
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}
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ctl->flush_bits |= BIT(31) >>
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/* TIMING_2 flush bit on 8939 is BIT 31 */
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(ctl->intf_num - MDSS_MDP_INTF0);
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if (mdata->mdp_rev == MDSS_MDP_HW_REV_108 &&
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ctx->intf_num == MDSS_MDP_INTF2)
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ctl->flush_bits |= BIT(31);
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else
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ctl->flush_bits |= BIT(31) >>
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(ctx->intf_num - MDSS_MDP_INTF0);
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hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
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hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
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hsync_end_x = hsync_period - p->h_front_porch - 1;
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hsync_end_x = hsync_period - p->h_front_porch - 1;
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