evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

msm: mdss: correct the flush bit for TIMING_2 interface for 8939

Browse source 
On 8939, the flush bit for TIMING_2 interface is BIT-31 whereas,
it is BIT-29 for other targets. Add change to take care of this.
Also the CTL flush bit for timing interfaces should be based on
ctx->intf_num variable rather than ctl->intf_num. This is to
handle cases related to destination split.

Change-Id: I8c750714ca931341e179057f5c53edce0ad2803e
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
This commit is contained in:
Padmanabhan Komanduru 2014-09-17 16:30:50 +05:30 • committed by David Keitel
parent 347712d7da
commit ccd8eda7dc
1 changed files with 9 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
drivers/video/fbdev/msm/mdss_mdp_intf_video.c
View file

@ -129,8 +129,10 @@ static int mdss_mdp_video_timegen_setup(struct mdss_mdp_ctl *ctl,
u32 den_polarity, hsync_polarity, vsync_polarity;
u32 display_hctl, active_hctl, hsync_ctl, polarity_ctl;
struct mdss_mdp_video_ctx *ctx;
struct mdss_data_type *mdata;
ctx = ctl->priv_data;
mdata = ctl->mdata;
hsync_period = p->hsync_pulse_width + p->h_back_porch +
p->width + p->h_front_porch;
vsync_period = p->vsync_pulse_width + p->v_back_porch +
@ -146,8 +148,13 @@ static int mdss_mdp_video_timegen_setup(struct mdss_mdp_ctl *ctl,
display_v_end -= p->h_front_porch;
}
/* TIMING_2 flush bit on 8939 is BIT 31 */
if (mdata->mdp_rev == MDSS_MDP_HW_REV_108 &&
ctx->intf_num == MDSS_MDP_INTF2)
ctl->flush_bits |= BIT(31);
else
ctl->flush_bits |= BIT(31) >>
(ctl->intf_num - MDSS_MDP_INTF0);
(ctx->intf_num - MDSS_MDP_INTF0);
hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
hsync_end_x = hsync_period - p->h_front_porch - 1;