From ce5504db5e715033ac6bcdca9c2601e7ec6bcf3a Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Wed, 16 Nov 2016 17:27:59 +0530 Subject: [PATCH] ARM: dts: msm: Set USB core clock rate for USB2/USB3 for msm8996 Set required USB core clock rate for USB3 working across connect/ disconnect for msm8996. Else USB enumeration fails after reconnection due to this invalid clock rate setting for USB core clock. Also set USB core clock rate for USB2 controller as well. Change-Id: I6ce48512df5973bf8a2a3081a3a6f8759aeb499f Signed-off-by: Vijayavardhan Vennapusa --- arch/arm/boot/dts/qcom/msm8996.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msm8996.dtsi b/arch/arm/boot/dts/qcom/msm8996.dtsi index 7e88f524367f..2735cfb93be0 100644 --- a/arch/arm/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996.dtsi @@ -1948,6 +1948,8 @@ clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "xo", "cfg_ahb_clk"; + qcom,core-clk-rate = <120000000>; + resets = <&clock_gcc USB_30_BCR>; reset-names = "core_reset"; @@ -2056,6 +2058,7 @@ <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>; clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk", "xo", "cfg_ahb_clk"; + qcom,core-clk-rate = <60000000>; resets = <&clock_gcc USB_20_BCR>; reset-names = "core_reset";