From ce96391696a5adb76bad05e17e0e2821c6a98bbe Mon Sep 17 00:00:00 2001 From: Padmanabhan Komanduru Date: Thu, 25 Feb 2016 14:16:27 +0530 Subject: [PATCH] clk: msm: mdss: update the programming of DYNAMIC_REFRESH_PLL_UPPER_ADDR2 As part of dynamic refresh sequence, we program PLL_UPPER_ADDR2 register to 0x003FFE00 instead of 0x001FFE00. This causes a register write to DSIPHY_PLL_KVCO_COUNT1 to 0x1 during the dynamic refresh operation whereas the register write is supposed to happen for DSIPHY_CMN_PLL_CNTRL register. Update the write value to DYNAMIC_REFRESH_PLL_UPPER_ADDR2 to take care of this. Change-Id: I991920d5a45e79670a4a033c8a83bef6c7f3136b Signed-off-by: Padmanabhan Komanduru --- drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c b/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c index a6ea5304587a..52621de2b0ab 100644 --- a/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c +++ b/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c @@ -909,7 +909,7 @@ static void shadow_pll_dynamic_refresh_8996(struct mdss_pll_resources *pll, MDSS_PLL_REG_W(pll->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR, 0x0000001E); MDSS_PLL_REG_W(pll->dyn_pll_base, - DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2, 0x003FFE00); + DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2, 0x001FFE00); /* * Ensure all the dynamic refresh registers are written before