ARM: dts: msm: optimize rm67195 settings for SDM660 PM660A QRD

Optimize the porch settings for rm67195 AMOLED panel, as this
panel is used for SDM660 PM660A QRD, and the current settings
will cause low FPS in some performance test scenarios.

CRs-Fixed: 2019860
Change-Id: I2d310761d644a39f42ab16c4e1a604c9a45dcf53
Signed-off-by: Yahui Wang <yahuiw@codeaurora.org>
This commit is contained in:
Yahui Wang 2017-03-16 13:27:10 +08:00 committed by Gerrit - the friendly Code Review server
parent 928cd38621
commit cfc80310ff
3 changed files with 18 additions and 16 deletions

View file

@ -20,11 +20,11 @@
qcom,mdss-dsi-stream = <0>;
qcom,mdss-dsi-panel-width = <1080>;
qcom,mdss-dsi-panel-height = <1920>;
qcom,mdss-dsi-h-front-porch = <32>;
qcom,mdss-dsi-h-back-porch = <40>;
qcom,mdss-dsi-h-pulse-width = <8>;
qcom,mdss-dsi-h-front-porch = <120>;
qcom,mdss-dsi-h-back-porch = <60>;
qcom,mdss-dsi-h-pulse-width = <12>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <16>;
qcom,mdss-dsi-v-back-porch = <12>;
qcom,mdss-dsi-v-front-porch = <8>;
qcom,mdss-dsi-v-pulse-width = <4>;
qcom,mdss-dsi-h-left-border = <0>;
@ -104,6 +104,8 @@
qcom,mdss-dsi-lane-1-state;
qcom,mdss-dsi-lane-2-state;
qcom,mdss-dsi-lane-3-state;
qcom,mdss-dsi-t-clk-post = <0x0d>;
qcom,mdss-dsi-t-clk-pre = <0x2f>;
qcom,mdss-dsi-wr-mem-start = <0x2c>;
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
qcom,mdss-dsi-te-pin-select = <1>;

View file

@ -152,11 +152,11 @@
};
&dsi_rm67195_amoled_fhd_cmd {
qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0
23 1e 07 08 05 03 04 a0
23 1e 07 08 05 03 04 a0
23 1e 07 08 05 03 04 a0
23 19 07 08 05 03 04 a0];
qcom,mdss-dsi-panel-timings-phy-v2 = [24 1f 08 09 05 03 04 a0
24 1f 08 09 05 03 04 a0
24 1f 08 09 05 03 04 a0
24 1f 08 09 05 03 04 a0
24 1a 08 09 05 03 04 a0];
qcom,mdss-dsi-t-clk-post = <0x0d>;
qcom,mdss-dsi-t-clk-pre = <0x2d>;
qcom,mdss-dsi-t-clk-pre = <0x2f>;
};

View file

@ -267,11 +267,11 @@
};
&dsi_rm67195_amoled_fhd_cmd {
qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0
23 1e 07 08 05 03 04 a0
23 1e 07 08 05 03 04 a0
23 1e 07 08 05 03 04 a0
23 19 07 08 05 03 04 a0];
qcom,mdss-dsi-panel-timings-phy-v2 = [24 1f 08 09 05 03 04 a0
24 1f 08 09 05 03 04 a0
24 1f 08 09 05 03 04 a0
24 1f 08 09 05 03 04 a0
24 1a 08 09 05 03 04 a0];
qcom,mdss-dsi-t-clk-post = <0x0d>;
qcom,mdss-dsi-t-clk-pre = <0x2d>;
qcom,mdss-dsi-t-clk-pre = <0x2f>;
};