clk: msm: mdss: add support for dsi pll on msmcobalt
Add support to program the DSI PLL on msmcobalt which is needed to drive the DSI byte and pixel clocks. CRs-Fixed: 1000576 Change-Id: Ic11a3747a0e008e1f71df91a1a79d33242d2a2a4 Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
This commit is contained in:
Aravind Venkateswaran
Jeevan Shriram
parent
e1cbb2f68d
commit
cffac32b87
7 changed files with 1380 additions and 4 deletions
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@ -13,7 +13,8 @@ Required properties:
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"qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992",
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"qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996",
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"qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2",
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"qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8"
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"qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8",
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"qcom,mdss_dsi_pll_cobalt"
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- cell-index: Specifies the controller used
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- reg: offset and length of the register set for the device.
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- reg-names : names to refer to register sets related to this device
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@ -2,4 +2,5 @@ obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll-util.o
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obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll.o
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obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996.o
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obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996-util.o
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obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-cobalt.o
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obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-8996.o
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1344
drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c
Normal file
1344
drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -1,4 +1,4 @@
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/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -65,6 +65,8 @@ int dsi_pll_clock_register_lpm(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res);
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int dsi_pll_clock_register_8996(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res);
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int dsi_pll_clock_register_cobalt(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res);
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int set_byte_mux_sel(struct mux_clk *clk, int sel);
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int get_byte_mux_sel(struct mux_clk *clk);
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@ -1,4 +1,4 @@
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/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -134,6 +134,8 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
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pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
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pll_res->target_id = MDSS_PLL_TARGET_8996;
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pll_res->revision = 2;
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} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_cobalt")) {
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pll_res->pll_interface_type = MDSS_DSI_PLL_COBALT;
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} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996")) {
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pll_res->pll_interface_type = MDSS_HDMI_PLL_8996;
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} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996_v2")) {
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@ -169,6 +171,9 @@ static int mdss_pll_clock_register(struct platform_device *pdev,
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case MDSS_DSI_PLL_8996:
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rc = dsi_pll_clock_register_8996(pdev, pll_res);
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break;
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case MDSS_DSI_PLL_COBALT:
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rc = dsi_pll_clock_register_cobalt(pdev, pll_res);
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break;
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case MDSS_HDMI_PLL_8996:
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rc = hdmi_8996_v1_pll_clock_register(pdev, pll_res);
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break;
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@ -379,6 +384,7 @@ static int mdss_pll_remove(struct platform_device *pdev)
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static const struct of_device_id mdss_pll_dt_match[] = {
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{.compatible = "qcom,mdss_dsi_pll_8996"},
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{.compatible = "qcom,mdss_dsi_pll_8996_v2"},
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{.compatible = "qcom,mdss_dsi_pll_cobalt"},
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{.compatible = "qcom,mdss_hdmi_pll_8996"},
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{.compatible = "qcom,mdss_hdmi_pll_8996_v2"},
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{.compatible = "qcom,mdss_hdmi_pll_8996_v3"},
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@ -1,4 +1,4 @@
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/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -30,6 +30,7 @@
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enum {
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MDSS_DSI_PLL_8996,
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MDSS_DSI_PLL_COBALT,
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MDSS_HDMI_PLL_8996,
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MDSS_HDMI_PLL_8996_V2,
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MDSS_HDMI_PLL_8996_V3,
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@ -424,6 +424,27 @@
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#define clk_mmss_vmem_maxi_clk 0xb6067889
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#define clk_mmss_debug_mux 0xe646ffda
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/* external multimedia clocks */
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#define clk_dsi0pll_byteclk_mux 0xecf2c434
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#define clk_dsi0pll_byteclk_src 0x6f6f740f
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#define clk_dsi0pll_pclk_mux 0x6c9da335
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#define clk_dsi0pll_pclk_src 0x5efd85d4
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#define clk_dsi0pll_pclk_src_mux 0x84b14663
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#define clk_dsi0pll_post_bit_div 0xf46dcf27
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#define clk_dsi0pll_post_vco_div 0x8ee956ff
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#define clk_dsi0pll_bitclk_src 0x36c3c437
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#define clk_dsi0pll_vco_clk 0x15940d40
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#define clk_dsi1pll_byteclk_mux 0x14e2f38f
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#define clk_dsi1pll_byteclk_src 0x4b65c298
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#define clk_dsi1pll_pclk_mux 0x4c0518b5
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#define clk_dsi1pll_pclk_src 0xeddcd80e
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#define clk_dsi1pll_pclk_src_mux 0x3651feb3
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#define clk_dsi1pll_post_bit_div 0x712f0260
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#define clk_dsi1pll_post_vco_div 0x623e04de
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#define clk_dsi1pll_bitclk_src 0x13ab045b
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#define clk_dsi1pll_vco_clk 0x99797b50
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/* clock_gpu controlled clocks*/
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#define clk_gpucc_xo 0xc4e1a890
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#define clk_gpucc_gpll0 0x0db0e37f
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