ARM: dts: msm: add support for qdss nodes on msmfalcon
Add support for CTI, DCC and Watchdog for msmfalcon. DCC is used for capturing register values and CTI is used to map triggers. Watchdog is used to handle kernel panics. Change-Id: I4202cfb21868983792e75e8ef6a305030879fb39 CRs-fixed: 1056777 Signed-off-by: Amey Telawane <ameyt@codeaurora.org>
This commit is contained in:
Amey Telawane
parent
9e2d528dc4
commit
d0110c84d9
2 changed files with 324 additions and 0 deletions
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@ -26,6 +26,8 @@
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arm,buffer-size = <0x400000>;
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arm,sg-enable;
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coresight-ctis = <&cti0 &cti8>;
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coresight-name = "coresight-tmc-etr";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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@ -76,6 +78,8 @@
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coresight-name = "coresight-tmc-etf";
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coresight-ctis = <&cti0 &cti8>;
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "apb_pclk", "core_a_clk";
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@ -161,6 +165,14 @@
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<&funnel_merg_in_funnel_in0>;
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};
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};
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port@3 {
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reg = <6>;
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funnel_in0_in_funnel_qatb: endpoint {
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slave-mode;
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remote-endpoint =
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<&funnel_qatb_out_funnel_in0>;
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};
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};
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port@4 {
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reg = <7>;
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funnel_in0_in_stm: endpoint {
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@ -191,4 +203,294 @@
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};
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};
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};
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cti0: cti@6010000 {
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compatible = "arm,coresight-cti";
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reg = <0x6010000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti0";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti1: cti@6011000 {
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compatible = "arm,coresight-cti";
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reg = <0x6011000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti1";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti2: cti@6012000 {
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compatible = "arm,coresight-cti";
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reg = <0x6012000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti2";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti3: cti@6013000 {
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compatible = "arm,coresight-cti";
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reg = <0x6013000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti3";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti4: cti@6014000 {
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compatible = "arm,coresight-cti";
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reg = <0x6014000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti4";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti5: cti@6015000 {
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compatible = "arm,coresight-cti";
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reg = <0x6015000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti5";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti6: cti@6016000 {
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compatible = "arm,coresight-cti";
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reg = <0x6016000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti6";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti7: cti@6017000 {
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compatible = "arm,coresight-cti";
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reg = <0x6017000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti7";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti8: cti@6018000 {
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compatible = "arm,coresight-cti";
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reg = <0x6018000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti8";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti9: cti@6019000 {
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compatible = "arm,coresight-cti";
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reg = <0x6019000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti9";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti10: cti@601a000 {
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compatible = "arm,coresight-cti";
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reg = <0x601a000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti10";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti11: cti@601b000 {
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compatible = "arm,coresight-cti";
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reg = <0x601b000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti11";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti12: cti@601c000 {
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compatible = "arm,coresight-cti";
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reg = <0x601c000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti12";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti13: cti@601d000 {
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compatible = "arm,coresight-cti";
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reg = <0x601d000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti13";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti14: cti@601e000 {
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compatible = "arm,coresight-cti";
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reg = <0x601e000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti14";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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cti15: cti@601f000 {
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compatible = "arm,coresight-cti";
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reg = <0x601f000 0x1000>;
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reg-names = "cti-base";
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coresight-name = "coresight-cti15";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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};
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funnel_qatb: funnel@6005000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x0003b908>;
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reg = <0x6005000 0x1000>;
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reg-names = "funnel-base";
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coresight-name = "coresight-funnel-qatb";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "apb_pclk", "core_a_clk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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funnel_qatb_out_funnel_in0: endpoint {
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remote-endpoint =
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<&funnel_in0_in_funnel_qatb>;
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};
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};
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port@1 {
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reg = <0>;
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funnel_qatb_in_tpda: endpoint {
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slave-mode;
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remote-endpoint =
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<&tpda_out_funnel_qatb>;
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};
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};
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};
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};
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tpda: tpda@6004000 {
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compatible = "qcom,coresight-tpda";
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reg = <0x6004000 0x1000>;
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reg-names = "tpda-base";
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coresight-name = "coresight-tpda";
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qcom,tpda-atid = <65>;
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qcom,bc-elem-size = <7 32>,
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<9 32>;
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qcom,tc-elem-size = <3 32>,
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<6 32>,
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<9 32>;
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qcom,dsb-elem-size = <7 32>,
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<9 32>;
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qcom,cmb-elem-size = <3 32>,
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<4 32>,
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<5 32>,
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<9 64>;
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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tpda_out_funnel_qatb: endpoint {
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remote-endpoint =
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<&funnel_qatb_in_tpda>;
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};
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};
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port@2 {
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reg = <5>;
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tpda_in_tpdm_dcc: endpoint {
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slave-mode;
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remote-endpoint =
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<&tpdm_dcc_out_tpda>;
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};
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};
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};
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};
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tpdm_dcc: tpdm@7054000 {
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compatible = "qcom,coresight-tpdm";
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reg = <0x7054000 0x1000>;
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reg-names = "tpdm-base";
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coresight-name = "coresight-tpdm-dcc";
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clocks = <&clock_gcc RPM_QDSS_CLK>,
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<&clock_gcc RPM_QDSS_A_CLK>;
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clock-names = "core_clk", "core_a_clk";
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port{
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tpdm_dcc_out_tpda: endpoint {
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remote-endpoint = <&tpda_in_tpdm_dcc>;
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};
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};
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};
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};
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@ -231,6 +231,18 @@
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clock-frequency = <19200000>;
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};
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wdog: qcom,wdt@17817000 {
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status = "disabled";
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compatible = "qcom,msm-watchdog";
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reg = <0x17817000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <0 3 0>, <0 4 0>;
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qcom,bark-time = <11000>;
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qcom,pet-time = <10000>;
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qcom,ipi-ping;
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qcom,wakeup-enable;
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};
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qcom,sps {
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compatible = "qcom,msm_sps_4k";
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qcom,pipe-attr-ee;
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@ -359,6 +371,16 @@
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qcom,mpu-enabled;
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};
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dcc: dcc@10b3000 {
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compatible = "qcom,dcc";
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reg = <0x10b3000 0x1000>,
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<0x10b4000 0x800>;
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reg-names = "dcc-base", "dcc-ram-base";
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clocks = <&clock_gcc RPM_QDSS_CLK>;
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clock-names = "dcc_clk";
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};
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qcom,glink-smem-native-xprt-modem@86000000 {
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compatible = "qcom,glink-smem-native-xprt";
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reg = <0x86000000 0x200000>,
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