From d07060d4f160c7ad8c02ff0ce01c0a215372c28e Mon Sep 17 00:00:00 2001 From: Vidyakumar Athota Date: Tue, 27 Sep 2016 17:42:11 -0700 Subject: [PATCH] ASoC: wcd934x: enable rate converter clock for AANC Rate converter clock needs to enable for adaptive ANC (Active Noise Cancellation)to work otherwise noise mic data will not go to Rx path. Add change to enable rate converter clock. Change-Id: I8c83f6305dbc0a40b67bf2ffd53d37a0abdcf953 Signed-off-by: Vidyakumar Athota --- sound/soc/codecs/wcd934x/wcd934x.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/sound/soc/codecs/wcd934x/wcd934x.c b/sound/soc/codecs/wcd934x/wcd934x.c index 28914ed3f937..ccf140f0df12 100644 --- a/sound/soc/codecs/wcd934x/wcd934x.c +++ b/sound/soc/codecs/wcd934x/wcd934x.c @@ -1033,17 +1033,15 @@ static int tavil_codec_enable_anc(struct snd_soc_dapm_widget *w, snd_soc_write(codec, reg, (val & mask)); } + /* Rate converter clk enable and set bypass mode */ + snd_soc_update_bits(codec, WCD934X_CDC_ANC0_RC_COMMON_CTL, + 0x05, 0x05); if (!hwdep_cal) release_firmware(fw); break; - case SND_SOC_DAPM_POST_PMU: - /* Remove ANC Rx from reset */ - snd_soc_update_bits(codec, WCD934X_CDC_ANC0_CLK_RESET_CTL, - 0x08, 0x00); - snd_soc_update_bits(codec, WCD934X_CDC_ANC1_CLK_RESET_CTL, - 0x08, 0x00); - break; case SND_SOC_DAPM_POST_PMD: + snd_soc_update_bits(codec, WCD934X_CDC_ANC0_RC_COMMON_CTL, + 0x05, 0x00); if (!strcmp(w->name, "ANC EAR PA") || !strcmp(w->name, "ANC SPK1 PA")) { snd_soc_update_bits(codec, WCD934X_CDC_ANC0_MODE_1_CTL,