From d0b7d378437c3658618f19b78d9f7a75ee0ceaf6 Mon Sep 17 00:00:00 2001 From: Deepak Katragadda Date: Tue, 17 Nov 2015 17:17:56 -0800 Subject: [PATCH] ARM: dts: msm: Add the timeout properties to SMMU GDSCs on MSM8996 The votable SMMU GDSCs might take longer to enable than the default limit of 100usecs depending on the clock WAKE and SLEEP settings and the clock rates. Make this polling timeout limit more configurable. Change-Id: I26cb00cefa5d45ed2a92f306921e2d95938795af Signed-off-by: Deepak Katragadda --- .../devicetree/bindings/regulator/gdsc-regulator.txt | 2 ++ arch/arm/boot/dts/qcom/msm-gdsc-8996.dtsi | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/gdsc-regulator.txt b/Documentation/devicetree/bindings/regulator/gdsc-regulator.txt index b4ef2566727b..02a2cb2551c1 100644 --- a/Documentation/devicetree/bindings/regulator/gdsc-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/gdsc-regulator.txt @@ -46,6 +46,8 @@ Optional properties: - qcom,disallow-clear: Presence denotes the periph & core memory will not be cleared, unless the required subsystem does not invoke the api which will allow clearing the bits. + - qcom,gds-timeout: Maximum time (in usecs) that might be taken by a GDSC + to enable. Example: gdsc_oxili_gx: qcom,gdsc@fd8c4024 { diff --git a/arch/arm/boot/dts/qcom/msm-gdsc-8996.dtsi b/arch/arm/boot/dts/qcom/msm-gdsc-8996.dtsi index 3c536e158f2d..2f0f4695a5c9 100644 --- a/arch/arm/boot/dts/qcom/msm-gdsc-8996.dtsi +++ b/arch/arm/boot/dts/qcom/msm-gdsc-8996.dtsi @@ -26,6 +26,7 @@ <0x8c120c 0x4>; reg-names = "base", "hw_ctrl_addr"; qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; status = "disabled"; }; @@ -36,6 +37,7 @@ <0x8c2480 0x4>; reg-names = "base", "hw_ctrl_addr"; qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; status = "disabled"; }; @@ -46,6 +48,7 @@ <0x8c3c50 0x4>; reg-names = "base", "hw_ctrl_addr"; qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; status = "disabled"; }; @@ -161,6 +164,7 @@ <0x8c4038 0x4>; reg-names = "base", "hw_ctrl_addr"; qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; status = "disabled"; }; @@ -204,6 +208,7 @@ <0x381028 0x4>; reg-names = "base", "hw_ctrl_addr"; qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; status = "disabled"; }; };