qpnp-fg-gen3: add support to configure ki coefficients during discharge
During medium and high discharging scenario, voltage mode correction needs to be applied so that the battery SOC can follow closely with the battery voltage. Add support for this by configuring the ki coefficients for medium and high discharge current during discharging. Change-Id: I0a76e9e2f74c40b55e01f9dc106d31a148edefdf Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
This commit is contained in:
Subbaraman Narayanamurthy
parent
54b2b24dea
commit
d352e8e9b5
3 changed files with 200 additions and 0 deletions
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@ -222,6 +222,36 @@ First Level Node - FG Gen3 device
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Definition: A boolean property that when defined holds SOC at 100% when
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the battery is full.
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- qcom,ki-coeff-soc-dischg:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: Array of monotonic SOC threshold values to change the ki
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coefficient for medium discharge current during discharge.
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This should be defined in the ascending order and in the
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range of 0-100. Array limit is set to 3.
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- qcom,ki-coeff-med-dischg:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: Array of ki coefficient values for medium discharge current
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during discharge. These values will be applied when the
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monotonic SOC goes below the SOC threshold specified under
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qcom,ki-coeff-soc-dischg. Array limit is set to 3. This
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property should be specified if qcom,ki-coeff-soc-dischg
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is specified to make it fully functional. Value has no
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unit. Allowed range is 0 to 62200 in micro units.
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- qcom,ki-coeff-hi-dischg:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: Array of ki coefficient values for high discharge current
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during discharge. These values will be applied when the
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monotonic SOC goes below the SOC threshold specified under
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qcom,ki-coeff-soc-dischg. Array limit is set to 3. This
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property should be specified if qcom,ki-coeff-soc-dischg
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is specified to make it fully functional. Value has no
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unit. Allowed range is 0 to 62200 in micro units.
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==========================================================
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Second Level Nodes - Peripherals managed by FG Gen3 driver
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==========================================================
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@ -252,6 +282,9 @@ pmicobalt_fg: qpnp,fg {
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qcom,pmic-revid = <&pmicobalt_revid>;
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io-channels = <&pmicobalt_rradc 3>;
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io-channel-names = "rradc_batt_id";
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qcom,ki-coeff-soc-dischg = <30 60 90>;
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qcom,ki-coeff-med-dischg = <800 1000 1400>;
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qcom,ki-coeff-hi-dischg = <1200 1500 2100>;
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status = "okay";
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qcom,fg-batt-soc@4000 {
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@ -61,6 +61,9 @@
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#define BUCKET_COUNT 8
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#define BUCKET_SOC_PCT (256 / BUCKET_COUNT)
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#define KI_COEFF_MAX 62200
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#define KI_COEFF_SOC_LEVELS 3
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/* Debug flag definitions */
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enum fg_debug_flag {
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FG_IRQ = BIT(0), /* Show interrupts */
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@ -139,6 +142,8 @@ enum fg_sram_param_id {
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FG_SRAM_CHG_TERM_CURR,
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FG_SRAM_DELTA_SOC_THR,
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FG_SRAM_RECHARGE_SOC_THR,
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FG_SRAM_KI_COEFF_MED_DISCHG,
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FG_SRAM_KI_COEFF_HI_DISCHG,
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FG_SRAM_MAX,
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};
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@ -198,6 +203,9 @@ struct fg_dt_props {
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int cl_min_cap_limit;
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int jeita_hyst_temp;
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int batt_temp_delta;
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int ki_coeff_soc[KI_COEFF_SOC_LEVELS];
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int ki_coeff_med_dischg[KI_COEFF_SOC_LEVELS];
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int ki_coeff_hi_dischg[KI_COEFF_SOC_LEVELS];
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};
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/* parameters from battery profile */
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@ -275,6 +283,7 @@ struct fg_chip {
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bool fg_restarting;
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bool charge_full;
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bool recharge_soc_adjusted;
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bool ki_coeff_dischg_en;
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struct completion soc_update;
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struct completion soc_ready;
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struct delayed_work profile_load_work;
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@ -36,6 +36,12 @@
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#define SYS_TERM_CURR_OFFSET 0
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#define VBATT_FULL_WORD 7
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#define VBATT_FULL_OFFSET 0
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#define KI_COEFF_MED_DISCHG_WORD 9
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#define KI_COEFF_MED_DISCHG_OFFSET 3
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#define KI_COEFF_HI_DISCHG_WORD 10
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#define KI_COEFF_HI_DISCHG_OFFSET 0
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#define KI_COEFF_LOW_DISCHG_WORD 10
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#define KI_COEFF_LOW_DISCHG_OFFSET 2
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#define DELTA_SOC_THR_WORD 12
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#define DELTA_SOC_THR_OFFSET 3
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#define RECHARGE_SOC_THR_WORD 14
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@ -88,6 +94,12 @@
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#define ALG_FLAGS_OFFSET 1
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/* v2 SRAM address and offset in ascending order */
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#define KI_COEFF_LOW_DISCHG_v2_WORD 9
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#define KI_COEFF_LOW_DISCHG_v2_OFFSET 3
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#define KI_COEFF_MED_DISCHG_v2_WORD 10
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#define KI_COEFF_MED_DISCHG_v2_OFFSET 0
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#define KI_COEFF_HI_DISCHG_v2_WORD 10
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#define KI_COEFF_HI_DISCHG_v2_OFFSET 1
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#define DELTA_SOC_THR_v2_WORD 13
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#define DELTA_SOC_THR_v2_OFFSET 0
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#define RECHARGE_SOC_THR_v2_WORD 14
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@ -173,6 +185,12 @@ static struct fg_sram_param pmicobalt_v1_sram_params[] = {
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ESR_TIMER_CHG_MAX_OFFSET, 2, 1, 1, 0, fg_encode_default, NULL),
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PARAM(ESR_TIMER_CHG_INIT, ESR_TIMER_CHG_INIT_WORD,
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ESR_TIMER_CHG_INIT_OFFSET, 2, 1, 1, 0, fg_encode_default, NULL),
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PARAM(KI_COEFF_MED_DISCHG, KI_COEFF_MED_DISCHG_WORD,
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KI_COEFF_MED_DISCHG_OFFSET, 1, 1000, 244141, 0,
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fg_encode_default, NULL),
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PARAM(KI_COEFF_HI_DISCHG, KI_COEFF_HI_DISCHG_WORD,
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KI_COEFF_HI_DISCHG_OFFSET, 1, 1000, 244141, 0,
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fg_encode_default, NULL),
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};
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static struct fg_sram_param pmicobalt_v2_sram_params[] = {
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@ -222,6 +240,12 @@ static struct fg_sram_param pmicobalt_v2_sram_params[] = {
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ESR_TIMER_CHG_MAX_OFFSET, 2, 1, 1, 0, fg_encode_default, NULL),
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PARAM(ESR_TIMER_CHG_INIT, ESR_TIMER_CHG_INIT_WORD,
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ESR_TIMER_CHG_INIT_OFFSET, 2, 1, 1, 0, fg_encode_default, NULL),
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PARAM(KI_COEFF_MED_DISCHG, KI_COEFF_MED_DISCHG_v2_WORD,
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KI_COEFF_MED_DISCHG_v2_OFFSET, 1, 1000, 244141, 0,
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fg_encode_default, NULL),
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PARAM(KI_COEFF_HI_DISCHG, KI_COEFF_HI_DISCHG_v2_WORD,
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KI_COEFF_HI_DISCHG_v2_OFFSET, 1, 1000, 244141, 0,
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fg_encode_default, NULL),
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};
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static struct fg_alg_flag pmicobalt_v1_alg_flags[] = {
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@ -1124,6 +1148,60 @@ out:
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mutex_unlock(&chip->cl.lock);
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}
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#define KI_COEFF_MED_DISCHG_DEFAULT 1500
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#define KI_COEFF_HI_DISCHG_DEFAULT 2200
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static int fg_adjust_ki_coeff_dischg(struct fg_chip *chip)
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{
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int rc, i, msoc;
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int ki_coeff_med = KI_COEFF_MED_DISCHG_DEFAULT;
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int ki_coeff_hi = KI_COEFF_HI_DISCHG_DEFAULT;
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u8 val;
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if (!chip->ki_coeff_dischg_en)
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return 0;
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rc = fg_get_prop_capacity(chip, &msoc);
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if (rc < 0) {
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pr_err("Error in getting capacity, rc=%d\n", rc);
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return rc;
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}
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if (chip->status == POWER_SUPPLY_STATUS_DISCHARGING) {
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for (i = KI_COEFF_SOC_LEVELS - 1; i >= 0; i--) {
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if (msoc < chip->dt.ki_coeff_soc[i]) {
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ki_coeff_med = chip->dt.ki_coeff_med_dischg[i];
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ki_coeff_hi = chip->dt.ki_coeff_hi_dischg[i];
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}
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}
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}
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fg_encode(chip->sp, FG_SRAM_KI_COEFF_MED_DISCHG, ki_coeff_med, &val);
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rc = fg_sram_write(chip,
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chip->sp[FG_SRAM_KI_COEFF_MED_DISCHG].addr_word,
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chip->sp[FG_SRAM_KI_COEFF_MED_DISCHG].addr_byte, &val,
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chip->sp[FG_SRAM_KI_COEFF_MED_DISCHG].len,
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FG_IMA_DEFAULT);
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if (rc < 0) {
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pr_err("Error in writing ki_coeff_med, rc=%d\n", rc);
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return rc;
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}
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fg_encode(chip->sp, FG_SRAM_KI_COEFF_HI_DISCHG, ki_coeff_hi, &val);
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rc = fg_sram_write(chip,
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chip->sp[FG_SRAM_KI_COEFF_HI_DISCHG].addr_word,
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chip->sp[FG_SRAM_KI_COEFF_HI_DISCHG].addr_byte, &val,
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chip->sp[FG_SRAM_KI_COEFF_HI_DISCHG].len,
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FG_IMA_DEFAULT);
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if (rc < 0) {
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pr_err("Error in writing ki_coeff_hi, rc=%d\n", rc);
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return rc;
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}
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fg_dbg(chip, FG_STATUS, "Wrote ki_coeff_med %d ki_coeff_hi %d\n",
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ki_coeff_med, ki_coeff_hi);
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return 0;
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}
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static int fg_charge_full_update(struct fg_chip *chip)
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{
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union power_supply_propval prop = {0, };
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@ -1298,6 +1376,7 @@ static void status_change_work(struct work_struct *work)
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schedule_work(&chip->cycle_count_work);
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fg_cap_learning_update(chip);
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rc = fg_charge_full_update(chip);
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if (rc < 0)
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pr_err("Error in charge_full_update, rc=%d\n", rc);
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@ -1306,6 +1385,9 @@ static void status_change_work(struct work_struct *work)
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if (rc < 0)
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pr_err("Error in adjusting recharge_soc, rc=%d\n", rc);
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rc = fg_adjust_ki_coeff_dischg(chip);
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if (rc < 0)
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pr_err("Error in adjusting ki_coeff_dischg, rc=%d\n", rc);
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out:
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pm_relax(chip->dev);
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}
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@ -2138,6 +2220,10 @@ static irqreturn_t fg_delta_soc_irq_handler(int irq, void *data)
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if (rc < 0)
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pr_err("Error in charge_full_update, rc=%d\n", rc);
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rc = fg_adjust_ki_coeff_dischg(chip);
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if (rc < 0)
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pr_err("Error in adjusting ki_coeff_dischg, rc=%d\n", rc);
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return IRQ_HANDLED;
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}
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@ -2298,6 +2384,73 @@ static int fg_register_interrupts(struct fg_chip *chip)
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return 0;
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}
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static int fg_parse_ki_coefficients(struct fg_chip *chip)
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{
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struct device_node *node = chip->dev->of_node;
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int rc, i;
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rc = of_property_count_elems_of_size(node, "qcom,ki-coeff-soc-dischg",
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sizeof(u32));
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if (rc != KI_COEFF_SOC_LEVELS)
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return 0;
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rc = of_property_read_u32_array(node, "qcom,ki-coeff-soc-dischg",
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chip->dt.ki_coeff_soc, KI_COEFF_SOC_LEVELS);
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if (rc < 0) {
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pr_err("Error in reading ki-coeff-soc-dischg, rc=%d\n",
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rc);
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return rc;
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}
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rc = of_property_count_elems_of_size(node, "qcom,ki-coeff-med-dischg",
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sizeof(u32));
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if (rc != KI_COEFF_SOC_LEVELS)
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return 0;
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rc = of_property_read_u32_array(node, "qcom,ki-coeff-med-dischg",
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chip->dt.ki_coeff_med_dischg, KI_COEFF_SOC_LEVELS);
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if (rc < 0) {
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pr_err("Error in reading ki-coeff-med-dischg, rc=%d\n",
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rc);
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return rc;
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}
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rc = of_property_count_elems_of_size(node, "qcom,ki-coeff-hi-dischg",
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sizeof(u32));
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if (rc != KI_COEFF_SOC_LEVELS)
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return 0;
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rc = of_property_read_u32_array(node, "qcom,ki-coeff-hi-dischg",
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chip->dt.ki_coeff_hi_dischg, KI_COEFF_SOC_LEVELS);
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if (rc < 0) {
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pr_err("Error in reading ki-coeff-hi-dischg, rc=%d\n",
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rc);
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return rc;
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}
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for (i = 0; i < KI_COEFF_SOC_LEVELS; i++) {
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if (chip->dt.ki_coeff_soc[i] < 0 ||
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chip->dt.ki_coeff_soc[i] > FULL_CAPACITY) {
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pr_err("Error in ki_coeff_soc_dischg values\n");
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return -EINVAL;
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}
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if (chip->dt.ki_coeff_med_dischg[i] < 0 ||
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chip->dt.ki_coeff_med_dischg[i] > KI_COEFF_MAX) {
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pr_err("Error in ki_coeff_med_dischg values\n");
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return -EINVAL;
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}
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if (chip->dt.ki_coeff_med_dischg[i] < 0 ||
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chip->dt.ki_coeff_med_dischg[i] > KI_COEFF_MAX) {
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pr_err("Error in ki_coeff_med_dischg values\n");
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return -EINVAL;
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}
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}
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chip->ki_coeff_dischg_en = true;
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return 0;
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}
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#define DEFAULT_CUTOFF_VOLT_MV 3200
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#define DEFAULT_EMPTY_VOLT_MV 3100
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#define DEFAULT_CHG_TERM_CURR_MA 100
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@ -2562,6 +2715,11 @@ static int fg_parse_dt(struct fg_chip *chip)
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chip->dt.hold_soc_while_full = of_property_read_bool(node,
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"qcom,hold-soc-while-full");
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rc = fg_parse_ki_coefficients(chip);
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if (rc < 0)
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pr_err("Error in parsing Ki coefficients, rc=%d\n", rc);
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return 0;
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}
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