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ARM: cache-v7: optimise branches in v7_flush_cache_louis

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Optimise the branches such that for the majority of unaffected devices,
we avoid needing to execute the errata work-around code path by
branching to start_flush_levels early.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2015-04-03 11:25:39 +01:00
parent cd8b24d9e8
commit d3cd451dfb
1 changed files with 10 additions and 9 deletions
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19
arch/arm/mm/cache-v7.S
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@ -93,17 +93,18 @@ ENTRY(v7_flush_dcache_louis)
ALT_SMP(mov r3, r0, lsr #20) @ move LoUIS into position ALT_SMP(mov r3, r0, lsr #20) @ move LoUIS into position
ALT_UP( mov r3, r0, lsr #26) @ move LoUU into position ALT_UP( mov r3, r0, lsr #26) @ move LoUU into position
ands r3, r3, #7 << 1 @ extract LoU*2 field from clidr ands r3, r3, #7 << 1 @ extract LoU*2 field from clidr
bne start_flush_levels @ LoU != 0, start flushing
#ifdef CONFIG_ARM_ERRATA_643719 #ifdef CONFIG_ARM_ERRATA_643719
ALT_SMP(mrceq p15, 0, r2, c0, c0, 0) @ read main ID register ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register
ALT_UP(reteq lr) @ LoUU is zero, so nothing to do ALT_UP( ret lr) @ LoUU is zero, so nothing to do
movweq r1, #:lower16:0x410fc090 @ ID of ARM Cortex A9 r0p? movw r1, #:lower16:0x410fc090 @ ID of ARM Cortex A9 r0p?
movteq r1, #:upper16:0x410fc090 movt r1, #:upper16:0x410fc090
biceq r2, r2, #0x0000000f @ clear minor revision number bic r2, r2, #0x0000000f @ clear minor revision number
teqeq r2, r1 @ test for errata affected core and if so... teq r2, r1 @ test for errata affected core and if so...
moveqs r3, #1 << 1 @ fix LoUIS value (and set flags state to 'ne') moveq r3, #1 << 1 @ fix LoUIS value
beq start_flush_levels @ start flushing cache levels
#endif #endif
reteq lr @ return if level == 0 ret lr
b start_flush_levels @ start flushing cache levels
ENDPROC(v7_flush_dcache_louis) ENDPROC(v7_flush_dcache_louis)
/* /*