Merge "clock: qcom: Update the list of clocks supported on MSMFalcon"
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d43110ab63
4 changed files with 446 additions and 416 deletions
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@ -314,6 +314,16 @@
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#clock-cells = <1>;
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};
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clock_mmss: qcom,dummycc {
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compatible = "qcom,dummycc";
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#clock-cells = <1>;
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};
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clock_gfx: qcom,dummycc {
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compatible = "qcom,dummycc";
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#clock-cells = <1>;
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};
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qcom,ipc-spinlock@1f40000 {
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compatible = "qcom,ipc-spinlock-sfpb";
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reg = <0x1f40000 0x8000>;
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@ -14,230 +14,229 @@
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#ifndef _DT_BINDINGS_CLK_MSM_GCC_FALCON_H
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#define _DT_BINDINGS_CLK_MSM_GCC_FALCON_H
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/* Clocks */
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#define GPLL0 0
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#define GPLL1 1
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#define GPLL2 2
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#define GPLL3 3
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#define GPLL4 4
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#define GPLL5 5
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#define GPLL6 6
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#define MMSS_QM_CORE_CLK_SRC 7
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#define USB30_MASTER_CLK_SRC 8
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#define USB30_MOCK_UTMI_CLK_SRC 9
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#define USB3_PHY_AUX_CLK_SRC 10
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#define USB20_MASTER_CLK_SRC 11
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#define USB20_MOCK_UTMI_CLK_SRC 12
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#define SDCC2_APPS_CLK_SRC 13
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#define SDCC1_ICE_CORE_CLK_SRC 14
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#define SDCC1_APPS_CLK_SRC 15
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 16
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 17
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#define BLSP1_UART1_APPS_CLK_SRC 18
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 20
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#define BLSP1_UART2_APPS_CLK_SRC 21
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 22
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 23
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 24
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 25
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#define BLSP2_QUP1_SPI_APPS_CLK_SRC 26
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#define BLSP2_QUP1_I2C_APPS_CLK_SRC 27
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#define BLSP2_UART1_APPS_CLK_SRC 28
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#define BLSP2_QUP2_SPI_APPS_CLK_SRC 29
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#define BLSP2_QUP2_I2C_APPS_CLK_SRC 30
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#define BLSP2_UART2_APPS_CLK_SRC 31
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#define BLSP2_QUP3_SPI_APPS_CLK_SRC 32
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#define BLSP2_QUP3_I2C_APPS_CLK_SRC 33
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#define BLSP2_QUP4_SPI_APPS_CLK_SRC 34
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#define BLSP2_QUP4_I2C_APPS_CLK_SRC 35
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#define PDM2_CLK_SRC 36
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#define HMSS_AHB_CLK_SRC 37
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#define BIMC_HMSS_AXI_CLK_SRC 38
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#define HMSS_RBCPR_CLK_SRC 39
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#define HMSS_GPLL0_CLK_SRC 40
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#define HMSS_GPLL4_CLK_SRC 41
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#define GP1_CLK_SRC 42
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#define GP2_CLK_SRC 43
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#define GP3_CLK_SRC 44
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#define UFS_AXI_CLK_SRC 45
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#define UFS_ICE_CORE_CLK_SRC 46
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#define UFS_UNIPRO_CORE_CLK_SRC 47
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#define UFS_PHY_AUX_CLK_SRC 48
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#define QSPI_SER_CLK_SRC 49
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#define GLM_CLK_SRC 50
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#define GCC_MMSS_SYS_NOC_AXI_CLK 51
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#define GCC_MMSS_NOC_CFG_AHB_CLK 52
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#define GCC_MMSS_QM_CORE_CLK 53
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#define GCC_MMSS_QM_AHB_CLK 54
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#define GCC_USB30_MASTER_CLK 55
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#define GCC_USB30_SLEEP_CLK 56
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#define GCC_USB30_MOCK_UTMI_CLK 57
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#define GCC_USB3_PHY_AUX_CLK 58
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#define GCC_USB3_PHY_PIPE_CLK 59
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#define GCC_USB20_MASTER_CLK 60
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#define GCC_USB20_SLEEP_CLK 61
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#define GCC_USB20_MOCK_UTMI_CLK 62
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 63
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#define GCC_SDCC2_APPS_CLK 64
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#define GCC_SDCC2_AHB_CLK 65
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#define GCC_SDCC1_APPS_CLK 66
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#define GCC_SDCC1_AHB_CLK 67
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#define GCC_SDCC1_ICE_CORE_CLK 68
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#define GCC_BLSP1_AHB_CLK 69
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#define GCC_BLSP1_SLEEP_CLK 70
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 71
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 72
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#define GCC_BLSP1_UART1_APPS_CLK 73
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 74
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 75
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#define GCC_BLSP1_UART2_APPS_CLK 76
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 77
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 78
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 79
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 80
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#define GCC_BLSP2_AHB_CLK 81
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#define GCC_BLSP2_SLEEP_CLK 82
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#define GCC_BLSP2_QUP1_SPI_APPS_CLK 83
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#define GCC_BLSP2_QUP1_I2C_APPS_CLK 84
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#define GCC_BLSP2_UART1_APPS_CLK 85
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#define GCC_BLSP2_QUP2_SPI_APPS_CLK 86
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#define GCC_BLSP2_QUP2_I2C_APPS_CLK 87
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#define GCC_BLSP2_UART2_APPS_CLK 88
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#define GCC_BLSP2_QUP3_SPI_APPS_CLK 89
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#define GCC_BLSP2_QUP3_I2C_APPS_CLK 90
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#define GCC_BLSP2_QUP4_SPI_APPS_CLK 91
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#define GCC_BLSP2_QUP4_I2C_APPS_CLK 92
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#define GCC_PDM_AHB_CLK 93
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#define GCC_PDM_XO4_CLK 94
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#define GCC_PDM2_CLK 95
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#define GCC_PRNG_AHB_CLK 96
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#define GCC_BIMC_GFX_CLK 97
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#define GCC_MCCC_CFG_AHB_CLK 98
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#define GCC_LPASS_TRIG_CLK 99
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#define GCC_LPASS_AT_CLK 100
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#define GCC_TURING_TRIG_CLK 101
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#define GCC_TURING_AT_CLK 102
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#define GCC_HMSS_AHB_CLK 103
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#define GCC_BIMC_HMSS_AXI_CLK 104
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#define GCC_HMSS_RBCPR_CLK 105
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#define GCC_HMSS_TRIG_CLK 106
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#define GCC_HMSS_AT_CLK 107
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#define GCC_HMSS_DVM_BUS_CLK 108
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#define GCC_GP1_CLK 109
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#define GCC_GP2_CLK 110
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#define GCC_GP3_CLK 111
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#define GCC_UFS_AXI_CLK 112
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#define GCC_UFS_AHB_CLK 113
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#define GCC_UFS_TX_SYMBOL_0_CLK 114
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#define GCC_UFS_RX_SYMBOL_0_CLK 115
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#define GCC_UFS_UNIPRO_CORE_CLK 116
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#define GCC_UFS_ICE_CORE_CLK 117
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#define GCC_UFS_PHY_AUX_CLK 118
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#define GCC_UFS_RX_SYMBOL_1_CLK 119
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#define GCC_AGGRE2_USB3_AXI_CLK 120
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#define GCC_AGGRE2_UFS_AXI_CLK 121
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#define GCC_QSPI_AHB_CLK 122
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#define GCC_QSPI_SER_CLK 123
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#define GCC_GLM_AHB_CLK 124
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#define GCC_GLM_CLK 125
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#define GCC_GLM_XO_CLK 126
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#define GCC_WCSS_AHB_S0_CLK 127
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#define GCC_WCSS_AXI_M_CLK 128
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#define GCC_WCSS_ECAHB_CLK 129
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#define GCC_WCSS_SHDREG_AHB_CLK 130
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#define GCC_GPU_CFG_AHB_CLK 131
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#define GCC_GPU_BIMC_GFX_SRC_CLK 132
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#define GCC_GPU_BIMC_GFX_CLK 133
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#define GCC_GPU_SNOC_DVM_GFX_CLK 134
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#define BIMC_HMSS_AXI_CLK_SRC 0
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 1
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 2
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 3
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 4
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 5
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 6
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 7
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 8
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#define BLSP1_UART1_APPS_CLK_SRC 9
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#define BLSP1_UART2_APPS_CLK_SRC 10
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#define BLSP2_QUP1_I2C_APPS_CLK_SRC 11
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#define BLSP2_QUP1_SPI_APPS_CLK_SRC 12
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#define BLSP2_QUP2_I2C_APPS_CLK_SRC 13
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#define BLSP2_QUP2_SPI_APPS_CLK_SRC 14
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#define BLSP2_QUP3_I2C_APPS_CLK_SRC 15
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#define BLSP2_QUP3_SPI_APPS_CLK_SRC 16
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#define BLSP2_QUP4_I2C_APPS_CLK_SRC 17
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#define BLSP2_QUP4_SPI_APPS_CLK_SRC 18
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#define BLSP2_UART1_APPS_CLK_SRC 19
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#define BLSP2_UART2_APPS_CLK_SRC 20
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#define GCC_AGGRE2_UFS_AXI_CLK 21
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#define GCC_AGGRE2_USB3_AXI_CLK 22
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#define GCC_BIMC_GFX_CLK 23
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#define GCC_BIMC_HMSS_AXI_CLK 24
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#define GCC_BIMC_MSS_Q6_AXI_CLK 25
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#define GCC_BLSP1_AHB_CLK 26
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 27
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 28
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 29
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 30
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 31
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 32
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 33
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 34
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#define GCC_BLSP1_UART1_APPS_CLK 35
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#define GCC_BLSP1_UART2_APPS_CLK 36
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#define GCC_BLSP2_AHB_CLK 37
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#define GCC_BLSP2_QUP1_I2C_APPS_CLK 38
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#define GCC_BLSP2_QUP1_SPI_APPS_CLK 39
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#define GCC_BLSP2_QUP2_I2C_APPS_CLK 40
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#define GCC_BLSP2_QUP2_SPI_APPS_CLK 41
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#define GCC_BLSP2_QUP3_I2C_APPS_CLK 42
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#define GCC_BLSP2_QUP3_SPI_APPS_CLK 43
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#define GCC_BLSP2_QUP4_I2C_APPS_CLK 44
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#define GCC_BLSP2_QUP4_SPI_APPS_CLK 45
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#define GCC_BLSP2_UART1_APPS_CLK 46
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#define GCC_BLSP2_UART2_APPS_CLK 47
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#define GCC_BOOT_ROM_AHB_CLK 48
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#define GCC_CFG_NOC_USB2_AXI_CLK 49
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#define GCC_CFG_NOC_USB3_AXI_CLK 50
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#define GCC_GLM_AHB_CLK 51
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#define GCC_GLM_CLK 52
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#define GCC_GP1_CLK 53
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#define GCC_GP2_CLK 54
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#define GCC_GP3_CLK 55
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#define GCC_GPU_BIMC_GFX_CLK 56
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#define GCC_GPU_BIMC_GFX_SRC_CLK 57
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#define GCC_GPU_CFG_AHB_CLK 58
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#define GCC_GPU_SNOC_DVM_GFX_CLK 59
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#define GCC_HMSS_AHB_CLK 60
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#define GCC_HMSS_DVM_BUS_CLK 61
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#define GCC_HMSS_RBCPR_CLK 62
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#define GCC_MMSS_NOC_CFG_AHB_CLK 63
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#define GCC_MMSS_QM_AHB_CLK 64
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#define GCC_MMSS_QM_CORE_CLK 65
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#define GCC_MMSS_SYS_NOC_AXI_CLK 66
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#define GCC_PDM2_CLK 67
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#define GCC_PDM_AHB_CLK 68
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#define GCC_PRNG_AHB_CLK 69
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#define GCC_QSPI_AHB_CLK 70
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#define GCC_QSPI_SER_CLK 71
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#define GCC_SDCC1_AHB_CLK 72
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#define GCC_SDCC1_APPS_CLK 73
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#define GCC_SDCC1_ICE_CORE_CLK 74
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#define GCC_SDCC2_AHB_CLK 75
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#define GCC_SDCC2_APPS_CLK 76
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#define GCC_UFS_AHB_CLK 77
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#define GCC_UFS_AXI_CLK 78
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#define GCC_UFS_ICE_CORE_CLK 79
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#define GCC_UFS_PHY_AUX_CLK 80
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#define GCC_UFS_RX_SYMBOL_0_CLK 81
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#define GCC_UFS_RX_SYMBOL_1_CLK 82
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#define GCC_UFS_TX_SYMBOL_0_CLK 83
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#define GCC_UFS_UNIPRO_CORE_CLK 84
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#define GCC_USB20_MASTER_CLK 85
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#define GCC_USB20_MOCK_UTMI_CLK 86
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#define GCC_USB20_SLEEP_CLK 87
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#define GCC_USB30_MASTER_CLK 88
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#define GCC_USB30_MOCK_UTMI_CLK 89
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#define GCC_USB30_SLEEP_CLK 90
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#define GCC_USB3_PHY_AUX_CLK 91
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#define GCC_USB3_PHY_PIPE_CLK 92
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 93
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#define GCC_WCSS_AHB_S0_CLK 94
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#define GCC_WCSS_AXI_M_CLK 95
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#define GCC_WCSS_ECAHB_CLK 96
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#define GCC_WCSS_SHDREG_AHB_CLK 97
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#define GLM_CLK_SRC 98
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#define GP1_CLK_SRC 99
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#define GP2_CLK_SRC 100
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#define GP3_CLK_SRC 101
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#define GPLL0 102
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#define GPLL0_OUT_AUX 103
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#define GPLL0_OUT_AUX2 104
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#define GPLL0_OUT_EARLY 105
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#define GPLL0_OUT_MAIN 106
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#define GPLL0_OUT_TEST 107
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#define GPLL1 108
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#define GPLL1_OUT_AUX 109
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#define GPLL1_OUT_AUX2 110
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#define GPLL1_OUT_EARLY 111
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#define GPLL1_OUT_MAIN 112
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#define GPLL1_OUT_TEST 113
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#define GPLL2 114
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#define GPLL2_OUT_AUX 115
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#define GPLL2_OUT_AUX2 116
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#define GPLL2_OUT_EARLY 117
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#define GPLL2_OUT_MAIN 118
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#define GPLL2_OUT_TEST 119
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#define GPLL3 120
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#define GPLL3_OUT_AUX 121
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#define GPLL3_OUT_AUX2 122
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#define GPLL3_OUT_EARLY 123
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#define GPLL3_OUT_MAIN 124
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#define GPLL3_OUT_TEST 125
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#define GPLL4 126
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#define GPLL4_OUT_AUX 127
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#define GPLL4_OUT_AUX2 128
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#define GPLL4_OUT_EARLY 129
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#define GPLL4_OUT_MAIN 130
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#define GPLL4_OUT_TEST 131
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#define GPLL5 132
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#define GPLL5_OUT_AUX 133
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#define GPLL5_OUT_AUX2 134
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#define GPLL5_OUT_EARLY 135
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#define GPLL5_OUT_MAIN 136
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#define GPLL5_OUT_TEST 137
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#define GPLL6 138
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#define GPLL6_OUT_AUX 139
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#define GPLL6_OUT_AUX2 140
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#define GPLL6_OUT_EARLY 141
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#define GPLL6_OUT_MAIN 142
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#define GPLL6_OUT_TEST 143
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#define HMSS_AHB_CLK_SRC 144
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#define HMSS_GPLL0_CLK_SRC 145
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#define HMSS_GPLL4_CLK_SRC 146
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#define HMSS_RBCPR_CLK_SRC 147
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#define MMSS_QM_CORE_CLK_SRC 148
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#define PDM2_CLK_SRC 149
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#define QSPI_SER_CLK_SRC 150
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#define SDCC1_APPS_CLK_SRC 151
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#define SDCC1_ICE_CORE_CLK_SRC 152
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#define SDCC2_APPS_CLK_SRC 153
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#define UFS_AXI_CLK_SRC 154
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#define UFS_ICE_CORE_CLK_SRC 155
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#define UFS_PHY_AUX_CLK_SRC 156
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#define UFS_UNIPRO_CORE_CLK_SRC 157
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#define USB20_MASTER_CLK_SRC 158
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#define USB20_MOCK_UTMI_CLK_SRC 159
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#define USB30_MASTER_CLK_SRC 160
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#define USB30_MOCK_UTMI_CLK_SRC 161
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#define USB3_PHY_AUX_CLK_SRC 162
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/* Block Resets */
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#define GCC_SYSTEM_NOC_BCR 0
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#define GCC_CONFIG_NOC_BCR 1
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#define GCC_IMEM_BCR 2
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#define GCC_MMSS_BCR 3
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#define GCC_PIMEM_BCR 4
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#define GCC_QDSS_BCR 5
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#define GCC_USB_30_BCR 6
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#define GCC_USB_20_BCR 7
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#define GCC_QUSB2PHY_PRIM_BCR 8
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#define GCC_QUSB2PHY_SEC_BCR 9
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
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#define GCC_SDCC2_BCR 11
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#define GCC_SDCC1_BCR 12
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#define GCC_BLSP1_BCR 13
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#define GCC_BLSP1_QUP1_BCR 14
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#define GCC_BLSP1_UART1_BCR 15
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#define GCC_BLSP1_QUP2_BCR 16
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#define GCC_BLSP1_UART2_BCR 17
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#define GCC_BLSP1_QUP3_BCR 18
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#define GCC_BLSP1_QUP4_BCR 19
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#define GCC_BLSP2_BCR 20
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#define GCC_BLSP2_QUP1_BCR 21
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#define GCC_BLSP2_UART1_BCR 22
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#define GCC_BLSP2_QUP2_BCR 23
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#define GCC_BLSP2_UART2_BCR 24
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#define GCC_BLSP2_QUP3_BCR 25
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#define GCC_BLSP2_QUP4_BCR 26
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#define GCC_PDM_BCR 27
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#define GCC_PRNG_BCR 28
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#define GCC_TCSR_BCR 29
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#define GCC_BOOT_ROM_BCR 30
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#define GCC_MSG_RAM_BCR 31
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#define GCC_TLMM_BCR 32
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#define GCC_MPM_BCR 33
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#define GCC_SEC_CTRL_BCR 34
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#define GCC_SPMI_BCR 35
|
||||
#define GCC_SPDM_BCR 36
|
||||
#define GCC_CE1_BCR 37
|
||||
#define GCC_BIMC_BCR 38
|
||||
#define GCC_SNOC_BUS_TIMEOUT0_BCR 39
|
||||
#define GCC_SNOC_BUS_TIMEOUT1_BCR 40
|
||||
#define GCC_SNOC_BUS_TIMEOUT3_BCR 41
|
||||
#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 42
|
||||
#define GCC_SNOC_BUS_TIMEOUT4_BCR 43
|
||||
#define GCC_PNOC_BUS_TIMEOUT0_BCR 44
|
||||
#define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR 45
|
||||
#define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR 46
|
||||
#define GCC_CNOC_BUS_TIMEOUT0_BCR 47
|
||||
#define GCC_CNOC_BUS_TIMEOUT2_BCR 48
|
||||
#define GCC_CNOC_BUS_TIMEOUT3_BCR 49
|
||||
#define GCC_CNOC_BUS_TIMEOUT4_BCR 50
|
||||
#define GCC_CNOC_BUS_TIMEOUT5_BCR 51
|
||||
#define GCC_CNOC_BUS_TIMEOUT6_BCR 52
|
||||
#define GCC_CNOC_BUS_TIMEOUT7_BCR 53
|
||||
#define GCC_CNOC_BUS_TIMEOUT8_BCR 54
|
||||
#define GCC_CNOC_BUS_TIMEOUT9_BCR 55
|
||||
#define GCC_CNOC_BUS_TIMEOUT10_BCR 56
|
||||
#define GCC_CNOC_BUS_TIMEOUT11_BCR 57
|
||||
#define GCC_CNOC_BUS_TIMEOUT12_BCR 58
|
||||
#define GCC_CNOC_BUS_TIMEOUT13_BCR 59
|
||||
#define GCC_CNOC_BUS_TIMEOUT14_BCR 60
|
||||
#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 61
|
||||
#define GCC_APB2JTAG_BCR 62
|
||||
#define GCC_RBCPR_CX_BCR 63
|
||||
#define GCC_RBCPR_MX_BCR 64
|
||||
#define GCC_OBT_ODT_BCR 65
|
||||
#define GCC_UFS_BCR 66
|
||||
#define GCC_VS_BCR 67
|
||||
#define GCC_AGGRE2_NOC_BCR 68
|
||||
#define GCC_DCC_BCR 69
|
||||
#define GCC_QSPI_BCR 70
|
||||
#define GCC_IPA_BCR 71
|
||||
#define GCC_GLM_BCR 72
|
||||
#define GCC_MSMPU_BCR 73
|
||||
#define GCC_QREFS_VBG_CAL_BCR 74
|
||||
#define GCC_WCSS_BCR 75
|
||||
#define GCC_GPU_BCR 76
|
||||
#define GCC_AHB2PHY_EAST_BCR 77
|
||||
#define GCC_CM_PHY_REFGEN1_BCR 78
|
||||
#define GCC_CM_PHY_REFGEN2_BCR 79
|
||||
#define GCC_SRAM_SENSOR_BCR 80
|
||||
#define UFS_GDSC 0
|
||||
#define USB_30_GDSC 1
|
||||
|
||||
/* GDSC */
|
||||
#define UFS_GDSC 0
|
||||
#define USB_30_GDSC 1
|
||||
#define DDR_DIM_WRAPPER_GDSC 2
|
||||
#define MMSS_GDSC 3
|
||||
#define GCC_QUSB2PHY_PRIM_BCR 0
|
||||
#define GCC_QUSB2PHY_SEC_BCR 1
|
||||
#define GCC_UFS_BCR 2
|
||||
#define GCC_USB3_DP_PHY_BCR 3
|
||||
#define GCC_USB3_PHY_BCR 4
|
||||
#define GCC_USB3PHY_PHY_BCR 5
|
||||
#define GCC_USB_20_BCR 6
|
||||
#define GCC_USB_30_BCR 7
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
|
||||
|
||||
/* RPM controlled clocks */
|
||||
#define RPM_CE1_CLK 1
|
||||
#define RPM_CE1_A_CLK 2
|
||||
#define RPM_CXO_CLK_SRC 3
|
||||
#define RPM_BIMC_CLK 4
|
||||
#define RPM_BIMC_A_CLK 5
|
||||
#define RPM_CNOC_CLK 6
|
||||
#define RPM_CNOC_A_CLK 7
|
||||
#define RPM_SNOC_CLK 8
|
||||
#define RPM_SNOC_A_CLK 9
|
||||
#define RPM_CNOC_PERIPH_CLK 10
|
||||
#define RPM_CNOC_PERIPH_A_CLK 11
|
||||
#define RPM_CNOC_PERIPH_KEEPALIVE_A_CLK 12
|
||||
#define RPM_LN_BB_CLK1 13
|
||||
#define RPM_LN_BB_CLK1_AO 14
|
||||
#define RPM_LN_BB_CLK1_PIN 15
|
||||
#define RPM_LN_BB_CLK1_PIN_AO 16
|
||||
#define RPM_BIMC_MSMBUS_CLK 17
|
||||
#define RPM_BIMC_MSMBUS_A_CLK 18
|
||||
#define RPM_CNOC_MSMBUS_CLK 19
|
||||
#define RPM_CNOC_MSMBUS_A_CLK 20
|
||||
#define RPM_CXO_CLK_SRC_AO 21
|
||||
#define RPM_CXO_DWC3_CLK 22
|
||||
#define RPM_CXO_LPM_CLK 23
|
||||
#define RPM_CXO_OTG_CLK 24
|
||||
#define RPM_CXO_PIL_LPASS_CLK 25
|
||||
#define RPM_CXO_PIL_SSC_CLK 26
|
||||
#define RPM_CXO_PIL_SPSS_CLK 27
|
||||
#define RPM_DIV_CLK1 28
|
||||
#define RPM_DIV_CLK1_AO 29
|
||||
#define RPM_IPA_CLK 30
|
||||
#define RPM_IPA_A_CLK 31
|
||||
#define RPM_MCD_CE1_CLK 32
|
||||
#define RPM_MMSSNOC_AXI_CLK 33
|
||||
#define RPM_MMSSNOC_AXI_A_CLK 34
|
||||
#define RPM_QCEDEV_CE1_CLK 35
|
||||
#define RPM_QCRYPTO_CE1_CLK 36
|
||||
#define RPM_QDSS_CLK 37
|
||||
#define RPM_QDSS_A_CLK 38
|
||||
#define RPM_QSEECOM_CE1_CLK 39
|
||||
#define RPM_RF_CLK2 40
|
||||
#define RPM_RF_CLK2_AO 41
|
||||
#define RPM_SCM_CE1_CLK 42
|
||||
#define RPM_SNOC_MSMBUS_CLK 43
|
||||
#define RPM_SNOC_MSMBUS_A_CLK 44
|
||||
#define RPM_AGGRE2_NOC_CLK 45
|
||||
#define RPM_AGGRE2_NOC_A_CLK 46
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -14,25 +14,27 @@
|
|||
#ifndef _DT_BINDINGS_CLK_MSM_GPU_FALCON_H
|
||||
#define _DT_BINDINGS_CLK_MSM_GPU_FALCON_H
|
||||
|
||||
/* Clocks */
|
||||
#define GPU_PLL0_PLL 0
|
||||
#define GPU_PLL1_PLL 1
|
||||
#define GFX3D_CLK_SRC 2
|
||||
#define RBBMTIMER_CLK_SRC 3
|
||||
#define RBCPR_CLK_SRC 4
|
||||
#define GPUCC_CXO_CLK 5
|
||||
#define GPUCC_GFX3D_CLK 6
|
||||
#define GPUCC_RBBMTIMER_CLK 7
|
||||
#define GPUCC_RBCPR_CLK 8
|
||||
#define GFX3D_CLK_SRC 0
|
||||
#define GPU_PLL0_PLL 1
|
||||
#define GPU_PLL0_PLL_OUT_AUX 2
|
||||
#define GPU_PLL0_PLL_OUT_AUX2 3
|
||||
#define GPU_PLL0_PLL_OUT_EARLY 4
|
||||
#define GPU_PLL0_PLL_OUT_MAIN 5
|
||||
#define GPU_PLL0_PLL_OUT_TEST 6
|
||||
#define GPU_PLL1_PLL 7
|
||||
#define GPU_PLL1_PLL_OUT_AUX 8
|
||||
#define GPU_PLL1_PLL_OUT_AUX2 9
|
||||
#define GPU_PLL1_PLL_OUT_EARLY 10
|
||||
#define GPU_PLL1_PLL_OUT_MAIN 11
|
||||
#define GPU_PLL1_PLL_OUT_TEST 12
|
||||
#define GPUCC_CXO_CLK 13
|
||||
#define GPUCC_GFX3D_CLK 14
|
||||
#define GPUCC_RBBMTIMER_CLK 15
|
||||
#define GPUCC_RBCPR_CLK 16
|
||||
#define RBBMTIMER_CLK_SRC 18
|
||||
#define RBCPR_CLK_SRC 19
|
||||
|
||||
/* Block Reset */
|
||||
#define GPU_CC_GPU_GX_BCR 0
|
||||
#define GPU_CC_GPU_CX_BCR 1
|
||||
#define GPU_CC_RBCPR_BCR 2
|
||||
#define GPU_CC_SPDM_BCR 3
|
||||
|
||||
/* GDSC */
|
||||
#define GPU_GX_GDSC 0
|
||||
#define GPU_CX_GDSC 1
|
||||
#define GPU_CX_GDSC 0
|
||||
#define GPU_GX_GDSC 1
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -14,181 +14,200 @@
|
|||
#ifndef _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H
|
||||
#define _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H
|
||||
|
||||
/* Clocks */
|
||||
#define MMPLL3_PLL 0
|
||||
#define MMPLL4_PLL 1
|
||||
#define MMPLL5_PLL 2
|
||||
#define MMPLL6_PLL 3
|
||||
#define MMPLL7_PLL 4
|
||||
#define MMPLL8_PLL 5
|
||||
#define AHB_CLK_SRC 6
|
||||
#define VIDEO_CORE_CLK_SRC 7
|
||||
#define PCLK0_CLK_SRC 8
|
||||
#define PCLK1_CLK_SRC 9
|
||||
#define MDP_CLK_SRC 10
|
||||
#define ROT_CLK_SRC 11
|
||||
#define VSYNC_CLK_SRC 12
|
||||
#define BYTE0_CLK_SRC 13
|
||||
#define BYTE1_CLK_SRC 14
|
||||
#define ESC0_CLK_SRC 15
|
||||
#define ESC1_CLK_SRC 16
|
||||
#define DP_LINK_CLK_SRC 17
|
||||
#define DP_CRYPTO_CLK_SRC 18
|
||||
#define DP_PIXEL_CLK_SRC 19
|
||||
#define DP_AUX_CLK_SRC 20
|
||||
#define DP_GTC_CLK_SRC 21
|
||||
#define CAMSS_GP0_CLK_SRC 22
|
||||
#define CAMSS_GP1_CLK_SRC 23
|
||||
#define MCLK0_CLK_SRC 24
|
||||
#define MCLK1_CLK_SRC 25
|
||||
#define MCLK2_CLK_SRC 26
|
||||
#define MCLK3_CLK_SRC 27
|
||||
#define CCI_CLK_SRC 28
|
||||
#define CSI0PHYTIMER_CLK_SRC 29
|
||||
#define CSI1PHYTIMER_CLK_SRC 30
|
||||
#define CSI2PHYTIMER_CLK_SRC 31
|
||||
#define JPEG0_CLK_SRC 32
|
||||
#define VFE0_CLK_SRC 33
|
||||
#define VFE1_CLK_SRC 34
|
||||
#define CPP_CLK_SRC 35
|
||||
#define CSIPHY_CLK_SRC 36
|
||||
#define CSI0_CLK_SRC 37
|
||||
#define CSI1_CLK_SRC 38
|
||||
#define CSI2_CLK_SRC 39
|
||||
#define CSI3_CLK_SRC 40
|
||||
#define MMSS_CXO_CLK 41
|
||||
#define MMSS_SLEEP_CLK 42
|
||||
#define MMSS_MNOC_AHB_CLK 43
|
||||
#define MMSS_MISC_AHB_CLK 44
|
||||
#define MMSS_MISC_CXO_CLK 45
|
||||
#define MMSS_BIMC_SMMU_AHB_CLK 46
|
||||
#define MMSS_BIMC_SMMU_AXI_CLK 47
|
||||
#define MMSS_SNOC_DVM_AXI_CLK 48
|
||||
#define MMSS_THROTTLE_CAMSS_CXO_CLK 49
|
||||
#define MMSS_THROTTLE_CAMSS_AHB_CLK 50
|
||||
#define MMSS_THROTTLE_CAMSS_AXI_CLK 51
|
||||
#define MMSS_THROTTLE_MDSS_CXO_CLK 52
|
||||
#define MMSS_THROTTLE_MDSS_AHB_CLK 53
|
||||
#define MMSS_THROTTLE_MDSS_AXI_CLK 54
|
||||
#define MMSS_THROTTLE_VIDEO_CXO_CLK 55
|
||||
#define MMSS_THROTTLE_VIDEO_AHB_CLK 56
|
||||
#define MMSS_THROTTLE_VIDEO_AXI_CLK 57
|
||||
#define MMSS_VIDEO_CORE_CLK 58
|
||||
#define MMSS_VIDEO_AXI_CLK 59
|
||||
#define MMSS_VIDEO_AHB_CLK 60
|
||||
#define MMSS_MDSS_AHB_CLK 61
|
||||
#define MMSS_MDSS_HDMI_DP_AHB_CLK 62
|
||||
#define MMSS_MDSS_PCLK0_CLK 63
|
||||
#define MMSS_MDSS_PCLK1_CLK 64
|
||||
#define MMSS_MDSS_VSYNC_CLK 65
|
||||
#define MMSS_MDSS_BYTE0_CLK 66
|
||||
#define MMSS_MDSS_BYTE0_INTF_CLK 67
|
||||
#define MMSS_MDSS_BYTE1_CLK 68
|
||||
#define MMSS_MDSS_BYTE1_INTF_CLK 69
|
||||
#define MMSS_MDSS_ESC0_CLK 70
|
||||
#define MMSS_MDSS_ESC1_CLK 71
|
||||
#define MMSS_MDSS_DP_LINK_CLK 72
|
||||
#define MMSS_MDSS_DP_LINK_INTF_CLK 73
|
||||
#define MMSS_MDSS_DP_CRYPTO_CLK 74
|
||||
#define MMSS_MDSS_DP_PIXEL_CLK 75
|
||||
#define MMSS_MDSS_DP_AUX_CLK 76
|
||||
#define MMSS_MDSS_DP_GTC_CLK 77
|
||||
#define MMSS_CAMSS_TOP_AHB_CLK 78
|
||||
#define MMSS_CAMSS_AHB_CLK 79
|
||||
#define MMSS_CAMSS_GP0_CLK 80
|
||||
#define MMSS_CAMSS_GP1_CLK 81
|
||||
#define MMSS_CAMSS_MCLK0_CLK 82
|
||||
#define MMSS_CAMSS_MCLK1_CLK 83
|
||||
#define MMSS_CAMSS_MCLK2_CLK 84
|
||||
#define MMSS_CAMSS_MCLK3_CLK 85
|
||||
#define MMSS_CAMSS_CCI_CLK 86
|
||||
#define MMSS_CAMSS_CCI_AHB_CLK 87
|
||||
#define MMSS_CAMSS_CSI0PHYTIMER_CLK 88
|
||||
#define MMSS_CAMSS_CSI1PHYTIMER_CLK 89
|
||||
#define MMSS_CAMSS_CSI2PHYTIMER_CLK 90
|
||||
#define MMSS_CAMSS_JPEG_AHB_CLK 91
|
||||
#define MMSS_CAMSS_VFE_VBIF_AHB_CLK 92
|
||||
#define MMSS_CAMSS_VFE0_STREAM_CLK 93
|
||||
#define MMSS_CAMSS_VFE0_AHB_CLK 94
|
||||
#define MMSS_CAMSS_VFE1_STREAM_CLK 95
|
||||
#define MMSS_CAMSS_VFE1_AHB_CLK 96
|
||||
#define MMSS_CAMSS_CPP_VBIF_AHB_CLK 97
|
||||
#define MMSS_CAMSS_CPP_AHB_CLK 98
|
||||
#define MMSS_CAMSS_CSIPHY0_CLK 99
|
||||
#define MMSS_CAMSS_CSIPHY1_CLK 100
|
||||
#define MMSS_CAMSS_CSIPHY2_CLK 101
|
||||
#define MMSS_CSIPHY_AHB2CRIF_CLK 102
|
||||
#define MMSS_CAMSS_CSI0_CLK 103
|
||||
#define MMSS_CAMSS_CPHY_CSID0_CLK 104
|
||||
#define MMSS_CAMSS_CSI0_AHB_CLK 105
|
||||
#define MMSS_CAMSS_CSI0RDI_CLK 106
|
||||
#define MMSS_CAMSS_CSI0PIX_CLK 107
|
||||
#define MMSS_CAMSS_CSI1_CLK 108
|
||||
#define MMSS_CAMSS_CPHY_CSID1_CLK 109
|
||||
#define MMSS_CAMSS_CSI1_AHB_CLK 110
|
||||
#define MMSS_CAMSS_CSI1RDI_CLK 111
|
||||
#define MMSS_CAMSS_CSI1PIX_CLK 112
|
||||
#define MMSS_CAMSS_CSI2_CLK 113
|
||||
#define MMSS_CAMSS_CPHY_CSID2_CLK 114
|
||||
#define MMSS_CAMSS_CSI2_AHB_CLK 115
|
||||
#define MMSS_CAMSS_CSI2RDI_CLK 116
|
||||
#define MMSS_CAMSS_CSI2PIX_CLK 117
|
||||
#define MMSS_CAMSS_CSI3_CLK 118
|
||||
#define MMSS_CAMSS_CPHY_CSID3_CLK 119
|
||||
#define MMSS_CAMSS_CSI3_AHB_CLK 120
|
||||
#define MMSS_CAMSS_CSI3RDI_CLK 121
|
||||
#define MMSS_CAMSS_CSI3PIX_CLK 122
|
||||
#define MMSS_CAMSS_ISPIF_AHB_CLK 123
|
||||
#define AHB_CLK_SRC 0
|
||||
#define BYTE0_CLK_SRC 1
|
||||
#define BYTE1_CLK_SRC 2
|
||||
#define CAMSS_GP0_CLK_SRC 3
|
||||
#define CAMSS_GP1_CLK_SRC 4
|
||||
#define CCI_CLK_SRC 5
|
||||
#define CPP_CLK_SRC 6
|
||||
#define CSI0_CLK_SRC 7
|
||||
#define CSI0PHYTIMER_CLK_SRC 8
|
||||
#define CSI1_CLK_SRC 9
|
||||
#define CSI1PHYTIMER_CLK_SRC 10
|
||||
#define CSI2_CLK_SRC 11
|
||||
#define CSI2PHYTIMER_CLK_SRC 12
|
||||
#define CSI3_CLK_SRC 13
|
||||
#define CSIPHY_CLK_SRC 14
|
||||
#define DP_AUX_CLK_SRC 15
|
||||
#define DP_CRYPTO_CLK_SRC 16
|
||||
#define DP_GTC_CLK_SRC 17
|
||||
#define DP_LINK_CLK_SRC 18
|
||||
#define DP_PIXEL_CLK_SRC 19
|
||||
#define ESC0_CLK_SRC 20
|
||||
#define ESC1_CLK_SRC 21
|
||||
#define JPEG0_CLK_SRC 22
|
||||
#define MCLK0_CLK_SRC 23
|
||||
#define MCLK1_CLK_SRC 24
|
||||
#define MCLK2_CLK_SRC 25
|
||||
#define MCLK3_CLK_SRC 26
|
||||
#define MDP_CLK_SRC 27
|
||||
#define MMPLL0_PLL 28
|
||||
#define MMPLL0_PLL_OUT_AUX 29
|
||||
#define MMPLL0_PLL_OUT_AUX2 30
|
||||
#define MMPLL0_PLL_OUT_EARLY 31
|
||||
#define MMPLL0_PLL_OUT_MAIN 32
|
||||
#define MMPLL0_PLL_OUT_TEST 33
|
||||
#define MMPLL10_PLL 34
|
||||
#define MMPLL10_PLL_OUT_AUX 35
|
||||
#define MMPLL10_PLL_OUT_AUX2 36
|
||||
#define MMPLL10_PLL_OUT_EARLY 37
|
||||
#define MMPLL10_PLL_OUT_MAIN 38
|
||||
#define MMPLL10_PLL_OUT_TEST 39
|
||||
#define MMPLL1_PLL 40
|
||||
#define MMPLL1_PLL_OUT_AUX 41
|
||||
#define MMPLL1_PLL_OUT_AUX2 42
|
||||
#define MMPLL1_PLL_OUT_EARLY 43
|
||||
#define MMPLL1_PLL_OUT_MAIN 44
|
||||
#define MMPLL1_PLL_OUT_TEST 45
|
||||
#define MMPLL3_PLL 46
|
||||
#define MMPLL3_PLL_OUT_AUX 47
|
||||
#define MMPLL3_PLL_OUT_AUX2 48
|
||||
#define MMPLL3_PLL_OUT_EARLY 49
|
||||
#define MMPLL3_PLL_OUT_MAIN 50
|
||||
#define MMPLL3_PLL_OUT_TEST 51
|
||||
#define MMPLL4_PLL 52
|
||||
#define MMPLL4_PLL_OUT_AUX 53
|
||||
#define MMPLL4_PLL_OUT_AUX2 54
|
||||
#define MMPLL4_PLL_OUT_EARLY 55
|
||||
#define MMPLL4_PLL_OUT_MAIN 56
|
||||
#define MMPLL4_PLL_OUT_TEST 57
|
||||
#define MMPLL5_PLL 58
|
||||
#define MMPLL5_PLL_OUT_AUX 59
|
||||
#define MMPLL5_PLL_OUT_AUX2 60
|
||||
#define MMPLL5_PLL_OUT_EARLY 61
|
||||
#define MMPLL5_PLL_OUT_MAIN 62
|
||||
#define MMPLL5_PLL_OUT_TEST 63
|
||||
#define MMPLL6_PLL 64
|
||||
#define MMPLL6_PLL_OUT_AUX 65
|
||||
#define MMPLL6_PLL_OUT_AUX2 66
|
||||
#define MMPLL6_PLL_OUT_EARLY 67
|
||||
#define MMPLL6_PLL_OUT_MAIN 68
|
||||
#define MMPLL6_PLL_OUT_TEST 69
|
||||
#define MMPLL7_PLL 70
|
||||
#define MMPLL7_PLL_OUT_AUX 71
|
||||
#define MMPLL7_PLL_OUT_AUX2 72
|
||||
#define MMPLL7_PLL_OUT_EARLY 73
|
||||
#define MMPLL7_PLL_OUT_MAIN 74
|
||||
#define MMPLL7_PLL_OUT_TEST 75
|
||||
#define MMPLL8_PLL 76
|
||||
#define MMPLL8_PLL_OUT_AUX 77
|
||||
#define MMPLL8_PLL_OUT_AUX2 78
|
||||
#define MMPLL8_PLL_OUT_EARLY 79
|
||||
#define MMPLL8_PLL_OUT_MAIN 80
|
||||
#define MMPLL8_PLL_OUT_TEST 81
|
||||
#define MMSS_BIMC_SMMU_AHB_CLK 82
|
||||
#define MMSS_BIMC_SMMU_AXI_CLK 83
|
||||
#define MMSS_CAMSS_AHB_CLK 84
|
||||
#define MMSS_CAMSS_CCI_AHB_CLK 85
|
||||
#define MMSS_CAMSS_CCI_CLK 86
|
||||
#define MMSS_CAMSS_CPHY_CSID0_CLK 87
|
||||
#define MMSS_CAMSS_CPHY_CSID1_CLK 88
|
||||
#define MMSS_CAMSS_CPHY_CSID2_CLK 89
|
||||
#define MMSS_CAMSS_CPHY_CSID3_CLK 90
|
||||
#define MMSS_CAMSS_CPP_AHB_CLK 91
|
||||
#define MMSS_CAMSS_CPP_AXI_CLK 92
|
||||
#define MMSS_CAMSS_CPP_CLK 93
|
||||
#define MMSS_CAMSS_CPP_VBIF_AHB_CLK 94
|
||||
#define MMSS_CAMSS_CSI0_AHB_CLK 95
|
||||
#define MMSS_CAMSS_CSI0_CLK 96
|
||||
#define MMSS_CAMSS_CSI0PHYTIMER_CLK 97
|
||||
#define MMSS_CAMSS_CSI0PIX_CLK 98
|
||||
#define MMSS_CAMSS_CSI0RDI_CLK 99
|
||||
#define MMSS_CAMSS_CSI1_AHB_CLK 100
|
||||
#define MMSS_CAMSS_CSI1_CLK 101
|
||||
#define MMSS_CAMSS_CSI1PHYTIMER_CLK 102
|
||||
#define MMSS_CAMSS_CSI1PIX_CLK 103
|
||||
#define MMSS_CAMSS_CSI1RDI_CLK 104
|
||||
#define MMSS_CAMSS_CSI2_AHB_CLK 105
|
||||
#define MMSS_CAMSS_CSI2_CLK 106
|
||||
#define MMSS_CAMSS_CSI2PHYTIMER_CLK 107
|
||||
#define MMSS_CAMSS_CSI2PIX_CLK 108
|
||||
#define MMSS_CAMSS_CSI2RDI_CLK 109
|
||||
#define MMSS_CAMSS_CSI3_AHB_CLK 110
|
||||
#define MMSS_CAMSS_CSI3_CLK 111
|
||||
#define MMSS_CAMSS_CSI3PIX_CLK 112
|
||||
#define MMSS_CAMSS_CSI3RDI_CLK 113
|
||||
#define MMSS_CAMSS_CSI_VFE0_CLK 114
|
||||
#define MMSS_CAMSS_CSI_VFE1_CLK 115
|
||||
#define MMSS_CAMSS_CSIPHY0_CLK 116
|
||||
#define MMSS_CAMSS_CSIPHY1_CLK 117
|
||||
#define MMSS_CAMSS_CSIPHY2_CLK 118
|
||||
#define MMSS_CAMSS_GP0_CLK 119
|
||||
#define MMSS_CAMSS_GP1_CLK 120
|
||||
#define MMSS_CAMSS_ISPIF_AHB_CLK 121
|
||||
#define MMSS_CAMSS_JPEG0_CLK 122
|
||||
#define MMSS_CAMSS_JPEG_AHB_CLK 123
|
||||
#define MMSS_CAMSS_JPEG_AXI_CLK 124
|
||||
#define MMSS_CAMSS_MCLK0_CLK 125
|
||||
#define MMSS_CAMSS_MCLK1_CLK 126
|
||||
#define MMSS_CAMSS_MCLK2_CLK 127
|
||||
#define MMSS_CAMSS_MCLK3_CLK 128
|
||||
#define MMSS_CAMSS_MICRO_AHB_CLK 129
|
||||
#define MMSS_CAMSS_TOP_AHB_CLK 130
|
||||
#define MMSS_CAMSS_VFE0_AHB_CLK 131
|
||||
#define MMSS_CAMSS_VFE0_CLK 132
|
||||
#define MMSS_CAMSS_VFE0_STREAM_CLK 133
|
||||
#define MMSS_CAMSS_VFE1_AHB_CLK 134
|
||||
#define MMSS_CAMSS_VFE1_CLK 135
|
||||
#define MMSS_CAMSS_VFE1_STREAM_CLK 136
|
||||
#define MMSS_CAMSS_VFE_VBIF_AHB_CLK 137
|
||||
#define MMSS_CAMSS_VFE_VBIF_AXI_CLK 138
|
||||
#define MMSS_CSIPHY_AHB2CRIF_CLK 139
|
||||
#define MMSS_CXO_CLK 140
|
||||
#define MMSS_MDSS_AHB_CLK 141
|
||||
#define MMSS_MDSS_AXI_CLK 142
|
||||
#define MMSS_MDSS_BYTE0_CLK 143
|
||||
#define MMSS_MDSS_BYTE0_INTF_CLK 144
|
||||
#define MMSS_MDSS_BYTE1_CLK 145
|
||||
#define MMSS_MDSS_BYTE1_INTF_CLK 146
|
||||
#define MMSS_MDSS_DP_AUX_CLK 147
|
||||
#define MMSS_MDSS_DP_CRYPTO_CLK 148
|
||||
#define MMSS_MDSS_DP_GTC_CLK 149
|
||||
#define MMSS_MDSS_DP_LINK_CLK 150
|
||||
#define MMSS_MDSS_DP_LINK_INTF_CLK 151
|
||||
#define MMSS_MDSS_DP_PIXEL_CLK 152
|
||||
#define MMSS_MDSS_ESC0_CLK 153
|
||||
#define MMSS_MDSS_ESC1_CLK 154
|
||||
#define MMSS_MDSS_HDMI_DP_AHB_CLK 155
|
||||
#define MMSS_MDSS_MDP_CLK 156
|
||||
#define MMSS_MDSS_PCLK0_CLK 157
|
||||
#define MMSS_MDSS_PCLK1_CLK 158
|
||||
#define MMSS_MDSS_ROT_CLK 159
|
||||
#define MMSS_MDSS_VSYNC_CLK 160
|
||||
#define MMSS_MISC_AHB_CLK 161
|
||||
#define MMSS_MISC_CXO_CLK 162
|
||||
#define MMSS_MNOC_AHB_CLK 163
|
||||
#define MMSS_SNOC_DVM_AXI_CLK 164
|
||||
#define MMSS_THROTTLE_CAMSS_AHB_CLK 165
|
||||
#define MMSS_THROTTLE_CAMSS_AXI_CLK 166
|
||||
#define MMSS_THROTTLE_CAMSS_CXO_CLK 167
|
||||
#define MMSS_THROTTLE_MDSS_AHB_CLK 168
|
||||
#define MMSS_THROTTLE_MDSS_AXI_CLK 169
|
||||
#define MMSS_THROTTLE_MDSS_CXO_CLK 170
|
||||
#define MMSS_THROTTLE_VIDEO_AHB_CLK 171
|
||||
#define MMSS_THROTTLE_VIDEO_AXI_CLK 172
|
||||
#define MMSS_THROTTLE_VIDEO_CXO_CLK 173
|
||||
#define MMSS_VIDEO_AHB_CLK 174
|
||||
#define MMSS_VIDEO_AXI_CLK 175
|
||||
#define MMSS_VIDEO_CORE_CLK 176
|
||||
#define MMSS_VIDEO_SUBCORE0_CLK 177
|
||||
#define PCLK0_CLK_SRC 178
|
||||
#define PCLK1_CLK_SRC 179
|
||||
#define ROT_CLK_SRC 180
|
||||
#define VFE0_CLK_SRC 181
|
||||
#define VFE1_CLK_SRC 182
|
||||
#define VIDEO_CORE_CLK_SRC 183
|
||||
#define VSYNC_CLK_SRC 184
|
||||
|
||||
/* Block Resets */
|
||||
#define MMSS_MNOCAHB_BCR 0
|
||||
#define MMSS_MISC_BCR 1
|
||||
#define MMSS_BTO_BCR 2
|
||||
#define MMSS_MNOCAXI_BCR 3
|
||||
#define MMSS_BIMC_SMMU_BCR 4
|
||||
#define MMSS_THROTTLE_CAMSS_BCR 5
|
||||
#define MMSS_THROTTLE_MDSS_BCR 6
|
||||
#define MMSS_THROTTLE_VIDEO_BCR 7
|
||||
#define MMSS_VIDEO_TOP_BCR 8
|
||||
#define MMSS_MDSS_BCR 9
|
||||
#define MMSS_CAMSS_TOP_BCR 10
|
||||
#define MMSS_CAMSS_AHB_BCR 11
|
||||
#define MMSS_CAMSS_MICRO_BCR 12
|
||||
#define MMSS_CAMSS_CCI_BCR 13
|
||||
#define MMSS_CAMSS_PHY0_BCR 14
|
||||
#define MMSS_CAMSS_PHY1_BCR 15
|
||||
#define MMSS_CAMSS_PHY2_BCR 16
|
||||
#define MMSS_CAMSS_JPEG_BCR 17
|
||||
#define MMSS_CAMSS_VFE_VBIF_BCR 18
|
||||
#define MMSS_CAMSS_VFE0_BCR 19
|
||||
#define MMSS_CAMSS_VFE1_BCR 20
|
||||
#define MMSS_CAMSS_CSI_VFE0_BCR 21
|
||||
#define MMSS_CAMSS_CSI_VFE1_BCR 22
|
||||
#define MMSS_CAMSS_CPP_TOP_BCR 23
|
||||
#define MMSS_CAMSS_CPP_BCR 24
|
||||
#define MMSS_CAMSS_CSIPHY_BCR 25
|
||||
#define MMSS_CAMSS_CSI0_BCR 26
|
||||
#define MMSS_CAMSS_CSI0RDI_BCR 27
|
||||
#define MMSS_CAMSS_CSI0PIX_BCR 28
|
||||
#define MMSS_CAMSS_CSI1_BCR 29
|
||||
#define MMSS_CAMSS_CSI1RDI_BCR 30
|
||||
#define MMSS_CAMSS_CSI1PIX_BCR 31
|
||||
#define MMSS_CAMSS_CSI2_BCR 32
|
||||
#define MMSS_CAMSS_CSI2RDI_BCR 33
|
||||
#define MMSS_CAMSS_CSI2PIX_BCR 34
|
||||
#define MMSS_CAMSS_CSI3_BCR 35
|
||||
#define MMSS_CAMSS_CSI3RDI_BCR 36
|
||||
#define MMSS_CAMSS_CSI3PIX_BCR 37
|
||||
#define MMSS_CAMSS_ISPIF_BCR 38
|
||||
#define BIMC_SMMU_GDSC 0
|
||||
#define CAMSS_CPP_GDSC 1
|
||||
#define CAMSS_TOP_GDSC 2
|
||||
#define CAMSS_VFE0_GDSC 3
|
||||
#define CAMSS_VFE1_GDSC 4
|
||||
#define MDSS_GDSC 5
|
||||
#define VIDEO_SUBCORE0_GDSC 6
|
||||
#define VIDEO_TOP_GDSC 7
|
||||
|
||||
/* GDSC */
|
||||
#define VIDEO_TOP_GDSC 0
|
||||
#define VIDEO_SUBCORE0_GDSC 1
|
||||
#define CAMSS_VFE0_GDSC 2
|
||||
#define BIMC_SMMU_GDSC 3
|
||||
#define CAMSS_TOP_GDSC 4
|
||||
#define MDSS_GDSC 5
|
||||
#define CAMSS_CPP_GDSC 6
|
||||
#define CAMSS_VFE1_GDSC 7
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue