diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
index 3517949726e7..4944d97e1e1e 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
@@ -1945,17 +1945,16 @@
 
 		clocks = <&clock_gcc clk_cxo_clk_src>,
 			 <&clock_gcc clk_gcc_mss_cfg_ahb_clk>,
-			 <&clock_gcc clk_pnoc_clk>,
 			 <&clock_gcc clk_gcc_bimc_mss_q6_axi_clk>,
 			 <&clock_gcc clk_gcc_boot_rom_ahb_clk>,
 			 <&clock_gcc clk_gpll0_out_msscc>,
 			 <&clock_gcc clk_gcc_mss_snoc_axi_clk>,
 			 <&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>,
 			 <&clock_gcc clk_qdss_clk>;
-		clock-names = "xo", "iface_clk", "pnoc_clk", "bus_clk",
+		clock-names = "xo", "iface_clk", "bus_clk",
 			      "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
 			      "mnoc_axi_clk", "qdss_clk";
-		qcom,proxy-clock-names = "xo", "pnoc_clk", "qdss_clk";
+		qcom,proxy-clock-names = "xo", "qdss_clk";
 		qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
 					  "gpll0_mss_clk", "snoc_axi_clk",
 					  "mnoc_axi_clk";
diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c
index 1718114c38a8..d225e710560b 100644
--- a/drivers/clk/msm/clock-gcc-cobalt.c
+++ b/drivers/clk/msm/clock-gcc-cobalt.c
@@ -59,10 +59,13 @@ static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
 
 DEFINE_CLK_RPM_SMD_BRANCH(cxo_clk_src, cxo_clk_src_ao, RPM_MISC_CLK_TYPE,
 			  CXO_CLK_SRC_ID, 19200000);
-DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_CLK_ID, NULL);
 DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_CLK_ID, NULL);
 DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_CLK_ID, NULL);
 DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_CLK_ID, NULL);
+DEFINE_CLK_RPM_SMD(cnoc_periph_clk, cnoc_periph_a_clk, RPM_BUS_CLK_TYPE,
+			CNOC_PERIPH_CLK_ID, NULL);
+static DEFINE_CLK_VOTER(cnoc_periph_keepalive_a_clk, &cnoc_periph_a_clk.c,
+			LONG_MAX);
 static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
 static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
 static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX);
@@ -91,17 +94,12 @@ DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(ln_bb_clk3_pin, ln_bb_clk3_pin_ao,
 				     LN_BB_CLK3_PIN_ID);
 static DEFINE_CLK_VOTER(mcd_ce1_clk, &ce1_clk.c, 85710000);
 DEFINE_CLK_DUMMY(measure_only_bimc_hmss_axi_clk, 0);
-DEFINE_CLK_RPM_SMD(mmssnoc_axi_clk, mmssnoc_axi_a_clk, RPM_BUS_CLK_TYPE,
-		   MMSSNOC_AXI_CLK_ID, NULL);
+DEFINE_CLK_RPM_SMD(mmssnoc_axi_clk, mmssnoc_axi_a_clk,
+			RPM_MMAXI_CLK_TYPE, MMSSNOC_AXI_CLK_ID, NULL);
 DEFINE_CLK_RPM_SMD_BRANCH(aggre1_noc_clk, aggre1_noc_a_clk,
 				RPM_AGGR_CLK_TYPE, AGGR1_NOC_ID, 1000);
 DEFINE_CLK_RPM_SMD_BRANCH(aggre2_noc_clk, aggre2_noc_a_clk,
 				RPM_AGGR_CLK_TYPE, AGGR2_NOC_ID, 1000);
-static DEFINE_CLK_VOTER(pnoc_keepalive_a_clk, &pnoc_a_clk.c, LONG_MAX);
-static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
-static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
-static DEFINE_CLK_VOTER(pnoc_pm_clk, &pnoc_clk.c, LONG_MAX);
-static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, 0);
 static DEFINE_CLK_VOTER(qcedev_ce1_clk, &ce1_clk.c, 85710000);
 static DEFINE_CLK_VOTER(qcrypto_ce1_clk, &ce1_clk.c, 85710000);
 DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE,
@@ -2468,14 +2466,15 @@ static struct mux_clk gcc_debug_mux = {
 
 static struct clk_lookup msm_clocks_rpm_cobalt[] = {
 	CLK_LIST(cxo_clk_src),
-	CLK_LIST(pnoc_clk),
-	CLK_LIST(pnoc_a_clk),
 	CLK_LIST(bimc_clk),
 	CLK_LIST(bimc_a_clk),
 	CLK_LIST(cnoc_clk),
 	CLK_LIST(cnoc_a_clk),
 	CLK_LIST(snoc_clk),
 	CLK_LIST(snoc_a_clk),
+	CLK_LIST(cnoc_periph_clk),
+	CLK_LIST(cnoc_periph_a_clk),
+	CLK_LIST(cnoc_periph_keepalive_a_clk),
 	CLK_LIST(bimc_msmbus_clk),
 	CLK_LIST(bimc_msmbus_a_clk),
 	CLK_LIST(ce1_clk),
@@ -2517,11 +2516,6 @@ static struct clk_lookup msm_clocks_rpm_cobalt[] = {
 	CLK_LIST(aggre1_noc_a_clk),
 	CLK_LIST(aggre2_noc_clk),
 	CLK_LIST(aggre2_noc_a_clk),
-	CLK_LIST(pnoc_keepalive_a_clk),
-	CLK_LIST(pnoc_msmbus_clk),
-	CLK_LIST(pnoc_msmbus_a_clk),
-	CLK_LIST(pnoc_pm_clk),
-	CLK_LIST(pnoc_sps_clk),
 	CLK_LIST(qcedev_ce1_clk),
 	CLK_LIST(qcrypto_ce1_clk),
 	CLK_LIST(qdss_clk),
@@ -2797,11 +2791,9 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	/*
-	 * Hold an active set vote for the PNOC AHB source. Sleep set vote is 0.
-	 */
-	clk_set_rate(&pnoc_keepalive_a_clk.c, 19200000);
-	clk_prepare_enable(&pnoc_keepalive_a_clk.c);
+	/* Hold an active set vote for the cnoc_periph resource */
+	clk_set_rate(&cnoc_periph_keepalive_a_clk.c, 19200000);
+	clk_prepare_enable(&cnoc_periph_keepalive_a_clk.c);
 
 	/* This clock is used for all MMSSCC register access */
 	clk_prepare_enable(&gcc_mmss_noc_cfg_ahb_clk.c);
diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h
index 607bcfb9b506..bb2c7b64809a 100644
--- a/include/dt-bindings/clock/msm-clocks-cobalt.h
+++ b/include/dt-bindings/clock/msm-clocks-cobalt.h
@@ -19,14 +19,15 @@
 #define clk_ce1_clk				0x42229c55
 #define clk_ce1_a_clk				0x44a833fe
 #define clk_cxo_clk_src				0x79e95308
-#define clk_pnoc_clk				0x4325d220
-#define clk_pnoc_a_clk				0x2808c12b
 #define clk_bimc_clk				0x4b80bf00
 #define clk_bimc_a_clk				0x4b25668a
 #define clk_cnoc_clk				0xd5ccb7f4
 #define clk_cnoc_a_clk				0xd8fe2ccc
 #define clk_snoc_clk				0x2c341aa0
 #define clk_snoc_a_clk				0x8fcef2af
+#define clk_cnoc_periph_clk			0xb11e9cf9
+#define clk_cnoc_periph_a_clk			0x1d7faa2e
+#define clk_cnoc_periph_keepalive_a_clk		0x7287aef2
 #define clk_ln_bb_clk1				0xb867b147
 #define clk_ln_bb_clk1_ao			0x7f63a93a
 #define clk_ln_bb_clk1_pin			0x6fc5653c
@@ -61,11 +62,6 @@
 #define clk_mcd_ce1_clk				0xbb615d26
 #define clk_mmssnoc_axi_clk			0xdb4b31e6
 #define clk_mmssnoc_axi_a_clk			0xd4970614
-#define clk_pnoc_keepalive_a_clk		0xf8f91f0b
-#define clk_pnoc_msmbus_clk			0x38b95c77
-#define clk_pnoc_msmbus_a_clk			0x8c9b4e93
-#define clk_pnoc_pm_clk				0xd6f7dfb9
-#define clk_pnoc_sps_clk			0xd482ecc7
 #define clk_qcedev_ce1_clk			0x293f97b0
 #define clk_qcrypto_ce1_clk			0xa6ac14df
 #define clk_qdss_clk				0x1492202a
diff --git a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
index a39433fa150f..52a28b5cbaf5 100644
--- a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
+++ b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
@@ -30,9 +30,9 @@
 
 #define CXO_CLK_SRC_ID						0x0
 #define QDSS_CLK_ID						0x1
-#define PNOC_CLK_ID						0x0
 #define SNOC_CLK_ID						0x1
 #define CNOC_CLK_ID						0x2
+#define CNOC_PERIPH_CLK_ID					0x0
 #define BIMC_CLK_ID						0x0
 #define IPA_CLK_ID						0x0
 #define CE1_CLK_ID						0x0